2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
8 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
10 #define CCM_CCOSR 0x020c4060
11 #define CCM_CCGR0 0x020C4068
12 #define CCM_CCGR1 0x020C406c
13 #define CCM_CCGR2 0x020C4070
14 #define CCM_CCGR3 0x020C4074
15 #define CCM_CCGR4 0x020C4078
16 #define CCM_CCGR5 0x020C407c
17 #define CCM_CCGR6 0x020C4080
19 #define PMU_MISC2 0x020C8170
27 u32 cacrr; /* 0x0010*/
31 u32 cscmr2; /* 0x0020 */
35 u32 cdcdr; /* 0x0030 */
39 u32 cscdr4; /* 0x0040 */
43 u32 ctor; /* 0x0050 */
47 u32 ccosr; /* 0x0060 */
51 u32 CCGR2; /* 0x0070 */
55 u32 CCGR6; /* 0x0080 */
61 /* Define the bits in register CCR */
62 #define MXC_CCM_CCR_RBC_EN (1 << 27)
63 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << CCR_REG_BYPASS_CNT_OFFSET)
64 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
65 #define MXC_CCM_CCR_WB_COUNT_MASK (0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET)
66 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
67 #define MXC_CCM_CCR_COSC_EN (1 << 12)
68 #ifdef CONFIG_SOC_MX6SX
69 #define MXC_CCM_CCR_OSCNT_MASK 0x7F
71 #define MXC_CCM_CCR_OSCNT_MASK 0xFF
73 #define MXC_CCM_CCR_OSCNT_OFFSET 0
75 /* Define the bits in register CCDR */
76 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
77 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
79 /* Define the bits in register CSR */
80 #define MXC_CCM_CSR_COSC_READY (1 << 5)
81 #define MXC_CCM_CSR_REF_EN_B (1 << 0)
83 /* Define the bits in register CCSR */
84 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15)
85 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14)
86 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13)
87 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12)
88 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11)
89 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10)
90 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9)
91 #define MXC_CCM_CCSR_STEP_SEL (1 << 8)
92 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
93 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
94 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
96 /* Define the bits in register CACRR */
97 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
98 #define MXC_CCM_CACRR_ARM_PODF_MASK (0x7 << MXC_CCM_CACRR_ARM_PODF_OFFSET)
100 /* Define the bits in register CBCDR */
101 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET)
102 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
103 #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
104 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
105 #ifndef CONFIG_SOC_MX6SX
106 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET)
107 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
109 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << MXC_CCM_CBCDR_AXI_PODF_OFFSET)
110 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
111 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << MXC_CCM_CBCDR_AHB_PODF_OFFSET)
112 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
113 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << MXC_CCM_CBCDR_IPG_PODF_OFFSET)
114 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
115 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
116 #define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
117 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET)
118 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3
119 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET)
120 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
122 /* Define the bits in register CBCMR */
123 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET)
124 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
125 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET)
126 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
127 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET)
128 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
129 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET)
130 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
131 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
132 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET)
133 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
134 #ifndef CONFIG_SOC_MX6SX
135 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET)
136 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
137 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET)
138 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
140 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET)
141 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
142 #ifndef CONFIG_SOC_MX6SX
143 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
145 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
146 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET)
147 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
148 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET)
149 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
150 #ifndef CONFIG_SOC_MX6SX
151 #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
152 #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0)
155 /* Define the bits in register CSCMR1 */
156 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET)
157 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
158 #ifdef CONFIG_SOC_MX6SX
159 #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET)
160 #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26
162 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET)
163 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
165 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET)
166 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
167 /* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
168 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET)
169 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
170 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
171 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
172 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
173 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
174 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET)
175 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14
176 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET)
177 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
178 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET)
179 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
180 #ifdef CONFIG_SOC_MX6SX
181 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)
182 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
184 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
185 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET)
186 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
188 #define MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET 0
189 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK (0x3F << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET)
191 /* Define the bits in register CSCMR2 */
192 #ifdef CONFIG_SOC_MX6SX
193 #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET)
194 #define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21
196 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET)
197 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
198 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
199 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
200 #ifdef CONFIG_SOC_MX6SX
201 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
202 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8
203 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET)
204 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2
206 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
207 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2
210 /* Define the bits in register CSCDR1 */
211 #ifndef CONFIG_SOC_MX6SX
212 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET)
213 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
215 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET)
216 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
217 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET)
218 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19
219 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET)
220 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
221 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET)
222 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
223 #ifndef CONFIG_SOC_MX6SX
224 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
225 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET)
226 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
227 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET)
229 #ifdef CONFIG_SOC_MX6SL
230 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x1F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
231 #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET)
233 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
234 #ifdef CONFIG_SOC_MX6SX
235 #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET)
238 #define MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET 6
239 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
241 /* Define the bits in register CS1CDR */
242 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET)
243 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
244 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET)
245 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22
246 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET)
247 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
248 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET)
249 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9
250 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET)
251 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6
252 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET)
253 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
255 /* Define the bits in register CS2CDR */
256 #ifdef CONFIG_SOC_MX6SX
257 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
258 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21
259 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
260 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET)
261 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18
262 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET)
263 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET)
264 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15
265 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET)
267 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
268 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
269 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
270 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
271 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
272 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
273 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET)
274 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
275 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET)
277 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
278 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
279 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
280 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9
281 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET)
282 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6
283 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET)
284 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
286 /* Define the bits in register CDCDR */
287 #ifndef CONFIG_SOC_MX6SX
288 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET)
289 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
290 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_MASK (1 << MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET)
291 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET 28
293 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET)
294 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
295 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET)
296 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22
297 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET)
298 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20
299 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET)
300 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12
301 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET)
302 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9
303 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET)
304 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
306 /* Define the bits in register CHSCCDR */
307 #ifdef CONFIG_SOC_MX6SX
308 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET)
309 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15
310 #define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET)
311 #define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12
312 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET)
313 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9
314 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET)
315 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6
316 #define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_M4_PODF_OFFSET)
317 #define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3
318 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET)
319 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0
321 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET)
322 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
323 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET)
324 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12
325 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET)
326 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9
327 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET)
328 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6
329 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
330 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
331 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
332 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
335 #define CHSCCDR_CLK_SEL_LDB_DI0 3
336 #define CHSCCDR_PODF_DIVIDE_BY_3 2
337 #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5
339 /* Define the bits in register CSCDR2 */
340 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET)
341 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
342 /* All IPU2_DI1 are LCDIF1 on MX6SX */
343 #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET)
344 #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
345 #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET)
346 #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET 12
347 #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET)
348 #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET 9
349 /* All IPU2_DI0 are LCDIF2 on MX6SX */
350 #define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET)
351 #define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
352 #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET)
353 #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET 3
354 #define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET)
355 #define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET 0
357 /* Define the bits in register CSCDR3 */
358 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET)
359 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16
360 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET)
361 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14
362 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET)
363 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11
364 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET)
365 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
367 /* Define the bits in register CDHIPR */
368 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
369 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
370 #ifndef CONFIG_SOC_MX6SX
371 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
373 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
374 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
375 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
376 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY (1 << 0)
378 /* Define the bits in register CLPCR */
379 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
380 #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
381 #ifndef CONFIG_SOC_MX6SX
382 #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
383 #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
384 #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
386 #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
387 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
388 #ifndef CONFIG_SOC_MX6SX
389 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
390 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
392 #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16)
393 #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
394 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET)
395 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
396 #define MXC_CCM_CLPCR_VSTBY (1 << 8)
397 #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
398 #define MXC_CCM_CLPCR_SBYOS (1 << 6)
399 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
400 #ifndef CONFIG_SOC_MX6SX
401 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET)
402 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
403 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
405 #define MXC_CCM_CLPCR_LPM_MASK (0x3 << MXC_CCM_CLPCR_LPM_OFFSET)
406 #define MXC_CCM_CLPCR_LPM_OFFSET 0
408 /* Define the bits in register CISR */
409 #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
410 #ifndef CONFIG_SOC_MX6SX
411 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
413 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
414 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
415 #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
416 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
417 #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
418 #define MXC_CCM_CISR_COSC_READY (1 << 6)
419 #define MXC_CCM_CISR_LRF_PLL (1 << 0)
421 /* Define the bits in register CIMR */
422 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
423 #ifndef CONFIG_SOC_MX6SX
424 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
426 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
427 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
428 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
429 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19)
430 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
431 #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
432 #define MXC_CCM_CIMR_MASK_LRF_PLL (1 << 0)
434 /* Define the bits in register CCOSR */
435 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
436 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKO2_DIV_OFFSET)
437 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
438 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
439 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << MXC_CCM_CCOSR_CKO2_SEL_OFFSET)
440 #define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8)
441 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
442 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKOL_DIV_OFFSET)
443 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
444 #define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF << MXC_CCM_CCOSR_CKOL_SEL_OFFSET)
445 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
447 /* Define the bits in registers CGPR */
448 #define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16)
449 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
450 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
451 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER (1 << 0)
453 /* Define the bits in registers CCGRx */
454 #define MXC_CCM_CCGR_CG_MASK 3
456 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
457 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
458 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
459 #define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
460 #define MXC_CCM_CCGR0_APBHDMA_OFFSET 4
461 #define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET)
462 #define MXC_CCM_CCGR0_ASRC_OFFSET 6
463 #define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET)
464 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8
465 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
466 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10
467 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
468 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12
469 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
470 #define MXC_CCM_CCGR0_CAN1_OFFSET 14
471 #define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET)
472 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16
473 #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
474 #define MXC_CCM_CCGR0_CAN2_OFFSET 18
475 #define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET)
476 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20
477 #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
478 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22
479 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
480 #define MXC_CCM_CCGR0_DCIC1_OFFSET 24
481 #define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
482 #define MXC_CCM_CCGR0_DCIC2_OFFSET 26
483 #define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
484 #ifdef CONFIG_SOC_MX6SX
485 #define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET 30
486 #define MXC_CCM_CCGR0_AIPS_TZ3_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET)
488 #define MXC_CCM_CCGR0_DTCP_OFFSET 28
489 #define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET)
492 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
493 #define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
494 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2
495 #define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET)
496 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4
497 #define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET)
498 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6
499 #define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
500 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
501 #define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
502 #ifndef CONFIG_SOC_MX6SX
503 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10
504 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
506 #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
507 #define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
508 #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
509 #define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
510 #define MXC_CCM_CCGR1_ESAIS_OFFSET 16
511 #define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
512 #ifdef CONFIG_SOC_MX6SX
513 #define MXC_CCM_CCGR1_WAKEUP_OFFSET 18
514 #define MXC_CCM_CCGR1_WAKEUP_MASK (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET)
516 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20
517 #define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
518 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22
519 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
520 #ifndef CONFIG_SOC_MX6SX
521 #define MXC_CCM_CCGR1_GPU2D_OFFSET 24
522 #define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
524 #define MXC_CCM_CCGR1_GPU3D_OFFSET 26
525 #define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
526 #ifdef CONFIG_SOC_MX6SX
527 #define MXC_CCM_CCGR1_OCRAM_S_OFFSET 28
528 #define MXC_CCM_CCGR1_OCRAM_S_MASK (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET)
529 #define MXC_CCM_CCGR1_CANFD_OFFSET 30
530 #define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
533 #ifndef CONFIG_SOC_MX6SX
534 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
535 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
537 #define MXC_CCM_CCGR2_CSI_OFFSET 2
538 #define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET)
540 #ifndef CONFIG_SOC_MX6SX
541 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
542 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
544 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6
545 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
546 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8
547 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
548 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10
549 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
550 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12
551 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
552 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14
553 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
554 #define MXC_CCM_CCGR2_IPMUX1_OFFSET 16
555 #define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET)
556 #define MXC_CCM_CCGR2_IPMUX2_OFFSET 18
557 #define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET)
558 #define MXC_CCM_CCGR2_IPMUX3_OFFSET 20
559 #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
560 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
561 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
562 #ifdef CONFIG_SOC_MX6SX
563 #define MXC_CCM_CCGR2_LCD_OFFSET 28
564 #define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET)
565 #define MXC_CCM_CCGR2_PXP_OFFSET 30
566 #define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET)
568 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
569 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
570 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
571 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
574 #ifdef CONFIG_SOC_MX6SX
575 #define MXC_CCM_CCGR3_M4_OFFSET 2
576 #define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET)
577 #define MXC_CCM_CCGR3_ENET_OFFSET 4
578 #define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET)
579 #define MXC_CCM_CCGR3_QSPI_OFFSET 14
580 #define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET)
582 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
583 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
584 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
585 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
586 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
587 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
589 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
590 #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
591 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
592 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
593 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10
594 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
595 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
596 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
597 #ifdef CONFIG_SOC_MX6SX
598 #define MXC_CCM_CCGR3_QSPI1_OFFSET 14
599 #define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
601 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
602 #define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
603 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
604 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
606 #define MXC_CCM_CCGR3_MLB_OFFSET 18
607 #define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET)
608 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
609 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
610 #ifndef CONFIG_SOC_MX6SX
611 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22
612 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
614 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24
615 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
616 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
617 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
618 #define MXC_CCM_CCGR3_OCRAM_OFFSET 28
619 #define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
620 #ifndef CONFIG_SOC_MX6SX
621 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
622 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
625 #define MXC_CCM_CCGR4_PCIE_OFFSET 0
626 #define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
627 #ifdef CONFIG_SOC_MX6SX
628 #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10
629 #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
631 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
632 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
634 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
635 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
636 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
637 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
638 #define MXC_CCM_CCGR4_PWM1_OFFSET 16
639 #define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET)
640 #define MXC_CCM_CCGR4_PWM2_OFFSET 18
641 #define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET)
642 #define MXC_CCM_CCGR4_PWM3_OFFSET 20
643 #define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET)
644 #define MXC_CCM_CCGR4_PWM4_OFFSET 22
645 #define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET)
646 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24
647 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
648 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26
649 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
650 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28
651 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
652 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30
653 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
655 #define MXC_CCM_CCGR5_ROM_OFFSET 0
656 #define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET)
657 #ifndef CONFIG_SOC_MX6SX
658 #define MXC_CCM_CCGR5_SATA_OFFSET 4
659 #define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET)
661 #define MXC_CCM_CCGR5_SDMA_OFFSET 6
662 #define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET)
663 #define MXC_CCM_CCGR5_SPBA_OFFSET 12
664 #define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET)
665 #define MXC_CCM_CCGR5_SPDIF_OFFSET 14
666 #define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
667 #define MXC_CCM_CCGR5_SSI1_OFFSET 18
668 #define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET)
669 #define MXC_CCM_CCGR5_SSI2_OFFSET 20
670 #define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET)
671 #define MXC_CCM_CCGR5_SSI3_OFFSET 22
672 #define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET)
673 #define MXC_CCM_CCGR5_UART_OFFSET 24
674 #define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET)
675 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
676 #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
677 #ifdef CONFIG_SOC_MX6SX
678 #define MXC_CCM_CCGR5_SAI1_OFFSET 20
679 #define MXC_CCM_CCGR5_SAI1_MASK (3 << MXC_CCM_CCGR5_SAI1_OFFSET)
680 #define MXC_CCM_CCGR5_SAI2_OFFSET 30
681 #define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET)
684 #define MXC_CCM_CCGR6_USBOH3_OFFSET 0
685 #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
686 #define MXC_CCM_CCGR6_USDHC1_OFFSET 2
687 #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
688 #define MXC_CCM_CCGR6_USDHC2_OFFSET 4
689 #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
690 #define MXC_CCM_CCGR6_USDHC3_OFFSET 6
691 #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
692 #define MXC_CCM_CCGR6_USDHC4_OFFSET 8
693 #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
694 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
695 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
696 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
697 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
699 #define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0
700 #define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f << ANATOP_PFD_480_PFD0_FRAC_SHIFT)
701 #define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6
702 #define ANATOP_PFD_480_PFD0_STABLE_MASK (1 << ANATOP_PFD_480_PFD0_STABLE_SHIFT)
703 #define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7
704 #define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1 << ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
705 #define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8
706 #define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f << ANATOP_PFD_480_PFD1_FRAC_SHIFT)
707 #define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14
708 #define ANATOP_PFD_480_PFD1_STABLE_MASK (1 << ANATOP_PFD_480_PFD1_STABLE_SHIFT)
709 #define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15
710 #define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f << ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
711 #define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16
712 #define ANATOP_PFD_480_PFD2_FRAC_MASK (1 << ANATOP_PFD_480_PFD2_FRAC_SHIFT)
713 #define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22
714 #define ANATOP_PFD_480_PFD2_STABLE_MASK (1 << ANATOP_PFD_480_PFD2_STABLE_SHIFT)
715 #define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23
716 #define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f << ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
717 #define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24
718 #define ANATOP_PFD_480_PFD3_FRAC_MASK (1 << ANATOP_PFD_480_PFD3_FRAC_SHIFT)
719 #define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30
720 #define ANATOP_PFD_480_PFD3_STABLE_MASK (1 << ANATOP_PFD_480_PFD3_STABLE_SHIFT)
721 #define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31
723 #define BM_ANADIG_PLL_ARM_LOCK (1 << 31)
724 #define BM_ANADIG_PLL_ARM_PLL_SEL (1 << 19)
725 #define BM_ANADIG_PLL_ARM_LVDS_24MHZ_SEL (1 << 18)
726 #define BM_ANADIG_PLL_ARM_LVDS_SEL (1 << 17)
727 #define BM_ANADIG_PLL_ARM_BYPASS (1 << 16)
728 #define BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC 14
729 #define BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
730 #define BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(v) \
731 (((v) << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC) & \
732 BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
733 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__OSC_24M 0x0
734 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_1 0x1
735 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_2 0x2
736 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__XOR 0x3
737 #define BM_ANADIG_PLL_ARM_ENABLE (1 << 13)
738 #define BM_ANADIG_PLL_ARM_POWERDOWN (1 << 12)
739 #define BM_ANADIG_PLL_ARM_HOLD_RING_OFF (1 << 11)
740 #define BM_ANADIG_PLL_ARM_DOUBLE_CP (1 << 10)
741 #define BM_ANADIG_PLL_ARM_HALF_CP (1 << 9)
742 #define BM_ANADIG_PLL_ARM_DOUBLE_LF (1 << 8)
743 #define BM_ANADIG_PLL_ARM_HALF_LF (1 << 7)
744 #define BP_ANADIG_PLL_ARM_DIV_SELECT 0
745 #define BM_ANADIG_PLL_ARM_DIV_SELECT (0x7F << BP_ANADIG_PLL_ARM_DIV_SELECT)
746 #define BF_ANADIG_PLL_ARM_DIV_SELECT(v) \
747 (((v) << BP_ANADIG_PLL_ARM_DIV_SELECT) & \
748 BM_ANADIG_PLL_ARM_DIV_SELECT)
750 #define BM_ANADIG_PLL_528_CTRL_LOCK (1 << 31)
751 #define BM_ANADIG_PLL_528_PFD_OFFSET_EN (1 << 18)
752 #define BM_ANADIG_PLL_528_DITHER_ENABLE (1 << 17)
753 #define BM_ANADIG_PLL_528_CTRL_BYPASS (1 << 16)
754 #define BP_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC 14
755 #define BM_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC)
756 #define BF_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC(v) \
757 (((v) << BP_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC) & \
758 BM_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC)
759 #define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
760 #define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
761 #define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
762 #define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__XOR 0x3
763 #define BM_ANADIG_PLL_528_CTRL_ENABLE (1 << 13)
764 #define BM_ANADIG_PLL_528_CTRL_POWER (1 << 12)
765 #define BM_ANADIG_PLL_528_CTRL_HOLD_RING_OFF (1 << 11)
766 #define BM_ANADIG_PLL_528_CTRL_DOUBLE_CP (1 << 10)
767 #define BM_ANADIG_PLL_528_CTRL_HALF_CP (1 << 9)
768 #define BM_ANADIG_PLL_528_CTRL_DOUBLE_LF (1 << 8)
769 #define BM_ANADIG_PLL_528_CTRL_HALF_LF (1 << 7)
770 #define BM_ANADIG_PLL_528_CTRL_EN_USB_CLKS (1 << 6)
771 #define BP_ANADIG_PLL_528_CTRL_CONTROL0 2
772 #define BM_ANADIG_PLL_528_CTRL_CONTROL0 (0x7 << BP_ANADIG_PLL_528_CTRL_CONTROL0)
773 #define BF_ANADIG_PLL_528_CTRL_CONTROL0(v) \
774 (((v) << BP_ANADIG_PLL_528_CTRL_CONTROL0) & \
775 BM_ANADIG_PLL_528_CTRL_CONTROL0)
776 #define BP_ANADIG_PLL_528_CTRL_DIV_SELECT 0
777 #define BM_ANADIG_PLL_528_CTRL_DIV_SELECT (0x3 << BP_ANADIG_PLL_528_CTRL_DIV_SELECT)
778 #define BF_ANADIG_PLL_528_CTRL_DIV_SELECT(v) \
779 (((v) << BP_ANADIG_PLL_528_CTRL_DIV_SELECT) & \
780 BM_ANADIG_PLL_528_CTRL_DIV_SELECT)
782 #define BM_ANADIG_PLL_AUDIO_LOCK (1 << 31)
783 #define BM_ANADIG_PLL_AUDIO_SSC_EN (1 << 21)
784 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
785 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
786 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
787 (((v) << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
788 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18)
789 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE (1 << 17)
790 #define BM_ANADIG_PLL_AUDIO_BYPASS (1 << 16)
791 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
792 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
793 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
794 (((v) << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
795 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
796 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
797 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
798 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
799 #define BM_ANADIG_PLL_AUDIO_ENABLE (1 << 13)
800 #define BM_ANADIG_PLL_AUDIO_POWERDOWN (1 << 12)
801 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF (1 << 11)
802 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP (1 << 10)
803 #define BM_ANADIG_PLL_AUDIO_HALF_CP (1 << 9)
804 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF (1 << 8)
805 #define BM_ANADIG_PLL_AUDIO_HALF_LF (1 << 7)
806 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
807 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT)
808 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
809 (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & \
810 BM_ANADIG_PLL_AUDIO_DIV_SELECT)
812 #define BP_ANADIG_PLL_AUDIO_NUM_A 0
813 #define BM_ANADIG_PLL_AUDIO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_NUM_A)
814 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
815 (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & \
816 BM_ANADIG_PLL_AUDIO_NUM_A)
818 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0
819 #define BM_ANADIG_PLL_AUDIO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_DENOM_B)
820 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
821 (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & \
822 BM_ANADIG_PLL_AUDIO_DENOM_B)
824 #define BM_ANADIG_PLL_VIDEO_LOCK (1 << 31)
825 #define BM_ANADIG_PLL_VIDEO_SSC_EN (1 << 21)
826 #define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19
827 #define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
828 #define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \
829 (((v) << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) & \
830 BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
831 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18)
832 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE (1 << 17)
833 #define BM_ANADIG_PLL_VIDEO_BYPASS (1 << 16)
834 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
835 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
836 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
837 (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & \
838 BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
839 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
840 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
841 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
842 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
843 #define BM_ANADIG_PLL_VIDEO_ENABLE (1 << 13)
844 #define BM_ANADIG_PLL_VIDEO_POWERDOWN (1 << 12)
845 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF (1 << 11)
846 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP (1 << 10)
847 #define BM_ANADIG_PLL_VIDEO_HALF_CP (1 << 9)
848 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF (1 << 8)
849 #define BM_ANADIG_PLL_VIDEO_HALF_LF (1 << 7)
850 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
851 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT)
852 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
853 (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & \
854 BM_ANADIG_PLL_VIDEO_DIV_SELECT)
856 #define BP_ANADIG_PLL_VIDEO_NUM_A 0
857 #define BM_ANADIG_PLL_VIDEO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A)
858 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
859 (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & \
860 BM_ANADIG_PLL_VIDEO_NUM_A)
862 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0
863 #define BM_ANADIG_PLL_VIDEO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B)
864 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
865 (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & \
866 BM_ANADIG_PLL_VIDEO_DENOM_B)
868 #define BM_ANADIG_PLL_MLB_LOCK (1 << 31)
869 #define BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG 26
870 #define BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
871 #define BF_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG(v) \
872 (((v) << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) & \
873 BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
874 #define BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG 23
875 #define BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
876 #define BF_ANADIG_PLL_MLB_RX_CLK_DLY_CFG(v) \
877 (((v) << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) & \
878 BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
879 #define BP_ANADIG_PLL_MLB_VDDD_DLY_CFG 20
880 #define BM_ANADIG_PLL_MLB_VDDD_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG)
881 #define BF_ANADIG_PLL_MLB_VDDD_DLY_CFG(v) \
882 (((v) << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG) & \
883 BM_ANADIG_PLL_MLB_VDDD_DLY_CFG)
884 #define BP_ANADIG_PLL_MLB_VDDA_DLY_CFG 17
885 #define BM_ANADIG_PLL_MLB_VDDA_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG)
886 #define BF_ANADIG_PLL_MLB_VDDA_DLY_CFG(v) \
887 (((v) << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG) & \
888 BM_ANADIG_PLL_MLB_VDDA_DLY_CFG)
889 #define BM_ANADIG_PLL_MLB_BYPASS (1 << 16)
890 #define BP_ANADIG_PLL_MLB_PHASE_SEL 12
891 #define BM_ANADIG_PLL_MLB_PHASE_SEL (0x7 << BP_ANADIG_PLL_MLB_PHASE_SEL)
892 #define BF_ANADIG_PLL_MLB_PHASE_SEL(v) \
893 (((v) << BP_ANADIG_PLL_MLB_PHASE_SEL) & \
894 BM_ANADIG_PLL_MLB_PHASE_SEL)
895 #define BM_ANADIG_PLL_MLB_HOLD_RING_OFF (1 << 11)
897 #define BM_ANADIG_PLL_ENET_LOCK (1 << 31)
898 #define BM_ANADIG_PLL_ENET_ENABLE_SATA (1 << 20)
899 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE (1 << 19)
900 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN (1 << 18)
901 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE (1 << 17)
902 #define BM_ANADIG_PLL_ENET_BYPASS (1 << 16)
903 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
904 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
905 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
906 (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & \
907 BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
908 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
909 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
910 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
911 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
912 #define BM_ANADIG_PLL_ENET_ENABLE (1 << 13)
913 #define BM_ANADIG_PLL_ENET_POWERDOWN (1 << 12)
914 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF (1 << 11)
915 #define BM_ANADIG_PLL_ENET_DOUBLE_CP (1 << 10)
916 #define BM_ANADIG_PLL_ENET_HALF_CP (1 << 9)
917 #define BM_ANADIG_PLL_ENET_DOUBLE_LF (1 << 8)
918 #define BM_ANADIG_PLL_ENET_HALF_LF (1 << 7)
919 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0
920 #define BM_ANADIG_PLL_ENET_DIV_SELECT (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT)
921 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
922 (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & \
923 BM_ANADIG_PLL_ENET_DIV_SELECT)
925 #define BM_ANADIG_PFD_480_PFD3_CLKGATE (1 << 31)
926 #define BM_ANADIG_PFD_480_PFD3_STABLE (1 << 30)
927 #define BP_ANADIG_PFD_480_PFD3_FRAC 24
928 #define BM_ANADIG_PFD_480_PFD3_FRAC (0x3F << BP_ANADIG_PFD_480_PFD3_FRAC)
929 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
930 (((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & \
931 BM_ANADIG_PFD_480_PFD3_FRAC)
933 #define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY 26
934 #define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY (0x7 << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY)
935 #define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v) \
936 (((v) << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY) & \
937 BM_ANADIG_ANA_MISC0_CLKGATE_DELAY)
938 #define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL (1 << 25)
939 #define BP_ANADIG_ANA_MISC0_ANAMUX 21
940 #define BM_ANADIG_ANA_MISC0_ANAMUX (0xf << BP_ANADIG_ANA_MISC0_ANAMUX)
941 #define BF_ANADIG_ANA_MISC0_ANAMUX(v) \
942 (((v) << BP_ANADIG_ANA_MISC0_ANAMUX) & \
943 BM_ANADIG_ANA_MISC0_ANAMUX)
944 #define BM_ANADIG_ANA_MISC0_ANAMUX_EN (1 << 20)
945 #define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 18
946 #define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH (0x3 << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
947 #define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v) \
948 (((v) << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) & \
949 BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
950 #define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN (1 << 17)
951 #define BM_ANADIG_ANA_MISC0_OSC_XTALOK (1 << 16)
952 #define BP_ANADIG_ANA_MISC0_OSC_I 14
953 #define BM_ANADIG_ANA_MISC0_OSC_I (0x3 << BP_ANADIG_ANA_MISC0_OSC_I)
954 #define BF_ANADIG_ANA_MISC0_OSC_I(v) \
955 (((v) << BP_ANADIG_ANA_MISC0_OSC_I) & \
956 BM_ANADIG_ANA_MISC0_OSC_I)
957 #define BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN (1 << 13)
958 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG (1 << 12)
959 #define BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 8
960 #define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST (0x3 << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
961 #define BF_ANADIG_ANA_MISC0_REFTOP_BIAS_TST(v) \
962 (((v) << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) & \
963 BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
964 #define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP (1 << 7)
965 #define BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ 4
966 #define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ (0x7 << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
967 #define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v) \
968 (((v) << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ) & \
969 BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
970 #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF (1 << 3)
971 #define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER (1 << 2)
972 #define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP (1 << 1)
973 #define BM_ANADIG_ANA_MISC0_REFTOP_PWD (1 << 0)
975 #define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO (1 << 31)
976 #define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO (1 << 30)
977 #define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO (1 << 29)
978 #define BM_ANADIG_ANA_MISC1_LVDSCLK2_IBEN (1 << 13)
979 #define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
980 #define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN (1 << 11)
981 #define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
982 #define BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 5
983 #define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL (0x1f << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
984 #define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v) \
985 (((v) << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) & \
986 BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
987 #define BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0
988 #define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL (0x1F << BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
989 #define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v) \
990 (((v) << BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL) & \
991 BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
993 #define BP_ANADIG_ANA_MISC2_CONTROL3 30
994 #define BM_ANADIG_ANA_MISC2_CONTROL3 (0x3 << BP_ANADIG_ANA_MISC2_CONTROL3)
995 #define BF_ANADIG_ANA_MISC2_CONTROL3(v) \
996 (((v) << BP_ANADIG_ANA_MISC2_CONTROL3) & \
997 BM_ANADIG_ANA_MISC2_CONTROL3)
998 #define BP_ANADIG_ANA_MISC2_REG2_STEP_TIME 28
999 #define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME (0x3 << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME)
1000 #define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v) \
1001 (((v) << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME) & \
1002 BM_ANADIG_ANA_MISC2_REG2_STEP_TIME)
1003 #define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME 26
1004 #define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME (0x3 << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME)
1005 #define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v) \
1006 (((v) << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME) & \
1007 BM_ANADIG_ANA_MISC2_REG1_STEP_TIME)
1008 #define BP_ANADIG_ANA_MISC2_REG0_STEP_TIME 24
1009 #define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME (0x3 << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME)
1010 #define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v) \
1011 (((v) << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME) & \
1012 BM_ANADIG_ANA_MISC2_REG0_STEP_TIME)
1013 #define BM_ANADIG_ANA_MISC2_CONTROL2 (1 << 23)
1014 #define BM_ANADIG_ANA_MISC2_REG2_OK (1 << 22)
1015 #define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO (1 << 21)
1016 #define BM_ANADIG_ANA_MISC2_REG2_BO_STATUS (1 << 19)
1017 #define BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET 16
1018 #define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
1019 #define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v) \
1020 (((v) << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET) & \
1021 BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
1022 #define BM_ANADIG_ANA_MISC2_CONTROL1 (1 << 15)
1023 #define BM_ANADIG_ANA_MISC2_REG1_OK (1 << 14)
1024 #define BM_ANADIG_ANA_MISC2_REG1_ENABLE_BO (1 << 13)
1025 #define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS (1 << 11)
1026 #define BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET 8
1027 #define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET
1028 #define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v) \
1029 (((v) << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET) & \
1030 BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET)
1031 #define BM_ANADIG_ANA_MISC2_CONTROL0 (1 << 7)
1032 #define BM_ANADIG_ANA_MISC2_REG0_OK (1 << 6)
1033 #define BM_ANADIG_ANA_MISC2_REG0_ENABLE_BO (1 << 5)
1034 #define BM_ANADIG_ANA_MISC2_REG0_BO_STATUS (1 << 3)
1035 #define BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0
1036 #define BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
1037 #define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v) \
1038 (((v) << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET) & \
1039 BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
1041 #define BP_ANADIG_TEMPSENSE0_ALARM_VALUE 20
1042 #define BM_ANADIG_TEMPSENSE0_ALARM_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_ALARM_VALUE)
1043 #define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v) \
1044 (((v) << BP_ANADIG_TEMPSENSE0_ALARM_VALUE) & \
1045 BM_ANADIG_TEMPSENSE0_ALARM_VALUE)
1046 #define BP_ANADIG_TEMPSENSE0_TEMP_VALUE 8
1047 #define BM_ANADIG_TEMPSENSE0_TEMP_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_TEMP_VALUE)
1048 #define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v) \
1049 (((v) << BP_ANADIG_TEMPSENSE0_TEMP_VALUE) & \
1050 BM_ANADIG_TEMPSENSE0_TEMP_VALUE)
1051 #define BM_ANADIG_TEMPSENSE0_TEST (1 << 6)
1052 #define BP_ANADIG_TEMPSENSE0_VBGADJ 3
1053 #define BM_ANADIG_TEMPSENSE0_VBGADJ (0x7 << BP_ANADIG_TEMPSENSE0_VBGADJ)
1054 #define BF_ANADIG_TEMPSENSE0_VBGADJ(v) \
1055 (((v) << BP_ANADIG_TEMPSENSE0_VBGADJ) & \
1056 BM_ANADIG_TEMPSENSE0_VBGADJ)
1057 #define BM_ANADIG_TEMPSENSE0_FINISHED (1 << 2)
1058 #define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP (1 << 1)
1059 #define BM_ANADIG_TEMPSENSE0_POWER_DOWN (1 << 0)
1061 #define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ 0
1062 #define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ (0xFFFF << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ)
1063 #define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v) \
1064 (((v) << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ) & \
1065 BM_ANADIG_TEMPSENSE1_MEASURE_FREQ)
1067 #define MXC_CCM_CCGR6_USBOH3_OFFSET 0
1068 #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
1069 #define MXC_CCM_CCGR6_USDHC1_OFFSET 2
1070 #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
1071 #define MXC_CCM_CCGR6_USDHC2_OFFSET 4
1072 #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
1073 #define MXC_CCM_CCGR6_USDHC3_OFFSET 6
1074 #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
1075 #define MXC_CCM_CCGR6_USDHC4_OFFSET 8
1076 #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
1077 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
1078 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
1079 #ifdef CONFIG_SOC_MX6SX
1080 #define MXC_CCM_CCGR6_PWM8_OFFSET 16
1081 #define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
1082 #define MXC_CCM_CCGR6_VADC_OFFSET 20
1083 #define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET)
1084 #define MXC_CCM_CCGR6_GIS_OFFSET 22
1085 #define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET)
1086 #define MXC_CCM_CCGR6_I2C4_OFFSET 24
1087 #define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET)
1088 #define MXC_CCM_CCGR6_PWM5_OFFSET 26
1089 #define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET)
1090 #define MXC_CCM_CCGR6_PWM6_OFFSET 28
1091 #define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
1092 #define MXC_CCM_CCGR6_PWM7_OFFSET 30
1093 #define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
1095 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
1096 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
1099 #define BM_ANADIG_USB_PLL_480_CTRL_LOCK (1 << 31)
1100 #define BM_ANADIG_USB_PLL_480_CTRL_BYPASS (1 << 16)
1101 #define BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC 14
1102 #define BM_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC)
1103 #define BF_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
1104 (((v) << BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC) & \
1105 BM_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC)
1106 #define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
1107 #define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
1108 #define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
1109 #define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
1110 #define BM_ANADIG_USB_PLL_480_CTRL_ENABLE (1 << 13)
1111 #define BM_ANADIG_USB_PLL_480_CTRL_POWER (1 << 12)
1112 #define BM_ANADIG_USB_PLL_480_CTRL_HOLD_RING_OFF (1 << 11)
1113 #define BM_ANADIG_USB_PLL_480_CTRL_DOUBLE_CP (1 << 10)
1114 #define BM_ANADIG_USB_PLL_480_CTRL_HALF_CP (1 << 9)
1115 #define BM_ANADIG_USB_PLL_480_CTRL_DOUBLE_LF (1 << 8)
1116 #define BM_ANADIG_USB_PLL_480_CTRL_HALF_LF (1 << 7)
1117 #define BM_ANADIG_USB_PLL_480_CTRL_EN_USB_CLKS (1 << 6)
1118 #define BP_ANADIG_USB_PLL_480_CTRL_CONTROL0 2
1119 #define BM_ANADIG_USB_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB_PLL_480_CTRL_CONTROL0)
1120 #define BF_ANADIG_USB_PLL_480_CTRL_CONTROL0(v) \
1121 (((v) << BP_ANADIG_USB_PLL_480_CTRL_CONTROL0) & \
1122 BM_ANADIG_USB_PLL_480_CTRL_CONTROL0)
1123 #define BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT 0
1124 #define BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT)
1125 #define BF_ANADIG_USB_PLL_480_CTRL_DIV_SELECT(v) \
1126 (((v) << BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT) & \
1127 BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT)
1129 #define BM_ANADIG_PLL_528_LOCK (1 << 31)
1130 #define BM_ANADIG_PLL_528_PLL_SEL (1 << 19)
1131 #define BM_ANADIG_PLL_528_LVDS_24MHZ_SEL (1 << 18)
1132 #define BM_ANADIG_PLL_528_LVDS_SEL (1 << 17)
1133 #define BM_ANADIG_PLL_528_BYPASS (1 << 16)
1134 #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
1135 #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_528_BYPASS_CLK_SRC)
1136 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \
1137 (((v) << BP_ANADIG_PLL_528_BYPASS_CLK_SRC) & \
1138 BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
1139 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
1140 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
1141 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
1142 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
1143 #define BM_ANADIG_PLL_528_ENABLE (1 << 13)
1144 #define BM_ANADIG_PLL_528_POWERDOWN (1 << 12)
1145 #define BM_ANADIG_PLL_528_HOLD_RING_OFF (1 << 11)
1146 #define BM_ANADIG_PLL_528_DOUBLE_CP (1 << 10)
1147 #define BM_ANADIG_PLL_528_HALF_CP (1 << 9)
1148 #define BM_ANADIG_PLL_528_DOUBLE_LF (1 << 8)
1149 #define BM_ANADIG_PLL_528_HALF_LF (1 << 7)
1150 #define BP_ANADIG_PLL_528_DIV_SELECT 0
1151 #define BM_ANADIG_PLL_528_DIV_SELECT (0x7F << BP_ANADIG_PLL_528_DIV_SELECT)
1152 #define BF_ANADIG_PLL_528_DIV_SELECT(v) \
1153 (((v) << BP_ANADIG_PLL_528_DIV_SELECT) & \
1154 BM_ANADIG_PLL_528_DIV_SELECT)
1156 #define BP_ANADIG_PLL_528_SS_STOP 16
1157 #define BM_ANADIG_PLL_528_SS_STOP (0xFFFF << BP_ANADIG_PLL_528_SS_STOP)
1158 #define BF_ANADIG_PLL_528_SS_STOP(v) \
1159 (((v) << BP_ANADIG_PLL_528_SS_STOP) & \
1160 BM_ANADIG_PLL_528_SS_STOP)
1161 #define BM_ANADIG_PLL_528_SS_ENABLE (1 << 15)
1162 #define BP_ANADIG_PLL_528_SS_STEP 0
1163 #define BM_ANADIG_PLL_528_SS_STEP (0x7FFF << BP_ANADIG_PLL_528_SS_STEP)
1164 #define BF_ANADIG_PLL_528_SS_STEP(v) \
1165 (((v) << BP_ANADIG_PLL_528_SS_STEP) & \
1166 BM_ANADIG_PLL_528_SS_STEP)
1168 #define BP_ANADIG_PLL_528_NUM_A 0
1169 #define BM_ANADIG_PLL_528_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_528_NUM_A)
1170 #define BF_ANADIG_PLL_528_NUM_A(v) \
1171 (((v) << BP_ANADIG_PLL_528_NUM_A) & \
1172 BM_ANADIG_PLL_528_NUM_A)
1174 #define BP_ANADIG_PLL_528_DENOM_B 0
1175 #define BM_ANADIG_PLL_528_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_528_DENOM_B)
1176 #define BF_ANADIG_PLL_528_DENOM_B(v) \
1177 (((v) << BP_ANADIG_PLL_528_DENOM_B) & \
1178 BM_ANADIG_PLL_528_DENOM_B)
1180 #define BM_ANADIG_PLL_AUDIO_LOCK (1 << 31)
1181 #define BM_ANADIG_PLL_AUDIO_SSC_EN (1 << 21)
1182 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
1183 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
1184 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
1185 (((v) << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) & \
1186 BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
1187 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18)
1188 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE (1 << 17)
1189 #define BM_ANADIG_PLL_AUDIO_BYPASS (1 << 16)
1190 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
1191 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
1192 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
1193 (((v) << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) & \
1194 BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
1195 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
1196 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
1197 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
1198 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
1199 #define BM_ANADIG_PLL_AUDIO_ENABLE (1 << 13)
1200 #define BM_ANADIG_PLL_AUDIO_POWERDOWN (1 << 12)
1201 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF (1 << 11)
1202 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP (1 << 10)
1203 #define BM_ANADIG_PLL_AUDIO_HALF_CP (1 << 9)
1204 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF (1 << 8)
1205 #define BM_ANADIG_PLL_AUDIO_HALF_LF (1 << 7)
1206 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
1207 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT)
1208 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
1209 (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & \
1210 BM_ANADIG_PLL_AUDIO_DIV_SELECT)
1212 #define BP_ANADIG_PLL_AUDIO_NUM_A 0
1213 #define BM_ANADIG_PLL_AUDIO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_NUM_A)
1214 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
1215 (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & \
1216 BM_ANADIG_PLL_AUDIO_NUM_A)
1218 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0
1219 #define BM_ANADIG_PLL_AUDIO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_DENOM_B)
1220 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
1221 (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & \
1222 BM_ANADIG_PLL_AUDIO_DENOM_B)
1224 #define BM_ANADIG_PLL_VIDEO_LOCK (1 << 31)
1225 #define BM_ANADIG_PLL_VIDEO_SSC_EN (1 << 21)
1226 #define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19
1227 #define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT (0x3 << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
1228 #define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \
1229 (((v) << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT) & \
1230 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
1231 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18)
1232 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE (1 << 17)
1233 #define BM_ANADIG_PLL_VIDEO_BYPASS (1 << 16)
1234 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
1235 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
1236 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
1237 (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & \
1238 BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
1239 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
1240 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
1241 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
1242 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
1243 #define BM_ANADIG_PLL_VIDEO_ENABLE (1 << 13)
1244 #define BM_ANADIG_PLL_VIDEO_POWERDOWN (1 << 12)
1245 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF (1 << 11)
1246 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP (1 << 10)
1247 #define BM_ANADIG_PLL_VIDEO_HALF_CP (1 << 9)
1248 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF (1 << 8)
1249 #define BM_ANADIG_PLL_VIDEO_HALF_LF (1 << 7)
1250 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
1251 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT)
1252 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
1253 (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & \
1254 BM_ANADIG_PLL_VIDEO_DIV_SELECT)
1256 #define BP_ANADIG_PLL_VIDEO_NUM_A 0
1257 #define BM_ANADIG_PLL_VIDEO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A)
1258 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
1259 (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & \
1260 BM_ANADIG_PLL_VIDEO_NUM_A)
1262 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0
1263 #define BM_ANADIG_PLL_VIDEO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B)
1264 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
1265 (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & \
1266 BM_ANADIG_PLL_VIDEO_DENOM_B)
1268 #define BM_ANADIG_PLL_ENET_LOCK (1 << 31)
1269 #define BM_ANADIG_PLL_ENET_REF_25M_ENABLE (1 << 21)
1270 #define BM_ANADIG_PLL_ENET_ENABLE_SATA (1 << 20)
1271 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE (1 << 19)
1272 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN (1 << 18)
1273 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE (1 << 17)
1274 #define BM_ANADIG_PLL_ENET_BYPASS (1 << 16)
1275 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
1276 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
1277 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
1278 (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & \
1279 BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
1280 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
1281 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
1282 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
1283 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
1284 #define BM_ANADIG_PLL_ENET_ENABLE (1 << 13)
1285 #define BM_ANADIG_PLL_ENET_POWERDOWN (1 << 12)
1286 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF (1 << 11)
1287 #define BM_ANADIG_PLL_ENET_DOUBLE_CP (1 << 10)
1288 #define BM_ANADIG_PLL_ENET_HALF_CP (1 << 9)
1289 #define BM_ANADIG_PLL_ENET_DOUBLE_LF (1 << 8)
1290 #define BM_ANADIG_PLL_ENET_HALF_LF (1 << 7)
1291 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0
1292 #define BM_ANADIG_PLL_ENET_DIV_SELECT (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT)
1293 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
1294 (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & \
1295 BM_ANADIG_PLL_ENET_DIV_SELECT)
1297 #define BM_ANADIG_PFD_480_PFD3_CLKGATE (1 << 31)
1298 #define BM_ANADIG_PFD_480_PFD3_STABLE (1 << 30)
1299 #define BP_ANADIG_PFD_480_PFD3_FRAC 24
1300 #define BM_ANADIG_PFD_480_PFD3_FRAC (0x3F << BP_ANADIG_PFD_480_PFD3_FRAC)
1301 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
1302 (((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & \
1303 BM_ANADIG_PFD_480_PFD3_FRAC)
1304 #define BM_ANADIG_PFD_480_PFD2_CLKGATE (1 << 23)
1305 #define BM_ANADIG_PFD_480_PFD2_STABLE (1 << 22)
1306 #define BP_ANADIG_PFD_480_PFD2_FRAC 16
1307 #define BM_ANADIG_PFD_480_PFD2_FRAC (0x3F << BP_ANADIG_PFD_480_PFD2_FRAC)
1308 #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
1309 (((v) << BP_ANADIG_PFD_480_PFD2_FRAC) & \
1310 BM_ANADIG_PFD_480_PFD2_FRAC)
1311 #define BM_ANADIG_PFD_480_PFD1_CLKGATE (1 << 15)
1312 #define BM_ANADIG_PFD_480_PFD1_STABLE (1 << 14)
1313 #define BP_ANADIG_PFD_480_PFD1_FRAC 8
1314 #define BM_ANADIG_PFD_480_PFD1_FRAC (0x3F << BP_ANADIG_PFD_480_PFD1_FRAC)
1315 #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
1316 (((v) << BP_ANADIG_PFD_480_PFD1_FRAC) & \
1317 BM_ANADIG_PFD_480_PFD1_FRAC)
1318 #define BM_ANADIG_PFD_480_PFD0_CLKGATE (1 << 7)
1319 #define BM_ANADIG_PFD_480_PFD0_STABLE (1 << 6)
1320 #define BP_ANADIG_PFD_480_PFD0_FRAC 0
1321 #define BM_ANADIG_PFD_480_PFD0_FRAC (0x3F << BP_ANADIG_PFD_480_PFD0_FRAC)
1322 #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
1323 (((v) << BP_ANADIG_PFD_480_PFD0_FRAC) & \
1324 BM_ANADIG_PFD_480_PFD0_FRAC)
1326 #define BM_ANADIG_PFD_528_PFD3_CLKGATE (1 << 31)
1327 #define BM_ANADIG_PFD_528_PFD3_STABLE (1 << 30)
1328 #define BP_ANADIG_PFD_528_PFD3_FRAC 24
1329 #define BM_ANADIG_PFD_528_PFD3_FRAC (0x3F << BP_ANADIG_PFD_528_PFD3_FRAC)
1330 #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
1331 (((v) << BP_ANADIG_PFD_528_PFD3_FRAC) & \
1332 BM_ANADIG_PFD_528_PFD3_FRAC)
1333 #define BM_ANADIG_PFD_528_PFD2_CLKGATE (1 << 23)
1334 #define BM_ANADIG_PFD_528_PFD2_STABLE (1 << 22)
1335 #define BP_ANADIG_PFD_528_PFD2_FRAC 16
1336 #define BM_ANADIG_PFD_528_PFD2_FRAC (0x3F << BP_ANADIG_PFD_528_PFD2_FRAC)
1337 #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
1338 (((v) << BP_ANADIG_PFD_528_PFD2_FRAC) & \
1339 BM_ANADIG_PFD_528_PFD2_FRAC)
1340 #define BM_ANADIG_PFD_528_PFD1_CLKGATE (1 << 15)
1341 #define BM_ANADIG_PFD_528_PFD1_STABLE (1 << 14)
1342 #define BP_ANADIG_PFD_528_PFD1_FRAC 8
1343 #define BM_ANADIG_PFD_528_PFD1_FRAC (0x3F << BP_ANADIG_PFD_528_PFD1_FRAC)
1344 #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
1345 (((v) << BP_ANADIG_PFD_528_PFD1_FRAC) & \
1346 BM_ANADIG_PFD_528_PFD1_FRAC)
1347 #define BM_ANADIG_PFD_528_PFD0_CLKGATE (1 << 7)
1348 #define BM_ANADIG_PFD_528_PFD0_STABLE (1 << 6)
1349 #define BP_ANADIG_PFD_528_PFD0_FRAC 0
1350 #define BM_ANADIG_PFD_528_PFD0_FRAC (0x3F << BP_ANADIG_PFD_528_PFD0_FRAC)
1351 #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
1352 (((v) << BP_ANADIG_PFD_528_PFD0_FRAC) & \
1353 BM_ANADIG_PFD_528_PFD0_FRAC)
1355 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */