3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/compiler.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 #if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */
19 #if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
21 #define PROFF_SMC PROFF_SMC1
22 #define CPM_CR_CH_SMC CPM_CR_CH_SMC1
24 #elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
26 #define PROFF_SMC PROFF_SMC2
27 #define CPM_CR_CH_SMC CPM_CR_CH_SMC2
29 #endif /* CONFIG_8xx_CONS_SMCx */
31 #if defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */
33 #define PROFF_SCC PROFF_SCC1
34 #define CPM_CR_CH_SCC CPM_CR_CH_SCC1
36 #elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */
38 #define PROFF_SCC PROFF_SCC2
39 #define CPM_CR_CH_SCC CPM_CR_CH_SCC2
41 #elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */
43 #define PROFF_SCC PROFF_SCC3
44 #define CPM_CR_CH_SCC CPM_CR_CH_SCC3
46 #elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */
48 #define PROFF_SCC PROFF_SCC4
49 #define CPM_CR_CH_SCC CPM_CR_CH_SCC4
51 #endif /* CONFIG_8xx_CONS_SCCx */
53 #if !defined(CONFIG_SYS_SMC_RXBUFLEN)
54 #define CONFIG_SYS_SMC_RXBUFLEN 1
55 #define CONFIG_SYS_MAXIDLE 0
57 #if !defined(CONFIG_SYS_MAXIDLE)
58 #error "you must define CONFIG_SYS_MAXIDLE"
62 typedef volatile struct serialbuffer {
63 cbd_t rxbd; /* Rx BD */
64 cbd_t txbd; /* Tx BD */
65 uint rxindex; /* index for next character to read */
66 volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
67 volatile uchar txbuf; /* tx buffers */
70 static void serial_setdivisor(volatile cpm8xx_t *cp)
72 int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
74 if(divisor/16>0x1000) {
75 /* bad divisor, assume 50MHz clock and 9600 baud */
76 divisor=(50*1000*1000 + 8*9600)/16/9600;
79 #ifdef CONFIG_SYS_BRGCLK_PRESCALE
80 divisor /= CONFIG_SYS_BRGCLK_PRESCALE;
84 cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
86 cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
90 #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
93 * Minimal serial functions needed to use one of the SMC ports
94 * as serial console interface.
97 static void smc_setbrg (void)
99 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
100 volatile cpm8xx_t *cp = &(im->im_cpm);
102 /* Set up the baud rate generator.
103 * See 8xx_io/commproc.c for details.
108 cp->cp_simode = 0x00000000;
110 serial_setdivisor(cp);
113 static int smc_init (void)
115 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
117 volatile smc_uart_t *up;
118 volatile cpm8xx_t *cp = &(im->im_cpm);
119 #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
120 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
123 volatile serialbuffer_t *rtx;
125 /* initialize pointers to SMC */
127 sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
128 up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
129 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
130 up = (smc_uart_t *) &cp->cp_dpmem[up->smc_rpbase];
132 /* Disable relocation */
136 /* Disable transmitter/receiver. */
137 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
140 im->im_siu_conf.sc_sdcr = 1;
142 /* clear error conditions */
143 #ifdef CONFIG_SYS_SDSR
144 im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
146 im->im_sdma.sdma_sdsr = 0x83;
149 /* clear SDMA interrupt mask */
150 #ifdef CONFIG_SYS_SDMR
151 im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
153 im->im_sdma.sdma_sdmr = 0x00;
156 #if defined(CONFIG_8xx_CONS_SMC1)
157 /* Use Port B for SMC1 instead of other functions. */
158 cp->cp_pbpar |= 0x000000c0;
159 cp->cp_pbdir &= ~0x000000c0;
160 cp->cp_pbodr &= ~0x000000c0;
161 #else /* CONFIG_8xx_CONS_SMC2 */
162 # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
163 /* Use Port A for SMC2 instead of other functions. */
164 ip->iop_papar |= 0x00c0;
165 ip->iop_padir &= ~0x00c0;
166 ip->iop_paodr &= ~0x00c0;
167 # else /* must be a 860 then */
168 /* Use Port B for SMC2 instead of other functions.
170 cp->cp_pbpar |= 0x00000c00;
171 cp->cp_pbdir &= ~0x00000c00;
172 cp->cp_pbodr &= ~0x00000c00;
176 #if defined(CONFIG_FADS)
178 #if defined(CONFIG_8xx_CONS_SMC1)
179 *((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
181 *((uint *) BCSR1) &= ~BCSR1_RS232EN_2;
183 #endif /* CONFIG_FADS */
185 /* Set the physical address of the host memory buffers in
186 * the buffer descriptors.
189 #ifdef CONFIG_SYS_ALLOC_DPRAM
191 * size of struct serialbuffer with bd rx/tx, buffer rx/tx and rx index
193 dpaddr = dpram_alloc_align((sizeof(serialbuffer_t)), 8);
195 dpaddr = CPM_SERIAL_BASE ;
198 rtx = (serialbuffer_t *)&cp->cp_dpmem[dpaddr];
199 /* Allocate space for two buffer descriptors in the DP ram.
200 * For now, this address seems OK, but it may have to
201 * change with newer versions of the firmware.
202 * damm: allocating space after the two buffers for rx/tx data
205 rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf;
206 rtx->rxbd.cbd_sc = 0;
208 rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf;
209 rtx->txbd.cbd_sc = 0;
211 /* Set up the uart parameters in the parameter ram. */
212 up->smc_rbase = dpaddr;
213 up->smc_tbase = dpaddr+sizeof(cbd_t);
214 up->smc_rfcr = SMC_EB;
215 up->smc_tfcr = SMC_EB;
216 #if defined (CONFIG_SYS_SMC_UCODE_PATCH)
217 up->smc_rbptr = up->smc_rbase;
218 up->smc_tbptr = up->smc_tbase;
223 /* Set UART mode, 8 bit, no parity, one stop.
224 * Enable receive and transmit.
226 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
228 /* Mask all interrupts and remove anything pending.
233 #ifdef CONFIG_SYS_SPC1920_SMC1_CLK4
234 /* clock source is PLD */
236 /* set freq to 19200 Baud */
237 *((volatile uchar *) CONFIG_SYS_SPC1920_PLD_BASE+6) = 0x3;
238 /* configure clk4 as input */
239 im->im_ioport.iop_pdpar |= 0x800;
240 im->im_ioport.iop_pddir &= ~0x800;
242 cp->cp_simode = ((cp->cp_simode & ~0xf000) | 0x7000);
244 /* Set up the baud rate generator */
248 /* Make the first buffer the only buffer. */
249 rtx->txbd.cbd_sc |= BD_SC_WRAP;
250 rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
252 /* single/multi character receive. */
253 up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN;
254 up->smc_maxidl = CONFIG_SYS_MAXIDLE;
257 /* Initialize Tx/Rx parameters. */
258 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
261 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
263 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
266 /* Enable transmitter/receiver. */
267 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
273 smc_putc(const char c)
275 volatile smc_uart_t *up;
276 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
277 volatile cpm8xx_t *cpmp = &(im->im_cpm);
278 volatile serialbuffer_t *rtx;
280 #ifdef CONFIG_MODEM_SUPPORT
288 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
289 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
290 up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
293 rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
295 /* Wait for last character to go. */
297 rtx->txbd.cbd_datlen = 1;
298 rtx->txbd.cbd_sc |= BD_SC_READY;
301 while (rtx->txbd.cbd_sc & BD_SC_READY) {
308 smc_puts (const char *s)
318 volatile smc_uart_t *up;
319 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
320 volatile cpm8xx_t *cpmp = &(im->im_cpm);
321 volatile serialbuffer_t *rtx;
324 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
325 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
326 up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
328 rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
330 /* Wait for character to show up. */
331 while (rtx->rxbd.cbd_sc & BD_SC_EMPTY)
334 /* the characters are read one by one,
335 * use the rxindex to know the next char to deliver
337 c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr+rtx->rxindex);
340 /* check if all char are readout, then make prepare for next receive */
341 if (rtx->rxindex >= rtx->rxbd.cbd_datlen) {
343 rtx->rxbd.cbd_sc |= BD_SC_EMPTY;
351 volatile smc_uart_t *up;
352 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
353 volatile cpm8xx_t *cpmp = &(im->im_cpm);
354 volatile serialbuffer_t *rtx;
356 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
357 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
358 up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
361 rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
363 return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY);
366 struct serial_device serial_smc_device =
368 .name = "serial_smc",
371 .setbrg = smc_setbrg,
378 #endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */
380 #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
381 defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
386 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
387 volatile cpm8xx_t *cp = &(im->im_cpm);
389 /* Set up the baud rate generator.
390 * See 8xx_io/commproc.c for details.
395 cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
397 serial_setdivisor(cp);
400 static int scc_init (void)
402 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
404 volatile scc_uart_t *up;
405 volatile cbd_t *tbdf, *rbdf;
406 volatile cpm8xx_t *cp = &(im->im_cpm);
408 #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
409 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
412 /* initialize pointers to SCC */
414 sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
415 up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
417 #if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2)
418 { /* Disable Ethernet, enable Serial */
422 c &= ~0x40; /* enable COM3 */
423 c |= 0x80; /* disable Ethernet */
427 cp->cp_pbpar |= 0x2000;
428 cp->cp_pbdat |= 0x2000;
429 cp->cp_pbdir |= 0x2000;
431 #endif /* CONFIG_LWMON */
433 /* Disable transmitter/receiver. */
434 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
436 #if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
438 * The MPC850 has SCC3 on Port B
440 cp->cp_pbpar |= 0x06;
441 cp->cp_pbdir &= ~0x06;
442 cp->cp_pbodr &= ~0x06;
444 #elif (SCC_INDEX < 2) || !defined(CONFIG_IP860)
446 * Standard configuration for SCC's is on Part A
448 ip->iop_papar |= ((3 << (2 * SCC_INDEX)));
449 ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
450 ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
453 * The IP860 has SCC3 and SCC4 on Port D
455 ip->iop_pdpar |= ((3 << (2 * SCC_INDEX)));
458 /* Allocate space for two buffer descriptors in the DP ram. */
460 #ifdef CONFIG_SYS_ALLOC_DPRAM
461 dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
463 dpaddr = CPM_SERIAL2_BASE ;
467 im->im_siu_conf.sc_sdcr = 0x0001;
469 /* Set the physical address of the host memory buffers in
470 * the buffer descriptors.
473 rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
474 rbdf->cbd_bufaddr = (uint) (rbdf+2);
477 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
480 /* Set up the baud rate generator. */
483 /* Set up the uart parameters in the parameter ram. */
484 up->scc_genscc.scc_rbase = dpaddr;
485 up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
487 /* Initialize Tx/Rx parameters. */
488 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
490 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
492 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
495 up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
496 up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
498 up->scc_genscc.scc_mrblr = 1; /* Single character receive */
499 up->scc_maxidl = 0; /* disable max idle */
500 up->scc_brkcr = 1; /* send one break character on stop TX */
508 up->scc_char1 = 0x8000;
509 up->scc_char2 = 0x8000;
510 up->scc_char3 = 0x8000;
511 up->scc_char4 = 0x8000;
512 up->scc_char5 = 0x8000;
513 up->scc_char6 = 0x8000;
514 up->scc_char7 = 0x8000;
515 up->scc_char8 = 0x8000;
516 up->scc_rccm = 0xc0ff;
518 /* Set low latency / small fifo. */
519 sp->scc_gsmrh = SCC_GSMRH_RFW;
521 /* Set SCC(x) clock mode to 16x
522 * See 8xx_io/commproc.c for details.
527 /* Set UART mode, clock divider 16 on Tx and Rx */
528 sp->scc_gsmrl &= ~0xF;
530 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
533 sp->scc_psmr |= SCU_PSMR_CL;
535 /* Mask all interrupts and remove anything pending. */
537 sp->scc_scce = 0xffff;
538 sp->scc_dsr = 0x7e7e;
539 sp->scc_psmr = 0x3000;
541 /* Make the first buffer the only buffer. */
542 tbdf->cbd_sc |= BD_SC_WRAP;
543 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
545 /* Enable transmitter/receiver. */
546 sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
552 scc_putc(const char c)
554 volatile cbd_t *tbdf;
556 volatile scc_uart_t *up;
557 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
558 volatile cpm8xx_t *cpmp = &(im->im_cpm);
560 #ifdef CONFIG_MODEM_SUPPORT
568 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
570 tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
572 /* Wait for last character to go. */
574 buf = (char *)tbdf->cbd_bufaddr;
577 tbdf->cbd_datlen = 1;
578 tbdf->cbd_sc |= BD_SC_READY;
581 while (tbdf->cbd_sc & BD_SC_READY) {
588 scc_puts (const char *s)
598 volatile cbd_t *rbdf;
599 volatile unsigned char *buf;
600 volatile scc_uart_t *up;
601 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
602 volatile cpm8xx_t *cpmp = &(im->im_cpm);
605 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
607 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
609 /* Wait for character to show up. */
610 buf = (unsigned char *)rbdf->cbd_bufaddr;
612 while (rbdf->cbd_sc & BD_SC_EMPTY)
616 rbdf->cbd_sc |= BD_SC_EMPTY;
624 volatile cbd_t *rbdf;
625 volatile scc_uart_t *up;
626 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
627 volatile cpm8xx_t *cpmp = &(im->im_cpm);
629 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
631 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
633 return(!(rbdf->cbd_sc & BD_SC_EMPTY));
636 struct serial_device serial_scc_device =
638 .name = "serial_scc",
641 .setbrg = scc_setbrg,
648 #endif /* CONFIG_8xx_CONS_SCCx */
650 __weak struct serial_device *default_serial_console(void)
652 #if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
653 return &serial_smc_device;
655 return &serial_scc_device;
659 void mpc8xx_serial_initialize(void)
661 #if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
662 serial_register(&serial_smc_device);
664 #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
665 defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
666 serial_register(&serial_scc_device);
670 #ifdef CONFIG_MODEM_SUPPORT
671 void disable_putc(void)
676 void enable_putc(void)
682 #if defined(CONFIG_CMD_KGDB)
685 kgdb_serial_init(void)
689 if (strcmp(default_serial_console()->name, "serial_smc") == 0)
691 #if defined(CONFIG_8xx_CONS_SMC1)
693 #elif defined(CONFIG_8xx_CONS_SMC2)
697 else if (strcmp(default_serial_console()->name, "serial_scc") == 0)
699 #if defined(CONFIG_8xx_CONS_SCC1)
701 #elif defined(CONFIG_8xx_CONS_SCC2)
703 #elif defined(CONFIG_8xx_CONS_SCC3)
705 #elif defined(CONFIG_8xx_CONS_SCC4)
712 serial_printf("[on %s%d] ", default_serial_console()->name, i);
723 putDebugStr (const char *str)
731 return serial_getc();
735 kgdb_interruptible (int yes)
741 #endif /* CONFIG_8xx_CONS_NONE */