3 * Ingo Assmus <ingo.assmus@keymile.com>
5 * based on - Driver for MV64360X ethernet ports
6 * Copyright (C) 2002 rabeeh@galileo.co.il
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * mv_eth.c - header file for the polled mode GT ethernet driver
36 /* enable Debug outputs */
47 #undef MV64360_CHECKSUM_OFFLOAD
48 /*************************************************************************
49 **************************************************************************
50 **************************************************************************
51 * The first part is the high level driver of the gigE ethernet ports. *
52 **************************************************************************
53 **************************************************************************
54 *************************************************************************/
56 /* Definition for configuring driver */
57 /* #define UPDATE_STATS_BY_SOFTWARE */
58 #undef MV64360_RX_QUEUE_FILL_ON_TASK
62 #define MAGIC_ETH_RUNNING 8031971
63 #define MV64360_INTERNAL_SRAM_SIZE _256K
64 #define EXTRA_BYTES 32
65 #define WRAP ETH_HLEN + 2 + 4 + 16
66 #define BUFFER_MTU dev->mtu + WRAP
67 #define INT_CAUSE_UNMASK_ALL 0x0007ffff
68 #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
69 #ifdef MV64360_RX_FILL_ON_TASK
70 #define INT_CAUSE_MASK_ALL 0x00000000
71 #define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
72 #define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
75 /* Read/Write to/from MV64360 internal registers */
76 #define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
77 #define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
78 #define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
79 #define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
81 /* Static function declarations */
82 static int mv64360_eth_real_open (struct eth_device *eth);
83 static int mv64360_eth_real_stop (struct eth_device *eth);
84 static struct net_device_stats *mv64360_eth_get_stats (struct eth_device
86 static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
87 static void mv64360_eth_update_stat (struct eth_device *dev);
88 bool db64360_eth_start (struct eth_device *eth);
89 unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
90 unsigned int mib_offset);
91 int mv64360_eth_receive (struct eth_device *dev);
93 int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length);
95 #ifndef UPDATE_STATS_BY_SOFTWARE
96 static void mv64360_eth_print_stat (struct eth_device *dev);
99 extern unsigned int INTERNAL_REG_BASE_ADDR;
101 /*************************************************
102 *Helper functions - used inside the driver only *
103 *************************************************/
105 void print_globals (struct eth_device *dev)
107 printf ("Ethernet PRINT_Globals-Debug function\n");
108 printf ("Base Address for ETH_PORT_INFO: %08x\n",
109 (unsigned int) dev->priv);
110 printf ("Base Address for mv64360_eth_priv: %08x\n",
111 (unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
114 printf ("GT Internal Base Address: %08x\n",
115 INTERNAL_REG_BASE_ADDR);
116 printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE);
117 printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE);
118 printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n",
119 (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
121 (MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32);
122 printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n",
123 (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
125 (MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32);
129 #define my_cpu_to_le32(x) my_le32_to_cpu((x))
131 unsigned long my_le32_to_cpu (unsigned long x)
133 return (((x & 0x000000ffU) << 24) |
134 ((x & 0x0000ff00U) << 8) |
135 ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
139 /**********************************************************************
140 * mv64360_eth_print_phy_status
142 * Prints gigabit ethenret phy status
144 * Input : pointer to ethernet interface network device structure
146 **********************************************************************/
148 static void mv64360_eth_print_phy_status (struct eth_device *dev)
150 struct mv64360_eth_priv *port_private;
151 unsigned int port_num;
152 ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
153 unsigned int port_status, phy_reg_data;
156 (struct mv64360_eth_priv *) ethernet_private->port_private;
157 port_num = port_private->port_num;
159 /* Check Link status on phy */
160 eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
161 if (!(phy_reg_data & 0x20)) {
162 printf ("Ethernet port changed link status to DOWN\n");
165 MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
166 printf ("Ethernet status port %d: Link up", port_num);
168 (port_status & BIT2) ? "Full Duplex" : "Half Duplex");
169 if (port_status & BIT4)
170 printf (", Speed 1 Gbps");
173 (port_status & BIT5) ? "Speed 100 Mbps" :
179 /**********************************************************************
180 * u-boot entry functions for mv64360_eth
182 **********************************************************************/
183 int db64360_eth_probe (struct eth_device *dev)
185 return ((int) db64360_eth_start (dev));
188 int db64360_eth_poll (struct eth_device *dev)
190 return mv64360_eth_receive (dev);
193 int db64360_eth_transmit (struct eth_device *dev, volatile void *packet,
196 mv64360_eth_xmit (dev, packet, length);
200 void db64360_eth_disable (struct eth_device *dev)
202 mv64360_eth_stop (dev);
206 void mv6436x_eth_initialize (bd_t * bis)
208 struct eth_device *dev;
209 ETH_PORT_INFO *ethernet_private;
210 struct mv64360_eth_priv *port_private;
212 char *s, *e, buf[64];
214 for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
215 dev = calloc (sizeof (*dev), 1);
217 printf ("%s: mv_enet%d allocation failure, %s\n",
218 __FUNCTION__, devnum, "eth_device structure");
222 /* must be less than sizeof(dev->name) */
223 sprintf (dev->name, "mv_enet%d", devnum);
226 printf ("Initializing %s\n", dev->name);
229 /* Extract the MAC address from the environment */
243 default: /* this should never happen */
244 printf ("%s: Invalid device number %d\n",
245 __FUNCTION__, devnum);
249 temp = getenv_f(s, buf, sizeof (buf));
250 s = (temp > 0) ? buf : NULL;
253 printf ("Setting MAC %d to %s\n", devnum, s);
255 for (x = 0; x < 6; ++x) {
256 dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
258 s = (*e) ? e + 1 : e;
260 /* ronen - set the MAC addr in the HW */
261 eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
263 dev->init = (void *) db64360_eth_probe;
264 dev->halt = (void *) ethernet_phy_reset;
265 dev->send = (void *) db64360_eth_transmit;
266 dev->recv = (void *) db64360_eth_poll;
269 calloc (sizeof (*ethernet_private), 1);
270 dev->priv = (void *) ethernet_private;
271 if (!ethernet_private) {
272 printf ("%s: %s allocation failure, %s\n",
273 __FUNCTION__, dev->name,
274 "Private Device Structure");
278 /* start with an zeroed ETH_PORT_INFO */
279 memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
280 memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
282 /* set pointer to memory for stats data structure etc... */
284 calloc (sizeof (*ethernet_private), 1);
285 ethernet_private->port_private = (void *)port_private;
287 printf ("%s: %s allocation failure, %s\n",
288 __FUNCTION__, dev->name,
289 "Port Private Device Structure");
291 free (ethernet_private);
296 port_private->stats =
297 calloc (sizeof (struct net_device_stats), 1);
298 if (!port_private->stats) {
299 printf ("%s: %s allocation failure, %s\n",
300 __FUNCTION__, dev->name,
301 "Net stat Structure");
304 free (ethernet_private);
308 memset (ethernet_private->port_private, 0,
309 sizeof (struct mv64360_eth_priv));
312 ethernet_private->port_num = ETH_0;
315 ethernet_private->port_num = ETH_1;
318 ethernet_private->port_num = ETH_2;
321 printf ("Invalid device number %d\n", devnum);
325 port_private->port_num = devnum;
327 * Read MIB counter on the GT in order to reset them,
328 * then zero all the stats fields in memory
330 mv64360_eth_update_stat (dev);
331 memset (port_private->stats, 0,
332 sizeof (struct net_device_stats));
333 /* Extract the MAC address from the environment */
347 default: /* this should never happen */
348 printf ("%s: Invalid device number %d\n",
349 __FUNCTION__, devnum);
353 temp = getenv_f(s, buf, sizeof (buf));
354 s = (temp > 0) ? buf : NULL;
357 printf ("Setting MAC %d to %s\n", devnum, s);
359 for (x = 0; x < 6; ++x) {
360 dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
362 s = (*e) ? e + 1 : e;
365 DP (printf ("Allocating descriptor and buffer rings\n"));
367 ethernet_private->p_rx_desc_area_base[0] =
368 (ETH_RX_DESC *) memalign (16,
369 RX_DESC_ALIGNED_SIZE *
370 MV64360_RX_QUEUE_SIZE + 1);
371 ethernet_private->p_tx_desc_area_base[0] =
372 (ETH_TX_DESC *) memalign (16,
373 TX_DESC_ALIGNED_SIZE *
374 MV64360_TX_QUEUE_SIZE + 1);
376 ethernet_private->p_rx_buffer_base[0] =
377 (char *) memalign (16,
378 MV64360_RX_QUEUE_SIZE *
379 MV64360_TX_BUFFER_SIZE + 1);
380 ethernet_private->p_tx_buffer_base[0] =
381 (char *) memalign (16,
382 MV64360_RX_QUEUE_SIZE *
383 MV64360_TX_BUFFER_SIZE + 1);
386 /* DEBUG OUTPUT prints adresses of globals */
392 DP (printf ("%s: exit\n", __FUNCTION__));
396 /**********************************************************************
399 * This function is called when openning the network device. The function
400 * should initialize all the hardware, initialize cyclic Rx/Tx
401 * descriptors chain and buffers and allocate an IRQ to the network
404 * Input : a pointer to the network device structure
405 * / / ronen - changed the output to match net/eth.c needs
406 * Output : nonzero of success , zero if fails.
408 **********************************************************************/
410 int mv64360_eth_open (struct eth_device *dev)
412 return (mv64360_eth_real_open (dev));
415 /* Helper function for mv64360_eth_open */
416 static int mv64360_eth_real_open (struct eth_device *dev)
420 ETH_PORT_INFO *ethernet_private;
421 struct mv64360_eth_priv *port_private;
422 unsigned int port_num;
425 ethernet_private = (ETH_PORT_INFO *) dev->priv;
426 /* ronen - when we update the MAC env params we only update dev->enetaddr
427 see ./net/eth.c eth_set_enetaddr() */
428 memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
431 (struct mv64360_eth_priv *) ethernet_private->port_private;
432 port_num = port_private->port_num;
435 MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
438 /* Clear the ethernet port interrupts */
439 MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
440 MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
442 /* Unmask RX buffer and TX end interrupt */
443 MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num),
444 INT_CAUSE_UNMASK_ALL);
446 /* Unmask phy and link status changes interrupts */
447 MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
448 INT_CAUSE_UNMASK_ALL_EXT);
450 /* Set phy address of the port */
451 ethernet_private->port_phy_addr = 0x8 + port_num;
453 /* Activate the DMA channels etc */
454 eth_port_init (ethernet_private);
457 /* "Allocate" setup TX rings */
459 for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
462 port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE;
463 size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */
464 ethernet_private->tx_desc_area_size[queue] = size;
466 /* first clear desc area completely */
467 memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
468 0, ethernet_private->tx_desc_area_size[queue]);
470 /* initialize tx desc ring with low level driver */
471 if (ether_init_tx_desc_ring
472 (ethernet_private, ETH_Q0,
473 port_private->tx_ring_size[queue],
474 MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
475 (unsigned int) ethernet_private->
476 p_tx_desc_area_base[queue],
477 (unsigned int) ethernet_private->
478 p_tx_buffer_base[queue]) == false)
479 printf ("### Error initializing TX Ring\n");
482 /* "Allocate" setup RX rings */
483 for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
486 /* Meantime RX Ring are fixed - but must be configurable by user */
487 port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE;
488 size = (port_private->rx_ring_size[queue] *
489 RX_DESC_ALIGNED_SIZE);
490 ethernet_private->rx_desc_area_size[queue] = size;
492 /* first clear desc area completely */
493 memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
494 0, ethernet_private->rx_desc_area_size[queue]);
495 if ((ether_init_rx_desc_ring
496 (ethernet_private, ETH_Q0,
497 port_private->rx_ring_size[queue],
498 MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
499 (unsigned int) ethernet_private->
500 p_rx_desc_area_base[queue],
501 (unsigned int) ethernet_private->
502 p_rx_buffer_base[queue])) == false)
503 printf ("### Error initializing RX Ring\n");
506 eth_port_start (ethernet_private);
508 /* Set maximum receive buffer to 9700 bytes */
509 MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num),
512 (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num))
516 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
517 * disable the leaky bucket mechanism .
520 MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
521 MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
523 /* Check Link status on phy */
524 eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
525 if (!(phy_reg_data & 0x20)) {
527 if ((ethernet_phy_reset (port_num)) != true) {
528 printf ("$$ Warnning: No link on port %d \n",
532 eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
533 if (!(phy_reg_data & 0x20)) {
534 printf ("### Error: Phy is not active\n");
539 mv64360_eth_print_phy_status (dev);
541 port_private->eth_running = MAGIC_ETH_RUNNING;
546 static int mv64360_eth_free_tx_rings (struct eth_device *dev)
549 ETH_PORT_INFO *ethernet_private;
550 struct mv64360_eth_priv *port_private;
551 unsigned int port_num;
552 volatile ETH_TX_DESC *p_tx_curr_desc;
554 ethernet_private = (ETH_PORT_INFO *) dev->priv;
556 (struct mv64360_eth_priv *) ethernet_private->port_private;
557 port_num = port_private->port_num;
560 MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
564 DP (printf ("Clearing previously allocated TX queues... "));
565 for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
566 /* Free on TX rings */
567 for (p_tx_curr_desc =
568 ethernet_private->p_tx_desc_area_base[queue];
569 ((unsigned int) p_tx_curr_desc <= (unsigned int)
570 ethernet_private->p_tx_desc_area_base[queue] +
571 ethernet_private->tx_desc_area_size[queue]);
573 (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
574 TX_DESC_ALIGNED_SIZE)) {
575 /* this is inside for loop */
576 if (p_tx_curr_desc->return_info != 0) {
577 p_tx_curr_desc->return_info = 0;
578 DP (printf ("freed\n"));
581 DP (printf ("Done\n"));
586 static int mv64360_eth_free_rx_rings (struct eth_device *dev)
589 ETH_PORT_INFO *ethernet_private;
590 struct mv64360_eth_priv *port_private;
591 unsigned int port_num;
592 volatile ETH_RX_DESC *p_rx_curr_desc;
594 ethernet_private = (ETH_PORT_INFO *) dev->priv;
596 (struct mv64360_eth_priv *) ethernet_private->port_private;
597 port_num = port_private->port_num;
601 MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
605 DP (printf ("Clearing previously allocated RX queues... "));
606 for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
607 /* Free preallocated skb's on RX rings */
608 for (p_rx_curr_desc =
609 ethernet_private->p_rx_desc_area_base[queue];
610 (((unsigned int) p_rx_curr_desc <
611 ((unsigned int) ethernet_private->
612 p_rx_desc_area_base[queue] +
613 ethernet_private->rx_desc_area_size[queue])));
615 (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
616 RX_DESC_ALIGNED_SIZE)) {
617 if (p_rx_curr_desc->return_info != 0) {
618 p_rx_curr_desc->return_info = 0;
619 DP (printf ("freed\n"));
622 DP (printf ("Done\n"));
627 /**********************************************************************
630 * This function is used when closing the network device.
631 * It updates the hardware,
632 * release all memory that holds buffers and descriptors and release the IRQ.
633 * Input : a pointer to the device structure
634 * Output : zero if success , nonzero if fails
635 *********************************************************************/
637 int mv64360_eth_stop (struct eth_device *dev)
639 /* Disable all gigE address decoder */
640 MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
641 DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
642 mv64360_eth_real_stop (dev);
647 /* Helper function for mv64360_eth_stop */
649 static int mv64360_eth_real_stop (struct eth_device *dev)
651 ETH_PORT_INFO *ethernet_private;
652 struct mv64360_eth_priv *port_private;
653 unsigned int port_num;
655 ethernet_private = (ETH_PORT_INFO *) dev->priv;
657 (struct mv64360_eth_priv *) ethernet_private->port_private;
658 port_num = port_private->port_num;
661 mv64360_eth_free_tx_rings (dev);
662 mv64360_eth_free_rx_rings (dev);
664 eth_port_reset (ethernet_private->port_num);
665 /* Disable ethernet port interrupts */
666 MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
667 MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
668 /* Mask RX buffer and TX end interrupt */
669 MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0);
670 /* Mask phy and link status changes interrupts */
671 MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
672 MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH,
674 /* Print Network statistics */
675 #ifndef UPDATE_STATS_BY_SOFTWARE
677 * Print statistics (only if ethernet is running),
678 * then zero all the stats fields in memory
680 if (port_private->eth_running == MAGIC_ETH_RUNNING) {
681 port_private->eth_running = 0;
682 mv64360_eth_print_stat (dev);
684 memset (port_private->stats, 0, sizeof (struct net_device_stats));
686 DP (printf ("\nEthernet stopped ... \n"));
691 /**********************************************************************
692 * mv64360_eth_start_xmit
694 * This function is queues a packet in the Tx descriptor for
697 * Input : skb - a pointer to socket buffer
698 * dev - a pointer to the required port
700 * Output : zero upon success
701 **********************************************************************/
703 int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
706 ETH_PORT_INFO *ethernet_private;
707 struct mv64360_eth_priv *port_private;
709 ETH_FUNC_RET_STATUS status;
710 struct net_device_stats *stats;
711 ETH_FUNC_RET_STATUS release_result;
713 ethernet_private = (ETH_PORT_INFO *) dev->priv;
715 (struct mv64360_eth_priv *) ethernet_private->port_private;
717 stats = port_private->stats;
719 /* Update packet info data structure */
720 pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */
721 pkt_info.byte_cnt = dataSize;
722 pkt_info.buf_ptr = (unsigned int) dataPtr;
723 pkt_info.return_info = 0;
725 status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
726 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
727 printf ("Error on transmitting packet ..");
728 if (status == ETH_QUEUE_FULL)
729 printf ("ETH Queue is full. \n");
730 if (status == ETH_QUEUE_LAST_RESOURCE)
731 printf ("ETH Queue: using last available resource. \n");
735 /* Update statistics and start of transmittion time */
736 stats->tx_bytes += dataSize;
739 /* Check if packet(s) is(are) transmitted correctly (release everything) */
742 eth_tx_return_desc (ethernet_private, ETH_Q0,
744 switch (release_result) {
746 DP (printf ("descriptor released\n"));
747 if (pkt_info.cmd_sts & BIT0) {
748 printf ("Error in TX\n");
754 DP (printf ("transmission still in process\n"));
758 printf ("routine can not access Tx desc ring\n");
762 DP (printf ("the routine has nothing to release\n"));
764 default: /* should not happen */
767 } while (release_result == ETH_OK);
770 return 0; /* success */
772 return 1; /* Failed - higher layers will free the skb */
775 /**********************************************************************
776 * mv64360_eth_receive
778 * This function is forward packets that are received from the port's
779 * queues toward kernel core or FastRoute them to another interface.
781 * Input : dev - a pointer to the required interface
782 * max - maximum number to receive (0 means unlimted)
784 * Output : number of served packets
785 **********************************************************************/
787 int mv64360_eth_receive (struct eth_device *dev)
789 ETH_PORT_INFO *ethernet_private;
790 struct mv64360_eth_priv *port_private;
792 struct net_device_stats *stats;
795 ethernet_private = (ETH_PORT_INFO *) dev->priv;
797 (struct mv64360_eth_priv *) ethernet_private->port_private;
798 stats = port_private->stats;
800 while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
804 if (pkt_info.byte_cnt != 0) {
805 printf ("%s: Received %d byte Packet @ 0x%x\n",
806 __FUNCTION__, pkt_info.byte_cnt,
810 /* Update statistics. Note byte count includes 4 byte CRC count */
812 stats->rx_bytes += pkt_info.byte_cnt;
815 * In case received a packet without first / last bits on OR the error
816 * summary bit is on, the packets needs to be dropeed.
819 cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
820 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
821 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
824 printf ("Received packet spread on multiple descriptors\n");
826 /* Is this caused by an error ? */
827 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
831 /* free these descriptors again without forwarding them to the higher layers */
832 pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
833 pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
835 if (eth_rx_return_buff
836 (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
837 printf ("Error while returning the RX Desc to Ring\n");
839 DP (printf ("RX Desc returned to Ring\n"));
841 /* /free these descriptors again */
844 /* !!! call higher layer processing */
846 printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
848 /* let the upper layer handle the packet */
849 NetReceive ((uchar *) pkt_info.buf_ptr,
850 (int) pkt_info.byte_cnt);
852 /* **************************************************************** */
853 /* free descriptor */
854 pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
855 pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
857 ("RX: pkt_info.buf_ptr = %x\n",
859 if (eth_rx_return_buff
860 (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
861 printf ("Error while returning the RX Desc to Ring\n");
863 DP (printf ("RX Desc returned to Ring\n"));
866 /* **************************************************************** */
870 mv64360_eth_get_stats (dev); /* update statistics */
874 /**********************************************************************
875 * mv64360_eth_get_stats
877 * Returns a pointer to the interface statistics.
879 * Input : dev - a pointer to the required interface
881 * Output : a pointer to the interface's statistics
882 **********************************************************************/
884 static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev)
886 ETH_PORT_INFO *ethernet_private;
887 struct mv64360_eth_priv *port_private;
889 ethernet_private = (ETH_PORT_INFO *) dev->priv;
891 (struct mv64360_eth_priv *) ethernet_private->port_private;
893 mv64360_eth_update_stat (dev);
895 return port_private->stats;
899 /**********************************************************************
900 * mv64360_eth_update_stat
902 * Update the statistics structure in the private data structure
904 * Input : pointer to ethernet interface network device structure
906 **********************************************************************/
908 static void mv64360_eth_update_stat (struct eth_device *dev)
910 ETH_PORT_INFO *ethernet_private;
911 struct mv64360_eth_priv *port_private;
912 struct net_device_stats *stats;
914 ethernet_private = (ETH_PORT_INFO *) dev->priv;
916 (struct mv64360_eth_priv *) ethernet_private->port_private;
917 stats = port_private->stats;
919 /* These are false updates */
920 stats->rx_packets += (unsigned long)
921 eth_read_mib_counter (ethernet_private->port_num,
922 ETH_MIB_GOOD_FRAMES_RECEIVED);
923 stats->tx_packets += (unsigned long)
924 eth_read_mib_counter (ethernet_private->port_num,
925 ETH_MIB_GOOD_FRAMES_SENT);
926 stats->rx_bytes += (unsigned long)
927 eth_read_mib_counter (ethernet_private->port_num,
928 ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
930 * Ideally this should be as follows -
932 * stats->rx_bytes += stats->rx_bytes +
933 * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
934 * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
936 * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
937 * is just a dummy read for proper work of the GigE port
939 (void)eth_read_mib_counter (ethernet_private->port_num,
940 ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
941 stats->tx_bytes += (unsigned long)
942 eth_read_mib_counter (ethernet_private->port_num,
943 ETH_MIB_GOOD_OCTETS_SENT_LOW);
944 (void)eth_read_mib_counter (ethernet_private->port_num,
945 ETH_MIB_GOOD_OCTETS_SENT_HIGH);
946 stats->rx_errors += (unsigned long)
947 eth_read_mib_counter (ethernet_private->port_num,
948 ETH_MIB_MAC_RECEIVE_ERROR);
950 /* Rx dropped is for received packet with CRC error */
952 (unsigned long) eth_read_mib_counter (ethernet_private->
954 ETH_MIB_BAD_CRC_EVENT);
955 stats->multicast += (unsigned long)
956 eth_read_mib_counter (ethernet_private->port_num,
957 ETH_MIB_MULTICAST_FRAMES_RECEIVED);
959 (unsigned long) eth_read_mib_counter (ethernet_private->
962 (unsigned long) eth_read_mib_counter (ethernet_private->
964 ETH_MIB_LATE_COLLISION);
965 /* detailed rx errors */
966 stats->rx_length_errors +=
967 (unsigned long) eth_read_mib_counter (ethernet_private->
969 ETH_MIB_UNDERSIZE_RECEIVED)
971 (unsigned long) eth_read_mib_counter (ethernet_private->
973 ETH_MIB_OVERSIZE_RECEIVED);
974 /* detailed tx errors */
977 #ifndef UPDATE_STATS_BY_SOFTWARE
978 /**********************************************************************
979 * mv64360_eth_print_stat
981 * Update the statistics structure in the private data structure
983 * Input : pointer to ethernet interface network device structure
985 **********************************************************************/
987 static void mv64360_eth_print_stat (struct eth_device *dev)
989 ETH_PORT_INFO *ethernet_private;
990 struct mv64360_eth_priv *port_private;
991 struct net_device_stats *stats;
993 ethernet_private = (ETH_PORT_INFO *) dev->priv;
995 (struct mv64360_eth_priv *) ethernet_private->port_private;
996 stats = port_private->stats;
998 /* These are false updates */
999 printf ("\n### Network statistics: ###\n");
1000 printf ("--------------------------\n");
1001 printf (" Packets received: %ld\n", stats->rx_packets);
1002 printf (" Packets send: %ld\n", stats->tx_packets);
1003 printf (" Received bytes: %ld\n", stats->rx_bytes);
1004 printf (" Send bytes: %ld\n", stats->tx_bytes);
1005 if (stats->rx_errors != 0)
1006 printf (" Rx Errors: %ld\n",
1008 if (stats->rx_dropped != 0)
1009 printf (" Rx dropped (CRC Errors): %ld\n",
1011 if (stats->multicast != 0)
1012 printf (" Rx mulicast frames: %ld\n",
1014 if (stats->collisions != 0)
1015 printf (" No. of collisions: %ld\n",
1017 if (stats->rx_length_errors != 0)
1018 printf (" Rx length errors: %ld\n",
1019 stats->rx_length_errors);
1023 /**************************************************************************
1024 *network_start - Network Kick Off Routine UBoot
1027 **************************************************************************/
1029 bool db64360_eth_start (struct eth_device *dev)
1031 return (mv64360_eth_open (dev)); /* calls real open */
1034 /*************************************************************************
1035 **************************************************************************
1036 **************************************************************************
1037 * The second part is the low level driver of the gigE ethernet ports. *
1038 **************************************************************************
1039 **************************************************************************
1040 *************************************************************************/
1042 * based on Linux code
1043 * arch/powerpc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports
1044 * Copyright (C) 2002 rabeeh@galileo.co.il
1046 * This program is free software; you can redistribute it and/or
1047 * modify it under the terms of the GNU General Public License
1048 * as published by the Free Software Foundation; either version 2
1049 * of the License, or (at your option) any later version.
1051 * This program is distributed in the hope that it will be useful,
1052 * but WITHOUT ANY WARRANTY; without even the implied warranty of
1053 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1054 * GNU General Public License for more details.
1056 * You should have received a copy of the GNU General Public License
1057 * along with this program; if not, write to the Free Software
1058 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
1062 /********************************************************************************
1063 * Marvell's Gigabit Ethernet controller low level driver
1066 * This file introduce low level API to Marvell's Gigabit Ethernet
1067 * controller. This Gigabit Ethernet Controller driver API controls
1068 * 1) Operations (i.e. port init, start, reset etc').
1069 * 2) Data flow (i.e. port send, receive etc').
1070 * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
1072 * This struct includes user configuration information as well as
1073 * driver internal data needed for its operations.
1075 * Supported Features:
1076 * - This low level driver is OS independent. Allocating memory for
1077 * the descriptor rings and buffers are not within the scope of
1079 * - The user is free from Rx/Tx queue managing.
1080 * - This low level driver introduce functionality API that enable
1081 * the to operate Marvell's Gigabit Ethernet Controller in a
1083 * - Simple Gigabit Ethernet port operation API.
1084 * - Simple Gigabit Ethernet port data flow API.
1085 * - Data flow and operation API support per queue functionality.
1086 * - Support cached descriptors for better performance.
1087 * - Enable access to all four DRAM banks and internal SRAM memory
1089 * - PHY access and control API.
1090 * - Port control register configuration API.
1091 * - Full control over Unicast and Multicast MAC configurations.
1095 * Initialization phase
1096 * This phase complete the initialization of the ETH_PORT_INFO
1098 * User information regarding port configuration has to be set
1099 * prior to calling the port initialization routine. For example,
1100 * the user has to assign the port_phy_addr field which is board
1101 * depended parameter.
1102 * In this phase any port Tx/Rx activity is halted, MIB counters
1103 * are cleared, PHY address is set according to user parameter and
1104 * access to DRAM and internal SRAM memory spaces.
1106 * Driver ring initialization
1107 * Allocating memory for the descriptor rings and buffers is not
1108 * within the scope of this driver. Thus, the user is required to
1109 * allocate memory for the descriptors ring and buffers. Those
1110 * memory parameters are used by the Rx and Tx ring initialization
1111 * routines in order to curve the descriptor linked list in a form
1113 * Note: Pay special attention to alignment issues when using
1114 * cached descriptors/buffers. In this phase the driver store
1115 * information in the ETH_PORT_INFO struct regarding each queue
1119 * This phase prepares the Ethernet port for Rx and Tx activity.
1120 * It uses the information stored in the ETH_PORT_INFO struct to
1121 * initialize the various port registers.
1124 * All packet references to/from the driver are done using PKT_INFO
1126 * This struct is a unified struct used with Rx and Tx operations.
1127 * This way the user is not required to be familiar with neither
1128 * Tx nor Rx descriptors structures.
1129 * The driver's descriptors rings are management by indexes.
1130 * Those indexes controls the ring resources and used to indicate
1131 * a SW resource error:
1133 * This index points to the current available resource for use. For
1134 * example in Rx process this index will point to the descriptor
1135 * that will be passed to the user upon calling the receive routine.
1136 * In Tx process, this index will point to the descriptor
1137 * that will be assigned with the user packet info and transmitted.
1139 * This index points to the descriptor that need to restore its
1140 * resources. For example in Rx process, using the Rx buffer return
1141 * API will attach the buffer returned in packet info to the
1142 * descriptor pointed by 'used'. In Tx process, using the Tx
1143 * descriptor return will merely return the user packet info with
1144 * the command status of the transmitted buffer pointed by the
1145 * 'used' index. Nevertheless, it is essential to use this routine
1146 * to update the 'used' index.
1148 * This index supports Tx Scatter-Gather. It points to the first
1149 * descriptor of a packet assembled of multiple buffers. For example
1150 * when in middle of Such packet we have a Tx resource error the
1151 * 'curr' index get the value of 'first' to indicate that the ring
1152 * returned to its state before trying to transmit this packet.
1154 * Receive operation:
1155 * The eth_port_receive API set the packet information struct,
1156 * passed by the caller, with received information from the
1157 * 'current' SDMA descriptor.
1158 * It is the user responsibility to return this resource back
1159 * to the Rx descriptor ring to enable the reuse of this source.
1160 * Return Rx resource is done using the eth_rx_return_buff API.
1162 * Transmit operation:
1163 * The eth_port_send API supports Scatter-Gather which enables to
1164 * send a packet spanned over multiple buffers. This means that
1165 * for each packet info structure given by the user and put into
1166 * the Tx descriptors ring, will be transmitted only if the 'LAST'
1167 * bit will be set in the packet info command status field. This
1168 * API also consider restriction regarding buffer alignments and
1170 * The user must return a Tx resource after ensuring the buffer
1171 * has been transmitted to enable the Tx ring indexes to update.
1174 * This device is on-board. No jumper diagram is necessary.
1176 * EXTERNAL INTERFACE
1178 * Prior to calling the initialization routine eth_port_init() the user
1179 * must set the following fields under ETH_PORT_INFO struct:
1180 * port_num User Ethernet port number.
1181 * port_phy_addr User PHY address of Ethernet port.
1182 * port_mac_addr[6] User defined port MAC address.
1183 * port_config User port configuration value.
1184 * port_config_extend User port config extend value.
1185 * port_sdma_config User port SDMA config value.
1186 * port_serial_control User port serial control value.
1187 * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr.
1188 * *port_private User scratch pad for user specific data structures.
1190 * This driver introduce a set of default values:
1191 * PORT_CONFIG_VALUE Default port configuration value
1192 * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value
1193 * PORT_SDMA_CONFIG_VALUE Default sdma control value
1194 * PORT_SERIAL_CONTROL_VALUE Default port serial control value
1196 * This driver data flow is done using the PKT_INFO struct which is
1197 * a unified struct for Rx and Tx operations:
1198 * byte_cnt Tx/Rx descriptor buffer byte count.
1199 * l4i_chk CPU provided TCP Checksum. For Tx operation only.
1200 * cmd_sts Tx/Rx descriptor command status.
1201 * buf_ptr Tx/Rx descriptor buffer pointer.
1202 * return_info Tx/Rx user resource return information.
1205 * EXTERNAL SUPPORT REQUIREMENTS
1207 * This driver requires the following external support:
1209 * D_CACHE_FLUSH_LINE (address, address offset)
1211 * This macro applies assembly code to flush and invalidate cache
1213 * address - address base.
1214 * address offset - address offset
1219 * This macro applies assembly code to flush the CPU pipeline.
1221 *******************************************************************************/
1225 /* SDMA command macros */
1226 #define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
1227 MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
1229 #define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
1230 MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
1231 (1 << (8 + tx_queue)))
1233 #define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
1234 MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
1236 #define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
1237 MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
1239 #define CURR_RFD_GET(p_curr_desc, queue) \
1240 ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
1242 #define CURR_RFD_SET(p_curr_desc, queue) \
1243 (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
1245 #define USED_RFD_GET(p_used_desc, queue) \
1246 ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
1248 #define USED_RFD_SET(p_used_desc, queue)\
1249 (p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
1252 #define CURR_TFD_GET(p_curr_desc, queue) \
1253 ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
1255 #define CURR_TFD_SET(p_curr_desc, queue) \
1256 (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
1258 #define USED_TFD_GET(p_used_desc, queue) \
1259 ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
1261 #define USED_TFD_SET(p_used_desc, queue) \
1262 (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
1264 #define FIRST_TFD_GET(p_first_desc, queue) \
1265 ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
1267 #define FIRST_TFD_SET(p_first_desc, queue) \
1268 (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
1271 /* Macros that save access to desc in order to find next desc pointer */
1272 #define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
1274 #define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
1276 #define LINK_UP_TIMEOUT 100000
1277 #define PHY_BUSY_TIMEOUT 10000000
1282 static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
1283 static int ethernet_phy_get (ETH_PORT eth_port_num);
1285 /* Ethernet Port routines */
1286 static void eth_set_access_control (ETH_PORT eth_port_num,
1287 ETH_WIN_PARAM * param);
1288 static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
1289 ETH_QUEUE queue, int option);
1291 static bool eth_port_smc_addr (ETH_PORT eth_port_num,
1292 unsigned char mc_byte,
1293 ETH_QUEUE queue, int option);
1294 static bool eth_port_omc_addr (ETH_PORT eth_port_num,
1296 ETH_QUEUE queue, int option);
1299 static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
1302 void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
1305 typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
1306 u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
1309 u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
1311 if (enable & (1 << bank))
1314 result = MV_REG_READ (MV64360_CS_0_BASE_ADDR);
1316 result = MV_REG_READ (MV64360_CS_1_BASE_ADDR);
1318 result = MV_REG_READ (MV64360_CS_2_BASE_ADDR);
1320 result = MV_REG_READ (MV64360_CS_3_BASE_ADDR);
1321 result &= 0x0000ffff;
1322 result = result << 16;
1326 u32 mv_get_dram_bank_size (MEMORY_BANK bank)
1329 u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
1331 if (enable & (1 << bank))
1334 result = MV_REG_READ (MV64360_CS_0_SIZE);
1336 result = MV_REG_READ (MV64360_CS_1_SIZE);
1338 result = MV_REG_READ (MV64360_CS_2_SIZE);
1340 result = MV_REG_READ (MV64360_CS_3_SIZE);
1342 result &= 0x0000ffff;
1343 result = result << 16;
1347 u32 mv_get_internal_sram_base (void)
1351 result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR);
1352 result &= 0x0000ffff;
1353 result = result << 16;
1357 /*******************************************************************************
1358 * eth_port_init - Initialize the Ethernet port driver
1361 * This function prepares the ethernet port to start its activity:
1362 * 1) Completes the ethernet port driver struct initialization toward port
1364 * 2) Resets the device to a quiescent state in case of warm reboot.
1365 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1366 * 4) Clean MAC tables. The reset status of those tables is unknown.
1367 * 5) Set PHY address.
1368 * Note: Call this routine prior to eth_port_start routine and after setting
1369 * user values in the user fields of Ethernet port control struct (i.e.
1373 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
1381 *******************************************************************************/
1382 static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
1385 ETH_WIN_PARAM win_param;
1387 p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
1388 p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
1389 p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
1390 p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
1392 p_eth_port_ctrl->port_rx_queue_command = 0;
1393 p_eth_port_ctrl->port_tx_queue_command = 0;
1395 /* Zero out SW structs */
1396 for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
1397 CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
1398 USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
1399 p_eth_port_ctrl->rx_resource_err[queue] = false;
1402 for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
1403 CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
1404 USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
1405 FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
1406 p_eth_port_ctrl->tx_resource_err[queue] = false;
1409 eth_port_reset (p_eth_port_ctrl->port_num);
1411 /* Set access parameters for DRAM bank 0 */
1412 win_param.win = ETH_WIN0; /* Use Ethernet window 0 */
1413 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1414 win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */
1415 #ifndef CONFIG_NOT_COHERENT_CACHE
1416 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1418 win_param.high_addr = 0;
1420 win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
1421 win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */
1422 if (win_param.size == 0)
1423 win_param.enable = 0;
1425 win_param.enable = 1; /* Enable the access */
1426 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1428 /* Set the access control for address window (EPAPR) READ & WRITE */
1429 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1431 /* Set access parameters for DRAM bank 1 */
1432 win_param.win = ETH_WIN1; /* Use Ethernet window 1 */
1433 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1434 win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */
1435 #ifndef CONFIG_NOT_COHERENT_CACHE
1436 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1438 win_param.high_addr = 0;
1440 win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
1441 win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */
1442 if (win_param.size == 0)
1443 win_param.enable = 0;
1445 win_param.enable = 1; /* Enable the access */
1446 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1448 /* Set the access control for address window (EPAPR) READ & WRITE */
1449 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1451 /* Set access parameters for DRAM bank 2 */
1452 win_param.win = ETH_WIN2; /* Use Ethernet window 2 */
1453 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1454 win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */
1455 #ifndef CONFIG_NOT_COHERENT_CACHE
1456 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1458 win_param.high_addr = 0;
1460 win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
1461 win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */
1462 if (win_param.size == 0)
1463 win_param.enable = 0;
1465 win_param.enable = 1; /* Enable the access */
1466 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1468 /* Set the access control for address window (EPAPR) READ & WRITE */
1469 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1471 /* Set access parameters for DRAM bank 3 */
1472 win_param.win = ETH_WIN3; /* Use Ethernet window 3 */
1473 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1474 win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */
1475 #ifndef CONFIG_NOT_COHERENT_CACHE
1476 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1478 win_param.high_addr = 0;
1480 win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
1481 win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */
1482 if (win_param.size == 0)
1483 win_param.enable = 0;
1485 win_param.enable = 1; /* Enable the access */
1486 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1488 /* Set the access control for address window (EPAPR) READ & WRITE */
1489 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1491 /* Set access parameters for Internal SRAM */
1492 win_param.win = ETH_WIN4; /* Use Ethernet window 0 */
1493 win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */
1494 win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
1495 win_param.high_addr = 0;
1496 win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */
1497 win_param.size = MV64360_INTERNAL_SRAM_SIZE; /* Get bank size */
1498 win_param.enable = 1; /* Enable the access */
1499 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1501 /* Set the access control for address window (EPAPR) READ & WRITE */
1502 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1504 eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
1506 ethernet_phy_set (p_eth_port_ctrl->port_num,
1507 p_eth_port_ctrl->port_phy_addr);
1513 /*******************************************************************************
1514 * eth_port_start - Start the Ethernet port activity.
1517 * This routine prepares the Ethernet port for Rx and Tx activity:
1518 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1519 * has been initialized a descriptor's ring (using ether_init_tx_desc_ring
1520 * for Tx and ether_init_rx_desc_ring for Rx)
1521 * 2. Initialize and enable the Ethernet configuration port by writing to
1522 * the port's configuration and command registers.
1523 * 3. Initialize and enable the SDMA by writing to the SDMA's
1524 * configuration and command registers.
1525 * After completing these steps, the ethernet port SDMA can starts to
1526 * perform Rx and Tx activities.
1528 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1529 * to calling this function (use ether_init_tx_desc_ring for Tx queues and
1530 * ether_init_rx_desc_ring for Rx queues).
1533 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
1536 * Ethernet port is ready to receive and transmit.
1539 * false if the port PHY is not up.
1542 *******************************************************************************/
1543 static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
1546 volatile ETH_TX_DESC *p_tx_curr_desc;
1547 volatile ETH_RX_DESC *p_rx_curr_desc;
1548 unsigned int phy_reg_data;
1549 ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
1552 /* Assignment of Tx CTRP of given queue */
1553 for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
1554 CURR_TFD_GET (p_tx_curr_desc, queue);
1555 MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
1558 ((unsigned int) p_tx_curr_desc));
1562 /* Assignment of Rx CRDP of given queue */
1563 for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
1564 CURR_RFD_GET (p_rx_curr_desc, queue);
1565 MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
1568 ((unsigned int) p_rx_curr_desc));
1570 if (p_rx_curr_desc != NULL)
1571 /* Add the assigned Ethernet address to the port's address table */
1572 eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
1573 p_eth_port_ctrl->port_mac_addr,
1577 /* Assign port configuration and command. */
1578 MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
1579 p_eth_port_ctrl->port_config);
1581 MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
1582 p_eth_port_ctrl->port_config_extend);
1584 MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
1585 p_eth_port_ctrl->port_serial_control);
1587 MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
1588 ETH_SERIAL_PORT_ENABLE);
1590 /* Assign port SDMA configuration */
1591 MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
1592 p_eth_port_ctrl->port_sdma_config);
1594 MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
1595 (eth_port_num), 0x3fffffff);
1596 MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
1597 (eth_port_num), 0x03fffcff);
1598 /* Turn off the port/queue bandwidth limitation */
1599 MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
1601 /* Enable port Rx. */
1602 MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
1603 p_eth_port_ctrl->port_rx_queue_command);
1605 /* Check if link is up */
1606 eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
1608 if (!(phy_reg_data & 0x20))
1614 /*******************************************************************************
1615 * eth_port_uc_addr_set - This function Set the port Unicast address.
1618 * This function Set the port Ethernet MAC address.
1621 * ETH_PORT eth_port_num Port number.
1622 * char * p_addr Address to be set
1623 * ETH_QUEUE queue Rx queue number for this MAC address.
1626 * Set MAC address low and high registers. also calls eth_port_uc_addr()
1627 * To set the unicast table with the proper information.
1632 *******************************************************************************/
1633 static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
1634 unsigned char *p_addr, ETH_QUEUE queue)
1639 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1640 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
1641 (p_addr[2] << 8) | (p_addr[3] << 0);
1643 MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
1644 MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
1646 /* Accept frames of this address */
1647 eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
1652 /*******************************************************************************
1653 * eth_port_uc_addr - This function Set the port unicast address table
1656 * This function locates the proper entry in the Unicast table for the
1657 * specified MAC nibble and sets its properties according to function
1661 * ETH_PORT eth_port_num Port number.
1662 * unsigned char uc_nibble Unicast MAC Address last nibble.
1663 * ETH_QUEUE queue Rx queue number for this MAC address.
1664 * int option 0 = Add, 1 = remove address.
1667 * This function add/removes MAC addresses from the port unicast address
1671 * true is output succeeded.
1672 * false if option parameter is invalid.
1674 *******************************************************************************/
1675 static bool eth_port_uc_addr (ETH_PORT eth_port_num,
1676 unsigned char uc_nibble,
1677 ETH_QUEUE queue, int option)
1679 unsigned int unicast_reg;
1680 unsigned int tbl_offset;
1681 unsigned int reg_offset;
1683 /* Locate the Unicast table entry */
1684 uc_nibble = (0xf & uc_nibble);
1685 tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
1686 reg_offset = uc_nibble % 4; /* Entry offset within the above register */
1689 case REJECT_MAC_ADDR:
1690 /* Clear accepts frame bit at specified unicast DA table entry */
1692 MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
1696 unicast_reg &= (0x0E << (8 * reg_offset));
1698 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
1700 + tbl_offset), unicast_reg);
1703 case ACCEPT_MAC_ADDR:
1704 /* Set accepts frame bit at unicast DA filter table entry */
1706 MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
1710 unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
1712 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
1714 + tbl_offset), unicast_reg);
1725 /*******************************************************************************
1726 * eth_port_mc_addr - Multicast address settings.
1729 * This API controls the MV device MAC multicast support.
1730 * The MV device supports multicast using two tables:
1731 * 1) Special Multicast Table for MAC addresses of the form
1732 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
1733 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1734 * Table entries in the DA-Filter table.
1735 * In this case, the function calls eth_port_smc_addr() routine to set the
1736 * Special Multicast Table.
1737 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
1738 * is used as an index to the Other Multicast Table entries in the
1740 * In this case, the function calculates the CRC-8bit value and calls
1741 * eth_port_omc_addr() routine to set the Other Multicast Table.
1743 * ETH_PORT eth_port_num Port number.
1744 * unsigned char *p_addr Unicast MAC Address.
1745 * ETH_QUEUE queue Rx queue number for this MAC address.
1746 * int option 0 = Add, 1 = remove address.
1752 * true is output succeeded.
1753 * false if add_address_table_entry( ) failed.
1755 *******************************************************************************/
1756 static void eth_port_mc_addr (ETH_PORT eth_port_num,
1757 unsigned char *p_addr,
1758 ETH_QUEUE queue, int option)
1762 unsigned char crc_result = 0;
1768 if ((p_addr[0] == 0x01) &&
1769 (p_addr[1] == 0x00) &&
1770 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00))
1772 eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
1774 /* Calculate CRC-8 out of the given address */
1775 mac_h = (p_addr[0] << 8) | (p_addr[1]);
1776 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
1777 (p_addr[4] << 8) | (p_addr[5] << 0);
1779 for (i = 0; i < 32; i++)
1780 mac_array[i] = (mac_l >> i) & 0x1;
1781 for (i = 32; i < 48; i++)
1782 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
1785 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
1786 mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
1787 mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
1788 mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
1789 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
1790 mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
1791 mac_array[6] ^ mac_array[0];
1793 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
1794 mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
1795 mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
1796 mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
1797 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
1798 mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
1799 mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
1800 mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
1801 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
1804 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
1805 mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
1806 mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
1807 mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
1808 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
1809 mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
1810 mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
1811 mac_array[2] ^ mac_array[1] ^ mac_array[0];
1813 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
1814 mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
1815 mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
1816 mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
1817 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
1818 mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
1819 mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
1820 mac_array[2] ^ mac_array[1];
1822 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
1823 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
1824 mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
1825 mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
1826 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
1827 mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
1828 mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
1831 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
1832 mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
1833 mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
1834 mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
1835 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
1836 mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
1837 mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
1840 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
1841 mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
1842 mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
1843 mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
1844 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
1845 mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
1846 mac_array[6] ^ mac_array[5] ^ mac_array[4];
1848 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
1849 mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
1850 mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
1851 mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
1852 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
1853 mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
1854 mac_array[6] ^ mac_array[5];
1856 for (i = 0; i < 8; i++)
1857 crc_result = crc_result | (crc[i] << i);
1859 eth_port_omc_addr (eth_port_num, crc_result, queue, option);
1864 /*******************************************************************************
1865 * eth_port_smc_addr - Special Multicast address settings.
1868 * This routine controls the MV device special MAC multicast support.
1869 * The Special Multicast Table for MAC addresses supports MAC of the form
1870 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
1871 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1872 * Table entries in the DA-Filter table.
1873 * This function set the Special Multicast Table appropriate entry
1874 * according to the argument given.
1877 * ETH_PORT eth_port_num Port number.
1878 * unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits).
1879 * ETH_QUEUE queue Rx queue number for this MAC address.
1880 * int option 0 = Add, 1 = remove address.
1886 * true is output succeeded.
1887 * false if option parameter is invalid.
1889 *******************************************************************************/
1890 static bool eth_port_smc_addr (ETH_PORT eth_port_num,
1891 unsigned char mc_byte,
1892 ETH_QUEUE queue, int option)
1894 unsigned int smc_table_reg;
1895 unsigned int tbl_offset;
1896 unsigned int reg_offset;
1898 /* Locate the SMC table entry */
1899 tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */
1900 reg_offset = mc_byte % 4; /* Entry offset within the above register */
1904 case REJECT_MAC_ADDR:
1905 /* Clear accepts frame bit at specified Special DA table entry */
1907 MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1908 smc_table_reg &= (0x0E << (8 * reg_offset));
1910 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
1913 case ACCEPT_MAC_ADDR:
1914 /* Set accepts frame bit at specified Special DA table entry */
1916 MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1917 smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
1919 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
1928 /*******************************************************************************
1929 * eth_port_omc_addr - Multicast address settings.
1932 * This routine controls the MV device Other MAC multicast support.
1933 * The Other Multicast Table is used for multicast of another type.
1934 * A CRC-8bit is used as an index to the Other Multicast Table entries
1935 * in the DA-Filter table.
1936 * The function gets the CRC-8bit value from the calling routine and
1937 * set the Other Multicast Table appropriate entry according to the
1938 * CRC-8 argument given.
1941 * ETH_PORT eth_port_num Port number.
1942 * unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
1943 * ETH_QUEUE queue Rx queue number for this MAC address.
1944 * int option 0 = Add, 1 = remove address.
1950 * true is output succeeded.
1951 * false if option parameter is invalid.
1953 *******************************************************************************/
1954 static bool eth_port_omc_addr (ETH_PORT eth_port_num,
1956 ETH_QUEUE queue, int option)
1958 unsigned int omc_table_reg;
1959 unsigned int tbl_offset;
1960 unsigned int reg_offset;
1962 /* Locate the OMC table entry */
1963 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
1964 reg_offset = crc8 % 4; /* Entry offset within the above register */
1968 case REJECT_MAC_ADDR:
1969 /* Clear accepts frame bit at specified Other DA table entry */
1971 MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1972 omc_table_reg &= (0x0E << (8 * reg_offset));
1974 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
1977 case ACCEPT_MAC_ADDR:
1978 /* Set accepts frame bit at specified Other DA table entry */
1980 MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1981 omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
1983 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
1993 /*******************************************************************************
1994 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
1997 * Go through all the DA filter tables (Unicast, Special Multicast & Other
1998 * Multicast) and set each entry to 0.
2001 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2004 * Multicast and Unicast packets are rejected.
2009 *******************************************************************************/
2010 static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
2014 /* Clear DA filter unicast table (Ex_dFUT) */
2015 for (table_index = 0; table_index <= 0xC; table_index += 4)
2016 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
2017 (eth_port_num) + table_index), 0);
2019 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2020 /* Clear DA filter special multicast table (Ex_dFSMT) */
2021 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
2022 /* Clear DA filter other multicast table (Ex_dFOMT) */
2023 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
2027 /*******************************************************************************
2028 * eth_clear_mib_counters - Clear all MIB counters
2031 * This function clears all MIB counters of a specific ethernet port.
2032 * A read from the MIB counter will reset the counter.
2035 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2038 * After reading all MIB counters, the counters resets.
2041 * MIB counter value.
2043 *******************************************************************************/
2044 static void eth_clear_mib_counters (ETH_PORT eth_port_num)
2048 /* Perform dummy reads from MIB counters */
2049 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2051 (void)MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE
2052 (eth_port_num) + i));
2058 /*******************************************************************************
2059 * eth_read_mib_counter - Read a MIB counter
2062 * This function reads a MIB counter of a specific ethernet port.
2063 * NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
2064 * following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
2065 * register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
2066 * ETH_MIB_GOOD_OCTETS_SENT_HIGH
2069 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2070 * unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros).
2073 * After reading the MIB counter, the counter resets.
2076 * MIB counter value.
2078 *******************************************************************************/
2079 unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
2080 unsigned int mib_offset)
2082 return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num)
2086 /*******************************************************************************
2087 * ethernet_phy_set - Set the ethernet port PHY address.
2090 * This routine set the ethernet port PHY address according to given
2094 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2097 * Set PHY Address Register with given PHY address parameter.
2102 *******************************************************************************/
2103 static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
2105 unsigned int reg_data;
2107 reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
2109 reg_data &= ~(0x1F << (5 * eth_port_num));
2110 reg_data |= (phy_addr << (5 * eth_port_num));
2112 MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data);
2117 /*******************************************************************************
2118 * ethernet_phy_get - Get the ethernet port PHY address.
2121 * This routine returns the given ethernet port PHY address.
2124 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2132 *******************************************************************************/
2133 static int ethernet_phy_get (ETH_PORT eth_port_num)
2135 unsigned int reg_data;
2137 reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
2139 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2142 /*******************************************************************************
2143 * ethernet_phy_reset - Reset Ethernet port PHY.
2146 * This routine utilize the SMI interface to reset the ethernet port PHY.
2147 * The routine waits until the link is up again or link up is timeout.
2150 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2153 * The ethernet port PHY renew its link.
2158 *******************************************************************************/
2159 static bool ethernet_phy_reset (ETH_PORT eth_port_num)
2161 unsigned int time_out = 50;
2162 unsigned int phy_reg_data;
2165 eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
2166 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2167 eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
2169 /* Poll on the PHY LINK */
2171 eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
2173 if (time_out-- == 0)
2176 while (!(phy_reg_data & 0x20));
2181 /*******************************************************************************
2182 * eth_port_reset - Reset Ethernet port
2185 * This routine resets the chip by aborting any SDMA engine activity and
2186 * clearing the MIB counters. The Receiver and the Transmit unit are in
2187 * idle state after this command is performed and the port is disabled.
2190 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2193 * Channel activity is halted.
2198 *******************************************************************************/
2199 static void eth_port_reset (ETH_PORT eth_port_num)
2201 unsigned int reg_data;
2203 /* Stop Tx port activity. Check port Tx activity. */
2205 MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
2208 if (reg_data & 0xFF) {
2209 /* Issue stop command for active channels only */
2210 MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
2211 (eth_port_num), (reg_data << 8));
2213 /* Wait for all Tx activity to terminate. */
2215 /* Check port cause register that all Tx queues are stopped */
2218 (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
2221 while (reg_data & 0xFF);
2224 /* Stop Rx port activity. Check port Rx activity. */
2226 MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
2229 if (reg_data & 0xFF) {
2230 /* Issue stop command for active channels only */
2231 MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
2232 (eth_port_num), (reg_data << 8));
2234 /* Wait for all Rx activity to terminate. */
2236 /* Check port cause register that all Rx queues are stopped */
2239 (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
2242 while (reg_data & 0xFF);
2246 /* Clear all MIB counters */
2247 eth_clear_mib_counters (eth_port_num);
2249 /* Reset the Enable bit in the Configuration Register */
2251 MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG
2253 reg_data &= ~ETH_SERIAL_PORT_ENABLE;
2254 MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
2260 #if 0 /* Not needed here */
2261 /*******************************************************************************
2262 * ethernet_set_config_reg - Set specified bits in configuration register.
2265 * This function sets specified bits in the given ethernet
2266 * configuration register.
2269 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2270 * unsigned int value 32 bit value.
2273 * The set bits in the value parameter are set in the configuration
2279 *******************************************************************************/
2280 static void ethernet_set_config_reg (ETH_PORT eth_port_num,
2283 unsigned int eth_config_reg;
2286 MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num));
2287 eth_config_reg |= value;
2288 MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
2296 /*******************************************************************************
2297 * ethernet_reset_config_reg - Reset specified bits in configuration register.
2300 * This function resets specified bits in the given Ethernet
2301 * configuration register.
2304 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2305 * unsigned int value 32 bit value.
2308 * The set bits in the value parameter are reset in the configuration
2314 *******************************************************************************/
2315 static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
2318 unsigned int eth_config_reg;
2320 eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
2322 eth_config_reg &= ~value;
2323 MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
2330 #if 0 /* Not needed here */
2331 /*******************************************************************************
2332 * ethernet_get_config_reg - Get the port configuration register
2335 * This function returns the configuration register value of the given
2339 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2345 * Port configuration register value.
2347 *******************************************************************************/
2348 static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
2350 unsigned int eth_config_reg;
2352 eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
2354 return eth_config_reg;
2359 /*******************************************************************************
2360 * eth_port_read_smi_reg - Read PHY registers
2363 * This routine utilize the SMI interface to interact with the PHY in
2364 * order to perform PHY register read.
2367 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2368 * unsigned int phy_reg PHY register address offset.
2369 * unsigned int *value Register value buffer.
2372 * Write the value of a specified PHY register into given buffer.
2375 * false if the PHY is busy or read data is not in valid state.
2378 *******************************************************************************/
2379 static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
2380 unsigned int phy_reg, unsigned int *value)
2382 unsigned int reg_value;
2383 unsigned int time_out = PHY_BUSY_TIMEOUT;
2386 phy_addr = ethernet_phy_get (eth_port_num);
2387 /* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/
2389 /* first check that it is not busy */
2391 reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
2392 if (time_out-- == 0) {
2396 while (reg_value & ETH_SMI_BUSY);
2400 MV_REG_WRITE (MV64360_ETH_SMI_REG,
2401 (phy_addr << 16) | (phy_reg << 21) |
2402 ETH_SMI_OPCODE_READ);
2404 time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */
2407 reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
2408 if (time_out-- == 0) {
2412 while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */
2414 /* Wait for the data to update in the SMI register */
2415 #define PHY_UPDATE_TIMEOUT 10000
2416 for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
2418 reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
2420 *value = reg_value & 0xffff;
2425 /*******************************************************************************
2426 * eth_port_write_smi_reg - Write to PHY registers
2429 * This routine utilize the SMI interface to interact with the PHY in
2430 * order to perform writes to PHY registers.
2433 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2434 * unsigned int phy_reg PHY register address offset.
2435 * unsigned int value Register value.
2438 * Write the given value to the specified PHY register.
2441 * false if the PHY is busy.
2444 *******************************************************************************/
2445 static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
2446 unsigned int phy_reg, unsigned int value)
2448 unsigned int reg_value;
2449 unsigned int time_out = PHY_BUSY_TIMEOUT;
2452 phy_addr = ethernet_phy_get (eth_port_num);
2454 /* first check that it is not busy */
2456 reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
2457 if (time_out-- == 0) {
2461 while (reg_value & ETH_SMI_BUSY);
2464 MV_REG_WRITE (MV64360_ETH_SMI_REG,
2465 (phy_addr << 16) | (phy_reg << 21) |
2466 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2470 /*******************************************************************************
2471 * eth_set_access_control - Config address decode parameters for Ethernet unit
2474 * This function configures the address decode parameters for the Gigabit
2475 * Ethernet Controller according the given parameters struct.
2478 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2479 * ETH_WIN_PARAM *param Address decode parameter struct.
2482 * An access window is opened using the given access parameters.
2487 *******************************************************************************/
2488 static void eth_set_access_control (ETH_PORT eth_port_num,
2489 ETH_WIN_PARAM * param)
2491 unsigned int access_prot_reg;
2493 /* Set access control register */
2494 access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG
2496 access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */
2497 access_prot_reg |= (param->access_ctrl << (param->win * 2));
2498 MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num),
2501 /* Set window Size reg (SR) */
2502 MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 +
2503 (ETH_SIZE_REG_GAP * param->win)),
2504 (((param->size / 0x10000) - 1) << 16));
2506 /* Set window Base address reg (BA) */
2507 MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
2508 (param->target | param->attributes | param->base_addr));
2509 /* High address remap reg (HARR) */
2511 MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 +
2512 (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
2515 /* Base address enable reg (BARER) */
2516 if (param->enable == 1)
2517 MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
2520 MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
2524 /*******************************************************************************
2525 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
2528 * This function prepares a Rx chained list of descriptors and packet
2529 * buffers in a form of a ring. The routine must be called after port
2530 * initialization routine and before port start routine.
2531 * The Ethernet SDMA engine uses CPU bus addresses to access the various
2532 * devices in the system (i.e. DRAM). This function uses the ethernet
2533 * struct 'virtual to physical' routine (set by the user) to set the ring
2534 * with physical addresses.
2537 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2538 * ETH_QUEUE rx_queue Number of Rx queue.
2539 * int rx_desc_num Number of Rx descriptors
2540 * int rx_buff_size Size of Rx buffer
2541 * unsigned int rx_desc_base_addr Rx descriptors memory area base addr.
2542 * unsigned int rx_buff_base_addr Rx buffer memory area base addr.
2545 * The routine updates the Ethernet port control struct with information
2546 * regarding the Rx descriptors and buffers.
2549 * false if the given descriptors memory area is not aligned according to
2550 * Ethernet SDMA specifications.
2553 *******************************************************************************/
2554 static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
2558 unsigned int rx_desc_base_addr,
2559 unsigned int rx_buff_base_addr)
2561 ETH_RX_DESC *p_rx_desc;
2562 ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */
2563 unsigned int buffer_addr;
2564 int ix; /* a counter */
2567 p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
2568 p_rx_prev_desc = p_rx_desc;
2569 buffer_addr = rx_buff_base_addr;
2571 /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
2572 if (rx_buff_base_addr & 0xF)
2575 /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */
2576 if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
2579 /* Rx buffers must be 64-bit aligned. */
2580 if ((rx_buff_base_addr + rx_buff_size) & 0x7)
2583 /* initialize the Rx descriptors ring */
2584 for (ix = 0; ix < rx_desc_num; ix++) {
2585 p_rx_desc->buf_size = rx_buff_size;
2586 p_rx_desc->byte_cnt = 0x0000;
2587 p_rx_desc->cmd_sts =
2588 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2589 p_rx_desc->next_desc_ptr =
2590 ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
2591 p_rx_desc->buf_ptr = buffer_addr;
2592 p_rx_desc->return_info = 0x00000000;
2593 D_CACHE_FLUSH_LINE (p_rx_desc, 0);
2594 buffer_addr += rx_buff_size;
2595 p_rx_prev_desc = p_rx_desc;
2596 p_rx_desc = (ETH_RX_DESC *)
2597 ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
2600 /* Closing Rx descriptors ring */
2601 p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
2602 D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
2604 /* Save Rx desc pointer to driver struct. */
2605 CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
2606 USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
2608 p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
2609 (ETH_RX_DESC *) rx_desc_base_addr;
2610 p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
2611 rx_desc_num * RX_DESC_ALIGNED_SIZE;
2613 p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
2618 /*******************************************************************************
2619 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
2622 * This function prepares a Tx chained list of descriptors and packet
2623 * buffers in a form of a ring. The routine must be called after port
2624 * initialization routine and before port start routine.
2625 * The Ethernet SDMA engine uses CPU bus addresses to access the various
2626 * devices in the system (i.e. DRAM). This function uses the ethernet
2627 * struct 'virtual to physical' routine (set by the user) to set the ring
2628 * with physical addresses.
2631 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2632 * ETH_QUEUE tx_queue Number of Tx queue.
2633 * int tx_desc_num Number of Tx descriptors
2634 * int tx_buff_size Size of Tx buffer
2635 * unsigned int tx_desc_base_addr Tx descriptors memory area base addr.
2636 * unsigned int tx_buff_base_addr Tx buffer memory area base addr.
2639 * The routine updates the Ethernet port control struct with information
2640 * regarding the Tx descriptors and buffers.
2643 * false if the given descriptors memory area is not aligned according to
2644 * Ethernet SDMA specifications.
2647 *******************************************************************************/
2648 static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
2652 unsigned int tx_desc_base_addr,
2653 unsigned int tx_buff_base_addr)
2656 ETH_TX_DESC *p_tx_desc;
2657 ETH_TX_DESC *p_tx_prev_desc;
2658 unsigned int buffer_addr;
2659 int ix; /* a counter */
2662 /* save the first desc pointer to link with the last descriptor */
2663 p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
2664 p_tx_prev_desc = p_tx_desc;
2665 buffer_addr = tx_buff_base_addr;
2667 /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
2668 if (tx_buff_base_addr & 0xF)
2671 /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */
2672 if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
2673 || (tx_buff_size < TX_BUFFER_MIN_SIZE))
2676 /* Initialize the Tx descriptors ring */
2677 for (ix = 0; ix < tx_desc_num; ix++) {
2678 p_tx_desc->byte_cnt = 0x0000;
2679 p_tx_desc->l4i_chk = 0x0000;
2680 p_tx_desc->cmd_sts = 0x00000000;
2681 p_tx_desc->next_desc_ptr =
2682 ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
2684 p_tx_desc->buf_ptr = buffer_addr;
2685 p_tx_desc->return_info = 0x00000000;
2686 D_CACHE_FLUSH_LINE (p_tx_desc, 0);
2687 buffer_addr += tx_buff_size;
2688 p_tx_prev_desc = p_tx_desc;
2689 p_tx_desc = (ETH_TX_DESC *)
2690 ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
2693 /* Closing Tx descriptors ring */
2694 p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
2695 D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
2696 /* Set Tx desc pointer in driver struct. */
2697 CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
2698 USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
2700 /* Init Tx ring base and size parameters */
2701 p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
2702 (ETH_TX_DESC *) tx_desc_base_addr;
2703 p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
2704 (tx_desc_num * TX_DESC_ALIGNED_SIZE);
2706 /* Add the queue to the list of Tx queues of this port */
2707 p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
2712 /*******************************************************************************
2713 * eth_port_send - Send an Ethernet packet
2716 * This routine send a given packet described by p_pktinfo parameter. It
2717 * supports transmitting of a packet spaned over multiple buffers. The
2718 * routine updates 'curr' and 'first' indexes according to the packet
2719 * segment passed to the routine. In case the packet segment is first,
2720 * the 'first' index is update. In any case, the 'curr' index is updated.
2721 * If the routine get into Tx resource error it assigns 'curr' index as
2722 * 'first'. This way the function can abort Tx process of multiple
2723 * descriptors per packet.
2726 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2727 * ETH_QUEUE tx_queue Number of Tx queue.
2728 * PKT_INFO *p_pkt_info User packet buffer.
2731 * Tx ring 'curr' and 'first' indexes are updated.
2734 * ETH_QUEUE_FULL in case of Tx resource error.
2735 * ETH_ERROR in case the routine can not access Tx desc ring.
2736 * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
2739 *******************************************************************************/
2740 static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
2742 PKT_INFO * p_pkt_info)
2744 volatile ETH_TX_DESC *p_tx_desc_first;
2745 volatile ETH_TX_DESC *p_tx_desc_curr;
2746 volatile ETH_TX_DESC *p_tx_next_desc_curr;
2747 volatile ETH_TX_DESC *p_tx_desc_used;
2748 unsigned int command_status;
2750 /* Do not process Tx ring in case of Tx ring resource error */
2751 if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
2752 return ETH_QUEUE_FULL;
2754 /* Get the Tx Desc ring indexes */
2755 CURR_TFD_GET (p_tx_desc_curr, tx_queue);
2756 USED_TFD_GET (p_tx_desc_used, tx_queue);
2758 if (p_tx_desc_curr == NULL)
2761 /* The following parameters are used to save readings from memory */
2762 p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
2763 command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
2765 if (command_status & (ETH_TX_FIRST_DESC)) {
2766 /* Update first desc */
2767 FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
2768 p_tx_desc_first = p_tx_desc_curr;
2770 FIRST_TFD_GET (p_tx_desc_first, tx_queue);
2771 command_status |= ETH_BUFFER_OWNED_BY_DMA;
2774 /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
2775 /* boundary. We use the memory allocated for Tx descriptor. This memory */
2776 /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
2777 if (p_pkt_info->byte_cnt <= 8) {
2778 printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */
2781 p_tx_desc_curr->buf_ptr =
2782 (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
2783 eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
2784 p_pkt_info->byte_cnt);
2786 p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
2788 p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
2789 p_tx_desc_curr->return_info = p_pkt_info->return_info;
2791 if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
2792 /* Set last desc with DMA ownership and interrupt enable. */
2793 p_tx_desc_curr->cmd_sts = command_status |
2794 ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
2796 if (p_tx_desc_curr != p_tx_desc_first)
2797 p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
2799 /* Flush CPU pipe */
2801 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
2802 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
2805 /* Apply send command */
2806 ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
2808 /* Finish Tx packet. Update first desc in case of Tx resource error */
2809 p_tx_desc_first = p_tx_next_desc_curr;
2810 FIRST_TFD_SET (p_tx_desc_first, tx_queue);
2813 p_tx_desc_curr->cmd_sts = command_status;
2814 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
2817 /* Check for ring index overlap in the Tx desc ring */
2818 if (p_tx_next_desc_curr == p_tx_desc_used) {
2819 /* Update the current descriptor */
2820 CURR_TFD_SET (p_tx_desc_first, tx_queue);
2822 p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
2823 return ETH_QUEUE_LAST_RESOURCE;
2825 /* Update the current descriptor */
2826 CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
2831 /*******************************************************************************
2832 * eth_tx_return_desc - Free all used Tx descriptors
2835 * This routine returns the transmitted packet information to the caller.
2836 * It uses the 'first' index to support Tx desc return in case a transmit
2837 * of a packet spanned over multiple buffer still in process.
2838 * In case the Tx queue was in "resource error" condition, where there are
2839 * no available Tx resources, the function resets the resource error flag.
2842 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2843 * ETH_QUEUE tx_queue Number of Tx queue.
2844 * PKT_INFO *p_pkt_info User packet buffer.
2847 * Tx ring 'first' and 'used' indexes are updated.
2850 * ETH_ERROR in case the routine can not access Tx desc ring.
2851 * ETH_RETRY in case there is transmission in process.
2852 * ETH_END_OF_JOB if the routine has nothing to release.
2855 *******************************************************************************/
2856 static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
2859 PKT_INFO * p_pkt_info)
2861 volatile ETH_TX_DESC *p_tx_desc_used = NULL;
2862 volatile ETH_TX_DESC *p_tx_desc_first = NULL;
2863 unsigned int command_status;
2866 /* Get the Tx Desc ring indexes */
2867 USED_TFD_GET (p_tx_desc_used, tx_queue);
2868 FIRST_TFD_GET (p_tx_desc_first, tx_queue);
2872 if (p_tx_desc_used == NULL)
2875 command_status = p_tx_desc_used->cmd_sts;
2877 /* Still transmitting... */
2878 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2879 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
2883 /* Stop release. About to overlap the current available Tx descriptor */
2884 if ((p_tx_desc_used == p_tx_desc_first) &&
2885 (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
2886 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
2887 return ETH_END_OF_JOB;
2890 /* Pass the packet information to the caller */
2891 p_pkt_info->cmd_sts = command_status;
2892 p_pkt_info->return_info = p_tx_desc_used->return_info;
2893 p_tx_desc_used->return_info = 0;
2895 /* Update the next descriptor to release. */
2896 USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
2898 /* Any Tx return cancels the Tx resource error status */
2899 if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
2900 p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
2902 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
2908 /*******************************************************************************
2909 * eth_port_receive - Get received information from Rx ring.
2912 * This routine returns the received data to the caller. There is no
2913 * data copying during routine operation. All information is returned
2914 * using pointer to packet information struct passed from the caller.
2915 * If the routine exhausts Rx ring resources then the resource error flag
2919 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2920 * ETH_QUEUE rx_queue Number of Rx queue.
2921 * PKT_INFO *p_pkt_info User packet buffer.
2924 * Rx ring current and used indexes are updated.
2927 * ETH_ERROR in case the routine can not access Rx desc ring.
2928 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2929 * ETH_END_OF_JOB if there is no received data.
2932 *******************************************************************************/
2933 static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
2935 PKT_INFO * p_pkt_info)
2937 volatile ETH_RX_DESC *p_rx_curr_desc;
2938 volatile ETH_RX_DESC *p_rx_next_curr_desc;
2939 volatile ETH_RX_DESC *p_rx_used_desc;
2940 unsigned int command_status;
2942 /* Do not process Rx ring in case of Rx ring resource error */
2943 if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
2944 printf ("\nRx Queue is full ...\n");
2945 return ETH_QUEUE_FULL;
2948 /* Get the Rx Desc ring 'curr and 'used' indexes */
2949 CURR_RFD_GET (p_rx_curr_desc, rx_queue);
2950 USED_RFD_GET (p_rx_used_desc, rx_queue);
2953 if (p_rx_curr_desc == NULL)
2956 /* The following parameters are used to save readings from memory */
2957 p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
2958 command_status = p_rx_curr_desc->cmd_sts;
2960 /* Nothing to receive... */
2961 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2962 /* DP(printf("Rx: command_status: %08x\n", command_status)); */
2963 D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
2964 /* DP(printf("\nETH_END_OF_JOB ...\n"));*/
2965 return ETH_END_OF_JOB;
2968 p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
2969 p_pkt_info->cmd_sts = command_status;
2970 p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
2971 p_pkt_info->return_info = p_rx_curr_desc->return_info;
2972 p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */
2974 /* Clean the return info field to indicate that the packet has been */
2975 /* moved to the upper layers */
2976 p_rx_curr_desc->return_info = 0;
2978 /* Update 'curr' in data structure */
2979 CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
2981 /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
2982 if (p_rx_next_curr_desc == p_rx_used_desc)
2983 p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
2985 D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
2990 /*******************************************************************************
2991 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2994 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2995 * next 'used' descriptor and attached the returned buffer to it.
2996 * In case the Rx ring was in "resource error" condition, where there are
2997 * no available Rx resources, the function resets the resource error flag.
3000 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
3001 * ETH_QUEUE rx_queue Number of Rx queue.
3002 * PKT_INFO *p_pkt_info Information on the returned buffer.
3005 * New available Rx resource in Rx descriptor ring.
3008 * ETH_ERROR in case the routine can not access Rx desc ring.
3011 *******************************************************************************/
3012 static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
3015 PKT_INFO * p_pkt_info)
3017 volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */
3019 /* Get 'used' Rx descriptor */
3020 USED_RFD_GET (p_used_rx_desc, rx_queue);
3023 if (p_used_rx_desc == NULL)
3026 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
3027 p_used_rx_desc->return_info = p_pkt_info->return_info;
3028 p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
3029 p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE; /* Reset Buffer size */
3031 /* Flush the write pipe */
3034 /* Return the descriptor to DMA ownership */
3035 p_used_rx_desc->cmd_sts =
3036 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
3038 /* Flush descriptor and CPU pipe */
3039 D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
3042 /* Move the used descriptor pointer to the next descriptor */
3043 USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
3045 /* Any Rx return cancels the Rx resource error status */
3046 if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
3047 p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
3052 /*******************************************************************************
3053 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
3056 * This routine sets the RX coalescing interrupt mechanism parameter.
3057 * This parameter is a timeout counter, that counts in 64 t_clk
3058 * chunks ; that when timeout event occurs a maskable interrupt
3060 * The parameter is calculated using the tClk of the MV-643xx chip
3061 * , and the required delay of the interrupt in usec.
3064 * ETH_PORT eth_port_num Ethernet port number
3065 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
3066 * unsigned int delay Delay in usec
3069 * Interrupt coalescing mechanism value is set in MV-643xx chip.
3072 * The interrupt coalescing value set in the gigE port.
3074 *******************************************************************************/
3076 static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
3082 coal = ((t_clk / 1000000) * delay) / 64;
3083 /* Set RX Coalescing mechanism */
3084 MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
3085 ((coal & 0x3fff) << 8) |
3087 (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num))
3093 /*******************************************************************************
3094 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
3097 * This routine sets the TX coalescing interrupt mechanism parameter.
3098 * This parameter is a timeout counter, that counts in 64 t_clk
3099 * chunks ; that when timeout event occurs a maskable interrupt
3101 * The parameter is calculated using the t_cLK frequency of the
3102 * MV-643xx chip and the required delay in the interrupt in uSec
3105 * ETH_PORT eth_port_num Ethernet port number
3106 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
3107 * unsigned int delay Delay in uSeconds
3110 * Interrupt coalescing mechanism value is set in MV-643xx chip.
3113 * The interrupt coalescing value set in the gigE port.
3115 *******************************************************************************/
3117 static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
3123 coal = ((t_clk / 1000000) * delay) / 64;
3124 /* Set TX Coalescing mechanism */
3125 MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
3131 /*******************************************************************************
3132 * eth_b_copy - Copy bytes from source to destination
3135 * This function supports the eight bytes limitation on Tx buffer size.
3136 * The routine will zero eight bytes starting from the destination address
3137 * followed by copying bytes from the source address to the destination.
3140 * unsigned int src_addr 32 bit source address.
3141 * unsigned int dst_addr 32 bit destination address.
3142 * int byte_count Number of bytes to copy.
3150 *******************************************************************************/
3151 static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
3154 /* Zero the dst_addr area */
3155 *(unsigned int *) dst_addr = 0x0;
3157 while (byte_count != 0) {
3158 *(char *) dst_addr = *(char *) src_addr;