board/freescale/mpc8568mds/tlb.c

   1 /*
   2  * Copyright 2008 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2000
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <asm/mmu.h>
  28
  29 struct fsl_e_tlb_entry tlb_table[] = {
  30         /* TLB 0 - for temp stack in cache */
  31         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  32                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  33                       0, 0, BOOKE_PAGESZ_4K, 0),
  34         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  35                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  36                       0, 0, BOOKE_PAGESZ_4K, 0),
  37         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  38                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  39                       0, 0, BOOKE_PAGESZ_4K, 0),
  40         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  41                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  42                       0, 0, BOOKE_PAGESZ_4K, 0),
  43
  44         /* TLB 1 Initializations */
  45         /*
  46          * TLBe 0:      16M     Non-cacheable, guarded
  47          * 0xff000000   16M     FLASH (upper half)
  48          * Out of reset this entry is only 4K.
  49          */
  50         SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, CONFIG_SYS_FLASH_BASE + 0x1000000,
  51                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  52                       0, 0, BOOKE_PAGESZ_16M, 1),
  53
  54         /*
  55          * TLBe 1:      16M     Non-cacheable, guarded
  56          * 0xfe000000   16M     FLASH (lower half)
  57          */
  58         SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
  59                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  60                       0, 1, BOOKE_PAGESZ_16M, 1),
  61
  62         /*
  63          * TLBe 2:      1G      Non-cacheable, guarded
  64          * 0x80000000   512M    PCI1 MEM
  65          * 0xa0000000   512M    PCIe MEM
  66          */
  67         SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
  68                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  69                       0, 2, BOOKE_PAGESZ_1G, 1),
  70
  71         /*
  72          * TLBe 3:      64M     Non-cacheable, guarded
  73          * 0xe000_0000  1M      CCSRBAR
  74          * 0xe200_0000  8M      PCI1 IO
  75          * 0xe280_0000  8M      PCIe IO
  76          */
  77         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  78                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  79                       0, 3, BOOKE_PAGESZ_64M, 1),
  80
  81         /*
  82          * TLBe 4:      64M     Cacheable, non-guarded
  83          * 0xf000_0000  64M     LBC SDRAM
  84          */
  85         SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
  86                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  87                       0, 4, BOOKE_PAGESZ_64M, 1),
  88
  89         /*
  90          * TLBe 5:      256K    Non-cacheable, guarded
  91          * 0xf8000000   32K BCSR
  92          * 0xf8008000   32K PIB (CS4)
  93          * 0xf8010000   32K PIB (CS5)
  94          */
  95         SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE,
  96                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  97                       0, 5, BOOKE_PAGESZ_256K, 1),
  98 };
  99
 100 int num_tlb_entries = ARRAY_SIZE(tlb_table);