2 * Copyright (C) 2012-2013 Lothar Waßmann <LW@KARO-electronics.de>
5 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
24 #include <fdt_support.h>
27 #include <linux/mtd/nand.h>
30 #include <asm/cache.h>
31 #include <asm/omap_common.h>
33 #include <asm/arch/cpu.h>
34 #include <asm/arch/hardware.h>
35 #include <asm/arch/mmc_host_def.h>
36 #include <asm/arch/sys_proto.h>
37 #include <asm/arch/clock.h>
39 #include <asm/arch/da8xx-fb.h>
41 #include "../common/karo.h"
43 DECLARE_GLOBAL_DATA_PTR;
45 #define TX48_LED_GPIO AM33XX_GPIO_NR(1, 26)
46 #define TX48_ETH_PHY_RST_GPIO AM33XX_GPIO_NR(3, 8)
47 #define TX48_LCD_RST_GPIO AM33XX_GPIO_NR(1, 19)
48 #define TX48_LCD_PWR_GPIO AM33XX_GPIO_NR(1, 22)
49 #define TX48_LCD_BACKLIGHT_GPIO AM33XX_GPIO_NR(3, 14)
50 #define TX48_MMC_CD_GPIO AM33XX_GPIO_NR(3, 15)
52 #define GMII_SEL (CTRL_BASE + 0x650)
55 #define UART_SYSCFG_OFFSET 0x54
56 #define UART_SYSSTS_OFFSET 0x58
58 #define UART_RESET (0x1 << 1)
59 #define UART_CLK_RUNNING_MASK 0x1
60 #define UART_SMART_IDLE_EN (0x1 << 0x3)
63 #define TSICR_REG 0x54
64 #define TIOCP_CFG_REG 0x10
67 /* RGMII mode define */
68 #define RGMII_MODE_ENABLE 0xA
69 #define RMII_MODE_ENABLE 0x5
70 #define MII_MODE_ENABLE 0x0
72 #define NO_OF_MAC_ADDR 1
75 /* PAD Control Fields */
76 #define SLEWCTRL (0x1 << 6)
77 #define RXACTIVE (0x1 << 5)
78 #define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
79 #define PULLUDEN (0x0 << 3) /* Pull up enabled */
80 #define PULLUDDIS (0x1 << 3) /* Pull up disabled */
81 #define MODE(val) (val)
85 * Field names corresponds to the pad signal name
177 int ecap0_in_pwm0_out;
196 int xdma_event_intr0;
197 int xdma_event_intr1;
301 #define PAD_CTRL_BASE 0x800
302 #define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
306 * Configure the pin mux for the module
308 static inline void tx48_set_pin_mux(const struct pin_mux *pin_mux,
313 for (i = 0; i < num_pins; i++)
314 writel(pin_mux[i].val, CTRL_BASE + pin_mux[i].reg_offset);
317 #define PRM_RSTST_GLOBAL_COLD_RST (1 << 0)
318 #define PRM_RSTST_GLOBAL_WARM_SW_RST (1 << 1)
319 #define PRM_RSTST_WDT1_RST (1 << 4)
320 #define PRM_RSTST_EXTERNAL_WARM_RST (1 << 5)
321 #define PRM_RSTST_ICEPICK_RST (1 << 9)
323 static u32 prm_rstst __attribute__((section(".data")));
326 * Basic board specific setup
328 static const struct pin_mux stk5_pads[] = {
330 { OFFSET(gpmc_a10), MODE(7) | PULLUDEN, },
332 { OFFSET(gpmc_a3), MODE(7) | PULLUDEN, },
333 /* LCD POWER_ENABLE */
334 { OFFSET(gpmc_a6), MODE(7) | PULLUDEN, },
335 /* LCD Backlight (PWM) */
336 { OFFSET(mcasp0_aclkx), MODE(7) | PULLUDEN, },
338 { OFFSET(mcasp0_fsx), MODE(7) | PULLUDEN | PULLUP_EN, },
341 static const struct gpio stk5_gpios[] = {
342 { TX48_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
343 { TX48_MMC_CD_GPIO, GPIOF_INPUT, "MMC0 CD", },
346 static const struct pin_mux stk5_lcd_pads[] = {
348 { OFFSET(lcd_data0), MODE(0) | PULLUDEN, },
349 { OFFSET(lcd_data1), MODE(0) | PULLUDEN, },
350 { OFFSET(lcd_data2), MODE(0) | PULLUDEN, },
351 { OFFSET(lcd_data3), MODE(0) | PULLUDEN, },
352 { OFFSET(lcd_data4), MODE(0) | PULLUDEN, },
353 { OFFSET(lcd_data5), MODE(0) | PULLUDEN, },
354 { OFFSET(lcd_data6), MODE(0) | PULLUDEN, },
355 { OFFSET(lcd_data7), MODE(0) | PULLUDEN, },
356 { OFFSET(lcd_data8), MODE(0) | PULLUDEN, },
357 { OFFSET(lcd_data9), MODE(0) | PULLUDEN, },
358 { OFFSET(lcd_data10), MODE(0) | PULLUDEN, },
359 { OFFSET(lcd_data11), MODE(0) | PULLUDEN, },
360 { OFFSET(lcd_data12), MODE(0) | PULLUDEN, },
361 { OFFSET(lcd_data13), MODE(0) | PULLUDEN, },
362 { OFFSET(lcd_data14), MODE(0) | PULLUDEN, },
363 { OFFSET(lcd_data15), MODE(0) | PULLUDEN, },
364 /* LCD control signals */
365 { OFFSET(lcd_hsync), MODE(0) | PULLUDEN, },
366 { OFFSET(lcd_vsync), MODE(0) | PULLUDEN, },
367 { OFFSET(lcd_pclk), MODE(0) | PULLUDEN, },
368 { OFFSET(lcd_ac_bias_en), MODE(0) | PULLUDEN, },
371 static const struct gpio stk5_lcd_gpios[] = {
372 { AM33XX_GPIO_NR(1, 19), GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
373 { AM33XX_GPIO_NR(1, 22), GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
374 { AM33XX_GPIO_NR(3, 14), GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
377 static const struct pin_mux stk5v5_pads[] = {
378 /* CAN transceiver control */
379 { OFFSET(gpmc_ad8), MODE(7) | PULLUDEN, },
382 static const struct gpio stk5v5_gpios[] = {
383 { AM33XX_GPIO_NR(0, 22), GPIOF_OUTPUT_INIT_HIGH, "CAN XCVR", },
387 static u16 tx48_cmap[256];
388 vidinfo_t panel_info = {
389 /* set to max. size supported by SoC */
393 .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
397 #define FB_SYNC_OE_LOW_ACT (1 << 31)
398 #define FB_SYNC_CLK_LAT_FALL (1 << 30)
400 static struct fb_videomode tx48_fb_modes[] = {
402 /* Standard VGA timing */
407 .pixclock = KHZ2PICOS(25175),
414 .sync = FB_SYNC_CLK_LAT_FALL,
417 /* Emerging ETV570 640 x 480 display. Syncs low active,
418 * DE high active, 115.2 mm x 86.4 mm display area
419 * VGA compatible timing
425 .pixclock = KHZ2PICOS(25175),
432 .sync = FB_SYNC_CLK_LAT_FALL,
435 /* Emerging ET0350G0DH6 320 x 240 display.
436 * 70.08 mm x 52.56 mm display area.
442 .pixclock = KHZ2PICOS(6500),
443 .left_margin = 68 - 34,
446 .upper_margin = 18 - 3,
449 .sync = FB_SYNC_CLK_LAT_FALL,
452 /* Emerging ET0430G0DH6 480 x 272 display.
453 * 95.04 mm x 53.856 mm display area.
459 .pixclock = KHZ2PICOS(9000),
468 /* Emerging ET0500G0DH6 800 x 480 display.
469 * 109.6 mm x 66.4 mm display area.
475 .pixclock = KHZ2PICOS(33260),
476 .left_margin = 216 - 128,
478 .right_margin = 1056 - 800 - 216,
479 .upper_margin = 35 - 2,
481 .lower_margin = 525 - 480 - 35,
482 .sync = FB_SYNC_CLK_LAT_FALL,
485 /* Emerging ETQ570G0DH6 320 x 240 display.
486 * 115.2 mm x 86.4 mm display area.
492 .pixclock = KHZ2PICOS(6400),
496 .upper_margin = 16, /* 15 according to datasheet */
497 .vsync_len = 3, /* TVP -> 1>x>5 */
498 .lower_margin = 4, /* 4.5 according to datasheet */
499 .sync = FB_SYNC_CLK_LAT_FALL,
502 /* Emerging ET0700G0DH6 800 x 480 display.
503 * 152.4 mm x 91.44 mm display area.
509 .pixclock = KHZ2PICOS(33260),
510 .left_margin = 216 - 128,
512 .right_margin = 1056 - 800 - 216,
513 .upper_margin = 35 - 2,
515 .lower_margin = 525 - 480 - 35,
516 .sync = FB_SYNC_CLK_LAT_FALL,
519 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
527 .sync = FB_SYNC_CLK_LAT_FALL,
531 void *lcd_base; /* Start of framebuffer memory */
532 void *lcd_console_address; /* Start of console buffer */
540 static int lcd_enabled = 1;
541 static int lcd_bl_polarity;
543 static int lcd_backlight_polarity(void)
545 return lcd_bl_polarity;
548 void lcd_initcolregs(void)
552 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
556 void lcd_enable(void)
559 * global variable from common/lcd.c
560 * Set to 0 here to prevent messages from going to LCD
561 * rather than serial console
566 karo_load_splashimage(1);
568 debug("Switching LCD on\n");
569 gpio_set_value(TX48_LCD_PWR_GPIO, 1);
571 gpio_set_value(TX48_LCD_RST_GPIO, 1);
573 gpio_set_value(TX48_LCD_BACKLIGHT_GPIO,
574 lcd_backlight_polarity());
578 void lcd_disable(void)
581 printf("Disabling LCD\n");
587 static void tx48_lcd_panel_setup(struct da8xx_panel *p,
588 struct fb_videomode *fb)
590 p->pxl_clk = PICOS2KHZ(fb->pixclock) * 1000;
593 p->hbp = fb->left_margin;
594 p->hsw = fb->hsync_len;
595 p->hfp = fb->right_margin;
597 p->height = fb->yres;
598 p->vbp = fb->upper_margin;
599 p->vsw = fb->vsync_len;
600 p->vfp = fb->lower_margin;
602 p->invert_pxl_clk = !!(fb->sync & FB_SYNC_CLK_LAT_FALL);
605 void lcd_panel_disable(void)
608 debug("Switching LCD off\n");
609 gpio_set_value(TX48_LCD_BACKLIGHT_GPIO,
610 !lcd_backlight_polarity());
611 gpio_set_value(TX48_LCD_PWR_GPIO, 0);
612 gpio_set_value(TX48_LCD_RST_GPIO, 0);
616 void lcd_ctrl_init(void *lcdbase)
618 int color_depth = 24;
619 const char *video_mode = karo_get_vmode(getenv("video_mode"));
623 struct fb_videomode *p = &tx48_fb_modes[0];
624 struct fb_videomode fb_mode;
625 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
628 debug("LCD disabled\n");
632 if (had_ctrlc() || (prm_rstst & PRM_RSTST_WDT1_RST)) {
633 debug("Disabling LCD\n");
635 setenv("splashimage", NULL);
640 lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
642 if (video_mode == NULL) {
643 debug("Disabling LCD\n");
648 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
650 debug("Using video mode from FDT\n");
652 if (fb_mode.xres > panel_info.vl_col ||
653 fb_mode.yres > panel_info.vl_row) {
654 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
655 fb_mode.xres, fb_mode.yres,
656 panel_info.vl_col, panel_info.vl_row);
662 debug("Trying compiled-in video modes\n");
663 while (p->name != NULL) {
664 if (strcmp(p->name, vm) == 0) {
665 debug("Using video mode: '%s'\n", p->name);
672 debug("Trying to decode video_mode: '%s'\n", vm);
673 while (*vm != '\0') {
674 if (*vm >= '0' && *vm <= '9') {
677 val = simple_strtoul(vm, &end, 0);
680 if (val > panel_info.vl_col)
681 val = panel_info.vl_col;
683 panel_info.vl_col = val;
685 } else if (!yres_set) {
686 if (val > panel_info.vl_row)
687 val = panel_info.vl_row;
689 panel_info.vl_row = val;
691 } else if (!bpp_set) {
700 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
701 end - vm, vm, color_depth);
704 } else if (!refresh_set) {
731 if (p->xres == 0 || p->yres == 0) {
732 printf("Invalid video mode: %s\n", getenv("video_mode"));
734 printf("Supported video modes are:");
735 for (p = &tx48_fb_modes[0]; p->name != NULL; p++) {
736 printf(" %s", p->name);
741 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
742 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
743 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
747 panel_info.vl_col = p->xres;
748 panel_info.vl_row = p->yres;
750 switch (color_depth) {
752 panel_info.vl_bpix = LCD_COLOR8;
755 panel_info.vl_bpix = LCD_COLOR16;
758 panel_info.vl_bpix = LCD_COLOR24;
761 p->pixclock = KHZ2PICOS(refresh *
762 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
763 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
765 debug("Pixel clock set to %lu.%03lu MHz\n",
766 PICOS2KHZ(p->pixclock) / 1000,
767 PICOS2KHZ(p->pixclock) % 1000);
772 debug("Creating new display-timing node from '%s'\n",
774 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
776 printf("Failed to create new display-timing node from '%s': %d\n",
780 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
781 tx48_set_pin_mux(stk5_lcd_pads, ARRAY_SIZE(stk5_lcd_pads));
783 if (karo_load_splashimage(0) == 0) {
784 struct da8xx_panel da8xx_panel = { };
786 debug("Initializing FB driver\n");
787 tx48_lcd_panel_setup(&da8xx_panel, p);
788 da8xx_video_init(&da8xx_panel, color_depth);
790 debug("Initializing LCD controller\n");
793 debug("Skipping initialization of LCD controller\n");
797 #define lcd_enabled 0
798 #endif /* CONFIG_LCD */
800 static void stk5_board_init(void)
802 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
803 tx48_set_pin_mux(stk5_pads, ARRAY_SIZE(stk5_pads));
806 static void stk5v3_board_init(void)
811 static void stk5v5_board_init(void)
815 gpio_request_array(stk5v5_gpios, ARRAY_SIZE(stk5v5_gpios));
816 tx48_set_pin_mux(stk5v5_pads, ARRAY_SIZE(stk5v5_pads));
819 /* called with default environment! */
822 /* mach type passed to kernel */
823 #ifdef CONFIG_OF_LIBFDT
824 gd->bd->bi_arch_number = -1;
826 /* address of boot parameters */
827 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
830 printf("CTRL-C detected\n");
835 static void show_reset_cause(u32 prm_rstst)
837 const char *dlm = "";
839 printf("RESET cause: ");
840 if (prm_rstst & PRM_RSTST_GLOBAL_COLD_RST) {
841 printf("%sPOR", dlm);
844 if (prm_rstst & PRM_RSTST_GLOBAL_WARM_SW_RST) {
848 if (prm_rstst & PRM_RSTST_WDT1_RST) {
849 printf("%sWATCHDOG", dlm);
852 if (prm_rstst & PRM_RSTST_EXTERNAL_WARM_RST) {
853 printf("%sWARM", dlm);
856 if (prm_rstst & PRM_RSTST_ICEPICK_RST) {
857 printf("%sJTAG", dlm);
866 /* called with default environment! */
869 prm_rstst = readl(PRM_RSTST);
870 show_reset_cause(prm_rstst);
872 printf("Board: Ka-Ro TX48-7020\n");
878 static void tx48_set_cpu_clock(void)
880 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
882 if (had_ctrlc() || (prm_rstst & PRM_RSTST_WDT1_RST))
885 if (cpu_clk == 0 || cpu_clk == mpu_clk_rate() / 1000000)
888 mpu_pll_config_val(cpu_clk);
890 printf("CPU clock set to %lu.%03lu MHz\n",
891 mpu_clk_rate() / 1000000,
892 mpu_clk_rate() / 1000 % 1000);
895 static void tx48_init_mac(void)
897 uint8_t mac_addr[ETH_ALEN];
898 uint32_t mac_hi, mac_lo;
900 /* try reading mac address from efuse */
901 mac_lo = __raw_readl(MAC_ID0_LO);
902 mac_hi = __raw_readl(MAC_ID0_HI);
904 mac_addr[0] = mac_hi & 0xFF;
905 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
906 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
907 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
908 mac_addr[4] = mac_lo & 0xFF;
909 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
911 if (!is_valid_ether_addr(mac_addr)) {
912 printf("No valid MAC address programmed\n");
915 printf("MAC addr from fuse: %pM\n", mac_addr);
916 eth_setenv_enetaddr("ethaddr", mac_addr);
919 /* called with environment from NAND or MMC */
920 int board_late_init(void)
923 const char *baseboard;
925 tx48_set_cpu_clock();
928 baseboard = getenv("baseboard");
932 if (strncmp(baseboard, "stk5", 4) == 0) {
933 printf("Baseboard: %s\n", baseboard);
934 if ((strlen(baseboard) == 4) ||
935 strcmp(baseboard, "stk5-v3") == 0) {
937 } else if (strcmp(baseboard, "stk5-v5") == 0) {
940 printf("WARNING: Unsupported STK5 board rev.: %s\n",
944 printf("WARNING: Unsupported baseboard: '%s'\n",
955 #ifdef CONFIG_DRIVER_TI_CPSW
956 static void tx48_phy_init(char *name, int addr)
958 debug("%s: Resetting ethernet PHY\n", __func__);
960 gpio_direction_output(TX48_ETH_PHY_RST_GPIO, 0);
965 gpio_set_value(TX48_ETH_PHY_RST_GPIO, 1);
967 /* Wait for PHY internal POR signal to deassert */
971 static void cpsw_control(int enabled)
973 /* nothing for now */
974 /* TODO : VTP was here before */
977 static struct cpsw_slave_data cpsw_slaves[] = {
979 .slave_reg_ofs = 0x208,
980 .sliver_reg_ofs = 0xd80,
982 .phy_if = PHY_INTERFACE_MODE_RMII,
988 /* Nothing to be done here */
991 static struct cpsw_platform_data cpsw_data = {
992 .mdio_base = CPSW_MDIO_BASE,
993 .cpsw_base = CPSW_BASE,
996 .cpdma_reg_ofs = 0x800,
997 .slaves = ARRAY_SIZE(cpsw_slaves),
998 .slave_data = cpsw_slaves,
999 .ale_reg_ofs = 0xd00,
1000 .ale_entries = 1024,
1001 .host_port_reg_ofs = 0x108,
1002 .hw_stats_reg_ofs = 0x900,
1003 .mac_control = (1 << 5) /* MIIEN */,
1004 .control = cpsw_control,
1005 .phy_init = tx48_phy_init,
1008 .version = CPSW_CTRL_VERSION_2,
1011 int board_eth_init(bd_t *bis)
1013 __raw_writel(RMII_MODE_ENABLE, MAC_MII_SEL);
1014 __raw_writel(0x5D, GMII_SEL);
1015 return cpsw_register(&cpsw_data);
1017 #endif /* CONFIG_DRIVER_TI_CPSW */
1019 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
1020 int cpu_mmc_init(bd_t *bis)
1022 return omap_mmc_init(1, 0, 0, TX48_MMC_CD_GPIO, -1);
1026 void tx48_disable_watchdog(void)
1028 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
1030 while (readl(&wdtimer->wdtwwps) & (1 << 4))
1032 writel(0xaaaa, &wdtimer->wdtwspr);
1033 while (readl(&wdtimer->wdtwwps) & (1 << 4))
1035 writel(0x5555, &wdtimer->wdtwspr);
1039 LED_STATE_INIT = -1,
1044 void show_activity(int arg)
1046 static int led_state = LED_STATE_INIT;
1049 if (led_state == LED_STATE_INIT) {
1050 last = get_timer(0);
1051 gpio_set_value(TX48_LED_GPIO, 1);
1052 led_state = LED_STATE_ON;
1054 if (get_timer(last) > CONFIG_SYS_HZ) {
1055 last = get_timer(0);
1056 if (led_state == LED_STATE_ON) {
1057 gpio_set_value(TX48_LED_GPIO, 0);
1059 gpio_set_value(TX48_LED_GPIO, 1);
1061 led_state = 1 - led_state;
1066 #ifdef CONFIG_OF_BOARD_SETUP
1067 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1068 #include <jffs2/jffs2.h>
1069 #include <mtd_node.h>
1070 static struct node_info nodes[] = {
1071 { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
1072 { "ti,am3352-gpmc", MTD_DEV_TYPE_NAND, },
1076 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1077 #endif /* CONFIG_FDT_FIXUP_PARTITIONS */
1079 static const char *tx48_touchpanels[] = {
1085 void ft_board_setup(void *blob, bd_t *bd)
1087 const char *baseboard = getenv("baseboard");
1088 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1089 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1092 ret = fdt_increase_size(blob, 4096);
1094 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1096 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1097 fdt_fixup_ethernet(blob);
1099 karo_fdt_fixup_touchpanel(blob, tx48_touchpanels,
1100 ARRAY_SIZE(tx48_touchpanels));
1101 karo_fdt_fixup_usb_otg(blob, "usb0", "phys", "vcc-supply");
1102 karo_fdt_fixup_flexcan(blob, stk5_v5);
1104 karo_fdt_update_fb_mode(blob, video_mode);
1106 tx48_disable_watchdog();
1108 #endif /* CONFIG_OF_BOARD_SETUP */