2 * Copyright (C) 2012,2013 Lothar Waßmann <LW@KARO-electronics.de>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
21 #include <fdt_support.h>
25 #include <fsl_esdhc.h>
33 #include <asm/arch/mx6-pins.h>
34 #include <asm/arch/clock.h>
35 #include <asm/arch/imx-regs.h>
36 #include <asm/arch/crm_regs.h>
37 #include <asm/arch/sys_proto.h>
39 #include "../common/karo.h"
41 #define TX6_FEC_RST_GPIO IMX_GPIO_NR(7, 6)
42 #define TX6_FEC_PWR_GPIO IMX_GPIO_NR(3, 20)
43 #define TX6_FEC_INT_GPIO IMX_GPIO_NR(2, 4)
44 #define TX6_LED_GPIO IMX_GPIO_NR(2, 20)
46 #define TX6_LCD_PWR_GPIO IMX_GPIO_NR(2, 31)
47 #define TX6_LCD_RST_GPIO IMX_GPIO_NR(3, 29)
48 #define TX6_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
50 #define TX6_RESET_OUT_GPIO IMX_GPIO_NR(7, 12)
52 #define TEMPERATURE_MIN -40
53 #define TEMPERATURE_HOT 80
54 #define TEMPERATURE_MAX 125
56 DECLARE_GLOBAL_DATA_PTR;
58 #define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
60 static const iomux_v3_cfg_t tx6qdl_pads[] = {
62 MX6_PAD_NANDF_CLE__RAWNAND_CLE,
63 MX6_PAD_NANDF_ALE__RAWNAND_ALE,
64 MX6_PAD_NANDF_WP_B__RAWNAND_RESETN,
65 MX6_PAD_NANDF_RB0__RAWNAND_READY0,
66 MX6_PAD_NANDF_CS0__RAWNAND_CE0N,
67 MX6_PAD_SD4_CMD__RAWNAND_RDN,
68 MX6_PAD_SD4_CLK__RAWNAND_WRN,
69 MX6_PAD_NANDF_D0__RAWNAND_D0,
70 MX6_PAD_NANDF_D1__RAWNAND_D1,
71 MX6_PAD_NANDF_D2__RAWNAND_D2,
72 MX6_PAD_NANDF_D3__RAWNAND_D3,
73 MX6_PAD_NANDF_D4__RAWNAND_D4,
74 MX6_PAD_NANDF_D5__RAWNAND_D5,
75 MX6_PAD_NANDF_D6__RAWNAND_D6,
76 MX6_PAD_NANDF_D7__RAWNAND_D7,
79 MX6_PAD_GPIO_17__GPIO_7_12,
82 #if CONFIG_MXC_UART_BASE == UART1_BASE
83 MX6_PAD_SD3_DAT7__UART1_TXD,
84 MX6_PAD_SD3_DAT6__UART1_RXD,
85 MX6_PAD_SD3_DAT1__UART1_RTS,
86 MX6_PAD_SD3_DAT0__UART1_CTS,
88 #if CONFIG_MXC_UART_BASE == UART2_BASE
89 MX6_PAD_SD4_DAT4__UART2_RXD,
90 MX6_PAD_SD4_DAT7__UART2_TXD,
91 MX6_PAD_SD4_DAT5__UART2_RTS,
92 MX6_PAD_SD4_DAT6__UART2_CTS,
94 #if CONFIG_MXC_UART_BASE == UART3_BASE
95 MX6_PAD_EIM_D24__UART3_TXD,
96 MX6_PAD_EIM_D25__UART3_RXD,
97 MX6_PAD_SD3_RST__UART3_RTS,
98 MX6_PAD_SD3_DAT3__UART3_CTS,
101 MX6_PAD_EIM_D28__I2C1_SDA,
102 MX6_PAD_EIM_D21__I2C1_SCL,
104 /* FEC PHY GPIO functions */
105 MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
106 MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
107 MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
110 static const iomux_v3_cfg_t tx6qdl_fec_pads[] = {
112 MX6_PAD_ENET_MDC__ENET_MDC,
113 MX6_PAD_ENET_MDIO__ENET_MDIO,
114 MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
115 MX6_PAD_ENET_RX_ER__ENET_RX_ER,
116 MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
117 MX6_PAD_ENET_RXD1__ENET_RDATA_1,
118 MX6_PAD_ENET_RXD0__ENET_RDATA_0,
119 MX6_PAD_ENET_TX_EN__ENET_TX_EN,
120 MX6_PAD_ENET_TXD1__ENET_TDATA_1,
121 MX6_PAD_ENET_TXD0__ENET_TDATA_0,
124 static const struct gpio tx6qdl_gpios[] = {
125 { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
126 { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
127 { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
128 { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
134 /* placed in section '.data' to prevent overwriting relocation info
137 static u32 wrsr __attribute__((section(".data")));
139 #define WRSR_POR (1 << 4)
140 #define WRSR_TOUT (1 << 1)
141 #define WRSR_SFTW (1 << 0)
143 static void print_reset_cause(void)
145 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
146 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
150 printf("Reset cause: ");
152 srsr = readl(&src_regs->srsr);
153 wrsr = readw(wdt_base + 4);
155 if (wrsr & WRSR_POR) {
156 printf("%sPOR", dlm);
159 if (srsr & 0x00004) {
160 printf("%sCSU", dlm);
163 if (srsr & 0x00008) {
164 printf("%sIPP USER", dlm);
167 if (srsr & 0x00010) {
168 if (wrsr & WRSR_SFTW) {
169 printf("%sSOFT", dlm);
172 if (wrsr & WRSR_TOUT) {
173 printf("%sWDOG", dlm);
177 if (srsr & 0x00020) {
178 printf("%sJTAG HIGH-Z", dlm);
181 if (srsr & 0x00040) {
182 printf("%sJTAG SW", dlm);
185 if (srsr & 0x10000) {
186 printf("%sWARM BOOT", dlm);
195 int read_cpu_temperature(void);
196 int check_cpu_temperature(int boot);
198 static void tx6qdl_print_cpuinfo(void)
200 u32 cpurev = get_cpu_rev();
203 switch ((cpurev >> 12) & 0xff) {
210 case MXC_CPU_MX6SOLO:
218 printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
220 (cpurev & 0x000F0) >> 4,
221 (cpurev & 0x0000F) >> 0,
222 mxc_get_clock(MXC_ARM_CLK) / 1000000);
225 check_cpu_temperature(1);
228 #define LTC3676_DVB2A 0x0C
229 #define LTC3676_DVB2B 0x0D
230 #define LTC3676_DVB4A 0x10
231 #define LTC3676_DVB4B 0x11
233 #define VDD_SOC_mV (1375 + 50)
234 #define VDD_CORE_mV (1375 + 50)
236 #define mV_to_regval(mV) (((mV) * 360 / 330 - 825 + 1) / 25)
237 #define regval_to_mV(v) (((v) * 25 + 825) * 330 / 360)
239 static int setup_pmic_voltages(void)
244 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
246 ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
248 printf("Failed to initialize I2C\n");
252 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
254 printf("%s: i2c_read error: %d\n", __func__, ret);
258 /* VDDCORE/VDDSOC default 1.375V is not enough, considering
259 pfuze tolerance and IR drop and ripple, need increase
260 to 1.425V for SabreSD */
262 value = 0x39; /* VB default value & PGOOD not forced when slewing */
263 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2B, 1, &value, 1);
265 printf("%s: failed to write PMIC DVB2B register: %d\n",
269 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4B, 1, &value, 1);
271 printf("%s: failed to write PMIC DVB4B register: %d\n",
276 value = mV_to_regval(VDD_SOC_mV);
277 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2A, 1, &value, 1);
279 printf("%s: failed to write PMIC DVB2A register: %d\n",
283 printf("VDDSOC set to %dmV\n", regval_to_mV(value));
285 value = mV_to_regval(VDD_CORE_mV);
286 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4A, 1, &value, 1);
288 printf("%s: failed to write PMIC DVB4A register: %d\n",
292 printf("VDDCORE set to %dmV\n", regval_to_mV(value));
296 int board_early_init_f(void)
298 gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
299 imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
308 /* Address of boot parameters */
309 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
310 #ifdef CONFIG_OF_LIBFDT
311 gd->bd->bi_arch_number = -1;
313 gd->bd->bi_arch_number = 4429;
315 ret = setup_pmic_voltages();
317 printf("Failed to setup PMIC voltages\n");
325 /* dram_init must store complete ramsize in gd->ram_size */
326 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
331 void dram_init_banksize(void)
333 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
334 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
336 #if CONFIG_NR_DRAM_BANKS > 1
337 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
338 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
343 #ifdef CONFIG_CMD_MMC
344 static const iomux_v3_cfg_t mmc0_pads[] = {
345 MX6_PAD_SD1_CMD__USDHC1_CMD,
346 MX6_PAD_SD1_CLK__USDHC1_CLK,
347 MX6_PAD_SD1_DAT0__USDHC1_DAT0,
348 MX6_PAD_SD1_DAT1__USDHC1_DAT1,
349 MX6_PAD_SD1_DAT2__USDHC1_DAT2,
350 MX6_PAD_SD1_DAT3__USDHC1_DAT3,
352 MX6_PAD_SD3_CMD__GPIO_7_2,
355 static const iomux_v3_cfg_t mmc1_pads[] = {
356 MX6_PAD_SD2_CMD__USDHC2_CMD,
357 MX6_PAD_SD2_CLK__USDHC2_CLK,
358 MX6_PAD_SD2_DAT0__USDHC2_DAT0,
359 MX6_PAD_SD2_DAT1__USDHC2_DAT1,
360 MX6_PAD_SD2_DAT2__USDHC2_DAT2,
361 MX6_PAD_SD2_DAT3__USDHC2_DAT3,
363 MX6_PAD_SD3_CLK__GPIO_7_3,
366 static struct tx6_esdhc_cfg {
367 const iomux_v3_cfg_t *pads;
369 enum mxc_clock clkid;
370 struct fsl_esdhc_cfg cfg;
372 } tx6qdl_esdhc_cfg[] = {
375 .num_pads = ARRAY_SIZE(mmc0_pads),
376 .clkid = MXC_ESDHC_CLK,
378 .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
381 .cd_gpio = IMX_GPIO_NR(7, 2),
385 .num_pads = ARRAY_SIZE(mmc1_pads),
386 .clkid = MXC_ESDHC2_CLK,
388 .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
391 .cd_gpio = IMX_GPIO_NR(7, 3),
395 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
399 return p - offsetof(struct tx6_esdhc_cfg, cfg);
402 int board_mmc_getcd(struct mmc *mmc)
404 struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
406 if (cfg->cd_gpio < 0)
409 debug("SD card %d is %spresent\n",
410 cfg - tx6qdl_esdhc_cfg,
411 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
412 return !gpio_get_value(cfg->cd_gpio);
415 int board_mmc_init(bd_t *bis)
419 for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
421 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
424 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
427 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
428 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
430 ret = gpio_request_one(cfg->cd_gpio,
431 GPIOF_INPUT, "MMC CD");
433 printf("Error %d requesting GPIO%d_%d\n",
434 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
438 debug("%s: Initializing MMC slot %d\n", __func__, i);
439 fsl_esdhc_initialize(bis, &cfg->cfg);
441 mmc = find_mmc_device(i);
444 if (board_mmc_getcd(mmc) > 0)
449 #endif /* CONFIG_CMD_MMC */
451 #ifdef CONFIG_FEC_MXC
453 #define FEC_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
455 #define FEC_PAD_CTL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
456 #define GPIO_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
462 int board_eth_init(bd_t *bis)
466 /* delay at least 21ms for the PHY internal POR signal to deassert */
469 imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads));
471 /* Deassert RESET to the external phy */
472 gpio_set_value(TX6_FEC_RST_GPIO, 1);
474 ret = cpu_eth_init(bis);
476 printf("cpu_eth_init() failed: %d\n", ret);
480 #endif /* CONFIG_FEC_MXC */
488 static inline int calc_blink_rate(int tmp)
490 return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
491 (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
492 (TEMPERATURE_HOT - TEMPERATURE_MIN);
495 void show_activity(int arg)
497 static int led_state = LED_STATE_INIT;
498 static int blink_rate;
501 if (led_state == LED_STATE_INIT) {
503 gpio_set_value(TX6_LED_GPIO, 1);
504 led_state = LED_STATE_ON;
505 blink_rate = calc_blink_rate(check_cpu_temperature(0));
507 if (get_timer(last) > blink_rate) {
508 blink_rate = calc_blink_rate(check_cpu_temperature(0));
509 last = get_timer_masked();
510 if (led_state == LED_STATE_ON) {
511 gpio_set_value(TX6_LED_GPIO, 0);
513 gpio_set_value(TX6_LED_GPIO, 1);
515 led_state = 1 - led_state;
520 static const iomux_v3_cfg_t stk5_pads[] = {
521 /* SW controlled LED on STK5 baseboard */
522 MX6_PAD_EIM_A18__GPIO_2_20,
525 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
526 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
527 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
528 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
529 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
530 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
531 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
532 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
533 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
534 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
535 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
536 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
537 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
538 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
539 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
540 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
541 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
542 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
543 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
544 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
545 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
546 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
547 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
548 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
549 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
550 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
551 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
552 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
554 /* I2C bus on DIMM pins 40/41 */
555 MX6_PAD_GPIO_6__I2C3_SDA,
556 MX6_PAD_GPIO_3__I2C3_SCL,
558 /* TSC200x PEN IRQ */
559 MX6_PAD_EIM_D26__GPIO_3_26,
561 /* EDT-FT5x06 Polytouch panel */
562 MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
563 MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */
564 MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */
567 MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
568 MX6_PAD_EIM_D30__GPIO_3_30, /* OC */
570 MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
571 MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
572 MX6_PAD_GPIO_8__GPIO_1_8, /* OC */
575 static const struct gpio stk5_gpios[] = {
576 { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
578 { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
579 { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
580 { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
581 { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
582 { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
586 vidinfo_t panel_info = {
587 /* set to max. size supported by SoC */
591 .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
594 static struct fb_videomode tx6_fb_modes[] = {
596 /* Standard VGA timing */
601 .pixclock = KHZ2PICOS(25175),
608 .sync = FB_SYNC_CLK_LAT_FALL,
611 /* Emerging ETV570 640 x 480 display. Syncs low active,
612 * DE high active, 115.2 mm x 86.4 mm display area
613 * VGA compatible timing
619 .pixclock = KHZ2PICOS(25175),
626 .sync = FB_SYNC_CLK_LAT_FALL,
629 /* Emerging ET0350G0DH6 320 x 240 display.
630 * 70.08 mm x 52.56 mm display area.
636 .pixclock = KHZ2PICOS(6500),
637 .left_margin = 68 - 34,
640 .upper_margin = 18 - 3,
643 .sync = FB_SYNC_CLK_LAT_FALL,
646 /* Emerging ET0430G0DH6 480 x 272 display.
647 * 95.04 mm x 53.856 mm display area.
653 .pixclock = KHZ2PICOS(9000),
660 .sync = FB_SYNC_CLK_LAT_FALL,
663 /* Emerging ET0500G0DH6 800 x 480 display.
664 * 109.6 mm x 66.4 mm display area.
670 .pixclock = KHZ2PICOS(33260),
671 .left_margin = 216 - 128,
673 .right_margin = 1056 - 800 - 216,
674 .upper_margin = 35 - 2,
676 .lower_margin = 525 - 480 - 35,
677 .sync = FB_SYNC_CLK_LAT_FALL,
680 /* Emerging ETQ570G0DH6 320 x 240 display.
681 * 115.2 mm x 86.4 mm display area.
687 .pixclock = KHZ2PICOS(6400),
691 .upper_margin = 16, /* 15 according to datasheet */
692 .vsync_len = 3, /* TVP -> 1>x>5 */
693 .lower_margin = 4, /* 4.5 according to datasheet */
694 .sync = FB_SYNC_CLK_LAT_FALL,
697 /* Emerging ET0700G0DH6 800 x 480 display.
698 * 152.4 mm x 91.44 mm display area.
704 .pixclock = KHZ2PICOS(33260),
705 .left_margin = 216 - 128,
707 .right_margin = 1056 - 800 - 216,
708 .upper_margin = 35 - 2,
710 .lower_margin = 525 - 480 - 35,
711 .sync = FB_SYNC_CLK_LAT_FALL,
714 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
722 .sync = FB_SYNC_CLK_LAT_FALL,
726 static int lcd_enabled = 1;
728 void lcd_enable(void)
731 * global variable from common/lcd.c
732 * Set to 0 here to prevent messages from going to LCD
733 * rather than serial console
737 karo_load_splashimage(1);
740 debug("Switching LCD on\n");
741 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
743 gpio_set_value(TX6_LCD_RST_GPIO, 1);
745 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, 0);
749 void lcd_disable(void)
752 printf("Disabling LCD\n");
757 void lcd_panel_disable(void)
760 debug("Switching LCD off\n");
761 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, 1);
762 gpio_set_value(TX6_LCD_RST_GPIO, 0);
763 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
767 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
769 MX6_PAD_EIM_D29__GPIO_3_29,
770 /* LCD POWER_ENABLE */
771 MX6_PAD_EIM_EB3__GPIO_2_31,
772 /* LCD Backlight (PWM) */
773 MX6_PAD_GPIO_1__GPIO_1_1,
776 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
777 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
778 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
779 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
780 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
781 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
782 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
783 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
784 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
785 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
786 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
787 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
788 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
789 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
790 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
791 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
792 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
793 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
794 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
795 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
796 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
797 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
798 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
799 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
800 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
801 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
802 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
803 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
806 static const struct gpio stk5_lcd_gpios[] = {
807 { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
808 { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
809 { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
812 void lcd_ctrl_init(void *lcdbase)
814 int color_depth = 24;
818 struct fb_videomode *p = &tx6_fb_modes[0];
819 struct fb_videomode fb_mode;
820 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
822 ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
823 unsigned long di_clk_rate = 65000000;
826 debug("LCD disabled\n");
830 if (tstc() || (wrsr & WRSR_TOUT)) {
831 debug("Disabling LCD\n");
838 vm = getenv("video_mode");
840 debug("Disabling LCD\n");
844 if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
846 debug("Using video mode from FDT\n");
848 if (fb_mode.xres > panel_info.vl_col ||
849 fb_mode.yres > panel_info.vl_row) {
850 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
851 fb_mode.xres, fb_mode.yres,
852 panel_info.vl_col, panel_info.vl_row);
858 debug("Trying compiled-in video modes\n");
859 while (p->name != NULL) {
860 if (strcmp(p->name, vm) == 0) {
861 debug("Using video mode: '%s'\n", p->name);
868 debug("Trying to decode video_mode: '%s'\n", vm);
869 while (*vm != '\0') {
870 if (*vm >= '0' && *vm <= '9') {
873 val = simple_strtoul(vm, &end, 0);
876 if (val > panel_info.vl_col)
877 val = panel_info.vl_col;
879 panel_info.vl_col = val;
881 } else if (!yres_set) {
882 if (val > panel_info.vl_row)
883 val = panel_info.vl_row;
885 panel_info.vl_row = val;
887 } else if (!bpp_set) {
891 if (pix_fmt == IPU_PIX_FMT_LVDS666)
892 pix_fmt = IPU_PIX_FMT_LVDS888;
900 if (pix_fmt == IPU_PIX_FMT_LVDS666) {
906 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
907 end - vm, vm, color_depth);
910 } else if (!refresh_set) {
936 if (strncmp(vm, "LVDS", 4) == 0) {
937 pix_fmt = IPU_PIX_FMT_LVDS666;
938 di_clk_parent = DI_PCLK_LDB;
940 pix_fmt = IPU_PIX_FMT_RGB24;
942 tmp = strchr(vm, ':');
950 if (p->xres == 0 || p->yres == 0) {
951 printf("Invalid video mode: %s\n", getenv("video_mode"));
953 printf("Supported video modes are:");
954 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
955 printf(" %s", p->name);
960 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
961 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
962 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
966 panel_info.vl_col = p->xres;
967 panel_info.vl_row = p->yres;
969 switch (color_depth) {
971 panel_info.vl_bpix = LCD_COLOR8;
974 panel_info.vl_bpix = LCD_COLOR16;
977 panel_info.vl_bpix = LCD_COLOR24;
980 p->pixclock = KHZ2PICOS(refresh *
981 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
982 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
984 debug("Pixel clock set to %lu.%03lu MHz\n",
985 PICOS2KHZ(p->pixclock) / 1000,
986 PICOS2KHZ(p->pixclock) % 1000);
990 char *modename = getenv("video_mode");
992 printf("Creating new display-timing node from '%s'\n",
994 ret = karo_fdt_create_fb_mode(working_fdt, modename, p);
996 printf("Failed to create new display-timing node from '%s': %d\n",
1000 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1001 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1002 ARRAY_SIZE(stk5_lcd_pads));
1004 debug("Initializing FB driver\n");
1006 pix_fmt = IPU_PIX_FMT_RGB24;
1007 else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
1008 writel(0x01, IOMUXC_BASE_ADDR + 8);
1009 } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
1010 writel(0x21, IOMUXC_BASE_ADDR + 8);
1012 if (pix_fmt != IPU_PIX_FMT_RGB24) {
1013 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1014 /* enable LDB & DI0 clock */
1015 writel(readl(&ccm_regs->CCGR3) | MXC_CCM_CCGR3_LDB_DI0_MASK |
1016 MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK,
1020 if (karo_load_splashimage(0) == 0) {
1021 debug("Initializing LCD controller\n");
1022 ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
1024 debug("Skipping initialization of LCD controller\n");
1028 #define lcd_enabled 0
1029 #endif /* CONFIG_LCD */
1031 static void stk5_board_init(void)
1033 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1034 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1037 static void stk5v3_board_init(void)
1042 static void stk5v5_board_init(void)
1046 gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
1047 "Flexcan Transceiver");
1048 imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21);
1051 static void tx6qdl_set_cpu_clock(void)
1053 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1055 if (tstc() || (wrsr & WRSR_TOUT))
1058 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1061 if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1062 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1063 printf("CPU clock set to %lu.%03lu MHz\n",
1064 cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1066 printf("Failed to set CPU clock to %lu MHz\n", cpu_clk);
1070 static void tx6_init_mac(void)
1074 imx_get_mac_from_fuse(-1, mac);
1075 if (!is_valid_ether_addr(mac)) {
1076 printf("No valid MAC address programmed\n");
1080 eth_setenv_enetaddr("ethaddr", mac);
1081 printf("MAC addr from fuse: %pM\n", mac);
1084 int board_late_init(void)
1087 const char *baseboard;
1089 tx6qdl_set_cpu_clock();
1090 karo_fdt_move_fdt();
1092 baseboard = getenv("baseboard");
1096 printf("Baseboard: %s\n", baseboard);
1098 if (strncmp(baseboard, "stk5", 4) == 0) {
1099 if ((strlen(baseboard) == 4) ||
1100 strcmp(baseboard, "stk5-v3") == 0) {
1101 stk5v3_board_init();
1102 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1103 const char *otg_mode = getenv("otg_mode");
1105 if (otg_mode && strcmp(otg_mode, "host") == 0) {
1106 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1107 otg_mode, baseboard);
1108 setenv("otg_mode", "none");
1110 stk5v5_board_init();
1112 printf("WARNING: Unsupported STK5 board rev.: %s\n",
1116 printf("WARNING: Unsupported baseboard: '%s'\n",
1124 gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1128 int checkboard(void)
1130 u32 cpurev = get_cpu_rev();
1131 int cpu_variant = (cpurev >> 12) & 0xff;
1133 tx6qdl_print_cpuinfo();
1135 printf("Board: Ka-Ro TX6%c-%dxx%d\n",
1136 cpu_variant == MXC_CPU_MX6Q ? 'Q' : 'U',
1137 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
1138 1 - PHYS_SDRAM_1_WIDTH / 64);
1143 #ifdef CONFIG_SERIAL_TAG
1144 void get_board_serial(struct tag_serialnr *serialnr)
1146 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1147 struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1149 serialnr->low = readl(&fuse->cfg0);
1150 serialnr->high = readl(&fuse->cfg1);
1154 #if defined(CONFIG_OF_BOARD_SETUP)
1155 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1156 #include <jffs2/jffs2.h>
1157 #include <mtd_node.h>
1158 struct node_info nodes[] = {
1159 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1163 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1166 void ft_board_setup(void *blob, bd_t *bd)
1168 const char *baseboard = getenv("baseboard");
1169 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1171 karo_fdt_enable_node(blob, "stk5led", !stk5_v5);
1173 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1174 fdt_fixup_ethernet(blob);
1176 karo_fdt_fixup_touchpanel(blob);
1177 karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy");
1178 karo_fdt_fixup_flexcan(blob, stk5_v5);
1179 karo_fdt_update_fb_mode(blob, getenv("video_mode"));
1181 #endif /* CONFIG_OF_BOARD_SETUP */