2 * Copyright (C) 2015 Lothar Waßmann <LW@KARO-electronics.de>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <fdt_support.h>
14 #include <fsl_esdhc.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
29 #include "../common/karo.h"
32 #define __data __attribute__((section(".data")))
34 #define TX6UL_FEC_RST_GPIO IMX_GPIO_NR(5, 6)
35 #define TX6UL_FEC_PWR_GPIO IMX_GPIO_NR(5, 7)
36 #define TX6UL_FEC_INT_GPIO IMX_GPIO_NR(5, 5)
38 #define TX6UL_FEC2_RST_GPIO IMX_GPIO_NR(4, 28)
39 #define TX6UL_FEC2_INT_GPIO IMX_GPIO_NR(4, 27)
41 #define TX6UL_LED_GPIO IMX_GPIO_NR(5, 9)
43 #define TX6UL_LCD_PWR_GPIO IMX_GPIO_NR(5, 4)
44 #define TX6UL_LCD_RST_GPIO IMX_GPIO_NR(3, 4)
45 #define TX6UL_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(4, 16)
47 #ifdef CONFIG_SYS_I2C_SOFT
48 #define TX6UL_I2C1_SCL_GPIO CONFIG_SOFT_I2C_GPIO_SCL
49 #define TX6UL_I2C1_SDA_GPIO CONFIG_SOFT_I2C_GPIO_SDA
52 #define TX6UL_SD1_CD_GPIO IMX_GPIO_NR(4, 14)
54 #ifdef CONFIG_MX6_TEMPERATURE_MIN
55 #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
57 #define TEMPERATURE_MIN (-40)
59 #ifdef CONFIG_MX6_TEMPERATURE_HOT
60 #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
62 #define TEMPERATURE_HOT 80
65 DECLARE_GLOBAL_DATA_PTR;
67 #define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
69 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
70 #ifdef CONFIG_SECURE_BOOT
71 char __csf_data[0] __attribute__((section(".__csf_data")));
74 #define TX6UL_DEFAULT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP | \
78 #define TX6UL_I2C_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | \
84 #define TX6UL_ENET_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH | \
85 PAD_CTL_DSE_120ohm | \
86 PAD_CTL_PUS_100K_UP | \
88 #define TX6UL_GPIO_OUT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW | \
91 #define TX6UL_GPIO_IN_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW | \
95 static const iomux_v3_cfg_t tx6ul_pads[] = {
97 #if CONFIG_MXC_UART_BASE == UART1_BASE
98 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
99 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
100 MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
101 MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
103 #if CONFIG_MXC_UART_BASE == UART2_BASE
104 MX6_PAD_UART2_TX_DATA__UART2_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
105 MX6_PAD_UART2_RX_DATA__UART2_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
106 MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
107 MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
109 #if CONFIG_MXC_UART_BASE == UART5_BASE
110 MX6_PAD_GPIO1_IO04__UART5_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
111 MX6_PAD_GPIO1_IO05__UART5_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
112 MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
113 MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
115 /* FEC PHY GPIO functions */
116 MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY POWER */
117 MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY RESET */
118 MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | TX6UL_GPIO_IN_PAD_CTRL, /* PHY INT */
121 static const iomux_v3_cfg_t tx6ul_enet1_pads[] = {
123 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm |
125 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
128 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |
132 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | TX6UL_ENET_PAD_CTRL,
133 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | TX6UL_ENET_PAD_CTRL,
134 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | TX6UL_ENET_PAD_CTRL,
135 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | TX6UL_ENET_PAD_CTRL,
136 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | TX6UL_ENET_PAD_CTRL,
137 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | TX6UL_ENET_PAD_CTRL,
138 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | TX6UL_ENET_PAD_CTRL,
141 static const iomux_v3_cfg_t tx6ul_enet2_pads[] = {
142 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |
145 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | TX6UL_ENET_PAD_CTRL,
146 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | TX6UL_ENET_PAD_CTRL,
147 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | TX6UL_ENET_PAD_CTRL,
148 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | TX6UL_ENET_PAD_CTRL,
149 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | TX6UL_ENET_PAD_CTRL,
150 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | TX6UL_ENET_PAD_CTRL,
151 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | TX6UL_ENET_PAD_CTRL,
154 static const iomux_v3_cfg_t tx6ul_i2c_pads[] = {
156 MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
157 TX6UL_I2C_PAD_CTRL, /* I2C SCL */
158 MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
159 TX6UL_I2C_PAD_CTRL, /* I2C SDA */
162 static const struct gpio tx6ul_gpios[] = {
163 #ifdef CONFIG_SYS_I2C_SOFT
164 /* These two entries are used to forcefully reinitialize the I2C bus */
165 { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
166 { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
168 { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
169 { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
170 { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
173 static const struct gpio tx6ul_fec2_gpios[] = {
174 { TX6UL_FEC2_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC2 PHY RESET", },
175 { TX6UL_FEC2_INT_GPIO, GPIOFLAG_INPUT, "FEC2 PHY INT", },
182 /* run with default environment */
183 #if defined(TX6UL_I2C1_SCL_GPIO) && defined(TX6UL_I2C1_SDA_GPIO)
184 #define SCL_BANK (TX6UL_I2C1_SCL_GPIO / 32)
185 #define SDA_BANK (TX6UL_I2C1_SDA_GPIO / 32)
186 #define SCL_BIT (1 << (TX6UL_I2C1_SCL_GPIO % 32))
187 #define SDA_BIT (1 << (TX6UL_I2C1_SDA_GPIO % 32))
189 static void * const gpio_ports[] = {
190 (void *)GPIO1_BASE_ADDR,
191 (void *)GPIO2_BASE_ADDR,
192 (void *)GPIO3_BASE_ADDR,
193 (void *)GPIO4_BASE_ADDR,
194 (void *)GPIO5_BASE_ADDR,
197 static void tx6ul_i2c_recover(void)
201 struct gpio_regs *scl_regs = gpio_ports[SCL_BANK];
202 struct gpio_regs *sda_regs = gpio_ports[SDA_BANK];
204 if ((readl(&scl_regs->gpio_psr) & SCL_BIT) &&
205 (readl(&sda_regs->gpio_psr) & SDA_BIT))
208 debug("Clearing I2C bus\n");
209 if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) {
210 printf("I2C SCL stuck LOW\n");
213 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
214 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
216 imx_iomux_v3_setup_pad(MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 |
217 MUX_CFG_SION | TX6UL_GPIO_OUT_PAD_CTRL);
219 if (!(readl(&sda_regs->gpio_psr) & SDA_BIT)) {
220 printf("I2C SDA stuck LOW\n");
223 clrbits_le32(&sda_regs->gpio_dir, SDA_BIT);
224 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
225 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
229 for (i = 0; i < 18; i++) {
230 u32 reg = readl(&scl_regs->gpio_dr) ^ SCL_BIT;
232 debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
233 writel(reg, &scl_regs->gpio_dr);
236 if (readl(&sda_regs->gpio_psr) & SDA_BIT)
238 if (!(readl(&scl_regs->gpio_psr) & SCL_BIT))
245 bool scl = !!(readl(&scl_regs->gpio_psr) & SCL_BIT);
246 bool sda = !!(readl(&sda_regs->gpio_psr) & SDA_BIT);
249 printf("I2C bus recovery succeeded\n");
251 printf("I2C bus recovery FAILED: SCL: %d SDA: %d\n",
254 imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_pads,
255 ARRAY_SIZE(tx6ul_i2c_pads));
259 static inline void tx6ul_i2c_recover(void)
264 /* placed in section '.data' to prevent overwriting relocation info
267 static u32 wrsr __data;
269 #define WRSR_POR (1 << 4)
270 #define WRSR_TOUT (1 << 1)
271 #define WRSR_SFTW (1 << 0)
273 static void print_reset_cause(void)
275 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
276 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
280 printf("Reset cause: ");
282 srsr = readl(&src_regs->srsr);
283 wrsr = readw(wdt_base + 4);
285 if (wrsr & WRSR_POR) {
286 printf("%sPOR", dlm);
289 if (srsr & 0x00004) {
290 printf("%sCSU", dlm);
293 if (srsr & 0x00008) {
294 printf("%sIPP USER", dlm);
297 if (srsr & 0x00010) {
298 if (wrsr & WRSR_SFTW) {
299 printf("%sSOFT", dlm);
302 if (wrsr & WRSR_TOUT) {
303 printf("%sWDOG", dlm);
307 if (srsr & 0x00020) {
308 printf("%sJTAG HIGH-Z", dlm);
311 if (srsr & 0x00040) {
312 printf("%sJTAG SW", dlm);
315 if (srsr & 0x10000) {
316 printf("%sWARM BOOT", dlm);
325 #ifdef CONFIG_IMX6_THERMAL
327 #include <imx_thermal.h>
330 static void print_temperature(void)
332 struct udevice *thermal_dev;
333 int cpu_tmp, minc, maxc, ret;
334 char const *grade_str;
335 static u32 __data thermal_calib;
337 puts("Temperature: ");
338 switch (get_cpu_temp_grade(&minc, &maxc)) {
339 case TEMP_AUTOMOTIVE:
340 grade_str = "Automotive";
342 case TEMP_INDUSTRIAL:
343 grade_str = "Industrial";
345 case TEMP_EXTCOMMERCIAL:
346 grade_str = "Extended Commercial";
349 grade_str = "Commercial";
351 printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
352 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
354 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
357 printf(" at %dC", cpu_tmp);
359 puts(" - failed to read sensor data");
361 puts(" - no sensor device found");
364 if (fuse_read(1, 6, &thermal_calib) == 0) {
365 printf(" - calibration data 0x%08x\n", thermal_calib);
367 puts(" - Failed to read thermal calib fuse\n");
371 static inline void print_temperature(void)
378 u32 cpurev = get_cpu_rev();
381 if (is_cpu_type(MXC_CPU_MX6SL))
383 else if (is_cpu_type(MXC_CPU_MX6DL))
385 else if (is_cpu_type(MXC_CPU_MX6SOLO))
387 else if (is_cpu_type(MXC_CPU_MX6Q))
389 else if (is_cpu_type(MXC_CPU_MX6UL))
391 else if (is_cpu_type(MXC_CPU_MX6ULL))
394 printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
396 (cpurev & 0x000F0) >> 4,
397 (cpurev & 0x0000F) >> 0,
398 mxc_get_clock(MXC_ARM_CLK) / 1000000);
402 #ifdef CONFIG_MX6_TEMPERATURE_HOT
403 check_cpu_temperature(1);
409 /* serial port not initialized at this point */
410 int board_early_init_f(void)
415 #ifndef CONFIG_MX6_TEMPERATURE_HOT
416 static bool tx6ul_temp_check_enabled = true;
418 #define tx6ul_temp_check_enabled 0
421 #ifndef CONFIG_SYS_NAND_BLOCKS
422 #define CONFIG_SYS_NAND_BLOCKS 0
425 static inline u8 tx6ul_mem_suffix(void)
427 return '0' + CONFIG_SYS_SDRAM_CHIP_SIZE / 1024 * 2 +
428 IS_ENABLED(CONFIG_TX6_EMMC) +
429 CONFIG_SYS_NAND_BLOCKS / 2048 * 4;
432 #ifdef CONFIG_RN5T567
434 #define VDD_RTC_VAL rn5t_mV_to_regval_rtc(3000)
435 #define VDD_CORE_VAL rn5t_mV_to_regval(1300) /* DCDC1 */
436 #define VDD_CORE_VAL_LP rn5t_mV_to_regval(900)
437 #define VDD_DDR_VAL rn5t_mV_to_regval(1350) /* DCDC3 SDRAM 1.35V */
438 #define VDD_DDR_VAL_LP rn5t_mV_to_regval(1350)
439 #define VDD_IO_EXT_VAL rn5t_mV_to_regval(3300) /* DCDC4 eMMC/NAND,VDDIO_EXT 3.0V */
440 #define VDD_IO_EXT_VAL_LP rn5t_mV_to_regval(3300)
441 #define VDD_IO_INT_VAL rn5t_mV_to_regval2(3300) /* LDO1 ENET,GPIO,LCD,SD1,UART,3.3V */
442 #define VDD_IO_INT_VAL_LP rn5t_mV_to_regval2(3300)
443 #define VDD_ADC_VAL rn5t_mV_to_regval2(3300) /* LDO2 ADC */
444 #define VDD_ADC_VAL_LP rn5t_mV_to_regval2(3300)
445 #define VDD_PMIC_VAL rn5t_mV_to_regval2(2500) /* LDO3 PMIC */
446 #define VDD_PMIC_VAL_LP rn5t_mV_to_regval2(2500)
447 #define VDD_CSI_VAL rn5t_mV_to_regval2(3300) /* LDO4 CSI */
448 #define VDD_CSI_VAL_LP rn5t_mV_to_regval2(3300)
449 #define VDD_LDO5_VAL rn5t_mV_to_regval2(1200) /* LDO5 1.2V */
450 #define LDOEN1_LDO1EN (1 << 0)
451 #define LDOEN1_LDO2EN (1 << 1)
452 #define LDOEN1_LDO3EN (1 << 2)
453 #define LDOEN1_LDO4EN (1 << 3)
454 #define LDOEN1_LDO5EN (1 << 4)
455 #define LDOEN1_VAL (LDOEN1_LDO1EN | LDOEN1_LDO2EN | LDOEN1_LDO3EN | LDOEN1_LDO4EN)
456 #define LDOEN1_MASK 0x1f
457 #define LDOEN2_LDORTC1EN (1 << 4)
458 #define LDOEN2_LDORTC2EN (1 << 5)
459 #define LDOEN2_VAL LDOEN2_LDORTC1EN
460 #define LDOEN2_MASK 0x30
462 static struct pmic_regs rn5t567_regs[] = {
463 { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
464 { RN5T567_SLPCNT, 0, },
465 { RN5T567_REPCNT, (3 << 4) | (0 << 1), },
466 { RN5T567_DC1DAC, VDD_CORE_VAL, },
467 { RN5T567_DC3DAC, VDD_DDR_VAL, },
468 { RN5T567_DC4DAC, VDD_IO_EXT_VAL, },
469 { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
470 { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
471 { RN5T567_DC4DAC_SLP, VDD_IO_EXT_VAL_LP, },
472 { RN5T567_DC1CTL, DCnCTL_EN | DCnCTL_DIS | DCnMODE_SLP(MODE_PSM), },
473 { RN5T567_DC2CTL, DCnCTL_DIS, },
474 { RN5T567_DC3CTL, DCnCTL_EN | DCnCTL_DIS | DCnMODE_SLP(MODE_PSM), },
475 { RN5T567_DC4CTL, DCnCTL_EN | DCnCTL_DIS | DCnMODE_SLP(MODE_PSM), },
476 { RN5T567_DC1CTL2, DCnCTL2_LIMSDEN | DCnCTL2_LIM_HIGH | DCnCTL2_SR_HIGH | DCnCTL2_OSC_LOW, },
477 { RN5T567_DC2CTL2, DCnCTL2_LIMSDEN | DCnCTL2_LIM_HIGH | DCnCTL2_SR_HIGH | DCnCTL2_OSC_LOW, },
478 { RN5T567_DC3CTL2, DCnCTL2_LIMSDEN | DCnCTL2_LIM_HIGH | DCnCTL2_SR_HIGH | DCnCTL2_OSC_LOW, },
479 { RN5T567_DC4CTL2, DCnCTL2_LIMSDEN | DCnCTL2_LIM_HIGH | DCnCTL2_SR_HIGH | DCnCTL2_OSC_LOW, },
480 { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
481 { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
482 { RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
483 { RN5T567_LDO2DAC, VDD_ADC_VAL, },
484 { RN5T567_LDO3DAC, VDD_PMIC_VAL, },
485 { RN5T567_LDO4DAC, VDD_CSI_VAL, },
486 { RN5T567_LDO1DAC_SLP, VDD_IO_INT_VAL_LP, },
487 { RN5T567_LDO2DAC_SLP, VDD_ADC_VAL_LP, },
488 { RN5T567_LDO3DAC_SLP, VDD_PMIC_VAL_LP, },
489 { RN5T567_LDO4DAC_SLP, VDD_CSI_VAL_LP, },
490 { RN5T567_LDO5DAC, VDD_LDO5_VAL, },
491 { RN5T567_LDO1DAC_SLP, VDD_IO_INT_VAL_LP, },
492 { RN5T567_LDO2DAC_SLP, VDD_ADC_VAL_LP, },
493 { RN5T567_LDO3DAC_SLP, VDD_PMIC_VAL_LP, },
494 { RN5T567_LDO4DAC_SLP, VDD_CSI_VAL_LP, },
495 { RN5T567_LDOEN1, LDOEN1_VAL, ~LDOEN1_MASK, },
496 { RN5T567_LDOEN2, LDOEN2_VAL, ~LDOEN2_MASK, },
497 { RN5T567_LDODIS, 0x1f, ~0x1f, },
498 { RN5T567_INTPOL, 0, },
499 { RN5T567_INTEN, 0x3, },
500 { RN5T567_DCIREN, 0xf, },
501 { RN5T567_EN_GPIR, 0, },
504 static int pmic_addr = 0x33;
510 u32 cpurev = get_cpu_rev();
513 if (is_cpu_type(MXC_CPU_MX6UL))
514 f = ((cpurev & 0xff) > 0x10) ? '5' : '0';
515 else if (is_cpu_type(MXC_CPU_MX6ULL))
518 debug("%s@%d: cpurev=%08x\n", __func__, __LINE__, cpurev);
520 printf("Board: Ka-Ro TXUL-%c01%c\n", f, tx6ul_mem_suffix());
524 ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
526 printf("Failed to request tx6ul_gpios: %d\n", ret);
528 imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
530 /* Address of boot parameters */
531 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
532 gd->bd->bi_arch_number = -1;
534 if (ctrlc() || (wrsr & WRSR_TOUT)) {
535 if (wrsr & WRSR_TOUT)
536 printf("WDOG RESET detected; Skipping PMIC setup\n");
538 printf("<CTRL-C> detected; safeboot enabled\n");
539 #ifndef CONFIG_MX6_TEMPERATURE_HOT
540 tx6ul_temp_check_enabled = false;
545 ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
547 printf("Failed to setup PMIC voltages: %d\n", ret);
555 debug("%s@%d: \n", __func__, __LINE__);
557 /* dram_init must store complete ramsize in gd->ram_size */
558 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
559 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
563 void dram_init_banksize(void)
565 debug("%s@%d: \n", __func__, __LINE__);
567 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
568 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
570 #if CONFIG_NR_DRAM_BANKS > 1
571 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
572 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
577 #ifdef CONFIG_FSL_ESDHC
578 #define TX6UL_SD_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP | \
579 PAD_CTL_SPEED_MED | \
580 PAD_CTL_DSE_40ohm | \
583 static const iomux_v3_cfg_t mmc0_pads[] = {
584 MX6_PAD_SD1_CMD__USDHC1_CMD | TX6UL_SD_PAD_CTRL,
585 MX6_PAD_SD1_CLK__USDHC1_CLK | TX6UL_SD_PAD_CTRL,
586 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | TX6UL_SD_PAD_CTRL,
587 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | TX6UL_SD_PAD_CTRL,
588 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | TX6UL_SD_PAD_CTRL,
589 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | TX6UL_SD_PAD_CTRL,
591 MX6_PAD_NAND_CE1_B__GPIO4_IO14 | TX6UL_SD_PAD_CTRL,
594 #ifdef CONFIG_TX6_EMMC
595 static const iomux_v3_cfg_t mmc1_pads[] = {
596 MX6_PAD_NAND_WE_B__USDHC2_CMD | TX6UL_SD_PAD_CTRL,
597 MX6_PAD_NAND_RE_B__USDHC2_CLK | TX6UL_SD_PAD_CTRL,
598 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | TX6UL_SD_PAD_CTRL,
599 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | TX6UL_SD_PAD_CTRL,
600 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | TX6UL_SD_PAD_CTRL,
601 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | TX6UL_SD_PAD_CTRL,
603 MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
608 static struct tx6ul_esdhc_cfg {
609 const iomux_v3_cfg_t *pads;
611 enum mxc_clock clkid;
612 struct fsl_esdhc_cfg cfg;
614 } tx6ul_esdhc_cfg[] = {
615 #ifdef CONFIG_TX6_EMMC
618 .num_pads = ARRAY_SIZE(mmc1_pads),
619 .clkid = MXC_ESDHC2_CLK,
621 .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
629 .num_pads = ARRAY_SIZE(mmc0_pads),
630 .clkid = MXC_ESDHC_CLK,
632 .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
635 .cd_gpio = TX6UL_SD1_CD_GPIO,
639 static inline struct tx6ul_esdhc_cfg *to_tx6ul_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
641 return container_of(cfg, struct tx6ul_esdhc_cfg, cfg);
644 int board_mmc_getcd(struct mmc *mmc)
646 struct tx6ul_esdhc_cfg *cfg = to_tx6ul_esdhc_cfg(mmc->priv);
648 if (cfg->cd_gpio < 0)
651 debug("SD card %d is %spresent (GPIO %d)\n",
652 cfg - tx6ul_esdhc_cfg,
653 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
655 return !gpio_get_value(cfg->cd_gpio);
658 int board_mmc_init(bd_t *bis)
662 debug("%s@%d: \n", __func__, __LINE__);
664 #ifndef CONFIG_ENV_IS_IN_MMC
665 if (!(gd->flags & GD_FLG_ENV_READY)) {
666 printf("deferred ...");
670 for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
672 struct tx6ul_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
675 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
676 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
678 if (cfg->cd_gpio >= 0) {
679 ret = gpio_request_one(cfg->cd_gpio,
680 GPIOFLAG_INPUT, "MMC CD");
682 printf("Error %d requesting GPIO%d_%d\n",
683 ret, cfg->cd_gpio / 32,
689 debug("%s: Initializing MMC slot %d\n", __func__, i);
690 fsl_esdhc_initialize(bis, &cfg->cfg);
692 mmc = find_mmc_device(i);
695 if (board_mmc_getcd(mmc))
700 #endif /* CONFIG_FSL_ESDHC */
709 static inline int calc_blink_rate(void)
711 if (!tx6ul_temp_check_enabled)
712 return CONFIG_SYS_HZ;
714 return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
715 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
716 (TEMPERATURE_HOT - TEMPERATURE_MIN);
719 void show_activity(int arg)
721 static int led_state = LED_STATE_INIT;
722 static int blink_rate;
732 ret = gpio_set_value(TX6UL_LED_GPIO, 1);
734 led_state = LED_STATE_ERR;
736 led_state = LED_STATE_ON;
737 blink_rate = calc_blink_rate();
742 if (get_timer(last) > blink_rate) {
743 blink_rate = calc_blink_rate();
744 last = get_timer_masked();
745 if (led_state == LED_STATE_ON) {
746 gpio_set_value(TX6UL_LED_GPIO, 0);
748 gpio_set_value(TX6UL_LED_GPIO, 1);
750 led_state = 1 - led_state;
756 static const iomux_v3_cfg_t stk5_jtag_pads[] = {
757 MX6_PAD_JTAG_MOD__SJC_MOD | TX6UL_GPIO_IN_PAD_CTRL,
758 MX6_PAD_JTAG_TCK__SJC_TCK | TX6UL_GPIO_IN_PAD_CTRL,
759 MX6_PAD_JTAG_TRST_B__SJC_TRSTB | TX6UL_GPIO_IN_PAD_CTRL,
760 MX6_PAD_JTAG_TDI__SJC_TDI | TX6UL_GPIO_IN_PAD_CTRL,
761 MX6_PAD_JTAG_TDO__SJC_TDO | TX6UL_GPIO_OUT_PAD_CTRL,
762 MX6_PAD_JTAG_TMS__SJC_TMS | TX6UL_GPIO_IN_PAD_CTRL,
765 static const iomux_v3_cfg_t stk5_pads[] = {
766 /* SW controlled LED on STK5 baseboard */
767 MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
769 /* I2C bus on DIMM pins 40/41 */
770 MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
771 MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
773 /* TSC200x PEN IRQ */
774 MX6_PAD_JTAG_TMS__GPIO1_IO11 | TX6UL_GPIO_IN_PAD_CTRL,
776 /* EDT-FT5x06 Polytouch panel */
777 MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | TX6UL_GPIO_IN_PAD_CTRL, /* IRQ */
778 MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | TX6UL_GPIO_OUT_PAD_CTRL, /* RESET */
779 MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | TX6UL_GPIO_OUT_PAD_CTRL, /* WAKE */
782 MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
783 MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
786 MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
787 MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
790 static const struct gpio stk5_gpios[] = {
791 { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
793 { IMX_GPIO_NR(1, 27), GPIOFLAG_INPUT, "USBOTG OC", },
794 { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
797 static const iomux_v3_cfg_t tx_tester_pads[] = {
798 /* SW controlled LEDs on TX-TESTER-V5 baseboard */
799 MX6_PAD_SNVS_TAMPER4__GPIO5_IO04, /* red LED */
800 MX6_PAD_SNVS_TAMPER9__GPIO5_IO09, /* yellow LED */
801 MX6_PAD_SNVS_TAMPER8__GPIO5_IO08, /* green LED */
803 MX6_PAD_LCD_DATA04__GPIO3_IO09, /* IO_RESET */
805 /* I2C bus on DIMM pins 40/41 */
806 MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
807 MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
810 MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
811 MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
814 MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
815 MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
817 MX6_PAD_LCD_DATA08__GPIO3_IO13 | TX6UL_GPIO_OUT_PAD_CTRL,
818 MX6_PAD_LCD_DATA09__GPIO3_IO14 | TX6UL_GPIO_OUT_PAD_CTRL,
819 MX6_PAD_LCD_DATA10__GPIO3_IO15 | TX6UL_GPIO_OUT_PAD_CTRL,
822 MX6_PAD_LCD_DATA11__GPIO3_IO16 | TX6UL_GPIO_OUT_PAD_CTRL,
825 * no drive capability for DUT_ETN_LINKLED, DUT_ETN_ACTLED
826 * to not interfere whith the DUT ETN PHY strap pins
828 MX6_PAD_SNVS_TAMPER2__GPIO5_IO02, MUX_PAD_CTRL(PAD_CTL_HYS |
829 PAD_CTL_DSE_DISABLE |
831 MX6_PAD_SNVS_TAMPER3__GPIO5_IO03, MUX_PAD_CTRL(PAD_CTL_HYS |
832 PAD_CTL_DSE_DISABLE |
836 static const struct gpio tx_tester_gpios[] = {
837 { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LEDGE#", },
838 { IMX_GPIO_NR(5, 4), GPIOFLAG_OUTPUT_INIT_LOW, "LEDRT#", },
839 { IMX_GPIO_NR(5, 8), GPIOFLAG_OUTPUT_INIT_LOW, "LEDGN#", },
841 { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_HIGH, "PMIC PWR_ON", },
843 { IMX_GPIO_NR(3, 5), GPIOFLAG_INPUT, "TSTART#", },
844 { IMX_GPIO_NR(3, 6), GPIOFLAG_INPUT, "STARTED", },
845 { IMX_GPIO_NR(3, 7), GPIOFLAG_INPUT, "TSTOP#", },
846 { IMX_GPIO_NR(3, 8), GPIOFLAG_OUTPUT_INIT_LOW, "STOP#", },
848 { IMX_GPIO_NR(3, 10), GPIOFLAG_INPUT, "DUT_PGOOD", },
850 { IMX_GPIO_NR(3, 11), GPIOFLAG_OUTPUT_INIT_HIGH, "VBACKUP_OFF", },
851 { IMX_GPIO_NR(3, 12), GPIOFLAG_OUTPUT_INIT_LOW, "VBACKUP_LOAD", },
853 { IMX_GPIO_NR(1, 10), GPIOFLAG_OUTPUT_INIT_LOW, "VOUTLOAD1", },
854 { IMX_GPIO_NR(3, 30), GPIOFLAG_OUTPUT_INIT_LOW, "VOUTLOAD2", },
855 { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "VOUTLOAD3", },
857 { IMX_GPIO_NR(3, 13), GPIOFLAG_OUTPUT_INIT_LOW, "VIOLOAD1", },
858 { IMX_GPIO_NR(3, 14), GPIOFLAG_OUTPUT_INIT_LOW, "VIOLOAD2", },
859 { IMX_GPIO_NR(3, 15), GPIOFLAG_OUTPUT_INIT_LOW, "VIOLOAD3", },
863 vidinfo_t panel_info = {
864 /* set to max. size supported by SoC */
868 .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
871 static struct fb_videomode tx6ul_fb_modes[] = {
872 #ifndef CONFIG_SYS_LVDS_IF
874 /* Standard VGA timing */
879 .pixclock = KHZ2PICOS(25175),
886 .sync = FB_SYNC_CLK_LAT_FALL,
889 /* Emerging ETV570 640 x 480 display. Syncs low active,
890 * DE high active, 115.2 mm x 86.4 mm display area
891 * VGA compatible timing
897 .pixclock = KHZ2PICOS(25175),
904 .sync = FB_SYNC_CLK_LAT_FALL,
907 /* Emerging ET0350G0DH6 320 x 240 display.
908 * 70.08 mm x 52.56 mm display area.
914 .pixclock = KHZ2PICOS(6500),
915 .left_margin = 68 - 34,
918 .upper_margin = 18 - 3,
921 .sync = FB_SYNC_CLK_LAT_FALL,
924 /* Emerging ET0430G0DH6 480 x 272 display.
925 * 95.04 mm x 53.856 mm display area.
931 .pixclock = KHZ2PICOS(9000),
940 /* Emerging ET0500G0DH6 800 x 480 display.
941 * 109.6 mm x 66.4 mm display area.
947 .pixclock = KHZ2PICOS(33260),
948 .left_margin = 216 - 128,
950 .right_margin = 1056 - 800 - 216,
951 .upper_margin = 35 - 2,
953 .lower_margin = 525 - 480 - 35,
954 .sync = FB_SYNC_CLK_LAT_FALL,
957 /* Emerging ETQ570G0DH6 320 x 240 display.
958 * 115.2 mm x 86.4 mm display area.
964 .pixclock = KHZ2PICOS(6400),
968 .upper_margin = 16, /* 15 according to datasheet */
969 .vsync_len = 3, /* TVP -> 1>x>5 */
970 .lower_margin = 4, /* 4.5 according to datasheet */
971 .sync = FB_SYNC_CLK_LAT_FALL,
974 /* Emerging ET0700G0DH6 800 x 480 display.
975 * 152.4 mm x 91.44 mm display area.
981 .pixclock = KHZ2PICOS(33260),
982 .left_margin = 216 - 128,
984 .right_margin = 1056 - 800 - 216,
985 .upper_margin = 35 - 2,
987 .lower_margin = 525 - 480 - 35,
988 .sync = FB_SYNC_CLK_LAT_FALL,
991 /* Emerging ET070001DM6 800 x 480 display.
992 * 152.4 mm x 91.44 mm display area.
994 .name = "ET070001DM6",
998 .pixclock = KHZ2PICOS(33260),
999 .left_margin = 216 - 128,
1001 .right_margin = 1056 - 800 - 216,
1002 .upper_margin = 35 - 2,
1004 .lower_margin = 525 - 480 - 35,
1009 /* HannStar HSD100PXN1
1010 * 202.7m mm x 152.06 mm display area.
1012 .name = "HSD100PXN1",
1016 .pixclock = KHZ2PICOS(65000),
1019 .right_margin = 320,
1023 .sync = FB_SYNC_CLK_LAT_FALL,
1027 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
1035 .sync = FB_SYNC_CLK_LAT_FALL,
1039 static int lcd_enabled = 1;
1040 static int lcd_bl_polarity;
1042 static int lcd_backlight_polarity(void)
1044 return lcd_bl_polarity;
1047 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
1050 MX6_PAD_LCD_RESET__GPIO3_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
1051 /* LCD POWER_ENABLE */
1052 MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
1053 /* LCD Backlight (PWM) */
1054 MX6_PAD_NAND_DQS__GPIO4_IO16 | TX6UL_GPIO_OUT_PAD_CTRL,
1056 MX6_PAD_LCD_DATA00__LCDIF_DATA00,
1057 MX6_PAD_LCD_DATA01__LCDIF_DATA01,
1058 MX6_PAD_LCD_DATA02__LCDIF_DATA02,
1059 MX6_PAD_LCD_DATA03__LCDIF_DATA03,
1060 MX6_PAD_LCD_DATA04__LCDIF_DATA04,
1061 MX6_PAD_LCD_DATA05__LCDIF_DATA05,
1062 MX6_PAD_LCD_DATA06__LCDIF_DATA06,
1063 MX6_PAD_LCD_DATA07__LCDIF_DATA07,
1064 MX6_PAD_LCD_DATA08__LCDIF_DATA08,
1065 MX6_PAD_LCD_DATA09__LCDIF_DATA09,
1066 MX6_PAD_LCD_DATA10__LCDIF_DATA10,
1067 MX6_PAD_LCD_DATA11__LCDIF_DATA11,
1068 MX6_PAD_LCD_DATA12__LCDIF_DATA12,
1069 MX6_PAD_LCD_DATA13__LCDIF_DATA13,
1070 MX6_PAD_LCD_DATA14__LCDIF_DATA14,
1071 MX6_PAD_LCD_DATA15__LCDIF_DATA15,
1072 MX6_PAD_LCD_DATA16__LCDIF_DATA16,
1073 MX6_PAD_LCD_DATA17__LCDIF_DATA17,
1074 MX6_PAD_LCD_DATA18__LCDIF_DATA18,
1075 MX6_PAD_LCD_DATA19__LCDIF_DATA19,
1076 MX6_PAD_LCD_DATA20__LCDIF_DATA20,
1077 MX6_PAD_LCD_DATA21__LCDIF_DATA21,
1078 MX6_PAD_LCD_DATA22__LCDIF_DATA22,
1079 MX6_PAD_LCD_DATA23__LCDIF_DATA23,
1080 MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
1081 MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
1082 MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
1083 MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
1087 static const struct gpio stk5_lcd_gpios[] = {
1088 { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1089 { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1090 { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1093 /* run with valid env from NAND/eMMC */
1094 void lcd_enable(void)
1097 * global variable from common/lcd.c
1098 * Set to 0 here to prevent messages from going to LCD
1099 * rather than serial console
1104 karo_load_splashimage(1);
1106 debug("Switching LCD on\n");
1107 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
1109 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
1111 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
1112 lcd_backlight_polarity());
1116 static void lcd_disable(void)
1119 printf("Disabling LCD\n");
1120 panel_info.vl_row = 0;
1125 void lcd_ctrl_init(void *lcdbase)
1127 int color_depth = 24;
1128 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1132 struct fb_videomode *p = &tx6ul_fb_modes[0];
1133 struct fb_videomode fb_mode;
1134 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1137 debug("LCD disabled\n");
1141 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1143 setenv("splashimage", NULL);
1147 karo_fdt_move_fdt();
1148 lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1150 if (video_mode == NULL) {
1155 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1157 debug("Using video mode from FDT\n");
1159 if (fb_mode.xres > panel_info.vl_col ||
1160 fb_mode.yres > panel_info.vl_row) {
1161 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1162 fb_mode.xres, fb_mode.yres,
1163 panel_info.vl_col, panel_info.vl_row);
1168 if (p->name != NULL)
1169 debug("Trying compiled-in video modes\n");
1170 while (p->name != NULL) {
1171 if (strcmp(p->name, vm) == 0) {
1172 debug("Using video mode: '%s'\n", p->name);
1179 debug("Trying to decode video_mode: '%s'\n", vm);
1180 while (*vm != '\0') {
1181 if (*vm >= '0' && *vm <= '9') {
1184 val = simple_strtoul(vm, &end, 0);
1187 if (val > panel_info.vl_col)
1188 val = panel_info.vl_col;
1190 panel_info.vl_col = val;
1192 } else if (!yres_set) {
1193 if (val > panel_info.vl_row)
1194 val = panel_info.vl_row;
1196 panel_info.vl_row = val;
1198 } else if (!bpp_set) {
1209 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1214 } else if (!refresh_set) {
1241 if (p->xres == 0 || p->yres == 0) {
1242 printf("Invalid video mode: %s\n", getenv("video_mode"));
1244 printf("Supported video modes are:");
1245 for (p = &tx6ul_fb_modes[0]; p->name != NULL; p++) {
1246 printf(" %s", p->name);
1251 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1252 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1253 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1257 panel_info.vl_col = p->xres;
1258 panel_info.vl_row = p->yres;
1260 switch (color_depth) {
1262 panel_info.vl_bpix = LCD_COLOR8;
1265 panel_info.vl_bpix = LCD_COLOR16;
1268 panel_info.vl_bpix = LCD_COLOR32;
1271 if (refresh_set || p->pixclock == 0)
1272 p->pixclock = KHZ2PICOS(refresh *
1273 (p->xres + p->left_margin +
1274 p->right_margin + p->hsync_len) *
1275 (p->yres + p->upper_margin +
1276 p->lower_margin + p->vsync_len) /
1278 debug("Pixel clock set to %lu.%03lu MHz\n",
1279 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1281 if (p != &fb_mode) {
1284 debug("Creating new display-timing node from '%s'\n",
1286 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1288 printf("Failed to create new display-timing node from '%s': %d\n",
1292 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1293 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1294 ARRAY_SIZE(stk5_lcd_pads));
1296 debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
1297 color_depth, refresh);
1299 if (karo_load_splashimage(0) == 0) {
1302 /* setup env variable for mxsfb display driver */
1303 snprintf(vmode, sizeof(vmode),
1304 "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
1305 p->xres, p->yres, p->left_margin, p->right_margin,
1306 p->upper_margin, p->lower_margin, p->hsync_len,
1307 p->vsync_len, p->sync, p->pixclock, color_depth);
1308 setenv("videomode", vmode);
1310 debug("Initializing LCD controller\n");
1313 setenv("videomode", NULL);
1315 debug("Skipping initialization of LCD controller\n");
1319 #define lcd_enabled 0
1320 #endif /* CONFIG_LCD */
1322 #ifndef CONFIG_ENV_IS_IN_MMC
1323 static void tx6ul_mmc_init(void)
1326 if (board_mmc_init(gd->bd) < 0)
1327 cpu_mmc_init(gd->bd);
1328 print_mmc_devices(',');
1331 static inline void tx6ul_mmc_init(void)
1336 static void stk5_board_init(void)
1340 ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1342 printf("Failed to request stk5_gpios: %d\n", ret);
1346 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1347 if (getenv_yesno("jtag_enable") != 0) {
1348 /* true if unset or set to one of: 'yYtT1' */
1349 imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads, ARRAY_SIZE(stk5_jtag_pads));
1352 debug("%s@%d: \n", __func__, __LINE__);
1355 static void stk5v3_board_init(void)
1357 debug("%s@%d: \n", __func__, __LINE__);
1359 debug("%s@%d: \n", __func__, __LINE__);
1363 static void stk5v5_board_init(void)
1370 ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1371 "Flexcan Transceiver");
1373 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1377 imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1378 TX6UL_GPIO_OUT_PAD_CTRL);
1381 static void tx_tester_board_init(void)
1385 setenv("video_mode", NULL);
1386 setenv("touchpanel", NULL);
1387 if (getenv("eth1addr") && !getenv("ethprime"))
1388 setenv("ethprime", "FEC1");
1390 ret = gpio_request_array(tx_tester_gpios, ARRAY_SIZE(tx_tester_gpios));
1392 printf("Failed to request TX-Tester GPIOs: %d\n", ret);
1395 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1397 if (wrsr & WRSR_TOUT)
1398 gpio_set_value(IMX_GPIO_NR(5, 4), 1);
1400 if (getenv_yesno("jtag_enable") != 0) {
1401 /* true if unset or set to one of: 'yYtT1' */
1402 imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads,
1403 ARRAY_SIZE(stk5_jtag_pads));
1406 gpio_set_value(IMX_GPIO_NR(3, 8), 1);
1409 static void tx6ul_set_cpu_clock(void)
1411 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1413 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1416 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1417 printf("%s detected; skipping cpu clock change\n",
1418 (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1421 if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1422 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1423 printf("CPU clock set to %lu.%03lu MHz\n",
1424 cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1426 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1430 int board_late_init(void)
1432 const char *baseboard;
1434 debug("%s@%d: \n", __func__, __LINE__);
1438 if (tx6ul_temp_check_enabled)
1439 check_cpu_temperature(1);
1441 tx6ul_set_cpu_clock();
1444 setenv_ulong("safeboot", 1);
1445 else if (wrsr & WRSR_TOUT)
1446 setenv_ulong("wdreset", 1);
1448 karo_fdt_move_fdt();
1450 baseboard = getenv("baseboard");
1454 printf("Baseboard: %s\n", baseboard);
1456 if (strncmp(baseboard, "stk5", 4) == 0) {
1457 if ((strlen(baseboard) == 4) ||
1458 strcmp(baseboard, "stk5-v3") == 0) {
1459 stk5v3_board_init();
1460 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1461 const char *otg_mode = getenv("otg_mode");
1463 if (otg_mode && strcmp(otg_mode, "host") == 0) {
1464 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1465 otg_mode, baseboard);
1466 setenv("otg_mode", "none");
1468 stk5v5_board_init();
1470 printf("WARNING: Unsupported STK5 board rev.: %s\n",
1473 } else if (strncmp(baseboard, "ulmb-", 5) == 0) {
1474 const char *otg_mode = getenv("otg_mode");
1476 if (otg_mode && strcmp(otg_mode, "host") == 0) {
1477 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1478 otg_mode, baseboard);
1479 setenv("otg_mode", "none");
1482 } else if (strncmp(baseboard, "tx-tester-", 10) == 0) {
1483 const char *otg_mode = getenv("otg_mode");
1485 if (!otg_mode || strcmp(otg_mode, "none") != 0)
1486 setenv("otg_mode", "device");
1487 tx_tester_board_init();
1489 printf("WARNING: Unsupported baseboard: '%s'\n",
1491 printf("Reboot with <CTRL-C> pressed to fix this\n");
1497 debug("%s@%d: \n", __func__, __LINE__);
1503 #ifdef CONFIG_FEC_MXC
1509 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
1511 unsigned int mac0, mac1, mac2;
1512 unsigned int __maybe_unused fuse3_override, fuse4_override;
1518 if (fuse_read(4, 2, &mac0)) {
1519 printf("Failed to read MAC0 fuse\n");
1522 if (fuse_read(4, 3, &mac1)) {
1523 printf("Failed to read MAC1 fuse\n");
1528 mac[2] = mac0 >> 24;
1529 mac[3] = mac0 >> 16;
1535 if (fuse_read(4, 3, &mac1)) {
1536 printf("Failed to read MAC1 fuse\n");
1539 debug("read %08x from fuse 3\n", mac1);
1540 if (fuse_read(4, 4, &mac2)) {
1541 printf("Failed to read MAC2 fuse\n");
1544 debug("read %08x from fuse 4\n", mac2);
1545 mac[0] = mac2 >> 24;
1546 mac[1] = mac2 >> 16;
1549 mac[4] = mac1 >> 24;
1550 mac[5] = mac1 >> 16;
1556 debug("%s@%d: Done %d %pM\n", __func__, __LINE__, dev_id, mac);
1559 static void tx6ul_init_mac(void)
1562 const char *baseboard = getenv("baseboard");
1564 imx_get_mac_from_fuse(0, mac);
1565 if (!is_valid_ethaddr(mac)) {
1566 printf("No valid MAC address programmed\n");
1569 printf("MAC addr from fuse: %pM\n", mac);
1570 if (!getenv("ethaddr"))
1571 eth_setenv_enetaddr("ethaddr", mac);
1573 if (!baseboard || strncmp(baseboard, "stk5", 4) == 0) {
1574 setenv("eth1addr", NULL);
1577 if (getenv("eth1addr"))
1579 imx_get_mac_from_fuse(1, mac);
1580 if (is_valid_ethaddr(mac))
1581 eth_setenv_enetaddr("eth1addr", mac);
1584 int board_eth_init(bd_t *bis)
1590 /* delay at least 21ms for the PHY internal POR signal to deassert */
1593 imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
1594 ARRAY_SIZE(tx6ul_enet1_pads));
1596 /* Deassert RESET to the external phys */
1597 gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
1599 if (getenv("ethaddr")) {
1600 ret = fecmxc_initialize_multi(bis, 0, 0, ENET_BASE_ADDR);
1602 printf("failed to initialize FEC0: %d\n", ret);
1606 if (getenv("eth1addr")) {
1607 ret = gpio_request_array(tx6ul_fec2_gpios,
1608 ARRAY_SIZE(tx6ul_fec2_gpios));
1610 printf("Failed to request tx6ul_fec2_gpios: %d\n", ret);
1612 imx_iomux_v3_setup_multiple_pads(tx6ul_enet2_pads,
1613 ARRAY_SIZE(tx6ul_enet2_pads));
1615 writel(0x00100000, 0x020c80e4); /* assert ENET2_125M_EN */
1617 /* Minimum PHY reset duration */
1619 gpio_set_value(TX6UL_FEC2_RST_GPIO, 1);
1620 /* Wait for PHY internal POR to finish */
1623 ret = fecmxc_initialize_multi(bis, 1, 2, ENET2_BASE_ADDR);
1625 printf("failed to initialize FEC1: %d\n", ret);
1631 #endif /* CONFIG_FEC_MXC */
1633 #ifdef CONFIG_SERIAL_TAG
1634 void get_board_serial(struct tag_serialnr *serialnr)
1636 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1637 struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1639 serialnr->low = readl(&fuse->cfg0);
1640 serialnr->high = readl(&fuse->cfg1);
1644 #if defined(CONFIG_OF_BOARD_SETUP)
1645 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1646 #include <jffs2/jffs2.h>
1647 #include <mtd_node.h>
1648 static struct node_info nodes[] = {
1649 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1652 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1655 static const char *tx6ul_touchpanels[] = {
1661 int ft_board_setup(void *blob, bd_t *bd)
1663 const char *baseboard = getenv("baseboard");
1664 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1665 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1668 ret = fdt_increase_size(blob, 4096);
1670 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1674 karo_fdt_enable_node(blob, "stk5led", 0);
1676 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1678 karo_fdt_fixup_touchpanel(blob, tx6ul_touchpanels,
1679 ARRAY_SIZE(tx6ul_touchpanels));
1680 karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1681 karo_fdt_fixup_flexcan(blob, stk5_v5);
1683 karo_fdt_update_fb_mode(blob, video_mode, "/lcd-panel");
1687 #endif /* CONFIG_OF_BOARD_SETUP */