2 * Copyright (C) 2015 Lothar Waßmann <LW@KARO-electronics.de>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <fdt_support.h>
14 #include <fsl_esdhc.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
29 #include "../common/karo.h"
32 #define __data __attribute__((section(".data")))
34 #define TX6UL_FEC_RST_GPIO IMX_GPIO_NR(5, 6)
35 #define TX6UL_FEC_PWR_GPIO IMX_GPIO_NR(5, 7)
36 #define TX6UL_FEC_INT_GPIO IMX_GPIO_NR(5, 5)
38 #define TX6UL_FEC2_RST_GPIO IMX_GPIO_NR(4, 28)
39 #define TX6UL_FEC2_INT_GPIO IMX_GPIO_NR(4, 27)
41 #define TX6UL_LED_GPIO IMX_GPIO_NR(5, 9)
43 #define TX6UL_LCD_PWR_GPIO IMX_GPIO_NR(5, 4)
44 #define TX6UL_LCD_RST_GPIO IMX_GPIO_NR(3, 4)
45 #define TX6UL_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(4, 16)
47 #ifdef CONFIG_SYS_I2C_SOFT
48 #define TX6UL_I2C1_SCL_GPIO CONFIG_SOFT_I2C_GPIO_SCL
49 #define TX6UL_I2C1_SDA_GPIO CONFIG_SOFT_I2C_GPIO_SDA
52 #define TX6UL_SD1_CD_GPIO IMX_GPIO_NR(4, 14)
54 #ifdef CONFIG_MX6_TEMPERATURE_MIN
55 #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
57 #define TEMPERATURE_MIN (-40)
59 #ifdef CONFIG_MX6_TEMPERATURE_HOT
60 #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
62 #define TEMPERATURE_HOT 80
65 DECLARE_GLOBAL_DATA_PTR;
67 #define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
69 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
70 #ifdef CONFIG_SECURE_BOOT
71 char __csf_data[0] __attribute__((section(".__csf_data")));
74 #define TX6UL_DEFAULT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP | \
78 #define TX6UL_I2C_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | \
83 #define TX6UL_ENET_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH | \
85 PAD_CTL_PUS_100K_UP | \
87 #define TX6UL_GPIO_OUT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW | \
90 #define TX6UL_GPIO_IN_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW | \
94 static const iomux_v3_cfg_t const tx6ul_pads[] = {
96 #if CONFIG_MXC_UART_BASE == UART1_BASE
97 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
98 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
99 MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
100 MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
102 #if CONFIG_MXC_UART_BASE == UART2_BASE
103 MX6_PAD_UART2_TX_DATA__UART2_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
104 MX6_PAD_UART2_RX_DATA__UART2_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
105 MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
106 MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
108 #if CONFIG_MXC_UART_BASE == UART5_BASE
109 MX6_PAD_GPIO1_IO04__UART5_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
110 MX6_PAD_GPIO1_IO05__UART5_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
111 MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
112 MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
114 /* FEC PHY GPIO functions */
115 MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY POWER */
116 MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY RESET */
117 MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | TX6UL_GPIO_IN_PAD_CTRL, /* PHY INT */
120 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
122 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm |
124 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
125 PAD_CTL_DSE_48ohm | PAD_CTL_SPEED_MED),
126 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION |
127 MUX_PAD_CTRL(PAD_CTL_SPEED_MED |
128 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST),
129 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | TX6UL_ENET_PAD_CTRL,
130 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | TX6UL_ENET_PAD_CTRL,
131 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | TX6UL_ENET_PAD_CTRL,
132 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | TX6UL_ENET_PAD_CTRL,
133 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | TX6UL_ENET_PAD_CTRL,
134 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | TX6UL_ENET_PAD_CTRL,
135 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | TX6UL_ENET_PAD_CTRL,
138 static const iomux_v3_cfg_t const tx6ul_enet2_pads[] = {
139 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION |
140 MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |
141 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST),
142 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | TX6UL_ENET_PAD_CTRL,
143 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | TX6UL_ENET_PAD_CTRL,
144 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | TX6UL_ENET_PAD_CTRL,
145 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | TX6UL_ENET_PAD_CTRL,
146 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | TX6UL_ENET_PAD_CTRL,
147 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | TX6UL_ENET_PAD_CTRL,
148 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | TX6UL_ENET_PAD_CTRL,
151 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
153 MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
154 MUX_PAD_CTRL(PAD_CTL_DSE_240ohm | PAD_CTL_HYS |
155 PAD_CTL_ODE), /* I2C SCL */
156 MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
157 MUX_PAD_CTRL(PAD_CTL_DSE_240ohm | PAD_CTL_HYS |
158 PAD_CTL_ODE), /* I2C SDA */
161 static const struct gpio const tx6ul_gpios[] = {
162 #ifdef CONFIG_SYS_I2C_SOFT
163 /* These two entries are used to forcefully reinitialize the I2C bus */
164 { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
165 { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
167 { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
168 { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
169 { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
172 static const struct gpio const tx6ul_fec2_gpios[] = {
173 { TX6UL_FEC2_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC2 PHY RESET", },
174 { TX6UL_FEC2_INT_GPIO, GPIOFLAG_INPUT, "FEC2 PHY INT", },
181 /* run with default environment */
182 #if defined(TX6UL_I2C1_SCL_GPIO) && defined(TX6UL_I2C1_SDA_GPIO)
183 static void tx6_i2c_recover(void)
187 #define SCL_BIT (1 << (TX6UL_I2C1_SCL_GPIO % 32))
188 #define SDA_BIT (1 << (TX6UL_I2C1_SDA_GPIO % 32))
189 #define I2C_GPIO_BASE (GPIO1_BASE_ADDR + TX6UL_I2C1_SCL_GPIO / 32 * 0x4000)
191 if ((readl(I2C_GPIO_BASE + GPIO_PSR) &
192 (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
195 debug("Clearing I2C bus\n");
196 if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SCL_BIT)) {
197 printf("I2C SCL stuck LOW\n");
200 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
201 I2C_GPIO_BASE + GPIO_DR);
202 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
203 I2C_GPIO_BASE + GPIO_DIR);
205 if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)) {
206 printf("I2C SDA stuck LOW\n");
209 writel(readl(I2C_GPIO_BASE + GPIO_DIR) & ~SDA_BIT,
210 I2C_GPIO_BASE + GPIO_DIR);
211 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
212 I2C_GPIO_BASE + GPIO_DR);
213 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
214 I2C_GPIO_BASE + GPIO_DIR);
216 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
217 ARRAY_SIZE(tx6_i2c_gpio_pads));
220 for (i = 0; i < 18; i++) {
221 u32 reg = readl(I2C_GPIO_BASE + GPIO_DR) ^ SCL_BIT;
223 debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
224 writel(reg, I2C_GPIO_BASE + GPIO_DR);
227 readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)
232 u32 reg = readl(I2C_GPIO_BASE + GPIO_PSR);
234 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
235 printf("I2C bus recovery succeeded\n");
237 printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
243 static inline void tx6_i2c_recover(void)
248 /* placed in section '.data' to prevent overwriting relocation info
251 static u32 wrsr __data;
253 #define WRSR_POR (1 << 4)
254 #define WRSR_TOUT (1 << 1)
255 #define WRSR_SFTW (1 << 0)
257 static void print_reset_cause(void)
259 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
260 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
264 printf("Reset cause: ");
266 srsr = readl(&src_regs->srsr);
267 wrsr = readw(wdt_base + 4);
269 if (wrsr & WRSR_POR) {
270 printf("%sPOR", dlm);
273 if (srsr & 0x00004) {
274 printf("%sCSU", dlm);
277 if (srsr & 0x00008) {
278 printf("%sIPP USER", dlm);
281 if (srsr & 0x00010) {
282 if (wrsr & WRSR_SFTW) {
283 printf("%sSOFT", dlm);
286 if (wrsr & WRSR_TOUT) {
287 printf("%sWDOG", dlm);
291 if (srsr & 0x00020) {
292 printf("%sJTAG HIGH-Z", dlm);
295 if (srsr & 0x00040) {
296 printf("%sJTAG SW", dlm);
299 if (srsr & 0x10000) {
300 printf("%sWARM BOOT", dlm);
309 #ifdef CONFIG_IMX6_THERMAL
311 #include <imx_thermal.h>
314 static void print_temperature(void)
316 struct udevice *thermal_dev;
317 int cpu_tmp, minc, maxc, ret;
318 char const *grade_str;
319 static u32 __data thermal_calib;
321 puts("Temperature: ");
322 switch (get_cpu_temp_grade(&minc, &maxc)) {
323 case TEMP_AUTOMOTIVE:
324 grade_str = "Automotive";
326 case TEMP_INDUSTRIAL:
327 grade_str = "Industrial";
329 case TEMP_EXTCOMMERCIAL:
330 grade_str = "Extended Commercial";
333 grade_str = "Commercial";
335 printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
336 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
338 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
341 printf(" at %dC", cpu_tmp);
343 puts(" - failed to read sensor data");
345 puts(" - no sensor device found");
348 if (fuse_read(1, 6, &thermal_calib) == 0) {
349 printf(" - calibration data 0x%08x\n", thermal_calib);
351 puts(" - Failed to read thermal calib fuse\n");
355 static inline void print_temperature(void)
362 u32 cpurev = get_cpu_rev();
365 if (is_cpu_type(MXC_CPU_MX6SL))
367 else if (is_cpu_type(MXC_CPU_MX6DL))
369 else if (is_cpu_type(MXC_CPU_MX6SOLO))
371 else if (is_cpu_type(MXC_CPU_MX6Q))
373 else if (is_cpu_type(MXC_CPU_MX6UL))
376 printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
378 (cpurev & 0x000F0) >> 4,
379 (cpurev & 0x0000F) >> 0,
380 mxc_get_clock(MXC_ARM_CLK) / 1000000);
384 #ifdef CONFIG_MX6_TEMPERATURE_HOT
385 check_cpu_temperature(1);
391 /* serial port not initialized at this point */
392 int board_early_init_f(void)
397 #ifndef CONFIG_MX6_TEMPERATURE_HOT
398 static bool tx6_temp_check_enabled = true;
400 #define tx6_temp_check_enabled 0
403 static inline u8 tx6ul_mem_suffix(void)
405 #ifdef CONFIG_TX6_NAND
412 #ifdef CONFIG_RN5T567
414 #define VDD_RTC_VAL rn5t_mV_to_regval_rtc(3000)
415 #define VDD_CORE_VAL rn5t_mV_to_regval(1300) /* DCDC1 */
416 #define VDD_CORE_VAL_LP rn5t_mV_to_regval(900)
417 #define VDD_DDR_VAL rn5t_mV_to_regval(1350) /* DCDC3 */
418 #define VDD_DDR_VAL_LP rn5t_mV_to_regval(1350)
419 #define VDD_HIGH_VAL rn5t_mV_to_regval(3300) /* DCDC4 */
420 #define VDD_HIGH_VAL_LP rn5t_mV_to_regval(3300)
421 #define VDD_CSI_VAL rn5t_mV_to_regval2(3300) /* LDO4 */
422 #define VDD_CSI_VAL_LP rn5t_mV_to_regval2(3300)
424 static struct pmic_regs rn5t567_regs[] = {
425 { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
426 { RN5T567_DC2CTL, DC2_DC2DIS, },
427 { RN5T567_DC1DAC, VDD_CORE_VAL, },
428 { RN5T567_DC3DAC, VDD_DDR_VAL, },
429 { RN5T567_DC4DAC, VDD_HIGH_VAL, },
430 { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
431 { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
432 { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
433 { RN5T567_LDOEN1, 0x01f, ~0x1f, },
434 { RN5T567_LDOEN2, 0x10, ~0x30, },
435 { RN5T567_LDODIS, 0x00, },
436 { RN5T567_LDO4DAC, VDD_CSI_VAL, },
437 { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
438 { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
441 static int pmic_addr __maybe_unused = 0x33;
447 u32 cpurev = get_cpu_rev();
449 debug("%s@%d: \n", __func__, __LINE__);
451 printf("Board: Ka-Ro TXUL-%c01%c\n",
452 ((cpurev &0xff) > 0x10) ? '5' : '0',
457 ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
459 printf("Failed to request tx6ul_gpios: %d\n", ret);
461 imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
463 /* Address of boot parameters */
464 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
465 gd->bd->bi_arch_number = -1;
467 if (ctrlc() || (wrsr & WRSR_TOUT)) {
468 if (wrsr & WRSR_TOUT)
469 printf("WDOG RESET detected; Skipping PMIC setup\n");
471 printf("<CTRL-C> detected; safeboot enabled\n");
472 #ifndef CONFIG_MX6_TEMPERATURE_HOT
473 tx6_temp_check_enabled = false;
478 ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
480 printf("Failed to setup PMIC voltages: %d\n", ret);
488 debug("%s@%d: \n", __func__, __LINE__);
490 /* dram_init must store complete ramsize in gd->ram_size */
491 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
492 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
496 void dram_init_banksize(void)
498 debug("%s@%d: \n", __func__, __LINE__);
500 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
501 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
503 #if CONFIG_NR_DRAM_BANKS > 1
504 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
505 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
510 #ifdef CONFIG_FSL_ESDHC
511 #define TX6UL_SD_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP | \
512 PAD_CTL_SPEED_MED | \
513 PAD_CTL_DSE_40ohm | \
516 static const iomux_v3_cfg_t mmc0_pads[] = {
517 MX6_PAD_SD1_CMD__USDHC1_CMD | TX6UL_SD_PAD_CTRL,
518 MX6_PAD_SD1_CLK__USDHC1_CLK | TX6UL_SD_PAD_CTRL,
519 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | TX6UL_SD_PAD_CTRL,
520 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | TX6UL_SD_PAD_CTRL,
521 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | TX6UL_SD_PAD_CTRL,
522 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | TX6UL_SD_PAD_CTRL,
524 MX6_PAD_NAND_CE1_B__GPIO4_IO14 | TX6UL_SD_PAD_CTRL,
527 #ifdef CONFIG_TX6_EMMC
528 static const iomux_v3_cfg_t mmc1_pads[] = {
529 MX6_PAD_NAND_WE_B__USDHC2_CMD | TX6UL_SD_PAD_CTRL,
530 MX6_PAD_NAND_RE_B__USDHC2_CLK | TX6UL_SD_PAD_CTRL,
531 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | TX6UL_SD_PAD_CTRL,
532 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | TX6UL_SD_PAD_CTRL,
533 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | TX6UL_SD_PAD_CTRL,
534 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | TX6UL_SD_PAD_CTRL,
536 MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
541 static struct tx6_esdhc_cfg {
542 const iomux_v3_cfg_t *pads;
544 enum mxc_clock clkid;
545 struct fsl_esdhc_cfg cfg;
547 } tx6ul_esdhc_cfg[] = {
548 #ifdef CONFIG_TX6_EMMC
551 .num_pads = ARRAY_SIZE(mmc1_pads),
552 .clkid = MXC_ESDHC2_CLK,
554 .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
562 .num_pads = ARRAY_SIZE(mmc0_pads),
563 .clkid = MXC_ESDHC_CLK,
565 .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
568 .cd_gpio = TX6UL_SD1_CD_GPIO,
572 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
574 return container_of(cfg, struct tx6_esdhc_cfg, cfg);
577 int board_mmc_getcd(struct mmc *mmc)
579 struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
581 if (cfg->cd_gpio < 0)
584 debug("SD card %d is %spresent (GPIO %d)\n",
585 cfg - tx6ul_esdhc_cfg,
586 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
588 return !gpio_get_value(cfg->cd_gpio);
591 int board_mmc_init(bd_t *bis)
595 debug("%s@%d: \n", __func__, __LINE__);
597 #ifndef CONFIG_ENV_IS_IN_MMC
598 if (!(gd->flags & GD_FLG_ENV_READY)) {
599 printf("deferred ...");
603 for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
605 struct tx6_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
608 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
609 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
611 if (cfg->cd_gpio >= 0) {
612 ret = gpio_request_one(cfg->cd_gpio,
613 GPIOFLAG_INPUT, "MMC CD");
615 printf("Error %d requesting GPIO%d_%d\n",
616 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
621 debug("%s: Initializing MMC slot %d\n", __func__, i);
622 fsl_esdhc_initialize(bis, &cfg->cfg);
624 mmc = find_mmc_device(i);
627 if (board_mmc_getcd(mmc))
632 #endif /* CONFIG_FSL_ESDHC */
641 static inline int calc_blink_rate(void)
643 if (!tx6_temp_check_enabled)
644 return CONFIG_SYS_HZ;
646 return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
647 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
648 (TEMPERATURE_HOT - TEMPERATURE_MIN);
651 void show_activity(int arg)
653 static int led_state = LED_STATE_INIT;
654 static int blink_rate;
664 ret = gpio_set_value(TX6UL_LED_GPIO, 1);
666 led_state = LED_STATE_ERR;
668 led_state = LED_STATE_ON;
669 blink_rate = calc_blink_rate();
674 if (get_timer(last) > blink_rate) {
675 blink_rate = calc_blink_rate();
676 last = get_timer_masked();
677 if (led_state == LED_STATE_ON) {
678 gpio_set_value(TX6UL_LED_GPIO, 0);
680 gpio_set_value(TX6UL_LED_GPIO, 1);
682 led_state = 1 - led_state;
688 static const iomux_v3_cfg_t stk5_jtag_pads[] = {
689 MX6_PAD_JTAG_MOD__SJC_MOD | TX6UL_GPIO_IN_PAD_CTRL,
690 MX6_PAD_JTAG_TCK__SJC_TCK | TX6UL_GPIO_IN_PAD_CTRL,
691 MX6_PAD_JTAG_TRST_B__SJC_TRSTB | TX6UL_GPIO_IN_PAD_CTRL,
692 MX6_PAD_JTAG_TDI__SJC_TDI | TX6UL_GPIO_IN_PAD_CTRL,
693 MX6_PAD_JTAG_TDO__SJC_TDO | TX6UL_GPIO_OUT_PAD_CTRL,
694 MX6_PAD_JTAG_TMS__SJC_TMS | TX6UL_GPIO_IN_PAD_CTRL,
697 static const iomux_v3_cfg_t stk5_pads[] = {
698 /* SW controlled LED on STK5 baseboard */
699 MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
701 /* I2C bus on DIMM pins 40/41 */
702 MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
703 MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
705 /* TSC200x PEN IRQ */
706 MX6_PAD_JTAG_TMS__GPIO1_IO11 | TX6UL_GPIO_IN_PAD_CTRL,
708 /* EDT-FT5x06 Polytouch panel */
709 MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | TX6UL_GPIO_IN_PAD_CTRL, /* IRQ */
710 MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | TX6UL_GPIO_OUT_PAD_CTRL, /* RESET */
711 MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | TX6UL_GPIO_OUT_PAD_CTRL, /* WAKE */
714 MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
715 MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
718 MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
719 MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
722 static const struct gpio stk5_gpios[] = {
723 { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
725 { IMX_GPIO_NR(1, 27), GPIOFLAG_INPUT, "USBOTG OC", },
726 { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
730 vidinfo_t panel_info = {
731 /* set to max. size supported by SoC */
735 .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
738 static struct fb_videomode tx6_fb_modes[] = {
739 #ifndef CONFIG_SYS_LVDS_IF
741 /* Standard VGA timing */
746 .pixclock = KHZ2PICOS(25175),
753 .sync = FB_SYNC_CLK_LAT_FALL,
756 /* Emerging ETV570 640 x 480 display. Syncs low active,
757 * DE high active, 115.2 mm x 86.4 mm display area
758 * VGA compatible timing
764 .pixclock = KHZ2PICOS(25175),
771 .sync = FB_SYNC_CLK_LAT_FALL,
774 /* Emerging ET0350G0DH6 320 x 240 display.
775 * 70.08 mm x 52.56 mm display area.
781 .pixclock = KHZ2PICOS(6500),
782 .left_margin = 68 - 34,
785 .upper_margin = 18 - 3,
788 .sync = FB_SYNC_CLK_LAT_FALL,
791 /* Emerging ET0430G0DH6 480 x 272 display.
792 * 95.04 mm x 53.856 mm display area.
798 .pixclock = KHZ2PICOS(9000),
807 /* Emerging ET0500G0DH6 800 x 480 display.
808 * 109.6 mm x 66.4 mm display area.
814 .pixclock = KHZ2PICOS(33260),
815 .left_margin = 216 - 128,
817 .right_margin = 1056 - 800 - 216,
818 .upper_margin = 35 - 2,
820 .lower_margin = 525 - 480 - 35,
821 .sync = FB_SYNC_CLK_LAT_FALL,
824 /* Emerging ETQ570G0DH6 320 x 240 display.
825 * 115.2 mm x 86.4 mm display area.
831 .pixclock = KHZ2PICOS(6400),
835 .upper_margin = 16, /* 15 according to datasheet */
836 .vsync_len = 3, /* TVP -> 1>x>5 */
837 .lower_margin = 4, /* 4.5 according to datasheet */
838 .sync = FB_SYNC_CLK_LAT_FALL,
841 /* Emerging ET0700G0DH6 800 x 480 display.
842 * 152.4 mm x 91.44 mm display area.
848 .pixclock = KHZ2PICOS(33260),
849 .left_margin = 216 - 128,
851 .right_margin = 1056 - 800 - 216,
852 .upper_margin = 35 - 2,
854 .lower_margin = 525 - 480 - 35,
855 .sync = FB_SYNC_CLK_LAT_FALL,
858 /* Emerging ET070001DM6 800 x 480 display.
859 * 152.4 mm x 91.44 mm display area.
861 .name = "ET070001DM6",
865 .pixclock = KHZ2PICOS(33260),
866 .left_margin = 216 - 128,
868 .right_margin = 1056 - 800 - 216,
869 .upper_margin = 35 - 2,
871 .lower_margin = 525 - 480 - 35,
876 /* HannStar HSD100PXN1
877 * 202.7m mm x 152.06 mm display area.
879 .name = "HSD100PXN1",
883 .pixclock = KHZ2PICOS(65000),
890 .sync = FB_SYNC_CLK_LAT_FALL,
894 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
902 .sync = FB_SYNC_CLK_LAT_FALL,
906 static int lcd_enabled = 1;
907 static int lcd_bl_polarity;
909 static int lcd_backlight_polarity(void)
911 return lcd_bl_polarity;
914 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
917 MX6_PAD_LCD_RESET__GPIO3_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
918 /* LCD POWER_ENABLE */
919 MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
920 /* LCD Backlight (PWM) */
921 MX6_PAD_NAND_DQS__GPIO4_IO16 | TX6UL_GPIO_OUT_PAD_CTRL,
923 MX6_PAD_LCD_DATA00__LCDIF_DATA00,
924 MX6_PAD_LCD_DATA01__LCDIF_DATA01,
925 MX6_PAD_LCD_DATA02__LCDIF_DATA02,
926 MX6_PAD_LCD_DATA03__LCDIF_DATA03,
927 MX6_PAD_LCD_DATA04__LCDIF_DATA04,
928 MX6_PAD_LCD_DATA05__LCDIF_DATA05,
929 MX6_PAD_LCD_DATA06__LCDIF_DATA06,
930 MX6_PAD_LCD_DATA07__LCDIF_DATA07,
931 MX6_PAD_LCD_DATA08__LCDIF_DATA08,
932 MX6_PAD_LCD_DATA09__LCDIF_DATA09,
933 MX6_PAD_LCD_DATA10__LCDIF_DATA10,
934 MX6_PAD_LCD_DATA11__LCDIF_DATA11,
935 MX6_PAD_LCD_DATA12__LCDIF_DATA12,
936 MX6_PAD_LCD_DATA13__LCDIF_DATA13,
937 MX6_PAD_LCD_DATA14__LCDIF_DATA14,
938 MX6_PAD_LCD_DATA15__LCDIF_DATA15,
939 MX6_PAD_LCD_DATA16__LCDIF_DATA16,
940 MX6_PAD_LCD_DATA17__LCDIF_DATA17,
941 MX6_PAD_LCD_DATA18__LCDIF_DATA18,
942 MX6_PAD_LCD_DATA19__LCDIF_DATA19,
943 MX6_PAD_LCD_DATA20__LCDIF_DATA20,
944 MX6_PAD_LCD_DATA21__LCDIF_DATA21,
945 MX6_PAD_LCD_DATA22__LCDIF_DATA22,
946 MX6_PAD_LCD_DATA23__LCDIF_DATA23,
947 MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
948 MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
949 MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
950 MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
954 static const struct gpio stk5_lcd_gpios[] = {
955 { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
956 { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
957 { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
960 /* run with valid env from NAND/eMMC */
961 void lcd_enable(void)
964 * global variable from common/lcd.c
965 * Set to 0 here to prevent messages from going to LCD
966 * rather than serial console
971 karo_load_splashimage(1);
973 debug("Switching LCD on\n");
974 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
976 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
978 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
979 lcd_backlight_polarity());
983 static void lcd_disable(void)
986 printf("Disabling LCD\n");
987 panel_info.vl_row = 0;
992 void lcd_ctrl_init(void *lcdbase)
994 int color_depth = 24;
995 const char *video_mode = karo_get_vmode(getenv("video_mode"));
999 struct fb_videomode *p = &tx6_fb_modes[0];
1000 struct fb_videomode fb_mode;
1001 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1004 debug("LCD disabled\n");
1008 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1010 setenv("splashimage", NULL);
1014 karo_fdt_move_fdt();
1015 lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1017 if (video_mode == NULL) {
1022 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1024 debug("Using video mode from FDT\n");
1026 if (fb_mode.xres > panel_info.vl_col ||
1027 fb_mode.yres > panel_info.vl_row) {
1028 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1029 fb_mode.xres, fb_mode.yres,
1030 panel_info.vl_col, panel_info.vl_row);
1035 if (p->name != NULL)
1036 debug("Trying compiled-in video modes\n");
1037 while (p->name != NULL) {
1038 if (strcmp(p->name, vm) == 0) {
1039 debug("Using video mode: '%s'\n", p->name);
1046 debug("Trying to decode video_mode: '%s'\n", vm);
1047 while (*vm != '\0') {
1048 if (*vm >= '0' && *vm <= '9') {
1051 val = simple_strtoul(vm, &end, 0);
1054 if (val > panel_info.vl_col)
1055 val = panel_info.vl_col;
1057 panel_info.vl_col = val;
1059 } else if (!yres_set) {
1060 if (val > panel_info.vl_row)
1061 val = panel_info.vl_row;
1063 panel_info.vl_row = val;
1065 } else if (!bpp_set) {
1076 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1077 end - vm, vm, color_depth);
1080 } else if (!refresh_set) {
1107 if (p->xres == 0 || p->yres == 0) {
1108 printf("Invalid video mode: %s\n", getenv("video_mode"));
1110 printf("Supported video modes are:");
1111 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1112 printf(" %s", p->name);
1117 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1118 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1119 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1123 panel_info.vl_col = p->xres;
1124 panel_info.vl_row = p->yres;
1126 switch (color_depth) {
1128 panel_info.vl_bpix = LCD_COLOR8;
1131 panel_info.vl_bpix = LCD_COLOR16;
1134 panel_info.vl_bpix = LCD_COLOR32;
1137 p->pixclock = KHZ2PICOS(refresh *
1138 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1139 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1141 debug("Pixel clock set to %lu.%03lu MHz\n",
1142 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1144 if (p != &fb_mode) {
1147 debug("Creating new display-timing node from '%s'\n",
1149 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1151 printf("Failed to create new display-timing node from '%s': %d\n",
1155 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1156 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1157 ARRAY_SIZE(stk5_lcd_pads));
1159 debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
1160 color_depth, refresh);
1162 if (karo_load_splashimage(0) == 0) {
1165 /* setup env variable for mxsfb display driver */
1166 snprintf(vmode, sizeof(vmode),
1167 "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
1168 p->xres, p->yres, p->left_margin, p->right_margin,
1169 p->upper_margin, p->lower_margin, p->hsync_len,
1170 p->vsync_len, p->sync, p->pixclock, color_depth);
1171 setenv("videomode", vmode);
1173 debug("Initializing LCD controller\n");
1176 setenv("videomode", NULL);
1178 debug("Skipping initialization of LCD controller\n");
1182 #define lcd_enabled 0
1183 #endif /* CONFIG_LCD */
1185 #ifndef CONFIG_ENV_IS_IN_MMC
1186 static void tx6_mmc_init(void)
1189 if (board_mmc_init(gd->bd) < 0)
1190 cpu_mmc_init(gd->bd);
1191 print_mmc_devices(',');
1194 static inline void tx6_mmc_init(void)
1199 static void stk5_board_init(void)
1203 ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1205 printf("Failed to request stk5_gpios: %d\n", ret);
1208 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1209 if (getenv_yesno("jtag_enable") != 0) {
1210 /* true if unset or set to one of: 'yYtT1' */
1211 imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads, ARRAY_SIZE(stk5_jtag_pads));
1213 debug("%s@%d: \n", __func__, __LINE__);
1216 static void stk5v3_board_init(void)
1218 debug("%s@%d: \n", __func__, __LINE__);
1220 debug("%s@%d: \n", __func__, __LINE__);
1224 static void stk5v5_board_init(void)
1231 ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1232 "Flexcan Transceiver");
1234 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1238 imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1239 TX6UL_GPIO_OUT_PAD_CTRL);
1242 static void tx6ul_set_cpu_clock(void)
1244 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1246 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1249 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1250 printf("%s detected; skipping cpu clock change\n",
1251 (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1254 if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1255 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1256 printf("CPU clock set to %lu.%03lu MHz\n",
1257 cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1259 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1263 int board_late_init(void)
1265 const char *baseboard;
1267 debug("%s@%d: \n", __func__, __LINE__);
1271 if (tx6_temp_check_enabled)
1272 check_cpu_temperature(1);
1274 tx6ul_set_cpu_clock();
1277 setenv_ulong("safeboot", 1);
1278 else if (wrsr & WRSR_TOUT)
1279 setenv_ulong("wdreset", 1);
1281 karo_fdt_move_fdt();
1283 baseboard = getenv("baseboard");
1287 printf("Baseboard: %s\n", baseboard);
1289 if (strncmp(baseboard, "stk5", 4) == 0) {
1290 if ((strlen(baseboard) == 4) ||
1291 strcmp(baseboard, "stk5-v3") == 0) {
1292 stk5v3_board_init();
1293 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1294 const char *otg_mode = getenv("otg_mode");
1296 if (otg_mode && strcmp(otg_mode, "host") == 0) {
1297 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1298 otg_mode, baseboard);
1299 setenv("otg_mode", "none");
1301 stk5v5_board_init();
1303 printf("WARNING: Unsupported STK5 board rev.: %s\n",
1306 } else if (strncmp(baseboard, "ulmb-", 5) == 0) {
1307 const char *otg_mode = getenv("otg_mode");
1309 if (otg_mode && strcmp(otg_mode, "host") == 0) {
1310 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1311 otg_mode, baseboard);
1312 setenv("otg_mode", "none");
1316 printf("WARNING: Unsupported baseboard: '%s'\n",
1323 debug("%s@%d: \n", __func__, __LINE__);
1329 #ifdef CONFIG_FEC_MXC
1335 static void tx6_init_mac(void)
1338 const char *baseboard = getenv("baseboard");
1340 imx_get_mac_from_fuse(0, mac);
1341 if (!is_valid_ethaddr(mac)) {
1342 printf("No valid MAC address programmed\n");
1345 printf("MAC addr from fuse: %pM\n", mac);
1346 if (!getenv("ethaddr"))
1347 eth_setenv_enetaddr("ethaddr", mac);
1349 if (!baseboard || strncmp(baseboard, "stk5", 4) == 0) {
1350 setenv("eth1addr", NULL);
1353 if (getenv("eth1addr"))
1355 imx_get_mac_from_fuse(1, mac);
1356 eth_setenv_enetaddr("eth1addr", mac);
1359 int board_eth_init(bd_t *bis)
1365 /* delay at least 21ms for the PHY internal POR signal to deassert */
1368 imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
1369 ARRAY_SIZE(tx6ul_enet1_pads));
1371 /* Deassert RESET to the external phys */
1372 gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
1374 if (getenv("ethaddr")) {
1375 ret = fecmxc_initialize_multi(bis, 0, 0, ENET_BASE_ADDR);
1377 printf("failed to initialize FEC0: %d\n", ret);
1381 if (getenv("eth1addr")) {
1382 ret = gpio_request_array(tx6ul_fec2_gpios,
1383 ARRAY_SIZE(tx6ul_fec2_gpios));
1385 printf("Failed to request tx6ul_fec2_gpios: %d\n", ret);
1387 imx_iomux_v3_setup_multiple_pads(tx6ul_enet2_pads,
1388 ARRAY_SIZE(tx6ul_enet2_pads));
1390 writel(0x00100000, 0x020c80e4); /* assert ENET2_125M_EN */
1392 /* Minimum PHY reset duration */
1394 gpio_set_value(TX6UL_FEC2_RST_GPIO, 1);
1395 /* Wait for PHY internal POR to finish */
1398 ret = fecmxc_initialize_multi(bis, 1, 2, ENET2_BASE_ADDR);
1400 printf("failed to initialize FEC1: %d\n", ret);
1406 #endif /* CONFIG_FEC_MXC */
1408 #ifdef CONFIG_SERIAL_TAG
1409 void get_board_serial(struct tag_serialnr *serialnr)
1411 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1412 struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1414 serialnr->low = readl(&fuse->cfg0);
1415 serialnr->high = readl(&fuse->cfg1);
1419 #if defined(CONFIG_OF_BOARD_SETUP)
1420 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1421 #include <jffs2/jffs2.h>
1422 #include <mtd_node.h>
1423 static struct node_info nodes[] = {
1424 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1427 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1430 static const char *tx6_touchpanels[] = {
1436 int ft_board_setup(void *blob, bd_t *bd)
1438 const char *baseboard = getenv("baseboard");
1439 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1440 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1443 ret = fdt_increase_size(blob, 4096);
1445 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1449 karo_fdt_enable_node(blob, "stk5led", 0);
1451 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1453 karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1454 ARRAY_SIZE(tx6_touchpanels));
1455 karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1456 karo_fdt_fixup_flexcan(blob, stk5_v5);
1458 karo_fdt_update_fb_mode(blob, video_mode);
1462 #endif /* CONFIG_OF_BOARD_SETUP */