board/sandburst/metrobox/metrobox.c

   1 /*
   2  *  Copyright (c) 2005
   3  *  Travis B. Sawyer,  Sandburst Corporation, tsawyer@sandburst.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23 #include <config.h>
  24 #include <common.h>
  25 #include <command.h>
  26 #include "metrobox.h"
  27 #include "metrobox_version.h"
  28 #include <timestamp.h>
  29 #include <asm/processor.h>
  30 #include <asm/io.h>
  31 #include <spd_sdram.h>
  32 #include <i2c.h>
  33 #include "../common/ppc440gx_i2c.h"
  34 #include "../common/sb_common.h"
  35
  36 void fpga_init (void);
  37
  38 METROBOX_BOARD_ID_ST board_id_as[] =
  39 {       {"Undefined"},                      /* Not specified */
  40         {"2x10Gb"},                         /* 2 ports, 10 GbE */
  41         {"20x1Gb"},                         /* 20 ports, 1 GbE */
  42         {"Reserved"},                        /* Reserved for future use */
  43 };
  44
  45 /*************************************************************************
  46  *  board_early_init_f
  47  *
  48  *  Setup chip selects, initialize the Opto-FPGA, initialize
  49  *  interrupt polarity and triggers.
  50  ************************************************************************/
  51 int board_early_init_f (void)
  52 {
  53         ppc440_gpio_regs_t *gpio_regs;
  54
  55         /* Enable GPIO interrupts */
  56         mtsdr(sdr_pfc0, 0x00103E00);
  57
  58         /* Setup access for LEDs, and system topology info */
  59         gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
  60         gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
  61         gpio_regs->tri_state  = SBCOMMON_GPIO_DBGLEDS;
  62
  63         /* Turn on all the leds for now */
  64         gpio_regs->out = SBCOMMON_GPIO_LEDS;
  65
  66         /*--------------------------------------------------------------------+
  67           | Initialize EBC CONFIG
  68           +-------------------------------------------------------------------*/
  69         mtebc(xbcfg,
  70               EBC_CFG_LE_UNLOCK    | EBC_CFG_PTD_ENABLE |
  71               EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
  72               EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
  73               EBC_CFG_EMC_DEFAULT  | EBC_CFG_PME_DISABLE |
  74               EBC_CFG_PR_32);
  75
  76         /*--------------------------------------------------------------------+
  77           | 1/2 MB FLASH. Initialize bank 0 with default values.
  78           +-------------------------------------------------------------------*/
  79         mtebc(pb0ap,
  80               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
  81               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
  82               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
  83               EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
  84               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
  85               EBC_BXAP_PEN_DISABLED);
  86
  87         mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
  88               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
  89         /*--------------------------------------------------------------------+
  90           | 8KB NVRAM/RTC. Initialize bank 1 with default values.
  91           +-------------------------------------------------------------------*/
  92         mtebc(pb1ap,
  93               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
  94               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
  95               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
  96               EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
  97               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
  98               EBC_BXAP_PEN_DISABLED);
  99
 100         mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
 101               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
 102
 103         /*--------------------------------------------------------------------+
 104           | Compact Flash, uses 2 Chip Selects (2 & 6)
 105           +-------------------------------------------------------------------*/
 106         mtebc(pb2ap,
 107               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
 108               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 109               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 110               EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
 111               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 112               EBC_BXAP_PEN_DISABLED);
 113
 114         mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |
 115               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
 116
 117         /*--------------------------------------------------------------------+
 118           | OPTO & OFEM FPGA. Initialize bank 3 with default values.
 119           +-------------------------------------------------------------------*/
 120         mtebc(pb3ap,
 121               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 122               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 123               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 124               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 125               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 126
 127         mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48200000) |
 128               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 129
 130         /*--------------------------------------------------------------------+
 131           | MAC A for metrobox
 132           | MAC A & B for Kamino.  OFEM FPGA decodes the addresses
 133           | Initialize bank 4 with default values.
 134           +-------------------------------------------------------------------*/
 135         mtebc(pb4ap,
 136               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 137               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 138               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 139               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 140               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 141
 142         mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |
 143               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 144
 145         /*--------------------------------------------------------------------+
 146           | Metrobox MAC B  Initialize bank 5 with default values.
 147           | KA REF FPGA  Initialize bank 5 with default values.
 148           +-------------------------------------------------------------------*/
 149         mtebc(pb5ap,
 150               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 151               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 152               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 153               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 154               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 155
 156         mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48700000) |
 157               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 158
 159         /*--------------------------------------------------------------------+
 160           | Compact Flash, uses 2 Chip Selects (2 & 6)
 161           +-------------------------------------------------------------------*/
 162         mtebc(pb6ap,
 163               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
 164               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 165               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 166               EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
 167               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 168               EBC_BXAP_PEN_DISABLED);
 169
 170         mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |
 171               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
 172
 173         /*--------------------------------------------------------------------+
 174           | BME-32. Initialize bank 7 with default values.
 175           +-------------------------------------------------------------------*/
 176         mtebc(pb7ap,
 177               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 178               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 179               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 180               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 181               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 182
 183         mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
 184               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 185
 186         /*--------------------------------------------------------------------+
 187          * Setup the interrupt controller polarities, triggers, etc.
 188          +-------------------------------------------------------------------*/
 189         /*
 190          * Because of the interrupt handling rework to handle 440GX interrupts
 191          * with the common code, we needed to change names of the UIC registers.
 192          * Here the new relationship:
 193          *
 194          * U-Boot name  440GX name
 195          * -----------------------
 196          * UIC0         UICB0
 197          * UIC1         UIC0
 198          * UIC2         UIC1
 199          * UIC3         UIC2
 200          */
 201         mtdcr (uic1sr, 0xffffffff);     /* clear all */
 202         mtdcr (uic1er, 0x00000000);     /* disable all */
 203         mtdcr (uic1cr, 0x00000000);     /* all non- critical */
 204         mtdcr (uic1pr, 0xfffffe03);     /* polarity */
 205         mtdcr (uic1tr, 0x01c00000);     /* trigger edge vs level */
 206         mtdcr (uic1vr, 0x00000001);     /* int31 highest, base=0x000 */
 207         mtdcr (uic1sr, 0xffffffff);     /* clear all */
 208
 209         mtdcr (uic2sr, 0xffffffff);     /* clear all */
 210         mtdcr (uic2er, 0x00000000);     /* disable all */
 211         mtdcr (uic2cr, 0x00000000);     /* all non-critical */
 212         mtdcr (uic2pr, 0xffffc8ff);     /* polarity */
 213         mtdcr (uic2tr, 0x00ff0000);     /* trigger edge vs level */
 214         mtdcr (uic2vr, 0x00000001);     /* int31 highest, base=0x000 */
 215         mtdcr (uic2sr, 0xffffffff);     /* clear all */
 216
 217         mtdcr (uic3sr, 0xffffffff);     /* clear all */
 218         mtdcr (uic3er, 0x00000000);     /* disable all */
 219         mtdcr (uic3cr, 0x00000000);     /* all non-critical */
 220         mtdcr (uic3pr, 0xffff83ff);     /* polarity */
 221         mtdcr (uic3tr, 0x00ff8c0f);     /* trigger edge vs level */
 222         mtdcr (uic3vr, 0x00000001);     /* int31 highest, base=0x000 */
 223         mtdcr (uic3sr, 0xffffffff);     /* clear all */
 224
 225         mtdcr (uic0sr, 0xfc000000);     /* clear all */
 226         mtdcr (uic0er, 0x00000000);     /* disable all */
 227         mtdcr (uic0cr, 0x00000000);     /* all non-critical */
 228         mtdcr (uic0pr, 0xfc000000);
 229         mtdcr (uic0tr, 0x00000000);
 230         mtdcr (uic0vr, 0x00000001);
 231
 232         fpga_init();
 233
 234         return 0;
 235 }
 236
 237 /*************************************************************************
 238  *  checkboard
 239  *
 240  *  Dump pertinent info to the console
 241  ************************************************************************/
 242 int checkboard (void)
 243 {
 244         sys_info_t sysinfo;
 245         unsigned char brd_rev, brd_id;
 246         unsigned short sernum;
 247         unsigned char opto_rev, opto_id;
 248         OPTO_FPGA_REGS_ST *opto_ps;
 249
 250         opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
 251
 252         opto_rev = (unsigned char)((opto_ps->revision_ul &
 253                                     SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
 254                                    >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
 255
 256         opto_id = (unsigned char)((opto_ps->revision_ul &
 257                                    SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK)
 258                                   >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT);
 259
 260         brd_rev = (unsigned char)((opto_ps->boardinfo_ul &
 261                                    SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK)
 262                                   >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT);
 263
 264         brd_id = (unsigned char)((opto_ps->boardinfo_ul &
 265                                   SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK)
 266                                  >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT);
 267
 268         get_sys_info (&sysinfo);
 269
 270         sernum = sbcommon_get_serial_number();
 271         printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum);
 272         printf ("%s\n", METROBOX_U_BOOT_REL_STR);
 273
 274         printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
 275         if (sbcommon_get_master()) {
 276                 printf("Slot 0 - Master\nSlave board");
 277                 if (sbcommon_secondary_present())
 278                         printf(" present\n");
 279                 else
 280                         printf(" not detected\n");
 281         } else {
 282                 printf("Slot 1 - Slave\n\n");
 283         }
 284
 285         printf ("OptoFPGA ID:\t0x%02X\tRev:  0x%02X\n", opto_id, opto_rev);
 286         printf ("Board Rev:\t0x%02X\tID:  %s\n", brd_rev, board_id_as[brd_id].name);
 287
 288         /* Fix the ack in the bme 32 */
 289         udelay(5000);
 290         out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
 291         asm("eieio");
 292
 293
 294         return (0);
 295 }
 296
 297 /*************************************************************************
 298  *  misc_init_f
 299  *
 300  *  Initialize I2C bus one to gain access to the fans
 301  ************************************************************************/
 302 int misc_init_f (void)
 303 {
 304         /* Turn on i2c bus 1 */
 305         puts ("I2C1:  ");
 306         i2c1_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 307         puts ("ready\n");
 308
 309         /* Turn on fans */
 310         sbcommon_fans();
 311
 312         return (0);
 313 }
 314
 315 /*************************************************************************
 316  *  misc_init_r
 317  *
 318  *  Do nothing.
 319  ************************************************************************/
 320 int misc_init_r (void)
 321 {
 322         unsigned short sernum;
 323         char envstr[255];
 324         unsigned char opto_rev;
 325         OPTO_FPGA_REGS_ST *opto_ps;
 326
 327         opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
 328
 329         if(NULL != getenv("secondserial")) {
 330             puts("secondserial is set, switching to second serial port\n");
 331             setenv("stderr", "serial1");
 332             setenv("stdout", "serial1");
 333             setenv("stdin", "serial1");
 334         }
 335
 336         setenv("ubrelver", METROBOX_U_BOOT_REL_STR);
 337
 338         memset(envstr, 0, 255);
 339         sprintf (envstr, "Built %s %s by %s",
 340                  U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
 341         setenv("bldstr", envstr);
 342         saveenv();
 343
 344         if( getenv("autorecover")) {
 345                 setenv("autorecover", NULL);
 346                 saveenv();
 347                 sernum = sbcommon_get_serial_number();
 348
 349                 printf("\nSetting up environment for automatic filesystem recovery\n");
 350                 /*
 351                  * Setup default bootargs
 352                  */
 353                 memset(envstr, 0, 255);
 354                 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
 355                         "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
 356                         sernum, sernum);
 357                 setenv("bootargs", envstr);
 358
 359                 /*
 360                  * Setup Default boot command
 361                  */
 362                 setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
 363                        "fatload ide 0 8100000 pramdisk;"
 364                        "bootm 8000000 8100000");
 365
 366                 printf("Done.  Please type allow the system to continue to boot\n");
 367         }
 368
 369         if( getenv("fakeled")) {
 370                 setenv("bootdelay", "-1");
 371                 saveenv();
 372                 printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
 373                 opto_rev = (unsigned char)((opto_ps->revision_ul &
 374                                             SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
 375                                            >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
 376
 377                 if(0x12 <= opto_rev) {
 378                         opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK;
 379                 }
 380         }
 381
 382         return (0);
 383 }
 384
 385 /*************************************************************************
 386  *  ide_set_reset
 387  ************************************************************************/
 388 #ifdef CONFIG_IDE_RESET
 389 void ide_set_reset(int on)
 390 {
 391         OPTO_FPGA_REGS_ST *opto_ps;
 392         opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
 393
 394         if (on) {               /* assert RESET */
 395             opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
 396         } else {                /* release RESET */
 397             opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
 398         }
 399 }
 400 #endif /* CONFIG_IDE_RESET */
 401
 402 /*************************************************************************
 403  *  fpga_init
 404  ************************************************************************/
 405 void fpga_init(void)
 406 {
 407         OPTO_FPGA_REGS_ST *opto_ps;
 408         unsigned char opto_rev;
 409         unsigned long tmp;
 410
 411         /* Ensure we have power all around */
 412         udelay(500);
 413
 414         /*
 415          * Take appropriate hw bits out of reset
 416          */
 417         opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
 418
 419         tmp =
 420             SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK |
 421             SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK |
 422             SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK |
 423             SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK |
 424             SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK |
 425             SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK |
 426             SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK |
 427             SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK |
 428             SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK |
 429             SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK |
 430             SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK |
 431             SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK |
 432             SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK |
 433             SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK |
 434             SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK |
 435             SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK |
 436             SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK |
 437             SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK;
 438         opto_ps->reset_ul = tmp;
 439         /*
 440          * Turn on the 'Slow Blink' for the System Error Led.
 441          * Ensure FPGA rev is up to at least rev 0x12
 442          */
 443         opto_rev = (unsigned char)((opto_ps->revision_ul &
 444                                     SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
 445                                    >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
 446         if(0x12 <= opto_rev) {
 447             opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT;
 448         }
 449
 450         asm("eieio");
 451
 452         return;
 453 }
 454
 455 int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 456 {
 457         unsigned short sernum;
 458         char envstr[255];
 459
 460         sernum = sbcommon_get_serial_number();
 461
 462         memset(envstr, 0, 255);
 463         /*
 464          * Setup our ip address
 465          */
 466         sprintf(envstr, "10.100.60.%d", sernum);
 467
 468         setenv("ipaddr", envstr);
 469         /*
 470          * Setup the host ip address
 471          */
 472         setenv("serverip", "10.100.17.10");
 473
 474         /*
 475          * Setup default bootargs
 476          */
 477         memset(envstr, 0, 255);
 478
 479         sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
 480                 "rw nfsroot=10.100.17.10:/home/metrobox/mbc%d "
 481                 "nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1"
 482                 ":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33",
 483                 sernum, sernum, sernum);
 484
 485         setenv("bootargs_nfs", envstr);
 486         setenv("bootargs", envstr);
 487
 488         /*
 489          * Setup CF bootargs
 490          */
 491         memset(envstr, 0, 255);
 492         sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
 493                 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
 494                 sernum, sernum);
 495
 496         setenv("bootargs_cf", envstr);
 497
 498         /*
 499          * Setup Default boot command
 500          */
 501         setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000");
 502         setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000");
 503
 504         /*
 505          * Setup compact flash boot command
 506          */
 507         setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000");
 508
 509         saveenv();
 510
 511
 512         return(1);
 513 }
 514
 515 int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 516 {
 517         unsigned short sernum;
 518         char envstr[255];
 519
 520         sernum = sbcommon_get_serial_number();
 521
 522         printf("\nSetting up environment for filesystem recovery\n");
 523         /*
 524          * Setup default bootargs
 525          */
 526         memset(envstr, 0, 255);
 527         sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
 528                 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none",
 529                 sernum, sernum);
 530
 531         setenv("bootargs", envstr);
 532
 533         /*
 534          * Setup Default boot command
 535          */
 536         setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
 537                "fatload ide 0 8100000 pramdisk;"
 538                "bootm 8000000 8100000");
 539
 540         printf("Done.  Please type boot<cr>.\nWhen the kernel has booted"
 541                " please type fsrecover.sh<cr>\n");
 542
 543         return(1);
 544 }
 545
 546 U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars,
 547            "mbsetup - Set environment to factory defaults\n", NULL);
 548
 549 U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover,
 550            "mbrecover - Set environment to allow for fs recovery\n", NULL);