3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
6 * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/imx-regs.h>
18 enum mxc_gpio_direction {
19 MXC_GPIO_DIRECTION_IN,
20 MXC_GPIO_DIRECTION_OUT,
23 #define GPIO_PER_BANK 32
25 struct mxc_gpio_plat {
27 struct gpio_regs *regs;
30 struct mxc_bank_info {
31 struct gpio_regs *regs;
34 #ifndef CONFIG_DM_GPIO
35 #define GPIO_TO_PORT(n) ((n) / 32)
37 /* GPIO port description */
38 static unsigned long gpio_ports[] = {
39 [0] = GPIO1_BASE_ADDR,
40 [1] = GPIO2_BASE_ADDR,
41 [2] = GPIO3_BASE_ADDR,
42 #if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX51) || \
43 defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
44 [3] = GPIO4_BASE_ADDR,
46 #if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
47 [4] = GPIO5_BASE_ADDR,
48 [5] = GPIO6_BASE_ADDR,
50 #if defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
51 [6] = GPIO7_BASE_ADDR,
55 static int mxc_gpio_direction(unsigned int gpio,
56 enum mxc_gpio_direction direction)
58 unsigned int port = GPIO_TO_PORT(gpio);
59 struct gpio_regs *regs;
62 if (port >= ARRAY_SIZE(gpio_ports)) {
63 printf("%s: Invalid GPIO %d\n", __func__, gpio);
69 regs = (struct gpio_regs *)gpio_ports[port];
71 l = readl(®s->gpio_dir);
74 case MXC_GPIO_DIRECTION_OUT:
77 case MXC_GPIO_DIRECTION_IN:
80 writel(l, ®s->gpio_dir);
85 int gpio_set_value(unsigned gpio, int value)
87 unsigned int port = GPIO_TO_PORT(gpio);
88 struct gpio_regs *regs;
91 if (port >= ARRAY_SIZE(gpio_ports)) {
92 printf("%s: Invalid GPIO %d\n", __func__, gpio);
98 regs = (struct gpio_regs *)gpio_ports[port];
100 l = readl(®s->gpio_dr);
105 writel(l, ®s->gpio_dr);
110 int gpio_get_value(unsigned gpio)
112 unsigned int port = GPIO_TO_PORT(gpio);
113 struct gpio_regs *regs;
116 if (port >= ARRAY_SIZE(gpio_ports)) {
117 printf("%s: Invalid GPIO %d\n", __func__, gpio);
123 regs = (struct gpio_regs *)gpio_ports[port];
125 if (readl(®s->gpio_dir) & (1 << gpio)) {
126 printf("WARNING: Reading status of output GPIO_%d_%d\n",
127 port - GPIO_TO_PORT(0), gpio);
128 val = (readl(®s->gpio_dr) >> gpio) & 0x01;
130 val = (readl(®s->gpio_psr) >> gpio) & 0x01;
135 int gpio_request(unsigned gpio, const char *label)
137 unsigned int port = GPIO_TO_PORT(gpio);
138 if (port >= ARRAY_SIZE(gpio_ports)) {
139 printf("%s: Invalid GPIO %d\n", __func__, gpio);
145 int gpio_free(unsigned gpio)
147 unsigned int port = GPIO_TO_PORT(gpio);
148 if (port >= ARRAY_SIZE(gpio_ports)) {
149 printf("%s: Invalid GPIO %d\n", __func__, gpio);
155 int gpio_direction_input(unsigned gpio)
157 return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_IN);
160 int gpio_direction_output(unsigned gpio, int value)
162 int ret = gpio_set_value(gpio, value);
167 return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT);
171 #ifdef CONFIG_DM_GPIO
172 static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)
176 val = readl(®s->gpio_dir);
178 return val & (1 << offset) ? 1 : 0;
181 static void mxc_gpio_bank_direction(struct gpio_regs *regs, int offset,
182 enum mxc_gpio_direction direction)
186 l = readl(®s->gpio_dir);
189 case MXC_GPIO_DIRECTION_OUT:
192 case MXC_GPIO_DIRECTION_IN:
195 writel(l, ®s->gpio_dir);
198 static void mxc_gpio_bank_set_value(struct gpio_regs *regs, int offset,
203 l = readl(®s->gpio_dr);
208 writel(l, ®s->gpio_dr);
211 static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset)
213 return (readl(®s->gpio_psr) >> offset) & 0x01;
216 /* set GPIO pin 'gpio' as an input */
217 static int mxc_gpio_direction_input(struct udevice *dev, unsigned offset)
219 struct mxc_bank_info *bank = dev_get_priv(dev);
221 /* Configure GPIO direction as input. */
222 mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_IN);
227 /* set GPIO pin 'gpio' as an output, with polarity 'value' */
228 static int mxc_gpio_direction_output(struct udevice *dev, unsigned offset,
231 struct mxc_bank_info *bank = dev_get_priv(dev);
233 /* Configure GPIO output value. */
234 mxc_gpio_bank_set_value(bank->regs, offset, value);
236 /* Configure GPIO direction as output. */
237 mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_OUT);
242 /* read GPIO IN value of pin 'gpio' */
243 static int mxc_gpio_get_value(struct udevice *dev, unsigned offset)
245 struct mxc_bank_info *bank = dev_get_priv(dev);
247 return mxc_gpio_bank_get_value(bank->regs, offset);
250 /* write GPIO OUT value to pin 'gpio' */
251 static int mxc_gpio_set_value(struct udevice *dev, unsigned offset,
254 struct mxc_bank_info *bank = dev_get_priv(dev);
256 mxc_gpio_bank_set_value(bank->regs, offset, value);
261 static int mxc_gpio_get_function(struct udevice *dev, unsigned offset)
263 struct mxc_bank_info *bank = dev_get_priv(dev);
265 /* GPIOF_FUNC is not implemented yet */
266 if (mxc_gpio_is_output(bank->regs, offset))
272 static const struct dm_gpio_ops gpio_mxc_ops = {
273 .direction_input = mxc_gpio_direction_input,
274 .direction_output = mxc_gpio_direction_output,
275 .get_value = mxc_gpio_get_value,
276 .set_value = mxc_gpio_set_value,
277 .get_function = mxc_gpio_get_function,
280 static const struct mxc_gpio_plat mxc_plat[] = {
281 { 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
282 { 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
283 { 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
284 #if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX51) || \
285 defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
286 { 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
288 #if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
289 { 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
290 { 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
292 #if defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
293 { 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
297 static int mxc_gpio_probe(struct udevice *dev)
299 struct mxc_bank_info *bank = dev_get_priv(dev);
300 struct mxc_gpio_plat *plat = dev_get_platdata(dev);
301 struct gpio_dev_priv *uc_priv = dev->uclass_priv;
305 banknum = plat->bank_index;
306 sprintf(name, "GPIO%d_", banknum + 1);
310 uc_priv->bank_name = str;
311 uc_priv->gpio_count = GPIO_PER_BANK;
312 bank->regs = plat->regs;
317 U_BOOT_DRIVER(gpio_mxc) = {
320 .ops = &gpio_mxc_ops,
321 .probe = mxc_gpio_probe,
322 .priv_auto_alloc_size = sizeof(struct mxc_bank_info),
325 U_BOOT_DEVICES(mxc_gpios) = {
326 { "gpio_mxc", &mxc_plat[0] },
327 { "gpio_mxc", &mxc_plat[1] },
328 { "gpio_mxc", &mxc_plat[2] },
329 #if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX51) || \
330 defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
331 { "gpio_mxc", &mxc_plat[3] },
333 #if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
334 { "gpio_mxc", &mxc_plat[4] },
335 { "gpio_mxc", &mxc_plat[5] },
337 #if defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
338 { "gpio_mxc", &mxc_plat[6] },