drivers/mmc/tegra_mmc.c

   1 /*
   2  * (C) Copyright 2009 SAMSUNG Electronics
   3  * Minkyu Kang <mk7.kang@samsung.com>
   4  * Jaehoon Chung <jh80.chung@samsung.com>
   5  * Portions Copyright 2011-2015 NVIDIA Corporation
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <bouncebuf.h>
  11 #include <common.h>
  12 #include <dm/device.h>
  13 #include <errno.h>
  14 #include <asm/gpio.h>
  15 #include <asm/io.h>
  16 #ifndef CONFIG_TEGRA186
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch-tegra/clk_rst.h>
  19 #endif
  20 #include <asm/arch-tegra/mmc.h>
  21 #include <asm/arch-tegra/tegra_mmc.h>
  22 #include <mmc.h>
  23
  24 /*
  25  * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that
  26  * should not be present. These are needed because newer Tegra SoCs support
  27  * only the standard clock/reset APIs, whereas older Tegra SoCs support only
  28  * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be
  29  * fixed to implement the standard APIs, and all drivers converted to solely
  30  * use the new standard APIs, with no ifdefs.
  31  */
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 struct mmc_host mmc_host[CONFIG_SYS_MMC_MAX_DEVICE];
  36
  37 #if !CONFIG_IS_ENABLED(OF_CONTROL)
  38 #error "Please enable device tree support to use this driver"
  39 #endif
  40
  41 static void mmc_set_power(struct mmc_host *host, unsigned short power)
  42 {
  43         u8 pwr = 0;
  44         debug("%s: power = %x\n", __func__, power);
  45
  46         if (power != (unsigned short)-1) {
  47                 switch (1 << power) {
  48                 case MMC_VDD_165_195:
  49                         pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8;
  50                         break;
  51                 case MMC_VDD_29_30:
  52                 case MMC_VDD_30_31:
  53                         pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0;
  54                         break;
  55                 case MMC_VDD_32_33:
  56                 case MMC_VDD_33_34:
  57                         pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3;
  58                         break;
  59                 }
  60         }
  61         debug("%s: pwr = %X\n", __func__, pwr);
  62
  63         /* Set the bus voltage first (if any) */
  64         writeb(pwr, &host->reg->pwrcon);
  65         if (pwr == 0)
  66                 return;
  67
  68         /* Now enable bus power */
  69         pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER;
  70         writeb(pwr, &host->reg->pwrcon);
  71 }
  72
  73 static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data,
  74                                 struct bounce_buffer *bbstate)
  75 {
  76         unsigned char ctrl;
  77
  78
  79         debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n",
  80                 bbstate->bounce_buffer, bbstate->user_buffer, data->blocks,
  81                 data->blocksize);
  82
  83         writel((u32)(unsigned long)bbstate->bounce_buffer, &host->reg->sysad);
  84         /*
  85          * DMASEL[4:3]
  86          * 00 = Selects SDMA
  87          * 01 = Reserved
  88          * 10 = Selects 32-bit Address ADMA2
  89          * 11 = Selects 64-bit Address ADMA2
  90          */
  91         ctrl = readb(&host->reg->hostctl);
  92         ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
  93         ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
  94         writeb(ctrl, &host->reg->hostctl);
  95
  96         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
  97         writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize);
  98         writew(data->blocks, &host->reg->blkcnt);
  99 }
 100
 101 static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
 102 {
 103         unsigned short mode;
 104         debug(" mmc_set_transfer_mode called\n");
 105         /*
 106          * TRNMOD
 107          * MUL1SIN0[5]  : Multi/Single Block Select
 108          * RD1WT0[4]    : Data Transfer Direction Select
 109          *      1 = read
 110          *      0 = write
 111          * ENACMD12[2]  : Auto CMD12 Enable
 112          * ENBLKCNT[1]  : Block Count Enable
 113          * ENDMA[0]     : DMA Enable
 114          */
 115         mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
 116                 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
 117
 118         if (data->blocks > 1)
 119                 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
 120
 121         if (data->flags & MMC_DATA_READ)
 122                 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
 123
 124         writew(mode, &host->reg->trnmod);
 125 }
 126
 127 static int mmc_wait_inhibit(struct mmc_host *host,
 128                             struct mmc_cmd *cmd,
 129                             struct mmc_data *data,
 130                             unsigned int timeout)
 131 {
 132         /*
 133          * PRNSTS
 134          * CMDINHDAT[1] : Command Inhibit (DAT)
 135          * CMDINHCMD[0] : Command Inhibit (CMD)
 136          */
 137         unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
 138
 139         /*
 140          * We shouldn't wait for data inhibit for stop commands, even
 141          * though they might use busy signaling
 142          */
 143         if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
 144                 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
 145
 146         while (readl(&host->reg->prnsts) & mask) {
 147                 if (timeout == 0) {
 148                         printf("%s: timeout error\n", __func__);
 149                         return -1;
 150                 }
 151                 timeout--;
 152                 udelay(1000);
 153         }
 154
 155         return 0;
 156 }
 157
 158 static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd,
 159                         struct mmc_data *data, struct bounce_buffer *bbstate)
 160 {
 161         struct mmc_host *host = mmc->priv;
 162         int flags, i;
 163         int result;
 164         unsigned int mask = 0;
 165         unsigned int retry = 0x100000;
 166         debug(" mmc_send_cmd called\n");
 167
 168         result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */);
 169
 170         if (result < 0)
 171                 return result;
 172
 173         if (data)
 174                 mmc_prepare_data(host, data, bbstate);
 175
 176         debug("cmd->arg: %08x\n", cmd->cmdarg);
 177         writel(cmd->cmdarg, &host->reg->argument);
 178
 179         if (data)
 180                 mmc_set_transfer_mode(host, data);
 181
 182         if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
 183                 return -1;
 184
 185         /*
 186          * CMDREG
 187          * CMDIDX[13:8] : Command index
 188          * DATAPRNT[5]  : Data Present Select
 189          * ENCMDIDX[4]  : Command Index Check Enable
 190          * ENCMDCRC[3]  : Command CRC Check Enable
 191          * RSPTYP[1:0]
 192          *      00 = No Response
 193          *      01 = Length 136
 194          *      10 = Length 48
 195          *      11 = Length 48 Check busy after response
 196          */
 197         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 198                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
 199         else if (cmd->resp_type & MMC_RSP_136)
 200                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
 201         else if (cmd->resp_type & MMC_RSP_BUSY)
 202                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
 203         else
 204                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
 205
 206         if (cmd->resp_type & MMC_RSP_CRC)
 207                 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
 208         if (cmd->resp_type & MMC_RSP_OPCODE)
 209                 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
 210         if (data)
 211                 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
 212
 213         debug("cmd: %d\n", cmd->cmdidx);
 214
 215         writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
 216
 217         for (i = 0; i < retry; i++) {
 218                 mask = readl(&host->reg->norintsts);
 219                 /* Command Complete */
 220                 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
 221                         if (!data)
 222                                 writel(mask, &host->reg->norintsts);
 223                         break;
 224                 }
 225         }
 226
 227         if (i == retry) {
 228                 printf("%s: waiting for status update\n", __func__);
 229                 writel(mask, &host->reg->norintsts);
 230                 return -ETIMEDOUT;
 231         }
 232
 233         if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
 234                 /* Timeout Error */
 235                 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
 236                 writel(mask, &host->reg->norintsts);
 237                 return -ETIMEDOUT;
 238         } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
 239                 /* Error Interrupt */
 240                 debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
 241                 writel(mask, &host->reg->norintsts);
 242                 return -1;
 243         }
 244
 245         if (cmd->resp_type & MMC_RSP_PRESENT) {
 246                 if (cmd->resp_type & MMC_RSP_136) {
 247                         /* CRC is stripped so we need to do some shifting. */
 248                         for (i = 0; i < 4; i++) {
 249                                 unsigned long offset =
 250                                         (unsigned long)(&host->reg->rspreg3 - i);
 251                                 cmd->response[i] = readl(offset) << 8;
 252
 253                                 if (i != 3) {
 254                                         cmd->response[i] |=
 255                                                 readb(offset - 1);
 256                                 }
 257                                 debug("cmd->resp[%d]: %08x\n",
 258                                                 i, cmd->response[i]);
 259                         }
 260                 } else if (cmd->resp_type & MMC_RSP_BUSY) {
 261                         for (i = 0; i < retry; i++) {
 262                                 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
 263                                 if (readl(&host->reg->prnsts)
 264                                         & (1 << 20))    /* DAT[0] */
 265                                         break;
 266                         }
 267
 268                         if (i == retry) {
 269                                 printf("%s: card is still busy\n", __func__);
 270                                 writel(mask, &host->reg->norintsts);
 271                                 return -ETIMEDOUT;
 272                         }
 273
 274                         cmd->response[0] = readl(&host->reg->rspreg0);
 275                         debug("cmd->resp[0]: %08x\n", cmd->response[0]);
 276                 } else {
 277                         cmd->response[0] = readl(&host->reg->rspreg0);
 278                         debug("cmd->resp[0]: %08x\n", cmd->response[0]);
 279                 }
 280         }
 281
 282         if (data) {
 283                 unsigned long   start = get_timer(0);
 284
 285                 while (1) {
 286                         mask = readl(&host->reg->norintsts);
 287
 288                         if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
 289                                 /* Error Interrupt */
 290                                 writel(mask, &host->reg->norintsts);
 291                                 printf("%s: error during transfer: 0x%08x\n",
 292                                                 __func__, mask);
 293                                 return -1;
 294                         } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
 295                                 /*
 296                                  * DMA Interrupt, restart the transfer where
 297                                  * it was interrupted.
 298                                  */
 299                                 unsigned int address = readl(&host->reg->sysad);
 300
 301                                 debug("DMA end\n");
 302                                 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
 303                                        &host->reg->norintsts);
 304                                 writel(address, &host->reg->sysad);
 305                         } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
 306                                 /* Transfer Complete */
 307                                 debug("r/w is done\n");
 308                                 break;
 309                         } else if (get_timer(start) > 8000UL) {
 310                                 writel(mask, &host->reg->norintsts);
 311                                 printf("%s: MMC Timeout\n"
 312                                        "    Interrupt status        0x%08x\n"
 313                                        "    Interrupt status enable 0x%08x\n"
 314                                        "    Interrupt signal enable 0x%08x\n"
 315                                        "    Present status          0x%08x\n",
 316                                        __func__, mask,
 317                                        readl(&host->reg->norintstsen),
 318                                        readl(&host->reg->norintsigen),
 319                                        readl(&host->reg->prnsts));
 320                                 return -1;
 321                         }
 322                 }
 323                 writel(mask, &host->reg->norintsts);
 324         }
 325
 326         udelay(1000);
 327         return 0;
 328 }
 329
 330 static int tegra_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 331                         struct mmc_data *data)
 332 {
 333         void *buf;
 334         unsigned int bbflags;
 335         size_t len;
 336         struct bounce_buffer bbstate;
 337         int ret;
 338
 339         if (data) {
 340                 if (data->flags & MMC_DATA_READ) {
 341                         buf = data->dest;
 342                         bbflags = GEN_BB_WRITE;
 343                 } else {
 344                         buf = (void *)data->src;
 345                         bbflags = GEN_BB_READ;
 346                 }
 347                 len = data->blocks * data->blocksize;
 348
 349                 bounce_buffer_start(&bbstate, buf, len, bbflags);
 350         }
 351
 352         ret = mmc_send_cmd_bounced(mmc, cmd, data, &bbstate);
 353
 354         if (data)
 355                 bounce_buffer_stop(&bbstate);
 356
 357         return ret;
 358 }
 359
 360 static void mmc_change_clock(struct mmc_host *host, uint clock)
 361 {
 362         int div;
 363         unsigned short clk;
 364         unsigned long timeout;
 365
 366         debug(" mmc_change_clock called\n");
 367
 368         /*
 369          * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0
 370          */
 371         if (clock == 0)
 372                 goto out;
 373 #ifdef CONFIG_TEGRA186
 374         {
 375                 ulong rate = clk_set_rate(&host->clk, clock);
 376                 div = (rate + clock - 1) / clock;
 377         }
 378 #else
 379         clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock,
 380                                     &div);
 381 #endif
 382         debug("div = %d\n", div);
 383
 384         writew(0, &host->reg->clkcon);
 385
 386         /*
 387          * CLKCON
 388          * SELFREQ[15:8]        : base clock divided by value
 389          * ENSDCLK[2]           : SD Clock Enable
 390          * STBLINTCLK[1]        : Internal Clock Stable
 391          * ENINTCLK[0]          : Internal Clock Enable
 392          */
 393         div >>= 1;
 394         clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
 395                TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
 396         writew(clk, &host->reg->clkcon);
 397
 398         /* Wait max 10 ms */
 399         timeout = 10;
 400         while (!(readw(&host->reg->clkcon) &
 401                  TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
 402                 if (timeout == 0) {
 403                         printf("%s: timeout error\n", __func__);
 404                         return;
 405                 }
 406                 timeout--;
 407                 udelay(1000);
 408         }
 409
 410         clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
 411         writew(clk, &host->reg->clkcon);
 412
 413         debug("mmc_change_clock: clkcon = %08X\n", clk);
 414
 415 out:
 416         host->clock = clock;
 417 }
 418
 419 static void tegra_mmc_set_ios(struct mmc *mmc)
 420 {
 421         struct mmc_host *host = mmc->priv;
 422         unsigned char ctrl;
 423         debug(" mmc_set_ios called\n");
 424
 425         debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
 426
 427         /* Change clock first */
 428         mmc_change_clock(host, mmc->clock);
 429
 430         ctrl = readb(&host->reg->hostctl);
 431
 432         /*
 433          * WIDE8[5]
 434          * 0 = Depend on WIDE4
 435          * 1 = 8-bit mode
 436          * WIDE4[1]
 437          * 1 = 4-bit mode
 438          * 0 = 1-bit mode
 439          */
 440         if (mmc->bus_width == 8)
 441                 ctrl |= (1 << 5);
 442         else if (mmc->bus_width == 4)
 443                 ctrl |= (1 << 1);
 444         else
 445                 ctrl &= ~(1 << 1);
 446
 447         writeb(ctrl, &host->reg->hostctl);
 448         debug("mmc_set_ios: hostctl = %08X\n", ctrl);
 449 }
 450
 451 static void pad_init_mmc(struct mmc_host *host)
 452 {
 453 #if defined(CONFIG_TEGRA30)
 454         enum periph_id id = host->mmc_id;
 455         u32 val;
 456
 457         debug("%s: sdmmc address = %08x, id = %d\n", __func__,
 458               (unsigned int)host->reg, id);
 459
 460         /* Set the pad drive strength for SDMMC1 or 3 only */
 461         if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
 462                 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
 463                       __func__);
 464                 return;
 465         }
 466
 467         val = readl(&host->reg->sdmemcmppadctl);
 468         val &= 0xFFFFFFF0;
 469         val |= MEMCOMP_PADCTRL_VREF;
 470         writel(val, &host->reg->sdmemcmppadctl);
 471
 472         val = readl(&host->reg->autocalcfg);
 473         val &= 0xFFFF0000;
 474         val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
 475         writel(val, &host->reg->autocalcfg);
 476 #endif
 477 }
 478
 479 static void mmc_reset(struct mmc_host *host, struct mmc *mmc)
 480 {
 481         unsigned int timeout;
 482         debug(" mmc_reset called\n");
 483
 484         /*
 485          * RSTALL[0] : Software reset for all
 486          * 1 = reset
 487          * 0 = work
 488          */
 489         writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst);
 490
 491         host->clock = 0;
 492
 493         /* Wait max 100 ms */
 494         timeout = 100;
 495
 496         /* hw clears the bit when it's done */
 497         while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
 498                 if (timeout == 0) {
 499                         printf("%s: timeout error\n", __func__);
 500                         return;
 501                 }
 502                 timeout--;
 503                 udelay(1000);
 504         }
 505
 506         /* Set SD bus voltage & enable bus power */
 507         mmc_set_power(host, fls(mmc->cfg->voltages) - 1);
 508         debug("%s: power control = %02X, host control = %02X\n", __func__,
 509                 readb(&host->reg->pwrcon), readb(&host->reg->hostctl));
 510
 511         /* Make sure SDIO pads are set up */
 512         pad_init_mmc(host);
 513 }
 514
 515 static int tegra_mmc_core_init(struct mmc *mmc)
 516 {
 517         struct mmc_host *host = mmc->priv;
 518         unsigned int mask;
 519         debug(" mmc_core_init called\n");
 520
 521         mmc_reset(host, mmc);
 522
 523         host->version = readw(&host->reg->hcver);
 524         debug("host version = %x\n", host->version);
 525
 526         /* mask all */
 527         writel(0xffffffff, &host->reg->norintstsen);
 528         writel(0xffffffff, &host->reg->norintsigen);
 529
 530         writeb(0xe, &host->reg->timeoutcon);    /* TMCLK * 2^27 */
 531         /*
 532          * NORMAL Interrupt Status Enable Register init
 533          * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
 534          * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
 535          * [3] ENSTADMAINT   : DMA boundary interrupt
 536          * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
 537          * [0] ENSTACMDCMPLT : Command Complete Status Enable
 538         */
 539         mask = readl(&host->reg->norintstsen);
 540         mask &= ~(0xffff);
 541         mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
 542                  TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
 543                  TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
 544                  TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
 545                  TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
 546         writel(mask, &host->reg->norintstsen);
 547
 548         /*
 549          * NORMAL Interrupt Signal Enable Register init
 550          * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
 551          */
 552         mask = readl(&host->reg->norintsigen);
 553         mask &= ~(0xffff);
 554         mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
 555         writel(mask, &host->reg->norintsigen);
 556
 557         return 0;
 558 }
 559
 560 static int tegra_mmc_getcd(struct mmc *mmc)
 561 {
 562         struct mmc_host *host = mmc->priv;
 563
 564         debug("tegra_mmc_getcd called\n");
 565
 566         if (dm_gpio_is_valid(&host->cd_gpio))
 567                 return dm_gpio_get_value(&host->cd_gpio);
 568
 569         return 1;
 570 }
 571
 572 static const struct mmc_ops tegra_mmc_ops = {
 573         .send_cmd       = tegra_mmc_send_cmd,
 574         .set_ios        = tegra_mmc_set_ios,
 575         .init           = tegra_mmc_core_init,
 576         .getcd          = tegra_mmc_getcd,
 577 };
 578
 579 static int do_mmc_init(int dev_index, bool removable)
 580 {
 581         struct mmc_host *host;
 582         struct mmc *mmc;
 583 #ifdef CONFIG_TEGRA186
 584         int ret;
 585 #endif
 586
 587         /* DT should have been read & host config filled in */
 588         host = &mmc_host[dev_index];
 589         if (!host->enabled)
 590                 return -1;
 591
 592         debug(" do_mmc_init: index %d, bus width %d pwr_gpio %d cd_gpio %d\n",
 593               dev_index, host->width, gpio_get_number(&host->pwr_gpio),
 594               gpio_get_number(&host->cd_gpio));
 595
 596         host->clock = 0;
 597
 598 #ifdef CONFIG_TEGRA186
 599         ret = reset_assert(&host->reset_ctl);
 600         if (ret)
 601                 return ret;
 602         ret = clk_enable(&host->clk);
 603         if (ret)
 604                 return ret;
 605         ret = clk_set_rate(&host->clk, 20000000);
 606         if (IS_ERR_VALUE(ret))
 607                 return ret;
 608         ret = reset_deassert(&host->reset_ctl);
 609         if (ret)
 610                 return ret;
 611 #else
 612         clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
 613 #endif
 614
 615         if (dm_gpio_is_valid(&host->pwr_gpio))
 616                 dm_gpio_set_value(&host->pwr_gpio, 1);
 617
 618         memset(&host->cfg, 0, sizeof(host->cfg));
 619
 620         host->cfg.name = "Tegra SD/MMC";
 621         host->cfg.ops = &tegra_mmc_ops;
 622
 623         host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 624         host->cfg.host_caps = 0;
 625         if (host->width == 8)
 626                 host->cfg.host_caps |= MMC_MODE_8BIT;
 627         if (host->width >= 4)
 628                 host->cfg.host_caps |= MMC_MODE_4BIT;
 629         host->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 630
 631         /*
 632          * min freq is for card identification, and is the highest
 633          *  low-speed SDIO card frequency (actually 400KHz)
 634          * max freq is highest HS eMMC clock as per the SD/MMC spec
 635          *  (actually 52MHz)
 636          */
 637         host->cfg.f_min = 375000;
 638         host->cfg.f_max = 48000000;
 639
 640         host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 641
 642         mmc = mmc_create(&host->cfg, host);
 643         mmc->block_dev.removable = removable;
 644         if (mmc == NULL)
 645                 return -1;
 646
 647         return 0;
 648 }
 649
 650 /**
 651  * Get the host address and peripheral ID for a node.
 652  *
 653  * @param blob          fdt blob
 654  * @param node          Device index (0-3)
 655  * @param host          Structure to fill in (reg, width, mmc_id)
 656  */
 657 static int mmc_get_config(const void *blob, int node, struct mmc_host *host,
 658                           bool *removablep)
 659 {
 660         debug("%s: node = %d\n", __func__, node);
 661
 662         host->enabled = fdtdec_get_is_enabled(blob, node);
 663
 664         host->reg = (struct tegra_mmc *)fdtdec_get_addr(blob, node, "reg");
 665         if ((fdt_addr_t)host->reg == FDT_ADDR_T_NONE) {
 666                 debug("%s: no sdmmc base reg info found\n", __func__);
 667                 return -FDT_ERR_NOTFOUND;
 668         }
 669
 670 #ifdef CONFIG_TEGRA186
 671         {
 672                 /*
 673                  * FIXME: This variable should go away when the MMC device
 674                  * actually is a udevice.
 675                  */
 676                 struct udevice dev;
 677                 int ret;
 678                 dev.of_offset = node;
 679                 ret = reset_get_by_name(&dev, "sdhci", &host->reset_ctl);
 680                 if (ret) {
 681                         debug("reset_get_by_name() failed: %d\n", ret);
 682                         return ret;
 683                 }
 684                 ret = clk_get_by_index(&dev, 0, &host->clk);
 685                 if (ret) {
 686                         debug("clk_get_by_index() failed: %d\n", ret);
 687                         return ret;
 688                 }
 689         }
 690 #else
 691         host->mmc_id = clock_decode_periph_id(blob, node);
 692         if (host->mmc_id == PERIPH_ID_NONE) {
 693                 debug("%s: could not decode periph id\n", __func__);
 694                 return -FDT_ERR_NOTFOUND;
 695         }
 696 #endif
 697
 698         /*
 699          * NOTE: mmc->bus_width is determined by mmc.c dynamically.
 700          * TBD: Override it with this value?
 701          */
 702         host->width = fdtdec_get_int(blob, node, "bus-width", 0);
 703         if (!host->width)
 704                 debug("%s: no sdmmc width found\n", __func__);
 705
 706         /* These GPIOs are optional */
 707         gpio_request_by_name_nodev(blob, node, "cd-gpios", 0, &host->cd_gpio,
 708                                    GPIOD_IS_IN);
 709         gpio_request_by_name_nodev(blob, node, "wp-gpios", 0, &host->wp_gpio,
 710                                    GPIOD_IS_IN);
 711         gpio_request_by_name_nodev(blob, node, "power-gpios", 0,
 712                                    &host->pwr_gpio, GPIOD_IS_OUT);
 713         *removablep = !fdtdec_get_bool(blob, node, "non-removable");
 714
 715         debug("%s: found controller at %p, width = %d, periph_id = %d\n",
 716                 __func__, host->reg, host->width,
 717 #ifndef CONFIG_TEGRA186
 718                 host->mmc_id
 719 #else
 720                 -1
 721 #endif
 722         );
 723         return 0;
 724 }
 725
 726 /*
 727  * Process a list of nodes, adding them to our list of SDMMC ports.
 728  *
 729  * @param blob          fdt blob
 730  * @param node_list     list of nodes to process (any <=0 are ignored)
 731  * @param count         number of nodes to process
 732  * @return 0 if ok, -1 on error
 733  */
 734 static int process_nodes(const void *blob, int node_list[], int count)
 735 {
 736         struct mmc_host *host;
 737         bool removable;
 738         int i, node;
 739
 740         debug("%s: count = %d\n", __func__, count);
 741
 742         /* build mmc_host[] for each controller */
 743         for (i = 0; i < count; i++) {
 744                 node = node_list[i];
 745                 if (node <= 0)
 746                         continue;
 747
 748                 host = &mmc_host[i];
 749                 host->id = i;
 750
 751                 if (mmc_get_config(blob, node, host, &removable)) {
 752                         printf("%s: failed to decode dev %d\n", __func__, i);
 753                         return -1;
 754                 }
 755                 do_mmc_init(i, removable);
 756         }
 757         return 0;
 758 }
 759
 760 void tegra_mmc_init(void)
 761 {
 762         int node_list[CONFIG_SYS_MMC_MAX_DEVICE], count;
 763         const void *blob = gd->fdt_blob;
 764         debug("%s entry\n", __func__);
 765
 766         /* See if any Tegra186 MMC controllers are present */
 767         count = fdtdec_find_aliases_for_id(blob, "mmc",
 768                 COMPAT_NVIDIA_TEGRA186_SDMMC, node_list,
 769                 CONFIG_SYS_MMC_MAX_DEVICE);
 770         debug("%s: count of Tegra186 sdhci nodes is %d\n", __func__, count);
 771         if (process_nodes(blob, node_list, count)) {
 772                 printf("%s: Error processing T186 mmc node(s)!\n", __func__);
 773                 return;
 774         }
 775
 776         /* See if any Tegra210 MMC controllers are present */
 777         count = fdtdec_find_aliases_for_id(blob, "mmc",
 778                 COMPAT_NVIDIA_TEGRA210_SDMMC, node_list,
 779                 CONFIG_SYS_MMC_MAX_DEVICE);
 780         debug("%s: count of Tegra210 sdhci nodes is %d\n", __func__, count);
 781         if (process_nodes(blob, node_list, count)) {
 782                 printf("%s: Error processing T210 mmc node(s)!\n", __func__);
 783                 return;
 784         }
 785
 786         /* See if any Tegra124 MMC controllers are present */
 787         count = fdtdec_find_aliases_for_id(blob, "mmc",
 788                 COMPAT_NVIDIA_TEGRA124_SDMMC, node_list,
 789                 CONFIG_SYS_MMC_MAX_DEVICE);
 790         debug("%s: count of Tegra124 sdhci nodes is %d\n", __func__, count);
 791         if (process_nodes(blob, node_list, count)) {
 792                 printf("%s: Error processing T124 mmc node(s)!\n", __func__);
 793                 return;
 794         }
 795
 796         /* See if any Tegra30 MMC controllers are present */
 797         count = fdtdec_find_aliases_for_id(blob, "mmc",
 798                 COMPAT_NVIDIA_TEGRA30_SDMMC, node_list,
 799                 CONFIG_SYS_MMC_MAX_DEVICE);
 800         debug("%s: count of T30 sdhci nodes is %d\n", __func__, count);
 801         if (process_nodes(blob, node_list, count)) {
 802                 printf("%s: Error processing T30 mmc node(s)!\n", __func__);
 803                 return;
 804         }
 805
 806         /* Now look for any Tegra20 MMC controllers */
 807         count = fdtdec_find_aliases_for_id(blob, "mmc",
 808                 COMPAT_NVIDIA_TEGRA20_SDMMC, node_list,
 809                 CONFIG_SYS_MMC_MAX_DEVICE);
 810         debug("%s: count of T20 sdhci nodes is %d\n", __func__, count);
 811         if (process_nodes(blob, node_list, count)) {
 812                 printf("%s: Error processing T20 mmc node(s)!\n", __func__);
 813                 return;
 814         }
 815 }