2 * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
3 * Rohit Choraria <rohitkc@ti.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
11 #include <asm/arch/mem.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/omap_gpmc.h>
14 #include <linux/mtd/nand_ecc.h>
15 #include <linux/bch.h>
16 #include <linux/compiler.h>
19 #include <asm/arch/elm.h>
23 static __maybe_unused struct nand_ecclayout hw_nand_oob =
24 GPMC_NAND_HW_ECC_LAYOUT;
25 static __maybe_unused struct nand_ecclayout hw_bch8_nand_oob =
26 GPMC_NAND_HW_BCH8_ECC_LAYOUT;
28 static struct gpmc __iomem *gpmc_cfg = (void __iomem *)GPMC_BASE;
30 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
31 static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
32 static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
34 static struct nand_bbt_descr bbt_main_descr = {
35 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
36 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
37 .offs = 0, /* may be overwritten depending on ECC layout */
39 .veroffs = 4, /* may be overwritten depending on ECC layout */
41 .pattern = bbt_pattern,
44 static struct nand_bbt_descr bbt_mirror_descr = {
45 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
46 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
47 .offs = 0, /* may be overwritten depending on ECC layout */
49 .veroffs = 4, /* may be overwritten depending on ECC layout */
51 .pattern = mirror_pattern,
55 #define PREFETCH_FIFOTHRESHOLD_MAX 0x40
56 #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
58 #define PREFETCH_ENABLEOPTIMIZEDACCESS (0x1 << 27)
60 #define GPMC_PREFETCH_STATUS_FIFO_CNT(val) (((val) >> 24) & 0x7F)
61 #define GPMC_PREFETCH_STATUS_COUNT(val) ((val) & 0x00003fff)
63 #define CS_NUM_SHIFT 24
64 #define ENABLE_PREFETCH (0x1 << 7)
65 #define DMA_MPU_MODE 2
67 #define OMAP_NAND_TIMEOUT_MS 5000
69 #define PRINT_REG(x) debug("+++ %.15s (0x%08x)=0x%08x\n", #x, &gpmc_cfg->x, readl(&gpmc_cfg->x))
71 #ifdef CONFIG_SYS_GPMC_PREFETCH_ENABLE
73 * gpmc_prefetch_enable - configures and starts prefetch transfer
74 * @cs: cs (chip select) number
75 * @fifo_th: fifo threshold to be used for read/ write
76 * @count: number of bytes to be transferred
77 * @is_write: prefetch read(0) or write post(1) mode
79 static inline void gpmc_prefetch_enable(int cs, int fifo_th,
80 unsigned int count, int is_write)
82 writel(count, &gpmc_cfg->pref_config2);
84 /* Set the prefetch read / post write and enable the engine.
85 * Set which cs is has requested for.
87 uint32_t val = (cs << CS_NUM_SHIFT) |
88 PREFETCH_ENABLEOPTIMIZEDACCESS |
89 PREFETCH_FIFOTHRESHOLD(fifo_th) |
92 writel(val, &gpmc_cfg->pref_config1);
94 /* Start the prefetch engine */
95 writel(0x1, &gpmc_cfg->pref_control);
99 * gpmc_prefetch_reset - disables and stops the prefetch engine
101 static inline void gpmc_prefetch_reset(void)
103 /* Stop the PFPW engine */
104 writel(0x0, &gpmc_cfg->pref_control);
106 /* Reset/disable the PFPW engine */
107 writel(0x0, &gpmc_cfg->pref_config1);
110 //#define FIFO_IOADDR (nand->IO_ADDR_R)
111 #define FIFO_IOADDR PISMO1_NAND_BASE
114 * read_buf_pref - read data from NAND controller into buffer
115 * @mtd: MTD device structure
116 * @buf: buffer to store date
117 * @len: number of bytes to read
119 static void read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
121 gpmc_prefetch_enable(cs, PREFETCH_FIFOTHRESHOLD_MAX, len, 0);
123 // Get number of bytes waiting in the FIFO
124 uint32_t read_bytes = GPMC_PREFETCH_STATUS_FIFO_CNT(readl(&gpmc_cfg->pref_status));
128 // Alignment of Destination Buffer
129 while (read_bytes && ((unsigned int)buf & 3)) {
130 *buf++ = readb(FIFO_IOADDR);
134 // Use maximum word size (32bit) inside this loop, because speed is limited by
135 // GPMC bus arbitration with a maximum transfer rate of 3.000.000/sec.
136 len -= read_bytes & ~3;
137 while (read_bytes >= 4) {
138 *((uint32_t*)buf) = readl(FIFO_IOADDR);
142 // Transfer the last (non-aligned) bytes only at the last iteration,
143 // to maintain full speed up to the end of the transfer.
144 if (read_bytes == len) {
146 *buf++ = readb(FIFO_IOADDR);
152 gpmc_prefetch_reset();
156 * write_buf_pref - write buffer to NAND controller
157 * @mtd: MTD device structure
159 * @len: number of bytes to write
161 static void write_buf_pref(struct mtd_info *mtd, const u_char *buf, int len)
163 /* configure and start prefetch transfer */
164 gpmc_prefetch_enable(cs, PREFETCH_FIFOTHRESHOLD_MAX, len, 1);
167 // Get number of free bytes in the FIFO
168 uint32_t write_bytes = GPMC_PREFETCH_STATUS_FIFO_CNT(readl(&gpmc_cfg->pref_status));
170 // don't write more bytes than requested
171 if (write_bytes > len)
174 // Alignment of Source Buffer
175 while (write_bytes && ((unsigned int)buf & 3)) {
176 writeb(*buf++, FIFO_IOADDR);
181 // Use maximum word size (32bit) inside this loop, because speed is limited by
182 // GPMC bus arbitration with a maximum transfer rate of 3.000.000/sec.
183 len -= write_bytes & ~3;
184 while (write_bytes >= 4) {
185 writel(*((uint32_t*)buf), FIFO_IOADDR);
190 // Transfer the last (non-aligned) bytes only at the last iteration,
191 // to maintain full speed up to the end of the transfer.
192 if (write_bytes == len) {
193 while (write_bytes) {
194 writeb(*buf++, FIFO_IOADDR);
201 /* wait for data to be flushed out before resetting the prefetch */
202 while ((len = GPMC_PREFETCH_STATUS_COUNT(readl(&gpmc_cfg->pref_status)))) {
203 debug("%u bytes still in FIFO\n", PREFETCH_FIFOTHRESHOLD_MAX - len);
207 /* disable and stop the PFPW engine */
208 gpmc_prefetch_reset();
210 #endif /* CONFIG_SYS_GPMC_PREFETCH_ENABLE */
213 * omap_nand_hwcontrol - Set the address pointers corretly for the
214 * following address/data/command operation
216 static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
219 register struct nand_chip *this = mtd->priv;
222 * Point the IO_ADDR to DATA and ADDRESS registers instead
226 case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
227 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
229 case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
230 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
232 case NAND_CTRL_CHANGE | NAND_NCE:
233 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
237 if (cmd != NAND_CMD_NONE)
238 writeb(cmd, this->IO_ADDR_W);
241 #ifdef CONFIG_SPL_BUILD
242 /* Check wait pin as dev ready indicator */
243 int omap_spl_dev_ready(struct mtd_info *mtd)
245 return readl(&gpmc_cfg->status) & (1 << 8);
250 * omap_hwecc_init - Initialize the Hardware ECC for NAND flash in
252 * @mtd: MTD device structure
255 static void __maybe_unused omap_hwecc_init(struct nand_chip *chip)
258 * Init ECC Control Register
259 * Clear all ECC | Enable Reg1
261 writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
262 writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_cfg->ecc_size_config);
266 * gen_true_ecc - This function will generate true ECC value, which
267 * can be used when correcting data read from NAND flash memory core
269 * @ecc_buf: buffer to store ecc code
271 * @return: re-formatted ECC value
273 static uint32_t gen_true_ecc(uint8_t *ecc_buf)
275 return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
276 ((ecc_buf[2] & 0x0F) << 8);
280 * omap_correct_data - Compares the ecc read from nand spare area with ECC
281 * registers values and corrects one bit error if it has occured
282 * Further details can be had from OMAP TRM and the following selected links:
283 * http://en.wikipedia.org/wiki/Hamming_code
284 * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
286 * @mtd: MTD device structure
288 * @read_ecc: ecc read from nand flash
289 * @calc_ecc: ecc read from ECC registers
291 * @return 0 if data is OK or corrected, else returns -1
293 static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
294 uint8_t *read_ecc, uint8_t *calc_ecc)
296 uint32_t orig_ecc, new_ecc, res, hm;
297 uint16_t parity_bits, byte;
300 /* Regenerate the orginal ECC */
301 orig_ecc = gen_true_ecc(read_ecc);
302 new_ecc = gen_true_ecc(calc_ecc);
303 /* Get the XOR of real ecc */
304 res = orig_ecc ^ new_ecc;
306 /* Get the hamming width */
308 /* Single bit errors can be corrected! */
310 /* Correctable data! */
311 parity_bits = res >> 16;
312 bit = (parity_bits & 0x7);
313 byte = (parity_bits >> 3) & 0x1FF;
314 /* Flip the bit to correct */
315 dat[byte] ^= (0x1 << bit);
316 } else if (hm == 1) {
317 printf("Error: Ecc is wrong\n");
318 /* ECC itself is corrupted */
322 * hm distance != parity pairs OR one, could mean 2 bit
323 * error OR potentially be on a blank page..
324 * orig_ecc: contains spare area data from nand flash.
325 * new_ecc: generated ecc while reading data area.
326 * Note: if the ecc = 0, all data bits from which it was
327 * generated are 0xFF.
328 * The 3 byte(24 bits) ecc is generated per 512byte
329 * chunk of a page. If orig_ecc(from spare area)
330 * is 0xFF && new_ecc(computed now from data area)=0x0,
331 * this means that data area is 0xFF and spare area is
332 * 0xFF. A sure sign of a erased page!
334 if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
336 printf("Error: Bad compare! failed\n");
337 /* detected 2 bit error */
345 * omap_calculate_ecc - Generate non-inverted ECC bytes.
347 * Using noninverted ECC can be considered ugly since writing a blank
348 * page ie. padding will clear the ECC bytes. This is no problem as
349 * long nobody is trying to write data on the seemingly unused page.
350 * Reading an erased page will produce an ECC mismatch between
351 * generated and read ECC bytes that has to be dealt with separately.
352 * E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
353 * is used, the result of read will be 0x0 while the ECC offsets of the
354 * spare area will be 0xFF which will result in an ECC mismatch.
355 * @mtd: MTD structure
357 * @ecc_code: ecc_code buffer
359 static int __maybe_unused omap_calculate_ecc(struct mtd_info *mtd,
360 const uint8_t *dat, uint8_t *ecc_code)
364 /* Start Reading from HW ECC1_Result = 0x200 */
365 val = readl(&gpmc_cfg->ecc1_result);
367 ecc_code[0] = val & 0xFF;
368 ecc_code[1] = (val >> 16) & 0xFF;
369 ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
372 * Stop reading anymore ECC vals and clear old results
373 * enable will be called if more reads are required
375 writel(0x000, &gpmc_cfg->ecc_config);
381 * omap_enable_ecc - This function enables the hardware ecc functionality
382 * @mtd: MTD device structure
383 * @mode: Read/Write mode
385 static void __maybe_unused omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
387 struct nand_chip *chip = mtd->priv;
388 uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
393 /* Clear the ecc result registers, select ecc reg as 1 */
394 writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
397 * Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes
398 * tell all regs to generate size0 sized regs
399 * we just have a single ECC engine for all CS
401 writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL,
402 &gpmc_cfg->ecc_size_config);
403 val = (dev_width << 7) | (cs << 1) | (1 << 0);
404 writel(val, &gpmc_cfg->ecc_config);
407 printf("Error: Unrecognized Mode[%d]!\n", mode);
412 * Generic BCH interface
414 struct nand_bch_priv {
418 struct bch_control *control;
426 /* GPMC ecc engine settings */
427 #define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */
428 #define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */
430 /* BCH nibbles for diff bch levels */
431 #define NAND_ECC_HW_BCH ((uint8_t)(NAND_ECC_HW_OOB_FIRST) + 1)
432 #define ECC_BCH4_NIBBLES 13
433 #define ECC_BCH8_NIBBLES 26
434 #define ECC_BCH16_NIBBLES 52
437 * This can be a single instance cause all current users have only one NAND
438 * with nearly the same setup (BCH8, some with ELM and others with sw BCH
440 * When some users with other BCH strength will exists this have to change!
442 static __maybe_unused struct nand_bch_priv bch_priv = {
443 .mode = NAND_ECC_HW_BCH,
445 .nibbles = ECC_BCH8_NIBBLES,
450 * omap_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in
452 * @mtd: MTD device structure
453 * @mode: Read/Write mode
456 static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode)
459 uint32_t dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
461 uint32_t unused_length = 0;
463 uint32_t wr_mode = BCH_WRAPMODE_6;
464 struct nand_bch_priv *bch = chip->priv;
466 /* Clear the ecc result registers, select ecc reg as 1 */
467 writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
470 wr_mode = BCH_WRAPMODE_1;
472 switch (bch->nibbles) {
473 case ECC_BCH4_NIBBLES:
476 case ECC_BCH8_NIBBLES:
479 case ECC_BCH16_NIBBLES:
485 * This is ecc_size_config for ELM mode.
486 * Here we are using different settings for read and write access and
487 * also depending on BCH strength.
491 /* write access only setup eccsize1 config */
492 val = ((unused_length + bch->nibbles) << 22);
498 * by default eccsize0 selected for ecc1resultsize
501 val = (bch->nibbles << 12);
502 /* eccsize1 config */
503 val |= (unused_length << 22);
508 * This ecc_size_config setting is for BCH sw library.
510 * Note: we only support BCH8 currently with BCH sw library!
511 * Should be really easy to adopt to BCH4, however some omap3 have
514 * Here we are using wrapping mode 6 both for reading and writing, with:
515 * size0 = 0 (no additional protected byte in spare area)
516 * size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
518 val = (32 << 22) | (0 << 12);
520 /* ecc size configuration */
521 writel(val, &gpmc_cfg->ecc_size_config);
524 * Configure the ecc engine in gpmc
525 * We assume 512 Byte sector pages for access to NAND.
527 val = 1 << 16; /* select BCH mode */
528 val |= bch->type << 12; /* setup BCH type */
529 val |= wr_mode << 8; /* setup wrapping mode */
530 val |= dev_width << 7; /* setup device width (16 or 8 bit) */
531 val |= (chip->ecc.size / 512 - 1) << 4; /* set ECC size */
532 val |= cs << 1; /* setup chip select to work on */
533 val |= 1 << 0; /* enable ECC engine */
535 debug("set ECC_CONFIG=0x%08x\n", val);
536 writel(val, &gpmc_cfg->ecc_config);
540 * omap_enable_ecc_bch - This function enables the bch h/w ecc functionality
541 * @mtd: MTD device structure
542 * @mode: Read/Write mode
545 static void omap_enable_ecc_bch(struct mtd_info *mtd, int32_t mode)
547 struct nand_chip *chip = mtd->priv;
549 omap_hwecc_init_bch(chip, mode);
553 * omap_ecc_disable - Disable H/W ECC calculation
555 * @mtd: MTD device structure
557 static void __maybe_unused omap_ecc_disable(struct mtd_info *mtd)
559 writel((readl(&gpmc_cfg->ecc_config) & ~0x1), &gpmc_cfg->ecc_config);
563 * BCH8 support (needs ELM and thus AM33xx-only)
567 * omap_read_bch8_result - Read BCH result for BCH8 level
569 * @mtd: MTD device structure
570 * @big_endian: When set read register 3 first
571 * @ecc_code: Read syndrome from BCH result registers
573 static void omap_read_bch8_result(struct mtd_info *mtd, uint8_t big_endian,
578 struct nand_chip *chip = mtd->priv;
579 int num_steps = chip->ecc.size / 512;
581 for (k = 0; k < num_steps; k++) {
583 ptr = &gpmc_cfg->bch_result_0_3[k].bch_result_x[3];
584 ecc_code[i++] = readl(ptr) & 0xFF;
586 for (j = 0; j < 3; j++) {
587 ecc_code[i++] = (readl(ptr) >> 24) & 0xFF;
588 ecc_code[i++] = (readl(ptr) >> 16) & 0xFF;
589 ecc_code[i++] = (readl(ptr) >> 8) & 0xFF;
590 ecc_code[i++] = readl(ptr) & 0xFF;
594 ptr = &gpmc_cfg->bch_result_0_3[k].bch_result_x[0];
595 for (j = 0; j < 3; j++) {
596 ecc_code[i++] = readl(ptr) & 0xFF;
597 ecc_code[i++] = (readl(ptr) >> 8) & 0xFF;
598 ecc_code[i++] = (readl(ptr) >> 16) & 0xFF;
599 ecc_code[i++] = (readl(ptr) >> 24) & 0xFF;
602 ecc_code[i++] = readl(ptr) & 0xFF;
604 ecc_code[i++] = 0; /* 14th byte is always zero */
609 * omap_rotate_ecc_bch - Rotate the syndrome bytes
611 * @mtd: MTD device structure
612 * @calc_ecc: ECC read from ECC registers
613 * @syndrome: Rotated syndrome will be returned in this array
616 static void omap_rotate_ecc_bch(struct mtd_info *mtd, uint8_t *calc_ecc,
619 struct nand_chip *chip = mtd->priv;
620 struct nand_bch_priv *bch = chip->priv;
639 for (i = 0, j = n_bytes - 1; i < n_bytes; i++, j--)
640 syndrome[i] = calc_ecc[j];
644 * omap_calculate_ecc_bch - Read BCH ECC result
646 * @mtd: MTD structure
648 * @ecc_code: ecc_code buffer
650 static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat,
653 struct nand_chip *chip = mtd->priv;
654 struct nand_bch_priv *bch = chip->priv;
655 uint8_t big_endian = 1;
658 if (bch->type == ECC_BCH8)
659 omap_read_bch8_result(mtd, big_endian, ecc_code);
660 else /* BCH4 and BCH16 currently not supported */
664 * Stop reading anymore ECC vals and clear old results
665 * enable will be called if more reads are required
667 omap_ecc_disable(mtd);
673 * omap_fix_errors_bch - Correct bch error in the data
675 * @mtd: MTD device structure
676 * @data: Data read from flash
677 * @error_count:Number of errors in data
678 * @error_loc: Locations of errors in the data
681 static void omap_fix_errors_bch(struct mtd_info *mtd, uint8_t *data,
682 uint32_t error_count, uint32_t *error_loc)
684 struct nand_chip *chip = mtd->priv;
685 struct nand_bch_priv *bch = chip->priv;
687 uint32_t error_byte_pos;
688 uint32_t error_bit_mask;
689 uint32_t last_bit = (bch->nibbles * 4) - 1;
691 /* Flip all bits as specified by the error location array. */
692 /* FOR( each found error location flip the bit ) */
693 for (count = 0; count < error_count; count++) {
694 if (error_loc[count] > last_bit) {
695 /* Remove the ECC spare bits from correction. */
696 error_loc[count] -= (last_bit + 1);
697 /* Offset bit in data region */
698 error_byte_pos = ((512 * 8) -
699 (error_loc[count]) - 1) / 8;
701 error_bit_mask = 0x1 << (error_loc[count] % 8);
702 /* Toggle the error bit to make the correction. */
703 data[error_byte_pos] ^= error_bit_mask;
709 * omap_correct_data_bch - Compares the ecc read from nand spare area
710 * with ECC registers values and corrects one bit error if it has occured
712 * @mtd: MTD device structure
714 * @read_ecc: ecc read from nand flash (ignored)
715 * @calc_ecc: ecc read from ECC registers
717 * @return 0 if data is OK or corrected, else returns -1
719 static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
720 uint8_t *read_ecc, uint8_t *calc_ecc)
722 struct nand_chip *chip = mtd->priv;
723 struct nand_bch_priv *bch = chip->priv;
724 uint8_t syndrome[28];
725 uint32_t error_count = 0;
726 uint32_t error_loc[8];
727 uint32_t i, ecc_flag;
728 int k, ecc_bytes, num_steps;
730 num_steps = chip->ecc.size / 512;
731 ecc_bytes = chip->ecc.bytes / num_steps;
733 for (k = 0; k < num_steps; k++) {
735 /* check if area is flashed */
736 for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++)
737 if (read_ecc[i] != 0xff)
742 /* check if any ecc error */
743 for (i = 0; (i < ecc_bytes) && !ecc_flag; i++)
744 if (calc_ecc[i] != 0)
752 elm_config((enum bch_level)(bch->type));
755 * while reading ECC result we read it in big endian.
756 * Hence while loading to ELM we have rotate to get the right endian.
758 omap_rotate_ecc_bch(mtd, calc_ecc, syndrome);
760 /* use elm module to check for errors */
761 if (elm_check_error(syndrome, bch->nibbles, &error_count,
763 printf("ECC: uncorrectable.\n");
767 /* correct bch error */
769 omap_fix_errors_bch(mtd, dat, error_count, error_loc);
771 read_ecc += ecc_bytes;
772 calc_ecc += ecc_bytes;
778 * omap_read_page_bch - hardware ecc based page read function
779 * @mtd: mtd info structure
780 * @chip: nand chip info structure
781 * @buf: buffer to store read data
782 * @oob_required: caller expects OOB data read to chip->oob_poi
783 * @page: page number to read
786 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
787 uint8_t *buf, int oob_required, int page)
789 int i, eccsize = chip->ecc.size;
790 int eccbytes = chip->ecc.bytes;
791 int eccsteps = chip->ecc.steps;
793 uint8_t *ecc_calc = chip->buffers->ecccalc;
794 uint8_t *ecc_code = chip->buffers->ecccode;
795 uint32_t *eccpos = chip->ecc.layout->eccpos;
796 uint8_t *oob = &chip->oob_poi[eccpos[0]];
802 oob_pos = (eccsize * eccsteps) + eccpos[0];
804 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
806 chip->ecc.hwctl(mtd, NAND_ECC_READ);
808 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, page);
809 chip->read_buf(mtd, p, eccsize);
811 /* read respective ecc from oob area */
812 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, page);
813 chip->read_buf(mtd, oob, eccbytes);
815 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
818 /* reread the OOB area to get the metadata */
819 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, page);
820 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
827 for (i = 0; i < chip->ecc.total; i++)
828 ecc_code[i] = chip->oob_poi[eccpos[i]];
830 eccsteps = chip->ecc.steps;
833 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
836 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
838 mtd->ecc_stats.failed++;
840 mtd->ecc_stats.corrected += stat;
844 #endif /* CONFIG_AM33XX */
847 * OMAP3 BCH8 support (with BCH library)
849 #ifdef CONFIG_NAND_OMAP_BCH8
851 * omap_calculate_ecc_bch - Read BCH ECC result
853 * @mtd: MTD device structure
854 * @dat: The pointer to data on which ecc is computed (unused here)
855 * @ecc: The ECC output buffer
857 static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat,
862 unsigned long nsectors, val1, val2, val3, val4;
864 nsectors = ((readl(&gpmc_cfg->ecc_config) >> 4) & 0x7) + 1;
866 for (i = 0; i < nsectors; i++) {
867 /* Read hw-computed remainder */
868 val1 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[0]);
869 val2 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[1]);
870 val3 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[2]);
871 val4 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[3]);
874 * Add constant polynomial to remainder, in order to get an ecc
875 * sequence of 0xFFs for a buffer filled with 0xFFs.
877 *ecc++ = 0xef ^ (val4 & 0xFF);
878 *ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF);
879 *ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF);
880 *ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF);
881 *ecc++ = 0xed ^ (val3 & 0xFF);
882 *ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF);
883 *ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF);
884 *ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
885 *ecc++ = 0x97 ^ (val2 & 0xFF);
886 *ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF);
887 *ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
888 *ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF);
889 *ecc++ = 0xb5 ^ (val1 & 0xFF);
893 * Stop reading anymore ECC vals and clear old results
894 * enable will be called if more reads are required
896 omap_ecc_disable(mtd);
902 * omap_correct_data_bch - Decode received data and correct errors
903 * @mtd: MTD device structure
905 * @read_ecc: ecc read from nand flash
906 * @calc_ecc: ecc read from HW ECC registers
908 static int omap_correct_data_bch(struct mtd_info *mtd, u_char *data,
909 u_char *read_ecc, u_char *calc_ecc)
912 /* cannot correct more than 8 errors */
913 unsigned int errloc[8];
914 struct nand_chip *chip = mtd->priv;
915 struct nand_bch_priv *chip_priv = chip->priv;
916 struct bch_control *bch = chip_priv->control;
918 count = decode_bch(bch, NULL, 512, read_ecc, calc_ecc, NULL, errloc);
921 for (i = 0; i < count; i++) {
922 /* correct data only, not ecc bytes */
923 if (errloc[i] < 8*512)
924 data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
925 printf("corrected bitflip %u\n", errloc[i]);
927 printf("read_ecc: ");
929 * BCH8 have 13 bytes of ECC; BCH4 needs adoption
932 for (i = 0; i < 13; i++)
933 printf("%02x ", read_ecc[i]);
935 printf("calc_ecc: ");
936 for (i = 0; i < 13; i++)
937 printf("%02x ", calc_ecc[i]);
941 } else if (count < 0) {
942 printf("ecc unrecoverable error\n");
948 * omap_free_bch - Release BCH ecc resources
949 * @mtd: MTD device structure
951 static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
953 struct nand_chip *chip = mtd->priv;
954 struct nand_bch_priv *chip_priv = chip->priv;
955 struct bch_control *bch = NULL;
958 bch = chip_priv->control;
962 chip_priv->control = NULL;
965 #endif /* CONFIG_NAND_OMAP_BCH8 */
967 #ifndef CONFIG_SPL_BUILD
969 * omap_nand_switch_ecc - switch the ECC operation between different engines
970 * (h/w and s/w) and different algorithms (hamming and BCHx)
972 * @hardware - true if one of the HW engines should be used
973 * @eccstrength - the number of bits that could be corrected
974 * (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16)
976 void omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
978 struct nand_chip *nand;
979 struct mtd_info *mtd;
981 if (nand_curr_device < 0 ||
982 nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
983 !nand_info[nand_curr_device].name) {
984 printf("Error: Can't switch ecc, no devices available\n");
988 mtd = &nand_info[nand_curr_device];
991 nand->options |= NAND_OWN_BUFFERS;
993 /* Reset ecc interface */
994 nand->ecc.mode = NAND_ECC_NONE;
995 nand->ecc.read_page = NULL;
996 nand->ecc.write_page = NULL;
997 nand->ecc.read_oob = NULL;
998 nand->ecc.write_oob = NULL;
999 nand->ecc.hwctl = NULL;
1000 nand->ecc.correct = NULL;
1001 nand->ecc.calculate = NULL;
1002 nand->ecc.strength = eccstrength;
1004 /* Setup the ecc configurations again */
1006 if (eccstrength == 1) {
1007 nand->ecc.mode = NAND_ECC_HW;
1008 nand->ecc.layout = &hw_nand_oob;
1009 nand->ecc.size = 512;
1010 nand->ecc.bytes = 3;
1011 nand->ecc.hwctl = omap_enable_hwecc;
1012 nand->ecc.correct = omap_correct_data;
1013 nand->ecc.calculate = omap_calculate_ecc;
1014 omap_hwecc_init(nand);
1015 printf("1-bit hamming HW ECC selected\n");
1017 #if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8)
1018 else if (eccstrength == 8) {
1019 nand->ecc.mode = NAND_ECC_HW;
1020 nand->ecc.layout = &hw_bch8_nand_oob;
1021 nand->ecc.size = 512;
1022 #ifdef CONFIG_AM33XX
1023 nand->ecc.bytes = 14;
1024 nand->ecc.read_page = omap_read_page_bch;
1026 nand->ecc.bytes = 13;
1028 nand->ecc.hwctl = omap_enable_ecc_bch;
1029 nand->ecc.correct = omap_correct_data_bch;
1030 nand->ecc.calculate = omap_calculate_ecc_bch;
1031 omap_hwecc_init_bch(nand, NAND_ECC_READ);
1032 printf("8-bit BCH HW ECC selected\n");
1036 nand->ecc.mode = NAND_ECC_SOFT;
1037 /* Use mtd default settings */
1038 nand->ecc.layout = NULL;
1040 printf("SW ECC selected\n");
1043 /* Update NAND handling after ECC mode switch */
1044 nand_scan_tail(mtd);
1046 nand->options &= ~NAND_OWN_BUFFERS;
1048 #endif /* CONFIG_SPL_BUILD */
1051 * Board-specific NAND initialization. The following members of the
1052 * argument are board-specific:
1053 * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
1054 * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
1055 * - cmd_ctrl: hardwarespecific function for accesing control-lines
1056 * - waitfunc: hardwarespecific function for accesing device ready/busy line
1057 * - ecc.hwctl: function to enable (reset) hardware ecc generator
1058 * - ecc.mode: mode of ecc, see defines
1059 * - chip_delay: chip dependent delay for transfering data from array to
1061 * - options: various chip options. They can partly be set to inform
1062 * nand_scan about special functionality. See the defines for further
1065 int board_nand_init(struct nand_chip *nand)
1067 int32_t gpmc_config = 0;
1071 * xloader/Uboot's gpmc configuration would have configured GPMC for
1072 * nand type of memory. The following logic scans and latches on to the
1073 * first CS with NAND type memory.
1074 * TBD: need to make this logic generic to handle multiple CS NAND
1077 while (cs < GPMC_MAX_CS) {
1078 /* Check if NAND type is set */
1079 if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
1085 if (cs >= GPMC_MAX_CS) {
1086 printf("NAND: Unable to find NAND settings in "
1087 "GPMC Configuration - quitting\n");
1091 gpmc_config = readl(&gpmc_cfg->config);
1092 /* Disable Write protect */
1093 gpmc_config |= 0x10;
1094 writel(gpmc_config, &gpmc_cfg->config);
1096 nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
1097 nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
1099 nand->cmd_ctrl = omap_nand_hwcontrol;
1100 nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_SUBPAGE_WRITE;
1101 /* If we are 16 bit dev, our gpmc config tells us that */
1102 if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000)
1103 nand->options |= NAND_BUSWIDTH_16;
1105 nand->chip_delay = 100;
1107 #if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8)
1108 #ifdef CONFIG_AM33XX
1109 /* AM33xx uses the ELM */
1110 /* required in case of BCH */
1114 * Whereas other OMAP based SoC do not have the ELM, they use the BCH
1117 bch_priv.control = init_bch(13, 8, 0x201b /* hw polynominal */);
1118 if (!bch_priv.control) {
1119 printf("Failed to initialize BCH engine\n");
1123 /* BCH info that will be correct for SPL or overridden otherwise. */
1124 nand->priv = &bch_priv;
1127 /* Default ECC mode */
1128 #if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8)
1129 nand->ecc.mode = NAND_ECC_HW;
1130 nand->ecc.layout = &hw_bch8_nand_oob;
1131 #ifdef CONFIG_SYS_GPMC_PREFETCH_ENABLE
1132 nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE * 4;
1133 nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES * 4;
1135 nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
1136 nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
1138 nand->ecc.strength = 8;
1139 nand->ecc.hwctl = omap_enable_ecc_bch;
1140 nand->ecc.correct = omap_correct_data_bch;
1141 nand->ecc.calculate = omap_calculate_ecc_bch;
1142 #ifdef CONFIG_AM33XX
1143 nand->ecc.read_page = omap_read_page_bch;
1145 omap_hwecc_init_bch(nand, NAND_ECC_READ);
1147 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC)
1148 nand->ecc.mode = NAND_ECC_SOFT;
1150 nand->ecc.mode = NAND_ECC_HW;
1151 nand->ecc.layout = &hw_nand_oob;
1152 nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
1153 nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
1154 nand->ecc.hwctl = omap_enable_hwecc;
1155 nand->ecc.correct = omap_correct_data;
1156 nand->ecc.calculate = omap_calculate_ecc;
1157 nand->ecc.strength = 1;
1158 omap_hwecc_init(nand);
1161 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1162 if (nand->ecc.layout) {
1163 bbt_main_descr.offs = nand->ecc.layout->oobfree[0].offset;
1164 bbt_main_descr.veroffs = bbt_main_descr.offs +
1165 sizeof(bbt_pattern);
1167 bbt_mirror_descr.offs = nand->ecc.layout->oobfree[0].offset;
1168 bbt_mirror_descr.veroffs = bbt_mirror_descr.offs +
1169 sizeof(mirror_pattern);
1172 nand->bbt_options |= NAND_BBT_USE_FLASH;
1173 nand->bbt_td = &bbt_main_descr;
1174 nand->bbt_md = &bbt_mirror_descr;
1177 #ifdef CONFIG_SPL_BUILD
1178 if (nand->options & NAND_BUSWIDTH_16)
1179 nand->read_buf = nand_read_buf16;
1181 nand->read_buf = nand_read_buf;
1182 nand->dev_ready = omap_spl_dev_ready;
1184 #ifdef CONFIG_SYS_GPMC_PREFETCH_ENABLE
1185 nand->write_buf = write_buf_pref;
1186 nand->read_buf = read_buf_pref;
1187 #endif /* CONFIG_SYS_GPMC_PREFETCH_ENABLE */
1188 #endif /* CONFIG_SPL_BUILD */