2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
4 * (C) Copyright 2008 Armadeus Systems nc
5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
8 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/sys_proto.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/imx-regs.h>
21 #include <asm/errno.h>
22 #include <linux/compiler.h>
26 DECLARE_GLOBAL_DATA_PTR;
29 * Timeout the transfer after 5 mS. This is usually a bit more, since
30 * the code in the tightloops this timeout is used in adds some overhead.
32 #define FEC_XFER_TIMEOUT 5000
35 * The standard 32-byte DMA alignment does not work on mx6solox, which requires
36 * 64-byte alignment in the DMA RX FEC buffer.
37 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
38 * satisfies the alignment on other SoCs (32-bytes)
40 #define FEC_DMA_RX_MINALIGN 64
43 #error "CONFIG_MII has to be defined!"
46 #ifndef CONFIG_FEC_XCV_TYPE
47 #define CONFIG_FEC_XCV_TYPE MII100
51 * The i.MX28 operates with packets in big endian. We need to swap them before
52 * sending and after receiving.
54 #ifdef CONFIG_SOC_MX28
55 #define CONFIG_FEC_MXC_SWAP_PACKET
58 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
60 /* Check various alignment issues at compile time */
61 #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
62 #error "ARCH_DMA_MINALIGN must be multiple of 16!"
65 #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
66 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
67 #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
73 uint8_t data[1500]; /**< actual data */
74 int length; /**< actual length */
75 int used; /**< buffer in use or not */
76 uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
81 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
82 static void swap_packet(uint32_t *packet, int length)
86 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
87 packet[i] = __swab32(packet[i]);
92 * MII-interface related functions
94 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr,
97 uint32_t reg; /* convenient holder for the PHY register */
98 uint32_t phy; /* convenient holder for the PHY */
103 * reading from any PHY's register is done by properly
104 * programming the FEC's MII data register.
106 writel(FEC_IEVENT_MII, ð->ievent);
107 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
108 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
110 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
111 phy | reg, ð->mii_data);
114 * wait for the related interrupt
116 start = get_timer(0);
117 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
118 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
119 if (readl(ð->ievent) & FEC_IEVENT_MII)
121 printf("Read MDIO failed...\n");
127 * clear mii interrupt bit
129 writel(FEC_IEVENT_MII, ð->ievent);
132 * it's now safe to read the PHY's register
134 val = (unsigned short)readl(ð->mii_data);
135 debug("%s: phy: %02x reg:%02x val:%#06x\n", __func__, phyAddr,
140 static void fec_mii_setspeed(struct ethernet_regs *eth)
143 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
144 * and do not drop the Preamble.
146 register u32 speed = DIV_ROUND_UP(imx_get_fecclk(), 5000000);
147 #ifdef FEC_QUIRK_ENET_MAC
151 writel(speed, ð->mii_speed);
152 debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
155 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
156 uint8_t regAddr, uint16_t data)
158 uint32_t reg; /* convenient holder for the PHY register */
159 uint32_t phy; /* convenient holder for the PHY */
162 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
163 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
165 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
166 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
169 * wait for the MII interrupt
171 start = get_timer(0);
172 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
173 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
174 if (readl(ð->ievent) & FEC_IEVENT_MII)
176 printf("Write MDIO failed...\n");
182 * clear MII interrupt bit
184 writel(FEC_IEVENT_MII, ð->ievent);
185 debug("%s: phy: %02x reg:%02x val:%#06x\n", __func__, phyAddr,
191 static int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr,
194 return fec_mdio_read(bus->priv, phyAddr, regAddr);
197 static int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr,
198 int regAddr, u16 data)
200 return fec_mdio_write(bus->priv, phyAddr, regAddr, data);
203 #ifndef CONFIG_PHYLIB
204 static int miiphy_restart_aneg(struct eth_device *dev)
207 #if !defined(CONFIG_FEC_MXC_NO_ANEG)
208 struct fec_priv *fec = (struct fec_priv *)dev->priv;
209 struct ethernet_regs *eth = fec->bus->priv;
212 * Wake up from sleep if necessary
213 * Reset PHY, then delay 300ns
215 #ifdef CONFIG_SOC_MX27
216 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
218 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
222 * Set the auto-negotiation advertisement register bits
224 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
225 LPA_100FULL | LPA_100HALF | LPA_10FULL |
226 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
227 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
228 BMCR_ANENABLE | BMCR_ANRESTART);
230 if (fec->mii_postcall)
231 ret = fec->mii_postcall(fec->phy_id);
237 static int miiphy_wait_aneg(struct eth_device *dev)
241 struct fec_priv *fec = (struct fec_priv *)dev->priv;
242 struct ethernet_regs *eth = fec->bus->priv;
245 * Wait for AN completion
247 start = get_timer(0);
249 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
250 printf("%s: Autonegotiation timeout\n", dev->name);
254 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
256 printf("%s: Autonegotiation failed. status: %d\n",
260 } while (!(status & BMSR_LSTATUS));
266 static inline void fec_rx_task_enable(struct fec_priv *fec)
268 writel(1 << 24, &fec->eth->r_des_active);
271 static inline void fec_rx_task_disable(struct fec_priv *fec)
275 static inline void fec_tx_task_enable(struct fec_priv *fec)
277 writel(1 << 24, &fec->eth->x_des_active);
280 static inline void fec_tx_task_disable(struct fec_priv *fec)
285 * Initialize receive task's buffer descriptors
286 * @param[in] fec all we know about the device yet
287 * @param[in] count receive buffer count to be allocated
288 * @param[in] dsize desired size of each receive buffer
289 * @return 0 on success
291 * Init all RX descriptors to default values.
293 static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
300 * Reload the RX descriptors with default values and wipe
303 size = roundup(dsize, ARCH_DMA_MINALIGN);
304 for (i = 0; i < count; i++) {
305 data = (uint8_t *)fec->rbd_base[i].data_pointer;
306 memset(data, 0, dsize);
307 flush_dcache_range((uint32_t)data, (uint32_t)data + size);
309 fec->rbd_base[i].status = FEC_RBD_EMPTY;
310 fec->rbd_base[i].data_length = 0;
313 /* Mark the last RBD to close the ring. */
314 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
317 flush_dcache_range((unsigned)fec->rbd_base,
318 (unsigned)fec->rbd_base + size);
322 * Initialize transmit task's buffer descriptors
323 * @param[in] fec all we know about the device yet
325 * Transmit buffers are created externally. We only have to init the BDs here.\n
326 * Note: There is a race condition in the hardware. When only one BD is in
327 * use it must be marked with the WRAP bit to use it for every transmitt.
328 * This bit in combination with the READY bit results into double transmit
329 * of each data buffer. It seems the state machine checks READY earlier then
330 * resetting it after the first transfer.
331 * Using two BDs solves this issue.
333 static void fec_tbd_init(struct fec_priv *fec)
335 unsigned addr = (unsigned)fec->tbd_base;
336 unsigned size = roundup(2 * sizeof(struct fec_bd),
339 memset(fec->tbd_base, 0, size);
340 fec->tbd_base[0].status = 0;
341 fec->tbd_base[1].status = FEC_TBD_WRAP;
343 flush_dcache_range(addr, addr + size);
347 * Mark the given read buffer descriptor as free
348 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
349 * @param[in] pRbd buffer descriptor to mark free again
351 static void fec_rbd_clean(int last, struct fec_bd *pRbd)
353 unsigned short flags = FEC_RBD_EMPTY;
355 flags |= FEC_RBD_WRAP;
356 writew(flags, &pRbd->status);
357 writew(0, &pRbd->data_length);
360 static int fec_get_hwaddr(struct eth_device *dev, int dev_id,
363 imx_get_mac_from_fuse(dev_id, mac);
364 return !is_valid_ethaddr(mac);
367 static int fec_set_hwaddr(struct eth_device *dev)
369 uchar *mac = dev->enetaddr;
370 struct fec_priv *fec = (struct fec_priv *)dev->priv;
372 writel(0, &fec->eth->iaddr1);
373 writel(0, &fec->eth->iaddr2);
374 writel(0, &fec->eth->gaddr1);
375 writel(0, &fec->eth->gaddr2);
378 * Set physical address
380 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
382 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
388 * Do initial configuration of the FEC registers
390 static void fec_reg_setup(struct fec_priv *fec)
395 * Set interrupt mask register
397 writel(0x00000000, &fec->eth->imask);
400 * Clear FEC-Lite interrupt event register(IEVENT)
402 writel(0xffffffff, &fec->eth->ievent);
406 * Set FEC-Lite receive control register(R_CNTRL):
409 /* Start with frame length = 1518, common for all modes. */
410 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
411 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
412 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
413 if (fec->xcv_type == RGMII)
414 rcntrl |= FEC_RCNTRL_RGMII;
415 else if (fec->xcv_type == RMII)
416 rcntrl |= FEC_RCNTRL_RMII;
418 writel(rcntrl, &fec->eth->r_cntrl);
422 * Start the FEC engine
423 * @param[in] dev Our device to handle
425 static int fec_open(struct eth_device *edev)
427 struct fec_priv *fec = edev->priv;
432 debug("fec_open: fec_open(dev)\n");
433 /* full-duplex, heartbeat disabled */
434 writel(1 << 2, &fec->eth->x_cntrl);
437 /* Invalidate all descriptors */
438 for (i = 0; i < FEC_RBD_NUM - 1; i++)
439 fec_rbd_clean(0, &fec->rbd_base[i]);
440 fec_rbd_clean(1, &fec->rbd_base[i]);
442 /* Flush the descriptors into RAM */
443 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
445 addr = (uint32_t)fec->rbd_base;
446 flush_dcache_range(addr, addr + size);
448 #ifdef FEC_QUIRK_ENET_MAC
449 /* Enable ENET HW endian SWAP */
450 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
452 /* Enable ENET store and forward mode */
453 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
457 * Enable FEC-Lite controller
459 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
461 #if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6SL)
464 * setup the MII gasket for RMII mode
467 /* disable the gasket */
468 writew(0, &fec->eth->miigsk_enr);
470 /* wait for the gasket to be disabled */
471 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
474 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
475 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
477 /* re-enable the gasket */
478 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
480 /* wait until MII gasket is ready */
482 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
483 if (--max_loops <= 0) {
484 printf("WAIT for MII Gasket ready timed out\n");
492 /* Start up the PHY */
493 int ret = phy_startup(fec->phydev);
496 printf("Could not initialize PHY %s\n",
497 fec->phydev->dev->name);
500 speed = fec->phydev->speed;
503 miiphy_wait_aneg(edev);
504 speed = miiphy_speed(edev->name, fec->phy_id);
505 miiphy_duplex(edev->name, fec->phy_id);
508 #ifdef FEC_QUIRK_ENET_MAC
510 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
511 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
513 if (speed == _1000BASET)
514 ecr |= FEC_ECNTRL_SPEED;
515 else if (speed != _100BASET)
516 rcr |= FEC_RCNTRL_RMII_10T;
517 writel(ecr, &fec->eth->ecntrl);
518 writel(rcr, &fec->eth->r_cntrl);
520 #elif defined(CONFIG_SOC_MX28)
522 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
524 if (speed == _10BASET)
525 rcr |= FEC_RCNTRL_RMII_10T;
526 writel(rcr, &fec->eth->r_cntrl);
529 debug("%s:Speed=%i\n", __func__, speed);
532 * Enable SmartDMA receive task
534 fec_rx_task_enable(fec);
540 static int fec_init(struct eth_device *dev, bd_t* bd)
542 struct fec_priv *fec = dev->priv;
543 uint32_t *mib_ptr = (uint32_t *)&fec->eth->rmon_t_drop;
546 /* Initialize MAC address */
550 * Setup transmit descriptors, there are two in total.
554 /* Setup receive descriptors. */
555 fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
559 if (fec->xcv_type != SEVENWIRE)
560 fec_mii_setspeed(fec->bus->priv);
563 * Set Opcode/Pause Duration Register
565 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
566 writel(0x2, &fec->eth->x_wmrk);
568 * Set multicast address filter
570 writel(0x00000000, &fec->eth->gaddr1);
571 writel(0x00000000, &fec->eth->gaddr2);
575 for (i = 0; i <= 0xfc >> 2; i++)
576 writel(0, &mib_ptr[i]);
578 /* FIFO receive start register */
579 writel(0x520, &fec->eth->r_fstart);
581 /* size and address of each buffer */
582 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
583 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
584 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
586 #ifndef CONFIG_PHYLIB
587 if (fec->xcv_type != SEVENWIRE)
588 miiphy_restart_aneg(dev);
595 * Halt the FEC engine
596 * @param[in] dev Our device to handle
598 static void fec_halt(struct eth_device *dev)
600 struct fec_priv *fec = (struct fec_priv *)dev->priv;
604 * issue graceful stop command to the FEC transmitter if necessary
606 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
609 debug("eth_halt: wait for stop regs\n");
611 * wait for graceful stop to register
613 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
617 * Disable SmartDMA tasks
619 fec_tx_task_disable(fec);
620 fec_rx_task_disable(fec);
623 * Disable the Ethernet Controller
624 * Note: this will also reset the BD index counter!
626 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
630 debug("eth_halt: done\n");
635 * @param[in] dev Our ethernet device to handle
636 * @param[in] packet Pointer to the data to be transmitted
637 * @param[in] length Data count in bytes
638 * @return 0 on success
640 static int fec_send(struct eth_device *dev, void *packet, int length)
645 int timeout = FEC_XFER_TIMEOUT;
649 * This routine transmits one frame. This routine only accepts
650 * 6-byte Ethernet addresses.
652 struct fec_priv *fec = dev->priv;
655 * Check for valid length of data.
657 if ((length > 1500) || (length <= 0)) {
658 printf("Payload (%d) too large\n", length);
663 * Setup the transmit buffer. We are always using the first buffer for
664 * transmission, the second will be empty and only used to stop the DMA
665 * engine. We also flush the packet to RAM here to avoid cache trouble.
667 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
668 swap_packet((uint32_t *)packet, length);
671 addr = (uint32_t)packet;
672 end = roundup(addr + length, ARCH_DMA_MINALIGN);
673 addr &= ~(ARCH_DMA_MINALIGN - 1);
674 flush_dcache_range(addr, end);
676 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
677 writel((unsigned long)packet,
678 &fec->tbd_base[fec->tbd_index].data_pointer);
681 * update BD's status now
683 * - is always the last in a chain (means no chain)
684 * - should transmit the CRC
685 * - might be the last BD in the list, so the address counter should
686 * wrap (-> keep the WRAP flag)
688 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
689 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
690 writew(status, &fec->tbd_base[fec->tbd_index].status);
693 * Flush data cache. This code flushes both TX descriptors to RAM.
694 * After this code, the descriptors will be safely in RAM and we
697 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
698 addr = (uint32_t)fec->tbd_base;
699 flush_dcache_range(addr, addr + size);
702 * Below we read the DMA descriptor's last four bytes back from the
703 * DRAM. This is important in order to make sure that all WRITE
704 * operations on the bus that were triggered by previous cache FLUSH
707 * Otherwise, on MX28, it is possible to observe a corruption of the
708 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
709 * for the bus structure of MX28. The scenario is as follows:
711 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
712 * to DRAM due to flush_dcache_range()
713 * 2) ARM core writes the FEC registers via AHB_ARB2
714 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
716 * Note that 2) does sometimes finish before 1) due to reordering of
717 * WRITE accesses on the AHB bus, therefore triggering 3) before the
718 * DMA descriptor is fully written into DRAM. This results in occasional
719 * corruption of the DMA descriptor.
721 readl(addr + size - 4);
724 * Enable SmartDMA transmit task
726 fec_tx_task_enable(fec);
729 * Wait until frame is sent. On each turn of the wait cycle, we must
730 * invalidate data cache to see what's really in RAM. Also, we need
734 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
744 * The TDAR bit is cleared when the descriptors are all out from TX
745 * but on mx6solox we noticed that the READY bit is still not cleared
747 * These are two distinct signals, and in IC simulation, we found that
748 * TDAR always gets cleared prior than the READY bit of last BD becomes
750 * In mx6solox, we use a later version of FEC IP. It looks like that
751 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
754 * Fix this by polling the READY bit of BD after the TDAR polling,
755 * which covers the mx6solox case and does not harm the other SoCs.
757 timeout = FEC_XFER_TIMEOUT;
759 invalidate_dcache_range(addr, addr + size);
760 if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
769 debug("fec_send: status 0x%x index %d ret %i\n",
770 readw(&fec->tbd_base[fec->tbd_index].status),
771 fec->tbd_index, ret);
772 /* for next transmission use the other buffer */
782 * Pull one frame from the card
783 * @param[in] dev Our ethernet device to handle
784 * @return Length of packet read
786 static int fec_recv(struct eth_device *dev)
788 struct fec_priv *fec = (struct fec_priv *)dev->priv;
789 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
790 unsigned long ievent;
791 int frame_length, len = 0;
794 uint32_t addr, size, end;
798 * Check if any critical events have happened
800 ievent = readl(&fec->eth->ievent);
802 writel(ievent, &fec->eth->ievent);
805 debug("fec_recv: ievent 0x%lx\n", ievent);
806 if (ievent & FEC_IEVENT_BABR) {
808 fec_init(dev, fec->bd);
809 printf("some error: 0x%08lx\n", ievent);
812 if (ievent & FEC_IEVENT_HBERR) {
813 /* Heartbeat error */
814 writel(0x00000001 | readl(&fec->eth->x_cntrl),
817 if (ievent & FEC_IEVENT_GRA) {
818 /* Graceful stop complete */
819 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
821 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
823 fec_init(dev, fec->bd);
828 * Read the buffer status. Before the status can be read, the data cache
829 * must be invalidated, because the data in RAM might have been changed
830 * by DMA. The descriptors are properly aligned to cachelines so there's
831 * no need to worry they'd overlap.
833 * WARNING: By invalidating the descriptor here, we also invalidate
834 * the descriptors surrounding this one. Therefore we can NOT change the
835 * contents of this descriptor nor the surrounding ones. The problem is
836 * that in order to mark the descriptor as processed, we need to change
837 * the descriptor. The solution is to mark the whole cache line when all
838 * descriptors in the cache line are processed.
840 addr = (uint32_t)rbd;
841 addr &= ~(ARCH_DMA_MINALIGN - 1);
842 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
843 invalidate_dcache_range(addr, addr + size);
845 bd_status = readw(&rbd->status);
846 if (!(bd_status & FEC_RBD_EMPTY)) {
847 debug("fec_recv: status 0x%04x len %u\n", bd_status,
848 readw(&rbd->data_length) - 4);
849 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
850 ((readw(&rbd->data_length) - 4) > 14)) {
852 * Get buffer address and size
854 frame = (struct nbuf *)readl(&rbd->data_pointer);
855 frame_length = readw(&rbd->data_length) - 4;
858 * Invalidate data cache over the buffer
860 addr = (uint32_t)frame;
861 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
862 addr &= ~(ARCH_DMA_MINALIGN - 1);
863 invalidate_dcache_range(addr, end);
866 * Fill the buffer and pass it to upper layers
868 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
869 swap_packet((uint32_t *)frame->data, frame_length);
871 memcpy((void *)NetRxPackets[rx_idx], frame->data, frame_length);
872 NetReceive(NetRxPackets[rx_idx], frame_length);
873 rx_idx = (rx_idx + 1) % PKTBUFSRX;
876 if (bd_status & FEC_RBD_ERR)
877 printf("error frame: 0x%08lx 0x%08x\n",
878 (ulong)rbd->data_pointer,
883 * Free the current buffer, restart the engine and move forward
884 * to the next buffer. Here we check if the whole cacheline of
885 * descriptors was already processed and if so, we mark it free
888 size = RXDESC_PER_CACHELINE - 1;
889 if ((fec->rbd_index & size) == size) {
890 i = fec->rbd_index - size;
891 addr = (uint32_t)&fec->rbd_base[i];
892 for (; i <= fec->rbd_index ; i++) {
893 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
896 flush_dcache_range(addr,
897 addr + ARCH_DMA_MINALIGN);
900 fec_rx_task_enable(fec);
901 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
902 debug("fec_recv: stop\n");
908 static void fec_set_dev_name(char *dest, int dev_id)
910 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
913 static int fec_alloc_descs(struct fec_priv *fec)
919 /* Allocate TX descriptors. */
920 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
921 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
925 /* Allocate RX descriptors. */
926 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
927 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
931 memset(fec->rbd_base, 0, size);
933 /* Allocate RX buffers. */
935 /* Maximum RX buffer size. */
936 size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
937 for (i = 0; i < FEC_RBD_NUM; i++) {
938 data = memalign(FEC_DMA_RX_MINALIGN, size);
940 printf("%s: error allocating rxbuf %d\n", __func__, i);
944 memset(data, 0, size);
946 fec->rbd_base[i].data_pointer = (uint32_t)data;
947 fec->rbd_base[i].status = FEC_RBD_EMPTY;
948 fec->rbd_base[i].data_length = 0;
949 /* Flush the buffer to memory. */
950 flush_dcache_range((uint32_t)data, (uint32_t)data + size);
953 /* Mark the last RBD to close the ring. */
954 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
963 free((void *)fec->rbd_base[i].data_pointer);
971 static void fec_free_descs(struct fec_priv *fec)
975 for (i = 0; i < FEC_RBD_NUM; i++)
976 free((void *)fec->rbd_base[i].data_pointer);
982 int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
983 struct mii_dev *bus, struct phy_device *phydev)
985 static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
986 struct mii_dev *bus, int phy_id)
989 struct eth_device *edev;
990 struct fec_priv *fec;
991 unsigned char ethaddr[6];
995 /* create and fill edev struct */
996 edev = calloc(sizeof(struct eth_device), 1);
998 puts("fec_mxc: not enough malloc memory for eth_device\n");
1003 fec = calloc(sizeof(struct fec_priv), 1);
1005 puts("fec_mxc: not enough malloc memory for fec_priv\n");
1010 ret = fec_alloc_descs(fec);
1015 edev->init = fec_init;
1016 edev->send = fec_send;
1017 edev->recv = fec_recv;
1018 edev->halt = fec_halt;
1019 edev->write_hwaddr = fec_set_hwaddr;
1021 fec->eth = (struct ethernet_regs *)base_addr;
1024 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
1027 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
1028 start = get_timer(0);
1029 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
1030 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1031 printf("FEC MXC: Timeout reseting chip\n");
1038 fec_set_dev_name(edev->name, dev_id);
1039 fec->dev_id = (dev_id == -1) ? 0 : dev_id;
1041 fec_mii_setspeed(bus->priv);
1042 #ifdef CONFIG_PHYLIB
1043 fec->phydev = phydev;
1044 phy_connect_dev(phydev, edev);
1048 fec->phy_id = phy_id;
1052 if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) {
1054 debug("got MAC address from fuse: %pM\n", ethaddr);
1056 debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
1057 memcpy(edev->enetaddr, ethaddr, 6);
1058 if (!getenv("ethaddr"))
1059 eth_setenv_enetaddr("ethaddr", ethaddr);
1063 fec_free_descs(fec);
1072 struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
1074 struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
1075 struct mii_dev *bus;
1080 printf("mdio_alloc failed\n");
1083 bus->read = fec_phy_read;
1084 bus->write = fec_phy_write;
1086 fec_set_dev_name(bus->name, dev_id);
1088 ret = mdio_register(bus);
1090 printf("mdio_register failed\n");
1094 fec_mii_setspeed(eth);
1098 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
1101 struct mii_dev *bus = NULL;
1102 #ifdef CONFIG_PHYLIB
1103 struct phy_device *phydev = NULL;
1107 #ifdef CONFIG_SOC_MX28
1109 * The i.MX28 has two ethernet interfaces, but they are not equal.
1110 * Only the first one can access the MDIO bus.
1112 base_mii = MXS_ENET0_BASE;
1116 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
1117 bus = fec_get_miibus(base_mii, dev_id);
1120 #ifdef CONFIG_PHYLIB
1121 phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
1126 ret = fec_probe(bd, dev_id, addr, bus, phydev);
1128 ret = fec_probe(bd, dev_id, addr, bus, phy_id);
1131 #ifdef CONFIG_PHYLIB
1139 #ifdef CONFIG_FEC_MXC_PHYADDR
1140 int fecmxc_initialize(bd_t *bd)
1142 return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
1147 #ifndef CONFIG_PHYLIB
1148 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1150 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1151 fec->mii_postcall = cb;