drivers/spmi/spmi-msm.c

   1 /*
   2  * Qualcomm SPMI bus driver
   3  *
   4  * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
   5  *
   6  * Loosely based on Little Kernel driver
   7  *
   8  * SPDX-License-Identifier:     BSD-3-Clause
   9  */
  10
  11 #include <common.h>
  12 #include <dm.h>
  13 #include <errno.h>
  14 #include <fdtdec.h>
  15 #include <asm/io.h>
  16 #include <spmi/spmi.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 #define ARB_CHANNEL_OFFSET(n)           (0x4 * (n))
  21 #define SPMI_CH_OFFSET(chnl)            ((chnl) * 0x8000)
  22
  23 #define PMIC_ARB_VERSION                0x0000
  24 #define PMIC_ARB_VERSION_V2_MIN         0x20010000
  25
  26 #define SPMI_REG_CMD0                   0x0
  27 #define SPMI_REG_CONFIG                 0x4
  28 #define SPMI_REG_STATUS                 0x8
  29 #define SPMI_REG_WDATA                  0x10
  30 #define SPMI_REG_RDATA                  0x18
  31
  32 #define SPMI_CMD_OPCODE_SHIFT           27
  33 #define SPMI_CMD_SLAVE_ID_SHIFT         20
  34 #define SPMI_CMD_ADDR_SHIFT             12
  35 #define SPMI_CMD_ADDR_OFFSET_SHIFT      4
  36 #define SPMI_CMD_BYTE_CNT_SHIFT         0
  37
  38 #define SPMI_V2_CMD_OPCODE_SHIFT        27
  39 #define SPMI_V2_CMD_ADDR_OFFSET_SHIFT   4
  40 #define SPMI_V2_CMD_BYTE_CNT_SHIFT      0
  41
  42 #define SPMI_CMD_EXT_REG_WRITE_LONG     0x00
  43 #define SPMI_CMD_EXT_REG_READ_LONG      0x01
  44
  45 #define SPMI_STATUS_DONE                0x1
  46
  47 #define SPMI_MAX_CHANNELS               128
  48 #define SPMI_MAX_SLAVES                 16
  49 #define SPMI_MAX_PERIPH                 256
  50
  51 #define SPMI_READ_TIMEOUT               100
  52 #define SPMI_WRITE_TIMEOUT              100
  53
  54 static int pmic_arb_ver;
  55
  56 static inline int pmic_arb_is_v1(void)
  57 {
  58         return pmic_arb_ver < PMIC_ARB_VERSION_V2_MIN;
  59 }
  60
  61 struct msm_spmi_priv {
  62         phys_addr_t arb_chnl; /* ARB channel mapping base */
  63         phys_addr_t spmi_core; /* SPMI core */
  64         phys_addr_t spmi_chnls; /* SPMI chnls */
  65         phys_addr_t spmi_obs; /* SPMI observer */
  66         /* SPMI channel map */
  67         uint8_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH];
  68 };
  69
  70 static int msm_spmi_write(struct udevice *dev, int usid, int pid, int off,
  71                           uint8_t val)
  72 {
  73         struct msm_spmi_priv *priv = dev_get_priv(dev);
  74         unsigned channel;
  75         uint32_t reg = 0;
  76
  77         if (usid >= SPMI_MAX_SLAVES)
  78                 return -EINVAL;
  79         if (pid >= SPMI_MAX_PERIPH)
  80                 return -EINVAL;
  81
  82         channel = priv->channel_map[usid][pid];
  83
  84         /* Disable IRQ mode for the current channel */
  85         writel(0x0, priv->spmi_chnls + SPMI_CH_OFFSET(channel) +
  86                SPMI_REG_CONFIG);
  87
  88         /* Write single byte */
  89         writel(val, priv->spmi_chnls + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA);
  90
  91         /* Prepare write command */
  92         if (pmic_arb_is_v1()) {
  93                 reg |= SPMI_CMD_EXT_REG_WRITE_LONG << SPMI_CMD_OPCODE_SHIFT;
  94                 reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
  95                 reg |= (pid << SPMI_CMD_ADDR_SHIFT);
  96                 reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
  97                 reg |= 1; /* byte count */
  98         } else {
  99                 reg |= SPMI_CMD_EXT_REG_WRITE_LONG << SPMI_CMD_OPCODE_SHIFT;
 100                 reg |= ((off & 0xff) << SPMI_CMD_ADDR_OFFSET_SHIFT);
 101                 reg |= 0; /* byte count - 1 */
 102         }
 103         /* Send write command */
 104         writel(reg, priv->spmi_chnls + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
 105
 106         /* Wait till CMD DONE status */
 107         reg = 0;
 108         while (!reg) {
 109                 reg = readl(priv->spmi_core + SPMI_CH_OFFSET(channel) +
 110                             SPMI_REG_STATUS);
 111         }
 112
 113         if (reg ^ SPMI_STATUS_DONE) {
 114                 printf("SPMI write failure.\n");
 115                 return -EIO;
 116         }
 117
 118         return 0;
 119 }
 120
 121 static int msm_spmi_read(struct udevice *dev, int usid, int pid, int off)
 122 {
 123         struct msm_spmi_priv *priv = dev_get_priv(dev);
 124         unsigned channel;
 125         uint32_t reg = 0;
 126
 127         if (usid >= SPMI_MAX_SLAVES)
 128                 return -EINVAL;
 129         if (pid >= SPMI_MAX_PERIPH)
 130                 return -EINVAL;
 131
 132         channel = priv->channel_map[usid][pid];
 133
 134         /* Disable IRQ mode for the current channel*/
 135         writel(0x0, priv->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
 136
 137         /* Prepare read command */
 138         if (pmic_arb_is_v1()) {
 139                 reg |= SPMI_CMD_EXT_REG_READ_LONG << SPMI_CMD_OPCODE_SHIFT;
 140                 reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
 141                 reg |= (pid << SPMI_CMD_ADDR_SHIFT);
 142                 reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
 143                 reg |= 1; /* byte count */
 144         } else {
 145                 reg |= SPMI_CMD_EXT_REG_READ_LONG << SPMI_CMD_OPCODE_SHIFT;
 146                 reg |= ((off & 0xff) << SPMI_CMD_ADDR_OFFSET_SHIFT);
 147                 reg |= 0; /* byte count - 1 */
 148         }
 149
 150         /* Request read */
 151         writel(reg, priv->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
 152
 153         /* Wait till CMD DONE status */
 154         reg = 0;
 155         while (!reg) {
 156                 reg = readl(priv->spmi_obs + SPMI_CH_OFFSET(channel) +
 157                             SPMI_REG_STATUS);
 158         }
 159
 160         if (reg ^ SPMI_STATUS_DONE) {
 161                 printf("SPMI read failure.\n");
 162                 return -EIO;
 163         }
 164
 165         /* Read the data */
 166         return readl(priv->spmi_obs + SPMI_CH_OFFSET(channel) +
 167                      SPMI_REG_RDATA) & 0xFF;
 168 }
 169
 170 static struct dm_spmi_ops msm_spmi_ops = {
 171         .read = msm_spmi_read,
 172         .write = msm_spmi_write,
 173 };
 174
 175 static int msm_spmi_probe(struct udevice *dev)
 176 {
 177         struct udevice *parent = dev->parent;
 178         struct msm_spmi_priv *priv = dev_get_priv(dev);
 179         int i;
 180
 181         priv->spmi_core = dev_get_addr(dev);
 182         priv->spmi_chnls = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
 183                                                            parent->of_offset,
 184                                                            dev->of_offset,
 185                                                            "reg", 1, NULL,
 186                                                            false);
 187         priv->spmi_obs = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
 188                                                           parent->of_offset,
 189                                                           dev->of_offset, "reg",
 190                                                           2, NULL, false);
 191         if (priv->spmi_core == FDT_ADDR_T_NONE ||
 192             priv->spmi_chnls == FDT_ADDR_T_NONE ||
 193             priv->spmi_obs == FDT_ADDR_T_NONE)
 194                 return -EINVAL;
 195
 196         priv->arb_chnl = priv->spmi_core + 0x800;
 197
 198         /* Scan peripherals connected to each SPMI channel */
 199         for (i = 0; i < SPMI_MAX_CHANNELS ; i++) {
 200                 uint32_t periph = readl(priv->arb_chnl + ARB_CHANNEL_OFFSET(i));
 201                 uint8_t slave_id = (periph & 0xf0000) >> 16;
 202                 uint8_t pid = (periph & 0xff00) >> 8;
 203
 204                 priv->channel_map[slave_id][pid] = i;
 205         }
 206         pmic_arb_ver = readl(priv->spmi_core + PMIC_ARB_VERSION);
 207         printf("PMIC: PM8916 ARB version %d\n", pmic_arb_is_v1() ? 1 : 2);
 208         return 0;
 209 }
 210
 211 static const struct udevice_id msm_spmi_ids[] = {
 212         { .compatible = "qcom,spmi-pmic-arb" },
 213         { }
 214 };
 215
 216 U_BOOT_DRIVER(msm_spmi) = {
 217         .name = "msm_spmi",
 218         .id = UCLASS_SPMI,
 219         .of_match = msm_spmi_ids,
 220         .ops = &msm_spmi_ops,
 221         .probe = msm_spmi_probe,
 222         .priv_auto_alloc_size = sizeof(struct msm_spmi_priv),
 223 };