5 * Stefano Babic, DENX Software Engineering, sbabic@denx.de
9 * (C) Copyright 2005-2011 Freescale Semiconductor, Inc.
11 * SPDX-License-Identifier: GPL-2.0+
18 #include <linux/types.h>
19 #include <asm/errno.h>
21 #include <asm/arch/imx-regs.h>
22 #include <asm/arch/sys_proto.h>
34 struct dp_csc_param_t {
41 /* DC display ID assignments */
42 #define DC_DISP_ID_SYNC(di) (di)
43 #define DC_DISP_ID_SERIAL 2
44 #define DC_DISP_ID_ASYNC 3
46 static int dmfc_type_setup;
47 static int dmfc_size_28, dmfc_size_29, dmfc_size_24, dmfc_size_27, dmfc_size_23;
48 static int g_di1_tvout;
50 void ipu_dmfc_init(int dmfc_type, int first)
52 u32 dmfc_wr_chan, dmfc_dp_chan;
55 if (dmfc_type_setup > dmfc_type)
56 dmfc_type = dmfc_type_setup;
58 dmfc_type_setup = dmfc_type;
60 /* disable DMFC-IC channel*/
61 __raw_writel(0x2, DMFC_IC_CTRL);
62 } else if (dmfc_type_setup >= DMFC_HIGH_RESOLUTION_DC) {
63 printf("DMFC high resolution has set, will not change\n");
66 dmfc_type_setup = dmfc_type;
68 if (dmfc_type == DMFC_HIGH_RESOLUTION_DC) {
72 * 1C, 2C and 6B, 6F unused;
74 debug("IPU DMFC DC HIGH RES: 1(0~3), 5B(4,5), 5F(6,7)\n");
75 dmfc_wr_chan = 0x00000088;
76 dmfc_dp_chan = 0x00009694;
77 dmfc_size_28 = 256 * 4;
80 dmfc_size_27 = 128 * 4;
81 dmfc_size_23 = 128 * 4;
82 } else if (dmfc_type == DMFC_HIGH_RESOLUTION_DP) {
86 * 1C, 2C and 6B, 6F unused;
88 debug("IPU DMFC DP HIGH RES: 1(0,1), 5B(2~5), 5F(6,7)\n");
89 dmfc_wr_chan = 0x00000090;
90 dmfc_dp_chan = 0x0000968a;
91 dmfc_size_28 = 128 * 4;
94 dmfc_size_27 = 128 * 4;
95 dmfc_size_23 = 256 * 4;
96 } else if (dmfc_type == DMFC_HIGH_RESOLUTION_ONLY_DP) {
99 * 1, 1C, 2C and 6B, 6F unused;
101 debug("IPU DMFC ONLY-DP HIGH RES: 5B(0~3), 5F(4~7)\n");
102 dmfc_wr_chan = 0x00000000;
103 dmfc_dp_chan = 0x00008c88;
107 dmfc_size_27 = 256 * 4;
108 dmfc_size_23 = 256 * 4;
111 * 5B - segement 4, 5;
112 * 5F - segement 6, 7;
113 * 1C, 2C and 6B, 6F unused;
115 debug("IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)\n");
116 dmfc_wr_chan = 0x00000090;
117 dmfc_dp_chan = 0x00009694;
118 dmfc_size_28 = 128 * 4;
121 dmfc_size_27 = 128 * 4;
122 dmfc_size_23 = 128 * 4;
124 __raw_writel(dmfc_wr_chan, DMFC_WR_CHAN);
125 __raw_writel(0x202020F6, DMFC_WR_CHAN_DEF);
126 __raw_writel(dmfc_dp_chan, DMFC_DP_CHAN);
127 /* Enable chan 5 watermark set at 5 bursts and clear at 7 bursts */
128 __raw_writel(0x2020F6F6, DMFC_DP_CHAN_DEF);
131 void ipu_dmfc_set_wait4eot(int dma_chan, int width)
133 u32 dmfc_gen1 = __raw_readl(DMFC_GENERAL1);
135 if (width >= HIGH_RESOLUTION_WIDTH) {
137 ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DP, 0);
138 else if (dma_chan == 28)
139 ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DC, 0);
142 if (dma_chan == 23) { /*5B*/
143 if (dmfc_size_23 / width > 3)
144 dmfc_gen1 |= 1UL << 20;
146 dmfc_gen1 &= ~(1UL << 20);
147 } else if (dma_chan == 24) { /*6B*/
148 if (dmfc_size_24 / width > 1)
149 dmfc_gen1 |= 1UL << 22;
151 dmfc_gen1 &= ~(1UL << 22);
152 } else if (dma_chan == 27) { /*5F*/
153 if (dmfc_size_27 / width > 2)
154 dmfc_gen1 |= 1UL << 21;
156 dmfc_gen1 &= ~(1UL << 21);
157 } else if (dma_chan == 28) { /*1*/
158 if (dmfc_size_28 / width > 2)
159 dmfc_gen1 |= 1UL << 16;
161 dmfc_gen1 &= ~(1UL << 16);
162 } else if (dma_chan == 29) { /*6F*/
163 if (dmfc_size_29 / width > 1)
164 dmfc_gen1 |= 1UL << 23;
166 dmfc_gen1 &= ~(1UL << 23);
169 __raw_writel(dmfc_gen1, DMFC_GENERAL1);
172 static void ipu_di_data_wave_config(int di,
174 int access_size, int component_size)
177 reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) |
178 (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET);
179 __raw_writel(reg, DI_DW_GEN(di, wave_gen));
182 static void ipu_di_data_pin_config(int di, int wave_gen, int di_pin, int set,
187 reg = __raw_readl(DI_DW_GEN(di, wave_gen));
188 reg &= ~(0x3 << (di_pin * 2));
189 reg |= set << (di_pin * 2);
190 __raw_writel(reg, DI_DW_GEN(di, wave_gen));
192 __raw_writel((down << 16) | up, DI_DW_SET(di, wave_gen, set));
195 static void ipu_di_sync_config(int di, int wave_gen,
196 int run_count, int run_src,
197 int offset_count, int offset_src,
198 int repeat_count, int cnt_clr_src,
199 int cnt_polarity_gen_en,
200 int cnt_polarity_clr_src,
201 int cnt_polarity_trigger_src,
202 int cnt_up, int cnt_down)
206 if ((run_count >= 0x1000) || (offset_count >= 0x1000) ||
207 (repeat_count >= 0x1000) ||
208 (cnt_up >= 0x400) || (cnt_down >= 0x400)) {
209 printf("DI%d counters out of range.\n", di);
213 reg = (run_count << 19) | (++run_src << 16) |
214 (offset_count << 3) | ++offset_src;
215 __raw_writel(reg, DI_SW_GEN0(di, wave_gen));
216 reg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) |
217 (++cnt_polarity_trigger_src << 12) | (++cnt_polarity_clr_src << 9);
218 reg |= (cnt_down << 16) | cnt_up;
219 if (repeat_count == 0) {
220 /* Enable auto reload */
223 __raw_writel(reg, DI_SW_GEN1(di, wave_gen));
224 reg = __raw_readl(DI_STP_REP(di, wave_gen));
225 reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1)));
226 reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1));
227 __raw_writel(reg, DI_STP_REP(di, wave_gen));
230 static void ipu_dc_map_config(int map, int byte_num, int offset, int mask)
232 int ptr = map * 3 + byte_num;
235 reg = __raw_readl(DC_MAP_CONF_VAL(ptr));
236 reg &= ~(0xFFFF << (16 * (ptr & 0x1)));
237 reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
238 __raw_writel(reg, DC_MAP_CONF_VAL(ptr));
240 reg = __raw_readl(DC_MAP_CONF_PTR(map));
241 reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte_num)));
242 reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
243 __raw_writel(reg, DC_MAP_CONF_PTR(map));
246 static void ipu_dc_map_clear(int map)
248 u32 reg = __raw_readl(DC_MAP_CONF_PTR(map));
249 __raw_writel(reg & ~(0xFFFF << (16 * (map & 0x1))),
250 DC_MAP_CONF_PTR(map));
253 static void ipu_dc_write_tmpl(int word, u32 opcode, u32 operand, int map,
254 int wave, int glue, int sync)
261 reg |= (++wave << 11);
262 reg |= (++map << 15);
263 reg |= (operand << 20) & 0xFFF00000;
264 __raw_writel(reg, ipu_dc_tmpl_reg + word * 2);
266 reg = (operand >> 12);
269 __raw_writel(reg, ipu_dc_tmpl_reg + word * 2 + 1);
272 static void ipu_dc_link_event(int chan, int event, int addr, int priority)
276 reg = __raw_readl(DC_RL_CH(chan, event));
277 reg &= ~(0xFFFF << (16 * (event & 0x1)));
278 reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
279 __raw_writel(reg, DC_RL_CH(chan, event));
282 /* Y = R * 1.200 + G * 2.343 + B * .453 + 0.250;
283 * U = R * -.672 + G * -1.328 + B * 2.000 + 512.250.;
284 * V = R * 2.000 + G * -1.672 + B * -.328 + 512.250.;
286 static const int rgb2ycbcr_coeff[5][3] = {
288 {0x3D5, 0x3AB, 0x80},
289 {0x80, 0x395, 0x3EB},
290 {0x0000, 0x0200, 0x0200}, /* B0, B1, B2 */
291 {0x2, 0x2, 0x2}, /* S0, S1, S2 */
294 /* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
295 * G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
296 * B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128);
298 static const int ycbcr2rgb_coeff[5][3] = {
299 {0x095, 0x000, 0x0CC},
300 {0x095, 0x3CE, 0x398},
301 {0x095, 0x0FF, 0x000},
302 {0x3E42, 0x010A, 0x3DD6}, /*B0,B1,B2 */
303 {0x1, 0x1, 0x1}, /*S0,S1,S2 */
306 #define mask_a(a) ((u32)(a) & 0x3FF)
307 #define mask_b(b) ((u32)(b) & 0x3FFF)
309 /* Pls keep S0, S1 and S2 as 0x2 by using this convertion */
310 static int rgb_to_yuv(int n, int red, int green, int blue)
313 c = red * rgb2ycbcr_coeff[n][0];
314 c += green * rgb2ycbcr_coeff[n][1];
315 c += blue * rgb2ycbcr_coeff[n][2];
317 c += rgb2ycbcr_coeff[3][n] * 4;
328 * Row is for BG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
329 * Column is for FG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
331 static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = {
333 {DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff},
336 {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff},
337 {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff}
341 {DP_COM_CONF_CSC_DEF_BOTH, &ycbcr2rgb_coeff},
342 {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff},
344 {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff}
348 {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff},
354 {DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff},
361 {DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff},
362 {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff},
369 static enum csc_type_t fg_csc_type = CSC_NONE, bg_csc_type = CSC_NONE;
370 static int color_key_4rgb = 1;
372 void ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param,
373 unsigned char srm_mode_update)
376 const int (*coeff)[5][3];
378 if (dp_csc_param.mode >= 0) {
379 reg = __raw_readl(DP_COM_CONF());
380 reg &= ~DP_COM_CONF_CSC_DEF_MASK;
381 reg |= dp_csc_param.mode;
382 __raw_writel(reg, DP_COM_CONF());
385 coeff = dp_csc_param.coeff;
388 __raw_writel(mask_a((*coeff)[0][0]) |
389 (mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0());
390 __raw_writel(mask_a((*coeff)[0][2]) |
391 (mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1());
392 __raw_writel(mask_a((*coeff)[1][1]) |
393 (mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2());
394 __raw_writel(mask_a((*coeff)[2][0]) |
395 (mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3());
396 __raw_writel(mask_a((*coeff)[2][2]) |
397 (mask_b((*coeff)[3][0]) << 16) |
398 ((*coeff)[4][0] << 30), DP_CSC_0());
399 __raw_writel(mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) |
400 (mask_b((*coeff)[3][2]) << 16) |
401 ((*coeff)[4][2] << 30), DP_CSC_1());
404 if (srm_mode_update) {
405 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
406 __raw_writel(reg, IPU_SRM_PRI2);
410 int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
411 uint32_t out_pixel_fmt)
418 if (channel == MEM_FG_SYNC) {
421 } else if (channel == MEM_BG_SYNC) {
424 } else if (channel == MEM_BG_ASYNC0) {
431 in_fmt = format_to_colorspace(in_pixel_fmt);
432 out_fmt = format_to_colorspace(out_pixel_fmt);
437 fg_csc_type = RGB2RGB;
439 fg_csc_type = RGB2YUV;
442 fg_csc_type = YUV2RGB;
444 fg_csc_type = YUV2YUV;
449 bg_csc_type = RGB2RGB;
451 bg_csc_type = RGB2YUV;
454 bg_csc_type = YUV2RGB;
456 bg_csc_type = YUV2YUV;
460 /* Transform color key from rgb to yuv if CSC is enabled */
461 reg = __raw_readl(DP_COM_CONF());
462 if (color_key_4rgb && (reg & DP_COM_CONF_GWCKE) &&
463 (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||
464 ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||
465 ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) ||
466 ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB)))) {
467 int red, green, blue;
469 uint32_t color_key = __raw_readl(DP_GRAPH_WIND_CTRL()) &
472 debug("_ipu_dp_init color key 0x%x need change to yuv fmt!\n",
475 red = (color_key >> 16) & 0xFF;
476 green = (color_key >> 8) & 0xFF;
477 blue = color_key & 0xFF;
479 y = rgb_to_yuv(0, red, green, blue);
480 u = rgb_to_yuv(1, red, green, blue);
481 v = rgb_to_yuv(2, red, green, blue);
482 color_key = (y << 16) | (u << 8) | v;
484 reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L;
485 __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL());
488 debug("_ipu_dp_init color key change to yuv fmt 0x%x!\n",
492 ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 1);
497 void ipu_dp_uninit(ipu_channel_t channel)
502 if (channel == MEM_FG_SYNC) {
505 } else if (channel == MEM_BG_SYNC) {
508 } else if (channel == MEM_BG_ASYNC0) {
516 fg_csc_type = CSC_NONE;
518 bg_csc_type = CSC_NONE;
520 ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 0);
523 void ipu_dc_init(int dc_chan, int di, unsigned char interlaced)
527 if ((dc_chan == 1) || (dc_chan == 5)) {
529 ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 3);
530 ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 2);
531 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 1);
534 ipu_dc_link_event(dc_chan, DC_EVT_NL, 2, 3);
535 ipu_dc_link_event(dc_chan, DC_EVT_EOL, 3, 2);
536 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA,
539 ipu_dc_link_event(dc_chan, DC_EVT_NL, 5, 3);
540 ipu_dc_link_event(dc_chan, DC_EVT_EOL, 6, 2);
541 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA,
545 ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0);
546 ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0);
547 ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0);
548 ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0);
549 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0);
550 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0);
553 reg |= DC_DISP_ID_SYNC(di) << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
556 reg |= DC_WR_CH_CONF_FIELD_MODE;
557 } else if ((dc_chan == 8) || (dc_chan == 9)) {
559 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0x64, 1);
560 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0x64, 1);
563 reg |= DC_DISP_ID_SERIAL << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
565 __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
567 __raw_writel(0x00000000, DC_WR_CH_ADDR(dc_chan));
569 __raw_writel(0x00000084, DC_GEN);
572 void ipu_dc_uninit(int dc_chan)
574 if ((dc_chan == 1) || (dc_chan == 5)) {
575 ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 0);
576 ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 0);
577 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 0);
578 ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0);
579 ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0);
580 ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0);
581 ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0);
582 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0);
583 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0);
584 } else if ((dc_chan == 8) || (dc_chan == 9)) {
585 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_0, 0, 0);
586 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_1, 0, 0);
587 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_0, 0, 0);
588 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_1, 0, 0);
589 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0, 0);
590 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0, 0);
591 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_0, 0, 0);
592 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_1, 0, 0);
593 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_0, 0, 0);
594 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_1, 0, 0);
595 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_0, 0, 0);
596 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_1, 0, 0);
600 int ipu_chan_is_interlaced(ipu_channel_t channel)
602 if (channel == MEM_DC_SYNC)
603 return !!(__raw_readl(DC_WR_CH_CONF_1) &
604 DC_WR_CH_CONF_FIELD_MODE);
605 else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))
606 return !!(__raw_readl(DC_WR_CH_CONF_5) &
607 DC_WR_CH_CONF_FIELD_MODE);
611 void ipu_dp_dc_enable(ipu_channel_t channel)
617 if (channel == MEM_FG_SYNC)
619 if (channel == MEM_DC_SYNC)
621 else if (channel == MEM_BG_SYNC)
626 if (channel == MEM_FG_SYNC) {
627 /* Enable FG channel */
628 reg = __raw_readl(DP_COM_CONF());
629 __raw_writel(reg | DP_COM_CONF_FG_EN, DP_COM_CONF());
631 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
632 __raw_writel(reg, IPU_SRM_PRI2);
636 di = g_dc_di_assignment[dc_chan];
638 /* Make sure other DC sync channel is not assigned same DI */
639 reg = __raw_readl(DC_WR_CH_CONF(6 - dc_chan));
640 if ((di << 2) == (reg & DC_WR_CH_CONF_PROG_DI_ID)) {
641 reg &= ~DC_WR_CH_CONF_PROG_DI_ID;
642 reg |= di ? 0 : DC_WR_CH_CONF_PROG_DI_ID;
643 __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan));
646 reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
647 reg |= 4 << DC_WR_CH_CONF_PROG_TYPE_OFFSET;
648 __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
650 clk_enable(g_pixel_clk[di]);
653 static unsigned char dc_swap;
655 void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap)
659 uint32_t dc_chan = 0;
664 if (channel == MEM_DC_SYNC) {
666 } else if (channel == MEM_BG_SYNC) {
668 } else if (channel == MEM_FG_SYNC) {
669 /* Disable FG channel */
672 reg = __raw_readl(DP_COM_CONF());
673 csc = reg & DP_COM_CONF_CSC_DEF_MASK;
674 if (csc == DP_COM_CONF_CSC_DEF_FG)
675 reg &= ~DP_COM_CONF_CSC_DEF_MASK;
677 reg &= ~DP_COM_CONF_FG_EN;
678 __raw_writel(reg, DP_COM_CONF());
680 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
681 __raw_writel(reg, IPU_SRM_PRI2);
686 * Wait for DC triple buffer to empty,
687 * this check is useful for tv overlay.
689 if (g_dc_di_assignment[dc_chan] == 0)
690 while ((__raw_readl(DC_STAT) & 0x00000002)
697 else if (g_dc_di_assignment[dc_chan] == 1)
698 while ((__raw_readl(DC_STAT) & 0x00000020)
711 /* Swap DC channel 1 and 5 settings, and disable old dc chan */
712 reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
713 __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan));
714 reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
715 reg ^= DC_WR_CH_CONF_PROG_DI_ID;
716 __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
720 /* Wait for DC triple buffer to empty */
721 if (g_dc_di_assignment[dc_chan] == 0)
722 while ((__raw_readl(DC_STAT) & 0x00000002)
729 else if (g_dc_di_assignment[dc_chan] == 1)
730 while ((__raw_readl(DC_STAT) & 0x00000020)
738 reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
739 reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
740 __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
742 reg = __raw_readl(IPU_DISP_GEN);
743 if (g_dc_di_assignment[dc_chan])
744 reg &= ~DI1_COUNTER_RELEASE;
746 reg &= ~DI0_COUNTER_RELEASE;
747 __raw_writel(reg, IPU_DISP_GEN);
749 /* Clock is already off because it must be done quickly, but
750 we need to fix the ref count */
751 clk_disable(g_pixel_clk[g_dc_di_assignment[dc_chan]]);
755 void ipu_init_dc_mappings(void)
757 /* IPU_PIX_FMT_RGB24 */
759 ipu_dc_map_config(0, 0, 7, 0xFF);
760 ipu_dc_map_config(0, 1, 15, 0xFF);
761 ipu_dc_map_config(0, 2, 23, 0xFF);
763 /* IPU_PIX_FMT_RGB666 */
765 ipu_dc_map_config(1, 0, 5, 0xFC);
766 ipu_dc_map_config(1, 1, 11, 0xFC);
767 ipu_dc_map_config(1, 2, 17, 0xFC);
769 /* IPU_PIX_FMT_YUV444 */
771 ipu_dc_map_config(2, 0, 15, 0xFF);
772 ipu_dc_map_config(2, 1, 23, 0xFF);
773 ipu_dc_map_config(2, 2, 7, 0xFF);
775 /* IPU_PIX_FMT_RGB565 */
777 ipu_dc_map_config(3, 0, 4, 0xF8);
778 ipu_dc_map_config(3, 1, 10, 0xFC);
779 ipu_dc_map_config(3, 2, 15, 0xF8);
781 /* IPU_PIX_FMT_LVDS666 */
783 ipu_dc_map_config(4, 0, 5, 0xFC);
784 ipu_dc_map_config(4, 1, 11, 0xFC);
785 ipu_dc_map_config(4, 2, 17, 0xFC);
788 int ipu_pixfmt_to_map(uint32_t fmt)
791 case IPU_PIX_FMT_GENERIC:
792 case IPU_PIX_FMT_RGB24:
793 case IPU_PIX_FMT_LVDS888:
795 case IPU_PIX_FMT_RGB666:
797 case IPU_PIX_FMT_YUV444:
799 case IPU_PIX_FMT_RGB565:
801 case IPU_PIX_FMT_LVDS666:
809 * This function is called to adapt synchronous LCD panel to IPU restriction.
811 void adapt_panel_to_ipu_restricitions(uint32_t *pixel_clk,
812 uint16_t width, uint16_t height,
813 uint16_t h_start_width,
814 uint16_t h_end_width,
815 uint16_t v_start_width,
816 uint16_t *v_end_width)
818 if (*v_end_width < 2) {
819 uint16_t total_width = width + h_start_width + h_end_width;
820 uint16_t total_height_old = height + v_start_width +
822 uint16_t total_height_new = height + v_start_width + 2;
824 *pixel_clk = (*pixel_clk) * total_width * total_height_new /
825 (total_width * total_height_old);
826 printf("WARNING: adapt panel end blank lines\n");
831 * This function is called to initialize a synchronous LCD panel.
833 * @param disp The DI the panel is attached to.
835 * @param pixel_clk Desired pixel clock frequency in Hz.
837 * @param pixel_fmt Input parameter for pixel format of buffer.
838 * Pixel format is a FOURCC ASCII code.
840 * @param width The width of panel in pixels.
842 * @param height The height of panel in pixels.
844 * @param hStartWidth The number of pixel clocks between the HSYNC
845 * signal pulse and the start of valid data.
847 * @param hSyncWidth The width of the HSYNC signal in units of pixel
850 * @param hEndWidth The number of pixel clocks between the end of
851 * valid data and the HSYNC signal for next line.
853 * @param vStartWidth The number of lines between the VSYNC
854 * signal pulse and the start of valid data.
856 * @param vSyncWidth The width of the VSYNC signal in units of lines
858 * @param vEndWidth The number of lines between the end of valid
859 * data and the VSYNC signal for next frame.
861 * @param sig Bitfield of signal polarities for LCD interface.
863 * @return This function returns 0 on success or negative error code on
867 int ipu_init_sync_panel(int disp, uint32_t pixel_clk,
868 uint16_t width, uint16_t height,
870 uint16_t h_start_width, uint16_t h_sync_width,
871 uint16_t h_end_width, uint16_t v_start_width,
872 uint16_t v_sync_width, uint16_t v_end_width,
873 uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig)
876 uint32_t di_gen, vsync_cnt;
877 uint32_t div, rounded_pixel_clk;
878 uint32_t h_total, v_total;
880 struct clk *di_parent;
882 debug("panel size = %d x %d\n", width, height);
884 if ((v_sync_width == 0) || (h_sync_width == 0))
887 adapt_panel_to_ipu_restricitions(&pixel_clk, width, height,
888 h_start_width, h_end_width,
889 v_start_width, &v_end_width);
890 h_total = width + h_sync_width + h_start_width + h_end_width;
891 v_total = height + v_sync_width + v_start_width + v_end_width;
894 debug("pixel clk = %d\n", pixel_clk);
897 if (!(g_di1_tvout && (disp == 1))) { /* don't round div for tvout */
899 * Set the PLL to be an even multiple
900 * of the pixel clock.
902 if ((clk_get_usecount(g_pixel_clk[0]) == 0) &&
903 (clk_get_usecount(g_pixel_clk[1]) == 0)) {
904 di_parent = clk_get_parent(g_di_clk[disp]);
906 clk_round_rate(g_pixel_clk[disp],
908 if (di_parent != NULL) {
909 div = clk_get_rate(di_parent) /
913 if (clk_get_rate(di_parent) != div *
915 clk_set_rate(di_parent,
916 div * rounded_pixel_clk);
918 clk_set_rate(g_di_clk[disp],
919 2 * rounded_pixel_clk);
924 clk_set_parent(g_pixel_clk[disp], g_ldb_clk);
926 if (clk_get_usecount(g_pixel_clk[disp]) != 0)
927 clk_set_parent(g_pixel_clk[disp], g_ipu_clk);
929 rounded_pixel_clk = clk_round_rate(g_pixel_clk[disp], pixel_clk);
930 clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk);
932 /* Get integer portion of divider */
933 div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) /
936 /* Enable for a divide by 2 clock change. */
937 reg = __raw_readl(IPU_PM);
940 reg &= ~(0x7f << 23);
942 __raw_writel(reg, IPU_PM);
946 if (pixel_fmt != IPU_PIX_FMT_LVDS666 &&
947 pixel_fmt != IPU_PIX_FMT_LVDS888) {
948 clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk);
950 /* Get integer portion of divider */
951 div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) /
953 ipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1);
955 clk_set_rate(g_pixel_clk[disp], clk_get_rate(g_ipu_clk));
957 ipu_di_data_wave_config(disp, SYNC_WAVE, 0, 0);
959 di_gen |= DI_GEN_DI_CLK_EXT;
961 ipu_di_data_pin_config(disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);
963 map = ipu_pixfmt_to_map(pixel_fmt);
965 debug("IPU_DISP: No MAP\n");
969 if (sig.interlaced) {
970 /* Setup internal HSYNC waveform */
974 h_total / 2 - 1,/* run count */
975 DI_SYNC_CLK, /* run_resolution */
977 DI_SYNC_NONE, /* offset resolution */
978 0, /* repeat count */
979 DI_SYNC_NONE, /* CNT_CLR_SEL */
980 0, /* CNT_POLARITY_GEN_EN */
981 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
982 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
987 /* Field 1 VSYNC waveform */
991 h_total - 1, /* run count */
992 DI_SYNC_CLK, /* run_resolution */
994 DI_SYNC_NONE, /* offset resolution */
995 0, /* repeat count */
996 DI_SYNC_NONE, /* CNT_CLR_SEL */
997 0, /* CNT_POLARITY_GEN_EN */
998 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
999 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
1004 /* Setup internal HSYNC waveform */
1008 v_total * 2 - 1,/* run count */
1009 DI_SYNC_INT_HSYNC, /* run_resolution */
1011 DI_SYNC_INT_HSYNC, /* offset resolution */
1012 0, /* repeat count */
1013 DI_SYNC_NONE, /* CNT_CLR_SEL */
1014 0, /* CNT_POLARITY_GEN_EN */
1015 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
1016 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
1021 /* Active Field ? */
1025 v_total / 2 - 1,/* run count */
1026 DI_SYNC_HSYNC, /* run_resolution */
1027 v_start_width, /* offset */
1028 DI_SYNC_HSYNC, /* offset resolution */
1029 2, /* repeat count */
1030 DI_SYNC_VSYNC, /* CNT_CLR_SEL */
1031 0, /* CNT_POLARITY_GEN_EN */
1032 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
1033 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
1043 DI_SYNC_HSYNC, /* run_resolution */
1045 DI_SYNC_NONE, /* offset resolution */
1046 height / 2, /* repeat count */
1047 4, /* CNT_CLR_SEL */
1048 0, /* CNT_POLARITY_GEN_EN */
1049 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
1050 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
1055 /* Field 0 VSYNC waveform */
1059 v_total - 1, /* run count */
1060 DI_SYNC_HSYNC, /* run_resolution */
1062 DI_SYNC_NONE, /* offset resolution */
1063 0, /* repeat count */
1064 DI_SYNC_NONE, /* CNT_CLR_SEL */
1065 0, /* CNT_POLARITY_GEN_EN */
1066 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
1067 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
1072 /* DC VSYNC waveform */
1077 v_total / 2 - 1,/* run count */
1078 DI_SYNC_HSYNC, /* run_resolution */
1080 DI_SYNC_HSYNC, /* offset resolution */
1081 2, /* repeat count */
1082 DI_SYNC_VSYNC, /* CNT_CLR_SEL */
1083 0, /* CNT_POLARITY_GEN_EN */
1084 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
1085 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
1090 /* active pixel waveform */
1095 DI_SYNC_CLK, /* run_resolution */
1096 h_start_width, /* offset */
1097 DI_SYNC_CLK, /* offset resolution */
1098 width, /* repeat count */
1099 5, /* CNT_CLR_SEL */
1100 0, /* CNT_POLARITY_GEN_EN */
1101 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
1102 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
1110 v_total - 1, /* run count */
1111 DI_SYNC_INT_HSYNC,/* run_resolution */
1112 v_total / 2, /* offset */
1113 DI_SYNC_INT_HSYNC,/* offset resolution */
1114 0, /* repeat count */
1115 DI_SYNC_HSYNC, /* CNT_CLR_SEL */
1116 0, /* CNT_POLARITY_GEN_EN */
1117 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
1118 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
1123 /* set gentime select and tag sel */
1124 reg = __raw_readl(DI_SW_GEN1(disp, 9));
1126 reg |= ((3 - 1) << 29) | 0x00008000;
1127 __raw_writel(reg, DI_SW_GEN1(disp, 9));
1129 __raw_writel(v_total / 2 - 1, DI_SCR_CONF(disp));
1132 di_gen |= 0x10000000;
1133 di_gen |= DI_GEN_POLARITY_5;
1134 di_gen |= DI_GEN_POLARITY_8;
1136 /* Setup internal HSYNC waveform */
1137 ipu_di_sync_config(disp, 1, h_total - 1, DI_SYNC_CLK,
1138 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
1140 DI_SYNC_NONE, 0, 0);
1142 /* Setup external (delayed) HSYNC waveform */
1143 ipu_di_sync_config(disp, DI_SYNC_HSYNC, h_total - 1,
1144 DI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK,
1145 0, DI_SYNC_NONE, 1, DI_SYNC_NONE,
1146 DI_SYNC_CLK, 0, h_sync_width * 2);
1147 /* Setup VSYNC waveform */
1148 vsync_cnt = DI_SYNC_VSYNC;
1149 ipu_di_sync_config(disp, DI_SYNC_VSYNC, v_total - 1,
1150 DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0,
1151 DI_SYNC_NONE, 1, DI_SYNC_NONE,
1152 DI_SYNC_INT_HSYNC, 0, v_sync_width * 2);
1153 __raw_writel(v_total - 1, DI_SCR_CONF(disp));
1155 /* Setup active data waveform to sync with DC */
1156 ipu_di_sync_config(disp, 4, 0, DI_SYNC_HSYNC,
1157 v_sync_width + v_start_width, DI_SYNC_HSYNC,
1159 DI_SYNC_VSYNC, 0, DI_SYNC_NONE,
1160 DI_SYNC_NONE, 0, 0);
1161 ipu_di_sync_config(disp, 5, 0, DI_SYNC_CLK,
1162 h_sync_width + h_start_width, DI_SYNC_CLK,
1163 width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0,
1166 /* reset all unused counters */
1167 __raw_writel(0, DI_SW_GEN0(disp, 6));
1168 __raw_writel(0, DI_SW_GEN1(disp, 6));
1169 __raw_writel(0, DI_SW_GEN0(disp, 7));
1170 __raw_writel(0, DI_SW_GEN1(disp, 7));
1171 __raw_writel(0, DI_SW_GEN0(disp, 8));
1172 __raw_writel(0, DI_SW_GEN1(disp, 8));
1173 __raw_writel(0, DI_SW_GEN0(disp, 9));
1174 __raw_writel(0, DI_SW_GEN1(disp, 9));
1176 reg = __raw_readl(DI_STP_REP(disp, 6));
1178 __raw_writel(reg, DI_STP_REP(disp, 6));
1179 __raw_writel(0, DI_STP_REP(disp, 7));
1180 __raw_writel(0, DI_STP_REP(disp, 9));
1182 h_total = ((width + h_start_width + h_sync_width) / 2) - 2;
1183 ipu_di_sync_config(disp, 6, 1, 0, 2, DI_SYNC_CLK, h_total,
1184 DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE,
1185 DI_SYNC_NONE, 0, 0);
1187 /* Init template microcode */
1189 ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5);
1190 ipu_dc_write_tmpl(3, WROD(0), 0, map, SYNC_WAVE, 4, 5);
1191 ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5);
1193 ipu_dc_write_tmpl(5, WROD(0), 0, map, SYNC_WAVE, 8, 5);
1194 ipu_dc_write_tmpl(6, WROD(0), 0, map, SYNC_WAVE, 4, 5);
1195 ipu_dc_write_tmpl(7, WROD(0), 0, map, SYNC_WAVE, 0, 5);
1199 di_gen |= DI_GEN_POLARITY_2;
1201 di_gen |= DI_GEN_POLARITY_3;
1204 di_gen |= DI_GEN_POL_CLK;
1206 /* Set the clock to stop at counter 6. */
1207 di_gen |= 0x6000000;
1210 __raw_writel(di_gen, DI_GENERAL(disp));
1213 __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) |
1214 0x00000002, DI_SYNC_AS_GEN(disp));
1216 __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET),
1217 DI_SYNC_AS_GEN(disp));
1219 reg = __raw_readl(DI_POL(disp));
1220 reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
1222 reg |= DI_POL_DRDY_POLARITY_15;
1224 reg |= DI_POL_DRDY_DATA_POLARITY;
1225 __raw_writel(reg, DI_POL(disp));
1227 __raw_writel(width, DC_DISP_CONF2(DC_DISP_ID_SYNC(disp)));
1233 * This function sets the foreground and background plane global alpha blending
1234 * modes. This function also sets the DP graphic plane according to the
1235 * parameter of IPUv3 DP channel.
1237 * @param channel IPUv3 DP channel
1239 * @param enable Boolean to enable or disable global alpha
1240 * blending. If disabled, local blending is used.
1242 * @param alpha Global alpha value.
1244 * @return Returns 0 on success or negative error code on fail
1246 int ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
1252 unsigned char bg_chan;
1254 if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) ||
1255 (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) ||
1256 (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)))
1259 if (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 ||
1260 channel == MEM_BG_ASYNC1)
1265 ret = clk_enable(g_ipu_clk);
1270 reg = __raw_readl(DP_COM_CONF());
1271 __raw_writel(reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF());
1273 reg = __raw_readl(DP_COM_CONF());
1274 __raw_writel(reg | DP_COM_CONF_GWSEL, DP_COM_CONF());
1278 reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0x00FFFFFFL;
1279 __raw_writel(reg | ((uint32_t) alpha << 24),
1280 DP_GRAPH_WIND_CTRL());
1282 reg = __raw_readl(DP_COM_CONF());
1283 __raw_writel(reg | DP_COM_CONF_GWAM, DP_COM_CONF());
1285 reg = __raw_readl(DP_COM_CONF());
1286 __raw_writel(reg & ~DP_COM_CONF_GWAM, DP_COM_CONF());
1289 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
1290 __raw_writel(reg, IPU_SRM_PRI2);
1292 clk_disable(g_ipu_clk);
1298 * This function sets the transparent color key for SDC graphic plane.
1300 * @param channel Input parameter for the logical channel ID.
1302 * @param enable Boolean to enable or disable color key
1304 * @param colorKey 24-bit RGB color for transparent color key.
1306 * @return Returns 0 on success or negative error code on fail
1308 int ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
1314 int red, green, blue;
1316 if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) ||
1317 (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) ||
1318 (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)))
1321 ret = clk_enable(g_ipu_clk);
1326 /* Transform color key from rgb to yuv if CSC is enabled */
1327 if (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||
1328 ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||
1329 ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) ||
1330 ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB))) {
1332 debug("color key 0x%x need change to yuv fmt\n", color_key);
1334 red = (color_key >> 16) & 0xFF;
1335 green = (color_key >> 8) & 0xFF;
1336 blue = color_key & 0xFF;
1338 y = rgb_to_yuv(0, red, green, blue);
1339 u = rgb_to_yuv(1, red, green, blue);
1340 v = rgb_to_yuv(2, red, green, blue);
1341 color_key = (y << 16) | (u << 8) | v;
1345 debug("color key change to yuv fmt 0x%x\n", color_key);
1349 reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L;
1350 __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL());
1352 reg = __raw_readl(DP_COM_CONF());
1353 __raw_writel(reg | DP_COM_CONF_GWCKE, DP_COM_CONF());
1355 reg = __raw_readl(DP_COM_CONF());
1356 __raw_writel(reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF());
1359 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
1360 __raw_writel(reg, IPU_SRM_PRI2);
1362 clk_disable(g_ipu_clk);