2 * Copyright (C) 2012 <LW@KARO-electronics.de>
4 * SPDX-License-Identifier: GPL-2.0
11 #define CONFIG_MX53 /* must be set before including imx-regs.h */
13 #include <asm/sizes.h>
14 #include <asm/arch/imx-regs.h>
17 * Ka-Ro TX53 board - SoC configuration
19 #define CONFIG_TX53 /* TX53 SoM */
20 #define CONFIG_SYS_MX5_IOMUX_V3
21 #define CONFIG_MXC_GPIO /* GPIO control */
22 #define CONFIG_SYS_MX5_HCLK 24000000
23 #define CONFIG_SYS_DDR_CLKSEL 0
24 #define CONFIG_SYS_HZ 1000 /* Ticks per second */
25 #define CONFIG_SHOW_ACTIVITY
26 #define CONFIG_DISPLAY_BOARDINFO
27 #define CONFIG_BOARD_LATE_INIT
28 #define CONFIG_BOARD_EARLY_INIT_F
30 /* LCD Logo and Splash screen support */
33 #define CONFIG_SPLASH_SCREEN
34 #define CONFIG_SPLASH_SCREEN_ALIGN
35 #define CONFIG_VIDEO_IPUV3
36 #define CONFIG_IPUV3_CLK 200000000
37 #define CONFIG_LCD_LOGO
38 #define LCD_BPP LCD_COLOR24
39 #define CONFIG_CMD_BMP
40 #define CONFIG_VIDEO_BMP_RLE8
41 #endif /* CONFIG_LCD */
44 * Memory configurations
46 #define PHYS_SDRAM_1 0x70000000 /* Base address of bank 1 */
47 #define PHYS_SDRAM_1_SIZE SZ_512M
48 #if CONFIG_NR_DRAM_BANKS > 1
49 #define PHYS_SDRAM_2 0xb0000000 /* Base address of bank 2 */
50 #define PHYS_SDRAM_2_SIZE SZ_512M
51 #define TX53_MOD_SUFFIX "1"
53 #define TX53_MOD_SUFFIX "0"
55 #define CONFIG_STACKSIZE SZ_128K
56 #define CONFIG_SYS_MALLOC_LEN SZ_8M
57 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */
58 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + SZ_4M) /* 4 MB RAM test */
59 #define CONFIG_SYS_SDRAM_CLK 400
62 * U-Boot general configurations
64 #define CONFIG_SYS_LONGHELP
65 #define CONFIG_SYS_PROMPT "TX53 U-Boot > "
66 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
67 #define CONFIG_SYS_PBSIZE \
68 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
69 /* Print buffer size */
70 #define CONFIG_SYS_MAXARGS 64 /* Max number of command args */
71 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
72 /* Boot argument buffer size */
73 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
74 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
75 #define CONFIG_CMDLINE_EDITING /* Command history etc */
77 #define CONFIG_SYS_64BIT_VSPRINTF
78 #define CONFIG_SYS_NO_FLASH
81 * Flattened Device Tree (FDT) support
83 #define CONFIG_OF_LIBFDT
84 #define CONFIG_OF_EMBED
85 #define CONFIG_OF_BOARD_SETUP
86 #define CONFIG_DEFAULT_DEVICE_TREE tx53
87 #define CONFIG_ARCH_DEVICE_TREE mx53
88 #define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M)
93 #define xstr(s) str(s)
95 #define __pfx(x, s) (x##s)
96 #define _pfx(x, s) __pfx(x, s)
98 #define CONFIG_CMDLINE_TAG
99 #define CONFIG_SETUP_MEMORY_TAGS
100 #define CONFIG_BOOTDELAY 3
101 #define CONFIG_ZERO_BOOTDELAY_CHECK
102 #define CONFIG_SYS_AUTOLOAD "no"
103 #define CONFIG_BOOTFILE "uImage"
104 #define CONFIG_BOOTARGS "console=ttymxc0,115200 ro debug panic=1"
105 #define CONFIG_BOOTCOMMAND "run bootcmd_nand"
106 #define CONFIG_LOADADDR 78000000
107 #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
108 #define CONFIG_U_BOOT_IMG_SIZE SZ_1M
109 #define CONFIG_HW_WATCHDOG
114 #define CONFIG_EXTRA_ENV_SETTINGS \
116 "baseboard=stk5-v3\0" \
117 "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
118 " root=/dev/mmcblk0p3 rootwait\0" \
119 "bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \
120 " root=/dev/mtdblock3 rootfstype=jffs2\0" \
121 "nfsroot=/tftpboot/rootfs\0" \
122 "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
123 " root=/dev/nfs ip=dhcp nfsroot=${nfs_server}:${nfsroot},nolock\0"\
124 "bootcmd_mmc=set autostart no;run bootargs_mmc;" \
125 "mmc read ${loadaddr} 100 3000;run bootm_cmd\0" \
126 "bootcmd_nand=set autostart no;run bootargs_nand;" \
127 "nboot linux;run bootm_cmd\0" \
128 "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \
130 "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \
131 "default_bootargs=set bootargs " CONFIG_BOOTARGS \
132 " video=${video_mode} ${append_bootargs}\0" \
134 "fdtaddr=71000000\0" \
135 "mtdids=" MTDIDS_DEFAULT "\0" \
136 "mtdparts=" MTDPARTS_DEFAULT "\0" \
137 "otg_mode=device\0" \
138 "touchpanel=tsc2007\0" \
139 "video_mode=VGA-1:640x480MR-24@60\0"
141 #define MTD_NAME "mxc_nand"
142 #define MTDIDS_DEFAULT "nand0=" MTD_NAME
143 #define CONFIG_FDT_FIXUP_PARTITIONS
148 #include <config_cmd_default.h>
149 #define CONFIG_CMD_CACHE
150 #define CONFIG_CMD_MMC
151 #define CONFIG_CMD_NAND
152 #define CONFIG_CMD_MTDPARTS
153 #define CONFIG_CMD_BOOTCE
154 #define CONFIG_CMD_TIME
155 #define CONFIG_CMD_MEMTEST
160 #define CONFIG_MXC_UART
161 #define CONFIG_MXC_UART_BASE UART1_BASE
162 #define CONFIG_MXC_GPIO
163 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
164 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
165 #define CONFIG_SYS_CONSOLE_INFO_QUIET
170 #define CONFIG_FEC_MXC
171 #ifdef CONFIG_FEC_MXC
172 #define IMX_FEC_BASE FEC_BASE_ADDR
173 #define CONFIG_FEC_MXC_PHYADDR 0
174 #define CONFIG_PHYLIB
175 #define CONFIG_PHY_SMSC
177 #define CONFIG_FEC_XCV_TYPE MII100
178 #define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
179 #define CONFIG_CMD_MII
180 #define CONFIG_CMD_DHCP
181 #define CONFIG_CMD_PING
182 /* Add for working with "strict" DHCP server */
183 #define CONFIG_BOOTP_SUBNETMASK
184 #define CONFIG_BOOTP_GATEWAY
185 #define CONFIG_BOOTP_DNS
191 #ifdef CONFIG_CMD_NAND
192 #define CONFIG_MTD_DEVICE
193 #define CONFIG_ENV_IS_IN_NAND
194 #define CONFIG_NAND_MXC
195 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
196 #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
197 #define CONFIG_MXC_NAND_HWECC
198 #define CONFIG_CMD_NAND_TRIMFFS
199 #define CONFIG_SYS_MAX_FLASH_SECT 1024
200 #define CONFIG_SYS_MAX_FLASH_BANKS 1
201 #define CONFIG_SYS_NAND_MAX_CHIPS 1
202 #define CONFIG_SYS_MAX_NAND_DEVICE 1
203 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
204 #define CONFIG_SYS_NAND_USE_FLASH_BBT
205 #ifdef CONFIG_ENV_IS_IN_NAND
206 #define CONFIG_ENV_OVERWRITE
207 #define CONFIG_ENV_OFFSET CONFIG_U_BOOT_IMG_SIZE
208 #define CONFIG_ENV_SIZE 0x20000 /* 128 KiB */
209 #define CONFIG_ENV_RANGE 0x60000
211 #ifndef CONFIG_SYS_NO_FLASH
212 #define CONFIG_CMD_FLASH
213 #define CONFIG_SYS_NAND_BASE 0xa0000000
216 #define CONFIG_SYS_NAND_BASE 0x00000000
217 #define CONFIG_CMD_ROMUPDATE
219 #endif /* CONFIG_CMD_NAND */
224 #ifdef CONFIG_CMD_MMC
225 #ifndef CONFIG_ENV_IS_IN_NAND
226 #define CONFIG_ENV_IS_IN_MMC
229 #define CONFIG_GENERIC_MMC
230 #define CONFIG_FSL_ESDHC
231 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
232 #define CONFIG_SYS_FSL_ESDHC_NUM 2
234 #define CONFIG_DOS_PARTITION
235 #define CONFIG_CMD_FAT
236 #define CONFIG_CMD_EXT2
239 * Environments on MMC
241 #ifdef CONFIG_ENV_IS_IN_MMC
242 #define CONFIG_SYS_MMC_ENV_DEV 0
243 #define CONFIG_ENV_OVERWRITE
244 /* Associated with the MMC layout defined in mmcops.c */
245 #define CONFIG_ENV_OFFSET SZ_1K
246 #define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET)
247 #define CONFIG_DYNAMIC_MMC_DEVNO
248 #endif /* CONFIG_ENV_IS_IN_MMC */
249 #endif /* CONFIG_CMD_MMC */
251 #ifdef CONFIG_ENV_OFFSET_REDUND
252 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
254 xstr(CONFIG_ENV_RANGE) \
256 xstr(CONFIG_ENV_RANGE) \
257 "(env2),4m(linux),16m(rootfs),256k(dtb),-(userfs)"
259 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
261 xstr(CONFIG_ENV_RANGE) \
262 "(env),4m(linux),16m(rootfs),256k(dtb),-(userfs)"
265 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
266 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
267 GENERATED_GBL_DATA_SIZE)
269 #ifdef CONFIG_CMD_IIM
270 #define CONFIG_FSL_IIM
273 #endif /* __CONFIG_H */