2 * Copyright (C) 2012-2015 <LW@KARO-electronics.de>
4 * SPDX-License-Identifier: GPL-2.0
11 #ifndef CONFIG_SOC_MX6UL
12 #define CONFIG_ARM_ERRATA_743622
13 #define CONFIG_ARM_ERRATA_751472
14 #define CONFIG_ARM_ERRATA_794072
15 #define CONFIG_ARM_ERRATA_761320
17 #ifndef CONFIG_SYS_L2CACHE_OFF
18 #define CONFIG_SYS_L2_PL310
19 #define CONFIG_SYS_PL310_BASE L2_PL310_BASE
22 #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
25 #define CONFIG_BOARD_POSTCLK_INIT
26 #define CONFIG_MXC_GPT_HCLK
28 #include <linux/kconfig.h>
29 #include <linux/sizes.h>
30 #include <asm/arch/imx-regs.h>
33 * Ka-Ro TX6 board - SoC configuration
35 #define CONFIG_SYS_MX6_HCLK 24000000
36 #define CONFIG_SYS_MX6_CLK32 32768
37 #define CONFIG_SYS_HZ 1000 /* Ticks per second */
38 #define CONFIG_SHOW_ACTIVITY
39 #define CONFIG_ARCH_CPU_INIT
40 #define CONFIG_DISPLAY_BOARDINFO
41 #define CONFIG_BOARD_LATE_INIT
42 #define CONFIG_BOARD_EARLY_INIT_F
43 #define CONFIG_SYS_GENERIC_BOARD
44 #define CONFIG_CMD_GPIO
46 #ifndef CONFIG_TX6_UBOOT_MFG
47 /* LCD Logo and Splash screen support */
49 #define CONFIG_SPLASH_SCREEN
50 #define CONFIG_SPLASH_SCREEN_ALIGN
51 #ifndef CONFIG_SOC_MX6UL
52 #define CONFIG_VIDEO_IPUV3
53 #define CONFIG_IPUV3_CLK (CONFIG_SYS_SDRAM_CLK * 1000000 / 2)
55 #define CONFIG_VIDEO_MXS
56 #define MXS_LCDIF_BASE 0x021c8000UL
57 #endif /* CONFIG_SOC_MX6UL */
58 #define CONFIG_LCD_LOGO
59 #define LCD_BPP LCD_COLOR32
60 #define CONFIG_CMD_BMP
61 #define CONFIG_BMP_8BPP
62 #define CONFIG_BMP_16BPP
63 #define CONFIG_BMP_24BPP
64 #define CONFIG_BMP_32BPP
65 #define CONFIG_VIDEO_BMP_RLE8
66 #endif /* CONFIG_LCD */
67 #endif /* CONFIG_TX6_UBOOT_MFG */
70 * Memory configuration options
72 #define CONFIG_NR_DRAM_BANKS 0x1 /* # of SDRAM banks */
73 #ifndef CONFIG_SOC_MX6UL
74 #define PHYS_SDRAM_1 0x10000000 /* Base address of bank 1 */
75 #define CONFIG_SYS_MPU_CLK 792
77 #define PHYS_SDRAM_1 0x80000000 /* Base address of bank 1 */
78 #define CONFIG_SYS_MPU_CLK 528
80 #ifndef CONFIG_SYS_SDRAM_BUS_WIDTH
81 #if defined(CONFIG_SYS_SDRAM_BUS_WIDTH_32)
82 #define CONFIG_SYS_SDRAM_BUS_WIDTH 32
83 #elif defined(CONFIG_SYS_SDRAM_BUS_WIDTH_16)
84 #define CONFIG_SYS_SDRAM_BUS_WIDTH 16
86 #define CONFIG_SYS_SDRAM_BUS_WIDTH 64
88 #endif /* CONFIG_SYS_SDRAM_BUS_WIDTH */
92 #define _AC(x,s) (x##s)
94 #define UL(x) _AC(x,UL)
95 #define PHYS_SDRAM_1_SIZE (UL(CONFIG_SYS_SDRAM_CHIP_SIZE) * SZ_1M \
96 / 32 * CONFIG_SYS_SDRAM_BUS_WIDTH)
97 #if PHYS_SDRAM_1_SIZE > SZ_1G
98 #define FDT_HIGH_STR "fdt_high=ffffffff\0"
100 #define FDT_HIGH_STR ""
103 #ifdef CONFIG_SOC_MX6Q
104 #define CONFIG_SYS_SDRAM_CLK 528
106 #define CONFIG_SYS_SDRAM_CLK 400
108 #define CONFIG_STACKSIZE SZ_128K
109 #define CONFIG_SPL_STACK (IRAM_BASE_ADDR + SZ_16K)
110 #define CONFIG_SYS_MALLOC_LEN SZ_8M
111 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */
112 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_4M)
115 * U-Boot general configurations
117 #define CONFIG_SYS_LONGHELP
118 #if defined(CONFIG_SOC_MX6Q)
119 #elif defined(CONFIG_SOC_MX6DL)
120 #elif defined(CONFIG_SOC_MX6S)
121 #elif defined(CONFIG_SOC_MX6UL)
123 #error Unsupported i.MX6 processor variant
125 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
126 #define CONFIG_SYS_PBSIZE \
127 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
128 /* Print buffer size */
129 #define CONFIG_SYS_MAXARGS 256 /* Max number of command args */
130 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
131 /* Boot argument buffer size */
132 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
133 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
134 #define CONFIG_CMDLINE_EDITING /* Command history etc */
136 #define CONFIG_SYS_64BIT_VSPRINTF
141 #define xstr(s) str(s)
143 #define __pfx(x, s) (x##s)
144 #define _pfx(x, s) __pfx(x, s)
146 #define CONFIG_CMDLINE_TAG
147 #define CONFIG_INITRD_TAG
148 #define CONFIG_SETUP_MEMORY_TAGS
149 #ifndef CONFIG_TX6_UBOOT_MFG
150 #define CONFIG_BOOTDELAY 1
152 #define CONFIG_BOOTDELAY 0
154 #define CONFIG_ZERO_BOOTDELAY_CHECK
155 #define CONFIG_SYS_AUTOLOAD "no"
156 #define DEFAULT_BOOTCMD "run bootcmd_${boot_mode} bootm_cmd"
157 #define CONFIG_BOOTFILE "uImage"
158 #define CONFIG_BOOTARGS "init=/linuxrc console=ttymxc0,115200 ro debug panic=1"
159 #ifndef CONFIG_TX6_UBOOT_MFG
160 #define CONFIG_BOOTCOMMAND DEFAULT_BOOTCMD
162 #define CONFIG_BOOTCOMMAND "setenv bootcmd '" DEFAULT_BOOTCMD "';" \
163 "env import " xstr(CONFIG_BOOTCMD_MFG_LOADADDR) ";run bootcmd_mfg"
164 #if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6UL))
165 #define CONFIG_BOOTCMD_MFG_LOADADDR 80500000
167 #define CONFIG_BOOTCMD_MFG_LOADADDR 10500000
169 #define CONFIG_DELAY_ENVIRONMENT
170 #endif /* CONFIG_TX6_UBOOT_MFG */
171 #if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6UL))
172 #define CONFIG_LOADADDR 82000000
173 #define CONFIG_FDTADDR 81000000
175 #define CONFIG_LOADADDR 18000000
176 #define CONFIG_FDTADDR 11000000
178 #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
179 #define CONFIG_SYS_FDT_ADDR _pfx(0x, CONFIG_FDTADDR)
180 #ifndef CONFIG_SYS_LVDS_IF
181 #define DEFAULT_VIDEO_MODE "VGA"
183 #define DEFAULT_VIDEO_MODE "HSD100PXN1"
189 #ifdef CONFIG_TX6_UBOOT_NOENV
190 #define CONFIG_EXTRA_ENV_SETTINGS \
193 "baseboard=stk5-v3\0" \
195 "fdtaddr=" xstr(CONFIG_FDTADDR) "\0" \
196 "mtdids=" MTDIDS_DEFAULT "\0" \
197 "mtdparts=" MTDPARTS_DEFAULT "\0"
199 #define CONFIG_SYS_CPU_CLK_STR xstr(CONFIG_SYS_MPU_CLK)
201 #define CONFIG_EXTRA_ENV_SETTINGS \
203 "baseboard=stk5-v3\0" \
204 "bootargs_jffs2=run default_bootargs" \
205 ";setenv bootargs ${bootargs}" \
206 " root=/dev/mtdblock3 rootfstype=jffs2\0" \
207 "bootargs_mmc=run default_bootargs;setenv bootargs ${bootargs}" \
209 "bootargs_nfs=run default_bootargs;setenv bootargs ${bootargs}" \
210 " root=/dev/nfs nfsroot=${nfs_server}:${nfsroot},nolock" \
212 "bootargs_ubifs=run default_bootargs" \
213 ";setenv bootargs ${bootargs}" \
214 " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0" \
215 "bootcmd_jffs2=setenv autostart no;run bootargs_jffs2" \
217 "bootcmd_mmc=setenv autostart no;run bootargs_mmc" \
218 ";fatload mmc 0 ${loadaddr} uImage\0" \
219 CONFIG_SYS_BOOT_CMD_NAND \
220 "bootcmd_net=setenv autoload y;setenv autostart n" \
221 ";run bootargs_nfs" \
223 "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \
224 "boot_mode=" CONFIG_SYS_DEFAULT_BOOT_MODE "\0" \
225 "cpu_clk=" CONFIG_SYS_CPU_CLK_STR "\0" \
226 "default_bootargs=setenv bootargs " CONFIG_BOOTARGS \
227 " ${append_bootargs}\0" \
230 "fdtaddr=" xstr(CONFIG_FDTADDR) "\0" \
233 "mtdids=" MTDIDS_DEFAULT "\0" \
234 "mtdparts=" MTDPARTS_DEFAULT "\0" \
235 "nfsroot=/tftpboot/rootfs\0" \
236 "otg_mode=device\0" \
238 "touchpanel=tsc2007\0" \
239 "video_mode=" DEFAULT_VIDEO_MODE "\0"
240 #endif /* CONFIG_ENV_IS_NOWHERE */
242 #ifdef CONFIG_TX6_NAND
243 #define CONFIG_SYS_DEFAULT_BOOT_MODE "nand"
244 #define CONFIG_SYS_BOOT_CMD_NAND \
245 "bootcmd_nand=setenv autostart no;run bootargs_ubifs;nboot linux\0"
246 #define FDTSAVE_CMD_STR \
247 "fdtsave=fdt resize;nand erase.part dtb" \
248 ";nand write ${fdtaddr} dtb ${fdtsize}\0"
249 #define MTD_NAME "gpmi-nand"
250 #define MTDIDS_DEFAULT "nand0=" MTD_NAME
251 #define CONFIG_SYS_NAND_ONFI_DETECTION
252 #define MMC_ROOT_STR " root=/dev/mmcblk0p2 rootwait\0"
253 #define ROOTPART_UUID_STR ""
254 #define EMMC_BOOT_ACK_STR ""
255 #define EMMC_BOOT_PART_STR ""
257 #define CONFIG_SYS_DEFAULT_BOOT_MODE "mmc"
258 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
259 #define CONFIG_SYS_BOOT_CMD_NAND ""
260 #define FDTSAVE_CMD_STR \
261 "fdtsave=mmc partconf 0 ${emmc_boot_ack} ${emmc_boot_part} ${emmc_boot_part}" \
262 ";mmc write ${fdtaddr} " xstr(CONFIG_SYS_DTB_BLKNO) " 80" \
263 ";mmc partconf 0 ${emmc_boot_ack} ${emmc_boot_part} 0\0"
265 #define MTDIDS_DEFAULT ""
266 #define MMC_ROOT_STR " root=PARTUUID=${rootpart_uuid} rootwait\0"
267 #define ROOTPART_UUID_STR "rootpart_uuid=0cc66cc0-02\0"
268 #define EMMC_BOOT_ACK_STR "emmc_boot_ack=1\0"
269 #define EMMC_BOOT_PART_STR "emmc_boot_part=" \
270 xstr(CONFIG_SYS_MMCSD_FS_BOOT_PARTITION) "\0"
271 #endif /* CONFIG_TX6_NAND */
276 #define CONFIG_MXC_UART
277 #define CONFIG_MXC_UART_BASE UART1_BASE
278 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
279 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
280 #define CONFIG_SYS_CONSOLE_INFO_QUIET
281 #define CONFIG_CONS_INDEX 1
286 #define CONFIG_MXC_GPIO
291 #ifdef CONFIG_FEC_MXC
292 /* This is required for the FEC driver to work with cache enabled */
293 #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
295 #ifndef CONFIG_SOC_MX6UL
296 #define CONFIG_FEC_MXC_PHYADDR 0
297 #define IMX_FEC_BASE ENET_BASE_ADDR
299 #define FEC_MDIO_BASE_ADDR ENET_BASE_ADDR
301 #define CONFIG_FEC_XCV_TYPE RMII
307 #ifdef CONFIG_HARD_I2C
308 #define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
309 #define CONFIG_SYS_I2C_SPEED 400000
310 #endif /* CONFIG_HARD_I2C */
311 #if defined(CONFIG_TX6_REV)
312 #if CONFIG_TX6_REV == 0x1
313 #define CONFIG_LTC3676
314 #elif CONFIG_TX6_REV == 0x2
315 #define CONFIG_RN5T618
316 #elif CONFIG_TX6_REV == 0x3
317 #define CONFIG_RN5T567
319 #error Unsupported TX6 module revision
321 #else /* CONFIG_TX6_REV */
322 #ifdef CONFIG_SOC_MX6UL
323 #ifdef CONFIG_SYS_I2C_SOFT
324 /* NOENV U-Boot is used for initial bootstrap.
325 * Since the TAMPER_PIN_DISABLE fuses have to be programmed
326 * to be able to use the TAMPER pins as GPIO to access the
327 * PMIC I2C bus, this is not possible on virgin hardware.
329 #define CONFIG_SYS_I2C_SOFT_SPEED 400000
330 #define CONFIG_SYS_I2C_SPEED CONFIG_SYS_I2C_SOFT_SPEED
331 #define CONFIG_SOFT_I2C_GPIO_SCL IMX_GPIO_NR(5, 0)
332 #define CONFIG_SOFT_I2C_GPIO_SDA IMX_GPIO_NR(5, 1)
333 #define CONFIG_SOFT_I2C_READ_REPEATED_START
334 #endif /* CONFIG_SYS_I2C_SOFT */
335 #else /* !CONFIG_SOC_MX6UL */
336 /* autodetect which PMIC is present to derive TX6_REV */
337 #define CONFIG_LTC3676 /* TX6_REV == 1 */
338 #endif /* CONFIG_SOC_MX6UL */
339 #define CONFIG_RN5T567 /* TX6_REV == 3 */
340 #endif /* CONFIG_TX6_REV */
342 #define CONFIG_ENV_OVERWRITE
347 #ifdef CONFIG_TX6_NAND
348 #define CONFIG_SYS_MXS_DMA_CHANNEL 4
349 #define CONFIG_SYS_MAX_FLASH_BANKS 0x1
350 #define CONFIG_SYS_NAND_MAX_CHIPS 0x1
351 #define CONFIG_SYS_MAX_NAND_DEVICE 0x1
352 #define CONFIG_SYS_NAND_BASE 0x00000000
353 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
355 #define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
356 #define CONFIG_ENV_SIZE SZ_128K
357 #define CONFIG_ENV_RANGE (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
358 #endif /* CONFIG_TX6_NAND */
360 #ifdef CONFIG_ENV_OFFSET_REDUND
361 #define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_SYS_ENV_PART_SIZE) \
363 xstr(CONFIG_SYS_ENV_PART_SIZE) \
365 #define CONFIG_SYS_USERFS_PART_STR xstr(CONFIG_SYS_USERFS_PART_SIZE) "(userfs)"
367 #define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_SYS_ENV_PART_SIZE) \
369 #define CONFIG_SYS_USERFS_PART_STR xstr(CONFIG_SYS_USERFS_PART_SIZE2) "(userfs)"
370 #endif /* CONFIG_ENV_OFFSET_REDUND */
375 #ifdef CONFIG_FSL_ESDHC
376 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
378 #ifdef CONFIG_CMD_MMC
379 #define CONFIG_CMD_FAT
380 #define CONFIG_FAT_WRITE
381 #define CONFIG_CMD_EXT2
384 * Environments on MMC
386 #ifdef CONFIG_ENV_IS_IN_MMC
387 #define CONFIG_SYS_MMC_ENV_DEV 0
388 #define CONFIG_SYS_MMC_ENV_PART 0x1
389 #define CONFIG_DYNAMIC_MMC_DEVNO
390 #endif /* CONFIG_ENV_IS_IN_MMC */
391 #endif /* CONFIG_CMD_MMC */
393 #ifdef CONFIG_TX6_NAND
394 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
395 xstr(CONFIG_SYS_U_BOOT_PART_SIZE) \
396 "@" xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) \
398 CONFIG_SYS_ENV_PART_STR \
399 "6m(linux),32m(rootfs)," CONFIG_SYS_USERFS_PART_STR "," \
400 xstr(CONFIG_SYS_DTB_PART_SIZE) \
401 "@" xstr(CONFIG_SYS_NAND_DTB_OFFSET) "(dtb)," \
402 xstr(CONFIG_SYS_NAND_BBT_SIZE) \
403 "@" xstr(CONFIG_SYS_NAND_BBT_OFFSET) "(bbt)ro"
405 #define MTDPARTS_DEFAULT ""
408 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
409 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
410 GENERATED_GBL_DATA_SIZE)
412 #endif /* __CONFIG_H */