2 * Copyright (C) 2012-2015 <LW@KARO-electronics.de>
4 * SPDX-License-Identifier: GPL-2.0
11 #ifndef CONFIG_SOC_MX6UL
12 #define CONFIG_ARM_ERRATA_743622
13 #define CONFIG_ARM_ERRATA_751472
14 #define CONFIG_ARM_ERRATA_794072
15 #define CONFIG_ARM_ERRATA_761320
17 #ifndef CONFIG_SYS_L2CACHE_OFF
18 #define CONFIG_SYS_L2_PL310
19 #define CONFIG_SYS_PL310_BASE L2_PL310_BASE
22 #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
25 #define CONFIG_BOARD_POSTCLK_INIT
26 #define CONFIG_MXC_GPT_HCLK
28 #include <linux/kconfig.h>
29 #include <linux/sizes.h>
30 #include <asm/arch/imx-regs.h>
33 * Ka-Ro TX6 board - SoC configuration
35 #define CONFIG_SYS_MX6_HCLK 24000000
36 #define CONFIG_SYS_MX6_CLK32 32768
37 #define CONFIG_SYS_HZ 1000 /* Ticks per second */
38 #define CONFIG_SHOW_ACTIVITY
39 #define CONFIG_ARCH_CPU_INIT
40 #define CONFIG_DISPLAY_BOARDINFO
41 #define CONFIG_BOARD_LATE_INIT
42 #define CONFIG_BOARD_EARLY_INIT_F
43 #define CONFIG_SYS_GENERIC_BOARD
44 #define CONFIG_CMD_GPIO
46 /* LCD Logo and Splash screen support */
48 #define CONFIG_SPLASH_SCREEN
49 #define CONFIG_SPLASH_SCREEN_ALIGN
50 #ifndef CONFIG_SOC_MX6UL
51 #define CONFIG_VIDEO_IPUV3
52 #define CONFIG_IPUV3_CLK (CONFIG_SYS_SDRAM_CLK * 1000000 / 2)
54 #define CONFIG_VIDEO_MXS
55 #define MXS_LCDIF_BASE 0x021c8000UL
56 #endif /* CONFIG_SOC_MX6UL */
57 #define CONFIG_LCD_LOGO
58 #define LCD_BPP LCD_COLOR32
59 #define CONFIG_CMD_BMP
60 #define CONFIG_BMP_8BPP
61 #define CONFIG_BMP_16BPP
62 #define CONFIG_BMP_24BPP
63 #define CONFIG_BMP_32BPP
64 #define CONFIG_VIDEO_BMP_RLE8
65 #endif /* CONFIG_LCD */
68 * Memory configuration options
70 #define CONFIG_NR_DRAM_BANKS 0x1 /* # of SDRAM banks */
71 #ifndef CONFIG_SOC_MX6UL
72 #define PHYS_SDRAM_1 0x10000000 /* Base address of bank 1 */
73 #define CONFIG_SYS_MPU_CLK 792
75 #define PHYS_SDRAM_1 0x80000000 /* Base address of bank 1 */
76 #define CONFIG_SYS_MPU_CLK 528
78 #ifndef CONFIG_SYS_SDRAM_BUS_WIDTH
79 #if defined(CONFIG_SYS_SDRAM_BUS_WIDTH_32)
80 #define CONFIG_SYS_SDRAM_BUS_WIDTH 32
81 #elif defined(CONFIG_SYS_SDRAM_BUS_WIDTH_16)
82 #define CONFIG_SYS_SDRAM_BUS_WIDTH 16
84 #define CONFIG_SYS_SDRAM_BUS_WIDTH 64
86 #endif /* CONFIG_SYS_SDRAM_BUS_WIDTH */
90 #define _AC(x,s) (x##s)
92 #define UL(x) _AC(x,UL)
93 #define PHYS_SDRAM_1_SIZE (UL(CONFIG_SYS_SDRAM_CHIP_SIZE) * SZ_1M \
94 / 32 * CONFIG_SYS_SDRAM_BUS_WIDTH)
95 #if PHYS_SDRAM_1_SIZE > SZ_1G
96 #define FDT_HIGH_STR "fdt_high=ffffffff\0"
98 #define FDT_HIGH_STR ""
101 #ifdef CONFIG_SOC_MX6Q
102 #define CONFIG_SYS_SDRAM_CLK 528
104 #define CONFIG_SYS_SDRAM_CLK 400
106 #define CONFIG_STACKSIZE SZ_128K
107 #define CONFIG_SPL_STACK (IRAM_BASE_ADDR + SZ_16K)
108 #define CONFIG_SYS_MALLOC_LEN SZ_8M
109 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */
110 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_4M)
113 * U-Boot general configurations
115 #define CONFIG_SYS_LONGHELP
116 #if defined(CONFIG_SOC_MX6Q)
117 #elif defined(CONFIG_SOC_MX6DL)
118 #elif defined(CONFIG_SOC_MX6S)
119 #elif defined(CONFIG_SOC_MX6UL)
121 #error Unsupported i.MX6 processor variant
123 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
124 #define CONFIG_SYS_PBSIZE \
125 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
126 /* Print buffer size */
127 #define CONFIG_SYS_MAXARGS 256 /* Max number of command args */
128 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
129 /* Boot argument buffer size */
130 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
131 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
132 #define CONFIG_CMDLINE_EDITING /* Command history etc */
134 #define CONFIG_SYS_64BIT_VSPRINTF
139 #define xstr(s) str(s)
141 #define __pfx(x, s) (x##s)
142 #define _pfx(x, s) __pfx(x, s)
144 #define CONFIG_CMDLINE_TAG
145 #define CONFIG_INITRD_TAG
146 #define CONFIG_SETUP_MEMORY_TAGS
147 #ifndef CONFIG_TX6_UBOOT_MFG
148 #define CONFIG_BOOTDELAY 1
150 #define CONFIG_BOOTDELAY 0
152 #define CONFIG_ZERO_BOOTDELAY_CHECK
153 #define CONFIG_SYS_AUTOLOAD "no"
154 #define DEFAULT_BOOTCMD "run bootcmd_${boot_mode} bootm_cmd"
155 #define CONFIG_BOOTFILE "uImage"
156 #define CONFIG_BOOTARGS "init=/linuxrc console=ttymxc0,115200 ro debug panic=1"
157 #ifndef CONFIG_TX6_UBOOT_MFG
158 #define CONFIG_BOOTCOMMAND DEFAULT_BOOTCMD
160 #define CONFIG_BOOTCOMMAND "setenv bootcmd '" DEFAULT_BOOTCMD "';" \
161 "env import " xstr(CONFIG_BOOTCMD_MFG_LOADADDR) ";run bootcmd_mfg"
162 #if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6UL))
163 #define CONFIG_BOOTCMD_MFG_LOADADDR 80500000
165 #define CONFIG_BOOTCMD_MFG_LOADADDR 10500000
167 #define CONFIG_DELAY_ENVIRONMENT
168 #endif /* CONFIG_TX6_UBOOT_MFG */
169 #if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6UL))
170 #define CONFIG_LOADADDR 82000000
171 #define CONFIG_FDTADDR 81000000
173 #define CONFIG_LOADADDR 18000000
174 #define CONFIG_FDTADDR 11000000
176 #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
177 #define CONFIG_SYS_FDT_ADDR _pfx(0x, CONFIG_FDTADDR)
178 #ifndef CONFIG_SYS_LVDS_IF
179 #define DEFAULT_VIDEO_MODE "VGA"
181 #define DEFAULT_VIDEO_MODE "HSD100PXN1"
185 * Extra Environment Settings
187 #ifdef CONFIG_TX6_UBOOT_NOENV
188 #define CONFIG_EXTRA_ENV_SETTINGS \
191 "baseboard=stk5-v3\0" \
193 "fdtaddr=" xstr(CONFIG_FDTADDR) "\0" \
194 "mtdids=" MTDIDS_DEFAULT "\0" \
195 "mtdparts=" MTDPARTS_DEFAULT "\0"
197 #define CONFIG_SYS_CPU_CLK_STR xstr(CONFIG_SYS_MPU_CLK)
199 #define CONFIG_EXTRA_ENV_SETTINGS \
201 "baseboard=stk5-v3\0" \
202 "bootargs_jffs2=run default_bootargs" \
203 ";setenv bootargs ${bootargs}" \
204 " root=/dev/mtdblock3 rootfstype=jffs2\0" \
205 "bootargs_mmc=run default_bootargs;setenv bootargs ${bootargs}" \
207 "bootargs_nfs=run default_bootargs;setenv bootargs ${bootargs}" \
208 " root=/dev/nfs nfsroot=${nfs_server}:${nfsroot},nolock" \
210 "bootargs_ubifs=run default_bootargs" \
211 ";setenv bootargs ${bootargs}" \
212 " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0" \
213 "bootcmd_jffs2=setenv autostart no;run bootargs_jffs2" \
215 "bootcmd_mmc=setenv autostart no;run bootargs_mmc" \
216 ";fatload mmc 0 ${loadaddr} uImage\0" \
217 CONFIG_SYS_BOOT_CMD_NAND \
218 "bootcmd_net=setenv autoload y;setenv autostart n" \
219 ";run bootargs_nfs" \
221 "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \
222 "boot_mode=" CONFIG_SYS_DEFAULT_BOOT_MODE "\0" \
223 "cpu_clk=" CONFIG_SYS_CPU_CLK_STR "\0" \
224 "default_bootargs=setenv bootargs " CONFIG_BOOTARGS \
225 " ${append_bootargs}\0" \
228 "fdtaddr=" xstr(CONFIG_FDTADDR) "\0" \
231 "mtdids=" MTDIDS_DEFAULT "\0" \
232 "mtdparts=" MTDPARTS_DEFAULT "\0" \
233 "nfsroot=/tftpboot/rootfs\0" \
234 "otg_mode=device\0" \
236 "touchpanel=tsc2007\0" \
237 "video_mode=" DEFAULT_VIDEO_MODE "\0"
238 #endif /* CONFIG_ENV_IS_NOWHERE */
240 #ifdef CONFIG_TX6_NAND
241 #define CONFIG_SYS_DEFAULT_BOOT_MODE "nand"
242 #define CONFIG_SYS_BOOT_CMD_NAND \
243 "bootcmd_nand=setenv autostart no;run bootargs_ubifs;nboot linux\0"
244 #define FDTSAVE_CMD_STR \
245 "fdtsave=fdt resize;nand erase.part dtb" \
246 ";nand write ${fdtaddr} dtb ${fdtsize}\0"
247 #define MTD_NAME "gpmi-nand"
248 #define MTDIDS_DEFAULT "nand0=" MTD_NAME
249 #define CONFIG_SYS_NAND_ONFI_DETECTION
250 #define MMC_ROOT_STR " root=/dev/mmcblk0p2 rootwait\0"
251 #define ROOTPART_UUID_STR ""
252 #define EMMC_BOOT_ACK_STR ""
253 #define EMMC_BOOT_PART_STR ""
255 #define CONFIG_SYS_DEFAULT_BOOT_MODE "mmc"
256 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
257 #define CONFIG_SYS_BOOT_CMD_NAND ""
258 #define FDTSAVE_CMD_STR \
259 "fdtsave=mmc partconf 0 ${emmc_boot_ack} ${emmc_boot_part} ${emmc_boot_part}" \
260 ";mmc write ${fdtaddr} " xstr(CONFIG_SYS_DTB_BLKNO) " 80" \
261 ";mmc partconf 0 ${emmc_boot_ack} ${emmc_boot_part} 0\0"
263 #define MTDIDS_DEFAULT ""
264 #define MMC_ROOT_STR " root=PARTUUID=${rootpart_uuid} rootwait\0"
265 #define ROOTPART_UUID_STR "rootpart_uuid=0cc66cc0-02\0"
266 #define EMMC_BOOT_ACK_STR "emmc_boot_ack=1\0"
267 #define EMMC_BOOT_PART_STR "emmc_boot_part=" \
268 xstr(CONFIG_SYS_MMCSD_FS_BOOT_PARTITION) "\0"
269 #endif /* CONFIG_TX6_NAND */
274 #define CONFIG_MXC_UART
275 #define CONFIG_MXC_UART_BASE UART1_BASE
276 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
277 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
278 #define CONFIG_SYS_CONSOLE_INFO_QUIET
279 #define CONFIG_CONS_INDEX 1
284 #define CONFIG_MXC_GPIO
289 #ifdef CONFIG_FEC_MXC
290 /* This is required for the FEC driver to work with cache enabled */
291 #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
293 #ifndef CONFIG_SOC_MX6UL
294 #define CONFIG_FEC_MXC_PHYADDR 0
295 #define IMX_FEC_BASE ENET_BASE_ADDR
297 #define FEC_MDIO_BASE_ADDR ENET_BASE_ADDR
299 #define CONFIG_FEC_XCV_TYPE RMII
305 #ifdef CONFIG_HARD_I2C
306 #define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
307 #define CONFIG_SYS_I2C_SPEED 400000
308 #endif /* CONFIG_HARD_I2C */
309 #if defined(CONFIG_TX6_REV)
310 #if CONFIG_TX6_REV == 0x1
311 #define CONFIG_LTC3676
312 #elif CONFIG_TX6_REV == 0x3
313 #define CONFIG_RN5T567
315 #error Unsupported TX6 module revision
317 #else /* CONFIG_TX6_REV */
318 #ifdef CONFIG_SOC_MX6UL
319 #ifdef CONFIG_SYS_I2C_SOFT
320 /* NOENV U-Boot is used for initial bootstrap.
321 * Since the TAMPER_PIN_DISABLE fuses have to be programmed
322 * to be able to use the TAMPER pins as GPIO to access the
323 * PMIC I2C bus, this is not possible on virgin hardware.
325 #define CONFIG_SYS_I2C_SOFT_SPEED 400000
326 #define CONFIG_SYS_I2C_SPEED CONFIG_SYS_I2C_SOFT_SPEED
327 #define CONFIG_SOFT_I2C_GPIO_SCL IMX_GPIO_NR(5, 0)
328 #define CONFIG_SOFT_I2C_GPIO_SDA IMX_GPIO_NR(5, 1)
329 #define CONFIG_SOFT_I2C_READ_REPEATED_START
330 #endif /* CONFIG_SYS_I2C_SOFT */
331 #else /* !CONFIG_SOC_MX6UL */
332 /* autodetect which PMIC is present to derive TX6_REV */
333 #define CONFIG_LTC3676 /* TX6_REV == 1 */
334 #endif /* CONFIG_SOC_MX6UL */
335 #define CONFIG_RN5T567 /* TX6_REV == 3 */
336 #endif /* CONFIG_TX6_REV */
338 #define CONFIG_ENV_OVERWRITE
343 #ifdef CONFIG_TX6_NAND
344 #define CONFIG_SYS_MXS_DMA_CHANNEL 4
345 #define CONFIG_SYS_MAX_FLASH_BANKS 0x1
346 #define CONFIG_SYS_NAND_MAX_CHIPS 0x1
347 #define CONFIG_SYS_MAX_NAND_DEVICE 0x1
348 #define CONFIG_SYS_NAND_BASE 0x00000000
349 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
351 #define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
352 #define CONFIG_ENV_SIZE SZ_128K
353 #define CONFIG_ENV_RANGE (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
354 #endif /* CONFIG_TX6_NAND */
356 #ifdef CONFIG_ENV_OFFSET_REDUND
357 #define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_SYS_ENV_PART_SIZE) \
359 xstr(CONFIG_SYS_ENV_PART_SIZE) \
361 #define CONFIG_SYS_USERFS_PART_STR xstr(CONFIG_SYS_USERFS_PART_SIZE) "(userfs)"
363 #define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_SYS_ENV_PART_SIZE) \
365 #define CONFIG_SYS_USERFS_PART_STR xstr(CONFIG_SYS_USERFS_PART_SIZE2) "(userfs)"
366 #endif /* CONFIG_ENV_OFFSET_REDUND */
371 #ifdef CONFIG_FSL_ESDHC
372 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
374 #ifdef CONFIG_CMD_MMC
375 #define CONFIG_CMD_FAT
376 #define CONFIG_FAT_WRITE
377 #define CONFIG_CMD_EXT2
380 * Environments on MMC
382 #ifdef CONFIG_ENV_IS_IN_MMC
383 #define CONFIG_SYS_MMC_ENV_DEV 0
384 #define CONFIG_SYS_MMC_ENV_PART 0x1
385 #define CONFIG_DYNAMIC_MMC_DEVNO
386 #endif /* CONFIG_ENV_IS_IN_MMC */
387 #endif /* CONFIG_CMD_MMC */
389 #ifdef CONFIG_TX6_NAND
390 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
391 xstr(CONFIG_SYS_U_BOOT_PART_SIZE) \
392 "@" xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) \
394 CONFIG_SYS_ENV_PART_STR \
395 "6m(linux),32m(rootfs)," CONFIG_SYS_USERFS_PART_STR "," \
396 xstr(CONFIG_SYS_DTB_PART_SIZE) \
397 "@" xstr(CONFIG_SYS_NAND_DTB_OFFSET) "(dtb)," \
398 xstr(CONFIG_SYS_NAND_BBT_SIZE) \
399 "@" xstr(CONFIG_SYS_NAND_BBT_OFFSET) "(bbt)ro"
401 #define MTDPARTS_DEFAULT ""
404 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
405 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
406 GENERATED_GBL_DATA_SIZE)
408 #endif /* __CONFIG_H */