1 From 1fa19862acbd764533c0d3d6e09cca768e7a9d81 Mon Sep 17 00:00:00 2001
2 From: Terry Lv <r65388@freescale.com>
3 Date: Fri, 18 Sep 2009 14:02:11 +0800
4 Subject: [PATCH] ENGR00116504-2: Add mx51 bbg to3 support.
6 Add mx51 bbg to3 support.
8 Signed-off-by: Terry Lv <r65388@freescale.com>
10 board/freescale/mx51_bbg/lowlevel_init.S | 9 ++-
11 board/freescale/mx51_bbg/mx51_bbg.c | 90 ++++++++++++++++++++++++-----
12 2 files changed, 81 insertions(+), 18 deletions(-)
14 diff --git a/board/freescale/mx51_bbg/lowlevel_init.S b/board/freescale/mx51_bbg/lowlevel_init.S
15 index b8abae4..b937067 100644
16 --- a/board/freescale/mx51_bbg/lowlevel_init.S
17 +++ b/board/freescale/mx51_bbg/lowlevel_init.S
19 orr r0, r0, #(1 << 22) /* disable write allocate */
21 cmp r3, #0x10 /* r3 contains the silicon rev */
22 - orrls r0, r0, #(1 << 25) /* ENGcm09124: disable write combine for TO 2 and lower revs */
23 + orrls r0, r0, #(1 << 25) /* disable write combine for TO 2 and lower revs */
25 mcr 15, 1, r0, c9, c0, 2
30 ldr r0, =CCM_BASE_ADDR
32 + /* Run TO 3.0 at Full speed, for other TO's wait till we increase VDDGP */
34 + ldr r3, [r1, #ROM_SI_REV]
38 str r1, [r0, #CLKCTL_CACRR]
40 /* Switch ARM back to PLL 1 */
41 diff --git a/board/freescale/mx51_bbg/mx51_bbg.c b/board/freescale/mx51_bbg/mx51_bbg.c
42 index 9e1bb1a..8ea4e2e 100644
43 --- a/board/freescale/mx51_bbg/mx51_bbg.c
44 +++ b/board/freescale/mx51_bbg/mx51_bbg.c
45 @@ -64,6 +64,9 @@ static inline void setup_soc_rev(void)
46 system_rev = 0x51000 | CHIP_REV_2_0;
50 + system_rev = 0x51000 | CHIP_REV_3_0;
53 system_rev = 0x51000 | CHIP_REV_1_0;
55 @@ -98,6 +101,9 @@ static void setup_uart(void)
56 mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
57 mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
58 mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
59 + /* enable GPIO1_9 for CLK0 and GPIO1_8 for CLK02 */
60 + writel(0x00000004, 0x73fa83e8);
61 + writel(0x00000004, 0x73fa83ec);
65 @@ -302,27 +308,79 @@ static void power_init(void)
69 +#define REV_ATLAS_LITE_1_0 0x8
70 +#define REV_ATLAS_LITE_1_1 0x9
71 +#define REV_ATLAS_LITE_2_0 0x10
72 +#define REV_ATLAS_LITE_2_1 0x11
74 slave = spi_pmic_probe();
76 + /* Write needed to Power Gate 2 register */
77 + val = pmic_reg(slave, 34, 0, 0);
79 + pmic_reg(slave, 34, val, 1);
81 + /* Write needed to update Charger 0 */
82 + pmic_reg(slave, 48, 0x0023807F, 1);
84 /* power up the system first */
85 pmic_reg(slave, 34, 0x00200000, 1);
87 - if (mxc_get_clock(MXC_FEC_CLK) > 800000000) {
88 - /* Set core voltage to 1.175V */
89 + if (is_soc_rev(CHIP_REV_2_0) >= 0) {
90 + /* Set core voltage to 1.1V */
91 val = pmic_reg(slave, 24, 0, 0);
92 - val = (val & (~0x1F)) | 0x17;
93 + val = (val & (~0x1F)) | 0x14;
94 pmic_reg(slave, 24, val, 1);
97 - /* Setup VCC (SW2) to 1.225 */
98 - val = pmic_reg(slave, 25, 0, 0);
99 - val = (val & (~0x1F)) | 0x19;
100 - pmic_reg(slave, 25, val, 1);
101 + /* Setup VCC (SW2) to 1.25 */
102 + val = pmic_reg(slave, 25, 0, 0);
103 + val = (val & (~0x1F)) | 0x1A;
104 + pmic_reg(slave, 25, val, 1);
106 + /* Setup 1V2_DIG1 (SW3) to 1.25 */
107 + val = pmic_reg(slave, 26, 0, 0);
108 + val = (val & (~0x1F)) | 0x1A;
109 + pmic_reg(slave, 26, val, 1);
111 + /* Raise the core frequency to 800MHz */
112 + writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
115 + /* Setup VCC (SW2) to 1.225 */
116 + val = pmic_reg(slave, 25, 0, 0);
117 + val = (val & (~0x1F)) | 0x19;
118 + pmic_reg(slave, 25, val, 1);
120 + /* Setup 1V2_DIG1 (SW3) to 1.2 */
121 + val = pmic_reg(slave, 26, 0, 0);
122 + val = (val & (~0x1F)) | 0x18;
123 + pmic_reg(slave, 26, val, 1);
126 - /* Setup 1V2_DIG1 (SW3) to 1.2 */
127 - val = pmic_reg(slave, 26, 0, 0);
128 - val = (val & (~0x1F)) | 0x18;
129 - pmic_reg(slave, 25, val, 1);
130 + if (((pmic_reg(slave, 7, 0, 0) & 0x1F) < REV_ATLAS_LITE_2_0) ||
131 + (((pmic_reg(slave, 7, 0, 0) >> 9) & 0x3) == 0)) {
132 + /* Set switchers in PWM mode for Atlas 2.0 and lower */
133 + /* Setup the switcher mode for SW1 & SW2*/
134 + val = pmic_reg(slave, 28, 0, 0);
135 + val = (val & (~0x3C0F)) | 0x1405;
136 + pmic_reg(slave, 28, val, 1);
138 + /* Setup the switcher mode for SW3 & SW4 */
139 + val = pmic_reg(slave, 29, 0, 0);
140 + val = (val & (~0xF0F)) | 0x505;
141 + pmic_reg(slave, 29, val, 1);
143 + /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */
144 + /* Setup the switcher mode for SW1 & SW2*/
145 + val = pmic_reg(slave, 28, 0, 0);
146 + val = (val & (~0x3C0F)) | 0x2008;
147 + pmic_reg(slave, 28, val, 1);
149 + /* Setup the switcher mode for SW3 & SW4 */
150 + val = pmic_reg(slave, 29, 0, 0);
151 + val = (val & (~0xF0F)) | 0x808;
152 + pmic_reg(slave, 29, val, 1);
155 /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */
156 val = pmic_reg(slave, 30, 0, 0);
157 @@ -362,9 +420,6 @@ static void power_init(void)
159 writel(reg, GPIO2_BASE_ADDR + 0x0);
161 - /* Setup the FEC after enabling the regulators */
164 spi_pmic_free(slave);
167 @@ -497,6 +552,7 @@ int board_init(void)
175 @@ -650,7 +706,9 @@ int checkboard(void)
177 printf("Board: MX51 BABBAGE ");
179 - if (system_rev & CHIP_REV_2_5) {
180 + if (system_rev & CHIP_REV_3_0) {
182 + } else if (system_rev & CHIP_REV_2_5) {
184 } else if (system_rev & CHIP_REV_2_0) {