1 From a012066c0996d8b79b815470aded18e266733e2b Mon Sep 17 00:00:00 2001
2 From: Jason <r64343@freescale.com>
3 Date: Mon, 30 Nov 2009 17:35:50 +0800
4 Subject: [PATCH] ENGR00118789 Uboot:Update NAND scan scheme to support new nand type
6 Update NAND scan scheme to support new nand type. With this
7 patch uboot can support new NAND flash on mx25/mx35 board
8 while compatible with old NAND on old boards.
10 Signed-off-by: Jason Liu <r64343@freescale.com>
12 drivers/mtd/nand/Makefile | 2 +-
13 drivers/mtd/nand/mxc_nand.c | 49 +-
14 drivers/mtd/nand/nand_device_info.c | 2296 ++++++++++++++++++++++++++++++++++
15 drivers/mtd/nand/nand_device_info.h | 144 +++
16 drivers/mtd/nand/nand_ids.c | 6 +
17 include/asm-arm/arch-mx25/mxc_nand.h | 14 +-
18 include/asm-arm/arch-mx35/mxc_nand.h | 15 +-
19 include/configs/mx35_3stack.h | 4 +-
20 include/linux/mtd/nand.h | 2 +
21 9 files changed, 2518 insertions(+), 14 deletions(-)
23 diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
24 index ecf2803..6fefe00 100644
25 --- a/drivers/mtd/nand/Makefile
26 +++ b/drivers/mtd/nand/Makefile
27 @@ -48,7 +48,7 @@ COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
28 COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
29 COBJS-$(CONFIG_MX25) += mxc_nand.o
30 COBJS-$(CONFIG_MX31_NAND) += mx31_nand.o
31 -COBJS-$(CONFIG_MXC_NAND) += mxc_nand.o
32 +COBJS-$(CONFIG_MXC_NAND) += mxc_nand.o nand_device_info.o
36 diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
37 index 71d2d9e..5961b4c 100644
38 --- a/drivers/mtd/nand/mxc_nand.c
39 +++ b/drivers/mtd/nand/mxc_nand.c
41 #include <asm/errno.h>
42 #include <linux/mtd/nand.h>
43 #include <asm-arm/arch/mxc_nand.h>
44 +#include "nand_device_info.h"
48 @@ -1059,7 +1060,7 @@ static int mxc_nand_prog_page(struct mtd_info *mtd, struct nand_chip *chip,
55 /* Define some generic bad / good block scan pattern which are used
56 * while scanning a device for factory marked good / bad blocks. */
57 @@ -1106,22 +1107,64 @@ static struct nand_bbt_descr bbt_mirror_descr = {
59 static int mxc_nand_scan_bbt(struct mtd_info *mtd)
62 + uint8_t id_bytes[NAND_DEVICE_ID_BYTE_COUNT];
63 struct nand_chip *this = mtd->priv;
64 struct nand_info *info = this->priv;
65 + struct nand_device_info *dev_info;
67 info->page_mask = this->pagemask;
69 + if (!IS_LARGE_PAGE_NAND)
72 + /* Read ID bytes from the first NAND Flash chip. */
73 + this->select_chip(mtd, 0);
75 + this->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
77 + for (i = 0; i < NAND_DEVICE_ID_BYTE_COUNT; i++)
78 + id_bytes[i] = this->read_byte(mtd);
80 + /* Get information about this device, based on the ID bytes. */
81 + dev_info = nand_device_get_info(id_bytes);
83 + /* Check if we understand this device. */
85 + printk(KERN_ERR "Unrecognized NAND Flash device.\n");
89 + nand_device_print_info(dev_info);
91 + /* Correct mtd setting */
92 + this->chipsize = dev_info->chip_size_in_bytes;
93 + mtd->size = dev_info->chip_size_in_bytes * this->numchips;
94 + mtd->writesize = dev_info->page_total_size_in_bytes & ~0x3ff;
95 + mtd->oobsize = dev_info->page_total_size_in_bytes & 0x3ff;;
96 + mtd->erasesize = dev_info->block_size_in_pages * mtd->writesize;
98 /* limit to 2G size due to Kernel
99 * larger 4G space support,need fix
102 - if (mtd->size == 0) {
103 - mtd->size = 1 << 31;
104 + if ((u32)mtd->size == 0) {
105 + mtd->size = (u32)(1 << 31);
107 this->chipsize = mtd->size;
110 + /* Calculate the address shift from the page size */
111 + this->page_shift = ffs(mtd->writesize) - 1;
112 + /* Convert chipsize to number of pages per chip -1. */
113 + this->pagemask = (this->chipsize >> this->page_shift) - 1;
115 + this->bbt_erase_shift = this->phys_erase_shift =
116 + ffs(mtd->erasesize) - 1;
117 + this->chip_shift = ffs(this->chipsize) - 1;
118 + this->oob_poi = this->buffers->databuf + mtd->writesize;
121 if (IS_2K_PAGE_NAND) {
122 NFC_SET_NFMS(1 << NFMS_NF_PG_SZ);
123 this->ecc.layout = &nand_hw_eccoob_2k;
124 diff --git a/drivers/mtd/nand/nand_device_info.c b/drivers/mtd/nand/nand_device_info.c
126 index 0000000..2f3bbb6
128 +++ b/drivers/mtd/nand/nand_device_info.c
131 + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
135 + * The code contained herein is licensed under the GNU General Public
136 + * License. You may obtain a copy of the GNU General Public License
137 + * Version 2 or later at the following locations:
139 + * http://www.opensource.org/licenses/gpl-license.html
140 + * http://www.gnu.org/copyleft/gpl.html
143 +#include <asm/sizes.h>
144 +#include <linux/mtd/nand.h>
146 +#include "nand_device_info.h"
151 +static struct nand_device_info nand_device_info_table_type_2[] =
154 + .end_of_table = false,
155 + .manufacturer_code = 0x20,
156 + .device_code = 0xf1,
157 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
158 + .chip_size_in_bytes = 128LL*SZ_1M,
159 + .block_size_in_pages = 64,
160 + .page_total_size_in_bytes = 2*SZ_1K + 64,
161 + .ecc_strength_in_bits = 4,
162 + .ecc_size_in_bytes = 512,
163 + .data_setup_in_ns = 30,
164 + .data_hold_in_ns = 20,
165 + .address_setup_in_ns = 25,
166 + .gpmi_sample_delay_in_ns = 6,
173 + .end_of_table = false,
174 + .manufacturer_code = 0xad,
175 + .device_code = 0xf1,
176 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
177 + .chip_size_in_bytes = 128LL*SZ_1M,
178 + .block_size_in_pages = 64,
179 + .page_total_size_in_bytes = 2*SZ_1K + 64,
180 + .ecc_strength_in_bits = 4,
181 + .ecc_size_in_bytes = 512,
182 + .data_setup_in_ns = 45,
183 + .data_hold_in_ns = 30,
184 + .address_setup_in_ns = 25,
185 + .gpmi_sample_delay_in_ns = 6,
192 + .end_of_table = false,
193 + .manufacturer_code = 0x2c,
194 + .device_code = 0xf1,
195 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
196 + .chip_size_in_bytes = 128LL*SZ_1M,
197 + .block_size_in_pages = 64,
198 + .page_total_size_in_bytes = 2*SZ_1K + 64,
199 + .ecc_strength_in_bits = 4,
200 + .ecc_size_in_bytes = 512,
201 + .data_setup_in_ns = 30,
202 + .data_hold_in_ns = 20,
203 + .address_setup_in_ns = 10,
204 + .gpmi_sample_delay_in_ns = 6,
211 + .end_of_table = false,
212 + .manufacturer_code = 0xec,
213 + .device_code = 0xf1,
214 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
215 + .chip_size_in_bytes = 128LL*SZ_1M,
216 + .block_size_in_pages = 64,
217 + .page_total_size_in_bytes = 2*SZ_1K + 64,
218 + .ecc_strength_in_bits = 4,
219 + .ecc_size_in_bytes = 512,
220 + .data_setup_in_ns = 35,
221 + .data_hold_in_ns = 25,
222 + .address_setup_in_ns = 0,
223 + .gpmi_sample_delay_in_ns = 6,
230 + .end_of_table = false,
231 + .manufacturer_code = 0x98,
232 + .device_code = 0xf1,
233 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
234 + .chip_size_in_bytes = 128LL*SZ_1M,
235 + .block_size_in_pages = 64,
236 + .page_total_size_in_bytes = 2*SZ_1K + 64,
237 + .ecc_strength_in_bits = 4,
238 + .ecc_size_in_bytes = 512,
239 + .data_setup_in_ns = 30,
240 + .data_hold_in_ns = 20,
241 + .address_setup_in_ns = 0,
242 + .gpmi_sample_delay_in_ns = 6,
249 + .end_of_table = false,
250 + .manufacturer_code = 0x45,
251 + .device_code = 0xf1,
252 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
253 + .chip_size_in_bytes = 128LL*SZ_1M,
254 + .block_size_in_pages = 64,
255 + .page_total_size_in_bytes = 2*SZ_1K + 64,
256 + .ecc_strength_in_bits = 4,
257 + .ecc_size_in_bytes = 512,
258 + .data_setup_in_ns = 45,
259 + .data_hold_in_ns = 32,
260 + .address_setup_in_ns = 0,
261 + .gpmi_sample_delay_in_ns = 6,
268 + .end_of_table = false,
269 + .manufacturer_code = 0x20,
270 + .device_code = 0xda,
271 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
272 + .chip_size_in_bytes = 256LL*SZ_1M,
273 + .block_size_in_pages = 64,
274 + .page_total_size_in_bytes = 2*SZ_1K + 64,
275 + .ecc_strength_in_bits = 4,
276 + .ecc_size_in_bytes = 512,
277 + .data_setup_in_ns = 20,
278 + .data_hold_in_ns = 30,
279 + .address_setup_in_ns = 0,
280 + .gpmi_sample_delay_in_ns = 6,
287 + .end_of_table = false,
288 + .manufacturer_code = 0xad,
289 + .device_code = 0xda,
290 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
291 + .chip_size_in_bytes = 256LL*SZ_1M,
292 + .block_size_in_pages = 64,
293 + .page_total_size_in_bytes = 2*SZ_1K + 64,
294 + .ecc_strength_in_bits = 4,
295 + .ecc_size_in_bytes = 512,
296 + .data_setup_in_ns = 30,
297 + .data_hold_in_ns = 25,
298 + .address_setup_in_ns = 10,
299 + .gpmi_sample_delay_in_ns = 6,
303 + "HY27UF082G2M, HY27UG082G2M, HY27UG082G1M",
306 + .end_of_table = false,
307 + .manufacturer_code = 0x2c,
308 + .device_code = 0xda,
309 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
310 + .chip_size_in_bytes = 256LL*SZ_1M,
311 + .block_size_in_pages = 64,
312 + .page_total_size_in_bytes = 2*SZ_1K + 64,
313 + .ecc_strength_in_bits = 4,
314 + .ecc_size_in_bytes = 512,
315 + .data_setup_in_ns = 20,
316 + .data_hold_in_ns = 10,
317 + .address_setup_in_ns = 10,
318 + .gpmi_sample_delay_in_ns = 6,
325 + .end_of_table = false,
326 + .manufacturer_code = 0xec,
327 + .device_code = 0xda,
328 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
329 + .chip_size_in_bytes = 256LL*SZ_1M,
330 + .block_size_in_pages = 64,
331 + .page_total_size_in_bytes = 2*SZ_1K + 64,
332 + .ecc_strength_in_bits = 4,
333 + .ecc_size_in_bytes = 512,
334 + .data_setup_in_ns = 20,
335 + .data_hold_in_ns = 10,
336 + .address_setup_in_ns = 20,
337 + .gpmi_sample_delay_in_ns = 6,
344 + .end_of_table = false,
345 + .manufacturer_code = 0x98,
346 + .device_code = 0xda,
347 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
348 + .chip_size_in_bytes = 256LL*SZ_1M,
349 + .block_size_in_pages = 64,
350 + .page_total_size_in_bytes = 2*SZ_1K + 64,
351 + .ecc_strength_in_bits = 4,
352 + .ecc_size_in_bytes = 512,
353 + .data_setup_in_ns = 20,
354 + .data_hold_in_ns = 30,
355 + .address_setup_in_ns = 0,
356 + .gpmi_sample_delay_in_ns = 6,
363 + .end_of_table = false,
364 + .manufacturer_code = 0x45,
365 + .device_code = 0xda,
366 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
367 + .chip_size_in_bytes = 256LL*SZ_1M,
368 + .block_size_in_pages = 64,
369 + .page_total_size_in_bytes = 2*SZ_1K + 64,
370 + .ecc_strength_in_bits = 4,
371 + .ecc_size_in_bytes = 512,
372 + .data_setup_in_ns = 45,
373 + .data_hold_in_ns = 32,
374 + .address_setup_in_ns = 0,
375 + .gpmi_sample_delay_in_ns = 6,
382 + .end_of_table = false,
383 + .manufacturer_code = 0x20,
384 + .device_code = 0xdc,
385 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
386 + .chip_size_in_bytes = 512LL*SZ_1M,
387 + .block_size_in_pages = 64,
388 + .page_total_size_in_bytes = 2*SZ_1K + 64,
389 + .ecc_strength_in_bits = 4,
390 + .ecc_size_in_bytes = 512,
391 + .data_setup_in_ns = 45,
392 + .data_hold_in_ns = 30,
393 + .address_setup_in_ns = 10,
394 + .gpmi_sample_delay_in_ns = 6,
401 + .end_of_table = false,
402 + .manufacturer_code = 0xad,
403 + .device_code = 0xdc,
404 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
405 + .chip_size_in_bytes = 512LL*SZ_1M,
406 + .block_size_in_pages = 64,
407 + .page_total_size_in_bytes = 2*SZ_1K + 64,
408 + .ecc_strength_in_bits = 4,
409 + .ecc_size_in_bytes = 512,
410 + .data_setup_in_ns = 45,
411 + .data_hold_in_ns = 30,
412 + .address_setup_in_ns = 10,
413 + .gpmi_sample_delay_in_ns = 10,
417 + "HY27UH084G2M, HY27UG084G2M, HY27UH084G1M",
420 + .end_of_table = false,
421 + .manufacturer_code = 0x2c,
422 + .device_code = 0xdc,
423 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
424 + .chip_size_in_bytes = 512LL*SZ_1M,
425 + .block_size_in_pages = 64,
426 + .page_total_size_in_bytes = 2*SZ_1K + 64,
427 + .ecc_strength_in_bits = 4,
428 + .ecc_size_in_bytes = 512,
429 + .data_setup_in_ns = 20,
430 + .data_hold_in_ns = 10,
431 + .address_setup_in_ns = 10,
432 + .gpmi_sample_delay_in_ns = 6,
439 + .end_of_table = false,
440 + .manufacturer_code = 0xec,
441 + .device_code = 0xdc,
442 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
443 + .chip_size_in_bytes = 512LL*SZ_1M,
444 + .block_size_in_pages = 64,
445 + .page_total_size_in_bytes = 2*SZ_1K + 64,
446 + .ecc_strength_in_bits = 4,
447 + .ecc_size_in_bytes = 512,
448 + .data_setup_in_ns = 25,
449 + .data_hold_in_ns = 25,
450 + .address_setup_in_ns = 20,
451 + .gpmi_sample_delay_in_ns = 6,
458 + .end_of_table = false,
459 + .manufacturer_code = 0x98,
460 + .device_code = 0xdc,
461 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
462 + .chip_size_in_bytes = 512LL*SZ_1M,
463 + .block_size_in_pages = 64,
464 + .page_total_size_in_bytes = 2*SZ_1K + 64,
465 + .ecc_strength_in_bits = 4,
466 + .ecc_size_in_bytes = 512,
467 + .data_setup_in_ns = 25,
468 + .data_hold_in_ns = 25,
469 + .address_setup_in_ns = 0,
470 + .gpmi_sample_delay_in_ns = 6,
477 + .end_of_table = false,
478 + .manufacturer_code = 0x45,
479 + .device_code = 0xdc,
480 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
481 + .chip_size_in_bytes = 512LL*SZ_1M,
482 + .block_size_in_pages = 64,
483 + .page_total_size_in_bytes = 2*SZ_1K + 64,
484 + .ecc_strength_in_bits = 4,
485 + .ecc_size_in_bytes = 512,
486 + .data_setup_in_ns = 45,
487 + .data_hold_in_ns = 32,
488 + .address_setup_in_ns = 0,
489 + .gpmi_sample_delay_in_ns = 6,
496 + .end_of_table = false,
497 + .manufacturer_code = 0xad,
498 + .device_code = 0xd3,
499 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
500 + .chip_size_in_bytes = 1LL*SZ_1G,
501 + .block_size_in_pages = 64,
502 + .page_total_size_in_bytes = 2*SZ_1K + 64,
503 + .ecc_strength_in_bits = 4,
504 + .ecc_size_in_bytes = 512,
505 + .data_setup_in_ns = 30,
506 + .data_hold_in_ns = 25,
507 + .address_setup_in_ns = 20,
508 + .gpmi_sample_delay_in_ns = 6,
515 + .end_of_table = false,
516 + .manufacturer_code = 0x20,
517 + .device_code = 0xd3,
518 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
519 + .chip_size_in_bytes = 1LL*SZ_1G,
520 + .block_size_in_pages = 64,
521 + .page_total_size_in_bytes = 2*SZ_1K + 64,
522 + .ecc_strength_in_bits = 4,
523 + .ecc_size_in_bytes = 512,
524 + .data_setup_in_ns = 45,
525 + .data_hold_in_ns = 30,
526 + .address_setup_in_ns = 10,
527 + .gpmi_sample_delay_in_ns = 6,
534 + .end_of_table = false,
535 + .manufacturer_code = 0x2c,
536 + .device_code = 0xd3,
537 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
538 + .chip_size_in_bytes = 1LL*SZ_1G,
539 + .block_size_in_pages = 64,
540 + .page_total_size_in_bytes = 2*SZ_1K + 64,
541 + .ecc_strength_in_bits = 4,
542 + .ecc_size_in_bytes = 512,
543 + .data_setup_in_ns = 25,
544 + .data_hold_in_ns = 15,
545 + .address_setup_in_ns = 10,
546 + .gpmi_sample_delay_in_ns = 6,
553 + .end_of_table = false,
554 + .manufacturer_code = 0x98,
555 + .device_code = 0xd3,
556 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
557 + .chip_size_in_bytes = 1LL*SZ_1G,
558 + .block_size_in_pages = 64,
559 + .page_total_size_in_bytes = 2*SZ_1K + 64,
560 + .ecc_strength_in_bits = 4,
561 + .ecc_size_in_bytes = 512,
562 + .data_setup_in_ns = 45,
563 + .data_hold_in_ns = 32,
564 + .address_setup_in_ns = 0,
565 + .gpmi_sample_delay_in_ns = 6,
572 + .end_of_table = false,
573 + .manufacturer_code = 0x20,
574 + .device_code = 0xd5,
575 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
576 + .chip_size_in_bytes = 2LL*SZ_1G,
577 + .block_size_in_pages = 64,
578 + .page_total_size_in_bytes = 2*SZ_1K + 64,
579 + .ecc_strength_in_bits = 4,
580 + .ecc_size_in_bytes = 512,
581 + .data_setup_in_ns = 45,
582 + .data_hold_in_ns = 30,
583 + .address_setup_in_ns = 10,
584 + .gpmi_sample_delay_in_ns = 6,
591 + .end_of_table = false,
592 + .manufacturer_code = 0xad,
593 + .device_code = 0xd5,
594 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
595 + .chip_size_in_bytes = 2LL*SZ_1G,
596 + .block_size_in_pages = 64,
597 + .page_total_size_in_bytes = 2*SZ_1K + 64,
598 + .ecc_strength_in_bits = 4,
599 + .ecc_size_in_bytes = 512,
600 + .data_setup_in_ns = 25,
601 + .data_hold_in_ns = 30,
602 + .address_setup_in_ns = 10,
603 + .gpmi_sample_delay_in_ns = 6,
610 + .end_of_table = false,
611 + .manufacturer_code = 0x2c,
612 + .device_code = 0xd5,
613 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
614 + .chip_size_in_bytes = 2LL*SZ_1G,
615 + .block_size_in_pages = 64,
616 + .page_total_size_in_bytes = 2*SZ_1K + 64,
617 + .ecc_strength_in_bits = 4,
618 + .ecc_size_in_bytes = 512,
619 + .data_setup_in_ns = 45,
620 + .data_hold_in_ns = 32,
621 + .address_setup_in_ns = 0,
622 + .gpmi_sample_delay_in_ns = 6,
634 +static struct nand_device_info nand_device_info_table_large_mlc[] =
637 + .end_of_table = false,
638 + .manufacturer_code = 0x98,
639 + .device_code = 0xda,
640 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
641 + .chip_size_in_bytes = 256LL*SZ_1M,
642 + .block_size_in_pages = 128,
643 + .page_total_size_in_bytes = 2*SZ_1K + 64,
644 + .ecc_strength_in_bits = 4,
645 + .ecc_size_in_bytes = 512,
646 + .data_setup_in_ns = 20,
647 + .data_hold_in_ns = 30,
648 + .address_setup_in_ns = 0,
649 + .gpmi_sample_delay_in_ns = 6,
656 + .end_of_table = false,
657 + .manufacturer_code = 0x45,
658 + .device_code = 0xda,
659 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
660 + .chip_size_in_bytes = 256LL*SZ_1M,
661 + .block_size_in_pages = 128,
662 + .page_total_size_in_bytes = 2*SZ_1K + 64,
663 + .ecc_strength_in_bits = 4,
664 + .ecc_size_in_bytes = 512,
665 + .data_setup_in_ns = 20,
666 + .data_hold_in_ns = 30,
667 + .address_setup_in_ns = 0,
668 + .gpmi_sample_delay_in_ns = 6,
675 + .end_of_table = false,
676 + .manufacturer_code = 0x45,
677 + .device_code = 0xdc,
678 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
679 + .chip_size_in_bytes = 512LL*SZ_1M,
680 + .block_size_in_pages = 128,
681 + .page_total_size_in_bytes = 2*SZ_1K + 64,
682 + .ecc_strength_in_bits = 4,
683 + .ecc_size_in_bytes = 512,
684 + .data_setup_in_ns = 20,
685 + .data_hold_in_ns = 30,
686 + .address_setup_in_ns = 0,
687 + .gpmi_sample_delay_in_ns = 6,
694 + .end_of_table = false,
695 + .manufacturer_code = 0x98,
696 + .device_code = 0xd3,
697 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
698 + .chip_size_in_bytes = 1LL*SZ_1G,
699 + .block_size_in_pages = 128,
700 + .page_total_size_in_bytes = 2*SZ_1K + 64,
701 + .ecc_strength_in_bits = 4,
702 + .ecc_size_in_bytes = 512,
703 + .data_setup_in_ns = 35,
704 + .data_hold_in_ns = 30,
705 + .address_setup_in_ns = 0,
706 + .gpmi_sample_delay_in_ns = 6,
713 + .end_of_table = false,
714 + .manufacturer_code = 0x45,
715 + .device_code = 0xd3,
716 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
717 + .chip_size_in_bytes = 1LL*SZ_1G,
718 + .block_size_in_pages = 128,
719 + .page_total_size_in_bytes = 2*SZ_1K + 64,
720 + .ecc_strength_in_bits = 4,
721 + .ecc_size_in_bytes = 512,
722 + .data_setup_in_ns = 35,
723 + .data_hold_in_ns = 20,
724 + .address_setup_in_ns = 0,
725 + .gpmi_sample_delay_in_ns = 6,
732 + .end_of_table = false,
733 + .manufacturer_code = 0x98,
734 + .device_code = 0xd5,
735 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
736 + .chip_size_in_bytes = 2LL*SZ_1G,
737 + .block_size_in_pages = 128,
738 + .page_total_size_in_bytes = 2*SZ_1K + 64,
739 + .ecc_strength_in_bits = 4,
740 + .ecc_size_in_bytes = 512,
741 + .data_setup_in_ns = 35,
742 + .data_hold_in_ns = 15,
743 + .address_setup_in_ns = 0,
744 + .gpmi_sample_delay_in_ns = 6,
751 + .end_of_table = false,
752 + .manufacturer_code = 0x45,
753 + .device_code = 0xd5,
754 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
755 + .chip_size_in_bytes = 2LL*SZ_1G,
756 + .block_size_in_pages = 128,
757 + .page_total_size_in_bytes = 2*SZ_1K + 64,
758 + .ecc_strength_in_bits = 4,
759 + .ecc_size_in_bytes = 512,
760 + .data_setup_in_ns = 35,
761 + .data_hold_in_ns = 15,
762 + .address_setup_in_ns = 0,
763 + .gpmi_sample_delay_in_ns = 6,
770 + .end_of_table = false,
771 + .manufacturer_code = 0x98,
772 + .device_code = 0xdc,
773 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
774 + .chip_size_in_bytes = 512LL*SZ_1M,
775 + .block_size_in_pages = 128,
776 + .page_total_size_in_bytes = 2*SZ_1K + 64,
777 + .ecc_strength_in_bits = 4,
778 + .ecc_size_in_bytes = 512,
779 + .data_setup_in_ns = 20,
780 + .data_hold_in_ns = 30,
781 + .address_setup_in_ns = 0,
782 + .gpmi_sample_delay_in_ns = 6,
789 + .end_of_table = false,
790 + .manufacturer_code = 0xec,
791 + .device_code = 0xdc,
792 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
793 + .chip_size_in_bytes = 512LL*SZ_1M,
794 + .block_size_in_pages = 128,
795 + .page_total_size_in_bytes = 2*SZ_1K + 64,
796 + .ecc_strength_in_bits = 4,
797 + .ecc_size_in_bytes = 512,
798 + .data_setup_in_ns = 25,
799 + .data_hold_in_ns = 15,
800 + .address_setup_in_ns = 25,
801 + .gpmi_sample_delay_in_ns = 6,
808 + .end_of_table = false,
809 + .manufacturer_code = 0xad,
810 + .device_code = 0xdc,
811 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
812 + .chip_size_in_bytes = 512LL*SZ_1M,
813 + .block_size_in_pages = 128,
814 + .page_total_size_in_bytes = 2*SZ_1K + 64,
815 + .ecc_strength_in_bits = 4,
816 + .ecc_size_in_bytes = 512,
817 + .data_setup_in_ns = 45,
818 + .data_hold_in_ns = 25,
819 + .address_setup_in_ns = 50,
820 + .gpmi_sample_delay_in_ns = 6,
824 + "HY27UT084G2M, HY27UU088G5M",
827 + .end_of_table = false,
828 + .manufacturer_code = 0x20,
829 + .device_code = 0xdc,
830 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
831 + .chip_size_in_bytes = 512LL*SZ_1M,
832 + .block_size_in_pages = 128,
833 + .page_total_size_in_bytes = 2*SZ_1K + 64,
834 + .ecc_strength_in_bits = 4,
835 + .ecc_size_in_bytes = 512,
836 + .data_setup_in_ns = 40,
837 + .data_hold_in_ns = 20,
838 + .address_setup_in_ns = 30,
839 + .gpmi_sample_delay_in_ns = 6,
846 + .end_of_table = false,
847 + .manufacturer_code = 0xec,
848 + .device_code = 0xd3,
849 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
850 + .chip_size_in_bytes = 1LL*SZ_1G,
851 + .block_size_in_pages = 128,
852 + .page_total_size_in_bytes = 2*SZ_1K + 64,
853 + .ecc_strength_in_bits = 4,
854 + .ecc_size_in_bytes = 512,
855 + .data_setup_in_ns = 20,
856 + .data_hold_in_ns = 15,
857 + .address_setup_in_ns = 20,
858 + .gpmi_sample_delay_in_ns = 6,
862 + "K9G8G08U0M, K9HAG08U1M",
865 + .end_of_table = false,
866 + .manufacturer_code = 0xad,
867 + .device_code = 0xd3,
868 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
869 + .chip_size_in_bytes = 1LL*SZ_1G,
870 + .block_size_in_pages = 128,
871 + .page_total_size_in_bytes = 2*SZ_1K + 64,
872 + .ecc_strength_in_bits = 4,
873 + .ecc_size_in_bytes = 512,
874 + .data_setup_in_ns = 60,
875 + .data_hold_in_ns = 30,
876 + .address_setup_in_ns = 50,
877 + .gpmi_sample_delay_in_ns = 6,
884 + .end_of_table = false,
885 + .manufacturer_code = 0x2c,
886 + .device_code = 0xd3,
887 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
888 + .chip_size_in_bytes = 1LL*SZ_1G,
889 + .block_size_in_pages = 128,
890 + .page_total_size_in_bytes = 2*SZ_1K + 64,
891 + .ecc_strength_in_bits = 4,
892 + .ecc_size_in_bytes = 512,
893 + .data_setup_in_ns = 15,
894 + .data_hold_in_ns = 15,
895 + .address_setup_in_ns = 15,
896 + .gpmi_sample_delay_in_ns = 6,
900 + "Intel JS29F08G08AAMiB1 and Micron MT29F8G08MAA; "
901 + "Intel JS29F08G08CAMiB1 and Micron MT29F16G08QAA",
904 + .end_of_table = false,
905 + .manufacturer_code = 0xec,
906 + .device_code = 0xd5,
907 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
908 + .chip_size_in_bytes = 2LL*SZ_1G,
909 + .block_size_in_pages = 128,
910 + .page_total_size_in_bytes = 2*SZ_1K + 64,
911 + .ecc_strength_in_bits = 4,
912 + .ecc_size_in_bytes = 512,
913 + .data_setup_in_ns = 20,
914 + .data_hold_in_ns = 15,
915 + .address_setup_in_ns = 20,
916 + .gpmi_sample_delay_in_ns = 6,
920 + "K9LAG08U0M K9HBG08U1M K9GAG08U0M",
923 + .end_of_table = false,
924 + .manufacturer_code = 0x2c,
925 + .device_code = 0xd5,
926 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
927 + .chip_size_in_bytes = 2LL*SZ_1G,
928 + .block_size_in_pages = 128,
929 + .page_total_size_in_bytes = 2*SZ_1K + 64,
930 + .ecc_strength_in_bits = 4,
931 + .ecc_size_in_bytes = 512,
932 + .data_setup_in_ns = 15,
933 + .data_hold_in_ns = 10,
934 + .address_setup_in_ns = 15,
935 + .gpmi_sample_delay_in_ns = 6,
939 + "Intel JS29F32G08FAMiB1 and Micron MT29F32G08TAA",
942 + .end_of_table = false,
943 + .manufacturer_code = 0x2c,
944 + .device_code = 0xdc,
945 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
946 + .chip_size_in_bytes = 512LL*SZ_1M,
947 + .block_size_in_pages = 128,
948 + .page_total_size_in_bytes = 2*SZ_1K + 64,
949 + .ecc_strength_in_bits = 4,
950 + .ecc_size_in_bytes = 512,
951 + .data_setup_in_ns = 20,
952 + .data_hold_in_ns = 20,
953 + .address_setup_in_ns = 20,
954 + .gpmi_sample_delay_in_ns = 6,
961 + .end_of_table = false,
962 + .manufacturer_code = 0x89,
963 + .device_code = 0xd3,
964 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
965 + .chip_size_in_bytes = 1LL*SZ_1G,
966 + .block_size_in_pages = 128,
967 + .page_total_size_in_bytes = 2*SZ_1K + 64,
968 + .ecc_strength_in_bits = 4,
969 + .ecc_size_in_bytes = 512,
970 + .data_setup_in_ns = 15,
971 + .data_hold_in_ns = 10,
972 + .address_setup_in_ns = 15,
973 + .gpmi_sample_delay_in_ns = 6,
977 + "JS29F08G08AAMiB2, JS29F08G08CAMiB2",
980 + .end_of_table = false,
981 + .manufacturer_code = 0x89,
982 + .device_code = 0xd5,
983 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
984 + .chip_size_in_bytes = 2LL*SZ_1G,
985 + .block_size_in_pages = 128,
986 + .page_total_size_in_bytes = 2*SZ_1K + 64,
987 + .ecc_strength_in_bits = 4,
988 + .ecc_size_in_bytes = 512,
989 + .data_setup_in_ns = 15,
990 + .data_hold_in_ns = 10,
991 + .address_setup_in_ns = 15,
992 + .gpmi_sample_delay_in_ns = 6,
996 + "JS29F32G08FAMiB2",
999 + .end_of_table = false,
1000 + .manufacturer_code = 0xad,
1001 + .device_code = 0xd5,
1002 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
1003 + .chip_size_in_bytes = 2LL*SZ_1G,
1004 + .block_size_in_pages = 128,
1005 + .page_total_size_in_bytes = 2*SZ_1K + 64,
1006 + .ecc_strength_in_bits = 4,
1007 + .ecc_size_in_bytes = 512,
1008 + .data_setup_in_ns = 15,
1009 + .data_hold_in_ns = 10,
1010 + .address_setup_in_ns = 20,
1011 + .gpmi_sample_delay_in_ns = 6,
1013 + .tRLOH_in_ns = -1,
1014 + .tRHOH_in_ns = -1,
1023 +static struct nand_device_info nand_device_info_table_type_7[] =
1026 + .end_of_table = false,
1027 + .manufacturer_code = 0x2c,
1028 + .device_code = 0xd3,
1029 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
1030 + .chip_size_in_bytes = 1LL*SZ_1G,
1031 + .block_size_in_pages = 64,
1032 + .page_total_size_in_bytes = 2*SZ_1K + 64,
1033 + .ecc_strength_in_bits = 4,
1034 + .ecc_size_in_bytes = 512,
1035 + .data_setup_in_ns = 25,
1036 + .data_hold_in_ns = 15,
1037 + .address_setup_in_ns = 10,
1038 + .gpmi_sample_delay_in_ns = 6,
1040 + .tRLOH_in_ns = -1,
1041 + .tRHOH_in_ns = -1,
1045 + .end_of_table = false,
1046 + .manufacturer_code = 0x2c,
1047 + .device_code = 0xdc,
1048 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
1049 + .chip_size_in_bytes = 512LL*SZ_1M,
1050 + .block_size_in_pages = 64,
1051 + .page_total_size_in_bytes = 2*SZ_1K + 64,
1052 + .ecc_strength_in_bits = 4,
1053 + .ecc_size_in_bytes = 512,
1054 + .data_setup_in_ns = 20,
1055 + .data_hold_in_ns = 10,
1056 + .address_setup_in_ns = 10,
1057 + .gpmi_sample_delay_in_ns = 6,
1059 + .tRLOH_in_ns = -1,
1060 + .tRHOH_in_ns = -1,
1064 + .end_of_table = false,
1065 + .manufacturer_code = 0xec,
1066 + .device_code = 0xdc,
1067 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
1068 + .chip_size_in_bytes = 512LL*SZ_1M,
1069 + .block_size_in_pages = 64,
1070 + .page_total_size_in_bytes = 2*SZ_1K + 64,
1071 + .ecc_strength_in_bits = 4,
1072 + .ecc_size_in_bytes = 512,
1073 + .data_setup_in_ns = 15,
1074 + .data_hold_in_ns = 12,
1075 + .address_setup_in_ns = 25,
1076 + .gpmi_sample_delay_in_ns = 6,
1078 + .tRLOH_in_ns = -1,
1079 + .tRHOH_in_ns = -1,
1083 + .end_of_table = false,
1084 + .manufacturer_code = 0xec,
1085 + .device_code = 0xd3,
1086 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
1087 + .chip_size_in_bytes = 1LL*SZ_1G,
1088 + .block_size_in_pages = 64,
1089 + .page_total_size_in_bytes = 2*SZ_1K + 64,
1090 + .ecc_strength_in_bits = 4,
1091 + .ecc_size_in_bytes = 512,
1092 + .data_setup_in_ns = 25,
1093 + .data_hold_in_ns = 15,
1094 + .address_setup_in_ns = 35,
1095 + .gpmi_sample_delay_in_ns = 6,
1097 + .tRLOH_in_ns = -1,
1098 + .tRHOH_in_ns = -1,
1099 + "K9K8G08UXM, K9NBG08U5A, K9WAG08U1A",
1102 + .end_of_table = false,
1103 + .manufacturer_code = 0xec,
1104 + .device_code = 0xd5,
1105 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
1106 + .chip_size_in_bytes = 2LL*SZ_1G,
1107 + .block_size_in_pages = 64,
1108 + .page_total_size_in_bytes = 2*SZ_1K + 64,
1109 + .ecc_strength_in_bits = 4,
1110 + .ecc_size_in_bytes = 512,
1111 + .data_setup_in_ns = 15,
1112 + .data_hold_in_ns = 12,
1113 + .address_setup_in_ns = 25,
1114 + .gpmi_sample_delay_in_ns = 6,
1116 + .tRLOH_in_ns = -1,
1117 + .tRHOH_in_ns = -1,
1121 + .end_of_table = false,
1122 + .manufacturer_code = 0xec,
1123 + .device_code = 0xda,
1124 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
1125 + .chip_size_in_bytes = 256LL*SZ_1M,
1126 + .block_size_in_pages = 64,
1127 + .page_total_size_in_bytes = 2*SZ_1K + 64,
1128 + .ecc_strength_in_bits = 4,
1129 + .ecc_size_in_bytes = 512,
1130 + .data_setup_in_ns = 20,
1131 + .data_hold_in_ns = 10,
1132 + .address_setup_in_ns = 20,
1133 + .gpmi_sample_delay_in_ns = 6,
1135 + .tRLOH_in_ns = -1,
1136 + .tRHOH_in_ns = -1,
1140 + .end_of_table = false,
1141 + .manufacturer_code = 0xec,
1142 + .device_code = 0xf1,
1143 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
1144 + .chip_size_in_bytes = 128LL*SZ_1M,
1145 + .block_size_in_pages = 64,
1146 + .page_total_size_in_bytes = 2*SZ_1K + 64,
1147 + .ecc_strength_in_bits = 4,
1148 + .ecc_size_in_bytes = 512,
1149 + .data_setup_in_ns = 15,
1150 + .data_hold_in_ns = 12,
1151 + .address_setup_in_ns = 20,
1152 + .gpmi_sample_delay_in_ns = 6,
1154 + .tRLOH_in_ns = -1,
1155 + .tRHOH_in_ns = -1,
1164 +static struct nand_device_info nand_device_info_table_type_8[] =
1167 + .end_of_table = false,
1168 + .manufacturer_code = 0xec,
1169 + .device_code = 0xd5,
1170 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
1171 + .chip_size_in_bytes = 2LL*SZ_1G,
1172 + .block_size_in_pages = 128,
1173 + .page_total_size_in_bytes = 4*SZ_1K + 128,
1174 + .ecc_strength_in_bits = 4,
1175 + .ecc_size_in_bytes = 512,
1176 + .data_setup_in_ns = 15,
1177 + .data_hold_in_ns = 10,
1178 + .address_setup_in_ns = 20,
1179 + .gpmi_sample_delay_in_ns = 6,
1181 + .tRLOH_in_ns = -1,
1182 + .tRHOH_in_ns = -1,
1186 + .end_of_table = false,
1187 + .manufacturer_code = 0xec,
1188 + .device_code = 0xd7,
1189 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
1190 + .chip_size_in_bytes = 4LL*SZ_1G,
1191 + .block_size_in_pages = 128,
1192 + .page_total_size_in_bytes = 4*SZ_1K + 128,
1193 + .ecc_strength_in_bits = 4,
1194 + .ecc_size_in_bytes = 512,
1195 + .data_setup_in_ns = 15,
1196 + .data_hold_in_ns = 15,
1197 + .address_setup_in_ns = 25,
1198 + .gpmi_sample_delay_in_ns = 6,
1200 + .tRLOH_in_ns = -1,
1201 + .tRHOH_in_ns = -1,
1202 + "K9LBG08U0M (32Gb), K9HCG08U1M (64Gb), K9MDG08U5M (128Gb)",
1205 + .end_of_table = false,
1206 + .manufacturer_code = 0xad,
1207 + .device_code = 0xd5,
1208 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
1209 + .chip_size_in_bytes = 2LL*SZ_1G,
1210 + .block_size_in_pages = 128,
1211 + .page_total_size_in_bytes = 4*SZ_1K + 128,
1212 + .ecc_strength_in_bits = 4,
1213 + .ecc_size_in_bytes = 512,
1214 + .data_setup_in_ns = 20,
1215 + .data_hold_in_ns = 20,
1216 + .address_setup_in_ns = 20,
1217 + .gpmi_sample_delay_in_ns = 0,
1219 + .tRLOH_in_ns = -1,
1220 + .tRHOH_in_ns = -1,
1224 + .end_of_table = false,
1225 + .manufacturer_code = 0xad,
1226 + .device_code = 0xd7,
1227 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
1228 + .chip_size_in_bytes = 4LL*SZ_1G,
1229 + .block_size_in_pages = 128,
1230 + .page_total_size_in_bytes = 4*SZ_1K + 128,
1231 + .ecc_strength_in_bits = 4,
1232 + .ecc_size_in_bytes = 512,
1233 + .data_setup_in_ns = 23,
1234 + .data_hold_in_ns = 20,
1235 + .address_setup_in_ns = 25,
1236 + .gpmi_sample_delay_in_ns = 0,
1238 + .tRLOH_in_ns = -1,
1239 + .tRHOH_in_ns = -1,
1248 +static struct nand_device_info nand_device_info_table_type_9[] =
1251 + .end_of_table = false,
1252 + .manufacturer_code = 0x98,
1253 + .device_code = 0xd3,
1254 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
1255 + .chip_size_in_bytes = 1LL*SZ_1G,
1256 + .block_size_in_pages = 128,
1257 + .page_total_size_in_bytes = 4*SZ_1K + 218,
1258 + .ecc_strength_in_bits = 8,
1259 + .ecc_size_in_bytes = 512,
1260 + .data_setup_in_ns = 15,
1261 + .data_hold_in_ns = 15,
1262 + .address_setup_in_ns = 10,
1263 + .gpmi_sample_delay_in_ns = 6,
1265 + .tRLOH_in_ns = -1,
1266 + .tRHOH_in_ns = -1,
1267 + "TC58NVG3D1DTG00",
1270 + .end_of_table = false,
1271 + .manufacturer_code = 0x98,
1272 + .device_code = 0xd5,
1273 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
1274 + .chip_size_in_bytes = 2LL*SZ_1G,
1275 + .block_size_in_pages = 128,
1276 + .page_total_size_in_bytes = 4*SZ_1K + 218,
1277 + .ecc_strength_in_bits = 8,
1278 + .ecc_size_in_bytes = 512,
1279 + .data_setup_in_ns = 15,
1280 + .data_hold_in_ns = 15,
1281 + .address_setup_in_ns = 10,
1282 + .gpmi_sample_delay_in_ns = 6,
1284 + .tRLOH_in_ns = -1,
1285 + .tRHOH_in_ns = -1,
1286 + "TC58NVG4D1DTG00",
1289 + .end_of_table = false,
1290 + .manufacturer_code = 0x98,
1291 + .device_code = 0xd7,
1292 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
1293 + .chip_size_in_bytes = 4LL*SZ_1G,
1294 + .block_size_in_pages = 128,
1295 + .page_total_size_in_bytes = 4*SZ_1K + 218,
1296 + .ecc_strength_in_bits = 8,
1297 + .ecc_size_in_bytes = 512,
1298 + .data_setup_in_ns = 15,
1299 + .data_hold_in_ns = 15,
1300 + .address_setup_in_ns = 10,
1301 + .gpmi_sample_delay_in_ns = 6,
1303 + .tRLOH_in_ns = -1,
1304 + .tRHOH_in_ns = -1,
1305 + "TH58NVG6D1DTG20",
1308 + .end_of_table = false,
1309 + .manufacturer_code = 0x89,
1310 + .device_code = 0xd5,
1311 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
1312 + .chip_size_in_bytes = 2LL*SZ_1G,
1313 + .block_size_in_pages = 128,
1314 + .page_total_size_in_bytes = 4*SZ_1K + 218,
1315 + .ecc_strength_in_bits = 8,
1316 + .ecc_size_in_bytes = 512,
1317 + .data_setup_in_ns = 10,
1318 + .data_hold_in_ns = 10,
1319 + .address_setup_in_ns = 15,
1320 + .gpmi_sample_delay_in_ns = 6,
1322 + .tRLOH_in_ns = -1,
1323 + .tRHOH_in_ns = -1,
1324 + "JS29F16G08AAMC1, JS29F32G08CAMC1",
1327 + .end_of_table = false,
1328 + .manufacturer_code = 0x2c,
1329 + .device_code = 0xd5,
1330 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
1331 + .chip_size_in_bytes = 2LL*SZ_1G,
1332 + .block_size_in_pages = 128,
1333 + .page_total_size_in_bytes = 4*SZ_1K + 218,
1334 + .ecc_strength_in_bits = 8,
1335 + .ecc_size_in_bytes = 512,
1336 + .data_setup_in_ns = 15,
1337 + .data_hold_in_ns = 10,
1338 + .address_setup_in_ns = 15,
1339 + .gpmi_sample_delay_in_ns = 6,
1341 + .tRLOH_in_ns = -1,
1342 + .tRHOH_in_ns = -1,
1343 + "MT29F16G08MAA, MT29F32G08QAA",
1346 + .end_of_table = false,
1347 + .manufacturer_code = 0x2c,
1348 + .device_code = 0xd7,
1349 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
1350 + .chip_size_in_bytes = 4LL*SZ_1G,
1351 + .block_size_in_pages = 128,
1352 + .page_total_size_in_bytes = 4*SZ_1K + 218,
1353 + .ecc_strength_in_bits = 8,
1354 + .ecc_size_in_bytes = 512,
1355 + .data_setup_in_ns = 15,
1356 + .data_hold_in_ns = 10,
1357 + .address_setup_in_ns = 15,
1358 + .gpmi_sample_delay_in_ns = 6,
1360 + .tRLOH_in_ns = -1,
1361 + .tRHOH_in_ns = -1,
1362 + "MT29F64G08TAA (32Gb), MT29F32G08CBAAA (32Gb) MT29F64G08CFAAA (64Gb)",
1365 + .end_of_table = false,
1366 + .manufacturer_code = 0x2c,
1367 + .device_code = 0xd9,
1368 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
1369 + .chip_size_in_bytes = 8LL*SZ_1G,
1370 + .block_size_in_pages = 128,
1371 + .page_total_size_in_bytes = 4*SZ_1K + 218,
1372 + .ecc_strength_in_bits = 8,
1373 + .ecc_size_in_bytes = 512,
1374 + .data_setup_in_ns = 10,
1375 + .data_hold_in_ns = 10,
1376 + .address_setup_in_ns = 15,
1377 + .gpmi_sample_delay_in_ns = 6,
1379 + .tRLOH_in_ns = -1,
1380 + .tRHOH_in_ns = -1,
1381 + "MT29F128G08CJAAA",
1384 + .end_of_table = false,
1385 + .manufacturer_code = 0x89,
1386 + .device_code = 0xd7,
1387 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
1388 + .chip_size_in_bytes = 4LL*SZ_1G,
1389 + .block_size_in_pages = 128,
1390 + .page_total_size_in_bytes = 4*SZ_1K + 218,
1391 + .ecc_strength_in_bits = 8,
1392 + .ecc_size_in_bytes = 512,
1393 + .data_setup_in_ns = 10,
1394 + .data_hold_in_ns = 10,
1395 + .address_setup_in_ns = 15,
1396 + .gpmi_sample_delay_in_ns = 6,
1398 + .tRLOH_in_ns = -1,
1399 + .tRHOH_in_ns = -1,
1403 + .end_of_table = false,
1404 + .manufacturer_code = 0xec,
1405 + .device_code = 0xd7,
1406 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
1407 + .chip_size_in_bytes = 4LL*SZ_1G,
1408 + .block_size_in_pages = 128,
1409 + .page_total_size_in_bytes = 4*SZ_1K + 218,
1410 + .ecc_strength_in_bits = 8,
1411 + .ecc_size_in_bytes = 512,
1412 + .data_setup_in_ns = 20,
1413 + .data_hold_in_ns = 10,
1414 + .address_setup_in_ns = 25,
1415 + .gpmi_sample_delay_in_ns = 6,
1417 + .tRLOH_in_ns = -1,
1418 + .tRHOH_in_ns = -1,
1422 + .end_of_table = false,
1423 + .manufacturer_code = 0xec,
1424 + .device_code = 0xd5,
1425 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
1426 + .chip_size_in_bytes = 2LL*SZ_1G,
1427 + .block_size_in_pages = 128,
1428 + .page_total_size_in_bytes = 4*SZ_1K + 218,
1429 + .ecc_strength_in_bits = 8,
1430 + .ecc_size_in_bytes = 512,
1431 + .data_setup_in_ns = 20,
1432 + .data_hold_in_ns = 10,
1433 + .address_setup_in_ns = 20,
1434 + .gpmi_sample_delay_in_ns = 6,
1436 + .tRLOH_in_ns = -1,
1437 + .tRHOH_in_ns = -1,
1438 + "K9GAG08U0D, K9LBG08U1D, K9HCG08U5D",
1446 +static struct nand_device_info nand_device_info_table_type_10[] =
1449 + .end_of_table = false,
1450 + .manufacturer_code = 0xec,
1451 + .device_code = 0xd3,
1452 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
1453 + .chip_size_in_bytes = 1LL*SZ_1G,
1454 + .block_size_in_pages = 64,
1455 + .page_total_size_in_bytes = 4*SZ_1K + 128,
1456 + .ecc_strength_in_bits = 4,
1457 + .ecc_size_in_bytes = 512,
1458 + .data_setup_in_ns = 15,
1459 + .data_hold_in_ns = 10,
1460 + .address_setup_in_ns = 20,
1461 + .gpmi_sample_delay_in_ns = 6,
1463 + .tRLOH_in_ns = -1,
1464 + .tRHOH_in_ns = -1,
1468 + .end_of_table = false,
1469 + .manufacturer_code = 0xec,
1470 + .device_code = 0xd5,
1471 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
1472 + .chip_size_in_bytes = 2LL*SZ_1G,
1473 + .block_size_in_pages = 64,
1474 + .page_total_size_in_bytes = 4*SZ_1K + 128,
1475 + .ecc_strength_in_bits = 4,
1476 + .ecc_size_in_bytes = 512,
1477 + .data_setup_in_ns = 25,
1478 + .data_hold_in_ns = 15,
1479 + .address_setup_in_ns = 30,
1480 + .gpmi_sample_delay_in_ns = 6,
1482 + .tRLOH_in_ns = -1,
1483 + .tRHOH_in_ns = -1,
1487 + .end_of_table = false,
1488 + .manufacturer_code = 0xec,
1489 + .device_code = 0xd7,
1490 + .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
1491 + .chip_size_in_bytes = 4LL*SZ_1G,
1492 + .block_size_in_pages = 64,
1493 + .page_total_size_in_bytes = 4*SZ_1K + 128,
1494 + .ecc_strength_in_bits = 4,
1495 + .ecc_size_in_bytes = 512,
1496 + .data_setup_in_ns = 15,
1497 + .data_hold_in_ns = 15,
1498 + .address_setup_in_ns = 25,
1499 + .gpmi_sample_delay_in_ns = 6,
1501 + .tRLOH_in_ns = -1,
1502 + .tRHOH_in_ns = -1,
1511 +static struct nand_device_info nand_device_info_table_type_11[] =
1514 + .end_of_table = false,
1515 + .manufacturer_code = 0x98,
1516 + .device_code = 0xd7,
1517 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
1518 + .chip_size_in_bytes = 4LL*SZ_1G,
1519 + .block_size_in_pages = 128,
1520 + .page_total_size_in_bytes = 8*SZ_1K + 376,
1521 + .ecc_strength_in_bits = 14,
1522 + .ecc_size_in_bytes = 512,
1523 + .data_setup_in_ns = 15,
1524 + .data_hold_in_ns = 10,
1525 + .address_setup_in_ns = 8,
1526 + .gpmi_sample_delay_in_ns = 6,
1529 + .tRHOH_in_ns = 25,
1530 + "TC58NVG5D2ELAM8 (4GB), TH58NVG6D2ELAM8 (8GB)",
1533 + .end_of_table = false,
1534 + .manufacturer_code = 0x98,
1535 + .device_code = 0xde,
1536 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
1537 + .chip_size_in_bytes = 8LL*SZ_1G,
1538 + .block_size_in_pages = 128,
1539 + .page_total_size_in_bytes = 8*SZ_1K + 376,
1540 + .ecc_strength_in_bits = 14,
1541 + .ecc_size_in_bytes = 512,
1542 + .data_setup_in_ns = 15,
1543 + .data_hold_in_ns = 10,
1544 + .address_setup_in_ns = 8,
1545 + .gpmi_sample_delay_in_ns = 6,
1548 + .tRHOH_in_ns = 25,
1549 + "TH58NVG7D2ELAM8",
1557 +static struct nand_device_info nand_device_info_table_type_15[] =
1560 + .end_of_table = false,
1561 + .manufacturer_code = 0xec,
1562 + .device_code = 0xd7,
1563 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
1564 + .chip_size_in_bytes = 4LL*SZ_1G,
1565 + .block_size_in_pages = 128,
1566 + .page_total_size_in_bytes = 8*SZ_1K + 436,
1567 + .ecc_strength_in_bits = 16,
1568 + .ecc_size_in_bytes = 512,
1569 + .data_setup_in_ns = 20,
1570 + .data_hold_in_ns = 10,
1571 + .address_setup_in_ns = 25,
1572 + .gpmi_sample_delay_in_ns = 6,
1575 + .tRHOH_in_ns = 15,
1576 + "K9GBG08U0M (4GB, 1CE); K9LCG08U1M (8GB, 2CE); K9HDG08U5M (16GB, 4CE)",
1584 +static struct nand_device_info nand_device_info_table_bch_ecc12[] =
1587 + .end_of_table = false,
1588 + .manufacturer_code = 0xad,
1589 + .device_code = 0xd7,
1590 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
1591 + .chip_size_in_bytes = 4LL*SZ_1G,
1592 + .block_size_in_pages = 128,
1593 + .page_total_size_in_bytes = 4*SZ_1K + 224,
1594 + .ecc_strength_in_bits = 12,
1595 + .ecc_size_in_bytes = 512,
1596 + .data_setup_in_ns = 15,
1597 + .data_hold_in_ns = 10,
1598 + .address_setup_in_ns = 20,
1599 + .gpmi_sample_delay_in_ns = 6,
1602 + .tRHOH_in_ns = 15,
1603 + "H27UBG8T2M (4GB, 1CE), H27UCG8UDM (8GB, 2CE), H27UDG8VEM (16GB, 4CE)",
1606 + .end_of_table = false,
1607 + .manufacturer_code = 0xad,
1608 + .device_code = 0xde,
1609 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
1610 + .chip_size_in_bytes = 8LL*SZ_1G,
1611 + .block_size_in_pages = 128,
1612 + .page_total_size_in_bytes = 4*SZ_1K + 224,
1613 + .ecc_strength_in_bits = 12,
1614 + .ecc_size_in_bytes = 512,
1615 + .data_setup_in_ns = 15,
1616 + .data_hold_in_ns = 10,
1617 + .address_setup_in_ns = 20,
1618 + .gpmi_sample_delay_in_ns = 6,
1621 + .tRHOH_in_ns = 15,
1622 + "H27UEG8YEM (32GB, 4CE)",
1625 + .end_of_table = false,
1626 + .manufacturer_code = 0x2c,
1627 + .device_code = 0xd7,
1628 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
1629 + .chip_size_in_bytes = 4LL*SZ_1G,
1630 + .block_size_in_pages = 128,
1631 + .page_total_size_in_bytes = 4*SZ_1K + 218,
1632 + .ecc_strength_in_bits = 12,
1633 + .ecc_size_in_bytes = 512,
1634 + .data_setup_in_ns = 10,
1635 + .data_hold_in_ns = 10,
1636 + .address_setup_in_ns = 15,
1637 + .gpmi_sample_delay_in_ns = 6,
1640 + .tRHOH_in_ns = 15,
1641 + "MT29F32G08CBAAA (4GB, 1CE), MT29F64G08CFAAA (8GB, 2CE)",
1644 + .end_of_table = false,
1645 + .manufacturer_code = 0x2c,
1646 + .device_code = 0xd9,
1647 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
1648 + .chip_size_in_bytes = 8LL*SZ_1G,
1649 + .block_size_in_pages = 128,
1650 + .page_total_size_in_bytes = 4*SZ_1K + 218,
1651 + .ecc_strength_in_bits = 12,
1652 + .ecc_size_in_bytes = 512,
1653 + .data_setup_in_ns = 10,
1654 + .data_hold_in_ns = 10,
1655 + .address_setup_in_ns = 15,
1656 + .gpmi_sample_delay_in_ns = 6,
1659 + .tRHOH_in_ns = 15,
1660 + "MT29F128G08CJAAA (16GB, 2CE)",
1663 + .end_of_table = false,
1664 + .manufacturer_code = 0x2c,
1665 + .device_code = 0x48,
1666 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
1667 + .chip_size_in_bytes = 2LL*SZ_1G,
1668 + .block_size_in_pages = 256,
1669 + .page_total_size_in_bytes = 4*SZ_1K + 224,
1670 + .ecc_strength_in_bits = 12,
1671 + .ecc_size_in_bytes = 512,
1672 + .data_setup_in_ns = 15,
1673 + .data_hold_in_ns = 10,
1674 + .address_setup_in_ns = 20,
1675 + .gpmi_sample_delay_in_ns = 6,
1678 + .tRHOH_in_ns = 15,
1679 + "MT29F16G08CBABA (2GB, 1CE)",
1682 + .end_of_table = false,
1683 + .manufacturer_code = 0x2c,
1684 + .device_code = 0x68,
1685 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
1686 + .chip_size_in_bytes = 4LL*SZ_1G,
1687 + .block_size_in_pages = 256,
1688 + .page_total_size_in_bytes = 4*SZ_1K + 224,
1689 + .ecc_strength_in_bits = 12,
1690 + .ecc_size_in_bytes = 512,
1691 + .data_setup_in_ns = 15,
1692 + .data_hold_in_ns = 10,
1693 + .address_setup_in_ns = 20,
1694 + .gpmi_sample_delay_in_ns = 6,
1697 + .tRHOH_in_ns = 15,
1698 + "MT29F32G08CBABA (4GB, 1CE); "
1699 + "MT29F64G08CEABA (8GB, 2CE); "
1700 + "MT29F64G08CFABA (8GB, 2CE)",
1703 + .end_of_table = false,
1704 + .manufacturer_code = 0x2c,
1705 + .device_code = 0x88,
1706 + .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
1707 + .chip_size_in_bytes = 8LL*SZ_1G,
1708 + .block_size_in_pages = 256,
1709 + .page_total_size_in_bytes = 4*SZ_1K + 224,
1710 + .ecc_strength_in_bits = 12,
1711 + .ecc_size_in_bytes = 512,
1712 + .data_setup_in_ns = 15,
1713 + .data_hold_in_ns = 10,
1714 + .address_setup_in_ns = 20,
1715 + .gpmi_sample_delay_in_ns = 6,
1718 + .tRHOH_in_ns = 15,
1719 + "MT29F128G08CJABA (16GB, 2CE); "
1720 + "MT29F128G08CKABA (16GB, 2CE); "
1721 + "MT29F256G08CUABA (32GB, 4CE)",
1727 + * The following macros make it convenient to extract information from an ID
1728 + * byte array. All these macros begin with the prefix "ID_".
1730 + * Macros of the form:
1732 + * ID_GET_[<manufacturer>_[<modifier>_]]<field>
1734 + * extract the given field from an ID byte array. Macros of the form:
1736 + * ID_[<manufacturer>_[<modifier>_]]<field>_<meaning>
1738 + * contain the value for the given field that has the given meaning.
1740 + * If the <manufacturer> appears, it means this macro represents a view of this
1741 + * field that is specific to the given manufacturer.
1743 + * If the <modifier> appears, it means this macro represents a view of this
1744 + * field that the given manufacturer applies only under specific conditions.
1746 + * Here is a simple example:
1748 + * ID_PAGE_SIZE_CODE_2K
1750 + * This macro has the value of the "Page Size" field that indicates the page
1753 + * A more complicated example:
1755 + * ID_SAMSUNG_6_BYTE_PAGE_SIZE_CODE_8K (0x2)
1757 + * This macro has the value of the "Page Size" field for Samsung parts that
1758 + * indicates the page size is 8K. However, this interpretation is only correct
1759 + * for devices that return 6 ID bytes.
1762 +/* Byte 1 ------------------------------------------------------------------- */
1764 +#define ID_GET_BYTE_1(id) ((id)[0])
1766 +#define ID_GET_MFR_CODE(id) ID_GET_BYTE_1(id)
1768 +/* Byte 2 ------------------------------------------------------------------- */
1770 +#define ID_GET_BYTE_2(id) ((id)[1])
1772 +#define ID_GET_DEVICE_CODE(id) ID_GET_BYTE_2(id)
1773 + #define ID_SAMSUNG_DEVICE_CODE_1_GBIT (0xf1)
1774 + #define ID_SAMSUNG_DEVICE_CODE_2_GBIT (0xda)
1775 + #define ID_HYNIX_DEVICE_CODE_ECC12 (0xd7)
1776 + #define ID_HYNIX_DEVICE_CODE_ECC12_LARGE (0xde)
1777 + #define ID_MICRON_DEVICE_CODE_ECC12 (0xd7) /* ECC12 */
1778 + #define ID_MICRON_DEVICE_CODE_ECC12_LARGE (0xd9) /* ECC12 8GB/CE */
1779 + #define ID_MICRON_DEVICE_CODE_ECC12_2GB_PER_CE (0x48) /* L63B 2GB/CE */
1780 + #define ID_MICRON_DEVICE_CODE_ECC12_4GB_PER_CE (0x68) /* L63B 4GB/CE */
1781 + #define ID_MICRON_DEVICE_CODE_ECC12_8GB_PER_CE (0x88) /* L63B 8GB/CE */
1783 +/* Byte 3 ------------------------------------------------------------------- */
1785 +#define ID_GET_BYTE_3(id) ((id)[2])
1787 +#define ID_GET_DIE_COUNT_CODE(id) ((ID_GET_BYTE_3(id) >> 0) & 0x3)
1789 +#define ID_GET_CELL_TYPE_CODE(id) ((ID_GET_BYTE_3(id) >> 2) & 0x3)
1790 + #define ID_CELL_TYPE_CODE_SLC (0x0) /* All others => MLC. */
1792 +#define ID_GET_SAMSUNG_SIMUL_PROG(id) ((ID_GET_BYTE_3(id) >> 4) & 0x3)
1794 +#define ID_GET_MICRON_SIMUL_PROG(id) ((ID_GET_BYTE_3(id) >> 4) & 0x3)
1796 +#define ID_GET_CACHE_PROGRAM(id) ((ID_GET_BYTE_3(id) >> 7) & 0x1)
1798 +/* Byte 4 ------------------------------------------------------------------- */
1800 +#define ID_GET_BYTE_4(id) ((id)[3])
1801 + #define ID_HYNIX_BYTE_4_ECC12_DEVICE (0x25)
1803 +#define ID_GET_PAGE_SIZE_CODE(id) ((ID_GET_BYTE_4(id) >> 0) & 0x3)
1804 + #define ID_PAGE_SIZE_CODE_1K (0x0)
1805 + #define ID_PAGE_SIZE_CODE_2K (0x1)
1806 + #define ID_PAGE_SIZE_CODE_4K (0x2)
1807 + #define ID_PAGE_SIZE_CODE_8K (0x3)
1808 + #define ID_SAMSUNG_6_BYTE_PAGE_SIZE_CODE_8K (0x2)
1810 +#define ID_GET_OOB_SIZE_CODE(id) ((ID_GET_BYTE_4(id) >> 2) & 0x1)
1812 +#define ID_GET_BLOCK_SIZE_CODE(id) ((ID_GET_BYTE_4(id) >> 4) & 0x3)
1814 +/* Byte 5 ------------------------------------------------------------------- */
1816 +#define ID_GET_BYTE_5(id) ((id)[4])
1817 + #define ID_MICRON_BYTE_5_ECC12 (0x84)
1819 +#define ID_GET_SAMSUNG_ECC_LEVEL_CODE(id) ((ID_GET_BYTE_5(id) >> 4) & 0x7)
1820 + #define ID_SAMSUNG_ECC_LEVEL_CODE_8 (0x03)
1821 + #define ID_SAMSUNG_ECC_LEVEL_CODE_24 (0x05)
1823 +#define ID_GET_PLANE_COUNT_CODE(id) ((ID_GET_BYTE_5(id) >> 2) & 0x3)
1825 +/* Byte 6 ------------------------------------------------------------------- */
1827 +#define ID_GET_BYTE_6(id) ((id)[5])
1828 + #define ID_TOSHIBA_BYTE_6_PAGE_SIZE_CODE_8K (0x54)
1829 + #define ID_TOSHIBA_BYTE_6_PAGE_SIZE_CODE_4K (0x13)
1831 +#define ID_GET_SAMSUNG_DEVICE_VERSION_CODE(id) ((ID_GET_BYTE_6(id)>>0) & 0x7)
1832 + #define ID_SAMSUNG_DEVICE_VERSION_CODE_40NM (0x01)
1834 +/* -------------------------------------------------------------------------- */
1836 +void nand_device_print_info(struct nand_device_info *info)
1839 + const char *mfr_name;
1840 + const char *cell_technology_name;
1841 + uint64_t chip_size;
1842 + const char *chip_size_units;
1843 + unsigned page_data_size_in_bytes;
1844 + unsigned page_oob_size_in_bytes;
1846 + /* Check for nonsense. */
1851 + /* Prepare the manufacturer name. */
1853 + mfr_name = "Unknown";
1855 + for (i = 0; nand_manuf_ids[i].id; i++) {
1856 + if (nand_manuf_ids[i].id == info->manufacturer_code) {
1857 + mfr_name = nand_manuf_ids[i].name;
1862 + /* Prepare the name of the cell technology. */
1864 + switch (info->cell_technology) {
1865 + case NAND_DEVICE_CELL_TECH_SLC:
1866 + cell_technology_name = "SLC";
1868 + case NAND_DEVICE_CELL_TECH_MLC:
1869 + cell_technology_name = "MLC";
1872 + cell_technology_name = "Unknown";
1876 + /* Prepare the chip size. */
1878 + if ((info->chip_size_in_bytes >= SZ_1G) &&
1879 + !(info->chip_size_in_bytes % SZ_1G)) {
1880 + chip_size = info->chip_size_in_bytes / ((uint64_t) SZ_1G);
1881 + chip_size_units = "GiB";
1882 + } else if ((info->chip_size_in_bytes >= SZ_1M) &&
1883 + !(info->chip_size_in_bytes % SZ_1M)) {
1884 + chip_size = info->chip_size_in_bytes / ((uint64_t) SZ_1M);
1885 + chip_size_units = "MiB";
1887 + chip_size = info->chip_size_in_bytes;
1888 + chip_size_units = "B";
1891 + /* Prepare the page geometry. */
1893 + page_data_size_in_bytes = info->page_total_size_in_bytes & ~0x3ff;
1894 + page_oob_size_in_bytes = info->page_total_size_in_bytes & 0x3ff;
1896 + /* Print the information. */
1898 + printk(KERN_INFO "Manufacturer : %s (0x%02x)\n", mfr_name,
1899 + info->manufacturer_code);
1900 + printk(KERN_INFO "Device Code : 0x%02x\n", info->device_code);
1901 + printk(KERN_INFO "Cell Technology : %s\n", cell_technology_name);
1902 + printk(KERN_INFO "Chip Size : %u %s\n", (u32)chip_size,
1904 + printk(KERN_INFO "Pages per Block : %u\n",
1905 + info->block_size_in_pages);
1906 + printk(KERN_INFO "Page Geometry : %u+%u\n", page_data_size_in_bytes,
1907 + page_oob_size_in_bytes);
1908 + printk(KERN_INFO "ECC Strength : %u bits\n",
1909 + info->ecc_strength_in_bits);
1910 + printk(KERN_INFO "ECC Size : %u B\n", info->ecc_size_in_bytes);
1911 + printk(KERN_INFO "Data Setup Time : %u ns\n", info->data_setup_in_ns);
1912 + printk(KERN_INFO "Data Hold Time : %u ns\n", info->data_hold_in_ns);
1913 + printk(KERN_INFO "Address Setup Time: %u ns\n",
1914 + info->address_setup_in_ns);
1915 + printk(KERN_INFO "GPMI Sample Delay : %u ns\n",
1916 + info->gpmi_sample_delay_in_ns);
1917 + if (info->tREA_in_ns >= 0)
1918 + printk(KERN_INFO "tREA : %u ns\n",
1919 + info->tREA_in_ns);
1921 + printk(KERN_INFO "tREA : Unknown\n");
1922 + if (info->tREA_in_ns >= 0)
1923 + printk(KERN_INFO "tRLOH : %u ns\n",
1924 + info->tRLOH_in_ns);
1926 + printk(KERN_INFO "tRLOH : Unknown\n");
1927 + if (info->tREA_in_ns >= 0)
1928 + printk(KERN_INFO "tRHOH : %u ns\n",
1929 + info->tRHOH_in_ns);
1931 + printk(KERN_INFO "tRHOH : Unknown\n");
1932 + if (info->description)
1933 + printk(KERN_INFO "Description : %s\n", info->description);
1935 + printk(KERN_INFO "Description : <None>\n");
1939 +static struct nand_device_info *nand_device_info_search(
1940 + struct nand_device_info *table, uint8_t mfr_code, uint8_t device_code)
1943 + for (; !table->end_of_table; table++) {
1944 + if (table->manufacturer_code != mfr_code)
1946 + if (table->device_code != device_code)
1955 +static struct nand_device_info *nand_device_info_fn_toshiba(const uint8_t id[])
1957 + struct nand_device_info *table;
1959 + /* Check for an SLC device. */
1961 + if (ID_GET_CELL_TYPE_CODE(id) == ID_CELL_TYPE_CODE_SLC) {
1963 + return nand_device_info_search(nand_device_info_table_type_2,
1964 + ID_GET_MFR_CODE(id), ID_GET_DEVICE_CODE(id));
1968 + * Look for 8K page Toshiba MLC devices.
1970 + * The page size field in byte 4 can't be used because the field was
1971 + * redefined in the 8K parts so the value meaning "8K page" is the same
1972 + * as the value meaning "4K page" on the 4K page devices.
1974 + * The only identifiable difference between the 4K and 8K page Toshiba
1975 + * devices with a device code of 0xd7 is the undocumented 6th ID byte.
1976 + * The 4K device returns a value of 0x13 and the 8K a value of 0x54.
1977 + * Toshiba has verified that this is an acceptable method to distinguish
1978 + * the two device families.
1981 + if (ID_GET_BYTE_6(id) == ID_TOSHIBA_BYTE_6_PAGE_SIZE_CODE_8K) {
1983 + table = nand_device_info_table_type_11;
1984 + } else if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) {
1986 + table = nand_device_info_table_type_9;
1989 + table = nand_device_info_table_large_mlc;
1992 + return nand_device_info_search(table, ID_GET_MFR_CODE(id),
1993 + ID_GET_DEVICE_CODE(id));
1997 +static struct nand_device_info *nand_device_info_fn_samsung(const uint8_t id[])
1999 + struct nand_device_info *table;
2001 + /* Check for an MLC device. */
2003 + if (ID_GET_CELL_TYPE_CODE(id) != ID_CELL_TYPE_CODE_SLC) {
2005 + /* Is this a Samsung 8K Page MLC device with 16 bit ECC? */
2006 + if ((ID_GET_SAMSUNG_ECC_LEVEL_CODE(id) ==
2007 + ID_SAMSUNG_ECC_LEVEL_CODE_24) &&
2008 + (ID_GET_PAGE_SIZE_CODE(id) ==
2009 + ID_SAMSUNG_6_BYTE_PAGE_SIZE_CODE_8K)) {
2011 + table = nand_device_info_table_type_15;
2013 + /* Is this a Samsung 42nm ECC8 device with a 6 byte ID? */
2014 + else if ((ID_GET_SAMSUNG_ECC_LEVEL_CODE(id) ==
2015 + ID_SAMSUNG_ECC_LEVEL_CODE_8) &&
2016 + (ID_GET_SAMSUNG_DEVICE_VERSION_CODE(id) ==
2017 + ID_SAMSUNG_DEVICE_VERSION_CODE_40NM)) {
2019 + table = nand_device_info_table_type_9;
2020 + } else if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) {
2022 + table = nand_device_info_table_type_8;
2025 + table = nand_device_info_table_large_mlc;
2030 + /* Check the page size first. */
2031 + if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) {
2033 + table = nand_device_info_table_type_10;
2035 + /* Check the chip size. */
2036 + else if (ID_GET_DEVICE_CODE(id) ==
2037 + ID_SAMSUNG_DEVICE_CODE_1_GBIT) {
2038 + if (!ID_GET_CACHE_PROGRAM(id)) {
2040 + * 128 MiB Samsung chips without cache program
2043 + * The K9F1G08U0B does not support multi-plane
2044 + * program, so the if statement below cannot be
2045 + * used to identify it.
2047 + table = nand_device_info_table_type_7;
2050 + /* Smaller sizes are Type 2 by default. */
2051 + table = nand_device_info_table_type_2;
2054 + /* Check number of simultaneously programmed pages. */
2055 + if (ID_GET_SAMSUNG_SIMUL_PROG(id) &&
2056 + ID_GET_PLANE_COUNT_CODE(id)) {
2058 + table = nand_device_info_table_type_7;
2061 + table = nand_device_info_table_type_2;
2068 + return nand_device_info_search(table, ID_GET_MFR_CODE(id),
2069 + ID_GET_DEVICE_CODE(id));
2073 +static struct nand_device_info *nand_device_info_fn_stmicro(const uint8_t id[])
2075 + struct nand_device_info *table;
2077 + /* Check for an SLC device. */
2079 + if (ID_GET_CELL_TYPE_CODE(id) == ID_CELL_TYPE_CODE_SLC)
2081 + table = nand_device_info_table_type_2;
2084 + table = nand_device_info_table_large_mlc;
2086 + return nand_device_info_search(table, ID_GET_MFR_CODE(id),
2087 + ID_GET_DEVICE_CODE(id));
2091 +static struct nand_device_info *nand_device_info_fn_hynix(const uint8_t id[])
2093 + struct nand_device_info *table;
2095 + /* Check for an SLC device. */
2097 + if (ID_GET_CELL_TYPE_CODE(id) == ID_CELL_TYPE_CODE_SLC) {
2099 + return nand_device_info_search(nand_device_info_table_type_2,
2100 + ID_GET_MFR_CODE(id), ID_GET_DEVICE_CODE(id));
2104 + * Check for ECC12 devices.
2106 + * We look at the 4th ID byte to distinguish some Hynix ECC12 devices
2107 + * from the similar ECC8 part. For example H27UBG8T2M (ECC12) 4th byte
2108 + * is 0x25, whereas H27UDG8WFM (ECC8) 4th byte is 0xB6.
2111 + if ((ID_GET_DEVICE_CODE(id) == ID_HYNIX_DEVICE_CODE_ECC12 &&
2112 + ID_GET_BYTE_4(id) == ID_HYNIX_BYTE_4_ECC12_DEVICE) ||
2113 + (ID_GET_DEVICE_CODE(id) == ID_HYNIX_DEVICE_CODE_ECC12_LARGE)) {
2115 + table = nand_device_info_table_bch_ecc12;
2116 + } else if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) {
2118 + * So far, all other Samsung and Hynix 4K page devices are
2121 + table = nand_device_info_table_type_8;
2124 + table = nand_device_info_table_large_mlc;
2126 + return nand_device_info_search(table, ID_GET_MFR_CODE(id),
2127 + ID_GET_DEVICE_CODE(id));
2131 +static struct nand_device_info *nand_device_info_fn_micron(const uint8_t id[])
2133 + struct nand_device_info *table;
2135 + /* Check for an SLC device. */
2137 + if (ID_GET_CELL_TYPE_CODE(id) == ID_CELL_TYPE_CODE_SLC) {
2139 + /* Check number of simultaneously programmed pages. */
2141 + if (ID_GET_MICRON_SIMUL_PROG(id)) {
2143 + table = nand_device_info_table_type_7;
2145 + /* Zero simultaneously programmed pages means Type 2. */
2146 + table = nand_device_info_table_type_2;
2149 + return nand_device_info_search(table, ID_GET_MFR_CODE(id),
2150 + ID_GET_DEVICE_CODE(id));
2155 + * We look at the 5th ID byte to distinguish some Micron ECC12 NANDs
2156 + * from the similar ECC8 part.
2158 + * For example MT29F64G08CFAAA (ECC12) 5th byte is 0x84, whereas
2159 + * MT29F64G08TAA (ECC8) 5th byte is 0x78.
2161 + * We also have a special case for the Micron L63B family
2162 + * (256 page/block), which has unique device codes but no ID fields that
2163 + * can easily be used to distinguish the family.
2166 + if ((ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC12 &&
2167 + ID_GET_BYTE_5(id) == ID_MICRON_BYTE_5_ECC12) ||
2168 + (ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC12_LARGE) ||
2169 + (ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC12_2GB_PER_CE) ||
2170 + (ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC12_4GB_PER_CE) ||
2171 + (ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC12_8GB_PER_CE)) {
2173 + table = nand_device_info_table_bch_ecc12;
2174 + } else if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) {
2175 + /* Toshiba devices with 4K pages are Type 9. */
2176 + table = nand_device_info_table_type_9;
2179 + table = nand_device_info_table_large_mlc;
2182 + return nand_device_info_search(table, ID_GET_MFR_CODE(id),
2183 + ID_GET_DEVICE_CODE(id));
2187 +static struct nand_device_info *nand_device_info_fn_sandisk(const uint8_t id[])
2189 + struct nand_device_info *table;
2191 + if (ID_GET_CELL_TYPE_CODE(id) != ID_CELL_TYPE_CODE_SLC) {
2193 + table = nand_device_info_table_large_mlc;
2196 + table = nand_device_info_table_type_2;
2199 + return nand_device_info_search(table, ID_GET_MFR_CODE(id),
2200 + ID_GET_DEVICE_CODE(id));
2204 +static struct nand_device_info *nand_device_info_fn_intel(const uint8_t id[])
2206 + struct nand_device_info *table;
2208 + /* Check for an SLC device. */
2210 + if (ID_GET_CELL_TYPE_CODE(id) == ID_CELL_TYPE_CODE_SLC) {
2212 + return nand_device_info_search(nand_device_info_table_type_2,
2213 + ID_GET_MFR_CODE(id), ID_GET_DEVICE_CODE(id));
2216 + if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) {
2218 + table = nand_device_info_table_type_9;
2221 + table = nand_device_info_table_large_mlc;
2224 + return nand_device_info_search(table, ID_GET_MFR_CODE(id),
2225 + ID_GET_DEVICE_CODE(id));
2230 + * struct nand_device_type_info - Information about a NAND Flash type.
2232 + * @name: A human-readable name for this type.
2233 + * @table: The device info table for this type.
2236 +struct nand_device_type_info {
2237 + struct nand_device_info *table;
2242 + * A table that maps manufacturer IDs to device information tables.
2245 +static struct nand_device_type_info nand_device_type_directory[] =
2247 + {nand_device_info_table_type_2, "Type 2" },
2248 + {nand_device_info_table_large_mlc, "Large MLC"},
2249 + {nand_device_info_table_type_7, "Type 7" },
2250 + {nand_device_info_table_type_8, "Type 8" },
2251 + {nand_device_info_table_type_9, "Type 9" },
2252 + {nand_device_info_table_type_10, "Type 10" },
2253 + {nand_device_info_table_type_11, "Type 11" },
2254 + {nand_device_info_table_type_15, "Type 15" },
2255 + {nand_device_info_table_bch_ecc12, "BCH ECC12"},
2260 + * struct nand_device_mfr_info - Information about a NAND Flash manufacturer.
2262 + * @id: The value of the first NAND Flash ID byte, which identifies the
2264 + * @fn: A pointer to a function to use for identifying devices from the
2265 + * given manufacturer.
2268 +struct nand_device_mfr_info {
2270 + struct nand_device_info *(*fn)(const uint8_t id[]);
2274 + * A table that maps manufacturer IDs to device information tables.
2277 +static struct nand_device_mfr_info nand_device_mfr_directory[] =
2280 + .id = NAND_MFR_TOSHIBA,
2281 + .fn = nand_device_info_fn_toshiba,
2284 + .id = NAND_MFR_SAMSUNG,
2285 + .fn = nand_device_info_fn_samsung,
2288 + .id = NAND_MFR_FUJITSU,
2292 + .id = NAND_MFR_NATIONAL,
2296 + .id = NAND_MFR_RENESAS,
2300 + .id = NAND_MFR_STMICRO,
2301 + .fn = nand_device_info_fn_stmicro,
2304 + .id = NAND_MFR_HYNIX,
2305 + .fn = nand_device_info_fn_hynix,
2308 + .id = NAND_MFR_MICRON,
2309 + .fn = nand_device_info_fn_micron,
2312 + .id = NAND_MFR_AMD,
2316 + .id = NAND_MFR_SANDISK,
2317 + .fn = nand_device_info_fn_sandisk,
2320 + .id = NAND_MFR_INTEL,
2321 + .fn = nand_device_info_fn_intel,
2327 + * nand_device_info_test_table - Validate a device info table.
2329 + * This function runs tests on the given device info table to check that it
2330 + * meets the current assumptions.
2333 +static void nand_device_info_test_table(
2334 + struct nand_device_info *table, const char * name)
2339 + uint8_t device_code;
2341 + /* Loop over entries in this table. */
2343 + for (i = 0; !table[i].end_of_table; i++) {
2345 + /* Get discriminating attributes of the current device. */
2347 + mfr_code = table[i].manufacturer_code;
2348 + device_code = table[i].device_code;
2350 + /* Compare with the remaining devices in this table. */
2352 + for (j = i + 1; !table[j].end_of_table; j++) {
2353 + if ((mfr_code == table[j].manufacturer_code) &&
2354 + (device_code == table[j].device_code))
2365 + "\n== NAND Flash device info table failed validity check ==\n");
2367 + printk(KERN_EMERG "\nDevice Info Table: %s\n", name);
2368 + printk(KERN_EMERG "\nTable Index %u\n", i);
2369 + nand_device_print_info(table + i);
2370 + printk(KERN_EMERG "\nTable Index %u\n", j);
2371 + nand_device_print_info(table + j);
2372 + printk(KERN_EMERG "\n");
2379 + * nand_device_info_test_data - Test the NAND Flash device data.
2382 +static void nand_device_info_test_data(void)
2387 + for (i = 0; nand_device_type_directory[i].name; i++) {
2388 + nand_device_info_test_table(
2389 + nand_device_type_directory[i].table,
2390 + nand_device_type_directory[i].name);
2395 +struct nand_device_info *nand_device_get_info(const uint8_t id[])
2398 + uint8_t mfr_id = ID_GET_MFR_CODE(id);
2399 + struct nand_device_info *(*fn)(const uint8_t id[]) = 0;
2401 + /* Test the data. */
2403 + nand_device_info_test_data();
2405 + /* Look for information about this manufacturer. */
2407 + for (i = 0; nand_device_mfr_directory[i].id; i++) {
2408 + if (nand_device_mfr_directory[i].id == mfr_id) {
2409 + fn = nand_device_mfr_directory[i].fn;
2418 + * If control arrives here, we found both a table of device information,
2419 + * and a function we can use to identify the current device. Attempt to
2420 + * identify the device and return the result.
2426 diff --git a/drivers/mtd/nand/nand_device_info.h b/drivers/mtd/nand/nand_device_info.h
2427 new file mode 100644
2428 index 0000000..9b7923a
2430 +++ b/drivers/mtd/nand/nand_device_info.h
2433 + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
2437 + * The code contained herein is licensed under the GNU General Public
2438 + * License. You may obtain a copy of the GNU General Public License
2439 + * Version 2 or later at the following locations:
2441 + * http://www.opensource.org/licenses/gpl-license.html
2442 + * http://www.gnu.org/copyleft/gpl.html
2444 +#ifndef __DRIVERS_NAND_DEVICE_INFO_H
2445 +#define __DRIVERS_NAND_DEVICE_INFO_H
2448 + * The number of ID bytes to read from the NAND Flash device and hand over to
2449 + * the identification system.
2452 +#define NAND_DEVICE_ID_BYTE_COUNT (6)
2459 + * The number of ID bytes to read from the NAND Flash device and hand over to
2460 + * the identification system.
2463 +enum nand_device_cell_technology {
2464 + NAND_DEVICE_CELL_TECH_SLC = 0,
2465 + NAND_DEVICE_CELL_TECH_MLC = 1,
2469 + * struct nand_device_info - Information about a single NAND Flash device.
2471 + * This structure contains all the *essential* information about a NAND Flash
2472 + * device, derived from the device's data sheet. For each manufacturer, we have
2473 + * an array of these structures.
2475 + * @end_of_table: If true, marks the end of a table of device
2477 + * @manufacturer_code: The manufacturer code (1st ID byte) reported by
2479 + * @device_code: The device code (2nd ID byte) reported by the
2481 + * @cell_technology: The storage cell technology.
2482 + * @chip_size_in_bytes: The total size of the storage behind a single
2483 + * chip select, in bytes. Notice that this is *not*
2484 + * necessarily the total size of the storage in a
2485 + * *package*, which may contain several chips.
2486 + * @block_size_in_pages: The number of pages in a block.
2487 + * @page_total_size_in_bytes: The total size of a page, in bytes, including
2488 + * both the data and the OOB.
2489 + * @ecc_strength_in_bits: The strength of the ECC called for by the
2490 + * manufacturer, in number of correctable bits.
2491 + * @ecc_size_in_bytes: The size of the data block over which the
2492 + * manufacturer calls for the given ECC algorithm
2494 + * @data_setup_in_ns: The data setup time, in nanoseconds. Usually the
2495 + * maximum of tDS and tWP. A negative value
2496 + * indicates this characteristic isn't known.
2497 + * @data_hold_in_ns: The data hold time, in nanoseconds. Usually the
2498 + * maximum of tDH, tWH and tREH. A negative value
2499 + * indicates this characteristic isn't known.
2500 + * @address_setup_in_ns: The address setup time, in nanoseconds. Usually
2501 + * the maximum of tCLS, tCS and tALS. A negative
2502 + * value indicates this characteristic isn't known.
2503 + * @gpmi_sample_delay_in_ns: A GPMI-specific timing parameter. A negative
2504 + * value indicates this characteristic isn't known.
2505 + * @tREA_in_ns: tREA, in nanoseconds, from the data sheet. A
2506 + * negative value indicates this characteristic
2508 + * @tRLOH_in_ns: tRLOH, in nanoseconds, from the data sheet. A
2509 + * negative value indicates this characteristic
2511 + * @tRHOH_in_ns: tRHOH, in nanoseconds, from the data sheet. A
2512 + * negative value indicates this characteristic
2516 +struct nand_device_info {
2518 + /* End of table marker */
2520 + bool end_of_table;
2522 + /* Manufacturer and Device codes */
2524 + uint8_t manufacturer_code;
2525 + uint8_t device_code;
2529 + enum nand_device_cell_technology cell_technology;
2533 + uint64_t chip_size_in_bytes;
2534 + uint32_t block_size_in_pages;
2535 + uint16_t page_total_size_in_bytes;
2539 + uint8_t ecc_strength_in_bits;
2540 + uint16_t ecc_size_in_bytes;
2544 + int8_t data_setup_in_ns;
2545 + int8_t data_hold_in_ns;
2546 + int8_t address_setup_in_ns;
2547 + int8_t gpmi_sample_delay_in_ns;
2548 + int8_t tREA_in_ns;
2549 + int8_t tRLOH_in_ns;
2550 + int8_t tRHOH_in_ns;
2554 + const char *description;
2559 + * nand_device_get_info - Get info about a device based on ID bytes.
2561 + * @id_bytes: An array of NAND_DEVICE_ID_BYTE_COUNT ID bytes retrieved from the
2562 + * NAND Flash device.
2565 +struct nand_device_info *nand_device_get_info(const uint8_t id_bytes[]);
2568 + * nand_device_print_info - Prints information about a NAND Flash device.
2570 + * @info A pointer to a NAND Flash device information structure.
2573 +void nand_device_print_info(struct nand_device_info *info);
2576 diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
2577 index 3fd4220..e4be857 100644
2578 --- a/drivers/mtd/nand/nand_ids.c
2579 +++ b/drivers/mtd/nand/nand_ids.c
2580 @@ -108,6 +108,9 @@ struct nand_flash_dev nand_flash_ids[] = {
2581 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
2582 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
2584 + /* 32 Gigabit ,only use 2G due to the linux mtd limitation*/
2585 + {"NAND 4GiB 3,3V 8-bit", 0xD7, 0, 2048, 0, LP_OPTIONS},
2588 * Renesas AND 1 Gigabit. Those chips do not support extended id and
2589 * have a strange page/block layout ! The chosen minimum erasesize is
2590 @@ -138,5 +141,8 @@ struct nand_manufacturers nand_manuf_ids[] = {
2591 {NAND_MFR_HYNIX, "Hynix"},
2592 {NAND_MFR_MICRON, "Micron"},
2593 {NAND_MFR_AMD, "AMD"},
2594 + {NAND_MFR_SANDISK, "SanDisk"} ,
2595 + {NAND_MFR_INTEL, "Intel"} ,
2599 diff --git a/include/asm-arm/arch-mx25/mxc_nand.h b/include/asm-arm/arch-mx25/mxc_nand.h
2600 index 20a146c..9b2eec6 100644
2601 --- a/include/asm-arm/arch-mx25/mxc_nand.h
2602 +++ b/include/asm-arm/arch-mx25/mxc_nand.h
2604 == NAND_PAGESIZE_4KB)
2605 #define IS_LARGE_PAGE_NAND ((mtd->writesize / info->num_of_intlv) > 512)
2607 +#define GET_NAND_OOB_SIZE (mtd->oobsize / info->num_of_intlv)
2608 #define NAND_PAGESIZE_2KB 2048
2609 #define NAND_PAGESIZE_4KB 4096
2610 #define NAND_MAX_PAGESIZE 4096
2611 @@ -94,16 +95,21 @@ do { \
2613 #define NFC_SET_NFMS(v) \
2616 if (((v) & (1 << NFMS_NF_PG_SZ))) { \
2617 if (IS_2K_PAGE_NAND) { \
2618 + (NFMS |= 0x00000100); \
2619 + (NFMS &= ~0x00000200); \
2620 NFC_SET_SPAS(NFC_SPAS_64); \
2621 } else if (IS_4K_PAGE_NAND) { \
2622 - NFC_SET_SPAS(NFC_SPAS_128); \
2623 + (NFMS &= ~0x00000100); \
2624 + (NFMS |= 0x00000200); \
2625 + GET_NAND_OOB_SIZE == 128 ? \
2626 + NFC_SET_SPAS(NFC_SPAS_128) : \
2627 + NFC_SET_SPAS(NFC_SPAS_218); \
2629 - NFC_SET_SPAS(NFC_SPAS_16); \
2630 + printk(KERN_ERR "Err for setting page/oob size"); \
2632 - NFC_SET_ECC_MODE(NFC_SPAS_128); \
2633 + NFC_SET_ECC_MODE(GET_NAND_OOB_SIZE >> 1); \
2637 diff --git a/include/asm-arm/arch-mx35/mxc_nand.h b/include/asm-arm/arch-mx35/mxc_nand.h
2638 index 047b232..5946703 100644
2639 --- a/include/asm-arm/arch-mx35/mxc_nand.h
2640 +++ b/include/asm-arm/arch-mx35/mxc_nand.h
2642 == NAND_PAGESIZE_4KB)
2643 #define IS_LARGE_PAGE_NAND ((mtd->writesize / info->num_of_intlv) > 512)
2645 +#define GET_NAND_OOB_SIZE (mtd->oobsize / info->num_of_intlv)
2647 #define NAND_PAGESIZE_2KB 2048
2648 #define NAND_PAGESIZE_4KB 4096
2650 @@ -93,16 +95,21 @@ do { \
2652 #define NFC_SET_NFMS(v) \
2655 if (((v) & (1 << NFMS_NF_PG_SZ))) { \
2656 if (IS_2K_PAGE_NAND) { \
2657 + (NFMS |= 0x00000100); \
2658 + (NFMS &= ~0x00000200); \
2659 NFC_SET_SPAS(NFC_SPAS_64); \
2660 } else if (IS_4K_PAGE_NAND) { \
2661 - NFC_SET_SPAS(NFC_SPAS_128); \
2662 + (NFMS &= ~0x00000100); \
2663 + (NFMS |= 0x00000200); \
2664 + GET_NAND_OOB_SIZE == 128 ? \
2665 + NFC_SET_SPAS(NFC_SPAS_128) : \
2666 + NFC_SET_SPAS(NFC_SPAS_218); \
2668 - NFC_SET_SPAS(NFC_SPAS_16); \
2669 + printk(KERN_ERR "Err for setting page/oob size"); \
2671 - NFC_SET_ECC_MODE(NFC_SPAS_128); \
2672 + NFC_SET_ECC_MODE(GET_NAND_OOB_SIZE >> 1); \
2676 diff --git a/include/configs/mx35_3stack.h b/include/configs/mx35_3stack.h
2677 index f0d3d63..b2fb714 100644
2678 --- a/include/configs/mx35_3stack.h
2679 +++ b/include/configs/mx35_3stack.h
2681 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
2683 /* Address and size of Redundant Environment Sector */
2684 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
2685 +#define CONFIG_ENV_OFFSET_REDUND (2 * 1024 * 1024)
2686 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
2691 #if defined(CONFIG_FSL_ENV_IN_NAND)
2692 #define CONFIG_ENV_IS_IN_NAND 1
2693 - #define CONFIG_ENV_OFFSET (768 * 1024)
2694 + #define CONFIG_ENV_OFFSET (1024 * 1024)
2695 #elif defined(CONFIG_FSL_ENV_IS_IN_FLASH)
2696 #define CONFIG_ENV_IS_IN_FLASH 1
2698 diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
2699 index 7d5196a..ea90961 100644
2700 --- a/include/linux/mtd/nand.h
2701 +++ b/include/linux/mtd/nand.h
2702 @@ -437,6 +437,8 @@ struct nand_chip {
2703 #define NAND_MFR_HYNIX 0xad
2704 #define NAND_MFR_MICRON 0x2c
2705 #define NAND_MFR_AMD 0x01
2706 +#define NAND_MFR_SANDISK 0x45
2707 +#define NAND_MFR_INTEL 0x89
2710 * struct nand_flash_dev - NAND Flash Device ID Structure