patches/0068-ENGR00119591-Fix-SPI-NOR-reset-issue.patch

   1 From 5c5128b60555aa6a793eac9e507d5c984bd5f3ec Mon Sep 17 00:00:00 2001
   2 From: Lily Zhang <r58066@freescale.com>
   3 Date: Fri, 25 Dec 2009 16:21:56 +0800
   4 Subject: [PATCH] ENGR00119591 Fix SPI-NOR reset issue
   5
   6 Add the workaround for ENGcm09397: reconfigure eCSPI SS signal
   7 as GPIO before reset.
   8
   9 Signed-off-by: Lily Zhang <r58066@freescale.com>
  10 ---
  11  cpu/arm_cortexa8/mx51/interrupts.c |    9 +++++++++
  12  1 files changed, 9 insertions(+), 0 deletions(-)
  13
  14 diff --git a/cpu/arm_cortexa8/mx51/interrupts.c b/cpu/arm_cortexa8/mx51/interrupts.c
  15 index 9758bef..5212a42 100644
  16 --- a/cpu/arm_cortexa8/mx51/interrupts.c
  17 +++ b/cpu/arm_cortexa8/mx51/interrupts.c
  18 @@ -24,6 +24,7 @@
  19   */
  20
  21  #include <common.h>
  22 +#include <asm/io.h>
  23  #include <asm/arch/mx51.h>
  24
  25  /* nothing really to do with interrupts, just starts up a counter. */
  26 @@ -34,5 +35,13 @@ int interrupt_init(void)
  27
  28  void reset_cpu(ulong addr)
  29  {
  30 +       /* workaround for ENGcm09397 - Fix SPI NOR reset issue*/
  31 +       /* de-select SS0 of instance: eCSPI1 */
  32 +       writel(0x3, IOMUXC_BASE_ADDR + 0x218);
  33 +       writel(0x85, IOMUXC_BASE_ADDR + 0x608);
  34 +       /* de-select SS1 of instance: ecspi1 */
  35 +       writel(0x3, IOMUXC_BASE_ADDR + 0x21C);
  36 +       writel(0x85, IOMUXC_BASE_ADDR + 0x60C);
  37 +
  38         __REG16(WDOG1_BASE_ADDR) = 4;
  39  }
  40 --
  41 1.5.4.4
  42