imx:mx6ul add dram spl configuration and header file

1. Define two structures mx6ul_iomux_ddr_regs and mx6ul_iomux_grp_regs.
2. Add a new function mx6ul_dram_iocfg to configure dram io.
3. Refactor MMDC1 macro, discard "#ifdef CONFIG_MX6SX". Since
   only mmdc0 channel exists on i.MX6SX/UL, redefine MMDC1 macro support
   runtime check, but not hardcoding #ifdef macros.
4. Introduce mx6ul-ddr.h, which includes the register address for DRAM
   IO configuration.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 012eb078c3d11f968c26c949072787b663aad82d..135256a969ae69151c1c3ffd4edd03986858eff5 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -71,6 +71,50 @@ void mx6sx_dram_iocfg(unsigned width,
 }
 #endif
 
+#ifdef CONFIG_MX6UL
+void mx6ul_dram_iocfg(unsigned width,
+                     const struct mx6ul_iomux_ddr_regs *ddr,
+                     const struct mx6ul_iomux_grp_regs *grp)
+{
+       struct mx6ul_iomux_ddr_regs *mx6_ddr_iomux;
+       struct mx6ul_iomux_grp_regs *mx6_grp_iomux;
+
+       mx6_ddr_iomux = (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
+       mx6_grp_iomux = (struct mx6ul_iomux_grp_regs *)MX6UL_IOM_GRP_BASE;
+
+       /* DDR IO TYPE */
+       writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
+       writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
+
+       /* CLOCK */
+       writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
+
+       /* ADDRESS */
+       writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
+       writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
+       writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
+
+       /* Control */
+       writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
+       writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
+       writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
+       writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
+       writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
+
+       /* Data Strobes */
+       writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
+       writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
+       writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
+
+       /* Data */
+       writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
+       writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
+       writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
+       writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
+       writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
+}
+#endif
+
 #if defined(CONFIG_SOC_MX6QDL) || defined(CONFIG_SOC_MX6Q) || defined(CONFIG_SOC_MX6D)
 /* Configure MX6DQ mmdc iomux */
 void mx6dq_dram_iocfg(unsigned width,
@@ -243,19 +287,17 @@ void mx6sdl_dram_iocfg(unsigned width,
  */
 #define MR(val, ba, cmd, cs1) \
        ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
-#ifdef CONFIG_SOC_MX6SX
-#define MMDC1(entry, value)    do {} while (0)
-#else
-#define MMDC1(entry, value) do { mmdc1->entry = value; } while (0)
-#endif
+#define MMDC1(entry, value) do {                                         \
+       if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL))   \
+               mmdc1->entry = value;                                     \
+       } while (0)
+
 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
                  const struct mx6_mmdc_calibration *calib,
                  const struct mx6_ddr3_cfg *ddr3_cfg)
 {
        volatile struct mmdc_p_regs *mmdc0;
-#ifndef CONFIG_SOC_MX6SX
        volatile struct mmdc_p_regs *mmdc1;
-#endif
        u32 val;
        u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
        u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
@@ -270,9 +312,8 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
        u16 mem_speed = ddr3_cfg->mem_speed;
 
        mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
-#ifndef CONFIG_SOC_MX6SX
-       mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
-#endif
+       if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL))
+               mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
 
        /* Limit mem_speed for MX6D/MX6Q */
        if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {

diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index 6eaff95ad0e010745c88d406a58e46e57550fef8..2a545c4fa0b08d07b8468f7ea9d1daa96705d37a 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -16,7 +16,11 @@
 #ifdef CONFIG_SOC_MX6SX
 #include "mx6sx-ddr.h"
 #else
+#ifdef CONFIG_SOC_MX6UL
+#include "mx6ul-ddr.h"
+#else
 #error "Please select cpu"
+#endif /* CONFIG_SOC_MX6UL */
 #endif /* CONFIG_SOC_MX6SX */
 #endif /* CONFIG_SOC_MX6DL or CONFIG_SOC_MX6S */
 #endif /* CONFIG_SOC_MX6Q */
@@ -62,6 +66,44 @@ struct mmdc_p_regs {
        u32 mpmur0;
 };
 
+#define MX6UL_IOM_DDR_BASE     0x020e0200
+struct mx6ul_iomux_ddr_regs {
+       u32 res1[17];
+       u32 dram_dqm0;
+       u32 dram_dqm1;
+       u32 dram_ras;
+       u32 dram_cas;
+       u32 dram_cs0;
+       u32 dram_cs1;
+       u32 dram_sdwe_b;
+       u32 dram_odt0;
+       u32 dram_odt1;
+       u32 dram_sdba0;
+       u32 dram_sdba1;
+       u32 dram_sdba2;
+       u32 dram_sdcke0;
+       u32 dram_sdcke1;
+       u32 dram_sdclk_0;
+       u32 dram_sdqs0;
+       u32 dram_sdqs1;
+       u32 dram_reset;
+};
+
+#define MX6UL_IOM_GRP_BASE     0x020e0400
+struct mx6ul_iomux_grp_regs {
+       u32 res1[36];
+       u32 grp_addds;
+       u32 grp_ddrmode_ctl;
+       u32 grp_b0ds;
+       u32 grp_ddrpk;
+       u32 grp_ctlds;
+       u32 grp_b1ds;
+       u32 grp_ddrhys;
+       u32 grp_ddrpke;
+       u32 grp_ddrmode;
+       u32 grp_ddr_type;
+};
+
 #define MX6SX_IOM_DDR_BASE     0x020e0200
 struct mx6sx_iomux_ddr_regs {
        u32 res1[59];
@@ -290,6 +332,9 @@ void mx6sdl_dram_iocfg(unsigned width,
 void mx6sx_dram_iocfg(unsigned width,
                      const struct mx6sx_iomux_ddr_regs *,
                      const struct mx6sx_iomux_grp_regs *);
+void mx6ul_dram_iocfg(unsigned width,
+                     const struct mx6ul_iomux_ddr_regs *,
+                     const struct mx6ul_iomux_grp_regs *);
 
 /* configure mx6 mmdc registers */
 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,

diff --git a/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h b/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h
new file mode 100644 (file)
index 0000000..ed11c4b
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX6UL_DDR_H__
+#define __ASM_ARCH_MX6UL_DDR_H__
+
+#ifndef CONFIG_MX6UL
+#error "wrong CPU"
+#endif
+
+#define MX6_IOM_DRAM_DQM0      0x020e0244
+#define MX6_IOM_DRAM_DQM1      0x020e0248
+
+#define MX6_IOM_DRAM_RAS       0x020e024c
+#define MX6_IOM_DRAM_CAS       0x020e0250
+#define MX6_IOM_DRAM_CS0       0x020e0254
+#define MX6_IOM_DRAM_CS1       0x020e0258
+#define MX6_IOM_DRAM_SDWE_B    0x020e025c
+#define MX6_IOM_DRAM_SDODT0    0x020e0260
+#define MX6_IOM_DRAM_SDODT1    0x020e0264
+#define MX6_IOM_DRAM_SDBA0     0x020e0268
+#define MX6_IOM_DRAM_SDBA1     0x020e026c
+#define MX6_IOM_DRAM_SDBA2     0x020e0270
+#define MX6_IOM_DRAM_SDCKE0    0x020e0274
+#define MX6_IOM_DRAM_SDCKE1    0x020e0278
+#define MX6_IOM_DRAM_SDCLK_0   0x020e027c
+#define MX6_IOM_DRAM_SDQS0     0x020e0280
+#define MX6_IOM_DRAM_SDQS1     0x020e0284
+#define MX6_IOM_DRAM_RESET     0x020e0288
+
+#define MX6_IOM_GRP_ADDDS      0x020e0490
+#define MX6_IOM_DDRMODE_CTL    0x020e0494
+#define MX6_IOM_GRP_B0DS       0x020e0498
+#define MX6_IOM_GRP_DDRPK      0x020e049c
+#define MX6_IOM_GRP_CTLDS      0x020e04a0
+#define MX6_IOM_GRP_B1DS       0x020e04a4
+#define MX6_IOM_GRP_DDRHYS     0x020e04a8
+#define MX6_IOM_GRP_DDRPKE     0x020e04ac
+#define MX6_IOM_GRP_DDRMODE    0x020e04b0
+#define MX6_IOM_GRP_DDR_TYPE   0x020e04b4
+
+#endif /*__ASM_ARCH_MX6SX_DDR_H__ */