Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
int print_cpuinfo(void)
{
int print_cpuinfo(void)
{
- struct mx28_spl_data *data = (struct mx28_spl_data *)
- ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf);
+ struct mxs_spl_data *data = (struct mxs_spl_data *)
+ ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
printf("CPU: Freescale i.MX%s rev%s at %d MHz\n",
get_cpu_type(),
printf("CPU: Freescale i.MX%s rev%s at %d MHz\n",
get_cpu_type(),
int mx28_dram_init(void)
{
int mx28_dram_init(void)
{
- struct mx28_spl_data *data = (struct mx28_spl_data *)
- ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf);
+ struct mxs_spl_data *data = (struct mxs_spl_data *)
+ ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
if (data->mem_dram_size == 0) {
printf("MX28:\n"
if (data->mem_dram_size == 0) {
printf("MX28:\n"
void early_delay(int delay);
void early_delay(int delay);
-void mx28_power_init(void);
+void mxs_power_init(void);
#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
-void mx28_power_wait_pswitch(void);
+void mxs_power_wait_pswitch(void);
-static inline void mx28_power_wait_pswitch(void) { }
+static inline void mxs_power_wait_pswitch(void) { }
-void mx28_mem_init(void);
-uint32_t mx28_mem_get_size(void);
+void mxs_mem_init(void);
+uint32_t mxs_mem_get_size(void);
-void mx28_lradc_init(void);
-void mx28_lradc_enable_batt_measurement(void);
+void mxs_lradc_init(void);
+void mxs_lradc_enable_batt_measurement(void);
#endif /* __M28_INIT_H__ */
#endif /* __M28_INIT_H__ */
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
/*
* This delay function is intended to be used only in early stage of boot, where
/*
* This delay function is intended to be used only in early stage of boot, where
MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
};
MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
};
-uint8_t mx28_get_bootmode_index(void)
+uint8_t mxs_get_bootmode_index(void)
{
uint8_t bootmode = 0;
int i;
{
uint8_t bootmode = 0;
int i;
-void mx28_common_spl_init(const iomux_cfg_t *iomux_setup,
+void mxs_common_spl_init(const iomux_cfg_t *iomux_setup,
const unsigned int iomux_size)
{
const unsigned int iomux_size)
{
- struct mx28_spl_data *data = (struct mx28_spl_data *)
- ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf);
- uint8_t bootmode = mx28_get_bootmode_index();
+ struct mxs_spl_data *data = (struct mxs_spl_data *)
+ ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
+ uint8_t bootmode = mxs_get_bootmode_index();
mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size);
mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size);
- mx28_mem_init();
- data->mem_dram_size = mx28_mem_get_size();
+ mxs_mem_init();
+ data->mem_dram_size = mxs_mem_get_size();
data->boot_mode_idx = bootmode;
data->boot_mode_idx = bootmode;
- mx28_power_wait_pswitch();
+ mxs_power_wait_pswitch();
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-void mx28_lradc_init(void)
+void mxs_lradc_init(void)
{
struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
{
struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
LRADC_CTRL4_LRADC6SELECT_CHANNEL10);
}
LRADC_CTRL4_LRADC6SELECT_CHANNEL10);
}
-void mx28_lradc_enable_batt_measurement(void)
+void mxs_lradc_enable_batt_measurement(void)
{
struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
{
struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
#include <asm/arch/iomux-mx28.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux-mx28.h>
#include <asm/arch/imx-regs.h>
static uint32_t mx28_dram_vals[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000,
static uint32_t mx28_dram_vals[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00010001
};
0x00000000, 0x00010001
};
-void __mx28_adjust_memory_params(uint32_t *dram_vals)
+void __mxs_adjust_memory_params(uint32_t *dram_vals)
-void mx28_adjust_memory_params(uint32_t *dram_vals)
- __attribute__((weak, alias("__mx28_adjust_memory_params")));
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+ __attribute__((weak, alias("__mxs_adjust_memory_params")));
void init_mx28_200mhz_ddr2(void)
{
int i;
void init_mx28_200mhz_ddr2(void)
{
int i;
- mx28_adjust_memory_params(mx28_dram_vals);
+ mxs_adjust_memory_params(mx28_dram_vals);
for (i = 0; i < ARRAY_SIZE(mx28_dram_vals); i++)
writel(mx28_dram_vals[i], MXS_DRAM_BASE + (4 * i));
}
for (i = 0; i < ARRAY_SIZE(mx28_dram_vals); i++)
writel(mx28_dram_vals[i], MXS_DRAM_BASE + (4 * i));
}
-void mx28_mem_init_clock(void)
+void mxs_mem_init_clock(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
-void mx28_mem_setup_cpu_and_hbus(void)
+void mxs_mem_setup_cpu_and_hbus(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
-void mx28_mem_setup_vdda(void)
+void mxs_mem_setup_vdda(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
&power_regs->hw_power_vddactrl);
}
&power_regs->hw_power_vddactrl);
}
-void mx28_mem_setup_vddd(void)
+void mxs_mem_setup_vddd(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
&power_regs->hw_power_vdddctrl);
}
&power_regs->hw_power_vdddctrl);
}
-uint32_t mx28_mem_get_size(void)
+uint32_t mxs_mem_get_size(void)
{
uint32_t sz, da;
uint32_t *vt = (uint32_t *)0x20;
{
uint32_t sz, da;
uint32_t *vt = (uint32_t *)0x20;
-void mx28_mem_init(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
/*
* Configure the DRAM registers
/*
* Configure the DRAM registers
while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
;
while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
;
- mx28_mem_setup_cpu_and_hbus();
+ mxs_mem_setup_cpu_and_hbus();
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-void mx28_power_clock2xtal(void)
+void mxs_power_clock2xtal(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
&clkctrl_regs->hw_clkctrl_clkseq_set);
}
&clkctrl_regs->hw_clkctrl_clkseq_set);
}
-void mx28_power_clock2pll(void)
+void mxs_power_clock2pll(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
CLKCTRL_CLKSEQ_BYPASS_CPU);
}
CLKCTRL_CLKSEQ_BYPASS_CPU);
}
-void mx28_power_clear_auto_restart(void)
+void mxs_power_clear_auto_restart(void)
{
struct mxs_rtc_regs *rtc_regs =
(struct mxs_rtc_regs *)MXS_RTC_BASE;
{
struct mxs_rtc_regs *rtc_regs =
(struct mxs_rtc_regs *)MXS_RTC_BASE;
-void mx28_power_set_linreg(void)
+void mxs_power_set_linreg(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
}
POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
}
-int mx28_get_batt_volt(void)
+int mxs_get_batt_volt(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
-int mx28_is_batt_ready(void)
+int mxs_is_batt_ready(void)
- return (mx28_get_batt_volt() >= 3600);
+ return (mxs_get_batt_volt() >= 3600);
-int mx28_is_batt_good(void)
+int mxs_is_batt_good(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
- uint32_t volt = mx28_get_batt_volt();
+ uint32_t volt = mxs_get_batt_volt();
if ((volt >= 2400) && (volt <= 4300))
return 1;
if ((volt >= 2400) && (volt <= 4300))
return 1;
- volt = mx28_get_batt_volt();
+ volt = mxs_get_batt_volt();
if (volt >= 3500)
return 0;
if (volt >= 3500)
return 0;
-void mx28_power_setup_5v_detect(void)
+void mxs_power_setup_5v_detect(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
POWER_5VCTRL_PWRUP_VBUS_CMPS);
}
POWER_5VCTRL_PWRUP_VBUS_CMPS);
}
-void mx28_src_power_init(void)
+void mxs_src_power_init(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
}
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
}
-void mx28_power_init_4p2_params(void)
+void mxs_power_init_4p2_params(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
}
0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
}
-void mx28_enable_4p2_dcdc_input(int xfer)
+void mxs_enable_4p2_dcdc_input(int xfer)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
POWER_CTRL_ENIRQ_VDD5V_DROOP);
}
POWER_CTRL_ENIRQ_VDD5V_DROOP);
}
-void mx28_power_init_4p2_regulator(void)
+void mxs_power_init_4p2_regulator(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
* gradually to avoid large inrush current from the 5V cable which can
* cause transients/problems
*/
* gradually to avoid large inrush current from the 5V cable which can
* cause transients/problems
*/
- mx28_enable_4p2_dcdc_input(0);
+ mxs_enable_4p2_dcdc_input(0);
if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
/*
if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
/*
writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
}
writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
}
-void mx28_power_init_dcdc_4p2_source(void)
+void mxs_power_init_dcdc_4p2_source(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
- mx28_enable_4p2_dcdc_input(1);
+ mxs_enable_4p2_dcdc_input(1);
if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
clrbits_le32(&power_regs->hw_power_dcdc4p2,
if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
clrbits_le32(&power_regs->hw_power_dcdc4p2,
-void mx28_power_enable_4p2(void)
+void mxs_power_enable_4p2(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
setbits_le32(&power_regs->hw_power_vddioctrl,
POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
setbits_le32(&power_regs->hw_power_vddioctrl,
POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
- mx28_power_init_4p2_params();
- mx28_power_init_4p2_regulator();
+ mxs_power_init_4p2_params();
+ mxs_power_init_4p2_regulator();
/* Shutdown battery (none present) */
/* Shutdown battery (none present) */
- if (!mx28_is_batt_ready()) {
+ if (!mxs_is_batt_ready()) {
clrbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_BO_MASK);
writel(POWER_CTRL_DCDC4P2_BO_IRQ,
clrbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_BO_MASK);
writel(POWER_CTRL_DCDC4P2_BO_IRQ,
&power_regs->hw_power_ctrl_clr);
}
&power_regs->hw_power_ctrl_clr);
}
- mx28_power_init_dcdc_4p2_source();
+ mxs_power_init_dcdc_4p2_source();
writel(vdddctrl, &power_regs->hw_power_vdddctrl);
early_delay(20);
writel(vdddctrl, &power_regs->hw_power_vdddctrl);
early_delay(20);
&power_regs->hw_power_charge_clr);
}
&power_regs->hw_power_charge_clr);
}
-void mx28_boot_valid_5v(void)
+void mxs_boot_valid_5v(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
&power_regs->hw_power_ctrl_clr);
writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
&power_regs->hw_power_ctrl_clr);
- mx28_power_enable_4p2();
+ mxs_power_enable_4p2();
-void mx28_powerdown(void)
+void mxs_powerdown(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
&power_regs->hw_power_reset);
}
&power_regs->hw_power_reset);
}
-void mx28_batt_boot(void)
+void mxs_batt_boot(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
clrsetbits_le32(&power_regs->hw_power_minpwr,
POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
clrsetbits_le32(&power_regs->hw_power_minpwr,
POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
- mx28_power_set_linreg();
+ mxs_power_set_linreg();
clrbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
clrbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
}
0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
}
-void mx28_handle_5v_conflict(void)
+void mxs_handle_5v_conflict(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
tmp = readl(&power_regs->hw_power_sts);
if (tmp & POWER_STS_VDDIO_BO) {
tmp = readl(&power_regs->hw_power_sts);
if (tmp & POWER_STS_VDDIO_BO) {
break;
}
if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
break;
}
if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
break;
}
if (tmp & POWER_STS_PSWITCH_MASK) {
break;
}
if (tmp & POWER_STS_PSWITCH_MASK) {
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
* but their implementation always returns 1 so we omit it here.
*/
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
* but their implementation always returns 1 so we omit it here.
*/
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
return;
}
early_delay(1000);
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
return;
}
early_delay(1000);
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
- mx28_handle_5v_conflict();
+ mxs_handle_5v_conflict();
-void mx28_init_batt_bo(void)
+void mxs_init_batt_bo(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
}
writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
}
-void mx28_switch_vddd_to_dcdc_source(void)
+void mxs_switch_vddd_to_dcdc_source(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
POWER_VDDDCTRL_DISABLE_STEPPING);
}
POWER_VDDDCTRL_DISABLE_STEPPING);
}
-void mx28_power_configure_power_source(void)
+void mxs_power_configure_power_source(void)
{
int batt_ready, batt_good;
struct mxs_power_regs *power_regs =
{
int batt_ready, batt_good;
struct mxs_power_regs *power_regs =
struct mxs_lradc_regs *lradc_regs =
(struct mxs_lradc_regs *)MXS_LRADC_BASE;
struct mxs_lradc_regs *lradc_regs =
(struct mxs_lradc_regs *)MXS_LRADC_BASE;
- batt_ready = mx28_is_batt_ready();
+ batt_ready = mxs_is_batt_ready();
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
- batt_good = mx28_is_batt_good();
+ batt_good = mxs_is_batt_good();
if (batt_ready) {
/* 5V source detected, good battery detected. */
if (batt_ready) {
/* 5V source detected, good battery detected. */
} else {
if (batt_good) {
/* 5V source detected, low battery detceted. */
} else {
if (batt_good) {
/* 5V source detected, low battery detceted. */
clrbits_le32(&power_regs->hw_power_battmonitor,
POWER_BATTMONITOR_BATT_VAL_MASK);
}
clrbits_le32(&power_regs->hw_power_battmonitor,
POWER_BATTMONITOR_BATT_VAL_MASK);
}
}
} else {
/* 5V not detected, booting from battery. */
}
} else {
/* 5V not detected, booting from battery. */
- mx28_power_clock2pll();
- mx28_switch_vddd_to_dcdc_source();
+ mxs_switch_vddd_to_dcdc_source();
-void mx28_enable_output_rail_protection(void)
+void mxs_enable_output_rail_protection(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
POWER_VDDIOCTRL_PWDN_BRNOUT);
}
POWER_VDDIOCTRL_PWDN_BRNOUT);
}
-int mx28_get_vddio_power_source_off(void)
+int mxs_get_vddio_power_source_off(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
-int mx28_get_vddd_power_source_off(void)
+int mxs_get_vddd_power_source_off(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
-void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
+void mxs_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
cur_target *= 50; /* 50 mV step*/
cur_target += 2800; /* 2800 mV lowest */
cur_target *= 50; /* 50 mV step*/
cur_target += 2800; /* 2800 mV lowest */
- powered_by_linreg = mx28_get_vddio_power_source_off();
+ powered_by_linreg = mxs_get_vddio_power_source_off();
if (new_target > cur_target) {
if (powered_by_linreg) {
if (new_target > cur_target) {
if (powered_by_linreg) {
new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
}
new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
}
-void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
+void mxs_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
cur_target *= 25; /* 25 mV step*/
cur_target += 800; /* 800 mV lowest */
cur_target *= 25; /* 25 mV step*/
cur_target += 800; /* 800 mV lowest */
- powered_by_linreg = mx28_get_vddd_power_source_off();
+ powered_by_linreg = mxs_get_vddd_power_source_off();
if (new_target > cur_target) {
if (powered_by_linreg) {
bo_int = readl(&power_regs->hw_power_vdddctrl);
if (new_target > cur_target) {
if (powered_by_linreg) {
bo_int = readl(&power_regs->hw_power_vdddctrl);
new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
}
new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
}
-void mx28_setup_batt_detect(void)
+void mxs_setup_batt_detect(void)
- mx28_lradc_init();
- mx28_lradc_enable_batt_measurement();
+ mxs_lradc_init();
+ mxs_lradc_enable_batt_measurement();
-void mx28_power_init(void)
+void mxs_power_init(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
- mx28_power_clock2xtal();
- mx28_power_clear_auto_restart();
- mx28_power_set_linreg();
- mx28_power_setup_5v_detect();
+ mxs_power_clock2xtal();
+ mxs_power_clear_auto_restart();
+ mxs_power_set_linreg();
+ mxs_power_setup_5v_detect();
- mx28_setup_batt_detect();
+ mxs_setup_batt_detect();
- mx28_power_configure_power_source();
- mx28_enable_output_rail_protection();
+ mxs_power_configure_power_source();
+ mxs_enable_output_rail_protection();
- mx28_power_set_vddio(3300, 3150);
+ mxs_power_set_vddio(3300, 3150);
- mx28_power_set_vddd(1350, 1200);
+ mxs_power_set_vddd(1350, 1200);
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
}
#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
}
#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
-void mx28_power_wait_pswitch(void)
+void mxs_power_wait_pswitch(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
#ifdef CONFIG_SPL_BUILD
#include <asm/arch/iomux-mx28.h>
#ifdef CONFIG_SPL_BUILD
#include <asm/arch/iomux-mx28.h>
-void mx28_common_spl_init(const iomux_cfg_t *iomux_setup,
+void mxs_common_spl_init(const iomux_cfg_t *iomux_setup,
const unsigned int iomux_size);
#endif
const unsigned int iomux_size);
#endif
{ 0x00, 0x00, "Reserved/Unknown/Wrong" },
};
{ 0x00, 0x00, "Reserved/Unknown/Wrong" },
};
uint8_t boot_mode_idx;
uint32_t mem_dram_size;
};
uint8_t boot_mode_idx;
uint32_t mem_dram_size;
};
void board_init_ll(void)
{
void board_init_ll(void)
{
- mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
+ mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
/* switch LED on */
gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
}
/* switch LED on */
gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
}
-void mx28_adjust_memory_params(uint32_t *dram_vals)
+void mxs_adjust_memory_params(uint32_t *dram_vals)
{
/*
* All address lines are routed from CPU to memory chip.
{
/*
* All address lines are routed from CPU to memory chip.
void board_init_ll(void)
{
void board_init_ll(void)
{
- mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
+ mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
void board_init_ll(void)
{
void board_init_ll(void)
{
- mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
+ mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));