+++ /dev/null
-#
-# Parts of the development effort for this project have been
-# sponsored by SIEMENS AG, Austria. Thanks to SIEMENS for
-# supporting an Open Source project!
-#
-#
-# This is at least a partial credits-file of individual people that
-# have contributed to the U-Boot project. It is sorted by name and
-# formatted to allow easy grepping and beautification by scripts.
-# The fields are: name (N), email (E), web-address (W), PGP key ID
-# and fingerprint (P), description (D), and snail-mail address (S).
-# Thanks,
-#
-# Wolfgang Denk
-#----------
-
-N: Dr. Bruno Achauer
-E: bruno@exet-ag.de
-D: Support for NetBSD (both as host and target system)
-
-N: Guillaume Alexandre
-E: guillaume.alexandre@gespac.ch
-D: Add PCIPPC6 configuration
-
-N: Pantelis Antoniou
-E: panto@intracom.gr
-D: NETVIA & NETPHONE board support, ARTOS support.
-D: Support for Silicon Turnkey eXpress XTc
-
-N: Pierre Aubert
-E: <p.aubert@staubli.com>
-D: Support for RPXClassic board
-
-N: Yuli Barcohen
-E: yuli@arabellasw.com
-D: Unified support for Motorola MPC826xADS/MPC8272ADS/PQ2FADS boards.
-D: Support for Zephyr Engineering ZPC.1900 board.
-D: Support for Interphase iSPAN boards.
-D: Support for Analogue&Micro Adder boards.
-D: Support for Analogue&Micro Rattler boards.
-W: http://www.arabellasw.com
-
-N: Jerry van Baren
-E: <vanbaren@cideas.com>
-D: BedBug port to 603e core (MPC82xx). Code for enhanced memory test.
-
-N: Pavel Bartusek
-E: <pba@sysgo.com>
-D: Reiserfs support
-W: http://www.elinos.com
-
-N: Andre Beaudin
-E: <andre.beaudin@colubris.com>
-D: PCMCIA, Ethernet, TFTP
-
-N: Jon Benediktsson
-E: jonb@marel.is
-D: Support for Marel V37 board
-
-N: Raphael Bossek
-E: raphael.bossek@solutions4linux.de
-D: 8xxrom-0.3.0
-
-N: Cliff Brake
-E: cliff.brake@gmail.com
-D: Port to Vibren PXA255 IDP platform
-W: http://www.vibren.com
-W: http://bec-systems.com
-
-N: Rick Bronson
-E: rick@efn.org
-D: Atmel AT91RM9200DK and NAND support
-
-N: David Brown
-E: DBrown03@harris.com
-D: Extensions to 8xxrom-0.3.0
-
-N: Oliver Brown
-E: obrown@adventnetworks.com
-D: Port to the gw8260 board
-
-N: Jonathan De Bruyne
-E: jonathan.debruyne@siemens.atea.be
-D: Port to Siemens IAD210 board
-
-N: Ken Chou
-E: kchou@ieee.org
-D: Support for A3000 SBC board
-
-N: Conn Clark
-E: clark@esteem.com
-D: ESTEEM192E support
-
-N: Magnus Damm
-E: damm@opensource.se
-D: 8xxrom
-
-N: Richard Danter
-E: richard.danter@windriver.com
-D: Support for Wind River PPMC 7xx/74xx boards
-
-N: George G. Davis
-E: gdavis@mvista.com
-D: Board ports for ADS GraphicsClient+ and Intel Assabet
-
-N: Arun Dharankar
-E: ADharankar@ATTBI.Com
-D: threads / scheduler example code
-
-N: K?ri Dav??sson
-E: kd@flaga.is
-D: FLAGA DM Support
-
-N: Wolfgang Denk
-E: wd@denx.de
-D: U-Boot initial version, continuing maintenance, ARMBoot merge
-W: http://www.denx.de
-
-N: Dan A. Dickey
-E: ddickey@charter.net
-D: FADS Support
-
-N: Mike Dunn
-E: mikedunn@newsguy.com
-D: Palmtreo680 board, docg4 nand flash driver
-
-N: Dave Ellis
-E: DGE@sixnetio.com
-D: EEPROM Speedup
-
-N: Daniel Engstr?m
-E: daniel@omicron.se
-D: x86 port, Support for sc520_cdp board
-
-N: Hayden Fraser
-E: Hayden.Fraser@freescale.com
-D: Support for ColdFire MCF5253
-W: www.freescale.com
-
-N: Dr. Wolfgang Grandegger
-E: wg@denx.de
-D: Support for Interphase 4539 T1/E1/J1 PMC, CCM, SCM boards
-W: www.denx.de
-
-N: Peter Figuli
-E: peposh@etc.sk
-D: Support for WEP EP250 (PXA) board
-
-N: Thomas Frieden
-E: ThomasF@hyperion-entertainment.com
-D: Support for AmigaOne
-
-N: Paul Gortmaker
-E: paul.gortmaker@windriver.com
-D: Support for WRS SBC8347/8349 boards
-
-N: Frank Gottschling
-E: fgottschling@eltec.de
-D: Support for ELTEC MHPC/ELPPC boards, cfb-console, i8042, SMI LynxEM
-W: www.eltec.de
-
-N: Marius Groeger
-E: mgroeger@sysgo.de
-D: MBX Support, board specific function interface, EST SBC8260 support; initial support for StrongARM (LART), ARM720TDMI (implementa A7)
-W: www.elinos.com
-
-N: Kirk Haderlie
-E: khaderlie@vividimage.com
-D: Added TFTP to 8xxrom (-> 0.3.1)
-
-N: Chris Hallinan
-E: clh@net1plus.com
-D: DHCP Support
-
-N: Anne-Sophie Harnois
-E: Anne-Sophie.Harnois@nextream.fr
-D: Port to Walnut405 board
-
-N: Andreas Heppel
-E: aheppel@sysgo.de
-D: CPU Support for MPC 75x
-
-N: Josh Huber
-E: huber@alum.wpi.edu
-D: Port to the Galileo Evaluation Board, and the MPC74xx cpu series.
-W: http://www.mclx.com/
-
-H: Stuart Hughes
-E: stuarth@lineo.com
-D: Port to MPC8260ADS board
-
-H: Rich Ireland
-E: r.ireland@computer.org
-D: FPGA device configuration driver
-
-H: Mark Jackson
-E: mpfj@mimc.co.uk
-D: Port to MIMC200 board
-
-N: Gary Jennejohn
-E: garyj@jennejohn.org
-D: Support for Samsung ARM920T S3C2400X, ARM920T "TRAB"
-W: www.denx.de
-
-N: Murray Jensen
-E: Murray.Jensen@csiro.au
-D: Initial 8260 support; GDB support
-D: Port to Cogent+Hymod boards; Hymod Board Database
-
-N: Yoo. Jonghoon
-E: yooth@ipone.co.kr
-D: Added port to the RPXlite board
-
-N: Mark Jonas
-E: mark.jonas@freescale.com
-D: Support for Freescale Total5200 platform
-W: http://www.mobilegt.com/
-
-N: Mark Jonas
-E: mark.jonas@de.bosch.com
-D: Support for MPR2 board
-
-N: Sam Song
-E: samsongshu@yahoo.com.cn
-D: Port to the RPXlite_DW board
-
-N: Brad Kemp
-E: Brad.Kemp@seranoa.com
-D: Port to Windriver ppmc8260 board
-
-N: Sangmoon Kim
-E: dogoil@etinsys.com
-D: Support for debris board
-D: Support for KVME080 board
-
-N: Frederick W. Klatt
-E: fred.klatt@windriver.com
-D: Support for Wind River SBC8540/SBC8560 boards
-
-N: Thomas Koeller
-E: tkoeller@gmx.net
-D: Port to Motorola Sandpoint 3 (MPC8240)
-
-N: Raghu Krishnaprasad
-E: Raghu.Krishnaprasad@fci.com
-D: Support for Adder-II MPC852T evaluation board
-W: http://www.forcecomputers.com
-
-N: Sergey Kubushyn
-E: ksi@koi8.net
-D: Support for various TI DaVinci based boards.
-
-N: Bernhard Kuhn
-E: bkuhn@metrowerks.com
-D Support for Coldfire CPU; Support for Motorola M5272C3 and M5282EVB boards
-
-N: Prakash Kumar
-E: prakash@embedx.com
-D Support for Intrinsyc CERF PXA250 board.
-
-N: Thomas Lange
-E: thomas@corelatus.se
-D: Support for GTH, GTH2 and dbau1x00 boards; lots of PCMCIA fixes
-
-N: The LEOX team
-E: team@leox.org
-D: Support for LEOX boards, DS164x RTC
-W: http://www.leox.org
-
-N: TsiChung Liew
-E: Tsi-Chung.Liew@freescale.com
-D: Support for ColdFire MCF523x, MCF532x, MCF5445x, MCF547x_8x
-W: www.freescale.com
-
-N: Leif Lindholm
-E: leif.lindholm@i3micro.com
-D: Support for AMD dbau1550 board.
-
-N: Stephan Linz
-E: linz@li-pro.net
-D: Support for Nios Stratix Development Kit (DK-1S10)
-D: Support for SSV ADNP/ESC1 (Nios Cyclone)
-W: http://www.li-pro.net
-
-N: Dave Liu
-E: daveliu@freescale.com
-D: Support for MPC8315, MPC832x, MPC8360, MPC837x
-W: www.freescale.com
-
-N: Raymond Lo
-E: lo@routefree.com
-D: Support for DOS partitions
-
-N: James MacAulay
-E: james.macaulay@amirix.com
-D: Suppport for Amirix AP1000
-W: www.amirix.com
-
-N: Dan Malek
-E: dan@embeddedalley.com
-D: FADSROM, the grandfather of all of this
-D: Support for Silicon Turnkey eXpress XTc
-
-N: Andrea "llandre" Marson
-E: andrea.marson@dave-tech.it
-D: Port to PPChameleonEVB board
-W: www.dave-tech.it
-
-N: Reinhard Meyer
-E: r.meyer@emk-elektronik.de
-D: Port to EMK TOP860 Module
-
-N: Jay Monkman
-E: jtm@smoothsmoothie.com
-D: EST SBC8260 support
-
-N: Frank Morauf
-E: frank.morauf@salzbrenner.com
-D: Support for Embedded Planet RPX Super Board
-
-N: David M?ller
-E: d.mueller@elsoft.ch
-D: Support for Samsung ARM920T SMDK2410 eval board
-
-N: Scott McNutt
-E: smcnutt@psyent.com
-D: Support for Altera Nios-32 CPU
-D: Support for Altera Nios-II CPU
-D: Support for Nios Cyclone Development Kit (DK-1C20)
-W: http://www.psyent.com
-
-N: Rolf Offermanns
-E: rof@sysgo.de
-D: Initial support for SSV-DNP1110, SMC91111 driver
-W: www.elinos.com
-
-N: John Otken
-E: jotken@softadvances.com
-D: Support for AMCC Luan 440SP board
-
-N: Tolunay Orkun
-E: torkun@nextio.com
-D: Support for Cogent CSB272 & CSB472 boards
-
-N: Keith Outwater
-E: keith_outwater@mvis.com
-D: Support for generic/custom MPC860T boards (GEN860T, GEN860T_SC)
-
-N: Frank Panno
-E: fpanno@delphintech.com
-D: Support for Embedded Planet EP8260 Board
-
-N: Denis Peter
-E: d.peter@mpl.ch
-D: Support for 4xx SCSI, floppy, CDROM, CT69000 video, ...
-D: Support for PIP405 board
-D: Support for MIP405 board
-
-N: Dave Peverley
-E: dpeverley@mpc-data.co.uk
-W: http://www.mpc-data.co.uk
-D: OMAP730 P2 board support
-
-N: Bill Pitts
-E: wlp@mindspring.com
-D: BedBug embedded debugger code
-
-N: Daniel Poirot
-E: dan.poirot@windriver.com
-D: Support for the Wind River sbc405, sbc8240 board
-W: http://www.windriver.com
-
-N: Stelian Pop
-E: stelian@popies.net
-D: Atmel AT91CAP9ADK support
-
-N: Ricardo Ribalda Delgado
-E: ricardo.ribalda@uam.es
-D: PPC440x5 (Virtex5), ML507 Board, eeprom_simul, adt7460, v5fx30teval
-D: Virtex ppc440 generic architecture
-D: Virtex ppc405 generic architecture
-W: http://www.ii.uam.es/~rribalda
-
-N: Stefan Roese
-E: sr@denx.de
-D: AMCC PPC4xx Support
-W: http://www.denx.de
-
-N: Erwin Rol
-E: erwin@muffin.org
-D: boot support for RTEMS
-
-N: Paul Ruhland
-E: pruhland@rochester.rr.com
-D: Port to Logic Zoom LH7A40x SDK board(s)
-
-N: Neil Russell
-E: caret@c-side.com
-D: Author of LiMon-1.4.2, which contributed some ideas
-
-N: Travis B. Sawyer
-E: travis.sawyer@sandburst.com
-D: Support for AMCC PPC440GX, XES XPedite1000 440GX PrPMC board. AMCC 440gx Ref Platform (Ocotea)
-
-N: Paolo Scaffardi
-E: arsenio@tin.it
-D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots more
-
-N: Andre Schwarz
-E: andre.schwarz@matrix-vision.de
-D: Support for Matrix Vision boards (MVBLM7/MVBC_P/MVSMR)
-
-N: Robert Schwebel
-E: r.schwebel@pengutronix.de
-D: Support for csb226 and innokom boards (PXA2xx)
-
-N: Aaron Sells
-E: sellsa@embeddedplanet.com
-D: Support for EP82xxM
-
-N: Art Shipkowski
-E: art@videon-central.com
-D: Support for NetSilicon NS7520
-D: Support for ColdFire MCF5275
-
-N: Jeremy C. Andrus
-E: jeremy@jeremya.com
-D: ColdFire MCF5249 initialization code
-W: jeremya.com
-
-N: Michal Simek
-E: monstr@monstr.eu
-D: Support for Microblaze, ML401, XUPV2P board
-W: www.monstr.eu
-
-N: Yasushi Shoji
-E: yashi@atmark-techno.com
-D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board
-
-N: Kurt Stremerch
-E: kurt@exys.be
-D: Support for Exys XSEngine board
-
-N: Andrea Scian
-E: andrea.scian@dave-tech.it
-D: Port to B2 board
-W: www.dave-tech.it
-
-N: Timur Tabi
-E: timur@freescale.com
-D: Support for MPC8349E-mITX
-W: www.freescale.com
-
-N: Rob Taylor
-E: robt@flyingpig.com
-D: Port to MBX860T and Sandpoint8240
-
-N: Erik Theisen
-E: etheisen@mindspring.com
-D: MBX8xx and many other patches
-
-N: Jim Thompson
-E: jim@musenki.com
-D: Support for MUSENKI board
-
-N: Rune Torgersen
-E: <runet@innovsys.com>
-D: Support for Motorola MPC8266ADS board
-
-N: Greg Ungerer
-E: greg.ungerer@opengear.com
-D: Support for ks8695 CPU, and OpenGear cmXXXX boards
-
-N: David Updegraff
-E: dave@cray.com
-D: Port to Cray L1 board; DHCP vendor extensions
-
-N: Christian Vejlbo
-E: christian.vejlbo@tellabs.com
-D: FADS860T ethernet support
-
-N: Robert Whaley
-E: rwhaley@applieddata.net
-D: Port to ARM PXA27x adsvix SBC
-
-N: Martin Winistoerfer
-E: martinwinistoerfer@gmx.ch
-D: Port to MPC555/556 microcontrollers and support for cmi board
-
-N: David Wu
-E: support@arcturusnetworks.com
-D: Mercury Security EP2500
-W: http://www.arcturusnetworks.com
-
-N: Ming-Len Wu
-E: minglen_wu@techware.com.tw
-D: Motorola MX1ADS board support
-W: http://www.techware.com.tw/
-
-N: Xianghua Xiao
-E: x.xiao@motorola.com
-D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards.
-
-N: John Zhan
-E: zhanz@sinovee.com
-D: Support for SinoVee Microsystems SC8xx SBC
-
-N: Alex Zuepke
-E: azu@sysgo.de
-D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
-W: www.elinos.com
-
-N: Nobuhiro Iwamatsu
-E: iwamatsu@nigauri.org
-D: Support for SuperH, MS7750SE01 and MS7722SE01 boards.
-W: http://www.nigauri.org/~iwamatsu/
-
-N: Alan Lu
-E: alnalu001@gmail.com
-D: Support for Artila M-501 starter kit
-W: http://www.artila.com/
-
-N: Kimmo Leppala
-E: kimmo.leppala@sysart.fi
-D: Support for Artila M-501 starter kit
-W: http://www.sysart.fi/
-
-N: Timo Tuunainen
-E: timo.tuunainen@sysart.fi
-D: Support for Artila M-501 starter kit
-W: http://www.sysart.fi/
-
-N: Philip Balister
-E: philip@opensdr.com
-D: Port to Lyrtech SFFSDR development board.
-W: www.opensdr.com
depends on $KCONFIG_OBJDIR="tpl"
default y
+config SUPPORT_SPL
+ bool
+
+config SUPPORT_TPL
+ bool
+
config SPL
bool
+ depends on SUPPORT_SPL
prompt "Enable SPL" if !SPL_BUILD
default y if SPL_BUILD
help
config TPL
bool
- depends on SPL
+ depends on SPL && SUPPORT_TPL
prompt "Enable TPL" if !SPL_BUILD
default y if TPL_BUILD
default n
configuration to Kconfig. Since this option will be removed sometime,
new boards should not use this option.
+config SYS_TEXT_BASE
+ depends on SPARC
+ hex "Text Base"
+ help
+ TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture
+
endmenu # Boot images
source "arch/Kconfig"
M: Stefan Roese <sr@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-cfi-flash.git
-F: drivers/mtd/*
+F: drivers/mtd/cfi_flash.c
+F: drivers/mtd/jedec_flash.c
COLDFIRE
M: Jason Jin <jason.jin@freescale.com>
F: arch/mips/
MMC
-M: Pantelis Antoniou <panto.antoniou-consulting.com>
+M: Pantelis Antoniou <panto@antoniou-consulting.com>
S: Maintained
T: git git://git.denx.de/u-boot-mmc.git
F: drivers/mmc/
-#
-# (C) Copyright 2000-2013
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
VERSION = 2014
PATCHLEVEL = 10
SUBLEVEL =
# Comments in this file are targeted only to the developer, do not
# expect to learn how to build the kernel reading this file.
-# Do not:
-# o use make's built-in rules and variables
-# (this increases performance and avoids hard-to-debug behaviour);
-# o print "Entering directory ...";
-MAKEFLAGS += -rR --no-print-directory
+# Do not use make's built-in rules and variables
+# (this increases performance and avoids hard-to-debug behaviour);
+MAKEFLAGS += -rR
# Avoid funny character set dependencies
unexport LC_ALL
LC_NUMERIC=C
export LC_COLLATE LC_NUMERIC
+# Avoid interference with shell env settings
+unexport GREP_OPTIONS
+
# We are using a recursive build, so we need to do a little thinking
# to get the ordering right.
#
# descending is started. They are now explicitly listed as the
# prepare rule.
+# Beautify output
+# ---------------------------------------------------------------------------
+#
+# Normally, we echo the whole command before executing it. By making
+# that echo $($(quiet)$(cmd)), we now have the possibility to set
+# $(quiet) to choose other forms of output instead, e.g.
+#
+# quiet_cmd_cc_o_c = Compiling $(RELDIR)/$@
+# cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $<
+#
+# If $(quiet) is empty, the whole command will be printed.
+# If it is set to "quiet_", only the short version will be printed.
+# If it is set to "silent_", nothing will be printed at all, since
+# the variable $(silent_cmd_cc_o_c) doesn't exist.
+#
+# A simple variant is to prefix commands with $(Q) - that's useful
+# for commands that shall be hidden in non-verbose mode.
+#
+# $(Q)ln $@ :<
+#
+# If KBUILD_VERBOSE equals 0 then the above command will be hidden.
+# If KBUILD_VERBOSE equals 1 then the above command is displayed.
+#
# To put more focus on warnings, be less verbose as default
# Use 'make V=1' to see the full commands
KBUILD_VERBOSE = 0
endif
-# Call a source code checker (by default, "sparse") as part of the
-# C compilation.
-#
-# Use 'make C=1' to enable checking of only re-compiled files.
-# Use 'make C=2' to enable checking of *all* source files, regardless
-# of whether they are re-compiled or not.
-#
-# See the file "Documentation/sparse.txt" for more details, including
-# where to get the "sparse" utility.
+ifeq ($(KBUILD_VERBOSE),1)
+ quiet =
+ Q =
+else
+ quiet=quiet_
+ Q = @
+endif
-ifeq ("$(origin C)", "command line")
- KBUILD_CHECKSRC = $(C)
+# If the user is running make -s (silent mode), suppress echoing of
+# commands
+
+ifneq ($(filter 4.%,$(MAKE_VERSION)),) # make-4
+ifneq ($(filter %s ,$(firstword x$(MAKEFLAGS))),)
+ quiet=silent_
endif
-ifndef KBUILD_CHECKSRC
- KBUILD_CHECKSRC = 0
+else # make-3.8x
+ifneq ($(filter s% -s%,$(MAKEFLAGS)),)
+ quiet=silent_
endif
-
-# Use make M=dir to specify directory of external module to build
-# Old syntax make ... SUBDIRS=$PWD is still supported
-# Setting the environment variable KBUILD_EXTMOD take precedence
-ifdef SUBDIRS
- KBUILD_EXTMOD ?= $(SUBDIRS)
endif
-ifeq ("$(origin M)", "command line")
- KBUILD_EXTMOD := $(M)
-endif
+export quiet Q KBUILD_VERBOSE
# kbuild supports saving output files in a separate directory.
# To locate output files in a separate directory two syntaxes are supported.
# The O= assignment takes precedence over the KBUILD_OUTPUT environment
# variable.
-
# KBUILD_SRC is set on invocation of make in OBJ directory
# KBUILD_SRC is not intended to be used by the regular user (for now)
ifeq ($(KBUILD_SRC),)
@:
sub-make: FORCE
- $(if $(KBUILD_VERBOSE:1=),@)$(MAKE) -C $(KBUILD_OUTPUT) \
- KBUILD_SRC=$(CURDIR) \
- KBUILD_EXTMOD="$(KBUILD_EXTMOD)" -f $(CURDIR)/Makefile \
- $(filter-out _all sub-make,$(MAKECMDGOALS))
+ $(Q)$(MAKE) -C $(KBUILD_OUTPUT) KBUILD_SRC=$(CURDIR) \
+ -f $(CURDIR)/Makefile $(filter-out _all sub-make,$(MAKECMDGOALS))
# Leave processing to above invocation of make
skip-makefile := 1
# We process the rest of the Makefile if this is the final invocation of make
ifeq ($(skip-makefile),)
+# Do not print "Entering directory ...",
+# but we want to display it when entering to the output directory
+# so that IDEs/editors are able to understand relative filenames.
+MAKEFLAGS += --no-print-directory
+
+# Call a source code checker (by default, "sparse") as part of the
+# C compilation.
+#
+# Use 'make C=1' to enable checking of only re-compiled files.
+# Use 'make C=2' to enable checking of *all* source files, regardless
+# of whether they are re-compiled or not.
+#
+# See the file "Documentation/sparse.txt" for more details, including
+# where to get the "sparse" utility.
+
+ifeq ("$(origin C)", "command line")
+ KBUILD_CHECKSRC = $(C)
+endif
+ifndef KBUILD_CHECKSRC
+ KBUILD_CHECKSRC = 0
+endif
+
+# Use make M=dir to specify directory of external module to build
+# Old syntax make ... SUBDIRS=$PWD is still supported
+# Setting the environment variable KBUILD_EXTMOD take precedence
+ifdef SUBDIRS
+ KBUILD_EXTMOD ?= $(SUBDIRS)
+endif
+
+ifeq ("$(origin M)", "command line")
+ KBUILD_EXTMOD := $(M)
+endif
+
# If building an external module we do not care about the all: rule
# but instead _all depend on modules
PHONY += all
_all: modules
endif
-srctree := $(if $(KBUILD_SRC),$(KBUILD_SRC),$(CURDIR))
-objtree := $(CURDIR)
+ifeq ($(KBUILD_SRC),)
+ # building in the source tree
+ srctree := .
+else
+ ifeq ($(KBUILD_SRC)/,$(dir $(CURDIR)))
+ # building in a subdirectory of the source tree
+ srctree := ..
+ else
+ srctree := $(KBUILD_SRC)
+ endif
+endif
+objtree := .
src := $(srctree)
obj := $(objtree)
export KBUILD_MODULES KBUILD_BUILTIN
export KBUILD_CHECKSRC KBUILD_SRC KBUILD_EXTMOD
-# Beautify output
-# ---------------------------------------------------------------------------
-#
-# Normally, we echo the whole command before executing it. By making
-# that echo $($(quiet)$(cmd)), we now have the possibility to set
-# $(quiet) to choose other forms of output instead, e.g.
-#
-# quiet_cmd_cc_o_c = Compiling $(RELDIR)/$@
-# cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $<
-#
-# If $(quiet) is empty, the whole command will be printed.
-# If it is set to "quiet_", only the short version will be printed.
-# If it is set to "silent_", nothing will be printed at all, since
-# the variable $(silent_cmd_cc_o_c) doesn't exist.
-#
-# A simple variant is to prefix commands with $(Q) - that's useful
-# for commands that shall be hidden in non-verbose mode.
-#
-# $(Q)ln $@ :<
-#
-# If KBUILD_VERBOSE equals 0 then the above command will be hidden.
-# If KBUILD_VERBOSE equals 1 then the above command is displayed.
-
-ifeq ($(KBUILD_VERBOSE),1)
- quiet =
- Q =
-else
- quiet=quiet_
- Q = @
-endif
-
-# If the user is running make -s (silent mode), suppress echoing of
-# commands
-
-ifneq ($(filter 4.%,$(MAKE_VERSION)),) # make-4
-ifneq ($(filter %s ,$(firstword x$(MAKEFLAGS))),)
- quiet=silent_
-endif
-else # make-3.8x
-ifneq ($(filter s% -s%,$(MAKEFLAGS)),)
- quiet=silent_
-endif
-endif
-
-export quiet Q KBUILD_VERBOSE
-
# Look for make include files relative to root of kernel src
MAKEFLAGS += --include-dir=$(srctree)
cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@
all: $(ALL-y)
+ifneq ($(CONFIG_SYS_GENERIC_BOARD),y)
+ @echo "===================== WARNING ======================"
+ @echo "Please convert this board to generic board."
+ @echo "Otherwise it will be removed by the end of 2014."
+ @echo "See doc/README.generic-board for further information"
+ @echo "===================================================="
+endif
PHONY += dtbs
dtbs dts/dt.dtb: checkdtc u-boot
ifneq ($(CONFIG_SUNXI),)
OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
--pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
-u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE
+u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin \
+ u-boot$(if $(CONFIG_OF_CONTROL),-dtb,).img FORCE
$(call if_changed,pad_cat)
endif
# make distclean Remove editor backup files, patch leftover files and the like
# Directories & files removed with 'make clean'
-CLEAN_DIRS += $(MODVERDIR)
-CLEAN_FILES += u-boot.lds include/bmp_logo.h include/bmp_logo_data.h
-
-# Directories & files removed with 'make clobber'
-CLOBBER_DIRS += $(foreach d, spl tpl, $(patsubst %,$d/%, \
+CLEAN_DIRS += $(MODVERDIR) \
+ $(foreach d, spl tpl, $(patsubst %,$d/%, \
$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
-CLOBBER_FILES += u-boot* MLO* SPL System.map
+
+CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
+ u-boot* MLO* SPL System.map
# Directories & files removed with 'make mrproper'
MRPROPER_DIRS += include/config include/generated spl tpl \
-o -name modules.builtin -o -name '.tmp_*.o.*' \
-o -name '*.gcno' \) -type f -print | xargs rm -f
-# clobber
-#
-clobber: rm-dirs := $(CLOBBER_DIRS)
-clobber: rm-files := $(CLOBBER_FILES)
-
-PHONY += clobber
-
-clobber: clean
- $(call cmd,rmdirs)
- $(call cmd,rmfiles)
-
# mrproper - Delete all generated files, including .config
#
mrproper: rm-dirs := $(wildcard $(MRPROPER_DIRS))
$(mrproper-dirs):
$(Q)$(MAKE) $(clean)=$(patsubst _mrproper_%,%,$@)
-mrproper: clobber $(mrproper-dirs)
+mrproper: clean $(mrproper-dirs)
$(call cmd,rmdirs)
$(call cmd,rmfiles)
@rm -f arch/*/include/asm/arch
help:
@echo 'Cleaning targets:'
- @echo ' clean - Remove most generated files but keep the config and'
- @echo ' necessities for testing u-boot'
- @echo ' clobber - Remove most generated files but keep the config'
+ @echo ' clean - Remove most generated files but keep the config'
@echo ' mrproper - Remove all generated files + config + various backup files'
@echo ' distclean - mrproper + remove editor backup and patch files'
@echo ''
@echo ''
@echo 'Other generic targets:'
@echo ' all - Build all necessary images depending on configuration'
- @echo ' u-boot - Build the bare u-boot'
+ @echo '* u-boot - Build the bare u-boot'
@echo ' dir/ - Build all files in dir and below'
@echo ' dir/file.[oisS] - Build specified target only'
@echo ' dir/file.lst - Build specified mixed source/assembly target only'
@echo ' tags/ctags - Generate ctags file for editors'
@echo ' etags - Generate etags file for editors'
@echo ' cscope - Generate cscope index'
- @echo ' ubootrelease - Output the release version string'
- @echo ' ubootversion - Output the version stored in Makefile'
+ @echo ' ubootrelease - Output the release version string (use with make -s)'
+ @echo ' ubootversion - Output the version stored in Makefile (use with make -s)'
@echo ''
@echo 'Static analysers'
@echo ' checkstack - Generate a list of stack hogs'
# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.clean obj=dir
# Usage:
# $(Q)$(MAKE) $(clean)=dir
-clean := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.clean obj
+clean := -f $(srctree)/scripts/Makefile.clean obj
endif # skip-makefile
CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
txfilltuning field in the EHCI controller on reset.
+ CONFIG_USB_DWC2_REG_ADDR the physical CPU address of the DWC2
+ HW module registers.
+
- USB Device:
Define the below if you wish to use the USB console.
Once firmware is rebuilt from a serial console issue the
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS,
- CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION
+ CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION
Address, size and partition on the MMC to load U-Boot from
when the MMC is being used in raw mode.
CONFIG_SPL_FAT_SUPPORT
Support for fs/fat/libfat.o in SPL binary
- CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME
- Filename to read to load U-Boot when reading from FAT
+ CONFIG_SPL_EXT_SUPPORT
+ Support for EXT filesystem in SPL binary
+
+ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
+ Filename to read to load U-Boot when reading from filesystem
- CONFIG_SPL_FAT_LOAD_KERNEL_NAME
+ CONFIG_SPL_FS_LOAD_KERNEL_NAME
Filename to read to load kernel uImage when reading
- from FAT (for Falcon mode)
+ from filesystem (for Falcon mode)
- CONFIG_SPL_FAT_LOAD_ARGS_NAME
+ CONFIG_SPL_FS_LOAD_ARGS_NAME
Filename to read to load kernel argument parameters
- when reading from FAT (for Falcon mode)
+ when reading from filesystem (for Falcon mode)
CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
Set this for NAND SPL on PPC mpc83xx targets, so that
be asserted. See doc/README.omap-reset-time for details on how
the value can be calulated on a given board.
+- CONFIG_USE_STDINT
+ If stdint.h is available with your toolchain you can define this
+ option to enable it. You can provide option 'USE_STDINT=1' when
+ building U-Boot to enable this.
+
The following definitions that deal with the placement and management
of environment data (variable area); in general, we support the
following configurations:
make O=/tmp/build NAME_defconfig
make O=/tmp/build all
-2. Set environment variable BUILD_DIR to point to the desired location:
+2. Set environment variable KBUILD_OUTPUT to point to the desired location:
- export BUILD_DIR=/tmp/build
+ export KBUILD_OUTPUT=/tmp/build
make distclean
make NAME_defconfig
make all
-Note that the command line "O=" setting overrides the BUILD_DIR environment
+Note that the command line "O=" setting overrides the KBUILD_OUTPUT environment
variable.
config ARM64
bool
+config HAS_VBAR
+ bool
+
+config CPU_ARM720T
+ bool
+
+config CPU_ARM920T
+ bool
+
+config CPU_ARM926EJS
+ bool
+
+config CPU_ARM946ES
+ bool
+
+config CPU_ARM1136
+ bool
+
+config CPU_ARM1176
+ bool
+ select HAS_VBAR
+
+config CPU_V7
+ bool
+ select HAS_VBAR
+
+config CPU_PXA
+ bool
+
+config CPU_SA1100
+ bool
+
+config SYS_CPU
+ default "arm720t" if CPU_ARM720T
+ default "arm920t" if CPU_ARM920T
+ default "arm926ejs" if CPU_ARM926EJS
+ default "arm946es" if CPU_ARM946ES
+ default "arm1136" if CPU_ARM1136
+ default "arm1176" if CPU_ARM1176
+ default "armv7" if CPU_V7
+ default "pxa" if CPU_PXA
+ default "sa1100" if CPU_SA1100
+
choice
prompt "Target select"
config TARGET_INTEGRATORAP_CM720T
bool "Support integratorap_cm720t"
+ select CPU_ARM720T
config TARGET_INTEGRATORAP_CM920T
bool "Support integratorap_cm920t"
+ select CPU_ARM920T
config TARGET_INTEGRATORCP_CM920T
bool "Support integratorcp_cm920t"
+ select CPU_ARM920T
config TARGET_A320EVB
bool "Support a320evb"
+ select CPU_ARM920T
config TARGET_AT91RM9200EK
bool "Support at91rm9200ek"
+ select CPU_ARM920T
config TARGET_EB_CPUX9K2
bool "Support eb_cpux9k2"
+ select CPU_ARM920T
config TARGET_CPUAT91
bool "Support cpuat91"
+ select CPU_ARM920T
config TARGET_EDB93XX
bool "Support edb93xx"
+ select CPU_ARM920T
config TARGET_SCB9328
bool "Support scb9328"
+ select CPU_ARM920T
config TARGET_CM4008
bool "Support cm4008"
+ select CPU_ARM920T
config TARGET_CM41XX
bool "Support cm41xx"
+ select CPU_ARM920T
config TARGET_VCMA9
bool "Support VCMA9"
+ select CPU_ARM920T
config TARGET_SMDK2410
bool "Support smdk2410"
+ select CPU_ARM920T
config TARGET_INTEGRATORAP_CM926EJS
bool "Support integratorap_cm926ejs"
+ select CPU_ARM926EJS
config TARGET_INTEGRATORCP_CM926EJS
bool "Support integratorcp_cm926ejs"
+ select CPU_ARM926EJS
config TARGET_ASPENITE
bool "Support aspenite"
+ select CPU_ARM926EJS
config TARGET_GPLUGD
bool "Support gplugd"
+ select CPU_ARM926EJS
config TARGET_AFEB9260
bool "Support afeb9260"
+ select CPU_ARM926EJS
config TARGET_AT91SAM9260EK
bool "Support at91sam9260ek"
+ select CPU_ARM926EJS
config TARGET_AT91SAM9261EK
bool "Support at91sam9261ek"
+ select CPU_ARM926EJS
config TARGET_AT91SAM9263EK
bool "Support at91sam9263ek"
+ select CPU_ARM926EJS
config TARGET_AT91SAM9M10G45EK
bool "Support at91sam9m10g45ek"
+ select CPU_ARM926EJS
config TARGET_AT91SAM9N12EK
bool "Support at91sam9n12ek"
+ select CPU_ARM926EJS
config TARGET_AT91SAM9RLEK
bool "Support at91sam9rlek"
+ select CPU_ARM926EJS
config TARGET_AT91SAM9X5EK
bool "Support at91sam9x5ek"
+ select CPU_ARM926EJS
config TARGET_SNAPPER9260
bool "Support snapper9260"
+ select CPU_ARM926EJS
config TARGET_VL_MA2SC
bool "Support vl_ma2sc"
+ select CPU_ARM926EJS
config TARGET_SBC35_A9G20
bool "Support sbc35_a9g20"
+ select CPU_ARM926EJS
config TARGET_TNY_A9260
bool "Support tny_a9260"
+ select CPU_ARM926EJS
config TARGET_USB_A9263
bool "Support usb_a9263"
+ select CPU_ARM926EJS
config TARGET_ETHERNUT5
bool "Support ethernut5"
-
-config TARGET_TOP9000
- bool "Support top9000"
+ select CPU_ARM926EJS
config TARGET_MEESC
bool "Support meesc"
+ select CPU_ARM926EJS
config TARGET_OTC570
bool "Support otc570"
+ select CPU_ARM926EJS
config TARGET_CPU9260
bool "Support cpu9260"
+ select CPU_ARM926EJS
config TARGET_PM9261
bool "Support pm9261"
+ select CPU_ARM926EJS
config TARGET_PM9263
bool "Support pm9263"
+ select CPU_ARM926EJS
config TARGET_PM9G45
bool "Support pm9g45"
+ select CPU_ARM926EJS
config TARGET_CORVUS
bool "Support corvus"
+ select CPU_ARM926EJS
config TARGET_TAURUS
bool "Support taurus"
+ select CPU_ARM926EJS
config TARGET_STAMP9G20
bool "Support stamp9g20"
+ select CPU_ARM926EJS
config ARCH_DAVINCI
bool "TI DaVinci"
+ select CPU_ARM926EJS
help
Support for TI's DaVinci platform.
config KIRKWOOD
bool "Marvell Kirkwood"
+ select CPU_ARM926EJS
config TARGET_DB_MV784MP_GP
bool "Support db-mv784mp-gp"
config TARGET_DEVKIT3250
bool "Support devkit3250"
+ select CPU_ARM926EJS
config TARGET_JADECPU
bool "Support jadecpu"
+ select CPU_ARM926EJS
config TARGET_MX25PDK
bool "Support mx25pdk"
+ select CPU_ARM926EJS
config TARGET_TX25
bool "Support tx25"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_ZMX25
bool "Support zmx25"
+ select CPU_ARM926EJS
config TARGET_APF27
bool "Support apf27"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_IMX27LITE
bool "Support imx27lite"
+ select CPU_ARM926EJS
config TARGET_MAGNESIUM
bool "Support magnesium"
+ select CPU_ARM926EJS
config TARGET_APX4DEVKIT
bool "Support apx4devkit"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_XFI3
bool "Support xfi3"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_M28EVK
bool "Support m28evk"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_MX23EVK
bool "Support mx23evk"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_MX28EVK
bool "Support mx28evk"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_MX23_OLINUXINO
bool "Support mx23_olinuxino"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_BG0900
bool "Support bg0900"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_SANSA_FUZE_PLUS
bool "Support sansa_fuze_plus"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
config TARGET_SC_SPS_1
bool "Support sc_sps_1"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
config ARCH_NOMADIK
bool "ST-Ericsson Nomadik"
+ select CPU_ARM926EJS
config ORION5X
bool "Marvell Orion"
+ select CPU_ARM926EJS
config TARGET_DKB
bool "Support dkb"
+ select CPU_ARM926EJS
config TARGET_SPEAR300
bool "Support spear300"
+ select CPU_ARM926EJS
config TARGET_SPEAR310
bool "Support spear310"
+ select CPU_ARM926EJS
config TARGET_SPEAR320
bool "Support spear320"
+ select CPU_ARM926EJS
config TARGET_SPEAR600
bool "Support spear600"
+ select CPU_ARM926EJS
config TARGET_X600
bool "Support x600"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
config ARCH_VERSATILE
bool "ARM Ltd. Versatile family"
+ select CPU_ARM926EJS
config TARGET_INTEGRATORCP_CM1136
bool "Support integratorcp_cm1136"
+ select CPU_ARM1136
config TARGET_IMX31_PHYCORE
bool "Support imx31_phycore"
+ select CPU_ARM1136
config TARGET_QONG
bool "Support qong"
+ select CPU_ARM1136
config TARGET_MX31ADS
bool "Support mx31ads"
+ select CPU_ARM1136
config TARGET_MX31PDK
bool "Support mx31pdk"
+ select CPU_ARM1136
+ select SUPPORT_SPL
config TARGET_TT01
bool "Support tt01"
+ select CPU_ARM1136
config TARGET_IMX31_LITEKIT
bool "Support imx31_litekit"
+ select CPU_ARM1136
config TARGET_WOODBURN
bool "Support woodburn"
+ select CPU_ARM1136
config TARGET_WOODBURN_SD
bool "Support woodburn_sd"
+ select CPU_ARM1136
+ select SUPPORT_SPL
config TARGET_FLEA3
bool "Support flea3"
+ select CPU_ARM1136
config TARGET_MX35PDK
bool "Support mx35pdk"
+ select CPU_ARM1136
config TARGET_RPI_B
bool "Support rpi_b"
+ select CPU_ARM1176
config TARGET_TNETV107X_EVM
bool "Support tnetv107x_evm"
+ select CPU_ARM1176
config TARGET_INTEGRATORAP_CM946ES
bool "Support integratorap_cm946es"
+ select CPU_ARM946ES
config TARGET_INTEGRATORCP_CM946ES
bool "Support integratorcp_cm946es"
+ select CPU_ARM946ES
config TARGET_VEXPRESS_CA15_TC2
bool "Support vexpress_ca15_tc2"
+ select CPU_V7
config TARGET_VEXPRESS_CA5X2
bool "Support vexpress_ca5x2"
+ select CPU_V7
config TARGET_VEXPRESS_CA9X4
bool "Support vexpress_ca9x4"
+ select CPU_V7
config TARGET_KWB
bool "Support kwb"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_TSERIES
bool "Support tseries"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_CM_T335
bool "Support cm_t335"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_PEPPER
bool "Support pepper"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_AM335X_IGEP0033
bool "Support am335x_igep0033"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_PCM051
bool "Support pcm051"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_DRACO
bool "Support draco"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_DXR2
bool "Support dxr2"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_PXM2
bool "Support pxm2"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_RUT
bool "Support rut"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_PENGWYN
bool "Support pengwyn"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_AM335X_EVM
bool "Support am335x_evm"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_AM43XX_EVM
bool "Support am43xx_evm"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_TI814X_EVM
bool "Support ti814x_evm"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_TI816X_EVM
bool "Support ti816x_evm"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_SAMA5D3_XPLAINED
bool "Support sama5d3_xplained"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_SAMA5D3XEK
bool "Support sama5d3xek"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_BCM28155_AP
bool "Support bcm28155_ap"
+ select CPU_V7
config TARGET_BCM958300K
bool "Support bcm958300k"
+ select CPU_V7
config TARGET_BCM958622HR
bool "Support bcm958622hr"
+ select CPU_V7
config ARCH_EXYNOS
bool "Samsung EXYNOS"
+ select CPU_V7
config ARCH_S5PC1XX
bool "Samsung S5PC1XX"
+ select CPU_V7
config ARCH_HIGHBANK
bool "Calxeda Highbank"
+ select CPU_V7
config ARCH_KEYSTONE
bool "TI Keystone"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_M53EVK
bool "Support m53evk"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_IMA3_MX53
bool "Support ima3-mx53"
+ select CPU_V7
config TARGET_MX51EVK
bool "Support mx51evk"
+ select CPU_V7
config TARGET_MX53ARD
bool "Support mx53ard"
+ select CPU_V7
config TARGET_MX53EVK
bool "Support mx53evk"
+ select CPU_V7
config TARGET_MX53LOCO
bool "Support mx53loco"
+ select CPU_V7
config TARGET_MX53SMD
bool "Support mx53smd"
+ select CPU_V7
config TARGET_MX51_EFIKAMX
bool "Support mx51_efikamx"
+ select CPU_V7
config TARGET_VISION2
bool "Support vision2"
+ select CPU_V7
config TARGET_UDOO
bool "Support udoo"
+ select CPU_V7
config TARGET_WANDBOARD
bool "Support wandboard"
+ select CPU_V7
config TARGET_TITANIUM
bool "Support titanium"
+ select CPU_V7
config TARGET_NITROGEN6X
bool "Support nitrogen6x"
+ select CPU_V7
config TARGET_CGTQMX6EVAL
bool "Support cgtqmx6eval"
+ select CPU_V7
config TARGET_EMBESTMX6BOARDS
bool "Support embestmx6boards"
+ select CPU_V7
config TARGET_ARISTAINETOS
bool "Support aristainetos"
+ select CPU_V7
config TARGET_MX6QARM2
bool "Support mx6qarm2"
+ select CPU_V7
config TARGET_MX6QSABREAUTO
bool "Support mx6qsabreauto"
+ select CPU_V7
config TARGET_MX6SABRESD
bool "Support mx6sabresd"
+ select CPU_V7
config TARGET_MX6SLEVK
bool "Support mx6slevk"
+ select CPU_V7
config TARGET_MX6SXSABRESD
bool "Support mx6sxsabresd"
+ select CPU_V7
config TARGET_GW_VENTANA
bool "Support gw_ventana"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_HUMMINGBOARD
bool "Support hummingboard"
+ select CPU_V7
+
+config TARGET_KOSAGI_NOVENA
+ bool "Support Kosagi Novena"
config TARGET_TQMA6
bool "TQ Systems TQMa6 board"
+ select CPU_V7
config TARGET_OT1200
bool "Bachmann OT1200"
+ select CPU_V7
config OMAP34XX
bool "OMAP34XX SoC"
+ select CPU_V7
config OMAP44XX
bool "OMAP44XX SoC"
+ select CPU_V7
+ select SUPPORT_SPL
config OMAP54XX
bool "OMAP54XX SoC"
+ select CPU_V7
+ select SUPPORT_SPL
config RMOBILE
bool "Renesas ARM SoCs"
+ select CPU_V7
config TARGET_CM_FX6
bool "Support cm_fx6"
+ select CPU_V7
+ select SUPPORT_SPL
config TARGET_SOCFPGA_CYCLONE5
bool "Support socfpga_cyclone5"
+ select CPU_V7
+ select SUPPORT_SPL
-config TARGET_SUN4I
- bool "Support sun4i"
-
-config TARGET_SUN5I
- bool "Support sun5i"
-
-config TARGET_SUN7I
- bool "Support sun7i"
+config ARCH_SUNXI
+ bool "Support sunxi (Allwinner) SoCs"
config TARGET_SNOWBALL
bool "Support snowball"
+ select CPU_V7
config TARGET_U8500_HREF
bool "Support u8500_href"
+ select CPU_V7
config TARGET_VF610TWR
bool "Support vf610twr"
+ select CPU_V7
config ZYNQ
bool "Xilinx Zynq Platform"
+ select CPU_V7
+ select SUPPORT_SPL
config TEGRA
bool "NVIDIA Tegra"
+ select SUPPORT_SPL
select SPL
select OF_CONTROL if !SPL_BUILD
+ select CPU_ARM720T if SPL_BUILD
+ select CPU_V7 if !SPL_BUILD
config TARGET_VEXPRESS_AEMV8A
bool "Support vexpress_aemv8a"
config TARGET_LS1021AQDS
bool "Support ls1021aqds_nor"
+ select CPU_V7
config TARGET_LS1021ATWR
bool "Support ls1021atwr_nor"
+ select CPU_V7
config TARGET_BALLOON3
bool "Support balloon3"
+ select CPU_PXA
config TARGET_H2200
bool "Support h2200"
+ select CPU_PXA
config TARGET_PALMLD
bool "Support palmld"
+ select CPU_PXA
config TARGET_PALMTC
bool "Support palmtc"
+ select CPU_PXA
config TARGET_PALMTREO680
bool "Support palmtreo680"
+ select CPU_PXA
+ select SUPPORT_SPL
config TARGET_PXA255_IDP
bool "Support pxa255_idp"
+ select CPU_PXA
config TARGET_TRIZEPSIV
bool "Support trizepsiv"
+ select CPU_PXA
config TARGET_VPAC270
bool "Support vpac270"
+ select CPU_PXA
+ select SUPPORT_SPL
config TARGET_XAENIAX
bool "Support xaeniax"
+ select CPU_PXA
config TARGET_ZIPITZ2
bool "Support zipitz2"
+ select CPU_PXA
config TARGET_LP8X4X
bool "Support lp8x4x"
+ select CPU_PXA
config TARGET_COLIBRI_PXA270
bool "Support colibri_pxa270"
+ select CPU_PXA
config TARGET_JORNADA
bool "Support jornada"
+ select CPU_SA1100
config ARCH_UNIPHIER
bool "Panasonic UniPhier platform"
+ select CPU_V7
+ select SUPPORT_SPL
endchoice
source "board/denx/m53evk/Kconfig"
source "board/egnite/ethernut5/Kconfig"
source "board/embest/mx6boards/Kconfig"
-source "board/emk/top9000/Kconfig"
source "board/esd/meesc/Kconfig"
source "board/esd/otc570/Kconfig"
source "board/esg/ima3-mx53/Kconfig"
source "board/isee/igep0033/Kconfig"
source "board/jornada/Kconfig"
source "board/karo/tx25/Kconfig"
+source "board/kosagi/novena/Kconfig"
source "board/logicpd/imx27lite/Kconfig"
source "board/logicpd/imx31_litekit/Kconfig"
source "board/maxbcm/Kconfig"
switch (spl_boot_device()) {
case BOOT_DEVICE_MMC1:
#ifdef CONFIG_SPL_FAT_SUPPORT
- return MMCSD_MODE_FAT;
+ return MMCSD_MODE_FS;
#else
return MMCSD_MODE_RAW;
#endif
#include <common.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
+#include <status_led.h>
#ifdef CONFIG_RED_LED
void red_led_on(void)
/*
* Stub implementations for l2 cache operations
*/
-void __l2_cache_disable(void) {}
-
-void l2_cache_disable(void)
- __attribute__((weak, alias("__l2_cache_disable")));
+__weak void l2_cache_disable(void) {}
config TARGET_IPAM390
bool "IPAM390 board"
+ select SUPPORT_SPL
config TARGET_DA830EVM
bool "DA830 EVM board"
config TARGET_DA850EVM
bool "DA850 EVM board"
+ select SUPPORT_SPL
config TARGET_CAM_ENC_4XX
bool "CAM ENC 4xx board"
+ select SUPPORT_SPL
config TARGET_HAWKBOARD
bool "Hawkboard"
+ select SUPPORT_SPL
config TARGET_DAVINCI_DM355EVM
bool "DM355 EVM board"
endchoice
-config SYS_CPU
- default "arm926ejs"
-
config SYS_SOC
default "davinci"
endchoice
-config SYS_CPU
- default "arm926ejs"
-
config SYS_SOC
default "kirkwood"
int i;
for (i = 0; i < 8; i++) {
+ /* cppcheck-suppress nullPointer */
vt[i] = ldr_pc;
+ /* cppcheck-suppress nullPointer */
vt[i + 8] = start_addr + (4 * i);
}
}
* fine.
*/
extern uint32_t _start;
+
+ /* cppcheck-suppress nullPointer */
memcpy(0x0, &_start, 0x60);
}
TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET;
#elif defined(CONFIG_MX28)
now = readl(&timrot_regs->hw_timrot_running_count0);
+#else
+#error "Don't know how to read timrot_regs"
#endif
if (lastdec >= now) {
endchoice
-config SYS_CPU
- default "arm926ejs"
-
config SYS_SOC
default "nomadik"
endchoice
-config SYS_CPU
- default "arm926ejs"
-
config SYS_SOC
default "orion5x"
#if defined(CONFIG_DW_UDC)
periph1_clken |= MISC_USBDENB;
#endif
-#if defined(CONFIG_DW_I2C)
+#if defined(CONFIG_SYS_I2C_DW)
periph1_clken |= MISC_I2CENB;
#endif
#if defined(CONFIG_ST_SMI)
if ARCH_VERSATILE
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "versatile"
*/
#include <common.h>
+#include <dm.h>
#include <errno.h>
+#include <ns16550.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_DM_GPIO
+static const struct omap_gpio_platdata am33xx_gpio[] = {
+ { 0, AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
+ { 1, AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
+ { 2, AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
+ { 3, AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
+#ifdef CONFIG_AM43XX
+ { 4, AM33XX_GPIO4_BASE, METHOD_GPIO_24XX },
+ { 5, AM33XX_GPIO5_BASE, METHOD_GPIO_24XX },
+#endif
+};
+
+U_BOOT_DEVICES(am33xx_gpios) = {
+ { "gpio_omap", &am33xx_gpio[0] },
+ { "gpio_omap", &am33xx_gpio[1] },
+ { "gpio_omap", &am33xx_gpio[2] },
+ { "gpio_omap", &am33xx_gpio[3] },
+#ifdef CONFIG_AM43XX
+ { "gpio_omap", &am33xx_gpio[4] },
+ { "gpio_omap", &am33xx_gpio[5] },
+#endif
+};
+
+# ifndef CONFIG_OF_CONTROL
+/*
+ * TODO(sjg@chromium.org): When we can move SPL serial to DM, we can remove
+ * the CONFIGs. At the same time, we should move this to the board files.
+ */
+static const struct ns16550_platdata am33xx_serial[] = {
+ { CONFIG_SYS_NS16550_COM1, 2, CONFIG_SYS_NS16550_CLK },
+# ifdef CONFIG_SYS_NS16550_COM2
+ { CONFIG_SYS_NS16550_COM2, 2, CONFIG_SYS_NS16550_CLK },
+# ifdef CONFIG_SYS_NS16550_COM3
+ { CONFIG_SYS_NS16550_COM3, 2, CONFIG_SYS_NS16550_CLK },
+ { CONFIG_SYS_NS16550_COM4, 2, CONFIG_SYS_NS16550_CLK },
+ { CONFIG_SYS_NS16550_COM5, 2, CONFIG_SYS_NS16550_CLK },
+ { CONFIG_SYS_NS16550_COM6, 2, CONFIG_SYS_NS16550_CLK },
+# endif
+# endif
+};
+
+U_BOOT_DEVICES(am33xx_uarts) = {
+ { "serial_omap", &am33xx_serial[0] },
+# ifdef CONFIG_SYS_NS16550_COM2
+ { "serial_omap", &am33xx_serial[1] },
+# ifdef CONFIG_SYS_NS16550_COM3
+ { "serial_omap", &am33xx_serial[2] },
+ { "serial_omap", &am33xx_serial[3] },
+ { "serial_omap", &am33xx_serial[4] },
+ { "serial_omap", &am33xx_serial[5] },
+# endif
+# endif
+};
+# endif
+
+#else
+
static const struct gpio_bank gpio_bank_am33xx[] = {
{ (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
{ (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
+#endif
+
#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
int cpu_mmc_init(bd_t *bis)
{
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
#include <power/tps65910.h>
+#include <linux/compiler.h>
struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
/**
* get_board_rev() - setup to pass kernel board revision information
- * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
+ * returns: 0 for the ATAG REVISION tag value.
*/
-u32 get_board_rev(void)
+u32 __weak get_board_rev(void)
{
- return BOARD_REV_ID;
+ return 0;
}
/**
prompt "EXYNOS board select"
config TARGET_SMDKV310
+ select SUPPORT_SPL
bool "Exynos4210 SMDKV310 board"
select OF_CONTROL if !SPL_BUILD
config TARGET_ORIGEN
bool "Exynos4412 Origen board"
+ select SUPPORT_SPL
config TARGET_TRATS2
bool "Exynos4412 Trat2 board"
config TARGET_ARNDALE
bool "Exynos5250 Arndale board"
+ select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
config TARGET_SMDK5250
bool "SMDK5250 board"
+ select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
config TARGET_SNOW
bool "Snow board"
+ select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
config TARGET_SMDK5420
bool "SMDK5420 board"
+ select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
config TARGET_PEACH_PIT
bool "Peach Pi board"
+ select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
endchoice
-config SYS_CPU
- default "armv7"
-
config SYS_SOC
default "exynos"
if ARCH_HIGHBANK
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "highbank"
config TARGET_K2E_EVM
bool "TI Keystone 2 Edison EVM"
-endchoice
+config TARGET_K2L_EVM
+ bool "TI Keystone 2 Lamar EVM"
-config SYS_CPU
- default "armv7"
+endchoice
config SYS_SOC
default "keystone"
obj-y += clock.o
obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
obj-$(CONFIG_SOC_K2E) += clock-k2e.o
+obj-$(CONFIG_SOC_K2L) += clock-k2l.o
obj-y += cmd_clock.o
obj-y += cmd_mon.o
-obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o
obj-y += msmc.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
-obj-y += ddr3.o
+obj-y += ddr3.o cmd_ddr3.o
obj-y += keystone.o
--- /dev/null
+/*
+ * Keystone2: get clk rate for K2L
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clock_defs.h>
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+ [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+ [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+ [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
+ [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+};
+
+int dev_speeds[] = {
+ SPD800,
+ SPD1000,
+ SPD1200,
+ SPD800,
+ SPD800,
+ SPD800,
+ SPD800,
+ SPD800,
+ SPD1200,
+ SPD1000,
+ SPD800,
+ SPD800,
+ SPD800,
+};
+
+int arm_speeds[] = {
+ SPD800,
+ SPD1000,
+ SPD1200,
+ SPD1350,
+ SPD1400,
+ SPD800,
+ SPD1400,
+ SPD1350,
+ SPD1200,
+ SPD1000,
+ SPD800,
+ SPD800,
+ SPD800,
+};
+
+/**
+ * pll_freq_get - get pll frequency
+ * Fout = Fref * NF(mult) / NR(prediv) / OD
+ * @pll: pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+ unsigned long mult = 1, prediv = 1, output_div = 2;
+ unsigned long ret;
+ u32 tmp, reg;
+
+ if (pll == CORE_PLL) {
+ ret = external_clk[sys_clk];
+ if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
+ /* PLL mode */
+ tmp = __raw_readl(KS2_MAINPLLCTL0);
+ prediv = (tmp & PLL_DIV_MASK) + 1;
+ mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
+ (pllctl_reg_read(pll, mult) &
+ PLLM_MULT_LO_MASK)) + 1;
+ output_div = ((pllctl_reg_read(pll, secctl) >>
+ PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
+
+ ret = ret / prediv / output_div * mult;
+ }
+ } else {
+ switch (pll) {
+ case PASS_PLL:
+ ret = external_clk[pa_clk];
+ reg = KS2_PASSPLLCTL0;
+ break;
+ case TETRIS_PLL:
+ ret = external_clk[tetris_clk];
+ reg = KS2_ARMPLLCTL0;
+ break;
+ case DDR3_PLL:
+ ret = external_clk[ddr3_clk];
+ reg = KS2_DDR3APLLCTL0;
+ break;
+ default:
+ return 0;
+ }
+
+ tmp = __raw_readl(reg);
+ if (!(tmp & PLLCTL_BYPASS)) {
+ /* Bypass disabled */
+ prediv = (tmp & PLL_DIV_MASK) + 1;
+ mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
+ output_div = ((tmp >> PLL_CLKOD_SHIFT) &
+ PLL_CLKOD_MASK) + 1;
+ ret = ((ret / prediv) * mult) / output_div;
+ }
+ }
+
+ return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+ switch (clk) {
+ case core_pll_clk: return pll_freq_get(CORE_PLL);
+ case pass_pll_clk: return pll_freq_get(PASS_PLL);
+ case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
+ case ddr3_pll_clk: return pll_freq_get(DDR3_PLL);
+ case sys_clk0_1_clk:
+ case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
+ case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
+ case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
+ case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
+ case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
+ case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
+ case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
+ case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
+ case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
+ case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
+ case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
+ case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
+ case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
+ case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
+ case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
+ default:
+ break;
+ }
+
+ return 0;
+}
tmp &= ~(PLL_BWADJ_HI_MASK);
tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
- /* set PLL Select (bit 13) for PASS PLL */
- if (data->pll == PASS_PLL)
- tmp |= PLLCTL_PAPLL;
-
__raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
/* Reset bit: bit 14 for both DDR3 & PASS PLL */
return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds);
}
#endif
+
+void pass_pll_pa_clk_enable(void)
+{
+ u32 reg;
+
+ reg = readl(keystone_pll_regs[PASS_PLL].reg1);
+
+ reg |= PLLCTL_PAPLL;
+ writel(reg, keystone_pll_regs[PASS_PLL].reg1);
+
+ /* wait till clock is enabled */
+ sdelay(15000);
+}
return cmd_usage(cmdtp);
}
-#ifdef CONFIG_SOC_K2HK
-U_BOOT_CMD(
- pllset, 5, 0, do_pll_cmd,
- "set pll multiplier and pre divider",
- "<pa|arm|ddr3a|ddr3b> <mult> <div> <OD>\n"
-);
-#endif
-#ifdef CONFIG_SOC_K2E
U_BOOT_CMD(
pllset, 5, 0, do_pll_cmd,
"set pll multiplier and pre divider",
-
"<pa|ddr3> <mult> <div> <OD>\n"
+
PLLSET_CMD_LIST " <mult> <div> <OD>\n"
);
-#endif
int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
getclk, 2, 0, do_getclk_cmd,
"get clock rate",
"<clk index>\n"
-#ifdef CONFIG_SOC_K2HK
- "See the 'enum clk_e' in the clock-k2hk.h for clk indexes\n"
-#endif
-#ifdef CONFIG_SOC_K2E
- "See the 'enum clk_e' in the clock-k2e.h for clk indexes\n"
-#endif
+ "The indexes for clocks:\n"
+ CLOCK_INDEXES_LIST
);
int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
psc, 3, 0, do_psc_cmd,
"<enable/disable psc module os disable domain>",
"<mod/domain index> <en|di|domain>\n"
- "See the hardware.h for Power and Sleep Controller (PSC) Domains\n"
+ "Intended to control Power and Sleep Controller (PSC) domains and\n"
+ "modules. The module or domain index exectly corresponds to ones\n"
+ "listed in official TRM. For instance, to enable MSMC RAM clock\n"
+ "domain use command: psc 14 en.\n"
);
--- /dev/null
+/*
+ * Keystone2: DDR3 test commands
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/ddr3.h>
+#include <common.h>
+#include <command.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DDR_MIN_ADDR CONFIG_SYS_SDRAM_BASE
+
+#define DDR_REMAP_ADDR 0x80000000
+#define ECC_START_ADDR1 ((DDR_MIN_ADDR - DDR_REMAP_ADDR) >> 17)
+
+#define ECC_END_ADDR1 (((gd->start_addr_sp - DDR_REMAP_ADDR - \
+ CONFIG_STACKSIZE) >> 17) - 2)
+
+#define DDR_TEST_BURST_SIZE 1024
+
+static int ddr_memory_test(u32 start_address, u32 end_address, int quick)
+{
+ u32 index_start, value, index;
+
+ index_start = start_address;
+
+ while (1) {
+ /* Write a pattern */
+ for (index = index_start;
+ index < index_start + DDR_TEST_BURST_SIZE;
+ index += 4)
+ __raw_writel(index, index);
+
+ /* Read and check the pattern */
+ for (index = index_start;
+ index < index_start + DDR_TEST_BURST_SIZE;
+ index += 4) {
+ value = __raw_readl(index);
+ if (value != index) {
+ printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
+ index, value, __raw_readl(index));
+
+ return -1;
+ }
+ }
+
+ index_start += DDR_TEST_BURST_SIZE;
+ if (index_start >= end_address)
+ break;
+
+ if (quick)
+ continue;
+
+ /* Write a pattern for complementary values */
+ for (index = index_start;
+ index < index_start + DDR_TEST_BURST_SIZE;
+ index += 4)
+ __raw_writel((u32)~index, index);
+
+ /* Read and check the pattern */
+ for (index = index_start;
+ index < index_start + DDR_TEST_BURST_SIZE;
+ index += 4) {
+ value = __raw_readl(index);
+ if (value != ~index) {
+ printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
+ index, value, __raw_readl(index));
+
+ return -1;
+ }
+ }
+
+ index_start += DDR_TEST_BURST_SIZE;
+ if (index_start >= end_address)
+ break;
+
+ /* Write a pattern */
+ for (index = index_start;
+ index < index_start + DDR_TEST_BURST_SIZE;
+ index += 2)
+ __raw_writew((u16)index, index);
+
+ /* Read and check the pattern */
+ for (index = index_start;
+ index < index_start + DDR_TEST_BURST_SIZE;
+ index += 2) {
+ value = __raw_readw(index);
+ if (value != (u16)index) {
+ printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
+ index, value, __raw_readw(index));
+
+ return -1;
+ }
+ }
+
+ index_start += DDR_TEST_BURST_SIZE;
+ if (index_start >= end_address)
+ break;
+
+ /* Write a pattern */
+ for (index = index_start;
+ index < index_start + DDR_TEST_BURST_SIZE;
+ index += 1)
+ __raw_writeb((u8)index, index);
+
+ /* Read and check the pattern */
+ for (index = index_start;
+ index < index_start + DDR_TEST_BURST_SIZE;
+ index += 1) {
+ value = __raw_readb(index);
+ if (value != (u8)index) {
+ printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
+ index, value, __raw_readb(index));
+
+ return -1;
+ }
+ }
+
+ index_start += DDR_TEST_BURST_SIZE;
+ if (index_start >= end_address)
+ break;
+ }
+
+ puts("ddr memory test PASSED!\n");
+ return 0;
+}
+
+static int ddr_memory_compare(u32 address1, u32 address2, u32 size)
+{
+ u32 index, value, index2, value2;
+
+ for (index = address1, index2 = address2;
+ index < address1 + size;
+ index += 4, index2 += 4) {
+ value = __raw_readl(index);
+ value2 = __raw_readl(index2);
+
+ if (value != value2) {
+ printf("ddr_memory_test: Compare failed at address = 0x%x value = 0x%x, address2 = 0x%x value2 = 0x%x\n",
+ index, value, index2, value2);
+
+ return -1;
+ }
+ }
+
+ puts("ddr memory compare PASSED!\n");
+ return 0;
+}
+
+static int ddr_memory_ecc_err(u32 base, u32 address, u32 ecc_err)
+{
+ u32 value1, value2, value3;
+
+ puts("Disabling DDR ECC ...\n");
+ ddr3_disable_ecc(base);
+
+ value1 = __raw_readl(address);
+ value2 = value1 ^ ecc_err;
+ __raw_writel(value2, address);
+
+ value3 = __raw_readl(address);
+ printf("ECC err test, addr 0x%x, read data 0x%x, wrote data 0x%x, err pattern: 0x%x, read after write data 0x%x\n",
+ address, value1, value2, ecc_err, value3);
+
+ __raw_writel(ECC_START_ADDR1 | (ECC_END_ADDR1 << 16),
+ base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
+
+ puts("Enabling DDR ECC ...\n");
+ ddr3_enable_ecc(base, 1);
+
+ value1 = __raw_readl(address);
+ printf("ECC err test, addr 0x%x, read data 0x%x\n", address, value1);
+
+ ddr3_check_ecc_int(base);
+ return 0;
+}
+
+static int do_ddr_test(cmd_tbl_t *cmdtp,
+ int flag, int argc, char * const argv[])
+{
+ u32 start_addr, end_addr, size, ecc_err;
+
+ if ((argc == 4) && (strncmp(argv[1], "ecc_err", 8) == 0)) {
+ if (!ddr3_ecc_support_rmw(KS2_DDR3A_EMIF_CTRL_BASE)) {
+ puts("ECC RMW isn't supported for this SOC\n");
+ return 1;
+ }
+
+ start_addr = simple_strtoul(argv[2], NULL, 16);
+ ecc_err = simple_strtoul(argv[3], NULL, 16);
+
+ if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
+ (start_addr > (CONFIG_SYS_SDRAM_BASE +
+ CONFIG_MAX_RAM_BANK_SIZE - 1))) {
+ puts("Invalid address!\n");
+ return cmd_usage(cmdtp);
+ }
+
+ ddr_memory_ecc_err(KS2_DDR3A_EMIF_CTRL_BASE,
+ start_addr, ecc_err);
+ return 0;
+ }
+
+ if (!(((argc == 4) && (strncmp(argv[1], "test", 5) == 0)) ||
+ ((argc == 5) && (strncmp(argv[1], "compare", 8) == 0))))
+ return cmd_usage(cmdtp);
+
+ start_addr = simple_strtoul(argv[2], NULL, 16);
+ end_addr = simple_strtoul(argv[3], NULL, 16);
+
+ if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
+ (start_addr > (CONFIG_SYS_SDRAM_BASE +
+ CONFIG_MAX_RAM_BANK_SIZE - 1)) ||
+ (end_addr < CONFIG_SYS_SDRAM_BASE) ||
+ (end_addr > (CONFIG_SYS_SDRAM_BASE +
+ CONFIG_MAX_RAM_BANK_SIZE - 1)) || (start_addr >= end_addr)) {
+ puts("Invalid start or end address!\n");
+ return cmd_usage(cmdtp);
+ }
+
+ puts("Please wait ...\n");
+ if (argc == 5) {
+ size = simple_strtoul(argv[4], NULL, 16);
+ ddr_memory_compare(start_addr, end_addr, size);
+ } else {
+ ddr_memory_test(start_addr, end_addr, 0);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(ddr, 5, 1, do_ddr_test,
+ "DDR3 test",
+ "test <start_addr in hex> <end_addr in hex> - test DDR from start\n"
+ " address to end address\n"
+ "ddr compare <start_addr in hex> <end_addr in hex> <size in hex> -\n"
+ " compare DDR data of (size) bytes from start address to end\n"
+ " address\n"
+ "ddr ecc_err <addr in hex> <bit_err in hex> - generate bit errors\n"
+ " in DDR data at <addr>, the command will read a 32-bit data\n"
+ " from <addr>, and write (data ^ bit_err) back to <addr>\n"
+);
#include <asm/io.h>
#include <common.h>
+#include <asm/arch/msmc.h>
#include <asm/arch/ddr3.h>
#include <asm/arch/psc_defs.h>
+#include <asm/ti-common/ti-edma3.h>
+
+#define DDR3_EDMA_BLK_SIZE_SHIFT 10
+#define DDR3_EDMA_BLK_SIZE (1 << DDR3_EDMA_BLK_SIZE_SHIFT)
+#define DDR3_EDMA_BCNT 0x8000
+#define DDR3_EDMA_CCNT 1
+#define DDR3_EDMA_XF_SIZE (DDR3_EDMA_BLK_SIZE * DDR3_EDMA_BCNT)
+#define DDR3_EDMA_SLOT_NUM 1
+
void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
{
unsigned int tmp;
__raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET);
}
+int ddr3_ecc_support_rmw(u32 base)
+{
+ u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET);
+
+ /* Check the DDR3 controller ID reg if the controllers
+ supports ECC RMW or not */
+ if (value == 0x40461C02)
+ return 1;
+
+ return 0;
+}
+
+static void ddr3_ecc_config(u32 base, u32 value)
+{
+ u32 data;
+
+ __raw_writel(value, base + KS2_DDR3_ECC_CTRL_OFFSET);
+ udelay(100000); /* delay required to synchronize across clock domains */
+
+ if (value & KS2_DDR3_ECC_EN) {
+ /* Clear the 1-bit error count */
+ data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
+ __raw_writel(data, base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
+
+ /* enable the ECC interrupt */
+ __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
+ KS2_DDR3_WR_ECC_ERR_SYS,
+ base + KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET);
+
+ /* Clear the ECC error interrupt status */
+ __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
+ KS2_DDR3_WR_ECC_ERR_SYS,
+ base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
+ }
+}
+
+static void ddr3_reset_data(u32 base, u32 ddr3_size)
+{
+ u32 mpax[2];
+ u32 seg_num;
+ u32 seg, blks, dst, edma_blks;
+ struct edma3_slot_config slot;
+ struct edma3_channel_config edma_channel;
+ u32 edma_src[DDR3_EDMA_BLK_SIZE/4] __aligned(16) = {0, };
+
+ /* Setup an edma to copy the 1k block to the entire DDR */
+ puts("\nClear entire DDR3 memory to enable ECC\n");
+
+ /* save the SES MPAX regs */
+ msmc_get_ses_mpax(8, 0, mpax);
+
+ /* setup edma slot 1 configuration */
+ slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
+ EDMA3_SLOPT_COMP_CODE(0) |
+ EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC;
+ slot.bcnt = DDR3_EDMA_BCNT;
+ slot.acnt = DDR3_EDMA_BLK_SIZE;
+ slot.ccnt = DDR3_EDMA_CCNT;
+ slot.src_bidx = 0;
+ slot.dst_bidx = DDR3_EDMA_BLK_SIZE;
+ slot.src_cidx = 0;
+ slot.dst_cidx = 0;
+ slot.link = EDMA3_PARSET_NULL_LINK;
+ slot.bcntrld = 0;
+ edma3_slot_configure(KS2_EDMA0_BASE, DDR3_EDMA_SLOT_NUM, &slot);
+
+ /* configure quik edma channel */
+ edma_channel.slot = DDR3_EDMA_SLOT_NUM;
+ edma_channel.chnum = 0;
+ edma_channel.complete_code = 0;
+ /* event trigger after dst update */
+ edma_channel.trigger_slot_word = EDMA3_TWORD(dst);
+ qedma3_start(KS2_EDMA0_BASE, &edma_channel);
+
+ /* DDR3 size in segments (4KB seg size) */
+ seg_num = ddr3_size << (30 - KS2_MSMC_SEG_SIZE_SHIFT);
+
+ for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) {
+ /* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF
+ access slave interface so that edma driver can access */
+ msmc_map_ses_segment(8, 0, base >> KS2_MSMC_SEG_SIZE_SHIFT,
+ KS2_MSMC_DST_SEG_BASE + seg, MPAX_SEG_2G);
+
+ if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM)
+ edma_blks = KS2_MSMC_MAP_SEG_NUM <<
+ (KS2_MSMC_SEG_SIZE_SHIFT
+ - DDR3_EDMA_BLK_SIZE_SHIFT);
+ else
+ edma_blks = (seg_num - seg) << (KS2_MSMC_SEG_SIZE_SHIFT
+ - DDR3_EDMA_BLK_SIZE_SHIFT);
+
+ /* Use edma driver to scrub 2GB DDR memory */
+ for (dst = base, blks = 0; blks < edma_blks;
+ blks += DDR3_EDMA_BCNT, dst += DDR3_EDMA_XF_SIZE) {
+ edma3_set_src_addr(KS2_EDMA0_BASE,
+ edma_channel.slot, (u32)edma_src);
+ edma3_set_dest_addr(KS2_EDMA0_BASE,
+ edma_channel.slot, (u32)dst);
+
+ while (edma3_check_for_transfer(KS2_EDMA0_BASE,
+ &edma_channel))
+ udelay(10);
+ }
+ }
+
+ qedma3_stop(KS2_EDMA0_BASE, &edma_channel);
+
+ /* restore the SES MPAX regs */
+ msmc_set_ses_mpax(8, 0, mpax);
+}
+
+static void ddr3_ecc_init_range(u32 base)
+{
+ u32 ecc_val = KS2_DDR3_ECC_EN;
+ u32 rmw = ddr3_ecc_support_rmw(base);
+
+ if (rmw)
+ ecc_val |= KS2_DDR3_ECC_RMW_EN;
+
+ __raw_writel(0, base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
+
+ ddr3_ecc_config(base, ecc_val);
+}
+
+void ddr3_enable_ecc(u32 base, int test)
+{
+ u32 ecc_val = KS2_DDR3_ECC_ENABLE;
+ u32 rmw = ddr3_ecc_support_rmw(base);
+
+ if (test)
+ ecc_val |= KS2_DDR3_ECC_ADDR_RNG_1_EN;
+
+ if (!rmw) {
+ if (!test)
+ /* by default, disable ecc when rmw = 0 and no
+ ecc test */
+ ecc_val = 0;
+ } else {
+ ecc_val |= KS2_DDR3_ECC_RMW_EN;
+ }
+
+ ddr3_ecc_config(base, ecc_val);
+}
+
+void ddr3_disable_ecc(u32 base)
+{
+ ddr3_ecc_config(base, 0);
+}
+
+#if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
+static void cic_init(u32 base)
+{
+ /* Disable CIC global interrupts */
+ __raw_writel(0, base + KS2_CIC_GLOBAL_ENABLE);
+
+ /* Set to normal mode, no nesting, no priority hold */
+ __raw_writel(0, base + KS2_CIC_CTRL);
+ __raw_writel(0, base + KS2_CIC_HOST_CTRL);
+
+ /* Enable CIC global interrupts */
+ __raw_writel(1, base + KS2_CIC_GLOBAL_ENABLE);
+}
+
+static void cic_map_cic_to_gic(u32 base, u32 chan_num, u32 irq_num)
+{
+ /* Map the system interrupt to a CIC channel */
+ __raw_writeb(chan_num, base + KS2_CIC_CHAN_MAP(0) + irq_num);
+
+ /* Enable CIC system interrupt */
+ __raw_writel(irq_num, base + KS2_CIC_SYS_ENABLE_IDX_SET);
+
+ /* Enable CIC Host interrupt */
+ __raw_writel(chan_num, base + KS2_CIC_HOST_ENABLE_IDX_SET);
+}
+
+static void ddr3_map_ecc_cic2_irq(u32 base)
+{
+ cic_init(base);
+ cic_map_cic_to_gic(base, KS2_CIC2_DDR3_ECC_CHAN_NUM,
+ KS2_CIC2_DDR3_ECC_IRQ_NUM);
+}
+#endif
+
+void ddr3_init_ecc(u32 base)
+{
+ u32 ddr3_size;
+
+ if (!ddr3_ecc_support_rmw(base)) {
+ ddr3_disable_ecc(base);
+ return;
+ }
+
+ ddr3_ecc_init_range(base);
+ ddr3_size = ddr3_get_size();
+ ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size);
+
+ /* mapping DDR3 ECC system interrupt from CIC2 to GIC */
+#if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
+ ddr3_map_ecc_cic2_irq(KS2_CIC2_BASE);
+#endif
+ ddr3_enable_ecc(base, 0);
+}
+
+void ddr3_check_ecc_int(u32 base)
+{
+ char *env;
+ int ecc_test = 0;
+ u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
+
+ env = getenv("ecc_test");
+ if (env)
+ ecc_test = simple_strtol(env, NULL, 0);
+
+ if (value & KS2_DDR3_WR_ECC_ERR_SYS)
+ puts("DDR3 ECC write error interrupted\n");
+
+ if (value & KS2_DDR3_2B_ECC_ERR_SYS) {
+ puts("DDR3 ECC 2-bit error interrupted\n");
+
+ if (!ecc_test) {
+ puts("Reseting the device ...\n");
+ reset_cpu(0);
+ }
+ }
+
+ value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
+ if (value) {
+ printf("1-bit ECC err count: 0x%x\n", value);
+ value = __raw_readl(base +
+ KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET);
+ printf("1-bit ECC err address log: 0x%x\n", value);
+ }
+}
+
void ddr3_reset_ddrphy(void)
{
u32 tmp;
#include <asm/arch/msmc.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/psc_defs.h>
void chip_configuration_unlock(void)
{
__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
}
+#ifdef CONFIG_SOC_K2L
+void osr_init(void)
+{
+ u32 i;
+ u32 j;
+ u32 val;
+ u32 base = KS2_OSR_CFG_BASE;
+ u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
+
+ /* Enable the OSR clock domain */
+ psc_enable_module(KS2_LPSC_OSR);
+
+ /* Disable OSR ECC check for all the ram banks */
+ for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
+ val = i | KS2_OSR_ECC_VEC_TRIG_RD |
+ (KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);
+
+ writel(val , base + KS2_OSR_ECC_VEC);
+
+ /**
+ * wait till read is done.
+ * Print should be added after earlyprintk support is added.
+ */
+ for (j = 0; j < 10000; j++) {
+ val = readl(base + KS2_OSR_ECC_VEC);
+ if (val & KS2_OSR_ECC_VEC_RD_DONE)
+ break;
+ }
+
+ ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
+ KS2_OSR_ECC_CTRL_CHK;
+
+ writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
+ writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
+ }
+
+ /* Reset OSR memory to all zeros */
+ for (i = 0; i < KS2_OSR_SIZE; i += 4)
+ writel(0, KS2_OSR_DATA_BASE + i);
+
+ /* Enable OSR ECC check for all the ram banks */
+ for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
+ writel(ecc_ctrl[i] |
+ KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
+}
+#endif
+
int arch_cpu_init(void)
{
chip_configuration_unlock();
icache_enable();
- msmc_share_all_segments(8); /* TETRIS */
- msmc_share_all_segments(9); /* NETCP */
- msmc_share_all_segments(10); /* QM PDSP */
- msmc_share_all_segments(11); /* PCIE 0 */
-#ifdef CONFIG_SOC_K2E
- msmc_share_all_segments(13); /* PCIE 1 */
+ msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS);
+ msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
+ msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
+ msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
+#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
+ msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
+#endif
+#ifdef CONFIG_SOC_K2L
+ osr_init();
#endif
/*
msmc->ses[priv_id][j].mpaxh &= 0xffffff7ful;
}
}
+
+void msmc_map_ses_segment(int priv_id, int ses_pair,
+ u32 src_pfn, u32 dst_pfn, enum mpax_seg_size size)
+{
+ struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
+
+ msmc->ses[priv_id][ses_pair].mpaxh = src_pfn << 12 |
+ (size & 0x1f) | 0x80;
+ msmc->ses[priv_id][ses_pair].mpaxl = dst_pfn << 8 | 0x3f;
+}
+
+void msmc_get_ses_mpax(int priv_id, int ses_pair, u32 *mpax)
+{
+ struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
+
+ *mpax++ = msmc->ses[priv_id][ses_pair].mpaxl;
+ *mpax = msmc->ses[priv_id][ses_pair].mpaxh;
+}
+
+void msmc_set_ses_mpax(int priv_id, int ses_pair, u32 *mpax)
+{
+ struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
+
+ msmc->ses[priv_id][ses_pair].mpaxl = *mpax++;
+ msmc->ses[priv_id][ses_pair].mpaxh = *mpax;
+}
+++ /dev/null
-/*
- * common spl init code
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <config.h>
-#include <ns16550.h>
-#include <malloc.h>
-#include <spl.h>
-#include <spi_flash.h>
-
-#include <asm/u-boot.h>
-#include <asm/utils.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_K2HK_EVM
-static struct pll_init_data spl_pll_config[] = {
- CORE_PLL_799,
- TETRIS_PLL_500,
-};
-#endif
-
-#ifdef CONFIG_K2E_EVM
-static struct pll_init_data spl_pll_config[] = {
- CORE_PLL_800,
-};
-#endif
-
-void spl_init_keystone_plls(void)
-{
- init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
-}
-
-void spl_board_init(void)
-{
- spl_init_keystone_plls();
- preloader_console_init();
-}
-
-u32 spl_boot_device(void)
-{
-#if defined(CONFIG_SPL_SPI_LOAD)
- return BOOT_DEVICE_SPI;
-#else
- puts("Unknown boot device\n");
- hang();
-#endif
-}
u32 reg, perclk_podf;
reg = __raw_readl(&imx_ccm->cscmr1);
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+ if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
+ return MXC_HCLK; /* OSC 24Mhz */
+#endif
perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
return get_ipg_clk() / (perclk_podf + 1);
#include <common.h>
#include <asm/armv7.h>
+#include <asm/bootm.h>
#include <asm/pl310.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <stdbool.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
+#include <asm/bootm.h>
enum ldo_reg {
LDO_ARM,
writel(0, &mxc_ccm->ccdr);
}
+#ifdef CONFIG_MX6SL
+static void set_preclk_from_osc(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ u32 reg;
+
+ reg = readl(&mxc_ccm->cscmr1);
+ reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
+ writel(reg, &mxc_ccm->cscmr1);
+}
+#endif
+
int arch_cpu_init(void)
{
init_aips();
if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
set_ahb_rate(132000000);
+ /* Set perclk to source from OSC 24MHz */
+#if defined(CONFIG_MX6SL)
+ set_preclk_from_osc();
+#endif
+
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
#ifdef CONFIG_APBH_DMA
if (val == MMCSD_MODE_RAW)
return MMCSD_MODE_RAW;
- else if (val == MMCSD_MODE_FAT)
- return MMCSD_MODE_FAT;
+ else if (val == MMCSD_MODE_FS)
+ return MMCSD_MODE_FS;
else
#ifdef CONFIG_SUPPORT_EMMC_BOOT
return MMCSD_MODE_EMMCBOOT;
config TARGET_AM3517_EVM
bool "AM3517 EVM"
+ select SUPPORT_SPL
config TARGET_MT_VENTOUX
bool "TeeJet Mt.Ventoux"
+ select SUPPORT_SPL
config TARGET_OMAP3_SDP3430
bool "TI OMAP3430 SDP"
config TARGET_OMAP3_BEAGLE
bool "TI OMAP3 BeagleBoard"
+ select SUPPORT_SPL
config TARGET_CM_T35
- bool "CompuLab CM-T35"
+ bool "CompuLab CM-T3530 and CM-T3730 boards"
+ select SUPPORT_SPL
+
+config TARGET_CM_T3517
+ bool "CompuLab CM-T3517 boards"
config TARGET_DEVKIT8000
bool "TimLL OMAP3 Devkit8000"
+ select SUPPORT_SPL
config TARGET_OMAP3_EVM
bool "TI OMAP3 EVM"
+ select SUPPORT_SPL
config TARGET_OMAP3_EVM_QUICK_MMC
bool "TI OMAP3 EVM Quick MMC"
+ select SUPPORT_SPL
config TARGET_OMAP3_EVM_QUICK_NAND
bool "TI OMAP3 EVM Quick NAND"
+ select SUPPORT_SPL
config TARGET_OMAP3_IGEP00X0
bool "IGEP"
+ select SUPPORT_SPL
config TARGET_OMAP3_OVERO
bool "OMAP35xx Gumstix Overo"
+ select SUPPORT_SPL
config TARGET_OMAP3_ZOOM1
bool "TI Zoom1"
config TARGET_AM3517_CRANE
bool "am3517_crane"
+ select SUPPORT_SPL
config TARGET_OMAP3_PANDORA
bool "OMAP3 Pandora"
config TARGET_ECO5PK
bool "ECO5PK"
+ select SUPPORT_SPL
config TARGET_DIG297
bool "DIG297"
config TARGET_TRICORDER
bool "Tricorder"
+ select SUPPORT_SPL
config TARGET_MCX
bool "MCX"
+ select SUPPORT_SPL
config TARGET_OMAP3_LOGIC
bool "OMAP3 Logic"
config TARGET_TAO3530
bool "TAO3530"
+ select SUPPORT_SPL
config TARGET_TWISTER
bool "Twister"
+ select SUPPORT_SPL
endchoice
-config SYS_CPU
- default "armv7"
-
config SYS_SOC
default "omap3"
source "board/ti/sdp3430/Kconfig"
source "board/ti/beagle/Kconfig"
source "board/compulab/cm_t35/Kconfig"
+source "board/compulab/cm_t3517/Kconfig"
source "board/timll/devkit8000/Kconfig"
source "board/ti/evm/Kconfig"
source "board/isee/igep00x0/Kconfig"
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <dm.h>
+#include <mmc.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/cache.h>
#include <asm/armv7.h>
-#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
#include <asm/omap_common.h>
#include <asm/arch/mmc_host_def.h>
#include <i2c.h>
static void omap3_invalidate_l2_cache_secure(void);
#endif
+#ifdef CONFIG_DM_GPIO
+static const struct omap_gpio_platdata omap34xx_gpio[] = {
+ { 0, OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
+ { 1, OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
+ { 2, OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
+ { 3, OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
+ { 4, OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
+ { 5, OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
+};
+
+U_BOOT_DEVICES(am33xx_gpios) = {
+ { "gpio_omap", &omap34xx_gpio[0] },
+ { "gpio_omap", &omap34xx_gpio[1] },
+ { "gpio_omap", &omap34xx_gpio[2] },
+ { "gpio_omap", &omap34xx_gpio[3] },
+ { "gpio_omap", &omap34xx_gpio[4] },
+ { "gpio_omap", &omap34xx_gpio[5] },
+};
+
+#else
+
static const struct gpio_bank gpio_bank_34xx[6] = {
{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
+#endif
+
#ifdef CONFIG_SPL_BUILD
/*
* We use static variables because global data is not ready yet.
case BOOT_DEVICE_MMC2:
return MMCSD_MODE_RAW;
case BOOT_DEVICE_MMC1:
- return MMCSD_MODE_FAT;
+ return MMCSD_MODE_FS;
break;
default:
puts("spl: ERROR: unknown device - can't select boot mode\n");
* Routine: wait_for_command_complete
* Description: Wait for posting to finish on watchdog
*****************************************************************************/
-void wait_for_command_complete(struct watchdog *wd_base)
+static void wait_for_command_complete(struct watchdog *wd_base)
{
int pending = 1;
do {
* - Init the emif4 module for DDR access
* - Early init routines, called from flash or SRAM.
*/
-void do_emif4_init(void)
+static void do_emif4_init(void)
{
unsigned int regval;
/* Set the DDR PHY parameters in PHY ctrl registers */
#include <asm/io.h>
#include <asm/arch/mem.h> /* get mem tables */
#include <asm/arch/sys_proto.h>
+#include <asm/bootm.h>
+
#include <i2c.h>
#include <linux/compiler.h>
/********************************************************
* get_base(); get upper addr of current execution
*******************************************************/
-u32 get_base(void)
+static u32 get_base(void)
{
u32 val;
endchoice
-config SYS_CPU
- default "armv7"
-
config SYS_SOC
default "omap4"
endchoice
-config SYS_CPU
- default "armv7"
-
config SYS_SOC
default "omap5"
endchoice
-config SYS_CPU
- default "armv7"
-
config SYS_SOC
default "rmobile"
+config RMOBILE_EXTRAM_BOOT
+ bool "Enable boot from RAM"
+ depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER
+ default n
+
source "board/atmark-techno/armadillo-800eva/Kconfig"
source "board/renesas/koelsch/Kconfig"
source "board/renesas/lager/Kconfig"
cmp r1, #3 /* has already been set up */
bicne r0, r0, #0xe7
orrne r0, r0, #0x83 /* L2CTLR[7:6] + L2CTLR[2:0] */
-
- ldr r2, =0xFF000044 /* PRR */
- ldr r1, [r2]
- and r1, r1, #0x7F00
- lsrs r1, r1, #8
- cmp r1, #0x45 /* 0x45 is ID of r8a7790 */
- bne L2CTLR_5_SKIP
+#if defined(CONFIG_R8A7790)
orrne r0, r0, #0x20 /* L2CTLR[5] */
-L2CTLR_5_SKIP:
+#endif
mcrne p15, 1, r0, c9, c0, 2
-
_exit_init_l2_a15:
ldr r3, =(CONFIG_SYS_INIT_SP_ADDR)
sub sp, r3, #4
endchoice
-config SYS_CPU
- default "armv7"
-
config SYS_SOC
default "s5pc1xx"
static uint32_t iswgrp_handoff[8];
-int misc_init_r(void)
+int arch_early_init_r(void)
{
int i;
for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
. = ALIGN(4);
__bss_end = .;
} >.sdram
-
- . = ALIGN(8);
- __malloc_start = .;
- . = . + CONFIG_SPL_MALLOC_SIZE;
- __malloc_end = .;
-
- . = . + CONFIG_SPL_STACK_SIZE;
- . = ALIGN(8);
- __stack_start = .;
}
mcr p15, 0, r0, c7, c10, 4 @ DSB
mcr p15, 0, r0, c7, c5, 4 @ ISB
#endif
-/*
- * Move vector table
- */
- /* Set vector address in CP15 VBAR register */
- ldr r0, =_start
- mcr p15, 0, r0, c12, c0, 0 @Set VBAR
bx lr
obj-y += board.o
obj-y += clock.o
obj-y += pinmux.o
-obj-$(CONFIG_SUN4I) += clock_sun4i.o
-obj-$(CONFIG_SUN5I) += clock_sun4i.o
-obj-$(CONFIG_SUN7I) += clock_sun4i.o
+obj-$(CONFIG_MACH_SUN6I) += prcm.o
+obj-$(CONFIG_MACH_SUN8I) += prcm.o
+obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
+obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
+obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
+obj-$(CONFIG_MACH_SUN7I) += clock_sun4i.o
+obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o
ifndef CONFIG_SPL_BUILD
obj-y += cpu_info.o
endif
ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_SUN4I) += dram.o
-obj-$(CONFIG_SUN5I) += dram.o
-obj-$(CONFIG_SUN7I) += dram.o
+obj-$(CONFIG_MACH_SUN4I) += dram.o
+obj-$(CONFIG_MACH_SUN5I) += dram.o
+obj-$(CONFIG_MACH_SUN7I) += dram.o
ifdef CONFIG_SPL_FEL
obj-y += start.o
endif
int gpio_init(void)
{
-#if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
+#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+ /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
+#endif
+ sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX);
+ sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
+#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
- sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
+ sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
- sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
-#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
+ sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX);
+ sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
- sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
+ sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX);
+ sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
#else
#error Unsupported console port number. Please fix pin mux settings in board.c
#endif
void reset_cpu(ulong addr)
{
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
static const struct sunxi_wdog *wdog =
&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
/* sun5i sometimes gets stuck without this */
writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
}
+#else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || .. */
+ static const struct sunxi_wdog *wdog =
+ ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
+
+ /* Set the watchdog for its shortest interval (.5s) and wait */
+ writel(WDT_CFG_RESET, &wdog->cfg);
+ writel(WDT_MODE_EN, &wdog->mode);
+ writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
+#endif
}
/* do some early init */
void s_init(void)
{
-#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || defined CONFIG_SUN6I)
+#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
+ defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
asm volatile(
"mrc p15, 0, r0, c1, c0, 1\n"
APB0_DIV_1 << APB0_DIV_SHIFT |
CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
&ccm->cpu_ahb_apb0_cfg);
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
#endif
writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
}
#endif
+unsigned int clock_get_pll5p(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ uint32_t rval = readl(&ccm->pll5_cfg);
+ int n = ((rval & CCM_PLL5_CTRL_N_MASK) >> CCM_PLL5_CTRL_N_SHIFT);
+ int k = ((rval & CCM_PLL5_CTRL_K_MASK) >> CCM_PLL5_CTRL_K_SHIFT) + 1;
+ int p = ((rval & CCM_PLL5_CTRL_P_MASK) >> CCM_PLL5_CTRL_P_SHIFT);
+ return (24000000 * n * k) >> p;
+}
+
unsigned int clock_get_pll6(void)
{
struct sunxi_ccm_reg *const ccm =
--- /dev/null
+/*
+ * sun6i specific clock code
+ *
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/sys_proto.h>
+
+void clock_init_uart(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+#if CONFIG_CONS_INDEX < 5
+ /* uart clock source is apb2 */
+ writel(APB2_CLK_SRC_OSC24M|
+ APB2_CLK_RATE_N_1|
+ APB2_CLK_RATE_M(1),
+ &ccm->apb2_div);
+
+ /* open the clock for uart */
+ setbits_le32(&ccm->apb2_gate,
+ CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
+ CONFIG_CONS_INDEX - 1));
+
+ /* deassert uart reset */
+ setbits_le32(&ccm->apb2_reset_cfg,
+ 1 << (APB2_RESET_UART_SHIFT +
+ CONFIG_CONS_INDEX - 1));
+#else
+ /* enable R_PIO and R_UART clocks, and de-assert resets */
+ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
+#endif
+
+ /* Dup with clock_init_safe(), drop once sun6i SPL support lands */
+ writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+}
+
+int clock_twi_onoff(int port, int state)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ if (port > 3)
+ return -1;
+
+ /* set the apb clock gate for twi */
+ if (state)
+ setbits_le32(&ccm->apb2_gate,
+ CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
+ else
+ clrbits_le32(&ccm->apb2_gate,
+ CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
+
+ return 0;
+}
+
+unsigned int clock_get_pll6(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ uint32_t rval = readl(&ccm->pll6_cfg);
+ int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
+ int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
+ return 24000000 * n * k / 2;
+}
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
puts("CPU: Allwinner A10 (SUN4I)\n");
-#elif defined CONFIG_SUN5I
+#elif defined CONFIG_MACH_SUN5I
u32 val = readl(SUNXI_SID_BASE + 0x08);
switch ((val >> 12) & 0xf) {
case 0: puts("CPU: Allwinner A12 (SUN5I)\n"); break;
case 7: puts("CPU: Allwinner A10s (SUN5I)\n"); break;
default: puts("CPU: Allwinner A1X (SUN5I)\n");
}
-#elif defined CONFIG_SUN7I
+#elif defined CONFIG_MACH_SUN6I
+ puts("CPU: Allwinner A31 (SUN6I)\n");
+#elif defined CONFIG_MACH_SUN7I
puts("CPU: Allwinner A20 (SUN7I)\n");
+#elif defined CONFIG_MACH_SUN8I
+ puts("CPU: Allwinner A23 (SUN8I)\n");
#else
#warning Please update cpu_info.c with correct CPU information
puts("CPU: SUNXI Family\n");
struct sunxi_dram_reg *dram =
(struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
struct sunxi_timer_reg *timer =
(struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
u32 reg_val;
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),
#else
clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3),
}
static u32 hpcr_value[32] = {
-#ifdef CONFIG_SUN5I
+#ifdef CONFIG_MACH_SUN5I
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0x0301, 0x0301, 0x0301, 0x0301,
0x0301, 0x0301, 0x0301, 0
#endif
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
0x0301, 0x0301, 0x0301, 0x0301,
0x0301, 0x0301, 0, 0,
0, 0, 0, 0,
0x1035, 0x1031, 0x0731, 0x1035,
0x1031, 0x0301, 0x0301, 0x0731
#endif
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
0x0301, 0x0301, 0x0301, 0x0301,
0x0301, 0x0301, 0x0301, 0x0301,
0, 0, 0, 0,
{
u32 reg_val;
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- /* PLL5P and PLL6 are the potential clock sources for MBUS */
- u32 pll6x_div, pll5p_div;
- u32 pll6x_clk = clock_get_pll6() / 1000000;
- u32 pll5p_clk = clk / 24 * 48;
+ u32 pll5p_clk, pll6x_clk;
+ u32 pll5p_div, pll6x_div;
u32 pll5p_rate, pll6x_rate;
-#ifdef CONFIG_SUN7I
- pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */
-#endif
/* setup DRAM PLL */
reg_val = readl(&ccm->pll5_cfg);
reg_val &= ~CCM_PLL5_CTRL_K_MASK; /* set K to 0 (x1) */
reg_val &= ~CCM_PLL5_CTRL_N_MASK; /* set N to 0 (x0) */
reg_val &= ~CCM_PLL5_CTRL_P_MASK; /* set P to 0 (x1) */
+#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT
+ /* Old kernels are hardcoded to P=1 (divide by 2) */
+ reg_val |= CCM_PLL5_CTRL_P(1);
+#endif
if (clk >= 540 && clk < 552) {
- /* dram = 540MHz, pll5p = 1080MHz */
- pll5p_clk = 1080;
+ /* dram = 540MHz */
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15));
} else if (clk >= 512 && clk < 528) {
- /* dram = 512MHz, pll5p = 1536MHz */
- pll5p_clk = 1536;
+ /* dram = 512MHz */
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(4));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16));
} else if (clk >= 496 && clk < 504) {
- /* dram = 496MHz, pll5p = 1488MHz */
- pll5p_clk = 1488;
+ /* dram = 496MHz */
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31));
} else if (clk >= 468 && clk < 480) {
- /* dram = 468MHz, pll5p = 936MHz */
- pll5p_clk = 936;
+ /* dram = 468MHz */
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13));
} else if (clk >= 396 && clk < 408) {
- /* dram = 396MHz, pll5p = 792MHz */
- pll5p_clk = 792;
+ /* dram = 396MHz */
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11));
setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK);
-#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
/* reset GPS */
clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE);
setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
/* setup MBUS clock */
if (!mbus_clk)
mbus_clk = 300;
+
+ /* PLL5P and PLL6 are the potential clock sources for MBUS */
+ pll6x_clk = clock_get_pll6() / 1000000;
+#ifdef CONFIG_MACH_SUN7I
+ pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */
+#endif
+ pll5p_clk = clock_get_pll5p() / 1000000;
pll6x_div = DIV_ROUND_UP(pll6x_clk, mbus_clk);
pll5p_div = DIV_ROUND_UP(pll5p_clk, mbus_clk);
pll6x_rate = pll6x_clk / pll6x_div;
* open DRAMC AHB & DLL register clock
* close it first
*/
-#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
#else
clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
udelay(22);
/* then open it */
-#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
#else
setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
static void dramc_clock_output_en(u32 on)
{
-#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
if (on)
else
clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
#endif
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
if (on)
setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
u32 reg_val;
u32 zprog = zq & 0xFF, zdata = (zq >> 8) & 0xFFFFF;
-#ifndef CONFIG_SUN7I
+#ifndef CONFIG_MACH_SUN7I
/* Appears that some kind of automatically initiated default
* ZQ calibration is already in progress at this point on sun4i/sun5i
* hardware, but not on sun7i. So it is reasonable to wait for its
if (!odt_en)
return;
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
/* Enabling ODT in SDR_IOCR on sun7i hardware results in a deadlock
* unless bit 24 is set in SDR_ZQCR1. Not much is known about the
* SDR_ZQCR1 register, but there are hints indicating that it might
/* dram clock off */
dramc_clock_output_en(0);
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
/* select dram controller 1 */
writel(DRAM_CSEL_MAGIC, &dram->csel);
#endif
writel(para->tpr2, &dram->tpr2);
reg_val = DRAM_MR_BURST_LENGTH(0x0);
-#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I))
+#if (defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I))
reg_val |= DRAM_MR_POWER_DOWN;
#endif
reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);
/* disable drift compensation and set passive DQS window mode */
clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
/* Command rate timing mode 2T & 1T */
if (para->tpr4 & 0x1)
setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T);
/* try to autodetect the DRAM bus width and density */
para->io_width = 16;
para->bus_width = 32;
-#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I)
/* only A0-A14 address lines on A10/A13, limiting max density to 4096 */
para->density = 4096;
#else
#include <asm/io.h>
#include <asm/arch/gpio.h>
-int sunxi_gpio_set_cfgpin(u32 pin, u32 val)
+void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
{
- u32 bank = GPIO_BANK(pin);
- u32 index = GPIO_CFG_INDEX(pin);
- u32 offset = GPIO_CFG_OFFSET(pin);
- struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+ u32 index = GPIO_CFG_INDEX(bank_offset);
+ u32 offset = GPIO_CFG_OFFSET(bank_offset);
clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset);
-
- return 0;
}
-int sunxi_gpio_get_cfgpin(u32 pin)
+void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
{
- u32 cfg;
u32 bank = GPIO_BANK(pin);
- u32 index = GPIO_CFG_INDEX(pin);
- u32 offset = GPIO_CFG_OFFSET(pin);
struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+ sunxi_gpio_set_cfgbank(pio, pin, val);
+}
+
+int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
+{
+ u32 index = GPIO_CFG_INDEX(bank_offset);
+ u32 offset = GPIO_CFG_OFFSET(bank_offset);
+ u32 cfg;
+
cfg = readl(&pio->cfg[0] + index);
cfg >>= offset;
return cfg & 0xf;
}
+int sunxi_gpio_get_cfgpin(u32 pin)
+{
+ u32 bank = GPIO_BANK(pin);
+ struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+ return sunxi_gpio_get_cfgbank(pio, pin);
+}
+
int sunxi_gpio_set_drv(u32 pin, u32 val)
{
u32 bank = GPIO_BANK(pin);
--- /dev/null
+/*
+ * Sunxi A31 Power Management Unit
+ *
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ * http://linux-sunxi.org
+ *
+ * Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work
+ *
+ * (C) Copyright 2006-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/sys_proto.h>
+
+/* APB0 clock gate and reset bit offsets are the same. */
+void prcm_apb0_enable(u32 flags)
+{
+ struct sunxi_prcm_reg *prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+ /* open the clock for module */
+ setbits_le32(&prcm->apb0_gate, flags);
+
+ /* deassert reset for module */
+ setbits_le32(&prcm->apb0_reset, flags);
+}
writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
}
-int setup_window(struct disp_ctl_win *win, struct fdt_disp_config *config)
+static int setup_window(struct disp_ctl_win *win,
+ struct fdt_disp_config *config)
{
win->x = 0;
win->y = 0;
menu "Panasonic UniPhier platform"
depends on ARCH_UNIPHIER
-config SYS_CPU
- string
- default "armv7"
-
config SYS_SOC
- string
default "uniphier"
config SYS_CONFIG_NAME
- string
default "ph1_pro4" if MACH_PH1_PRO4
default "ph1_ld4" if MACH_PH1_LD4
default "ph1_sld8" if MACH_PH1_SLD8
endchoice
+config CMD_PINMON
+ bool "Enable boot mode pins monitor command"
+ depends on !SPL_BUILD
+ default y
+ help
+ The command "pinmon" shows the state of the boot mode pins.
+ The boot mode pins are latched when the system reset is deasserted
+ and determine which device the system should load a boot image from.
+
endmenu
obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
obj-$(CONFIG_UNIPHIER_SMP) += smp.o
-obj-$(if $(CONFIG_SPL_BUILD),,y) += cmd_pinmon.o
+obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
obj-y += board_common.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o
#
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
+obj-y += platdevice.o
obj-y += boot-mode.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/platdevice.h>
+
+#define UART_MASTER_CLK 36864000
+
+SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
+SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
+SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
+SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
#
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
+obj-y += platdevice.o
obj-y += boot-mode.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o sbc_init.o \
sg_init.o pll_init.o clkrst_init.o pinctrl.o
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/platdevice.h>
+
+#define UART_MASTER_CLK 73728000
+
+SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
+SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
+SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
+SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
#
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
+obj-y += platdevice.o
obj-y += boot-mode.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/platdevice.h>
+
+#define UART_MASTER_CLK 80000000
+
+SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
+SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
+SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
+SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
endchoice
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "zynq"
* first stage bootloader. To get ECC to work all memory has
* been initialized by writing any value.
*/
+ /* cppcheck-suppress nullPointer */
memset((void *)0, 0, 1 * 1024 * 1024);
} else {
puts("ECC disabled ");
#ifdef CONFIG_SPL_MMC_SUPPORT
u32 spl_boot_mode(void)
{
- return MMCSD_MODE_FAT;
+ return MMCSD_MODE_FS;
}
#endif
switch (spl_boot_device()) {
#ifdef CONFIG_SYS_USE_MMC
case BOOT_DEVICE_MMC1:
- return MMCSD_MODE_FAT;
+ return MMCSD_MODE_FS;
break;
#endif
case BOOT_DEVICE_NONE:
#include <common.h>
#include <linux/ctype.h>
-void upstring(char *s)
+static void upstring(char *s)
{
while (*s) {
*s = toupper(*s);
+dtb-$(CONFIG_MACH_SUN7I) += sun7i-a20-pcduino3.dtb
dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
model = "TI AM335x BeagleBone";
compatible = "ti,am335x-bone", "ti,am33xx";
+ chosen {
+ stdout-path = &uart0;
+ };
+
cpus {
cpu@0 {
cpu0-supply = <&dcdc2_reg>;
+++ /dev/null
-/*
- * This header provides constants for most GPIO bindings.
- *
- * Most GPIO bindings include a flags cell as part of the GPIO specifier.
- * In most cases, the format of the flags cell uses the standard values
- * defined in this header.
- */
-
-#ifndef _DT_BINDINGS_GPIO_GPIO_H
-#define _DT_BINDINGS_GPIO_GPIO_H
-
-#define GPIO_ACTIVE_HIGH 0
-#define GPIO_ACTIVE_LOW 1
-
-#endif
pinctrl_1: pinctrl@11000000 {
#address-cells = <1>;
#size-cells = <0>;
- gpy0: gpy0 {
+ gpx0: gpx0 {
reg = <0xc00>;
};
};
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
- pwr-gpios = <&gpio 0xA2 0>;
+ pwr-gpios = <&gpio 146 0>;
};
sdhci@12520000 {
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
- cd-gpios = <&gpio 0x39C 0>;
+ cd-gpios = <&gpio 284 0>;
};
sdhci@12540000 {
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
- pwr-gpios = <&gpio 0xA2 0>;
+ pwr-gpios = <&gpio 146 0>;
};
sdhci@12520000 {
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
- cd-gpios = <&gpio 0x39C 0>;
+ cd-gpios = <&gpio 284 0>;
};
sdhci@12540000 {
*/
/dts-v1/;
-#include "exynos4.dtsi"
+#include "exynos4412.dtsi"
/ {
model = "Odroid based on Exynos4412";
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
- cd-gpios = <&gpio 0xC2 0>;
+ cd-gpios = <&gpio 122 0>;
};
sdhci@12540000 {
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
- pwr-gpios = <&gpio 0xB2 0>;
+ pwr-gpios = <&gpio 0x6a 0>;
status = "disabled";
};
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
- cd-gpios = <&gpio 0x3BC 0>;
+ cd-gpios = <&gpio 0x7a 0>;
};
sdhci@12540000 {
dwmmc@12550000 {
samsung,bus-width = <8>;
samsung,timing = <2 1 0>;
- pwr-gpios = <&gpio 0xB2 0>;
+ pwr-gpios = <&gpio 0x6a 0>;
fifoth_val = <0x203f0040>;
bus_hz = <400000000>;
div = <0x3>;
#address-cells = <1>;
#size-cells = <0>;
gpf0: gpf0 {
- reg = <0xc180>;
+ reg = <0x180>;
};
gpj0: gpj0 {
reg = <0x240>;
gpm0: gpm0 {
reg = <0x260>;
};
- gpy0: gpy0 {
- reg = <0x120>;
- };
gpx0: gpx0 {
reg = <0xc00>;
};
#interrupt-cells = <2>;
};
- gpm0: gpm0 {
+ gpy0: gpy0 {
gpio-controller;
#gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
};
- gpm1: gpm1 {
+ gpy1: gpy1 {
gpio-controller;
#gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
};
- gpm2: gpm2 {
+ gpy2: gpy2 {
gpio-controller;
#gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
};
- gpm3: gpm3 {
+ gpy3: gpy3 {
gpio-controller;
#gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
};
- gpm4: gpm4 {
+ gpy4: gpy4 {
gpio-controller;
#gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
};
- gpy0: gpy0 {
+ gpy5: gpy5 {
gpio-controller;
#gpio-cells = <2>;
};
- gpy1: gpy1 {
+ gpy6: gpy6 {
gpio-controller;
#gpio-cells = <2>;
};
- gpy2: gpy2 {
+ gpm0: gpm0 {
gpio-controller;
#gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
- gpy3: gpy3 {
+ gpm1: gpm1 {
gpio-controller;
#gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
- gpy4: gpy4 {
+ gpm2: gpm2 {
gpio-controller;
#gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
- gpy5: gpy5 {
+ gpm3: gpm3 {
gpio-controller;
#gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
- gpy6: gpy6 {
+ gpm4: gpm4 {
gpio-controller;
#gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpx0: gpx0 {
--- /dev/null
+/*
+ * Copyright 2014 Zoltan HERPAI
+ * Zoltan HERPAI <wigyori@uid0.hu>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "sun7i-a20.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "LinkSprite pcDuino3";
+ compatible = "linksprite,pcduino3", "allwinner,sun7i-a20";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ soc@01c00000 {
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 0>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+ };
+
+ usbphy: phy@01c13400 {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+ };
+
+ ehci0: usb@01c14000 {
+ status = "okay";
+ };
+
+ ohci0: usb@01c14400 {
+ status = "okay";
+ };
+
+ ahci: sata@01c18000 {
+ target-supply = <®_ahci_5v>;
+ status = "okay";
+ };
+
+ ehci1: usb@01c1c000 {
+ status = "okay";
+ };
+
+ ohci1: usb@01c1c400 {
+ status = "okay";
+ };
+
+ pinctrl@01c20800 {
+ ahci_pwr_pin_a: ahci_pwr_pin@0 {
+ allwinner,pins = "PH2";
+ };
+
+ led_pins_pcduino3: led_pins@0 {
+ allwinner,pins = "PH15", "PH16";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ key_pins_pcduino3: key_pins@0 {
+ allwinner,pins = "PH17", "PH18", "PH19";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+ };
+
+ ir0: ir@01c21800 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_pins_a>;
+ status = "okay";
+ };
+
+ uart0: serial@01c28000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+ };
+
+ i2c0: i2c@01c2ac00 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 8>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ gmac: ethernet@01c50000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_mii_a>;
+ phy = <&phy1>;
+ phy-mode = "mii";
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_pcduino3>;
+
+ tx {
+ label = "pcduino3:green:tx";
+ gpios = <&pio 7 15 GPIO_ACTIVE_LOW>;
+ };
+
+ rx {
+ label = "pcduino3:green:rx";
+ gpios = <&pio 7 16 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_pins_pcduino3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ button@0 {
+ label = "Key Back";
+ linux,code = <KEY_BACK>;
+ gpios = <&pio 7 17 GPIO_ACTIVE_LOW>;
+ };
+ button@1 {
+ label = "Key Home";
+ linux,code = <KEY_HOME>;
+ gpios = <&pio 7 18 GPIO_ACTIVE_LOW>;
+ };
+ button@2 {
+ label = "Key Menu";
+ linux,code = <KEY_MENU>;
+ gpios = <&pio 7 19 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ reg_usb1_vbus: usb1-vbus {
+ status = "okay";
+ };
+
+ reg_usb2_vbus: usb2-vbus {
+ status = "okay";
+ };
+
+ reg_ahci_5v: ahci-5v {
+ gpio = <&pio 7 2 0>;
+ status = "okay";
+ };
+};
--- /dev/null
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ interrupt-parent = <&gic>;
+
+ aliases {
+ ethernet0 = &gmac;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &uart6;
+ serial7 = &uart7;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ };
+ };
+
+ memory {
+ reg = <0x40000000 0x80000000>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 13 0xf08>,
+ <1 14 0xf08>,
+ <1 11 0xf08>,
+ <1 10 0xf08>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
+ interrupts = <0 120 4>,
+ <0 121 4>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: clk@01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-osc-clk";
+ reg = <0x01c20050 0x4>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: clk@0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ pll1: clk@01c20000 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-pll1-clk";
+ reg = <0x01c20000 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll1";
+ };
+
+ pll4: clk@01c20018 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun7i-a20-pll4-clk";
+ reg = <0x01c20018 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll4";
+ };
+
+ pll5: clk@01c20020 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-pll5-clk";
+ reg = <0x01c20020 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll5_ddr", "pll5_other";
+ };
+
+ pll6: clk@01c20028 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-pll6-clk";
+ reg = <0x01c20028 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll6_sata", "pll6_other", "pll6";
+ };
+
+ pll8: clk@01c20040 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun7i-a20-pll4-clk";
+ reg = <0x01c20040 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll8";
+ };
+
+ cpu: cpu@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-cpu-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
+ clock-output-names = "cpu";
+ };
+
+ axi: axi@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-axi-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&cpu>;
+ clock-output-names = "axi";
+ };
+
+ ahb: ahb@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-ahb-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&axi>;
+ clock-output-names = "ahb";
+ };
+
+ ahb_gates: clk@01c20060 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun7i-a20-ahb-gates-clk";
+ reg = <0x01c20060 0x8>;
+ clocks = <&ahb>;
+ clock-output-names = "ahb_usb0", "ahb_ehci0",
+ "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
+ "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
+ "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
+ "ahb_nand", "ahb_sdram", "ahb_ace",
+ "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
+ "ahb_spi2", "ahb_spi3", "ahb_sata",
+ "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
+ "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
+ "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
+ "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
+ "ahb_de_fe1", "ahb_gmac", "ahb_mp",
+ "ahb_mali";
+ };
+
+ apb0: apb0@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb0-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&ahb>;
+ clock-output-names = "apb0";
+ };
+
+ apb0_gates: clk@01c20068 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun7i-a20-apb0-gates-clk";
+ reg = <0x01c20068 0x4>;
+ clocks = <&apb0>;
+ clock-output-names = "apb0_codec", "apb0_spdif",
+ "apb0_ac97", "apb0_iis0", "apb0_iis1",
+ "apb0_pio", "apb0_ir0", "apb0_ir1",
+ "apb0_iis2", "apb0_keypad";
+ };
+
+ apb1_mux: apb1_mux@01c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb1-mux-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
+ clock-output-names = "apb1_mux";
+ };
+
+ apb1: apb1@01c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb1-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&apb1_mux>;
+ clock-output-names = "apb1";
+ };
+
+ apb1_gates: clk@01c2006c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun7i-a20-apb1-gates-clk";
+ reg = <0x01c2006c 0x4>;
+ clocks = <&apb1>;
+ clock-output-names = "apb1_i2c0", "apb1_i2c1",
+ "apb1_i2c2", "apb1_i2c3", "apb1_can",
+ "apb1_scr", "apb1_ps20", "apb1_ps21",
+ "apb1_i2c4", "apb1_uart0", "apb1_uart1",
+ "apb1_uart2", "apb1_uart3", "apb1_uart4",
+ "apb1_uart5", "apb1_uart6", "apb1_uart7";
+ };
+
+ nand_clk: clk@01c20080 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20080 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "nand";
+ };
+
+ ms_clk: clk@01c20084 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20084 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ms";
+ };
+
+ mmc0_clk: clk@01c20088 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20088 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "mmc0";
+ };
+
+ mmc1_clk: clk@01c2008c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c2008c 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "mmc1";
+ };
+
+ mmc2_clk: clk@01c20090 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20090 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "mmc2";
+ };
+
+ mmc3_clk: clk@01c20094 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20094 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "mmc3";
+ };
+
+ ts_clk: clk@01c20098 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20098 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ts";
+ };
+
+ ss_clk: clk@01c2009c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c2009c 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ss";
+ };
+
+ spi0_clk: clk@01c200a0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a0 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "spi0";
+ };
+
+ spi1_clk: clk@01c200a4 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a4 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "spi1";
+ };
+
+ spi2_clk: clk@01c200a8 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a8 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "spi2";
+ };
+
+ pata_clk: clk@01c200ac {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200ac 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "pata";
+ };
+
+ ir0_clk: clk@01c200b0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200b0 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ir0";
+ };
+
+ ir1_clk: clk@01c200b4 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200b4 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ir1";
+ };
+
+ usb_clk: clk@01c200cc {
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ compatible = "allwinner,sun4i-a10-usb-clk";
+ reg = <0x01c200cc 0x4>;
+ clocks = <&pll6 1>;
+ clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
+ };
+
+ spi3_clk: clk@01c200d4 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200d4 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "spi3";
+ };
+
+ mbus_clk: clk@01c2015c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c2015c 0x4>;
+ clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
+ clock-output-names = "mbus";
+ };
+
+ /*
+ * The following two are dummy clocks, placeholders used in the gmac_tx
+ * clock. The gmac driver will choose one parent depending on the PHY
+ * interface mode, using clk_set_rate auto-reparenting.
+ * The actual TX clock rate is not controlled by the gmac_tx clock.
+ */
+ mii_phy_tx_clk: clk@2 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "mii_phy_tx";
+ };
+
+ gmac_int_tx_clk: clk@3 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_int_tx";
+ };
+
+ gmac_tx_clk: clk@01c20164 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun7i-a20-gmac-clk";
+ reg = <0x01c20164 0x4>;
+ clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
+ clock-output-names = "gmac_tx";
+ };
+
+ /*
+ * Dummy clock used by output clocks
+ */
+ osc24M_32k: clk@1 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <750>;
+ clock-mult = <1>;
+ clocks = <&osc24M>;
+ clock-output-names = "osc24M_32k";
+ };
+
+ clk_out_a: clk@01c201f0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun7i-a20-out-clk";
+ reg = <0x01c201f0 0x4>;
+ clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
+ clock-output-names = "clk_out_a";
+ };
+
+ clk_out_b: clk@01c201f4 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun7i-a20-out-clk";
+ reg = <0x01c201f4 0x4>;
+ clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
+ clock-output-names = "clk_out_b";
+ };
+ };
+
+ soc@01c00000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ nmi_intc: interrupt-controller@01c00030 {
+ compatible = "allwinner,sun7i-a20-sc-nmi";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x01c00030 0x0c>;
+ interrupts = <0 0 4>;
+ };
+
+ spi0: spi@01c05000 {
+ compatible = "allwinner,sun4i-a10-spi";
+ reg = <0x01c05000 0x1000>;
+ interrupts = <0 10 4>;
+ clocks = <&ahb_gates 20>, <&spi0_clk>;
+ clock-names = "ahb", "mod";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@01c06000 {
+ compatible = "allwinner,sun4i-a10-spi";
+ reg = <0x01c06000 0x1000>;
+ interrupts = <0 11 4>;
+ clocks = <&ahb_gates 21>, <&spi1_clk>;
+ clock-names = "ahb", "mod";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ emac: ethernet@01c0b000 {
+ compatible = "allwinner,sun4i-a10-emac";
+ reg = <0x01c0b000 0x1000>;
+ interrupts = <0 55 4>;
+ clocks = <&ahb_gates 17>;
+ status = "disabled";
+ };
+
+ mdio@01c0b080 {
+ compatible = "allwinner,sun4i-a10-mdio";
+ reg = <0x01c0b080 0x14>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc0: mmc@01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ahb_gates 8>, <&mmc0_clk>;
+ clock-names = "ahb", "mmc";
+ interrupts = <0 32 4>;
+ status = "disabled";
+ };
+
+ mmc1: mmc@01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ahb_gates 9>, <&mmc1_clk>;
+ clock-names = "ahb", "mmc";
+ interrupts = <0 33 4>;
+ status = "disabled";
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ahb_gates 10>, <&mmc2_clk>;
+ clock-names = "ahb", "mmc";
+ interrupts = <0 34 4>;
+ status = "disabled";
+ };
+
+ mmc3: mmc@01c12000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c12000 0x1000>;
+ clocks = <&ahb_gates 11>, <&mmc3_clk>;
+ clock-names = "ahb", "mmc";
+ interrupts = <0 35 4>;
+ status = "disabled";
+ };
+
+ usbphy: phy@01c13400 {
+ #phy-cells = <1>;
+ compatible = "allwinner,sun7i-a20-usb-phy";
+ reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
+ reg-names = "phy_ctrl", "pmu1", "pmu2";
+ clocks = <&usb_clk 8>;
+ clock-names = "usb_phy";
+ resets = <&usb_clk 1>, <&usb_clk 2>;
+ reset-names = "usb1_reset", "usb2_reset";
+ status = "disabled";
+ };
+
+ ehci0: usb@01c14000 {
+ compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
+ reg = <0x01c14000 0x100>;
+ interrupts = <0 39 4>;
+ clocks = <&ahb_gates 1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci0: usb@01c14400 {
+ compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
+ reg = <0x01c14400 0x100>;
+ interrupts = <0 64 4>;
+ clocks = <&usb_clk 6>, <&ahb_gates 2>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ spi2: spi@01c17000 {
+ compatible = "allwinner,sun4i-a10-spi";
+ reg = <0x01c17000 0x1000>;
+ interrupts = <0 12 4>;
+ clocks = <&ahb_gates 22>, <&spi2_clk>;
+ clock-names = "ahb", "mod";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ ahci: sata@01c18000 {
+ compatible = "allwinner,sun4i-a10-ahci";
+ reg = <0x01c18000 0x1000>;
+ interrupts = <0 56 4>;
+ clocks = <&pll6 0>, <&ahb_gates 25>;
+ status = "disabled";
+ };
+
+ ehci1: usb@01c1c000 {
+ compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
+ reg = <0x01c1c000 0x100>;
+ interrupts = <0 40 4>;
+ clocks = <&ahb_gates 3>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb@01c1c400 {
+ compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
+ reg = <0x01c1c400 0x100>;
+ interrupts = <0 65 4>;
+ clocks = <&usb_clk 7>, <&ahb_gates 4>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ spi3: spi@01c1f000 {
+ compatible = "allwinner,sun4i-a10-spi";
+ reg = <0x01c1f000 0x1000>;
+ interrupts = <0 50 4>;
+ clocks = <&ahb_gates 23>, <&spi3_clk>;
+ clock-names = "ahb", "mod";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pio: pinctrl@01c20800 {
+ compatible = "allwinner,sun7i-a20-pinctrl";
+ reg = <0x01c20800 0x400>;
+ interrupts = <0 28 4>;
+ clocks = <&apb0_gates 5>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #size-cells = <0>;
+ #gpio-cells = <3>;
+
+ pwm0_pins_a: pwm0@0 {
+ allwinner,pins = "PB2";
+ allwinner,function = "pwm";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ pwm1_pins_a: pwm1@0 {
+ allwinner,pins = "PI3";
+ allwinner,function = "pwm";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ uart0_pins_a: uart0@0 {
+ allwinner,pins = "PB22", "PB23";
+ allwinner,function = "uart0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ uart2_pins_a: uart2@0 {
+ allwinner,pins = "PI16", "PI17", "PI18", "PI19";
+ allwinner,function = "uart2";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ uart6_pins_a: uart6@0 {
+ allwinner,pins = "PI12", "PI13";
+ allwinner,function = "uart6";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ uart7_pins_a: uart7@0 {
+ allwinner,pins = "PI20", "PI21";
+ allwinner,function = "uart7";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ i2c0_pins_a: i2c0@0 {
+ allwinner,pins = "PB0", "PB1";
+ allwinner,function = "i2c0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ i2c1_pins_a: i2c1@0 {
+ allwinner,pins = "PB18", "PB19";
+ allwinner,function = "i2c1";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ i2c2_pins_a: i2c2@0 {
+ allwinner,pins = "PB20", "PB21";
+ allwinner,function = "i2c2";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ emac_pins_a: emac0@0 {
+ allwinner,pins = "PA0", "PA1", "PA2",
+ "PA3", "PA4", "PA5", "PA6",
+ "PA7", "PA8", "PA9", "PA10",
+ "PA11", "PA12", "PA13", "PA14",
+ "PA15", "PA16";
+ allwinner,function = "emac";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ clk_out_a_pins_a: clk_out_a@0 {
+ allwinner,pins = "PI12";
+ allwinner,function = "clk_out_a";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ clk_out_b_pins_a: clk_out_b@0 {
+ allwinner,pins = "PI13";
+ allwinner,function = "clk_out_b";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ gmac_pins_mii_a: gmac_mii@0 {
+ allwinner,pins = "PA0", "PA1", "PA2",
+ "PA3", "PA4", "PA5", "PA6",
+ "PA7", "PA8", "PA9", "PA10",
+ "PA11", "PA12", "PA13", "PA14",
+ "PA15", "PA16";
+ allwinner,function = "gmac";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ gmac_pins_rgmii_a: gmac_rgmii@0 {
+ allwinner,pins = "PA0", "PA1", "PA2",
+ "PA3", "PA4", "PA5", "PA6",
+ "PA7", "PA8", "PA10",
+ "PA11", "PA12", "PA13",
+ "PA15", "PA16";
+ allwinner,function = "gmac";
+ /*
+ * data lines in RGMII mode use DDR mode
+ * and need a higher signal drive strength
+ */
+ allwinner,drive = <3>;
+ allwinner,pull = <0>;
+ };
+
+ spi1_pins_a: spi1@0 {
+ allwinner,pins = "PI16", "PI17", "PI18", "PI19";
+ allwinner,function = "spi1";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ spi2_pins_a: spi2@0 {
+ allwinner,pins = "PC19", "PC20", "PC21", "PC22";
+ allwinner,function = "spi2";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ mmc0_pins_a: mmc0@0 {
+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <2>;
+ allwinner,pull = <0>;
+ };
+
+ mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
+ allwinner,pins = "PH1";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <0>;
+ allwinner,pull = <1>;
+ };
+
+ mmc3_pins_a: mmc3@0 {
+ allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
+ allwinner,function = "mmc3";
+ allwinner,drive = <2>;
+ allwinner,pull = <0>;
+ };
+
+ ir0_pins_a: ir0@0 {
+ allwinner,pins = "PB3","PB4";
+ allwinner,function = "ir0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ ir1_pins_a: ir1@0 {
+ allwinner,pins = "PB22","PB23";
+ allwinner,function = "ir1";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+ };
+
+ timer@01c20c00 {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x01c20c00 0x90>;
+ interrupts = <0 22 4>,
+ <0 23 4>,
+ <0 24 4>,
+ <0 25 4>,
+ <0 67 4>,
+ <0 68 4>;
+ clocks = <&osc24M>;
+ };
+
+ wdt: watchdog@01c20c90 {
+ compatible = "allwinner,sun4i-a10-wdt";
+ reg = <0x01c20c90 0x10>;
+ };
+
+ rtc: rtc@01c20d00 {
+ compatible = "allwinner,sun7i-a20-rtc";
+ reg = <0x01c20d00 0x20>;
+ interrupts = <0 24 4>;
+ };
+
+ pwm: pwm@01c20e00 {
+ compatible = "allwinner,sun7i-a20-pwm";
+ reg = <0x01c20e00 0xc>;
+ clocks = <&osc24M>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ ir0: ir@01c21800 {
+ compatible = "allwinner,sun4i-a10-ir";
+ clocks = <&apb0_gates 6>, <&ir0_clk>;
+ clock-names = "apb", "ir";
+ interrupts = <0 5 4>;
+ reg = <0x01c21800 0x40>;
+ status = "disabled";
+ };
+
+ ir1: ir@01c21c00 {
+ compatible = "allwinner,sun4i-a10-ir";
+ clocks = <&apb0_gates 7>, <&ir1_clk>;
+ clock-names = "apb", "ir";
+ interrupts = <0 6 4>;
+ reg = <0x01c21c00 0x40>;
+ status = "disabled";
+ };
+
+ sid: eeprom@01c23800 {
+ compatible = "allwinner,sun7i-a20-sid";
+ reg = <0x01c23800 0x200>;
+ };
+
+ rtp: rtp@01c25000 {
+ compatible = "allwinner,sun4i-a10-ts";
+ reg = <0x01c25000 0x100>;
+ interrupts = <0 29 4>;
+ };
+
+ uart0: serial@01c28000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28000 0x400>;
+ interrupts = <0 1 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 16>;
+ status = "disabled";
+ };
+
+ uart1: serial@01c28400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28400 0x400>;
+ interrupts = <0 2 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 17>;
+ status = "disabled";
+ };
+
+ uart2: serial@01c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <0 3 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 18>;
+ status = "disabled";
+ };
+
+ uart3: serial@01c28c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28c00 0x400>;
+ interrupts = <0 4 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 19>;
+ status = "disabled";
+ };
+
+ uart4: serial@01c29000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29000 0x400>;
+ interrupts = <0 17 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 20>;
+ status = "disabled";
+ };
+
+ uart5: serial@01c29400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29400 0x400>;
+ interrupts = <0 18 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 21>;
+ status = "disabled";
+ };
+
+ uart6: serial@01c29800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29800 0x400>;
+ interrupts = <0 19 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 22>;
+ status = "disabled";
+ };
+
+ uart7: serial@01c29c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29c00 0x400>;
+ interrupts = <0 20 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 23>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@01c2ac00 {
+ compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
+ reg = <0x01c2ac00 0x400>;
+ interrupts = <0 7 4>;
+ clocks = <&apb1_gates 0>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@01c2b000 {
+ compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
+ reg = <0x01c2b000 0x400>;
+ interrupts = <0 8 4>;
+ clocks = <&apb1_gates 1>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@01c2b400 {
+ compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
+ reg = <0x01c2b400 0x400>;
+ interrupts = <0 9 4>;
+ clocks = <&apb1_gates 2>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c3: i2c@01c2b800 {
+ compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
+ reg = <0x01c2b800 0x400>;
+ interrupts = <0 88 4>;
+ clocks = <&apb1_gates 3>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c4: i2c@01c2c000 {
+ compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
+ reg = <0x01c2c000 0x400>;
+ interrupts = <0 89 4>;
+ clocks = <&apb1_gates 15>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ gmac: ethernet@01c50000 {
+ compatible = "allwinner,sun7i-a20-gmac";
+ reg = <0x01c50000 0x10000>;
+ interrupts = <0 85 4>;
+ interrupt-names = "macirq";
+ clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
+ clock-names = "stmmaceth", "allwinner_gmac_tx";
+ snps,pbl = <2>;
+ snps,fixed-burst;
+ snps,force_sf_dma_mode;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ hstimer@01c60000 {
+ compatible = "allwinner,sun7i-a20-hstimer";
+ reg = <0x01c60000 0x1000>;
+ interrupts = <0 81 4>,
+ <0 82 4>,
+ <0 83 4>,
+ <0 84 4>;
+ clocks = <&ahb_gates 28>;
+ };
+
+ gic: interrupt-controller@01c81000 {
+ compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ reg = <0x01c81000 0x1000>,
+ <0x01c82000 0x1000>,
+ <0x01c84000 0x2000>,
+ <0x01c86000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <1 9 0xf04>;
+ };
+ };
+};
--- /dev/null
+/*
+ * sunxi boards common regulator (ahci target power supply, usb-vbus) code
+ *
+ * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/ {
+ soc@01c00000 {
+ pio: pinctrl@01c20800 {
+ ahci_pwr_pin_a: ahci_pwr_pin@0 {
+ allwinner,pins = "PB8";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ usb1_vbus_pin_a: usb1_vbus_pin@0 {
+ allwinner,pins = "PH6";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ usb2_vbus_pin_a: usb2_vbus_pin@0 {
+ allwinner,pins = "PH3";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+ };
+ };
+
+ reg_ahci_5v: ahci-5v {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ahci_pwr_pin_a>;
+ regulator-name = "ahci-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&pio 1 8 0>;
+ status = "disabled";
+ };
+
+ reg_usb1_vbus: usb1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_vbus_pin_a>;
+ regulator-name = "usb1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&pio 7 6 0>;
+ status = "disabled";
+ };
+
+ reg_usb2_vbus: usb2-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_vbus_pin_a>;
+ regulator-name = "usb2-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&pio 7 3 0>;
+ status = "disabled";
+ };
+
+ reg_vcc3v0: vcc3v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <bootm.h>
#include <common.h>
+#include <netdev.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
p += stride;
}
}
+
+void imx_iomux_set_gpr_register(int group, int start_bit,
+ int num_bits, int value)
+{
+ int i = 0;
+ u32 reg;
+ reg = readl(base + group * 4);
+ while (num_bits) {
+ reg &= ~(1<<(start_bit + i));
+ i++;
+ num_bits--;
+ }
+ reg |= (value << start_bit);
+ writel(reg, base + group * 4);
+}
*/
#include <common.h>
+#include <asm/arch/sys_proto.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/imx-common/regs-common.h>
case BOOT_DEVICE_MMC1:
case BOOT_DEVICE_MMC2:
#ifdef CONFIG_SPL_FAT_SUPPORT
- return MMCSD_MODE_FAT;
+ return MMCSD_MODE_FS;
#else
return MMCSD_MODE_RAW;
#endif
#include <div64.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
/* General purpose timers registers */
struct mxc_gpt {
/* General purpose timers bitfields */
#define GPTCR_SWR (1 << 15) /* Software reset */
+#define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input */
#define GPTCR_FRR (1 << 9) /* Freerun / restart */
-#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
+#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source 32khz */
+#define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */
+#define GPTCR_CLKSOURCE_PRE (1 << 6) /* Clock source PRECLK */
+#define GPTCR_CLKSOURCE_MASK (0x7 << 6)
#define GPTCR_TEN 1 /* Timer enable */
+#define GPTPR_PRESCALER24M_SHIFT 12
+#define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
+
DECLARE_GLOBAL_DATA_PTR;
+static inline int gpt_has_clk_source_osc(void)
+{
+#if defined(CONFIG_MX6)
+ if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
+ (is_soc_rev(CHIP_REV_1_0) > 0)) || is_cpu_type(MXC_CPU_MX6DL) ||
+ is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX))
+ return 1;
+
+ return 0;
+#else
+ return 0;
+#endif
+}
+
+static inline ulong gpt_get_clk(void)
+{
+#ifdef CONFIG_MXC_GPT_HCLK
+ if (gpt_has_clk_source_osc())
+ return MXC_HCLK >> 3;
+ else
+ return mxc_get_clock(MXC_IPG_PERCLK);
+#else
+ return MXC_CLK32;
+#endif
+}
static inline unsigned long long tick_to_time(unsigned long long tick)
{
+ ulong gpt_clk = gpt_get_clk();
+
tick *= CONFIG_SYS_HZ;
- do_div(tick, MXC_CLK32);
+ do_div(tick, gpt_clk);
return tick;
}
static inline unsigned long long us_to_tick(unsigned long long usec)
{
- usec = usec * MXC_CLK32 + 999999;
+ ulong gpt_clk = gpt_get_clk();
+
+ usec = usec * gpt_clk + 999999;
do_div(usec, 1000000);
return usec;
for (i = 0; i < 100; i++)
__raw_writel(0, &cur_gpt->control);
- __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
-
- /* Freerun Mode, PERCLK1 input */
i = __raw_readl(&cur_gpt->control);
- __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
+ i &= ~GPTCR_CLKSOURCE_MASK;
+
+#ifdef CONFIG_MXC_GPT_HCLK
+ if (gpt_has_clk_source_osc()) {
+ i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
+
+ /* For DL/S, SX, set 24Mhz OSC Enable bit and prescaler */
+ if (is_cpu_type(MXC_CPU_MX6DL) ||
+ is_cpu_type(MXC_CPU_MX6SOLO) ||
+ is_cpu_type(MXC_CPU_MX6SX)) {
+ i |= GPTCR_24MEN;
+
+ /* Produce 3Mhz clock */
+ __raw_writel((7 << GPTPR_PRESCALER24M_SHIFT),
+ &cur_gpt->prescaler);
+ }
+ } else {
+ i |= GPTCR_CLKSOURCE_PRE | GPTCR_TEN;
+ }
+#else
+ __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
+ i |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
+#endif
+ __raw_writel(i, &cur_gpt->control);
gd->arch.tbl = __raw_readl(&cur_gpt->counter);
gd->arch.tbu = 0;
{
/*
* get_ticks() returns a long long (64 bit), it wraps in
- * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+ * 2^64 / GPT_CLK = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
* 5 * 10^6 days - long enough.
*/
*/
ulong get_tbclk(void)
{
- return MXC_CLK32;
+ return gpt_get_clk();
}
#include <asm/errno.h>
#include <asm/imx-common/video.h>
-extern struct display_info_t const displays[];
-extern size_t display_count;
-
int board_video_skip(void)
{
int i;
/* Pad control register offset */
#define PAD_CTRL_BASE 0x800
-#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
+#define OFFSET(x) (unsigned int) (&((struct pad_signals *)\
(PAD_CTRL_BASE))->x)
/*
#include <asm/ti-common/sys_proto.h>
#include <asm/arch/cpu.h>
-#define BOARD_REV_ID 0x0
-
u32 get_cpu_rev(void);
u32 get_sysboot_value(void);
+++ /dev/null
-/*
- * Copyright (C) 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- *
- * Shutdown Controller
- * Based on AT91SAM9XE datasheet
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91_SHDWN_H
-#define AT91_SHDWN_H
-
-#ifndef __ASSEMBLY__
-
-struct at91_shdwn {
- u32 cr; /* Control Rer. WO */
- u32 mr; /* Mode Register RW 0x00000003 */
- u32 sr; /* Status Register RO 0x00000000 */
-};
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_SHDW_CR_KEY 0xa5000000
-#define AT91_SHDW_CR_SHDW 0x00000001
-
-#define AT91_SHDW_MR_RTTWKEN 0x00010000
-#define AT91_SHDW_MR_CPTWK0 0x000000f0
-#define AT91_SHDW_MR_WKMODE0H2L 0x00000002
-#define AT91_SHDW_MR_WKMODE0L2H 0x00000001
-
-#define AT91_SHDW_SR_RTTWK 0x00010000
-#define AT91_SHDW_SR_WAKEUP0 0x00000001
-
-#endif
* };
*/
+#define BCM2835_MBOX_TAG_GET_MAC_ADDRESS 0x00010003
+
+struct bcm2835_mbox_tag_get_mac_address {
+ struct bcm2835_mbox_tag_hdr tag_hdr;
+ union {
+ struct {
+ } req;
+ struct {
+ u8 mac[6];
+ u8 pad[2];
+ } resp;
+ } body;
+};
+
#define BCM2835_MBOX_TAG_GET_ARM_MEMORY 0x00010005
struct bcm2835_mbox_tag_get_arm_mem {
#define EXYNOS4_MIU_BASE 0x10600000
#define EXYNOS4_ACE_SFR_BASE 0x10830000
#define EXYNOS4_GPIO_PART2_BASE 0x11000000
+#define EXYNOS4_GPIO_PART2_0 0x11000000 /* GPJ0 */
+#define EXYNOS4_GPIO_PART2_1 0x11000c00 /* GPX0 */
#define EXYNOS4_GPIO_PART1_BASE 0x11400000
#define EXYNOS4_FIMD_BASE 0x11C00000
#define EXYNOS4_MIPI_DSIM_BASE 0x11C80000
#define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000
#define EXYNOS4X12_ACE_SFR_BASE 0x10830000
#define EXYNOS4X12_GPIO_PART2_BASE 0x11000000
+#define EXYNOS4X12_GPIO_PART2_0 0x11000000
+#define EXYNOS4X12_GPIO_PART2_1 0x11000040 /* GPK0 */
+#define EXYNOS4X12_GPIO_PART2_2 0x11000260 /* GPM0 */
+#define EXYNOS4X12_GPIO_PART2_3 0x11000c00 /* GPX0 */
#define EXYNOS4X12_GPIO_PART1_BASE 0x11400000
+#define EXYNOS4X12_GPIO_PART1_0 0x11400000 /* GPA0 */
+#define EXYNOS4X12_GPIO_PART1_1 0x11400180 /* GPF0 */
+#define EXYNOS4X12_GPIO_PART1_2 0x11400240 /* GPJ0 */
#define EXYNOS4X12_FIMD_BASE 0x11C00000
#define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000
#define EXYNOS4X12_USBOTG_BASE 0x12480000
EXYNOS4_GPIO_Y65,
EXYNOS4_GPIO_Y66,
EXYNOS4_GPIO_Y67,
- EXYNOS4_GPIO_X00, /* 256 0x100 */
+
+ /* GPIO_PART2_1 STARTS */
+ EXYNOS4_GPIO_MAX_PORT_PART_2_0, /* 256 0x100 */
+ EXYNOS4_GPIO_X00 = EXYNOS4_GPIO_MAX_PORT_PART_2_0,
EXYNOS4_GPIO_X01,
EXYNOS4_GPIO_X02,
EXYNOS4_GPIO_X03,
EXYNOS4_GPIO_X37,
/* GPIO_PART3_STARTS */
- EXYNOS4_GPIO_MAX_PORT_PART_2, /* 288 0x120 */
- EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2,
+ EXYNOS4_GPIO_MAX_PORT_PART_2_1, /* 288 0x120 */
+ EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2_1,
EXYNOS4_GPIO_Z1,
EXYNOS4_GPIO_Z2,
EXYNOS4_GPIO_Z3,
};
enum exynos4X12_gpio_pin {
- /* GPIO_PART1_STARTS */
+ /* EXYNOS4X12_GPIO_PART1_0 starts here */
EXYNOS4X12_GPIO_A00, /* 0 */
EXYNOS4X12_GPIO_A01,
EXYNOS4X12_GPIO_A02,
EXYNOS4X12_GPIO_D15,
EXYNOS4X12_GPIO_D16,
EXYNOS4X12_GPIO_D17,
- EXYNOS4X12_GPIO_F00, /* 56 0x38 */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_1_0, /* 56 0x38 */
+ /* EXYNOS4X12_GPIO_PART1_1 starts here */
+ EXYNOS4X12_GPIO_F00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_0,
EXYNOS4X12_GPIO_F01,
EXYNOS4X12_GPIO_F02,
EXYNOS4X12_GPIO_F03,
EXYNOS4X12_GPIO_F35,
EXYNOS4X12_GPIO_F36,
EXYNOS4X12_GPIO_F37,
- EXYNOS4X12_GPIO_J00, /* 88 0x58 */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_1_1, /* 88 0x58 */
+ /* EXYNOS4X12_GPIO_PART1_2 starts here */
+ EXYNOS4X12_GPIO_J00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_1,
EXYNOS4X12_GPIO_J01,
EXYNOS4X12_GPIO_J02,
EXYNOS4X12_GPIO_J03,
EXYNOS4X12_GPIO_J16,
EXYNOS4X12_GPIO_J17,
- /* GPIO_PART2_STARTS */
- EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 104 0x66 */
- EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1,
+ /**
+ * EXYNOS4X12_GPIO_PART2_0 is not used
+ * EXYNOS4X12_GPIO_PART2_1 starts here
+ */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_1_2, /* 104 0x66 */
+ EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_2,
EXYNOS4X12_GPIO_K01,
EXYNOS4X12_GPIO_K02,
EXYNOS4X12_GPIO_K03,
EXYNOS4X12_GPIO_Y65,
EXYNOS4X12_GPIO_Y66,
EXYNOS4X12_GPIO_Y67,
- EXYNOS4X12_GPIO_M00, /* 216 0xd8 */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_2_1, /* 216 0xd8 */
+ /* EXYNOS4X12_GPIO_PART2_2 starts here */
+ EXYNOS4X12_GPIO_M00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_1,
EXYNOS4X12_GPIO_M01,
EXYNOS4X12_GPIO_M02,
EXYNOS4X12_GPIO_M03,
EXYNOS4X12_GPIO_M45,
EXYNOS4X12_GPIO_M46,
EXYNOS4X12_GPIO_M47,
- EXYNOS4X12_GPIO_X00, /* 256 0x100 */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_2_2, /* 256 0x100 */
+ /* EXYNOS4X12_GPIO_PART2_3 starts here */
+ EXYNOS4X12_GPIO_X00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_2,
EXYNOS4X12_GPIO_X01,
EXYNOS4X12_GPIO_X02,
EXYNOS4X12_GPIO_X03,
EXYNOS4X12_GPIO_X36,
EXYNOS4X12_GPIO_X37,
- /* GPIO_PART3_STARTS */
- EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 288 0x120 */
- EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2,
+ /* EXYNOS4X12_GPIO_PART3 starts here */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_2_3, /* 288 0x120 */
+ EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_3,
EXYNOS4X12_GPIO_Z1,
EXYNOS4X12_GPIO_Z2,
EXYNOS4X12_GPIO_Z3,
EXYNOS4X12_GPIO_Z6,
EXYNOS4X12_GPIO_Z7,
- /* GPIO_PART4_STARTS */
+ /* EXYNOS4X12_GPIO_PART4 starts here */
EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 296 0x128 */
EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3,
EXYNOS4X12_GPIO_V01,
unsigned int max_gpio; /* Maximum GPIO in this part */
};
-#define EXYNOS4_GPIO_NUM_PARTS 3
+#define EXYNOS4_GPIO_NUM_PARTS 4
static struct gpio_info exynos4_gpio_data[EXYNOS4_GPIO_NUM_PARTS] = {
{ EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 },
- { EXYNOS4_GPIO_PART2_BASE, EXYNOS4_GPIO_MAX_PORT_PART_2 },
+ { EXYNOS4_GPIO_PART2_0, EXYNOS4_GPIO_MAX_PORT_PART_2_0 },
+ { EXYNOS4_GPIO_PART2_1, EXYNOS4_GPIO_MAX_PORT_PART_2_1 },
{ EXYNOS4_GPIO_PART3_BASE, EXYNOS4_GPIO_MAX_PORT },
};
-#define EXYNOS4X12_GPIO_NUM_PARTS 4
+#define EXYNOS4X12_GPIO_NUM_PARTS 8
static struct gpio_info exynos4x12_gpio_data[EXYNOS4X12_GPIO_NUM_PARTS] = {
- { EXYNOS4X12_GPIO_PART1_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_1 },
- { EXYNOS4X12_GPIO_PART2_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_2 },
+ { EXYNOS4X12_GPIO_PART1_0, EXYNOS4X12_GPIO_MAX_PORT_PART_1_0 },
+ { EXYNOS4X12_GPIO_PART1_1, EXYNOS4X12_GPIO_MAX_PORT_PART_1_1 },
+ { EXYNOS4X12_GPIO_PART1_2, EXYNOS4X12_GPIO_MAX_PORT_PART_1_2 },
+ { EXYNOS4X12_GPIO_PART2_1, EXYNOS4X12_GPIO_MAX_PORT_PART_2_1 },
+ { EXYNOS4X12_GPIO_PART2_2, EXYNOS4X12_GPIO_MAX_PORT_PART_2_2 },
+ { EXYNOS4X12_GPIO_PART2_3, EXYNOS4X12_GPIO_MAX_PORT_PART_2_3 },
{ EXYNOS4X12_GPIO_PART3_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_3 },
{ EXYNOS4X12_GPIO_PART4_BASE, EXYNOS4X12_GPIO_MAX_PORT },
};
extern unsigned int external_clk[ext_clk_count];
-enum clk_e {
- core_pll_clk,
- pass_pll_clk,
- ddr3_pll_clk,
- sys_clk0_clk,
- sys_clk0_1_clk,
- sys_clk0_2_clk,
- sys_clk0_3_clk,
- sys_clk0_4_clk,
- sys_clk0_6_clk,
- sys_clk0_8_clk,
- sys_clk0_12_clk,
- sys_clk0_24_clk,
- sys_clk1_clk,
- sys_clk1_3_clk,
- sys_clk1_4_clk,
- sys_clk1_6_clk,
- sys_clk1_12_clk,
- sys_clk2_clk,
- sys_clk3_clk
-};
+#define CLK_LIST(CLK)\
+ CLK(0, core_pll_clk)\
+ CLK(1, pass_pll_clk)\
+ CLK(2, ddr3_pll_clk)\
+ CLK(3, sys_clk0_clk)\
+ CLK(4, sys_clk0_1_clk)\
+ CLK(5, sys_clk0_2_clk)\
+ CLK(6, sys_clk0_3_clk)\
+ CLK(7, sys_clk0_4_clk)\
+ CLK(8, sys_clk0_6_clk)\
+ CLK(9, sys_clk0_8_clk)\
+ CLK(10, sys_clk0_12_clk)\
+ CLK(11, sys_clk0_24_clk)\
+ CLK(12, sys_clk1_clk)\
+ CLK(13, sys_clk1_3_clk)\
+ CLK(14, sys_clk1_4_clk)\
+ CLK(15, sys_clk1_6_clk)\
+ CLK(16, sys_clk1_12_clk)\
+ CLK(17, sys_clk2_clk)\
+ CLK(18, sys_clk3_clk)
+
+#define PLLSET_CMD_LIST "<pa|ddr3>"
#define KS2_CLK1_6 sys_clk0_6_clk
extern unsigned int external_clk[ext_clk_count];
-enum clk_e {
- core_pll_clk,
- pass_pll_clk,
- tetris_pll_clk,
- ddr3a_pll_clk,
- ddr3b_pll_clk,
- sys_clk0_clk,
- sys_clk0_1_clk,
- sys_clk0_2_clk,
- sys_clk0_3_clk,
- sys_clk0_4_clk,
- sys_clk0_6_clk,
- sys_clk0_8_clk,
- sys_clk0_12_clk,
- sys_clk0_24_clk,
- sys_clk1_clk,
- sys_clk1_3_clk,
- sys_clk1_4_clk,
- sys_clk1_6_clk,
- sys_clk1_12_clk,
- sys_clk2_clk,
- sys_clk3_clk
-};
+#define CLK_LIST(CLK)\
+ CLK(0, core_pll_clk)\
+ CLK(1, pass_pll_clk)\
+ CLK(2, tetris_pll_clk)\
+ CLK(3, ddr3a_pll_clk)\
+ CLK(4, ddr3b_pll_clk)\
+ CLK(5, sys_clk0_clk)\
+ CLK(6, sys_clk0_1_clk)\
+ CLK(7, sys_clk0_2_clk)\
+ CLK(8, sys_clk0_3_clk)\
+ CLK(9, sys_clk0_4_clk)\
+ CLK(10, sys_clk0_6_clk)\
+ CLK(11, sys_clk0_8_clk)\
+ CLK(12, sys_clk0_12_clk)\
+ CLK(13, sys_clk0_24_clk)\
+ CLK(14, sys_clk1_clk)\
+ CLK(15, sys_clk1_3_clk)\
+ CLK(16, sys_clk1_4_clk)\
+ CLK(17, sys_clk1_6_clk)\
+ CLK(18, sys_clk1_12_clk)\
+ CLK(19, sys_clk2_clk)\
+ CLK(20, sys_clk3_clk)
+
+#define PLLSET_CMD_LIST "<pa|arm|ddr3a|ddr3b>"
#define KS2_CLK1_6 sys_clk0_6_clk
--- /dev/null
+/*
+ * K2L: Clock management APIs
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_K2L_H
+#define __ASM_ARCH_CLOCK_K2L_H
+
+enum ext_clk_e {
+ sys_clk,
+ alt_core_clk,
+ pa_clk,
+ tetris_clk,
+ ddr3_clk,
+ pcie_clk,
+ sgmii_clk,
+ usb_clk,
+ rp1_clk,
+ ext_clk_count /* number of external clocks */
+};
+
+extern unsigned int external_clk[ext_clk_count];
+
+#define CLK_LIST(CLK)\
+ CLK(0, core_pll_clk)\
+ CLK(1, pass_pll_clk)\
+ CLK(2, tetris_pll_clk)\
+ CLK(3, ddr3_pll_clk)\
+ CLK(4, sys_clk0_clk)\
+ CLK(5, sys_clk0_1_clk)\
+ CLK(6, sys_clk0_2_clk)\
+ CLK(7, sys_clk0_3_clk)\
+ CLK(8, sys_clk0_4_clk)\
+ CLK(9, sys_clk0_6_clk)\
+ CLK(10, sys_clk0_8_clk)\
+ CLK(11, sys_clk0_12_clk)\
+ CLK(12, sys_clk0_24_clk)\
+ CLK(13, sys_clk1_clk)\
+ CLK(14, sys_clk1_3_clk)\
+ CLK(15, sys_clk1_4_clk)\
+ CLK(16, sys_clk1_6_clk)\
+ CLK(17, sys_clk1_12_clk)\
+ CLK(18, sys_clk2_clk)\
+ CLK(19, sys_clk3_clk)\
+
+#define PLLSET_CMD_LIST "<pa|arm|ddr3>"
+
+#define KS2_CLK1_6 sys_clk0_6_clk
+
+/* PLL identifiers */
+enum pll_type_e {
+ CORE_PLL,
+ PASS_PLL,
+ TETRIS_PLL,
+ DDR3_PLL,
+};
+
+enum {
+ SPD800,
+ SPD1000,
+ SPD1200,
+ SPD1350,
+ SPD1400,
+ SPD_RSV
+};
+
+#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
+#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
+#define CORE_PLL_1000 {CORE_PLL, 114, 7, 2}
+#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2}
+#define CORE_PLL_1198 {CORE_PLL, 39, 2, 2}
+#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2}
+#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2}
+#define PASS_PLL_983 {PASS_PLL, 16, 1, 2}
+#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2}
+#define TETRIS_PLL_491 {TETRIS_PLL, 8, 1, 2}
+#define TETRIS_PLL_737 {TETRIS_PLL, 12, 1, 2}
+#define TETRIS_PLL_799 {TETRIS_PLL, 13, 1, 2}
+#define TETRIS_PLL_983 {TETRIS_PLL, 16, 1, 2}
+#define TETRIS_PLL_1000 {TETRIS_PLL, 114, 7, 2}
+#define TETRIS_PLL_1167 {TETRIS_PLL, 19, 1, 2}
+#define TETRIS_PLL_1198 {TETRIS_PLL, 39, 2, 2}
+#define TETRIS_PLL_1228 {TETRIS_PLL, 20, 1, 2}
+#define TETRIS_PLL_1352 {TETRIS_PLL, 22, 1, 2}
+#define TETRIS_PLL_1401 {TETRIS_PLL, 114, 5, 2}
+#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2}
+#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4}
+#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
+#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6}
+
+#endif
#include <asm/arch/clock-k2e.h>
#endif
+#ifdef CONFIG_SOC_K2L
+#include <asm/arch/clock-k2l.h>
+#endif
+
#define MAIN_PLL CORE_PLL
#include <asm/types.h>
+#define GENERATE_ENUM(NUM, ENUM) ENUM = NUM,
+#define GENERATE_INDX_STR(NUM, STRING) #NUM"\t- "#STRING"\n"
+#define CLOCK_INDEXES_LIST CLK_LIST(GENERATE_INDX_STR)
+
+enum clk_e {
+ CLK_LIST(GENERATE_ENUM)
+};
+
struct keystone_pll_regs {
u32 reg0;
u32 reg1;
unsigned long clk_get_rate(unsigned int clk);
unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
int clk_set_rate(unsigned int clk, unsigned long hz);
+void pass_pll_pa_clk_enable(void);
int get_max_dev_speed(void);
int get_max_arm_speed(void);
};
void ddr3_init(void);
+int ddr3_get_size(void);
void ddr3_reset_ddrphy(void);
+void ddr3_init_ecc(u32 base);
+void ddr3_disable_ecc(u32 base);
+void ddr3_check_ecc_int(u32 base);
+int ddr3_ecc_support_rmw(u32 base);
void ddr3_err_reset_workaround(void);
+void ddr3_enable_ecc(u32 base, int test);
void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
+++ /dev/null
-/*
- * emac definitions for keystone2 devices
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _EMAC_DEFS_H_
-#define _EMAC_DEFS_H_
-
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-#define EMAC_EMACSL_BASE_ADDR (KS2_PASS_BASE + 0x00090900)
-#define EMAC_MDIO_BASE_ADDR (KS2_PASS_BASE + 0x00090300)
-#define EMAC_SGMII_BASE_ADDR (KS2_PASS_BASE + 0x00090100)
-
-#define KEYSTONE2_EMAC_GIG_ENABLE
-
-#define MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
-
-#ifdef CONFIG_SOC_K2HK
-/* MDIO module input frequency */
-#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk))
-/* MDIO clock output frequency */
-#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 1.0 MHz */
-#endif
-
-/* MII Status Register */
-#define MII_STATUS_REG 1
-#define MII_STATUS_LINK_MASK (0x4)
-
-/* Marvell 88E1111 PHY ID */
-#define PHY_MARVELL_88E1111 (0x01410cc0)
-
-#define MDIO_CONTROL_IDLE (0x80000000)
-#define MDIO_CONTROL_ENABLE (0x40000000)
-#define MDIO_CONTROL_FAULT_ENABLE (0x40000)
-#define MDIO_CONTROL_FAULT (0x80000)
-#define MDIO_USERACCESS0_GO (0x80000000)
-#define MDIO_USERACCESS0_WRITE_READ (0x0)
-#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
-#define MDIO_USERACCESS0_ACK (0x20000000)
-
-#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
-#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
-#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
-#define EMAC_MACCONTROL_GIGFORCE (1 << 17)
-#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15)
-
-#define EMAC_MIN_ETHERNET_PKT_SIZE 60
-
-struct mac_sl_cfg {
- u_int32_t max_rx_len; /* Maximum receive packet length. */
- u_int32_t ctl; /* Control bitfield */
-};
-
-/*
- * Definition: Control bitfields used in the ctl field of hwGmacSlCfg_t
- */
-#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES (1 << 24)
-#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES (1 << 23)
-#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES (1 << 22)
-#define GMACSL_RX_ENABLE_EXT_CTL (1 << 18)
-#define GMACSL_RX_ENABLE_GIG_FORCE (1 << 17)
-#define GMACSL_RX_ENABLE_IFCTL_B (1 << 16)
-#define GMACSL_RX_ENABLE_IFCTL_A (1 << 15)
-#define GMACSL_RX_ENABLE_CMD_IDLE (1 << 11)
-#define GMACSL_TX_ENABLE_SHORT_GAP (1 << 10)
-#define GMACSL_ENABLE_GIG_MODE (1 << 7)
-#define GMACSL_TX_ENABLE_PACE (1 << 6)
-#define GMACSL_ENABLE (1 << 5)
-#define GMACSL_TX_ENABLE_FLOW_CTL (1 << 4)
-#define GMACSL_RX_ENABLE_FLOW_CTL (1 << 3)
-#define GMACSL_ENABLE_LOOPBACK (1 << 1)
-#define GMACSL_ENABLE_FULL_DUPLEX (1 << 0)
-
-/*
- * DEFINTITION: function return values
- */
-#define GMACSL_RET_OK 0
-#define GMACSL_RET_INVALID_PORT -1
-#define GMACSL_RET_WARN_RESET_INCOMPLETE -2
-#define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3
-#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4
-
-/* Register offsets */
-#define CPGMACSL_REG_ID 0x00
-#define CPGMACSL_REG_CTL 0x04
-#define CPGMACSL_REG_STATUS 0x08
-#define CPGMACSL_REG_RESET 0x0c
-#define CPGMACSL_REG_MAXLEN 0x10
-#define CPGMACSL_REG_BOFF 0x14
-#define CPGMACSL_REG_RX_PAUSE 0x18
-#define CPGMACSL_REG_TX_PAURSE 0x1c
-#define CPGMACSL_REG_EM_CTL 0x20
-#define CPGMACSL_REG_PRI 0x24
-
-/* Soft reset register values */
-#define CPGMAC_REG_RESET_VAL_RESET_MASK (1 << 0)
-#define CPGMAC_REG_RESET_VAL_RESET (1 << 0)
-
-/* Maxlen register values */
-#define CPGMAC_REG_MAXLEN_LEN 0x3fff
-
-/* Control bitfields */
-#define CPSW_CTL_P2_PASS_PRI_TAGGED (1 << 5)
-#define CPSW_CTL_P1_PASS_PRI_TAGGED (1 << 4)
-#define CPSW_CTL_P0_PASS_PRI_TAGGED (1 << 3)
-#define CPSW_CTL_P0_ENABLE (1 << 2)
-#define CPSW_CTL_VLAN_AWARE (1 << 1)
-#define CPSW_CTL_FIFO_LOOPBACK (1 << 0)
-
-#define DEVICE_CPSW_NUM_PORTS 5 /* 5 switch ports */
-#define DEVICE_CPSW_BASE (0x02090800)
-#define target_get_switch_ctl() CPSW_CTL_P0_ENABLE /* Enable port 0 */
-#define SWITCH_MAX_PKT_SIZE 9000
-
-/* Register offsets */
-#define CPSW_REG_CTL 0x004
-#define CPSW_REG_STAT_PORT_EN 0x00c
-#define CPSW_REG_MAXLEN 0x040
-#define CPSW_REG_ALE_CONTROL 0x608
-#define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x)*4)
-
-/* Register values */
-#define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf
-#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000)
-#define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010)
-#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3
-
-#define SGMII_REG_STATUS_LOCK BIT(4)
-#define SGMII_REG_STATUS_LINK BIT(0)
-#define SGMII_REG_STATUS_AUTONEG BIT(2)
-#define SGMII_REG_CONTROL_AUTONEG BIT(0)
-#define SGMII_REG_CONTROL_MASTER BIT(5)
-#define SGMII_REG_MR_ADV_ENABLE BIT(0)
-#define SGMII_REG_MR_ADV_LINK BIT(15)
-#define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12)
-#define SGMII_REG_MR_ADV_GIG_MODE BIT(11)
-
-#define SGMII_LINK_MAC_MAC_AUTONEG 0
-#define SGMII_LINK_MAC_PHY 1
-#define SGMII_LINK_MAC_MAC_FORCED 2
-#define SGMII_LINK_MAC_FIBER 3
-#define SGMII_LINK_MAC_PHY_FORCED 4
-
-#define TARGET_SGMII_BASE KS2_PASS_BASE + 0x00090100
-#define TARGET_SGMII_BASE_ADDRESSES {KS2_PASS_BASE + 0x00090100, \
- KS2_PASS_BASE + 0x00090200, \
- KS2_PASS_BASE + 0x00090400, \
- KS2_PASS_BASE + 0x00090500}
-
-#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
-
-/*
- * SGMII registers
- */
-#define SGMII_IDVER_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x000)
-#define SGMII_SRESET_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x004)
-#define SGMII_CTL_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x010)
-#define SGMII_STATUS_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x014)
-#define SGMII_MRADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x018)
-#define SGMII_LPADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x020)
-#define SGMII_TXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x030)
-#define SGMII_RXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x034)
-#define SGMII_AUXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x038)
-
-#define DEVICE_EMACSL_BASE(x) (KS2_PASS_BASE + 0x00090900 + (x) * 0x040)
-#define DEVICE_N_GMACSL_PORTS 4
-#define DEVICE_EMACSL_RESET_POLL_COUNT 100
-
-#define DEVICE_PSTREAM_CFG_REG_ADDR (KS2_PASS_BASE + 0x604)
-
-#ifdef CONFIG_SOC_K2HK
-#define DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI 0x06060606
-#endif
-
-#define hw_config_streaming_switch() \
- writel(DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI,\
- DEVICE_PSTREAM_CFG_REG_ADDR);
-
-/* EMAC MDIO Registers Structure */
-struct mdio_regs {
- dv_reg version;
- dv_reg control;
- dv_reg alive;
- dv_reg link;
- dv_reg linkintraw;
- dv_reg linkintmasked;
- u_int8_t rsvd0[8];
- dv_reg userintraw;
- dv_reg userintmasked;
- dv_reg userintmaskset;
- dv_reg userintmaskclear;
- u_int8_t rsvd1[80];
- dv_reg useraccess0;
- dv_reg userphysel0;
- dv_reg useraccess1;
- dv_reg userphysel1;
-};
-
-/* Ethernet MAC Registers Structure */
-struct emac_regs {
- dv_reg idver;
- dv_reg maccontrol;
- dv_reg macstatus;
- dv_reg soft_reset;
- dv_reg rx_maxlen;
- u32 rsvd0;
- dv_reg rx_pause;
- dv_reg tx_pause;
- dv_reg emcontrol;
- dv_reg pri_map;
- u32 rsvd1[6];
-};
-
-#define SGMII_ACCESS(port, reg) \
- *((volatile unsigned int *)(sgmiis[port] + reg))
-
-struct eth_priv_t {
- char int_name[32];
- int rx_flow;
- int phy_addr;
- int slave_port;
- int sgmii_link_type;
-};
-
-extern struct eth_priv_t eth_priv_cfg[];
-
-int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
-void sgmii_serdes_setup_156p25mhz(void);
-void sgmii_serdes_shutdown(void);
-
-#endif /* _EMAC_DEFS_H_ */
#define KS2_LPSC_PCIE_1 27
#define KS2_LPSC_XGE 50
+/* MSMC */
+#define KS2_MSMC_SEGMENT_PCIE1 13
+
/* Chip Interrupt Controller */
#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */
#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */
+/* SGMII SerDes */
+#define KS2_SGMII_SERDES2_BASE 0x02324000
+#define KS2_LANES_PER_SGMII_SERDES 4
+
/* Number of DSP cores */
#define KS2_NUM_DSPS 1
+/* NETCP pktdma */
+#define KS2_NETCP_PDMA_CTRL_BASE 0x24186000
+#define KS2_NETCP_PDMA_TX_BASE 0x24187000
+#define KS2_NETCP_PDMA_TX_CH_NUM 21
+#define KS2_NETCP_PDMA_RX_BASE 0x24188000
+#define KS2_NETCP_PDMA_RX_CH_NUM 91
+#define KS2_NETCP_PDMA_SCHED_BASE 0x24186100
+#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x24189000
+#define KS2_NETCP_PDMA_RX_FLOW_NUM 96
+#define KS2_NETCP_PDMA_TX_SND_QUEUE 896
+
+/* NETCP */
+#define KS2_NETCP_BASE 0x24000000
+
#endif
#ifndef __ASM_ARCH_HARDWARE_K2HK_H
#define __ASM_ARCH_HARDWARE_K2HK_H
-#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
-
#define KS2_ARM_PLL_EN BIT(13)
/* PA SS Registers */
#define KS2_DDR3B_EMIF_DATA_BASE 0x60000000
#define KS2_DDR3B_DDRPHYC 0x02328000
+#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 /* DDR3 ECC system irq number */
+#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D /* DDR3 ECC int mapped to CIC2
+ channel 29 */
+
+/* SGMII SerDes */
+#define KS2_LANES_PER_SGMII_SERDES 4
+
/* Number of DSP cores */
#define KS2_NUM_DSPS 8
+/* NETCP pktdma */
+#define KS2_NETCP_PDMA_CTRL_BASE 0x02004000
+#define KS2_NETCP_PDMA_TX_BASE 0x02004400
+#define KS2_NETCP_PDMA_TX_CH_NUM 9
+#define KS2_NETCP_PDMA_RX_BASE 0x02004800
+#define KS2_NETCP_PDMA_RX_CH_NUM 26
+#define KS2_NETCP_PDMA_SCHED_BASE 0x02004c00
+#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x02005000
+#define KS2_NETCP_PDMA_RX_FLOW_NUM 32
+#define KS2_NETCP_PDMA_TX_SND_QUEUE 648
+
+/* NETCP */
+#define KS2_NETCP_BASE 0x02000000
+
#endif /* __ASM_ARCH_HARDWARE_H */
--- /dev/null
+/*
+ * K2L: SoC definitions
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_K2L_H
+#define __ASM_ARCH_HARDWARE_K2L_H
+
+#define KS2_ARM_PLL_EN BIT(13)
+
+/* PA SS Registers */
+#define KS2_PASS_BASE 0x26000000
+
+/* Power and Sleep Controller (PSC) Domains */
+#define KS2_LPSC_MOD 0
+#define KS2_LPSC_DFE_IQN_SYS 1
+#define KS2_LPSC_USB 2
+#define KS2_LPSC_EMIF25_SPI 3
+#define KS2_LPSC_TSIP 4
+#define KS2_LPSC_DEBUGSS_TRC 5
+#define KS2_LPSC_TETB_TRC 6
+#define KS2_LPSC_PKTPROC 7
+#define KS2_LPSC_PA KS2_LPSC_PKTPROC
+#define KS2_LPSC_SGMII 8
+#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII
+#define KS2_LPSC_CRYPTO 9
+#define KS2_LPSC_PCIE0 10
+#define KS2_LPSC_PCIE1 11
+#define KS2_LPSC_JESD_MISC 12
+#define KS2_LPSC_CHIP_SRSS 13
+#define KS2_LPSC_MSMC 14
+#define KS2_LPSC_GEM_1 16
+#define KS2_LPSC_GEM_2 17
+#define KS2_LPSC_GEM_3 18
+#define KS2_LPSC_EMIF4F_DDR3 23
+#define KS2_LPSC_TAC 25
+#define KS2_LPSC_RAC 26
+#define KS2_LPSC_DDUC4X_CFR2X_BB 27
+#define KS2_LPSC_FFTC_A 28
+#define KS2_LPSC_OSR 34
+#define KS2_LPSC_TCP3D_0 35
+#define KS2_LPSC_TCP3D_1 37
+#define KS2_LPSC_VCP2X4_A 39
+#define KS2_LPSC_VCP2X4_B 40
+#define KS2_LPSC_VCP2X4_C 41
+#define KS2_LPSC_VCP2X4_D 42
+#define KS2_LPSC_BCP 47
+#define KS2_LPSC_DPD4X 48
+#define KS2_LPSC_FFTC_B 49
+#define KS2_LPSC_IQN_AIL 50
+
+/* MSMC */
+#define KS2_MSMC_SEGMENT_PCIE1 14
+
+/* Chip Interrupt Controller */
+#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3
+#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D
+
+/* OSR */
+#define KS2_OSR_DATA_BASE 0x70000000 /* OSR data base */
+#define KS2_OSR_CFG_BASE 0x02348c00 /* OSR config base */
+#define KS2_OSR_ECC_VEC 0x08 /* ECC Vector reg */
+#define KS2_OSR_ECC_CTRL 0x14 /* ECC control reg */
+
+/* OSR ECC Vector register */
+#define KS2_OSR_ECC_VEC_TRIG_RD BIT(15) /* trigger a read op */
+#define KS2_OSR_ECC_VEC_RD_DONE BIT(24) /* read complete */
+
+#define KS2_OSR_ECC_VEC_RAM_ID_SH 0 /* RAM ID shift */
+#define KS2_OSR_ECC_VEC_RD_ADDR_SH 16 /* read address shift */
+
+/* OSR ECC control register */
+#define KS2_OSR_ECC_CTRL_EN BIT(0) /* ECC enable bit */
+#define KS2_OSR_ECC_CTRL_CHK BIT(1) /* ECC check bit */
+#define KS2_OSR_ECC_CTRL_RMW BIT(2) /* ECC check bit */
+
+/* Number of OSR RAM banks */
+#define KS2_OSR_NUM_RAM_BANKS 4
+
+/* OSR memory size */
+#define KS2_OSR_SIZE 0x100000
+
+/* SGMII SerDes */
+#define KS2_SGMII_SERDES2_BASE 0x02320000
+#define KS2_LANES_PER_SGMII_SERDES 2
+
+/* Number of DSP cores */
+#define KS2_NUM_DSPS 4
+
+/* NETCP pktdma */
+#define KS2_NETCP_PDMA_CTRL_BASE 0x26186000
+#define KS2_NETCP_PDMA_TX_BASE 0x26187000
+#define KS2_NETCP_PDMA_TX_CH_NUM 21
+#define KS2_NETCP_PDMA_RX_BASE 0x26188000
+#define KS2_NETCP_PDMA_RX_CH_NUM 91
+#define KS2_NETCP_PDMA_SCHED_BASE 0x26186100
+#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x26189000
+#define KS2_NETCP_PDMA_RX_FLOW_NUM 96
+#define KS2_NETCP_PDMA_TX_SND_QUEUE 896
+
+/* NETCP */
+#define KS2_NETCP_BASE 0x26000000
+
+#endif /* __ASM_ARCH_HARDWARE_K2L_H */
#define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000
+/* DDR3 ECC */
+#define KS2_DDR3_ECC_INT_STATUS_OFFSET 0x0AC
+#define KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET 0x0B4
+#define KS2_DDR3_ECC_CTRL_OFFSET 0x110
+#define KS2_DDR3_ECC_ADDR_RANGE1_OFFSET 0x114
+#define KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET 0x130
+#define KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET 0x13C
+
+/* DDR3 ECC Interrupt Status register */
+#define KS2_DDR3_1B_ECC_ERR_SYS BIT(5)
+#define KS2_DDR3_2B_ECC_ERR_SYS BIT(4)
+#define KS2_DDR3_WR_ECC_ERR_SYS BIT(3)
+
+/* DDR3 ECC Control register */
+#define KS2_DDR3_ECC_EN BIT(31)
+#define KS2_DDR3_ECC_ADDR_RNG_PROT BIT(30)
+#define KS2_DDR3_ECC_VERIFY_EN BIT(29)
+#define KS2_DDR3_ECC_RMW_EN BIT(28)
+#define KS2_DDR3_ECC_ADDR_RNG_1_EN BIT(0)
+
+#define KS2_DDR3_ECC_ENABLE (KS2_DDR3_ECC_EN | \
+ KS2_DDR3_ECC_ADDR_RNG_PROT | \
+ KS2_DDR3_ECC_VERIFY_EN)
+
+/* EDMA */
+#define KS2_EDMA0_BASE 0x02700000
+
+/* EDMA3 register offsets */
+#define KS2_EDMA_QCHMAP0 0x0200
+#define KS2_EDMA_IPR 0x1068
+#define KS2_EDMA_ICR 0x1070
+#define KS2_EDMA_QEECR 0x1088
+#define KS2_EDMA_QEESR 0x108c
+#define KS2_EDMA_PARAM_1(x) (0x4020 + (4 * x))
+
+/* NETCP pktdma */
+#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001
+#define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002
+
+/* Chip Interrupt Controller */
+#define KS2_CIC2_BASE 0x02608000
+
+/* Chip Interrupt Controller register offsets */
+#define KS2_CIC_CTRL 0x04
+#define KS2_CIC_HOST_CTRL 0x0C
+#define KS2_CIC_GLOBAL_ENABLE 0x10
+#define KS2_CIC_SYS_ENABLE_IDX_SET 0x28
+#define KS2_CIC_HOST_ENABLE_IDX_SET 0x34
+#define KS2_CIC_CHAN_MAP(n) (0x0400 + (n << 2))
+
#define KS2_UART0_BASE 0x02530c00
#define KS2_UART1_BASE 0x02531000
/* Flag from ks2_debug options to check if DSPs need to stay ON */
#define DBG_LEAVE_DSPS_ON 0x1
+/* MSMC control */
+#define KS2_MSMC_CTRL_BASE 0x0bc00000
+#define KS2_MSMC_DATA_BASE 0x0c000000
+#define KS2_MSMC_SEGMENT_TETRIS 8
+#define KS2_MSMC_SEGMENT_NETCP 9
+#define KS2_MSMC_SEGMENT_QM_PDSP 10
+#define KS2_MSMC_SEGMENT_PCIE0 11
+
+/* MSMC segment size shift bits */
+#define KS2_MSMC_SEG_SIZE_SHIFT 12
+#define KS2_MSMC_MAP_SEG_NUM (2 << (30 - KS2_MSMC_SEG_SIZE_SHIFT))
+#define KS2_MSMC_DST_SEG_BASE (CONFIG_SYS_LPAE_SDRAM_BASE >> \
+ KS2_MSMC_SEG_SIZE_SHIFT)
+
/* Device speed */
#define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
#define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
+#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
/* Queue manager */
-#define KS2_QM_MANAGER_BASE 0x02a02000
+#define KS2_QM_BASE_ADDRESS 0x23a80000
+#define KS2_QM_CONF_BASE 0x02a02000
#define KS2_QM_DESC_SETUP_BASE 0x02a03000
-#define KS2_QM_MANAGER_QUEUES_BASEi 0x02a80000
+#define KS2_QM_STATUS_RAM_BASE 0x02a06000
+#define KS2_QM_INTD_CONF_BASE 0x02a0c000
+#define KS2_QM_PDSP1_CMD_BASE 0x02a20000
+#define KS2_QM_PDSP1_CTRL_BASE 0x02a0f000
+#define KS2_QM_PDSP1_IRAM_BASE 0x02a10000
+#define KS2_QM_MANAGER_QUEUES_BASE 0x02a80000
#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000
+#define KS2_QM_LINK_RAM_BASE 0x00100000
+#define KS2_QM_REGION_NUM 64
+#define KS2_QM_QPOOL_NUM 4000
-/* MSMC control */
-#define KS2_MSMC_CTRL_BASE 0x0bc00000
+/* USB */
+#define KS2_USB_SS_BASE 0x02680000
+#define KS2_USB_HOST_XHCI_BASE (KS2_USB_SS_BASE + 0x10000)
+#define KS2_DEV_USB_PHY_BASE 0x02620738
+#define KS2_USB_PHY_CFG_BASE 0x02630000
+
+#define KS2_MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
+
+/* SGMII SerDes */
+#define KS2_SGMII_SERDES_BASE 0x0232a000
#ifdef CONFIG_SOC_K2HK
#include <asm/arch/hardware-k2hk.h>
#include <asm/arch/hardware-k2e.h>
#endif
+#ifdef CONFIG_SOC_K2L
+#include <asm/arch/hardware-k2l.h>
+#endif
+
#ifndef __ASSEMBLY__
static inline int cpu_is_k2hk(void)
{
return (part_no == 0xb9a6) ? 1 : 0;
}
+static inline int cpu_is_k2l(void)
+{
+ unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
+ unsigned int part_no = (jtag_id >> 12) & 0xffff;
+
+ return (part_no == 0xb9a7) ? 1 : 0;
+}
+
static inline int cpu_revision(void)
{
unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
#include <asm/arch/hardware.h>
+enum mpax_seg_size {
+ MPAX_SEG_4K = 0x0b,
+ MPAX_SEG_8K,
+ MPAX_SEG_16K,
+ MPAX_SEG_32K,
+ MPAX_SEG_64K,
+ MPAX_SEG_128K,
+ MPAX_SEG_256K,
+ MPAX_SEG_512K,
+ MPAX_SEG_1M,
+ MPAX_SEG_2M,
+ MPAX_SEG_4M,
+ MPAX_SEG_8M,
+ MPAX_SEG_16M,
+ MPAX_SEG_32M,
+ MPAX_SEG_64M,
+ MPAX_SEG_128M,
+ MPAX_SEG_256M,
+ MPAX_SEG_512M,
+ MPAX_SEG_1G,
+ MPAX_SEG_2G,
+ MPAX_SEG_4G
+};
+
void msmc_share_all_segments(int priv_id);
+void msmc_get_ses_mpax(int priv_id, int ses_pair, u32 *mpax);
+void msmc_set_ses_mpax(int priv_id, int ses_pair, u32 *mpax);
+void msmc_map_ses_segment(int priv_id, int ses_pair,
+ u32 src_pfn, u32 dst_pfn, enum mpax_seg_size size);
#endif
+++ /dev/null
-/*
- * (C) Copyright 2012-2014
- * Texas Instruments, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _ASM_ARCH_SPL_H_
-#define _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_SPI 2
-
-#endif
--- /dev/null
+/*
+ * USB 3.0 DRD Controller
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define USB3_PHY_REF_SSP_EN BIT(29)
+#define USB3_PHY_OTG_VBUSVLDECTSEL BIT(16)
+
+/* KEYSTONE2 XHCI PHY register structure */
+struct keystone_xhci_phy {
+ unsigned int phy_utmi; /* ctl0 */
+ unsigned int phy_pipe; /* ctl1 */
+ unsigned int phy_param_ctrl_1; /* ctl2 */
+ unsigned int phy_param_ctrl_2; /* ctl3 */
+ unsigned int phy_clock; /* ctl4 */
+ unsigned int phy_pll; /* ctl5 */
+};
u32 analog_pll_video_tog;
u32 analog_pll_video_num; /* 0x40b0 */
u32 analog_reserved6[3];
- u32 analog_pll_vedio_denon; /* 0x40c0 */
+ u32 analog_pll_video_denom; /* 0x40c0 */
u32 analog_reserved7[7];
u32 analog_pll_enet; /* 0x40e0 */
u32 analog_pll_enet_set;
#ifdef CONFIG_MX6SX
#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7)
#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
+#endif
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
#define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
#endif
#define BF_ANADIG_PLL_VIDEO_RSVD0(v) \
(((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
-#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19
-#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000
-#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \
- (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
+#define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19
+#define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000
+#define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \
+ (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI = IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, 0),
MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK = IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, 0),
MX6_PAD_ECSPI1_SS0__GPIO4_IO11 = IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT4__USDHC1_DAT4 = IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT5__USDHC1_DAT5 = IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT6__USDHC1_DAT6 = IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT7__USDHC1_DAT7 = IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW7__GPIO_4_7 = IOMUX_PAD(0x04B0, 0x01A8, 5, 0x0000, 0, 0),
MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0),
MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT7__GPIO_5_0 = IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, 0),
+ MX6_PAD_REF_CLK_32K__GPIO_3_22 = IOMUX_PAD(0x0530, 0x0228, 5, 0x0000, 0, 0),
MX6_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0),
MX6_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0),
#ifndef __SYS_PROTO_H__
#define __SYS_PROTO_H__
+#include <asm/imx-common/regs-common.h>
+
int mxs_reset_block(struct mxs_register_32 *reg);
int mxs_wait_mask_set(struct mxs_register_32 *reg,
uint32_t mask,
#define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18
#define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A
#define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2
-#define CONTROL_PADCONF_JTAG_nTRST 0x0A1C
+#define CONTROL_PADCONF_JTAG_NTRST 0x0A1C
#define CONTROL_PADCONF_JTAG_TCK 0x0A1E
#define CONTROL_PADCONF_JTAG_TMS 0x0A20
#define CONTROL_PADCONF_JTAG_TDI 0x0A22
#define OMAP34XX_CTRL_WKUP_CTRL (OMAP34XX_CTRL_BASE + 0x0A5C)
#define OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ (1<<6)
-#define MUX_VAL(OFFSET,VALUE)\
+#define MUX_VAL(OFFSET, VALUE)\
writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
#define CP(x) (CONTROL_PADCONF_##x)
u32 get_boot_type(void);
void invalidate_dcache(u32);
u32 wait_on_value(u32, u32, void *, u32);
+void cancel_out(u32 *num, u32 *den, u32 den_limit);
void sdelay(unsigned long);
void make_cs1_contiguous(void);
void omap_nand_switch_ecc(uint32_t, uint32_t);
#define PLL0CR 0xE61500D8
#define PLL0_STC_MASK 0x7F000000
#define PLL0_STC_BIT 24
+#define PLLECR 0xE61500D0
+#define PLL0ST 0x100
#ifndef __ASSEMBLY__
#include <asm/types.h>
+++ /dev/null
-/*
- * Copyright (C) 2012 Pavel Machek <pavel@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SOCFPGA_SPL_H_
-#define _SOCFPGA_SPL_H_
-
-/* Symbols from linker script */
-extern char __malloc_start, __malloc_end, __stack_start;
-
-#define BOOT_DEVICE_RAM 1
-
-#endif
#define CLK_GATE_CLOSE 0x0
/* clock control module regs definition */
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
+#include <asm/arch/clock_sun6i.h>
+#else
#include <asm/arch/clock_sun4i.h>
+#endif
#ifndef __ASSEMBLY__
int clock_init(void);
int clock_twi_onoff(int port, int state);
void clock_set_pll1(unsigned int hz);
+unsigned int clock_get_pll5p(void);
unsigned int clock_get_pll6(void);
void clock_init_safe(void);
void clock_init_uart(void);
#define CCM_PLL5_CTRL_M1_MASK CCM_PLL5_CTRL_M1(0x3)
#define CCM_PLL5_CTRL_M1_X(n) ((n) - 1)
#define CCM_PLL5_CTRL_K(n) (((n) & 0x3) << 4)
+#define CCM_PLL5_CTRL_K_SHIFT 4
#define CCM_PLL5_CTRL_K_MASK CCM_PLL5_CTRL_K(0x3)
#define CCM_PLL5_CTRL_K_X(n) ((n) - 1)
#define CCM_PLL5_CTRL_LDO (0x1 << 7)
#define CCM_PLL5_CTRL_N(n) (((n) & 0x1f) << 8)
+#define CCM_PLL5_CTRL_N_SHIFT 8
#define CCM_PLL5_CTRL_N_MASK CCM_PLL5_CTRL_N(0x1f)
#define CCM_PLL5_CTRL_N_X(n) (n)
#define CCM_PLL5_CTRL_P(n) (((n) & 0x3) << 16)
+#define CCM_PLL5_CTRL_P_SHIFT 16
#define CCM_PLL5_CTRL_P_MASK CCM_PLL5_CTRL_P(0x3)
#define CCM_PLL5_CTRL_P_X(n) ((n) - 1)
#define CCM_PLL5_CTRL_BW (0x1 << 18)
--- /dev/null
+/*
+ * sun6i clock register definitions
+ *
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_CLOCK_SUN6I_H
+#define _SUNXI_CLOCK_SUN6I_H
+
+struct sunxi_ccm_reg {
+ u32 pll1_cfg; /* 0x00 pll1 control */
+ u32 reserved0;
+ u32 pll2_cfg; /* 0x08 pll2 control */
+ u32 reserved1;
+ u32 pll3_cfg; /* 0x10 pll3 control */
+ u32 reserved2;
+ u32 pll4_cfg; /* 0x18 pll4 control */
+ u32 reserved3;
+ u32 pll5_cfg; /* 0x20 pll5 control */
+ u32 reserved4;
+ u32 pll6_cfg; /* 0x28 pll6 control */
+ u32 reserved5;
+ u32 pll7_cfg; /* 0x30 pll7 control */
+ u32 reserved6;
+ u32 pll8_cfg; /* 0x38 pll8 control */
+ u32 reserved7;
+ u32 mipi_pll_cfg; /* 0x40 MIPI pll control */
+ u32 pll9_cfg; /* 0x44 pll9 control */
+ u32 pll10_cfg; /* 0x48 pll10 control */
+ u32 reserved8;
+ u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */
+ u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */
+ u32 apb2_div; /* 0x58 APB2 divide ratio */
+ u32 axi_gate; /* 0x5c axi module clock gating */
+ u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */
+ u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */
+ u32 apb1_gate; /* 0x68 apb1 module clock gating */
+ u32 apb2_gate; /* 0x6c apb2 module clock gating */
+ u32 reserved9[4];
+ u32 nand0_clk_cfg; /* 0x80 nand0 clock control */
+ u32 nand1_clk_cfg; /* 0x84 nand1 clock control */
+ u32 sd0_clk_cfg; /* 0x88 sd0 clock control */
+ u32 sd1_clk_cfg; /* 0x8c sd1 clock control */
+ u32 sd2_clk_cfg; /* 0x90 sd2 clock control */
+ u32 sd3_clk_cfg; /* 0x94 sd3 clock control */
+ u32 ts_clk_cfg; /* 0x98 transport stream clock control */
+ u32 ss_clk_cfg; /* 0x9c security system clock control */
+ u32 spi0_clk_cfg; /* 0xa0 spi0 clock control */
+ u32 spi1_clk_cfg; /* 0xa4 spi1 clock control */
+ u32 spi2_clk_cfg; /* 0xa8 spi2 clock control */
+ u32 spi3_clk_cfg; /* 0xac spi3 clock control */
+ u32 i2s0_clk_cfg; /* 0xb0 I2S0 clock control*/
+ u32 i2s1_clk_cfg; /* 0xb4 I2S1 clock control */
+ u32 reserved10[2];
+ u32 spdif_clk_cfg; /* 0xc0 SPDIF clock control */
+ u32 reserved11[2];
+ u32 usb_clk_cfg; /* 0xcc USB clock control */
+ u32 gmac_clk_cfg; /* 0xd0 GMAC clock control */
+ u32 reserved12[7];
+ u32 mdfs_clk_cfg; /* 0xf0 MDFS clock control */
+ u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */
+ u32 reserved13[2];
+ u32 dram_clk_gate; /* 0x100 DRAM module gating */
+ u32 be0_clk_cfg; /* 0x104 BE0 module clock */
+ u32 be1_clk_cfg; /* 0x108 BE1 module clock */
+ u32 fe0_clk_cfg; /* 0x10c FE0 module clock */
+ u32 fe1_clk_cfg; /* 0x110 FE1 module clock */
+ u32 mp_clk_cfg; /* 0x114 MP module clock */
+ u32 lcd0_ch0_clk_cfg; /* 0x118 LCD0 CH0 module clock */
+ u32 lcd1_ch0_clk_cfg; /* 0x11c LCD1 CH0 module clock */
+ u32 reserved14[3];
+ u32 lcd0_ch1_clk_cfg; /* 0x12c LCD0 CH1 module clock */
+ u32 lcd1_ch1_clk_cfg; /* 0x130 LCD1 CH1 module clock */
+ u32 csi0_clk_cfg; /* 0x134 CSI0 module clock */
+ u32 csi1_clk_cfg; /* 0x138 CSI1 module clock */
+ u32 ve_clk_cfg; /* 0x13c VE module clock */
+ u32 adda_clk_cfg; /* 0x140 ADDA module clock */
+ u32 avs_clk_cfg; /* 0x144 AVS module clock */
+ u32 dmic_clk_cfg; /* 0x148 Digital Mic module clock*/
+ u32 reserved15;
+ u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */
+ u32 ps_clk_cfg; /* 0x154 PS module clock */
+ u32 mtc_clk_cfg; /* 0x158 MTC module clock */
+ u32 mbus0_clk_cfg; /* 0x15c MBUS0 module clock */
+ u32 mbus1_clk_cfg; /* 0x160 MBUS1 module clock */
+ u32 reserved16;
+ u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */
+ u32 mipi_csi_clk_cfg; /* 0x16c MIPI CSI clock control */
+ u32 reserved17[4];
+ u32 iep_drc0_clk_cfg; /* 0x180 IEP DRC0 module clock */
+ u32 iep_drc1_clk_cfg; /* 0x184 IEP DRC1 module clock */
+ u32 iep_deu0_clk_cfg; /* 0x188 IEP DEU0 module clock */
+ u32 iep_deu1_clk_cfg; /* 0x18c IEP DEU1 module clock */
+ u32 reserved18[4];
+ u32 gpu_core_clk_cfg; /* 0x1a0 GPU core clock config */
+ u32 gpu_mem_clk_cfg; /* 0x1a4 GPU memory clock config */
+ u32 gpu_hyd_clk_cfg; /* 0x1a0 GPU HYD clock config */
+ u32 reserved19[21];
+ u32 pll_lock; /* 0x200 PLL Lock Time */
+ u32 pll1_lock; /* 0x204 PLL1 Lock Time */
+ u32 reserved20[6];
+ u32 pll1_bias_cfg; /* 0x220 PLL1 Bias config */
+ u32 pll2_bias_cfg; /* 0x224 PLL2 Bias config */
+ u32 pll3_bias_cfg; /* 0x228 PLL3 Bias config */
+ u32 pll4_bias_cfg; /* 0x22c PLL4 Bias config */
+ u32 pll5_bias_cfg; /* 0x230 PLL5 Bias config */
+ u32 pll6_bias_cfg; /* 0x234 PLL6 Bias config */
+ u32 pll7_bias_cfg; /* 0x238 PLL7 Bias config */
+ u32 pll8_bias_cfg; /* 0x23c PLL8 Bias config */
+ u32 mipi_bias_cfg; /* 0x240 MIPI Bias config */
+ u32 pll9_bias_cfg; /* 0x244 PLL9 Bias config */
+ u32 pll10_bias_cfg; /* 0x248 PLL10 Bias config */
+ u32 reserved21[13];
+ u32 pll1_pattern_cfg; /* 0x280 PLL1 Pattern config */
+ u32 pll2_pattern_cfg; /* 0x284 PLL2 Pattern config */
+ u32 pll3_pattern_cfg; /* 0x288 PLL3 Pattern config */
+ u32 pll4_pattern_cfg; /* 0x28c PLL4 Pattern config */
+ u32 pll5_pattern_cfg; /* 0x290 PLL5 Pattern config */
+ u32 pll6_pattern_cfg; /* 0x294 PLL6 Pattern config */
+ u32 pll7_pattern_cfg; /* 0x298 PLL7 Pattern config */
+ u32 pll8_pattern_cfg; /* 0x29c PLL8 Pattern config */
+ u32 mipi_pattern_cfg; /* 0x2a0 MIPI Pattern config */
+ u32 pll9_pattern_cfg; /* 0x2a4 PLL9 Pattern config */
+ u32 pll10_pattern_cfg; /* 0x2a8 PLL10 Pattern config */
+ u32 reserved22[5];
+ u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */
+ u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */
+ u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */
+ u32 reserved23;
+ u32 apb1_reset_cfg; /* 0x2d0 APB1 Reset config */
+ u32 reserved24;
+ u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */
+};
+
+/* apb2 bit field */
+#define APB2_CLK_SRC_LOSC (0x0 << 24)
+#define APB2_CLK_SRC_OSC24M (0x1 << 24)
+#define APB2_CLK_SRC_PLL6 (0x2 << 24)
+#define APB2_CLK_SRC_MASK (0x3 << 24)
+#define APB2_CLK_RATE_N_1 (0x0 << 16)
+#define APB2_CLK_RATE_N_2 (0x1 << 16)
+#define APB2_CLK_RATE_N_4 (0x2 << 16)
+#define APB2_CLK_RATE_N_8 (0x3 << 16)
+#define APB2_CLK_RATE_N_MASK (3 << 16)
+#define APB2_CLK_RATE_M(m) (((m)-1) << 0)
+#define APB2_CLK_RATE_M_MASK (0x1f << 0)
+
+/* apb2 gate field */
+#define APB2_GATE_UART_SHIFT (16)
+#define APB2_GATE_UART_MASK (0xff << APB2_GATE_UART_SHIFT)
+#define APB2_GATE_TWI_SHIFT (0)
+#define APB2_GATE_TWI_MASK (0xf << APB2_GATE_TWI_SHIFT)
+
+/* cpu_axi_cfg bits */
+#define AXI_DIV_SHIFT 0
+#define ATB_DIV_SHIFT 8
+#define CPU_CLK_SRC_SHIFT 16
+
+#define AXI_DIV_1 0
+#define AXI_DIV_2 1
+#define AXI_DIV_3 2
+#define AXI_DIV_4 3
+#define ATB_DIV_1 0
+#define ATB_DIV_2 1
+#define ATB_DIV_4 2
+#define CPU_CLK_SRC_OSC24M 1
+#define CPU_CLK_SRC_PLL1 2
+
+#define PLL1_CFG_DEFAULT 0x90011b21
+
+#define PLL6_CFG_DEFAULT 0x90041811
+
+#define CCM_PLL6_CTRL_N_SHIFT 8
+#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
+#define CCM_PLL6_CTRL_K_SHIFT 4
+#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
+
+#define AHB_GATE_OFFSET_MMC3 11
+#define AHB_GATE_OFFSET_MMC2 10
+#define AHB_GATE_OFFSET_MMC1 9
+#define AHB_GATE_OFFSET_MMC0 8
+#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n))
+
+#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
+#define CCM_MMC_CTRL_PLL6 (0x1 << 24)
+
+#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
+
+#define AHB_RESET_OFFSET_MMC3 11
+#define AHB_RESET_OFFSET_MMC2 10
+#define AHB_RESET_OFFSET_MMC1 9
+#define AHB_RESET_OFFSET_MMC0 8
+#define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n))
+
+/* apb2 reset */
+#define APB2_RESET_UART_SHIFT (16)
+#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT)
+#define APB2_RESET_TWI_SHIFT (0)
+#define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT)
+
+#endif /* _SUNXI_CLOCK_SUN6I_H */
#define SUNXI_MALI400_BASE 0x01c40000
#define SUNXI_GMAC_BASE 0x01c50000
+#define SUNXI_DRAM_COM_BASE 0x01c62000
+#define SUNXI_DRAM_CTL_BASE 0x01c63000
+#define SUNXI_DRAM_PHY_CH1_BASE 0x01c65000
+#define SUNXI_DRAM_PHY_CH2_BASE 0x01c66000
+
/* module sram */
#define SUNXI_SRAM_C_BASE 0x01d00000
#define SUNXI_MP_BASE 0x01e80000
#define SUNXI_AVG_BASE 0x01ea0000
+#define SUNXI_PRCM_BASE 0x01f01400
+#define SUNXI_R_UART_BASE 0x01f02800
+#define SUNXI_R_PIO_BASE 0x01f02c00
+#define SUNXI_P2WI_BASE 0x01f03400
+
/* CoreSight Debug Module */
#define SUNXI_CSDM_BASE 0x3f500000
#define _SUNXI_GPIO_H
#include <linux/types.h>
+#include <asm/arch/cpu.h>
/*
* sunxi has 9 banks of gpio, they are:
#define SUNXI_GPIO_G 6
#define SUNXI_GPIO_H 7
#define SUNXI_GPIO_I 8
+
+/*
+ * This defines the number of GPIO banks for the _main_ GPIO controller.
+ * You should fix up the padding in struct sunxi_gpio_reg below if you
+ * change this.
+ */
#define SUNXI_GPIO_BANKS 9
+/*
+ * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO)
+ * at a different register offset.
+ *
+ * sun6i has 2 banks:
+ * PL0 - PL8 | PM0 - PM7
+ *
+ * sun8i has 1 bank:
+ * PL0 - PL11
+ */
+#define SUNXI_GPIO_L 11
+#define SUNXI_GPIO_M 12
+
struct sunxi_gpio {
u32 cfg[4];
u32 dat;
struct sunxi_gpio_int gpio_int;
};
-#define BANK_TO_GPIO(bank) \
- &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]
+#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \
+ &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
+ &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L])
#define GPIO_BANK(pin) ((pin) >> 5)
#define GPIO_NUM(pin) ((pin) & 0x1f)
#define SUNXI_GPIO_G_NR 32
#define SUNXI_GPIO_H_NR 32
#define SUNXI_GPIO_I_NR 32
+#define SUNXI_GPIO_L_NR 32
+#define SUNXI_GPIO_M_NR 32
#define SUNXI_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + 0)
SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F),
SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G),
SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
+ SUNXI_GPIO_L_START = 352,
+ SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
};
/* SUNXI GPIO number definitions */
#define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr))
#define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr))
#define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr))
+#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr))
+#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr))
/* GPIO pin function config */
#define SUNXI_GPIO_INPUT 0
#define SUN5I_GPB19_UART0_TX 2
#define SUN5I_GPB20_UART0_RX 2
+#define SUN5I_GPG3_SDC1 2
+
#define SUN5I_GPG3_UART1_TX 4
#define SUN5I_GPG4_UART1_RX 4
#define SUNXI_GPF0_SDC0 2
#define SUNXI_GPF2_SDC0 2
+
+#ifdef CONFIG_MACH_SUN8I
+#define SUNXI_GPF2_UART0_TX 3
+#define SUNXI_GPF4_UART0_RX 3
+#else
#define SUNXI_GPF2_UART0_TX 4
#define SUNXI_GPF4_UART0_RX 4
+#endif
#define SUN4I_GPG0_SDC1 4
#define SUN4I_GPH22_SDC1 5
+#define SUN6I_GPH20_UART0_TX 2
+#define SUN6I_GPH21_UART0_RX 2
+
#define SUN4I_GPI4_SDC3 2
+#define SUN8I_GPL2_R_UART_TX 2
+#define SUN8I_GPL3_R_UART_RX 2
+
/* GPIO pin pull-up/down config */
#define SUNXI_GPIO_PULL_DISABLE 0
#define SUNXI_GPIO_PULL_UP 1
#define SUNXI_GPIO_PULL_DOWN 2
-int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
+void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val);
+void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
+int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
int sunxi_gpio_get_cfgpin(u32 pin);
int sunxi_gpio_set_drv(u32 pin, u32 val);
int sunxi_gpio_set_pull(u32 pin, u32 val);
u32 chda; /* 0x90 */
u32 cbda; /* 0x94 */
u32 res1[26];
- u32 fifo; /* 0x100 FIFO access address */
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
+ u32 res2[64];
+#endif
+ u32 fifo; /* 0x100 (0x200 on sun6i) FIFO access address */
};
#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17)
#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0)
#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1)
-int sunxi_mmc_init(int sdc_no);
+struct mmc *sunxi_mmc_init(int sdc_no);
#endif /* _SUNXI_MMC_H */
--- /dev/null
+/*
+ * Sunxi A31 Power Management Unit register definition.
+ *
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ * http://linux-sunxi.org
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_PRCM_H
+#define _SUNXI_PRCM_H
+
+#define __PRCM_CPUS_CFG_PRE(n) (((n) & 0x3) << 4)
+#define PRCM_CPUS_CFG_PRE_MASK __PRCM_CPUS_CFG_PRE(0x3)
+#define __PRCM_CPUS_CFG_PRE_DIV(n) (((n) >> 1) - 1)
+#define PRCM_CPUS_CFG_PRE_DIV(n) \
+ __PRCM_CPUS_CFG_PRE(__PRCM_CPUS_CFG_CLK_PRE(n))
+#define __PRCM_CPUS_CFG_POST(n) (((n) & 0x1f) << 8)
+#define PRCM_CPUS_CFG_POST_MASK __PRCM_CPUS_CFG_POST(0x1f)
+#define __PRCM_CPUS_CFG_POST_DIV(n) ((n) - 1)
+#define PRCM_CPUS_CFG_POST_DIV(n) \
+ __PRCM_CPUS_CFG_POST_DIV(__PRCM_CPUS_CFG_POST_DIV(n))
+#define __PRCM_CPUS_CFG_CLK_SRC(n) (((n) & 0x3) << 16)
+#define PRCM_CPUS_CFG_CLK_SRC_MASK __PRCM_CPUS_CFG_CLK_SRC(0x3)
+#define __PRCM_CPUS_CFG_CLK_SRC_LOSC 0x0
+#define __PRCM_CPUS_CFG_CLK_SRC_HOSC 0x1
+#define __PRCM_CPUS_CFG_CLK_SRC_PLL6 0x2
+#define __PRCM_CPUS_CFG_CLK_SRC_PDIV 0x3
+#define PRCM_CPUS_CFG_CLK_SRC_LOSC \
+ __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_LOSC)
+#define PRCM_CPUS_CFG_CLK_SRC_HOSC \
+ __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_HOSC)
+#define PRCM_CPUS_CFG_CLK_SRC_PLL6 \
+ __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PLL6)
+#define PRCM_CPUS_CFG_CLK_SRC_PDIV \
+ __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PDIV)
+
+#define __PRCM_APB0_RATIO(n) (((n) & 0x3) << 0)
+#define PRCM_APB0_RATIO_DIV_MASK __PRCM_APB0_RATIO_DIV(0x3)
+#define __PRCM_APB0_RATIO_DIV(n) (((n) >> 1) - 1)
+#define PRCM_APB0_RATIO_DIV(n) \
+ __PRCM_APB0_RATIO(__PRCM_APB0_RATIO_DIV(n))
+
+#define PRCM_CPU_CFG_NEON_CLK_EN (0x1 << 0)
+#define PRCM_CPU_CFG_CPU_CLK_EN (0x1 << 1)
+
+#define PRCM_APB0_GATE_PIO (0x1 << 0)
+#define PRCM_APB0_GATE_IR (0x1 << 1)
+#define PRCM_APB0_GATE_TIMER01 (0x1 << 2)
+#define PRCM_APB0_GATE_P2WI (0x1 << 3)
+#define PRCM_APB0_GATE_UART (0x1 << 4)
+#define PRCM_APB0_GATE_1WIRE (0x1 << 5)
+#define PRCM_APB0_GATE_I2C (0x1 << 6)
+
+#define PRCM_APB0_RESET_PIO (0x1 << 0)
+#define PRCM_APB0_RESET_IR (0x1 << 1)
+#define PRCM_APB0_RESET_TIMER01 (0x1 << 2)
+#define PRCM_APB0_RESET_P2WI (0x1 << 3)
+#define PRCM_APB0_RESET_UART (0x1 << 4)
+#define PRCM_APB0_RESET_1WIRE (0x1 << 5)
+#define PRCM_APB0_RESET_I2C (0x1 << 6)
+
+#define PRCM_PLL_CTRL_PLL_BIAS (0x1 << 0)
+#define PRCM_PLL_CTRL_HOSC_GAIN_ENH (0x1 << 1)
+#define __PRCM_PLL_CTRL_USB_CLK_SRC(n) (((n) & 0x3) << 4)
+#define PRCM_PLL_CTRL_USB_CLK_SRC_MASK \
+ __PRCM_PLL_CTRL_USB_CLK_SRC(0x3)
+#define __PRCM_PLL_CTRL_USB_CLK_0 0x0
+#define __PRCM_PLL_CTRL_USB_CLK_1 0x1
+#define __PRCM_PLL_CTRL_USB_CLK_2 0x2
+#define __PRCM_PLL_CTRL_USB_CLK_3 0x3
+#define PRCM_PLL_CTRL_USB_CLK_0 \
+ __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_0)
+#define PRCM_PLL_CTRL_USB_CLK_1 \
+ __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_1)
+#define PRCM_PLL_CTRL_USB_CLK_2 \
+ __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_2)
+#define PRCM_PLL_CTRL_USB_CLK_3 \
+ __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_3)
+#define __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) (((n) & 0x3) << 12)
+#define PRCM_PLL_CTRL_INT_PLL_IN_SEL_MASK \
+ __PRCM_PLL_CTRL_INT_PLL_IN_SEL(0x3)
+#define PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) \
+ __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n)
+#define __PRCM_PLL_CTRL_HOSC_CLK_SEL(n) (((n) & 0x3) << 20)
+#define PRCM_PLL_CTRL_HOSC_CLK_SEL_MASK \
+ __PRCM_PLL_CTRL_HOSC_CLK_SEL(0x3)
+#define __PRCM_PLL_CTRL_HOSC_CLK_0 0x0
+#define __PRCM_PLL_CTRL_HOSC_CLK_1 0x1
+#define __PRCM_PLL_CTRL_HOSC_CLK_2 0x2
+#define __PRCM_PLL_CTRL_HOSC_CLK_3 0x3
+#define PRCM_PLL_CTRL_HOSC_CLK_0 \
+ __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_0)
+#define PRCM_PLL_CTRL_HOSC_CLK_1 \
+ __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_1)
+#define PRCM_PLL_CTRL_HOSC_CLK_2 \
+ __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_2)
+#define PRCM_PLL_CTRL_HOSC_CLK_3 \
+ __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_3)
+#define PRCM_PLL_CTRL_PLL_TST_SRC_EXT (0x1 << 24)
+#define PRCM_PLL_CTRL_LDO_DIGITAL_EN (0x1 << 0)
+#define PRCM_PLL_CTRL_LDO_ANALOG_EN (0x1 << 1)
+#define PRCM_PLL_CTRL_EXT_OSC_EN (0x1 << 2)
+#define PRCM_PLL_CTRL_CLK_TST_EN (0x1 << 3)
+#define PRCM_PLL_CTRL_IN_PWR_HIGH (0x1 << 15) /* 3.3 for hi 2.5 for lo */
+#define __PRCM_PLL_CTRL_VDD_LDO_OUT(n) (((n) & 0x7) << 16)
+#define PRCM_PLL_CTRL_LDO_OUT_MASK \
+ __PRCM_PLL_CTRL_LDO_OUT(0x7)
+/* When using the low voltage 20 mV steps, and high voltage 30 mV steps */
+#define PRCM_PLL_CTRL_LDO_OUT_L(n) \
+ __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)
+#define PRCM_PLL_CTRL_LDO_OUT_H(n) \
+ __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7)
+#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \
+ __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)
+#define PRCM_PLL_CTRL_LDO_OUT_HV(n) \
+ __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160)
+#define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24)
+
+#define PRCM_CLK_1WIRE_GATE (0x1 << 31)
+
+#define __PRCM_CLK_MOD0_M(n) (((n) & 0xf) << 0)
+#define PRCM_CLK_MOD0_M_MASK __PRCM_CLK_MOD0_M(0xf)
+#define __PRCM_CLK_MOD0_M_X(n) (n - 1)
+#define PRCM_CLK_MOD0_M(n) __PRCM_CLK_MOD0_M(__PRCM_CLK_MOD0_M_X(n))
+#define PRCM_CLK_MOD0_OUT_PHASE(n) (((n) & 0x7) << 8)
+#define PRCM_CLK_MOD0_OUT_PHASE_MASK(n) PRCM_CLK_MOD0_OUT_PHASE(0x7)
+#define _PRCM_CLK_MOD0_N(n) (((n) & 0x3) << 16)
+#define PRCM_CLK_MOD0_N_MASK __PRCM_CLK_MOD_N(0x3)
+#define __PRCM_CLK_MOD0_N_X(n) (((n) >> 1) - 1)
+#define PRCM_CLK_MOD0_N(n) __PRCM_CLK_MOD0_N(__PRCM_CLK_MOD0_N_X(n))
+#define PRCM_CLK_MOD0_SMPL_PHASE(n) (((n) & 0x7) << 20)
+#define PRCM_CLK_MOD0_SMPL_PHASE_MASK PRCM_CLK_MOD0_SMPL_PHASE(0x7)
+#define PRCM_CLK_MOD0_SRC_SEL(n) (((n) & 0x7) << 24)
+#define PRCM_CLK_MOD0_SRC_SEL_MASK PRCM_CLK_MOD0_SRC_SEL(0x7)
+#define PRCM_CLK_MOD0_GATE_EN (0x1 << 31)
+
+#define PRCM_APB0_RESET_PIO (0x1 << 0)
+#define PRCM_APB0_RESET_IR (0x1 << 1)
+#define PRCM_APB0_RESET_TIMER01 (0x1 << 2)
+#define PRCM_APB0_RESET_P2WI (0x1 << 3)
+#define PRCM_APB0_RESET_UART (0x1 << 4)
+#define PRCM_APB0_RESET_1WIRE (0x1 << 5)
+#define PRCM_APB0_RESET_I2C (0x1 << 6)
+
+#define __PRCM_CLK_OUTD_M(n) (((n) & 0x7) << 8)
+#define PRCM_CLK_OUTD_M_MASK __PRCM_CLK_OUTD_M(0x7)
+#define __PRCM_CLK_OUTD_M_X() ((n) - 1)
+#define PRCM_CLK_OUTD_M(n) __PRCM_CLK_OUTD_M(__PRCM_CLK_OUTD_M_X(n))
+#define __PRCM_CLK_OUTD_N(n) (((n) & 0x7) << 20)
+#define PRCM_CLK_OUTD_N_MASK __PRCM_CLK_OUTD_N(0x7)
+#define __PRCM_CLK_OUTD_N_X(n) (((n) >> 1) - 1)
+#define PRCM_CLK_OUTD_N(n) __PRCM_CLK_OUTD_N(__PRCM_CLK_OUTD_N_X(n)
+#define __PRCM_CLK_OUTD_SRC_SEL(n) (((n) & 0x3) << 24)
+#define PRCM_CLK_OUTD_SRC_SEL_MASK __PRCM_CLK_OUTD_SRC_SEL(0x3)
+#define __PRCM_CLK_OUTD_SRC_LOSC2 0x0
+#define __PRCM_CLK_OUTD_SRC_LOSC 0x1
+#define __PRCM_CLK_OUTD_SRC_HOSC 0x2
+#define __PRCM_CLK_OUTD_SRC_ERR 0x3
+#define PRCM_CLK_OUTD_SRC_LOSC2 \
+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC2)
+#define PRCM_CLK_OUTD_SRC_LOSC \
+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC)
+#define PRCM_CLK_OUTD_SRC_HOSC \
+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_HOSC)
+#define PRCM_CLK_OUTD_SRC_ERR \
+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_ERR)
+#define PRCM_CLK_OUTD_EN (0x1 << 31)
+
+#define PRCM_CPU0_PWROFF (0x1 << 0)
+#define PRCM_CPU1_PWROFF (0x1 << 1)
+#define PRCM_CPU2_PWROFF (0x1 << 2)
+#define PRCM_CPU3_PWROFF (0x1 << 3)
+#define PRCM_CPU_ALL_PWROFF (0xf << 0)
+
+#define PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF (0x1 << 0)
+#define PRCM_VDD_SYS_DRAM_CH1_PAD_HOLD_PWROFF (0x1 << 1)
+#define PRCM_VDD_SYS_AVCC_A_PWROFF (0x1 << 2)
+#define PRCM_VDD_SYS_CPU0_VDD_PWROFF (0x1 << 3)
+
+#define PRCM_VDD_GPU_PWROFF (0x1 << 0)
+
+#define PRCM_VDD_SYS_RESET (0x1 << 0)
+
+#define PRCM_CPU1_PWR_CLAMP(n) (((n) & 0xff) << 0)
+#define PRCM_CPU1_PWR_CLAMP_MASK PRCM_CPU1_PWR_CLAMP(0xff)
+
+#define PRCM_CPU2_PWR_CLAMP(n) (((n) & 0xff) << 0)
+#define PRCM_CPU2_PWR_CLAMP_MASK PRCM_CPU2_PWR_CLAMP(0xff)
+
+#define PRCM_CPU3_PWR_CLAMP(n) (((n) & 0xff) << 0)
+#define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff)
+
+#ifndef __ASSEMBLY__
+struct sunxi_prcm_reg {
+ u32 cpus_cfg; /* 0x000 */
+ u8 res0[0x8]; /* 0x004 */
+ u32 apb0_ratio; /* 0x00c */
+ u32 cpu0_cfg; /* 0x010 */
+ u32 cpu1_cfg; /* 0x014 */
+ u32 cpu2_cfg; /* 0x018 */
+ u32 cpu3_cfg; /* 0x01c */
+ u8 res1[0x8]; /* 0x020 */
+ u32 apb0_gate; /* 0x028 */
+ u8 res2[0x14]; /* 0x02c */
+ u32 pll_ctrl0; /* 0x040 */
+ u32 pll_ctrl1; /* 0x044 */
+ u8 res3[0x8]; /* 0x048 */
+ u32 clk_1wire; /* 0x050 */
+ u32 clk_ir; /* 0x054 */
+ u8 res4[0x58]; /* 0x058 */
+ u32 apb0_reset; /* 0x0b0 */
+ u8 res5[0x3c]; /* 0x0b4 */
+ u32 clk_outd; /* 0x0f0 */
+ u8 res6[0xc]; /* 0x0f4 */
+ u32 cpu_pwroff; /* 0x100 */
+ u8 res7[0xc]; /* 0x104 */
+ u32 vdd_sys_pwroff; /* 0x110 */
+ u8 res8[0x4]; /* 0x114 */
+ u32 gpu_pwroff; /* 0x118 */
+ u8 res9[0x4]; /* 0x11c */
+ u32 vdd_pwr_reset; /* 0x120 */
+ u8 res10[0x20]; /* 0x124 */
+ u32 cpu1_pwr_clamp; /* 0x144 */
+ u32 cpu2_pwr_clamp; /* 0x148 */
+ u32 cpu3_pwr_clamp; /* 0x14c */
+ u8 res11[0x30]; /* 0x150 */
+ u32 dram_pwr; /* 0x180 */
+ u8 res12[0xc]; /* 0x184 */
+ u32 dram_tst; /* 0x190 */
+};
+
+void prcm_apb0_enable(u32 flags);
+#endif /* __ASSEMBLY__ */
+#endif /* _PRCM_H */
#ifndef _SUNXI_TIMER_H_
#define _SUNXI_TIMER_H_
-#define WDT_CTRL_RESTART (0x1 << 0)
-#define WDT_CTRL_KEY (0x0a57 << 1)
-#define WDT_MODE_EN (0x1 << 0)
-#define WDT_MODE_RESET_EN (0x1 << 1)
-
#ifndef __ASSEMBLY__
#include <linux/types.h>
+#include <asm/arch/watchdog.h>
/* General purpose timer */
struct sunxi_timer {
u32 hi; /* 0xa8 */
};
-/* Watchdog */
-struct sunxi_wdog {
- u32 ctl; /* 0x90 */
- u32 mode; /* 0x94 */
-};
-
/* Rtc */
struct sunxi_rtc {
u32 ctl; /* 0x100 */
struct sunxi_timer timer[6]; /* We have 6 timers */
u8 res2[16];
struct sunxi_avs avs;
- struct sunxi_wdog wdog;
- u8 res3[8];
- struct sunxi_64cnt cnt64;
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
+ struct sunxi_wdog wdog; /* 0x90 */
+ /* XXX the following is not accurate for sun5i/sun7i */
+ struct sunxi_64cnt cnt64; /* 0xa0 */
u8 res4[0x58];
struct sunxi_rtc rtc;
struct sunxi_alarm alarm;
struct sunxi_tgp tgp[4];
u8 res5[8];
u32 cpu_cfg;
+#else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || ... */
+ u8 res3[16];
+ struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */
+#endif
};
#endif /* __ASSEMBLY__ */
--- /dev/null
+/*
+ * (C) Copyright 2014
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * Watchdog register definitions
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_WATCHDOG_H_
+#define _SUNXI_WATCHDOG_H_
+
+#define WDT_CTRL_RESTART (0x1 << 0)
+#define WDT_CTRL_KEY (0x0a57 << 1)
+
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
+
+#define WDT_MODE_EN (0x1 << 0)
+#define WDT_MODE_RESET_EN (0x1 << 1)
+
+struct sunxi_wdog {
+ u32 ctl; /* 0x00 */
+ u32 mode; /* 0x04 */
+ u32 res[2];
+};
+
+#else
+
+#define WDT_CFG_RESET (0x1)
+#define WDT_MODE_EN (0x1)
+
+struct sunxi_wdog {
+ u32 irq_en; /* 0x00 */
+ u32 irq_sta; /* 0x04 */
+ u32 res1[2];
+ u32 ctl; /* 0x10 */
+ u32 cfg; /* 0x14 */
+ u32 mode; /* 0x18 */
+ u32 res2;
+};
+
+#endif
+
+#endif /* _SUNXI_WATCHDOG_H_ */
* an empty stub function will be called.
*/
-void pinmux_init(void); /* overrideable general pinmux setup */
-void pin_mux_usb(void); /* overrideable USB pinmux setup */
-void pin_mux_spi(void); /* overrideable SPI pinmux setup */
-void pin_mux_nand(void); /* overrideable NAND pinmux setup */
-void pin_mux_display(void); /* overrideable DISPLAY pinmux setup */
+void pinmux_init(void); /* overridable general pinmux setup */
+void pin_mux_usb(void); /* overridable USB pinmux setup */
+void pin_mux_spi(void); /* overridable SPI pinmux setup */
+void pin_mux_nand(void); /* overridable NAND pinmux setup */
+void pin_mux_mmc(void); /* overridable mmc pinmux setup */
+void pin_mux_display(void); /* overridable DISPLAY pinmux setup */
#endif
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_PLATDEVICE_H
+#define ARCH_PLATDEVICE_H
+
+#include <dm/platdata.h>
+#include <dm/platform_data/serial-uniphier.h>
+
+#define SERIAL_DEVICE(n, ba, clk) \
+static struct uniphier_serial_platform_data serial_device##n = { \
+ .base = ba, \
+ .uartclk = clk \
+}; \
+U_BOOT_DEVICE(serial##n) = { \
+ .name = DRIVER_NAME, \
+ .platdata = &serial_device##n \
+};
+
+#endif /* ARCH_PLATDEVICE_H */
void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
unsigned count);
+/*
+* Set bits for general purpose registers
+*/
+void imx_iomux_set_gpr_register(int group, int start_bit,
+ int num_bits, int value);
/* macros for declaring and using pinmux array */
#if defined(CONFIG_MX6QDL)
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MXC_SPI_H_
+#define __MXC_SPI_H_
+
+/*
+ * Board-level chip-select callback
+ * Should return GPIO # to be used for chip-select
+ */
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs);
+
+#endif
extern int detect_hdmi(struct display_info_t const *dev);
#endif
+#ifdef CONFIG_IMX_VIDEO_SKIP
+extern struct display_info_t const displays[];
+extern size_t display_count;
+#endif
+
#endif
#include <asm/arch/cpu.h>
+enum gpio_method {
+ METHOD_GPIO_24XX = 4,
+};
+
+#ifdef CONFIG_DM_GPIO
+
+/* Information about a GPIO bank */
+struct omap_gpio_platdata {
+ int bank_index;
+ ulong base; /* address of registers in physical memory */
+ enum gpio_method method;
+};
+
+#else
+
struct gpio_bank {
void *base;
int method;
extern const struct gpio_bank *const omap_gpio_bank;
-#define METHOD_GPIO_24XX 4
-
/**
* Check if gpio is valid.
*
* @return 1 if ok, 0 on error
*/
int gpio_is_valid(int gpio);
+#endif
+
#endif /* _GPIO_H_ */
#ifndef _ASM_SPL_H_
#define _ASM_SPL_H_
-#if defined(CONFIG_OMAP) || defined(CONFIG_SOCFPGA) \
+#if defined(CONFIG_OMAP) \
|| defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \
|| defined(CONFIG_EXYNOS4210)
/* Platform-specific defines */
#include <asm/arch/hardware.h>
#include <asm/io.h>
-enum soc_type_t {
- k2hk
-};
-
#define QM_OK 0
#define QM_ERR -1
#define QM_DESC_TYPE_HOST 0
u32 rx_flow; /* flow that is used for RX */
};
+extern struct pktdma_cfg netcp_pktdma;
+
/*
* packet dma user allocates memory for rx buffers
* and describe it in the following structure
u32 rx_flow;
};
-int netcp_close(void);
-int netcp_init(struct rx_buff_desc *rx_buffers);
-int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2);
-void *netcp_recv(u32 **pkt, int *num_bytes);
-void netcp_release_rxhd(void *hd);
+int ksnav_close(struct pktdma_cfg *pktdma);
+int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc *rx_buffers);
+int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes, u32 swinfo2);
+void *ksnav_recv(struct pktdma_cfg *pktdma, u32 **pkt, int *num_bytes);
+void ksnav_release_rxhd(struct pktdma_cfg *pktdma, void *hd);
#endif /* _KEYSTONE_NAV_H_ */
--- /dev/null
+/*
+ * emac definitions for keystone2 devices
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _KEYSTONE_NET_H_
+#define _KEYSTONE_NET_H_
+
+#include <asm/io.h>
+
+/* EMAC */
+#ifdef CONFIG_KSNET_NETCP_V1_0
+
+#define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00090000)
+#define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x900)
+#define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x300)
+#define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x100)
+#define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x040)
+
+/* Register offsets */
+#define CPGMACSL_REG_CTL 0x04
+#define CPGMACSL_REG_STATUS 0x08
+#define CPGMACSL_REG_RESET 0x0c
+#define CPGMACSL_REG_MAXLEN 0x10
+
+#elif defined CONFIG_KSNET_NETCP_V1_5
+
+#define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00200000)
+#define CPGMACSL_REG_RX_PRI_MAP 0x020
+#define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x22000)
+#define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x00f00)
+#define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x00100)
+#define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x1000)
+
+/* Register offsets */
+#define CPGMACSL_REG_CTL 0x330
+#define CPGMACSL_REG_STATUS 0x334
+#define CPGMACSL_REG_RESET 0x338
+#define CPGMACSL_REG_MAXLEN 0x024
+
+#endif
+
+#define KEYSTONE2_EMAC_GIG_ENABLE
+
+#define MAC_ID_BASE_ADDR CONFIG_KSNET_MAC_ID_BASE
+
+/* MDIO module input frequency */
+#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk))
+/* MDIO clock output frequency */
+#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */
+
+/* MII Status Register */
+#define MII_STATUS_REG 1
+#define MII_STATUS_LINK_MASK 0x4
+
+#define MDIO_CONTROL_IDLE 0x80000000
+#define MDIO_CONTROL_ENABLE 0x40000000
+#define MDIO_CONTROL_FAULT_ENABLE 0x40000
+#define MDIO_CONTROL_FAULT 0x80000
+#define MDIO_USERACCESS0_GO 0x80000000
+#define MDIO_USERACCESS0_WRITE_READ 0x0
+#define MDIO_USERACCESS0_WRITE_WRITE 0x40000000
+#define MDIO_USERACCESS0_ACK 0x20000000
+
+#define EMAC_MACCONTROL_MIIEN_ENABLE 0x20
+#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE 0x1
+#define EMAC_MACCONTROL_GIGABIT_ENABLE BIT(7)
+#define EMAC_MACCONTROL_GIGFORCE BIT(17)
+#define EMAC_MACCONTROL_RMIISPEED_100 BIT(15)
+
+#define EMAC_MIN_ETHERNET_PKT_SIZE 60
+
+struct mac_sl_cfg {
+ u_int32_t max_rx_len; /* Maximum receive packet length. */
+ u_int32_t ctl; /* Control bitfield */
+};
+
+/**
+ * Definition: Control bitfields used in the ctl field of mac_sl_cfg
+ */
+#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES BIT(24)
+#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES BIT(23)
+#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES BIT(22)
+#define GMACSL_RX_ENABLE_EXT_CTL BIT(18)
+#define GMACSL_RX_ENABLE_GIG_FORCE BIT(17)
+#define GMACSL_RX_ENABLE_IFCTL_B BIT(16)
+#define GMACSL_RX_ENABLE_IFCTL_A BIT(15)
+#define GMACSL_RX_ENABLE_CMD_IDLE BIT(11)
+#define GMACSL_TX_ENABLE_SHORT_GAP BIT(10)
+#define GMACSL_ENABLE_GIG_MODE BIT(7)
+#define GMACSL_TX_ENABLE_PACE BIT(6)
+#define GMACSL_ENABLE BIT(5)
+#define GMACSL_TX_ENABLE_FLOW_CTL BIT(4)
+#define GMACSL_RX_ENABLE_FLOW_CTL BIT(3)
+#define GMACSL_ENABLE_LOOPBACK BIT(1)
+#define GMACSL_ENABLE_FULL_DUPLEX BIT(0)
+
+/* EMAC SL function return values */
+#define GMACSL_RET_OK 0
+#define GMACSL_RET_INVALID_PORT -1
+#define GMACSL_RET_WARN_RESET_INCOMPLETE -2
+#define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3
+#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4
+
+/* EMAC SL register definitions */
+#define DEVICE_EMACSL_RESET_POLL_COUNT 100
+
+/* Soft reset register values */
+#define CPGMAC_REG_RESET_VAL_RESET_MASK BIT(0)
+#define CPGMAC_REG_RESET_VAL_RESET BIT(0)
+#define CPGMAC_REG_MAXLEN_LEN 0x3fff
+
+/* CPSW */
+/* Control bitfields */
+#define CPSW_CTL_P2_PASS_PRI_TAGGED BIT(5)
+#define CPSW_CTL_P1_PASS_PRI_TAGGED BIT(4)
+#define CPSW_CTL_P0_PASS_PRI_TAGGED BIT(3)
+#define CPSW_CTL_P0_ENABLE BIT(2)
+#define CPSW_CTL_VLAN_AWARE BIT(1)
+#define CPSW_CTL_FIFO_LOOPBACK BIT(0)
+
+#define DEVICE_CPSW_NUM_PORTS CONFIG_KSNET_CPSW_NUM_PORTS
+#define DEVICE_N_GMACSL_PORTS (DEVICE_CPSW_NUM_PORTS - 1)
+
+#ifdef CONFIG_KSNET_NETCP_V1_0
+
+#define DEVICE_CPSW_BASE (GBETH_BASE + 0x800)
+#define CPSW_REG_CTL 0x004
+#define CPSW_REG_STAT_PORT_EN 0x00c
+#define CPSW_REG_MAXLEN 0x040
+#define CPSW_REG_ALE_CONTROL 0x608
+#define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x) * 4)
+#define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf
+
+#elif defined CONFIG_KSNET_NETCP_V1_5
+
+#define DEVICE_CPSW_BASE (GBETH_BASE + 0x20000)
+#define CPSW_REG_CTL 0x00004
+#define CPSW_REG_STAT_PORT_EN 0x00014
+#define CPSW_REG_MAXLEN 0x01024
+#define CPSW_REG_ALE_CONTROL 0x1e008
+#define CPSW_REG_ALE_PORTCTL(x) (0x1e040 + (x) * 4)
+#define CPSW_REG_VAL_STAT_ENABLE_ALL 0x1ff
+
+#endif
+
+#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000)
+#define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010)
+#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3
+
+#define target_get_switch_ctl() CPSW_CTL_P0_ENABLE
+#define SWITCH_MAX_PKT_SIZE 9000
+
+/* SGMII */
+#define SGMII_REG_STATUS_LOCK BIT(4)
+#define SGMII_REG_STATUS_LINK BIT(0)
+#define SGMII_REG_STATUS_AUTONEG BIT(2)
+#define SGMII_REG_CONTROL_AUTONEG BIT(0)
+#define SGMII_REG_CONTROL_MASTER BIT(5)
+#define SGMII_REG_MR_ADV_ENABLE BIT(0)
+#define SGMII_REG_MR_ADV_LINK BIT(15)
+#define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12)
+#define SGMII_REG_MR_ADV_GIG_MODE BIT(11)
+
+#define SGMII_LINK_MAC_MAC_AUTONEG 0
+#define SGMII_LINK_MAC_PHY 1
+#define SGMII_LINK_MAC_MAC_FORCED 2
+#define SGMII_LINK_MAC_FIBER 3
+#define SGMII_LINK_MAC_PHY_FORCED 4
+
+#ifdef CONFIG_KSNET_NETCP_V1_0
+#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
+#elif defined CONFIG_KSNET_NETCP_V1_5
+#define SGMII_OFFSET(x) ((x) * 0x100)
+#endif
+
+#define SGMII_IDVER_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000)
+#define SGMII_SRESET_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004)
+#define SGMII_CTL_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010)
+#define SGMII_STATUS_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014)
+#define SGMII_MRADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018)
+#define SGMII_LPADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020)
+#define SGMII_TXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030)
+#define SGMII_RXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034)
+#define SGMII_AUXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038)
+
+/* PSS */
+#ifdef CONFIG_KSNET_NETCP_V1_0
+
+#define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x604)
+#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x06060606
+#define hw_config_streaming_switch()\
+ writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR);
+
+#elif defined CONFIG_KSNET_NETCP_V1_5
+
+#define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x500)
+#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x0
+
+#define hw_config_streaming_switch()\
+ writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+ DEVICE_PSTREAM_CFG_REG_ADDR);\
+ writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+ DEVICE_PSTREAM_CFG_REG_ADDR+4);\
+ writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+ DEVICE_PSTREAM_CFG_REG_ADDR+8);\
+ writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+ DEVICE_PSTREAM_CFG_REG_ADDR+12);
+
+#endif
+
+/* EMAC MDIO Registers Structure */
+struct mdio_regs {
+ u32 version;
+ u32 control;
+ u32 alive;
+ u32 link;
+ u32 linkintraw;
+ u32 linkintmasked;
+ u32 rsvd0[2];
+ u32 userintraw;
+ u32 userintmasked;
+ u32 userintmaskset;
+ u32 userintmaskclear;
+ u32 rsvd1[20];
+ u32 useraccess0;
+ u32 userphysel0;
+ u32 useraccess1;
+ u32 userphysel1;
+};
+
+struct eth_priv_t {
+ char int_name[32];
+ int rx_flow;
+ int phy_addr;
+ int slave_port;
+ int sgmii_link_type;
+ struct phy_device *phy_dev;
+};
+
+int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
+void sgmii_serdes_setup_156p25mhz(void);
+void sgmii_serdes_shutdown(void);
+
+#endif /* _KEYSTONE_NET_H_ */
--- /dev/null
+/*
+ * Texas Instruments Keystone SerDes driver
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __TI_KEYSTONE_SERDES_H__
+#define __TI_KEYSTONE_SERDES_H__
+
+/* SERDES Reference clock */
+enum ks2_serdes_clock {
+ SERDES_CLOCK_100M, /* 100 MHz */
+ SERDES_CLOCK_122P88M, /* 122.88 MHz */
+ SERDES_CLOCK_125M, /* 125 MHz */
+ SERDES_CLOCK_156P25M, /* 156.25 MHz */
+ SERDES_CLOCK_312P5M, /* 312.5 MHz */
+};
+
+/* SERDES Lane Baud Rate */
+enum ks2_serdes_rate {
+ SERDES_RATE_4P9152G, /* 4.9152 GBaud */
+ SERDES_RATE_5G, /* 5 GBaud */
+ SERDES_RATE_6P144G, /* 6.144 GBaud */
+ SERDES_RATE_6P25G, /* 6.25 GBaud */
+ SERDES_RATE_10p3125g, /* 10.3215 GBaud */
+ SERDES_RATE_12p5g, /* 12.5 GBaud */
+};
+
+/* SERDES Lane Rate Mode */
+enum ks2_serdes_rate_mode {
+ SERDES_FULL_RATE,
+ SERDES_HALF_RATE,
+ SERDES_QUARTER_RATE,
+};
+
+/* SERDES PHY TYPE */
+enum ks2_serdes_interface {
+ SERDES_PHY_SGMII,
+ SERDES_PHY_PCSR, /* XGE SERDES */
+};
+
+struct ks2_serdes {
+ enum ks2_serdes_clock clk;
+ enum ks2_serdes_rate rate;
+ enum ks2_serdes_rate_mode rate_mode;
+ enum ks2_serdes_interface intf;
+ u32 loopback;
+};
+
+int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes);
+
+#endif /* __TI_KEYSTONE_SERDES_H__ */
--- /dev/null
+/*
+ * Enhanced Direct Memory Access (EDMA3) Controller
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _EDMA3_H_
+#define _EDMA3_H_
+
+#include <linux/stddef.h>
+
+#define EDMA3_PARSET_NULL_LINK 0xffff
+
+/*
+ * All parameter RAM set options
+ * opt field in edma3_param_set_config structure
+ */
+#define EDMA3_SLOPT_PRIV_LEVEL BIT(31)
+#define EDMA3_SLOPT_PRIV_ID(id) ((0xf & (id)) << 24)
+#define EDMA3_SLOPT_INTERM_COMP_CHAIN_ENB BIT(23)
+#define EDMA3_SLOPT_TRANS_COMP_CHAIN_ENB BIT(22)
+#define EDMA3_SLOPT_INTERM_COMP_INT_ENB BIT(21)
+#define EDMA3_SLOPT_TRANS_COMP_INT_ENB BIT(20)
+#define EDMA3_SLOPT_COMP_CODE(code) ((0x3f & (code)) << 12)
+#define EDMA3_SLOPT_FIFO_WIDTH_8 0
+#define EDMA3_SLOPT_FIFO_WIDTH_16 (1 << 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_32 (2 << 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_64 (3 << 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_128 (4 << 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_256 (5 << 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_SET(w) ((w & 0x7) << 8)
+#define EDMA3_SLOPT_STATIC BIT(3)
+#define EDMA3_SLOPT_AB_SYNC BIT(2)
+#define EDMA3_SLOPT_DST_ADDR_CONST_MODE BIT(1)
+#define EDMA3_SLOPT_SRC_ADDR_CONST_MODE BIT(0)
+
+enum edma3_address_mode {
+ INCR = 0,
+ FIFO = 1
+};
+
+enum edma3_fifo_width {
+ W8BIT = 0,
+ W16BIT = 1,
+ W32BIT = 2,
+ W64BIT = 3,
+ W128BIT = 4,
+ W256BIT = 5
+};
+
+enum edma3_sync_dimension {
+ ASYNC = 0,
+ ABSYNC = 1
+};
+
+/* PaRAM slots are laid out like this */
+struct edma3_slot_layout {
+ u32 opt;
+ u32 src;
+ u32 a_b_cnt;
+ u32 dst;
+ u32 src_dst_bidx;
+ u32 link_bcntrld;
+ u32 src_dst_cidx;
+ u32 ccnt;
+} __packed;
+
+/*
+ * Use this to assign trigger word number of edma3_slot_layout struct.
+ * trigger_word_name - is the exact name from edma3_slot_layout.
+ */
+#define EDMA3_TWORD(trigger_word_name)\
+ (offsetof(struct edma3_slot_layout, trigger_word_name) / 4)
+
+struct edma3_slot_config {
+ u32 opt;
+ u32 src;
+ u32 dst;
+ int bcnt;
+ int acnt;
+ int ccnt;
+ int src_bidx;
+ int dst_bidx;
+ int src_cidx;
+ int dst_cidx;
+ int bcntrld;
+ int link;
+};
+
+struct edma3_channel_config {
+ int slot;
+ int chnum;
+ int complete_code; /* indicate pending complete interrupt */
+ int trigger_slot_word; /* only used for qedma */
+};
+
+void qedma3_start(u32 base, struct edma3_channel_config *cfg);
+void qedma3_stop(u32 base, struct edma3_channel_config *cfg);
+void edma3_slot_configure(u32 base, int slot, struct edma3_slot_config *cfg);
+int edma3_check_for_transfer(u32 base, struct edma3_channel_config *cfg);
+void edma3_write_slot(u32 base, int slot, struct edma3_slot_layout *param);
+void edma3_read_slot(u32 base, int slot, struct edma3_slot_layout *param);
+
+void edma3_set_dest(u32 base, int slot, u32 dst, enum edma3_address_mode mode,
+ enum edma3_fifo_width width);
+void edma3_set_dest_index(u32 base, unsigned slot, int bidx, int cidx);
+void edma3_set_dest_addr(u32 base, int slot, u32 dst);
+
+void edma3_set_src(u32 base, int slot, u32 src, enum edma3_address_mode mode,
+ enum edma3_fifo_width width);
+void edma3_set_src_index(u32 base, unsigned slot, int bidx, int cidx);
+void edma3_set_src_addr(u32 base, int slot, u32 src);
+
+void edma3_set_transfer_params(u32 base, int slot, int acnt,
+ int bcnt, int ccnt, u16 bcnt_rld,
+ enum edma3_sync_dimension sync_mode);
+
+#endif
ulong get_timer_masked (void);
void udelay_masked (unsigned long usec);
+/* calls to c from vectors.S */
+void bad_mode(void);
+void do_undefined_instruction(struct pt_regs *pt_regs);
+void do_software_interrupt(struct pt_regs *pt_regs);
+void do_prefetch_abort(struct pt_regs *pt_regs);
+void do_data_abort(struct pt_regs *pt_regs);
+void do_not_used(struct pt_regs *pt_regs);
+#ifdef CONFIG_ARM64
+void do_fiq(struct pt_regs *pt_regs, unsigned int esr);
+void do_irq(struct pt_regs *pt_regs, unsigned int esr);
+#else
+void do_fiq(struct pt_regs *pt_regs);
+void do_irq(struct pt_regs *pt_regswq);
+#endif
+
#endif /* _U_BOOT_ARM_H_ */
#include <onenand_uboot.h>
#include <mmc.h>
#include <scsi.h>
+#include <status_led.h>
#include <libfdt.h>
#include <fdtdec.h>
#include <post.h>
************************************************************************
* May be supplied by boards if desired
*/
-inline void __coloured_LED_init(void) {}
-void coloured_LED_init(void)
- __attribute__((weak, alias("__coloured_LED_init")));
-inline void __red_led_on(void) {}
-void red_led_on(void) __attribute__((weak, alias("__red_led_on")));
-inline void __red_led_off(void) {}
-void red_led_off(void) __attribute__((weak, alias("__red_led_off")));
-inline void __green_led_on(void) {}
-void green_led_on(void) __attribute__((weak, alias("__green_led_on")));
-inline void __green_led_off(void) {}
-void green_led_off(void) __attribute__((weak, alias("__green_led_off")));
-inline void __yellow_led_on(void) {}
-void yellow_led_on(void) __attribute__((weak, alias("__yellow_led_on")));
-inline void __yellow_led_off(void) {}
-void yellow_led_off(void) __attribute__((weak, alias("__yellow_led_off")));
-inline void __blue_led_on(void) {}
-void blue_led_on(void) __attribute__((weak, alias("__blue_led_on")));
-inline void __blue_led_off(void) {}
-void blue_led_off(void) __attribute__((weak, alias("__blue_led_off")));
+__weak void coloured_LED_init(void) {}
+__weak void red_led_on(void) {}
+__weak void red_led_off(void) {}
+__weak void green_led_on(void) {}
+__weak void green_led_off(void) {}
+__weak void yellow_led_on(void) {}
+__weak void yellow_led_off(void) {}
+__weak void blue_led_on(void) {}
+__weak void blue_led_off(void) {}
/*
************************************************************************
*/
typedef int (init_fnc_t) (void);
-void __dram_init_banksize(void)
+__weak void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
}
-void dram_init_banksize(void)
- __attribute__((weak, alias("__dram_init_banksize")));
-int __arch_cpu_init(void)
+__weak int arch_cpu_init(void)
{
return 0;
}
-int arch_cpu_init(void)
- __attribute__((weak, alias("__arch_cpu_init")));
-int __power_init_board(void)
+__weak int power_init_board(void)
{
return 0;
}
-int power_init_board(void)
- __attribute__((weak, alias("__power_init_board")));
/* Record the board_init_f() bootstage (after arch_cpu_init()) */
static int mark_bootstage(void)
#include <common.h>
#include <command.h>
#include <image.h>
+#include <vxworks.h>
#include <u-boot/zlib.h>
#include <asm/byteorder.h>
#include <libfdt.h>
#include <asm/bootm.h>
#include <asm/secure.h>
#include <linux/compiler.h>
+#include <bootm.h>
+#include <vxworks.h>
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
#include <asm/armv7.h>
* DIFFERENCE: Instead of calling prep and go at the end
* they are called if subcommand is equal 0.
*/
-int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+int do_bootm_linux(int flag, int argc, char * const argv[],
+ bootm_headers_t *images)
{
/* No need for those on ARM */
if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE)
#include <common.h>
#include <asm/proc-armv/ptrace.h>
+#include <asm/u-boot-arm.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_USE_IRQ
int interrupt_init (void)
{
+ unsigned long cpsr;
+
/*
* setup up stacks if necessary
*/
IRQ_STACK_START_IN = gd->irq_sp + 8;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
+
+ __asm__ __volatile__("mrs %0, cpsr\n"
+ : "=r" (cpsr)
+ :
+ : "memory");
+
+ __asm__ __volatile__("msr cpsr_c, %0\n"
+ "mov sp, %1\n"
+ :
+ : "r" (IRQ_MODE | I_BIT | F_BIT | (cpsr & ~FIQ_MODE)),
+ "r" (IRQ_STACK_START)
+ : "memory");
+
+ __asm__ __volatile__("msr cpsr_c, %0\n"
+ "mov sp, %1\n"
+ :
+ : "r" (FIQ_MODE | I_BIT | F_BIT | (cpsr & ~IRQ_MODE)),
+ "r" (FIQ_STACK_START)
+ : "memory");
+
+ __asm__ __volatile__("msr cpsr_c, %0"
+ :
+ : "r" (cpsr)
+ : "memory");
+
return arch_interrupt_init();
}
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <asm-offsets.h>
+#include <config.h>
#include <linux/linkage.h>
/*
cmp r2, r3
blo fixloop
+ /*
+ * Relocate the exception vectors
+ */
+#ifdef CONFIG_HAS_VBAR
+ /*
+ * If the ARM processor has the security extensions,
+ * use VBAR to relocate the exception vectors.
+ */
+ ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
+ mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */
+#else
+ /*
+ * Copy the relocated exception vectors to the
+ * correct address
+ * CP15 c1 V bit gives us the location of the vectors:
+ * 0x00000000 or 0xFFFF0000.
+ */
+ ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
+ mrc p15, 0, r2, c1, c0, 0 /* V bit (bit[13]) in CP15 c1 */
+ ands r2, r2, #(1 << 13)
+ ldreq r1, =0x00000000 /* If V=0 */
+ ldrne r1, =0xFFFF0000 /* If V=1 */
+ ldmia r0!, {r2-r8,r10}
+ stmia r1!, {r2-r8,r10}
+ ldmia r0!, {r2-r8,r10}
+ stmia r1!, {r2-r8,r10}
+#endif
+
relocate_done:
#ifdef __XSCALE__
*************************************************************************
*/
- .section ".vectors", "x"
+ .section ".vectors", "ax"
/*
*************************************************************************
uint32_t *hibernate_magic = 0;
SSYNC();
+ /* cppcheck-suppress nullPointer */
if (hibernate_magic[0] == 0xDEADBEEF) {
serial_putc('c');
bfin_write_EVT15(hibernate_magic[1]);
config TARGET_MICROBLAZE_GENERIC
bool "Support microblaze-generic"
+ select SUPPORT_SPL
endchoice
config SYS_ARCH
default "mips"
+config SYS_CPU
+ default "mips32" if CPU_MIPS32_R1 || CPU_MIPS32_R2
+ default "mips64" if CPU_MIPS64_R1 || CPU_MIPS64_R2
+
config USE_PRIVATE_LIBGCC
default y
config TARGET_QEMU_MIPS
bool "Support qemu-mips"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_LITTLE_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
+ select SUPPORTS_CPU_MIPS64_R1
+ select SUPPORTS_CPU_MIPS64_R2
config TARGET_MALTA
bool "Support malta"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_LITTLE_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
config TARGET_VCT
bool "Support vct"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
config TARGET_DBAU1X00
bool "Support dbau1x00"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_LITTLE_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
config TARGET_PB1X00
bool "Support pb1x00"
+ select SUPPORTS_LITTLE_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
-config TARGET_QEMU_MIPS64
- bool "Support qemu-mips64"
endchoice
source "board/pb1x00/Kconfig"
source "board/qemu-mips/Kconfig"
+if MIPS
+
+choice
+ prompt "Endianness selection"
+ help
+ Some MIPS boards can be configured for either little or big endian
+ byte order. These modes require different U-Boot images. In general there
+ is one preferred byteorder for a particular system but some systems are
+ just as commonly used in the one or the other endianness.
+
+config SYS_BIG_ENDIAN
+ bool "Big endian"
+ depends on SUPPORTS_BIG_ENDIAN
+
+config SYS_LITTLE_ENDIAN
+ bool "Little endian"
+ depends on SUPPORTS_LITTLE_ENDIAN
+
+endchoice
+
+choice
+ prompt "CPU selection"
+ default CPU_MIPS32_R2
+
+config CPU_MIPS32_R1
+ bool "MIPS32 Release 1"
+ depends on SUPPORTS_CPU_MIPS32_R1
+ select 32BIT
+ help
+ Choose this option to build an U-Boot for release 1 or later of the
+ MIPS32 architecture.
+
+config CPU_MIPS32_R2
+ bool "MIPS32 Release 2"
+ depends on SUPPORTS_CPU_MIPS32_R2
+ select 32BIT
+ help
+ Choose this option to build an U-Boot for release 2 or later of the
+ MIPS32 architecture.
+
+config CPU_MIPS64_R1
+ bool "MIPS64 Release 1"
+ depends on SUPPORTS_CPU_MIPS64_R1
+ select 64BIT
+ help
+ Choose this option to build a kernel for release 1 or later of the
+ MIPS64 architecture.
+
+config CPU_MIPS64_R2
+ bool "MIPS64 Release 2"
+ depends on SUPPORTS_CPU_MIPS64_R2
+ select 64BIT
+ help
+ Choose this option to build a kernel for release 2 or later of the
+ MIPS64 architecture.
+
+endchoice
+
+config SUPPORTS_BIG_ENDIAN
+ bool
+
+config SUPPORTS_LITTLE_ENDIAN
+ bool
+
+config SUPPORTS_CPU_MIPS32_R1
+ bool
+
+config SUPPORTS_CPU_MIPS32_R2
+ bool
+
+config SUPPORTS_CPU_MIPS64_R1
+ bool
+
+config SUPPORTS_CPU_MIPS64_R2
+ bool
+
+config 32BIT
+ bool
+
+config 64BIT
+ bool
+
+endif
+
endmenu
# SPDX-License-Identifier: GPL-2.0+
#
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := mips_4KC-
+ifdef CONFIG_SYS_BIG_ENDIAN
+32bit-emul := elf32btsmip
+64bit-emul := elf64btsmip
+32bit-bfd := elf32-tradbigmips
+64bit-bfd := elf64-tradbigmips
+PLATFORM_CPPFLAGS += -EB
+PLATFORM_LDFLAGS += -EB
endif
-# Handle special prefix in ELDK 4.0 toolchain
-ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
-ENDIANNESS := -EL
+ifdef CONFIG_SYS_LITTLE_ENDIAN
+32bit-emul := elf32ltsmip
+64bit-emul := elf64ltsmip
+32bit-bfd := elf32-tradlittlemips
+64bit-bfd := elf64-tradlittlemips
+PLATFORM_CPPFLAGS += -EL
+PLATFORM_LDFLAGS += -EL
endif
-ifdef CONFIG_SYS_LITTLE_ENDIAN
-ENDIANNESS := -EL
+ifdef CONFIG_32BIT
+PLATFORM_CPPFLAGS += -mabi=32
+PLATFORM_LDFLAGS += -m $(32bit-emul)
+OBJCOPYFLAGS += -O $(32bit-bfd)
endif
-ifdef CONFIG_SYS_BIG_ENDIAN
-ENDIANNESS := -EB
+ifdef CONFIG_64BIT
+PLATFORM_CPPFLAGS += -mabi=64
+PLATFORM_LDFLAGS += -m$(64bit-emul)
+OBJCOPYFLAGS += -O $(64bit-bfd)
endif
-# Default to EB if no endianess is configured
-ENDIANNESS ?= -EB
+cpuflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,-mips32
+cpuflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,-mips32r2
+cpuflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64
+cpuflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2
+PLATFORM_CPPFLAGS += $(cpuflags-y)
PLATFORM_CPPFLAGS += -D__MIPS__
# On the other hand, we want PIC in the U-Boot code to relocate it from ROM
# to RAM. $28 is always used as gp.
#
-PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic $(ENDIANNESS)
+PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic
PLATFORM_CPPFLAGS += -msoft-float
-PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib $(ENDIANNESS)
+PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
LDFLAGS_FINAL += --gc-sections -pie
OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .got
-OBJCOPYFLAGS += -j .u_boot_list -j .rel.dyn
+OBJCOPYFLAGS += -j .u_boot_list -j .rel.dyn -j .padding
# SPDX-License-Identifier: GPL-2.0+
#
-#
-# Default optimization level for MIPS32
-#
-# Note: Toolchains with binutils prior to v2.16
-# are no longer supported by U-Boot MIPS tree!
-#
-PLATFORM_CPPFLAGS += -DCONFIG_MIPS32 -march=mips32r2
-PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT
-ifdef CONFIG_SYS_BIG_ENDIAN
-PLATFORM_LDFLAGS += -m elf32btsmip
-else
-PLATFORM_LDFLAGS += -m elf32ltsmip
-endif
-
CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 \
-T $(srctree)/examples/standalone/mips.lds
# SPDX-License-Identifier: GPL-2.0+
#
-#
-# Default optimization level for MIPS64
-#
-# Note: Toolchains with binutils prior to v2.16
-# are no longer supported by U-Boot MIPS tree!
-#
-PLATFORM_CPPFLAGS += -DCONFIG_MIPS64 -march=mips64
-PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT
-ifdef CONFIG_SYS_BIG_ENDIAN
-PLATFORM_LDFLAGS += -m elf64btsmip
-else
-PLATFORM_LDFLAGS += -m elf64ltsmip
-endif
-
CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 \
-T $(srctree)/examples/standalone/mips64.lds
__rel_dyn_end = .;
}
+ .padding : {
+ /*
+ * Workaround for a binutils feature (or bug?).
+ *
+ * The GNU ld from binutils puts the dynamic relocation
+ * entries into the .rel.dyn section. Sometimes it
+ * allocates more dynamic relocation entries than it needs
+ * and the unused slots are set to R_MIPS_NONE entries.
+ *
+ * However the size of the .rel.dyn section in the ELF
+ * section header does not cover the unused entries, so
+ * objcopy removes those during stripping.
+ *
+ * Create a small section here to avoid that.
+ */
+ LONG(0xFFFFFFFF)
+ }
+
_end = .;
.bss __rel_dyn_start (OVERLAY) : {
config TARGET_ELPPC
bool "Support ELPPC"
-config TARGET_CPCI750
- bool "Support CPCI750"
-
config TARGET_MPC7448HPC2
bool "Support mpc7448hpc2"
-config TARGET_DB64360
- bool "Support DB64360"
-
-config TARGET_DB64460
- bool "Support DB64460"
-
-config TARGET_P3MX
- bool "Support p3mx"
-
endchoice
-source "board/Marvell/db64360/Kconfig"
-source "board/Marvell/db64460/Kconfig"
source "board/eltec/elppc/Kconfig"
-source "board/esd/cpci750/Kconfig"
source "board/evb64260/Kconfig"
source "board/freescale/mpc7448hpc2/Kconfig"
source "board/ppmc7xx/Kconfig"
-source "board/prodrive/p3mx/Kconfig"
endmenu
#include <asm/mmu.h>
#include <asm/u-boot.h>
-#if !defined(CONFIG_DB64360) && \
- !defined(CONFIG_DB64460) && \
- !defined(CONFIG_CPCI750) && \
- !defined(CONFIG_P3Mx)
-#include <galileo/gt64260R.h>
-#endif
-
/* We don't want the MMU yet.
*/
#undef MSR_KERNEL
bne 5b
6:
mr r3, r10 /* Destination Address */
-#if defined(CONFIG_DB64360) || \
- defined(CONFIG_DB64460) || \
- defined(CONFIG_CPCI750) || \
- defined(CONFIG_PPMC7XX) || \
- defined(CONFIG_P3Mx)
+#if defined(CONFIG_PPMC7XX)
mr r4, r9 /* Use RAM copy of the global data */
#endif
bl after_reloc
config TARGET_A3M071
bool "Support a3m071"
+ select SUPPORT_SPL
config TARGET_A4M072
bool "Support a4m072"
config TARGET_V38B
bool "Support v38b"
-config TARGET_TOP5200
- bool "Support TOP5200"
-
config TARGET_CPCI5200
bool "Support cpci5200"
source "board/bc3450/Kconfig"
source "board/canmb/Kconfig"
source "board/cm5200/Kconfig"
-source "board/emk/top5200/Kconfig"
source "board/esd/cpci5200/Kconfig"
source "board/esd/mecp5200/Kconfig"
source "board/esd/pf5200/Kconfig"
config TARGET_GW8260
bool "Support gw8260"
-config TARGET_HYMOD
- bool "Support hymod"
-
config TARGET_IPHASE4539
bool "Support IPHASE4539"
config TARGET_VOVPN_GW
bool "Support VoVPN-GW"
-config TARGET_IDS8247
- bool "Support IDS8247"
-
config TARGET_KM82XX
bool "Support km82xx"
-config TARGET_TQM8260
- bool "Support TQM8260"
-
-config TARGET_TQM8272
- bool "Support TQM8272"
-
endchoice
source "board/atc/Kconfig"
source "board/freescale/mpc8266ads/Kconfig"
source "board/funkwerk/vovpn-gw/Kconfig"
source "board/gw8260/Kconfig"
-source "board/hymod/Kconfig"
-source "board/ids/ids8247/Kconfig"
source "board/iphase4539/Kconfig"
source "board/keymile/km82xx/Kconfig"
source "board/muas3001/Kconfig"
source "board/pm828/Kconfig"
source "board/ppmc8260/Kconfig"
source "board/sacsng/Kconfig"
-source "board/tqc/tqm8260/Kconfig"
-source "board/tqc/tqm8272/Kconfig"
endmenu
/* 28.9 - (1-2): ioports have been set up already */
-#if defined(CONFIG_HYMOD)
- /*
- * Attention: this is board-specific
- * 0, FCC1
- * 1, FCC2
- * 2, FCC3
- */
-# define FCC_START_LOOP 0
-# define FCC_END_LOOP 2
-
- /*
- * Attention: this is board-specific
- * - FCC1 Rx-CLK is CLK10
- * - FCC1 Tx-CLK is CLK11
- * - FCC2 Rx-CLK is CLK13
- * - FCC2 Tx-CLK is CLK14
- * - FCC3 Rx-CLK is CLK15
- * - FCC3 Tx-CLK is CLK16
- */
-
- /* 28.9 - (3): connect FCC's tx and rx clocks */
- immr->im_cpmux.cmx_uar = 0;
- immr->im_cpmux.cmx_fcr = CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11|\
- CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14|\
- CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16;
-#elif defined(CONFIG_SACSng)
+#if defined(CONFIG_SACSng)
/*
* Attention: this is board-specific
* 1, FCC2
immr->im_intctl.ic_sipnrh = 0xffffffff;
immr->im_intctl.ic_sipnrl = 0xffffffff;
-#ifdef CONFIG_HYMOD
- /*
- * ensure all external interrupt sources default to trigger on
- * high-to-low transition (i.e. edge triggered active low)
- */
- immr->im_intctl.ic_siexr = -1;
-#endif
-
- return (0);
+ return 0;
}
/****************************************************************************/
| SIUMCR_CS10PC00
| SIUMCR_BCTLC00
| SIUMCR_MMR11;
-#elif defined(CONFIG_TQM8272)
-/* nothing to do for this Board here */
#else
/*
* Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
GOT_ENTRY(__init_end)
GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
-#if defined(CONFIG_HYMOD)
- GOT_ENTRY(environment)
-#endif
END_GOT
/*
* Now clear BSS segment
*/
lwz r3,GOT(__bss_start)
-#if defined(CONFIG_HYMOD)
- /*
- * For HYMOD - the environment is the very last item in flash.
- * The real .bss stops just before environment starts, so only
- * clear up to that point.
- *
- * taken from mods for FADS board
- */
- lwz r4,GOT(environment)
-#else
lwz r4,GOT(__bss_end)
-#endif
cmplw 0, r3, r4
beq 6f
config TARGET_MPC8313ERDB
bool "Support MPC8313ERDB"
+ select SUPPORT_SPL
config TARGET_MPC8315ERDB
bool "Support MPC8315ERDB"
* Now clear BSS segment
*/
lwz r3,GOT(__bss_start)
-#if defined(CONFIG_HYMOD)
- /*
- * For HYMOD - the environment is the very last item in flash.
- * The real .bss stops just before environment starts, so only
- * clear up to that point.
- *
- * taken from mods for FADS board
- */
- lwz r4,GOT(environment)
-#else
lwz r4,GOT(__bss_end)
-#endif
cmplw 0, r3, r4
beq 6f
config TARGET_SOCRATES
bool "Support socrates"
-config TARGET_HWW1U1A
- bool "Support HWW1U1A"
-
config TARGET_B4860QDS
bool "Support B4860QDS"
+ select SUPPORT_SPL
config TARGET_BSC9131RDB
bool "Support BSC9131RDB"
+ select SUPPORT_SPL
config TARGET_BSC9132QDS
bool "Support BSC9132QDS"
+ select SUPPORT_SPL
config TARGET_C29XPCIE
bool "Support C29XPCIE"
+ select SUPPORT_SPL
+ select SUPPORT_TPL
config TARGET_P3041DS
bool "Support P3041DS"
config TARGET_P1010RDB
bool "Support P1010RDB"
+ select SUPPORT_SPL
+ select SUPPORT_TPL
config TARGET_P1022DS
bool "Support P1022DS"
+ select SUPPORT_SPL
+ select SUPPORT_TPL
config TARGET_P1023RDB
bool "Support P1023RDB"
config TARGET_P1_P2_RDB
bool "Support P1_P2_RDB"
+ select SUPPORT_SPL
+ select SUPPORT_TPL
config TARGET_P1_P2_RDB_PC
bool "Support p1_p2_rdb_pc"
+ select SUPPORT_SPL
+ select SUPPORT_TPL
config TARGET_P1_TWR
bool "Support p1_twr"
config TARGET_T104XRDB
bool "Support T104xRDB"
+ select SUPPORT_SPL
config TARGET_T208XQDS
bool "Support T208xQDS"
+ select SUPPORT_SPL
config TARGET_T208XRDB
bool "Support T208xRDB"
+ select SUPPORT_SPL
config TARGET_T4240EMU
bool "Support T4240EMU"
config TARGET_T4240QDS
bool "Support T4240QDS"
+ select SUPPORT_SPL
config TARGET_T4240RDB
bool "Support T4240RDB"
endchoice
-source "board/exmeritus/hww1u1a/Kconfig"
source "board/freescale/b4860qds/Kconfig"
source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"
setup_ifc_sram = (void *)SRAM_BASE_ADDR;
dst = (u32 *) SRAM_BASE_ADDR;
src = (u32 *) setup_ifc;
- for (i = 0; i < 1024; i++)
+ for (i = 0; i < 1024; i++) {
+ /* cppcheck-suppress nullPointer */
*dst++ = *src++;
+ }
+ /* cppcheck-suppress nullPointer */
setup_ifc_sram();
/* CLEANUP */
config TARGET_HERMES
bool "Support hermes"
-config TARGET_ICU862
- bool "Support ICU862"
-
config TARGET_IP860
bool "Support IP860"
config TARGET_SPD823TS
bool "Support SPD823TS"
-config TARGET_MHPC
- bool "Support MHPC"
-
-config TARGET_TOP860
- bool "Support TOP860"
-
config TARGET_KUP4K
bool "Support KUP4K"
source "board/LEOX/elpt860/Kconfig"
source "board/RRvision/Kconfig"
source "board/cogent/Kconfig"
-source "board/eltec/mhpc/Kconfig"
-source "board/emk/top860/Kconfig"
source "board/esteem192e/Kconfig"
source "board/hermes/Kconfig"
-source "board/icu862/Kconfig"
source "board/ip860/Kconfig"
source "board/ivm/Kconfig"
source "board/kup/kup4k/Kconfig"
*/
#if defined(CONFIG_HERMES) || \
- defined(CONFIG_ICU862) || \
defined(CONFIG_IP860) || \
defined(CONFIG_IVML24) || \
defined(CONFIG_IVMS8) || \
defined(CONFIG_LWMON) || \
- defined(CONFIG_MHPC) || \
defined(CONFIG_R360MPI) || \
defined(CONFIG_RMU) || \
defined(CONFIG_SPD823TS)
j = 0;
while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
-#if defined(CONFIG_ICU862)
- udelay(10);
-#else
udelay(1);
-#endif
j++;
}
if (j>=TOUT_LOOP) {
#endif /* !CONFIG_RMII */
-#elif !defined(CONFIG_ICU862)
+#else
/*
* Configure all of port D for MII.
*/
immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
else
immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
-#else
- /*
- * Configure port A for MII.
- */
-
-#if defined(CONFIG_ICU862) && defined(CONFIG_SYS_DISCOVER_PHY)
-
- /*
- * On the ICU862 board the MII-MDC pin is routed to PD8 pin
- * * of CPU, so for this board we need to configure Utopia and
- * * enable PD8 to MII-MDC function
- */
- immr->im_ioport.iop_pdpar |= 0x4080;
#endif
- /*
- * Has Utopia been configured?
- */
- if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) {
- /*
- * YES - Use MUXED mode for UTOPIA bus.
- * This frees Port A for use by MII (see 862UM table 41-6).
- */
- immr->im_ioport.utmode &= ~0x80;
- } else {
- /*
- * NO - set SPLIT mode for UTOPIA bus.
- *
- * This doesn't really effect UTOPIA (which isn't
- * enabled anyway) but just tells the 862
- * to use port A for MII (see 862UM table 41-6).
- */
- immr->im_ioport.utmode |= 0x80;
- }
-#endif /* !defined(CONFIG_ICU862) */
-
#endif /* CONFIG_ETHER_ON_FEC1 */
} else if (fecidx == 1) {
config TARGET_LWMON5
bool "Support lwmon5"
+ select SUPPORT_SPL
config TARGET_PCS440EP
bool "Support pcs440ep"
#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+
+ /* Clear initial global data */
+ memset((void *)gd, 0, sizeof(gd_t));
}
/*
u8 res2[0x28];
law512x_t ddrlaw; /* DDR Local Access Window */
u8 res3[0x18];
+ u32 mbxbar; /* MBX Base Address */
u32 srambar; /* SRAM Base Address */
u32 nfcbar; /* NFC Base Address */
u8 res4[0x34];
unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
#endif
-#if defined(CONFIG_HYMOD)
- hymod_conf_t bi_hymod_conf; /* hymod configuration information */
-#endif
#ifdef CONFIG_HAS_ETH1
unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */
#include <common.h>
#include <os.h>
+#include <cli.h>
#include <asm/getopt.h>
#include <asm/io.h>
#include <asm/sections.h>
/* Execute command if required */
if (state->cmd) {
+ cli_init();
+
run_command_list(state->cmd, -1, 0);
if (!state->interactive)
os_exit(state->exit_type);
typedef signed int s32;
typedef unsigned int u32;
+#if !defined(CONFIG_USE_STDINT) || !defined(__INT64_TYPE__)
typedef signed long long s64;
typedef unsigned long long u64;
+#else
+typedef __INT64_TYPE__ s64;
+typedef __UINT64_TYPE__ u64;
+#endif
#define BITS_PER_LONG CONFIG_SANDBOX_BITS_PER_LONG
bootargs = getenv("bootargs");
/* Clear zero page */
+ /* cppcheck-suppress nullPointer */
memset(param, 0, 0x1000);
/* Set commandline */
menu "SPARC architecture"
depends on SPARC
-config SYS_ARCH
- default "sparc"
+config LEON
+ bool
+
+config LEON2
+ bool
+ select LEON
+
+config LEON3
+ bool
+ select LEON
choice
- prompt "Target select"
+ prompt "Board select"
config TARGET_GRSIM_LEON2
- bool "Support grsim_leon2"
+ bool "GRSIM simulating a LEON2 board"
+ select LEON2
config TARGET_GR_CPCI_AX2000
- bool "Support gr_cpci_ax2000"
+ bool "Gaisler GR-CPCI-AX2000 board"
+ select LEON3
config TARGET_GR_EP2S60
- bool "Support gr_ep2s60"
+ bool "Gaisler Template design for Altera NIOS board with Stratix EP2S60"
+ select LEON3
+ help
+ Gaisler Research AB's Template design (GPL Open Source SPARC/LEON3
+ 96MHz) for Altera NIOS Development board Stratix II edition,
+ with the FPGA device EP2S60.
config TARGET_GR_XC3S_1500
- bool "Support gr_xc3s_1500"
+ bool "Gaisler GR-XC3S-1500 spartan board"
+ select LEON3
config TARGET_GRSIM
- bool "Support grsim"
+ bool "GRSIM simulating a LEON3 GR-XC3S-1500 board"
+ select LEON3
endchoice
+config SYS_ARCH
+ default "sparc"
+
+config SYS_CPU
+ default "leon2" if LEON2
+ default "leon3" if LEON3
+
+config SYS_VENDOR
+ default "gaisler"
+
source "board/gaisler/gr_cpci_ax2000/Kconfig"
source "board/gaisler/gr_ep2s60/Kconfig"
source "board/gaisler/gr_xc3s_1500/Kconfig"
-T $(srctree)/examples/standalone/sparc.lds
PLATFORM_CPPFLAGS += -D__sparc__
+
+PLATFORM_RELFLAGS += -fPIC
+++ /dev/null
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_RELFLAGS += -fPIC
-
-PLATFORM_CPPFLAGS += -DCONFIG_LEON -DCONFIG_LEON2
+++ /dev/null
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_RELFLAGS += -fPIC
-
-PLATFORM_CPPFLAGS += -DCONFIG_LEON -DCONFIG_LEON3
extra-y = start.o
obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
-obj-y += interrupts.o cpu.o
+obj-y += interrupts.o cpu.o call64.o
--- /dev/null
+/*
+ * (C) Copyright 2014 Google, Inc
+ * Copyright (C) 1991, 1992, 1993 Linus Torvalds
+ *
+ * Parts of this copied from Linux arch/x86/boot/compressed/head_64.S
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/global_data.h>
+#include <asm/msr-index.h>
+#include <asm/processor-flags.h>
+
+.code32
+.globl cpu_call64
+cpu_call64:
+ /*
+ * cpu_call64(ulong pgtable, ulong setup_base, ulong target)
+ *
+ * eax - pgtable
+ * edx - setup_base
+ * ecx - target
+ */
+ cli
+ push %ecx /* arg2 = target */
+ push %edx /* arg1 = setup_base */
+ mov %eax, %ebx
+
+ /* Load new GDT with the 64bit segments using 32bit descriptor */
+ leal gdt, %eax
+ movl %eax, gdt+2
+ lgdt gdt
+
+ /* Enable PAE mode */
+ movl $(X86_CR4_PAE), %eax
+ movl %eax, %cr4
+
+ /* Enable the boot page tables */
+ leal (%ebx), %eax
+ movl %eax, %cr3
+
+ /* Enable Long mode in EFER (Extended Feature Enable Register) */
+ movl $MSR_EFER, %ecx
+ rdmsr
+ btsl $_EFER_LME, %eax
+ wrmsr
+
+ /* After gdt is loaded */
+ xorl %eax, %eax
+ lldt %ax
+ movl $0x20, %eax
+ ltr %ax
+
+ /*
+ * Setup for the jump to 64bit mode
+ *
+ * When the jump is performed we will be in long mode but
+ * in 32bit compatibility mode with EFER.LME = 1, CS.L = 0, CS.D = 1
+ * (and in turn EFER.LMA = 1). To jump into 64bit mode we use
+ * the new gdt/idt that has __KERNEL_CS with CS.L = 1.
+ * We place all of the values on our mini stack so lret can
+ * used to perform that far jump. See the gdt below.
+ */
+ pop %esi /* setup_base */
+
+ pushl $0x10
+ leal lret_target, %eax
+ pushl %eax
+
+ /* Enter paged protected Mode, activating Long Mode */
+ movl $(X86_CR0_PG | X86_CR0_PE), %eax
+ movl %eax, %cr0
+
+ /* Jump from 32bit compatibility mode into 64bit mode. */
+ lret
+
+code64:
+lret_target:
+ pop %eax /* target */
+ mov %eax, %eax /* Clear bits 63:32 */
+ jmp *%eax /* Jump to the 64-bit target */
+
+ .data
+gdt:
+ .word gdt_end - gdt
+ .long gdt
+ .word 0
+ .quad 0x0000000000000000 /* NULL descriptor */
+ .quad 0x00af9a000000ffff /* __KERNEL_CS */
+ .quad 0x00cf92000000ffff /* __KERNEL_DS */
+ .quad 0x0080890000000000 /* TS descriptor */
+ .quad 0x0000000000000000 /* TS continued */
+gdt_end:
#include <common.h>
#include <command.h>
+#include <errno.h>
+#include <malloc.h>
#include <asm/control_regs.h>
+#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/processor-flags.h>
#include <asm/interrupt.h>
{
return 1;
}
+
+void cpu_enable_paging_pae(ulong cr3)
+{
+ __asm__ __volatile__(
+ /* Load the page table address */
+ "movl %0, %%cr3\n"
+ /* Enable pae */
+ "movl %%cr4, %%eax\n"
+ "orl $0x00000020, %%eax\n"
+ "movl %%eax, %%cr4\n"
+ /* Enable paging */
+ "movl %%cr0, %%eax\n"
+ "orl $0x80000000, %%eax\n"
+ "movl %%eax, %%cr0\n"
+ :
+ : "r" (cr3)
+ : "eax");
+}
+
+void cpu_disable_paging_pae(void)
+{
+ /* Turn off paging */
+ __asm__ __volatile__ (
+ /* Disable paging */
+ "movl %%cr0, %%eax\n"
+ "andl $0x7fffffff, %%eax\n"
+ "movl %%eax, %%cr0\n"
+ /* Disable pae */
+ "movl %%cr4, %%eax\n"
+ "andl $0xffffffdf, %%eax\n"
+ "movl %%eax, %%cr4\n"
+ :
+ :
+ : "eax");
+}
+
+static bool has_cpuid(void)
+{
+ unsigned long flag;
+
+ asm volatile("pushf\n" \
+ "pop %%eax\n"
+ "mov %%eax, %%ecx\n" /* ecx = flags */
+ "xor %1, %%eax\n"
+ "push %%eax\n"
+ "popf\n" /* flags ^= $2 */
+ "pushf\n"
+ "pop %%eax\n" /* eax = flags */
+ "push %%ecx\n"
+ "popf\n" /* flags = ecx */
+ "xor %%ecx, %%eax\n"
+ "mov %%eax, %0"
+ : "=r" (flag)
+ : "i" (1 << 21)
+ : "eax", "ecx", "memory");
+
+ return flag != 0;
+}
+
+static bool can_detect_long_mode(void)
+{
+ unsigned long flag;
+
+ asm volatile("mov $0x80000000, %%eax\n"
+ "cpuid\n"
+ "mov %%eax, %0"
+ : "=r" (flag)
+ :
+ : "eax", "ebx", "ecx", "edx", "memory");
+
+ return flag > 0x80000000UL;
+}
+
+static bool has_long_mode(void)
+{
+ unsigned long flag;
+
+ asm volatile("mov $0x80000001, %%eax\n"
+ "cpuid\n"
+ "mov %%edx, %0"
+ : "=r" (flag)
+ :
+ : "eax", "ebx", "ecx", "edx", "memory");
+
+ return flag & (1 << 29) ? true : false;
+}
+
+int cpu_has_64bit(void)
+{
+ return has_cpuid() && can_detect_long_mode() &&
+ has_long_mode();
+}
+
+int print_cpuinfo(void)
+{
+ printf("CPU: %s\n", cpu_has_64bit() ? "x86_64" : "x86");
+
+ return 0;
+}
+
+#define PAGETABLE_SIZE (6 * 4096)
+
+/**
+ * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
+ *
+ * @pgtable: Pointer to a 24iKB block of memory
+ */
+static void build_pagetable(uint32_t *pgtable)
+{
+ uint i;
+
+ memset(pgtable, '\0', PAGETABLE_SIZE);
+
+ /* Level 4 needs a single entry */
+ pgtable[0] = (uint32_t)&pgtable[1024] + 7;
+
+ /* Level 3 has one 64-bit entry for each GiB of memory */
+ for (i = 0; i < 4; i++) {
+ pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] +
+ 0x1000 * i + 7;
+ }
+
+ /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
+ for (i = 0; i < 2048; i++)
+ pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
+}
+
+int cpu_jump_to_64bit(ulong setup_base, ulong target)
+{
+ uint32_t *pgtable;
+
+ pgtable = memalign(4096, PAGETABLE_SIZE);
+ if (!pgtable)
+ return -ENOMEM;
+
+ build_pagetable(pgtable);
+ cpu_call64((ulong)pgtable, setup_base, target);
+ free(pgtable);
+
+ return -EFAULT;
+}
/* Align global data to 16-byte boundary */
andl $0xfffffff0, %esp
+ /* Zero the global data since it won't happen later */
+ xorl %eax, %eax
+ movl $GENERATED_GBL_DATA_SIZE, %ecx
+ movl %esp, %edi
+ rep stosb
+
/* Setup first parameter to setup_gdt */
movl %esp, %eax
/* Reserve space for global descriptor table */
subl $X86_GDT_SIZE, %esp
+#if defined(CONFIG_SYS_MALLOC_F_LEN)
+ subl $CONFIG_SYS_MALLOC_F_LEN, %esp
+ movl %eax, %edx
+ addl $GD_MALLOC_BASE, %edx
+ movl %esp, (%edx)
+#endif
+
/* Align temporary global descriptor table to 16-byte boundary */
andl $0xfffffff0, %esp
/include/ "skeleton.dtsi"
/ {
- aliases {
- console = "/serial";
+ chosen {
+ stdout-path = "/serial";
};
serial {
- compatible = "ns16550";
- reg-shift = <1>;
+ compatible = "coreboot-uart";
+ reg = <0x3f8 0x10>;
+ reg-shift = <0>;
io-mapped = <1>;
multiplier = <1>;
baudrate = <115200>;
silent_console = <0>;
};
- gpio: gpio {};
+ gpioa {
+ compatible = "intel,ich6-gpio";
+ reg = <0 0x10>;
+ bank-name = "A";
+ };
+
+ gpiob {
+ compatible = "intel,ich6-gpio";
+ reg = <0x30 0x10>;
+ bank-name = "B";
+ };
+
+ gpioc {
+ compatible = "intel,ich6-gpio";
+ reg = <0x40 0x10>;
+ bank-name = "C";
+ };
serial {
reg = <0x3f8 8>;
--- /dev/null
+/*
+ * Copyright (c) 2014, Google Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _X86_ARCH_GPIO_H_
+#define _X86_ARCH_GPIO_H_
+
+struct ich6_bank_platdata {
+ uint32_t base_addr;
+ const char *bank_name;
+};
+
+#endif /* _X86_ARCH_GPIO_H_ */
void bootm_announce_and_cleanup(void);
+/**
+ * boot_linux_kernel() - boot a linux kernel
+ *
+ * This boots a kernel image, either 32-bit or 64-bit. It will also work with
+ * a self-extracting kernel, if you set @image_64bit to false.
+ *
+ * @setup_base: Pointer to the setup.bin information for the kernel
+ * @load_address: Pointer to the start of the kernel image
+ * @image_64bit: true if the image is a raw 64-bit kernel, false if it
+ * is raw 32-bit or any type of self-extracting kernel
+ * such as a bzImage.
+ * @return -ve error code. This function does not return if the kernel was
+ * booted successfully.
+ */
+int boot_linux_kernel(ulong setup_base, ulong load_address, bool image_64bit);
+
#endif
--- /dev/null
+/*
+ * Copyright (c) 2014 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __X86_CPU_H
+#define __X86_CPU_H
+
+ /**
+ * cpu_enable_paging_pae() - Enable PAE-paging
+ *
+ * @pdpt: Value to set in cr3 (PDPT or PML4T)
+ */
+void cpu_enable_paging_pae(ulong cr3);
+
+/**
+ * cpu_disable_paging_pae() - Disable paging and PAE
+ */
+void cpu_disable_paging_pae(void);
+
+/**
+ * cpu_has_64bit() - Check if the CPU has 64-bit support
+ *
+ * @return 1 if this CPU supports long mode (64-bit), 0 if not
+ */
+int cpu_has_64bit(void);
+
+/**
+ * cpu_call64() - Jump to a 64-bit Linux kernel (internal function)
+ *
+ * The kernel is uncompressed and the 64-bit entry point is expected to be
+ * at @target.
+ *
+ * This function is used internally - see cpu_jump_to_64bit() for a more
+ * useful function.
+ *
+ * @pgtable: Address of 24KB area containing the page table
+ * @setup_base: Pointer to the setup.bin information for the kernel
+ * @target: Pointer to the start of the kernel image
+ */
+void cpu_call64(ulong pgtable, ulong setup_base, ulong target);
+
+/**
+ * cpu_jump_to_64bit() - Jump to a 64-bit Linux kernel
+ *
+ * The kernel is uncompressed and the 64-bit entry point is expected to be
+ * at @target.
+ *
+ * @setup_base: Pointer to the setup.bin information for the kernel
+ * @target: Pointer to the start of the kernel image
+ */
+int cpu_jump_to_64bit(ulong setup_base, ulong target);
+
+#endif
#ifndef _X86_GPIO_H_
#define _X86_GPIO_H_
+#include <asm/arch/gpio.h>
#include <asm-generic/gpio.h>
#endif /* _X86_GPIO_H_ */
#define SYSCTLA 0x92
#define SLAVE_PIC 0xa0
-#if 1
-#define UART0_BASE 0x3f8
-#define UART1_BASE 0x2f8
-#else
-/* FixMe: uarts swapped */
-#define UART0_BASE 0x2f8
-#define UART1_BASE 0x3f8
-#endif
-
-
#endif
#define MSR_IA32_PERFCTR0 0x000000c1
#define MSR_IA32_PERFCTR1 0x000000c2
#define MSR_FSB_FREQ 0x000000cd
+#define MSR_NHM_PLATFORM_INFO 0x000000ce
#define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
#define NHM_C3_AUTO_DEMOTE (1UL << 25)
#define NHM_C1_AUTO_DEMOTE (1UL << 26)
#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
+#define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
+#define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
+#define MSR_PLATFORM_INFO 0x000000ce
#define MSR_MTRRcap 0x000000fe
#define MSR_IA32_BBL_CR_CTL 0x00000119
#define MSR_IA32_BBL_CR_CTL3 0x0000011e
#define MSR_OFFCORE_RSP_0 0x000001a6
#define MSR_OFFCORE_RSP_1 0x000001a7
+#define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad
+#define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae
+
+#define MSR_LBR_SELECT 0x000001c8
+#define MSR_LBR_TOS 0x000001c9
+#define MSR_LBR_NHM_FROM 0x00000680
+#define MSR_LBR_NHM_TO 0x000006c0
+#define MSR_LBR_CORE_FROM 0x00000040
+#define MSR_LBR_CORE_TO 0x00000060
#define MSR_IA32_PEBS_ENABLE 0x000003f1
#define MSR_IA32_DS_AREA 0x00000600
#define MSR_IA32_PERF_CAPABILITIES 0x00000345
+#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
#define MSR_MTRRfix64K_00000 0x00000250
#define MSR_MTRRfix16K_80000 0x00000258
#define MSR_IA32_LASTINTTOIP 0x000001de
/* DEBUGCTLMSR bits (others vary by model): */
-#define DEBUGCTLMSR_LBR (1UL << 0)
+#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
+/* single-step on branches */
#define DEBUGCTLMSR_BTF (1UL << 1)
#define DEBUGCTLMSR_TR (1UL << 6)
#define DEBUGCTLMSR_BTS (1UL << 7)
#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
+#define MSR_IA32_POWER_CTL 0x000001fc
+
#define MSR_IA32_MC0_CTL 0x00000400
#define MSR_IA32_MC0_STATUS 0x00000401
#define MSR_IA32_MC0_ADDR 0x00000402
#define MSR_IA32_MC0_MISC 0x00000403
+/* C-state Residency Counters */
+#define MSR_PKG_C3_RESIDENCY 0x000003f8
+#define MSR_PKG_C6_RESIDENCY 0x000003f9
+#define MSR_PKG_C7_RESIDENCY 0x000003fa
+#define MSR_CORE_C3_RESIDENCY 0x000003fc
+#define MSR_CORE_C6_RESIDENCY 0x000003fd
+#define MSR_CORE_C7_RESIDENCY 0x000003fe
+#define MSR_PKG_C2_RESIDENCY 0x0000060d
+#define MSR_PKG_C8_RESIDENCY 0x00000630
+#define MSR_PKG_C9_RESIDENCY 0x00000631
+#define MSR_PKG_C10_RESIDENCY 0x00000632
+
+/* Run Time Average Power Limiting (RAPL) Interface */
+
+#define MSR_RAPL_POWER_UNIT 0x00000606
+
+#define MSR_PKG_POWER_LIMIT 0x00000610
+#define MSR_PKG_ENERGY_STATUS 0x00000611
+#define MSR_PKG_PERF_STATUS 0x00000613
+#define MSR_PKG_POWER_INFO 0x00000614
+
+#define MSR_DRAM_POWER_LIMIT 0x00000618
+#define MSR_DRAM_ENERGY_STATUS 0x00000619
+#define MSR_DRAM_PERF_STATUS 0x0000061b
+#define MSR_DRAM_POWER_INFO 0x0000061c
+
+#define MSR_PP0_POWER_LIMIT 0x00000638
+#define MSR_PP0_ENERGY_STATUS 0x00000639
+#define MSR_PP0_POLICY 0x0000063a
+#define MSR_PP0_PERF_STATUS 0x0000063b
+
+#define MSR_PP1_POWER_LIMIT 0x00000640
+#define MSR_PP1_ENERGY_STATUS 0x00000641
+#define MSR_PP1_POLICY 0x00000642
+
+#define MSR_CORE_C1_RES 0x00000660
+
#define MSR_AMD64_MC0_MASK 0xc0010044
#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
#define MSR_P6_EVNTSEL0 0x00000186
#define MSR_P6_EVNTSEL1 0x00000187
+#define MSR_KNC_PERFCTR0 0x00000020
+#define MSR_KNC_PERFCTR1 0x00000021
+#define MSR_KNC_EVNTSEL0 0x00000028
+#define MSR_KNC_EVNTSEL1 0x00000029
+
+/* Alternative perfctr range with full access. */
+#define MSR_IA32_PMC0 0x000004c1
+
/* AMD64 MSRs. Not complete. See the architecture manual for a more
complete list. */
#define MSR_AMD64_PATCH_LEVEL 0x0000008b
+#define MSR_AMD64_TSC_RATIO 0xc0000104
#define MSR_AMD64_NB_CFG 0xc001001f
#define MSR_AMD64_PATCH_LOADER 0xc0010020
#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
#define MSR_AMD64_OSVW_STATUS 0xc0010141
+#define MSR_AMD64_LS_CFG 0xc0011020
#define MSR_AMD64_DC_CFG 0xc0011022
+#define MSR_AMD64_BU_CFG2 0xc001102a
#define MSR_AMD64_IBSFETCHCTL 0xc0011030
#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
+#define MSR_AMD64_IBSFETCH_REG_COUNT 3
+#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
#define MSR_AMD64_IBSOPCTL 0xc0011033
#define MSR_AMD64_IBSOPRIP 0xc0011034
#define MSR_AMD64_IBSOPDATA 0xc0011035
#define MSR_AMD64_IBSOPDATA3 0xc0011037
#define MSR_AMD64_IBSDCLINAD 0xc0011038
#define MSR_AMD64_IBSDCPHYSAD 0xc0011039
+#define MSR_AMD64_IBSOP_REG_COUNT 7
+#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
#define MSR_AMD64_IBSCTL 0xc001103a
#define MSR_AMD64_IBSBRTARGET 0xc001103b
+#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
+
+/* Fam 16h MSRs */
+#define MSR_F16H_L2I_PERF_CTL 0xc0010230
+#define MSR_F16H_L2I_PERF_CTR 0xc0010231
/* Fam 15h MSRs */
#define MSR_F15H_PERF_CTL 0xc0010200
#define MSR_F15H_PERF_CTR 0xc0010201
+#define MSR_F15H_NB_PERF_CTL 0xc0010240
+#define MSR_F15H_NB_PERF_CTR 0xc0010241
/* Fam 10h MSRs */
#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
#define MSR_IA32_PLATFORM_ID 0x00000017
#define MSR_IA32_EBL_CR_POWERON 0x0000002a
#define MSR_EBC_FREQUENCY_ID 0x0000002c
+#define MSR_SMI_COUNT 0x00000034
#define MSR_IA32_FEATURE_CONTROL 0x0000003a
+#define MSR_IA32_TSC_ADJUST 0x0000003b
#define FEATURE_CONTROL_LOCKED (1<<0)
#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
#define MSR_IA32_APICBASE_ENABLE (1<<11)
#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
+#define MSR_IA32_TSCDEADLINE 0x000006e0
+
#define MSR_IA32_UCODE_WRITE 0x00000079
#define MSR_IA32_UCODE_REV 0x0000008b
#define MSR_IA32_PERF_STATUS 0x00000198
#define MSR_IA32_PERF_CTL 0x00000199
+#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
+#define MSR_AMD_PERF_STATUS 0xc0010063
+#define MSR_AMD_PERF_CTL 0xc0010062
#define MSR_IA32_MPERF 0x000000e7
#define MSR_IA32_APERF 0x000000e8
#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
+#define ENERGY_PERF_BIAS_PERFORMANCE 0
+#define ENERGY_PERF_BIAS_NORMAL 6
+#define ENERGY_PERF_BIAS_POWERSAVE 15
#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38)
#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39)
+#define MSR_IA32_TSC_DEADLINE 0x000006E0
+
/* P4/Xeon+ specific */
#define MSR_IA32_MCG_EAX 0x00000180
#define MSR_IA32_MCG_EBX 0x00000181
#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
-
+#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
+#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
+#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
+#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
+#define MSR_IA32_VMX_VMFUNC 0x00000491
+
+/* VMX_BASIC bits and bitmasks */
+#define VMX_BASIC_VMCS_SIZE_SHIFT 32
+#define VMX_BASIC_64 0x0001000000000000LLU
+#define VMX_BASIC_MEM_TYPE_SHIFT 50
+#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
+#define VMX_BASIC_MEM_TYPE_WB 6LLU
+#define VMX_BASIC_INOUT 0x0040000000000000LLU
+
+/* MSR_IA32_VMX_MISC bits */
+#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
+#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
/* AMD-V MSRs */
#define MSR_VM_CR 0xc0010114
typedef signed int s32;
typedef unsigned int u32;
+#if !defined(CONFIG_USE_STDINT) || !defined(__INT64_TYPE__)
typedef signed long long s64;
typedef unsigned long long u64;
+#else
+typedef __INT64_TYPE__ s64;
+typedef __UINT64_TYPE__ u64;
+#endif
#define BITS_PER_LONG 32
unsigned install_e820_map(unsigned max_entries, struct e820entry *);
struct boot_params *load_zimage(char *image, unsigned long kernel_size,
- void **load_address);
+ ulong *load_addressp);
int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
unsigned long initrd_addr, unsigned long initrd_size);
-void boot_zimage(void *setup_base, void *load_address);
-
#endif
#include <common.h>
#include <command.h>
+#include <errno.h>
#include <fdt_support.h>
#include <image.h>
#include <u-boot/zlib.h>
#include <asm/bootparam.h>
+#include <asm/cpu.h>
#include <asm/byteorder.h>
#include <asm/zimage.h>
#ifdef CONFIG_SYS_COREBOOT
}
if (is_zimage) {
- void *load_address;
+ ulong load_address;
char *base_ptr;
base_ptr = (char *)load_zimage(data, len, &load_address);
- images->os.load = (ulong)load_address;
+ images->os.load = load_address;
cmd_line_dest = base_ptr + COMMAND_LINE_OFFSET;
images->ep = (ulong)base_ptr;
} else if (images->ep) {
cmd_line_dest = (void *)images->ep + COMMAND_LINE_OFFSET;
} else {
- printf("## Kernel loading failed (no setup) ...\n");
+ printf("## Kernel loading failed (missing x86 kernel setup) ...\n");
goto error;
}
return 1;
}
+int boot_linux_kernel(ulong setup_base, ulong load_address, bool image_64bit)
+{
+ bootm_announce_and_cleanup();
+
+#ifdef CONFIG_SYS_COREBOOT
+ timestamp_add_now(TS_U_BOOT_START_KERNEL);
+#endif
+ if (image_64bit) {
+ if (!cpu_has_64bit()) {
+ puts("Cannot boot 64-bit kernel on 32-bit machine\n");
+ return -EFAULT;
+ }
+ return cpu_jump_to_64bit(setup_base, load_address);
+ } else {
+ /*
+ * Set %ebx, %ebp, and %edi to 0, %esi to point to the
+ * boot_params structure, and then jump to the kernel. We
+ * assume that %cs is 0x10, 4GB flat, and read/execute, and
+ * the data segments are 0x18, 4GB flat, and read/write.
+ * U-boot is setting them up that way for itself in
+ * arch/i386/cpu/cpu.c.
+ */
+ __asm__ __volatile__ (
+ "movl $0, %%ebp\n"
+ "cli\n"
+ "jmp *%[kernel_entry]\n"
+ :: [kernel_entry]"a"(load_address),
+ [boot_params] "S"(setup_base),
+ "b"(0), "D"(0)
+ );
+ }
+
+ /* We can't get to here */
+ return -EFAULT;
+}
+
/* Subcommand: GO */
static int boot_jump_linux(bootm_headers_t *images)
{
debug("## Transferring control to Linux (at address %08lx, kernel %08lx) ...\n",
images->ep, images->os.load);
- boot_zimage((struct boot_params *)images->ep, (void *)images->os.load);
- /* does not return */
-
- return 1;
+ return boot_linux_kernel(images->ep, images->os.load,
+ images->os.arch == IH_ARCH_X86_64);
}
int do_bootm_linux(int flag, int argc, char * const argv[],
if (flag & BOOTM_STATE_OS_PREP)
return boot_prep_linux(images);
- if (flag & BOOTM_STATE_OS_GO) {
- boot_jump_linux(images);
- return 0;
- }
+ if (flag & BOOTM_STATE_OS_GO)
+ return boot_jump_linux(images);
return boot_jump_linux(images);
}
#include <common.h>
#include <physmem.h>
+#include <asm/cpu.h>
#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
x86_phys_map_page(page_addr, page_addr, 0);
}
- /* Turn on paging */
- __asm__ __volatile__(
- /* Load the page table address */
- "movl %0, %%cr3\n\t"
- /* Enable pae */
- "movl %%cr4, %%eax\n\t"
- "orl $0x00000020, %%eax\n\t"
- "movl %%eax, %%cr4\n\t"
- /* Enable paging */
- "movl %%cr0, %%eax\n\t"
- "orl $0x80000000, %%eax\n\t"
- "movl %%eax, %%cr0\n\t"
- :
- : "r" (pdpt)
- : "eax"
- );
+ cpu_enable_paging_pae((ulong)pdpt);
}
/* Disable paging and PAE mode. */
static void x86_phys_exit_paging(void)
{
- /* Turn off paging */
- __asm__ __volatile__ (
- /* Disable paging */
- "movl %%cr0, %%eax\n\t"
- "andl $0x7fffffff, %%eax\n\t"
- "movl %%eax, %%cr0\n\t"
- /* Disable pae */
- "movl %%cr4, %%eax\n\t"
- "andl $0xffffffdf, %%eax\n\t"
- "movl %%eax, %%cr4\n\t"
- :
- :
- : "eax"
- );
+ cpu_disable_paging_pae();
}
/*
*/
#include <common.h>
+#include <inttypes.h>
#include <libfdt.h>
#include <malloc.h>
#include <asm/u-boot-x86.h>
*offset_ptr_ram += gd->reloc_off;
} else {
debug(" %p: rom reloc %x, ram %p, value %x,"
- " limit %lx\n", re_src,
+ " limit %" PRIXPTR "\n", re_src,
re_src->r_offset, offset_ptr_ram,
*offset_ptr_ram,
CONFIG_SYS_TEXT_BASE + size);
}
struct boot_params *load_zimage(char *image, unsigned long kernel_size,
- void **load_address)
+ ulong *load_addressp)
{
struct boot_params *setup_base;
int setup_size;
/* Determine load address */
if (big_image)
- *load_address = (void *)BZIMAGE_LOAD_ADDR;
+ *load_addressp = BZIMAGE_LOAD_ADDR;
else
- *load_address = (void *)ZIMAGE_LOAD_ADDR;
+ *load_addressp = ZIMAGE_LOAD_ADDR;
printf("Building boot_params at 0x%8.8lx\n", (ulong)setup_base);
memset(setup_base, 0, sizeof(*setup_base));
return 0;
}
- printf("Loading %s at address %p (%ld bytes)\n",
- big_image ? "bzImage" : "zImage", *load_address, kernel_size);
+ printf("Loading %s at address %lx (%ld bytes)\n",
+ big_image ? "bzImage" : "zImage", *load_addressp, kernel_size);
- memmove(*load_address, image + setup_size, kernel_size);
+ memmove((void *)*load_addressp, image + setup_size, kernel_size);
return setup_base;
}
return 0;
}
-void boot_zimage(void *setup_base, void *load_address)
-{
- bootm_announce_and_cleanup();
-
-#ifdef CONFIG_SYS_COREBOOT
- timestamp_add_now(TS_U_BOOT_START_KERNEL);
-#endif
- /*
- * Set %ebx, %ebp, and %edi to 0, %esi to point to the boot_params
- * structure, and then jump to the kernel. We assume that %cs is
- * 0x10, 4GB flat, and read/execute, and the data segments are 0x18,
- * 4GB flat, and read/write. U-boot is setting them up that way for
- * itself in arch/i386/cpu/cpu.c.
- */
- __asm__ __volatile__ (
- "movl $0, %%ebp\n"
- "cli\n"
- "jmp *%[kernel_entry]\n"
- :: [kernel_entry]"a"(load_address),
- [boot_params] "S"(setup_base),
- "b"(0), "D"(0)
- : "%ebp"
- );
-}
-
void setup_pcat_compatibility(void)
__attribute__((weak, alias("__setup_pcat_compatibility")));
{
struct boot_params *base_ptr;
void *bzImage_addr = NULL;
- void *load_address;
+ ulong load_address;
char *s;
ulong bzImage_size = 0;
ulong initrd_addr = 0;
base_ptr = load_zimage(bzImage_addr, bzImage_size, &load_address);
if (!base_ptr) {
- printf("## Kernel loading failed ...\n");
+ puts("## Kernel loading failed ...\n");
return -1;
}
if (setup_zimage(base_ptr, (char *)base_ptr + COMMAND_LINE_OFFSET,
0, initrd_addr, initrd_size)) {
- printf("Setting up boot parameters failed ...\n");
+ puts("Setting up boot parameters failed ...\n");
return -1;
}
/* we assume that the kernel is in place */
- boot_zimage(base_ptr, load_address);
- /* does not return */
-
- return -1;
+ return boot_linux_kernel((ulong)base_ptr, load_address, false);
}
U_BOOT_CMD(
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
/* JTAG */\
- MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
if TARGET_KWB
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "kwb"
if TARGET_TSERIES
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "tseries"
if TARGET_EB_CPUX9K2
-config SYS_CPU
- default "arm920t"
-
config SYS_BOARD
default "eb_cpux9k2"
if TARGET_VL_MA2SC
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "vl_ma2sc"
if TARGET_FLEA3
-config SYS_CPU
- default "arm1136"
-
config SYS_BOARD
default "flea3"
WIRELESS_SPACE BOARD
-#M: -
+M: Albert ARIBAUD <albert.u.boot@aribaud.net>
S: Maintained
F: board/LaCie/wireless_space/
F: include/configs/wireless_space.h
if TARGET_ASPENITE
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "aspenite"
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * flash.c - flash support for the 512k, 8bit boot flash
- and the 8MB 32bit extra flash on the DB64360
- * most of this file was based on the existing U-Boot
- * flash drivers.
- *
- * written or collected and sometimes rewritten by
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include "../include/mv_gen_reg.h"
-#include "../include/memory.h"
-#include "intel_flash.h"
-
-#define FLASH_ROM 0xFFFD /* unknown flash type */
-#define FLASH_RAM 0xFFFE /* unknown flash type */
-#define FLASH_MAN_UNKNOWN 0xFFFF0000
-
-/* #define DEBUG */
-
-/* Intel flash commands */
-int flash_erase_intel (flash_info_t * info, int s_first, int s_last);
-int write_word_intel (bank_addr_t addr, bank_word_t value);
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (int portwidth, vu_long * addr,
- flash_info_t * info);
-static int write_word (flash_info_t * info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned int i;
- unsigned long size_b0 = 0, size_b1 = 0;
- unsigned long base, flash_size;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* the boot flash */
- base = CONFIG_SYS_FLASH_BASE;
- size_b0 =
- flash_get_size (CONFIG_SYS_BOOT_FLASH_WIDTH, (vu_long *) base,
- &flash_info[0]);
-
- printf ("[%ldkB@%lx] ", size_b0 / 1024, base);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", base, size_b0, size_b0 << 20);
- }
-
- base = memoryGetDeviceBaseAddress (CONFIG_SYS_EXTRA_FLASH_DEVICE);
-/* base = memoryGetDeviceBaseAddress(DEV_CS3_BASE_ADDR);*/
- for (i = 1; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- unsigned long size =
- flash_get_size (CONFIG_SYS_EXTRA_FLASH_WIDTH,
- (vu_long *) base, &flash_info[i]);
-
- printf ("[%ldMB@%lx] ", size >> 20, base);
-
- if (flash_info[i].flash_id == FLASH_UNKNOWN) {
- if (i == 1) {
- printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", base, size_b1, size_b1 << 20);
- }
- break;
- }
- size_b1 += size;
- base += size;
- }
-
- flash_size = size_b0 + size_b1;
- return flash_size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
- int i;
- int sector_size;
-
- if (!info->sector_count)
- return;
-
- /* set up sector start address table */
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- case FLASH_28F128J3A:
- case FLASH_28F640J3A:
- case FLASH_RAM:
- /* this chip has uniformly spaced sectors */
- sector_size = info->size / info->sector_count;
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * sector_size);
- break;
- default:
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] =
- base + (i * 0x00020000) - 0x00060000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_STM:
- printf ("STM ");
- break;
- case FLASH_MAN_AMD:
- printf ("AMD ");
- break;
- case FLASH_MAN_FUJ:
- printf ("FUJITSU ");
- break;
- case FLASH_MAN_INTEL:
- printf ("INTEL ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- printf ("AM29LV040B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400B:
- printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T:
- printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B:
- printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T:
- printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B:
- printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T:
- printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B:
- printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T:
- printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_28F640J3A:
- printf ("28F640J3A (64 Mbit)\n");
- break;
- case FLASH_28F128J3A:
- printf ("28F128J3A (128 Mbit)\n");
- break;
- case FLASH_ROM:
- printf ("ROM\n");
- break;
- case FLASH_RAM:
- printf ("RAM\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- if ((info->size >> 20) > 0) {
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
- } else {
- printf (" Size: %ld kB in %d Sectors\n",
- info->size >> 10, info->sector_count);
- }
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i], info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static inline void flash_cmd (int width, volatile unsigned char *addr,
- int offset, unsigned char cmd)
-{
- /* supports 1x8, 1x16, and 2x16 */
- /* 2x8 and 4x8 are not supported */
- if (width == 4) {
- /* assuming chips are in 16 bit mode */
- /* 2x16 */
- unsigned long cmd32 = (cmd << 16) | cmd;
-
- *(volatile unsigned long *) (addr + offset * 2) = cmd32;
- } else {
- /* 1x16 or 1x8 */
- *(volatile unsigned char *) (addr + offset) = cmd;
- }
-}
-
-static ulong
-flash_get_size (int portwidth, vu_long * addr, flash_info_t * info)
-{
- short i;
- volatile unsigned char *caddr = (unsigned char *) addr;
- volatile unsigned short *saddr = (unsigned short *) addr;
- volatile unsigned long *laddr = (unsigned long *) addr;
- char old[2], save;
- ulong id = 0, manu = 0, base = (ulong) addr;
-
-#ifdef DEBUG
- printf ("%s: enter\n", __FUNCTION__);
-#endif
- info->portwidth = portwidth;
-
- save = *caddr;
-
- flash_cmd (portwidth, caddr, 0, 0xf0);
- flash_cmd (portwidth, caddr, 0, 0xf0);
-
- udelay (10);
-
- old[0] = caddr[0];
- old[1] = caddr[1];
-
-
- if (old[0] != 0xf0) {
- flash_cmd (portwidth, caddr, 0, 0xf0);
- flash_cmd (portwidth, caddr, 0, 0xf0);
-
- udelay (10);
-
- if (*caddr == 0xf0) {
- /* this area is ROM */
- *caddr = save;
- info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN;
- info->sector_count = 8;
- info->size = 0x80000;
- flash_get_offsets (base, info);
- return info->size;
- }
- } else {
- *caddr = 0;
-
- udelay (10);
-
- if (*caddr == 0) {
- /* this area is RAM */
- *caddr = save;
- info->flash_id = FLASH_RAM + FLASH_MAN_UNKNOWN;
- info->sector_count = 8;
- info->size = 0x80000;
- flash_get_offsets (base, info);
- return info->size;
- }
- flash_cmd (portwidth, caddr, 0, 0xf0);
-
- udelay (10);
- }
-
- /* Write auto select command: read Manufacturer ID */
- flash_cmd (portwidth, caddr, 0x555, 0xAA);
- flash_cmd (portwidth, caddr, 0x2AA, 0x55);
- flash_cmd (portwidth, caddr, 0x555, 0x90);
-
- udelay (10);
-
- if ((caddr[0] == old[0]) && (caddr[1] == old[1])) {
-
- /* this area is ROM */
- info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN;
- info->sector_count = 8;
- info->size = 0x80000;
- flash_get_offsets (base, info);
- return info->size;
-#ifdef DEBUG
- } else {
- printf ("%px%d: %02x:%02x -> %02x:%02x\n",
- caddr, portwidth, old[0], old[1], caddr[0], caddr[1]);
-#endif
- }
-
- switch (portwidth) {
- case 1:
- manu = caddr[0];
- manu |= manu << 16;
- id = caddr[1];
- break;
- case 2:
- manu = saddr[0];
- manu |= manu << 16;
- id = saddr[1];
- id |= id << 16;
- break;
- case 4:
- manu = laddr[0];
- id = laddr[1];
- break;
- }
-
-#ifdef DEBUG
- flash_cmd (portwidth, caddr, 0, 0xf0);
-
- printf ("\n%08lx:%08lx:%08lx\n", base, manu, id);
- printf ("%08lx %08lx %08lx %08lx\n",
- laddr[0], laddr[1], laddr[2], laddr[3]);
-#endif
-
- switch (manu) {
- case STM_MANUFACT:
- info->flash_id = FLASH_MAN_STM;
- break;
- case AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- flash_cmd (portwidth, caddr, 0, 0xf0);
-
- printf ("Unknown Mfr [%08lx]:%08lx\n", manu, id);
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- switch (id) {
- case AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00100000;
- info->chipwidth = 1;
- break; /* => 1 MB */
-
- case AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00100000;
- info->chipwidth = 1;
- break; /* => 1 MB */
-
- case AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00200000;
- info->chipwidth = 1;
- break; /* => 2 MB */
-
- case AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00200000;
- info->chipwidth = 1;
- break; /* => 2 MB */
-
- case AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00400000;
- info->chipwidth = 1;
- break; /* => 4 MB */
-
- case AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00400000;
- info->chipwidth = 1;
- break; /* => 4 MB */
-#if 0 /* enable when device IDs are available */
- case AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-#endif
- case AMD_ID_LV040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x80000;
- info->chipwidth = 1;
- break; /* => 512 kB */
-
- case INTEL_ID_28F640J3A:
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = 64;
- info->size = 128 * 1024 * 64; /* 128kbytes x 64 blocks */
- info->chipwidth = 2;
- if (portwidth == 4)
- info->size *= 2; /* 2x16 */
- break;
-
- case INTEL_ID_28F128J3A:
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 128 * 1024 * 128; /* 128kbytes x 128 blocks */
- info->chipwidth = 2;
- if (portwidth == 4)
- info->size *= 2; /* 2x16 */
- break;
-
- default:
- flash_cmd (portwidth, caddr, 0, 0xf0);
-
- printf ("Unknown id %lx:[%lx]\n", manu, id);
- info->flash_id = FLASH_UNKNOWN;
- info->chipwidth = 1;
- return (0); /* => no or unknown flash */
-
- }
-
- flash_get_offsets (base, info);
-
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0)=0x02 */
- /* D0 = 1 if protected */
- caddr = (volatile unsigned char *) (info->start[i]);
- saddr = (volatile unsigned short *) (info->start[i]);
- laddr = (volatile unsigned long *) (info->start[i]);
- if (portwidth == 1)
- info->protect[i] = caddr[2] & 1;
- else if (portwidth == 2)
- info->protect[i] = saddr[2] & 1;
- else
- info->protect[i] = laddr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- caddr = (volatile unsigned char *) info->start[0];
-
- flash_cmd (portwidth, caddr, 0, 0xF0); /* reset bank */
- }
-
- return (info->size);
-}
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- volatile unsigned char *addr = (uchar *) (info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
-/* modified to support 2x16 Intel flash */
-/* Note that the code will not exit on a flash erasure error or timeout */
-/* but will print and error message and continue processing sectors */
-/* until they are all erased. */
-/* 10-16-2002 P. Marchese */
- ulong mask;
- int timeout;
-
- if (info->portwidth == 4)
-/* {
- printf ("- Warning: erasing of 32Bit (2*16Bit i.e. 2*28F640J3A) not supported yet !!!! \n");
- return 1;
- }*/
- {
- /* make sure it's Intel flash */
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- /* yup! it's an Intel flash */
- /* is it 16-bits wide? */
- if (info->chipwidth == 2) {
- /* yup! it's 16-bits wide */
- /* are there any sectors to process? */
- if ((s_first < 0) || (s_first > s_last)) {
- printf ("Error: There are no sectors to erase\n");
- printf ("Either sector %d is less than zero\n", s_first);
- printf ("or sector %d is greater than sector %d\n", s_first, s_last);
- return 1;
- }
- /* check for protected sectors */
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect)
- if (info->protect[sect])
- prot++;
- /* if variable "prot" is nonzero, there are protected sectors */
- if (prot)
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- /* reset the flash */
- flash_cmd (info->portwidth, addr, 0,
- CHIP_CMD_RST);
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
- /* Clear the status register */
- flash_cmd (info->portwidth, addr, 0,
- CHIP_CMD_CLR_STAT);
- flash_cmd (info->portwidth, addr, 0,
- CHIP_CMD_RST);
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- /* is the sector unprotected? */
- if (info->protect[sect] == 0) { /* not protected */
- /* issue the single block erase command, 0x20 */
- flash_cmd (info->portwidth,
- (volatile unsigned
- char *) info->
- start[sect], 0,
- CHIP_CMD_ERASE1);
- /* issue the erase confirm command, 0xD0 */
- flash_cmd (info->portwidth,
- (volatile unsigned
- char *) info->
- start[sect], 0,
- CHIP_CMD_ERASE2);
- l_sect = sect;
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
- /* poll for erasure completion */
- /* put flash into read status mode by writing 0x70 to it */
- flash_cmd (info->portwidth,
- addr, 0,
- CHIP_CMD_RD_STAT);
- /* setup the status register mask */
- mask = CHIP_STAT_RDY |
- (CHIP_STAT_RDY << 16);
- /* init. the timeout counter */
- start = get_timer (0);
- /* keep looping while the flash is not ready */
- /* exit the loop by timing out or the flash */
- /* becomes ready again */
- timeout = 0;
- while ((*
- (volatile unsigned
- long *) info->
- start[sect] & mask) !=
- mask) {
- /* has the timeout limit been reached? */
- if (get_timer (start)
- >
- CONFIG_SYS_FLASH_ERASE_TOUT)
- {
- /* timeout limit reached */
- printf ("Time out limit reached erasing sector at address %08lx\n", info->start[sect]);
- printf ("Continuing with next sector\n");
- timeout = 1;
- goto timed_out_error;
- }
- /* put flash into read status mode by writing 0x70 to it */
- flash_cmd (info->
- portwidth,
- addr, 0,
- CHIP_CMD_RD_STAT);
- }
- /* did we timeout? */
- timed_out_error:if (timeout == 0)
- {
- /* didn't timeout, so check the status register */
- /* create the status mask to check for errors */
- mask = CHIP_STAT_ECLBS;
- mask = mask | (mask <<
- 16);
- /* put flash into read status mode by writing 0x70 to it */
- flash_cmd (info->
- portwidth,
- addr, 0,
- CHIP_CMD_RD_STAT);
- /* are there any errors? */
- if ((*
- (volatile
- unsigned long *)
- info->
- start[sect] &
- mask) != 0) {
- /* We got an erasure error */
- printf ("Flash erasure error at address 0x%08lx\n", info->start[sect]);
- printf ("Continuing with next sector\n");
- /* reset the flash */
- flash_cmd
- (info->
- portwidth,
- addr,
- 0,
- CHIP_CMD_RST);
- }
- }
- /* erasure completed without errors */
- /* reset the flash */
- flash_cmd (info->portwidth,
- addr, 0,
- CHIP_CMD_RST);
- } /* end if not protected */
- } /* end for loop */
- printf ("Flash erasure done\n");
- return 0;
- } else {
- /* The Intel flash is not 16-bit wide */
- /* print and error message and return */
- /* NOTE: you can add routines here to handle other size flash */
- printf ("Error: Intel flash device is only %d-bits wide\n", info->chipwidth * 8);
- printf ("The erasure code only handles Intel 16-bit wide flash memory\n");
- return 1;
- }
- } else {
- /* Not Intel flash so return an error as a write timeout */
- /* NOTE: if it's another type flash, stick its routine here */
- printf ("Error: The flash device is not Intel type\n");
- printf ("The erasure code only supports Intel flash in a 32-bit port width\n");
- return 1;
- }
- }
-
- /* end 32-bit wide flash code */
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM)
- return 1; /* Rom can not be erased */
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { /* RAM just copy 0s to RAM */
- for (sect = s_first; sect <= s_last; sect++) {
- int sector_size = info->size / info->sector_count;
-
- addr = (uchar *) (info->start[sect]);
- memset ((void *) addr, 0, sector_size);
- }
- return 0;
- }
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { /* Intel works spezial */
- return flash_erase_intel (info,
- (unsigned short) s_first,
- (unsigned short) s_last);
- }
-#if 0
- if ((info->flash_id == FLASH_UNKNOWN) || /* Flash is unknown to PPCBoot */
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-#endif
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- flash_cmd (info->portwidth, addr, 0x555, 0xAA); /* start erase routine */
- flash_cmd (info->portwidth, addr, 0x2AA, 0x55);
- flash_cmd (info->portwidth, addr, 0x555, 0x80);
- flash_cmd (info->portwidth, addr, 0x555, 0xAA);
- flash_cmd (info->portwidth, addr, 0x2AA, 0x55);
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (uchar *) (info->start[sect]);
- flash_cmd (info->portwidth, addr, 0, 0x30);
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (volatile unsigned char *) (info->start[l_sect]);
- /* broken for 2x16: TODO */
- while ((addr[0] & 0x80) != 0x80) {
- if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- DONE:
- /* reset to read mode */
- addr = (volatile unsigned char *) info->start[0];
- flash_cmd (info->portwidth, addr, 0, 0xf0);
- flash_cmd (info->portwidth, addr, 0, 0xf0);
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-/* broken for 2x16: TODO */
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
-/* Commented out since the below code should work for 32-bit(2x 16 flash) */
-/* 10-16-2002 P. Marchese */
-/* if(info->portwidth==4) return 1; */
-/* if(info->portwidth==4) {
- printf ("- Warning: writting of 32Bit (2*16Bit i.e. 2*28F640J3A) not supported yet !!!! \n");
- return 1;
- }*/
-
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM)
- return 0;
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {
- memcpy ((void *) addr, src, cnt);
- return 0;
- }
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < 4 && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i = 0; i < 4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_word (info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-/* broken for 2x16: TODO */
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
- volatile unsigned char *addr = (uchar *) (info->start[0]);
- ulong start;
- int flag, i;
- ulong mask;
-
-/* modified so that it handles 32-bit(2x16 Intel flash programming */
-/* 10-16-2002 P. Marchese */
-
- if (info->portwidth == 4)
-/* {
- printf ("- Warning: writting of 32Bit (2*16Bit i.e. 2*28F640J3A) not supported yet !!!! \n");
- return 1;
- }*/
- {
- /* make sure it's Intel flash */
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- /* yup! it's an Intel flash */
- /* is it 16-bits wide? */
- if (info->chipwidth == 2) {
- /* yup! it's 16-bits wide */
- /* so we know how to program it */
- /* reset the flash */
- flash_cmd (info->portwidth, addr, 0,
- CHIP_CMD_RST);
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
- /* Clear the status register */
- flash_cmd (info->portwidth, addr, 0,
- CHIP_CMD_CLR_STAT);
- flash_cmd (info->portwidth, addr, 0,
- CHIP_CMD_RST);
- /* 1st cycle of word/byte program */
- /* write 0x40 to the location to program */
- flash_cmd (info->portwidth, (uchar *) dest, 0,
- CHIP_CMD_PROG);
- /* 2nd cycle of word/byte program */
- /* write the data to the destination address */
- *(ulong *) dest = data;
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
- /* setup the status register mask */
- mask = CHIP_STAT_RDY | (CHIP_STAT_RDY << 16);
- /* put flash into read status mode by writing 0x70 to it */
- flash_cmd (info->portwidth, addr, 0,
- CHIP_CMD_RD_STAT);
- /* init. the timeout counter */
- start = get_timer (0);
- /* keep looping while the flash is not ready */
- /* exit the loop by timing out or the flash */
- /* becomes ready again */
-/* 11-13-2002 Paul Marchese */
-/* modified while loop conditional statement */
-/* because we were always timing out. */
-/* there is a type mismatch, "addr[0]" */
-/* returns a byte but "mask" is a 32-bit value */
- while ((*(volatile unsigned long *) info->
- start[0] & mask) != mask)
-/* original code */
-/* while (addr[0] & mask) != mask) */
- {
- /* has the timeout limit been reached? */
- if (get_timer (start) >
- CONFIG_SYS_FLASH_WRITE_TOUT) {
- /* timeout limit reached */
- printf ("Time out limit reached programming address %08lx with data %08lx\n", dest, data);
- /* reset the flash */
- flash_cmd (info->portwidth,
- addr, 0,
- CHIP_CMD_RST);
- return (1);
- }
- /* put flash into read status mode by writing 0x70 to it */
- flash_cmd (info->portwidth, addr, 0,
- CHIP_CMD_RD_STAT);
- }
- /* flash is ready, so check the status */
- /* create the status mask to check for errors */
- mask = CHIP_STAT_DPS | CHIP_STAT_VPPS |
- CHIP_STAT_PSLBS;
- mask = mask | (mask << 16);
- /* put flash into read status mode by writing 0x70 to it */
- flash_cmd (info->portwidth, addr, 0,
- CHIP_CMD_RD_STAT);
- /* are there any errors? */
- if ((addr[0] & mask) != 0) {
- /* We got a one of the following errors: */
- /* Voltage range, Device protect, or programming */
- /* return the error as a device timeout */
- /* put flash into read status mode by writing 0x70 to it */
- flash_cmd (info->portwidth, addr, 0,
- CHIP_CMD_RD_STAT);
- printf ("Flash programming error at address 0x%08lx\n", dest);
- printf ("Flash status register contains 0x%08lx\n", (unsigned long) addr[0]);
- /* reset the flash */
- flash_cmd (info->portwidth, addr, 0,
- CHIP_CMD_RST);
- return 1;
- }
- /* write completed without errors */
- /* reset the flash */
- flash_cmd (info->portwidth, addr, 0,
- CHIP_CMD_RST);
- return 0;
- } else {
- /* it's not 16-bits wide, so return an error as a write timeout */
- /* NOTE: you can add routines here to handle other size flash */
- printf ("Error: Intel flash device is only %d-bits wide\n", info->chipwidth * 8);
- printf ("The write code only handles Intel 16-bit wide flash memory\n");
- return 1;
- }
- } else {
- /* not Intel flash so return an error as a write timeout */
- /* NOTE: if it's another type flash, stick its routine here */
- printf ("Error: The flash device is not Intel type\n");
- printf ("The code only supports Intel flash in a 32-bit port width\n");
- return 1;
- }
- }
-
- /* end of 32-bit flash code */
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM)
- return 1;
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {
- *(unsigned long *) dest = data;
- return 0;
- }
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- unsigned short low = data & 0xffff;
- unsigned short hi = (data >> 16) & 0xffff;
- int ret = write_word_intel ((bank_addr_t) dest, hi);
-
- if (!ret)
- ret = write_word_intel ((bank_addr_t) (dest + 2),
- low);
-
- return ret;
- }
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *) dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- /* first, perform an unlock bypass command to speed up flash writes */
- addr[0x555] = 0xAA;
- addr[0x2AA] = 0x55;
- addr[0x555] = 0x20;
-
- /* write each byte out */
- for (i = 0; i < 4; i++) {
- char *data_ch = (char *) &data;
-
- addr[0] = 0xA0;
- *(((char *) dest) + i) = data_ch[i];
- udelay (10); /* XXX */
- }
-
- /* we're done, now do an unlock bypass reset */
- addr[0] = 0x90;
- addr[0] = 0x00;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*((vu_long *) dest) & 0x00800080) != (data & 0x00800080)) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
- * extra improvments by Brain Waite
- */
-#include <common.h>
-#include <mpc8xx.h>
-#include <malloc.h>
-#include <i2c.h>
-#include "../include/mv_gen_reg.h"
-#include "../include/core.h"
-
-#define MAX_I2C_RETRYS 10
-#define I2C_DELAY 1000 /* Should be at least the # of MHz of Tclk */
-#undef DEBUG_I2C
-/*#define DEBUG_I2C*/
-
-#ifdef DEBUG_I2C
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-/* Assuming that there is only one master on the bus (us) */
-
-void i2c_init (int speed, int slaveaddr)
-{
- unsigned int n, m, freq, margin, power;
- unsigned int actualN = 0, actualM = 0;
- unsigned int control, status;
- unsigned int minMargin = 0xffffffff;
- unsigned int tclk = CONFIG_SYS_TCLK;
- unsigned int i2cFreq = speed; /* 100000 max. Fast mode not supported */
-
- DP (puts ("i2c_init\n"));
-/* gtI2cMasterInit */
- for (n = 0; n < 8; n++) {
- for (m = 0; m < 16; m++) {
- power = 2 << n; /* power = 2^(n+1) */
- freq = tclk / (10 * (m + 1) * power);
- if (i2cFreq > freq)
- margin = i2cFreq - freq;
- else
- margin = freq - i2cFreq;
- if (margin < minMargin) {
- minMargin = margin;
- actualN = n;
- actualM = m;
- }
- }
- }
-
- DP (puts ("setup i2c bus\n"));
-
- /* Setup bus */
-/* gtI2cReset */
- GT_REG_WRITE (I2C_SOFT_RESET, 0);
-
- DP (puts ("udelay...\n"));
-
- udelay (I2C_DELAY);
-
- DP (puts ("set baudrate\n"));
-
- GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN);
- GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6));
-
- udelay (I2C_DELAY * 10);
-
- DP (puts ("read control, baudrate\n"));
-
- GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
- GT_REG_READ (I2C_CONTROL, &control);
-}
-
-static uchar i2c_start (void)
-{ /* DB64360 checked -> ok */
- unsigned int control, status;
- int count = 0;
-
- DP (puts ("i2c_start\n"));
-
- /* Set the start bit */
-
-/* gtI2cGenerateStartBit() */
-
- GT_REG_READ (I2C_CONTROL, &control);
- control |= (0x1 << 5); /* generate the I2C_START_BIT */
- GT_REG_WRITE (I2C_CONTROL, control);
-
- GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
-
- count = 0;
- while ((status & 0xff) != 0x08) {
- udelay (I2C_DELAY);
- if (count > 20) {
- GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
- return (status);
- }
- GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
- count++;
- }
-
- return (0);
-}
-
-static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
-{
- unsigned int status, data, bits = 7;
- int count = 0;
-
- DP (puts ("i2c_select_device\n"));
-
- /* Output slave address */
-
- if (ten_bit) {
- bits = 10;
- }
-
- data = (dev_addr << 1);
- /* set the read bit */
- data |= read;
- GT_REG_WRITE (I2C_DATA, data);
- /* assert the address */
- RESET_REG_BITS (I2C_CONTROL, BIT3);
-
- udelay (I2C_DELAY);
-
- GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
- count = 0;
- while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) {
- udelay (I2C_DELAY);
- if (count > 20) {
- GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
- return (status);
- }
- GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
- count++;
- }
-
- if (bits == 10) {
- printf ("10 bit I2C addressing not yet implemented\n");
- return (0xff);
- }
-
- return (0);
-}
-
-static uchar i2c_get_data (uchar * return_data, int len)
-{
-
- unsigned int data, status = 0;
- int count = 0;
-
- DP (puts ("i2c_get_data\n"));
-
- while (len) {
-
- /* Get and return the data */
-
- RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
-
- udelay (I2C_DELAY * 5);
-
- GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
- count++;
- while ((status & 0xff) != 0x50) {
- udelay (I2C_DELAY);
- if (count > 2) {
- GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
- return 0;
- }
- GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
- count++;
- }
- GT_REG_READ (I2C_DATA, &data);
- len--;
- *return_data = (uchar) data;
- return_data++;
- }
- RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3);
- while ((status & 0xff) != 0x58) {
- udelay (I2C_DELAY);
- if (count > 200) {
- GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
- return (status);
- }
- GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
- count++;
- }
- GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /* stop */
-
- return (0);
-}
-
-static uchar i2c_write_data (unsigned int *data, int len)
-{
- unsigned int status;
- int count = 0;
- unsigned int temp;
- unsigned int *temp_ptr = data;
-
- DP (puts ("i2c_write_data\n"));
-
- while (len) {
- temp = (unsigned int) (*temp_ptr);
- GT_REG_WRITE (I2C_DATA, temp);
- RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
-
- udelay (I2C_DELAY);
-
- GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
- count++;
- while ((status & 0xff) != 0x28) {
- udelay (I2C_DELAY);
- if (count > 20) {
- GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
- return (status);
- }
- GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
- count++;
- }
- len--;
- temp_ptr++;
- }
-/* 11-14-2002 Paul Marchese */
-/* Can't have the write issuing a stop command */
-/* it's wrong to have a stop bit in read stream or write stream */
-/* since we don't know if it's really the end of the command */
-/* or whether we have just send the device address + offset */
-/* we will push issuing the stop command off to the original */
-/* calling function */
- /* set the interrupt bit in the control register */
- GT_REG_WRITE (I2C_CONTROL, (0x1 << 3));
- udelay (I2C_DELAY * 10);
- return (0);
-}
-
-/* 11-14-2002 Paul Marchese */
-/* created this function to get the i2c_write() */
-/* function working properly. */
-/* function to write bytes out on the i2c bus */
-/* this is identical to the function i2c_write_data() */
-/* except that it requires a buffer that is an */
-/* unsigned character array. You can't use */
-/* i2c_write_data() to send an array of unsigned characters */
-/* since the byte of interest ends up on the wrong end of the bus */
-/* aah, the joys of big endian versus little endian! */
-/* */
-/* returns 0 = success */
-/* anything other than zero is failure */
-static uchar i2c_write_byte (unsigned char *data, int len)
-{
- unsigned int status;
- int count = 0;
- unsigned int temp;
- unsigned char *temp_ptr = data;
-
- DP (puts ("i2c_write_byte\n"));
-
- while (len) {
- /* Set and assert the data */
- temp = *temp_ptr;
- GT_REG_WRITE (I2C_DATA, temp);
- RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
-
- udelay (I2C_DELAY);
-
- GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
- count++;
- while ((status & 0xff) != 0x28) {
- udelay (I2C_DELAY);
- if (count > 20) {
- GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
- return (status);
- }
- GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
- count++;
- }
- len--;
- temp_ptr++;
- }
-/* Can't have the write issuing a stop command */
-/* it's wrong to have a stop bit in read stream or write stream */
-/* since we don't know if it's really the end of the command */
-/* or whether we have just send the device address + offset */
-/* we will push issuing the stop command off to the original */
-/* calling function */
-/* GT_REG_WRITE(I2C_CONTROL, (0x1 << 3) | (0x1 << 4));
- GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); */
- /* set the interrupt bit in the control register */
- GT_REG_WRITE (I2C_CONTROL, (0x1 << 3));
- udelay (I2C_DELAY * 10);
-
- return (0);
-}
-
-static uchar
-i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit,
- int alen)
-{
- uchar status;
- unsigned int table[2];
-
-/* initialize the table of address offset bytes */
-/* utilized for 2 byte address offsets */
-/* NOTE: the order is high byte first! */
- table[1] = offset & 0xff; /* low byte */
- table[0] = offset / 0x100; /* high byte */
-
- DP (puts ("i2c_set_dev_offset\n"));
-
- status = i2c_select_device (dev_addr, 0, ten_bit);
- if (status) {
-#ifdef DEBUG_I2C
- printf ("Failed to select device setting offset: 0x%02x\n",
- status);
-#endif
- return status;
- }
-/* check the address offset length */
- if (alen == 0)
- /* no address offset */
- return (0);
- else if (alen == 1) {
- /* 1 byte address offset */
- status = i2c_write_data (&offset, 1);
- if (status) {
-#ifdef DEBUG_I2C
- printf ("Failed to write data: 0x%02x\n", status);
-#endif
- return status;
- }
- } else if (alen == 2) {
- /* 2 bytes address offset */
- status = i2c_write_data (table, 2);
- if (status) {
-#ifdef DEBUG_I2C
- printf ("Failed to write data: 0x%02x\n", status);
-#endif
- return status;
- }
- } else {
- /* address offset unknown or not supported */
- printf ("Address length offset %d is not supported\n", alen);
- return 1;
- }
- return 0; /* sucessful completion */
-}
-
-int
-i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
- int len)
-{
- uchar status = 0;
- unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
-
- DP (puts ("i2c_read\n"));
-
- /* set the i2c frequency */
- i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
-
- status = i2c_start ();
-
- if (status) {
-#ifdef DEBUG_I2C
- printf ("Transaction start failed: 0x%02x\n", status);
-#endif
- return status;
- }
-
- status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */
- if (status) {
-#ifdef DEBUG_I2C
- printf ("Failed to set slave address & offset: 0x%02x\n",
- status);
-#endif
- return status;
- }
-
- /* set the i2c frequency again */
- i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
-
- status = i2c_start ();
- if (status) {
-#ifdef DEBUG_I2C
- printf ("Transaction restart failed: 0x%02x\n", status);
-#endif
- return status;
- }
-
- status = i2c_select_device (dev_addr, 1, 0); /* send the slave address */
- if (status) {
-#ifdef DEBUG_I2C
- printf ("Address not acknowledged: 0x%02x\n", status);
-#endif
- return status;
- }
-
- status = i2c_get_data (data, len);
- if (status) {
-#ifdef DEBUG_I2C
- printf ("Data not received: 0x%02x\n", status);
-#endif
- return status;
- }
-
- return 0;
-}
-
-/* 11-14-2002 Paul Marchese */
-/* Function to set the I2C stop bit */
-void i2c_stop (void)
-{
- GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));
-}
-
-/* 11-14-2002 Paul Marchese */
-/* I2C write function */
-/* dev_addr = device address */
-/* offset = address offset */
-/* alen = length in bytes of the address offset */
-/* data = pointer to buffer to read data into */
-/* len = # of bytes to read */
-/* */
-/* returns 0 = succesful */
-/* anything but zero is failure */
-int
-i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
- int len)
-{
- uchar status = 0;
- unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
-
- DP (puts ("i2c_write\n"));
-
- /* set the i2c frequency */
- i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
-
- status = i2c_start (); /* send a start bit */
-
- if (status) {
-#ifdef DEBUG_I2C
- printf ("Transaction start failed: 0x%02x\n", status);
-#endif
- return status;
- }
-
- status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */
- if (status) {
-#ifdef DEBUG_I2C
- printf ("Failed to set slave address & offset: 0x%02x\n",
- status);
-#endif
- return status;
- }
-
-
- status = i2c_write_byte (data, len); /* write the data */
- if (status) {
-#ifdef DEBUG_I2C
- printf ("Data not written: 0x%02x\n", status);
-#endif
- return status;
- }
- /* issue a stop bit */
- i2c_stop ();
- return 0;
-}
-
-/* 11-14-2002 Paul Marchese */
-/* function to determine if an I2C device is present */
-/* chip = device address of chip to check for */
-/* */
-/* returns 0 = sucessful, the device exists */
-/* anything other than zero is failure, no device */
-int i2c_probe (uchar chip)
-{
-
- /* We are just looking for an <ACK> back. */
- /* To see if the device/chip is there */
-
-#ifdef DEBUG_I2C
- unsigned int i2c_status;
-#endif
- uchar status = 0;
- unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
-
- DP (puts ("i2c_probe\n"));
-
- /* set the i2c frequency */
- i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
-
- status = i2c_start (); /* send a start bit */
-
- if (status) {
-#ifdef DEBUG_I2C
- printf ("Transaction start failed: 0x%02x\n", status);
-#endif
- return (int) status;
- }
-
- status = i2c_set_dev_offset (chip, 0, 0, 0); /* send the slave address + no offset */
- if (status) {
-#ifdef DEBUG_I2C
- printf ("Failed to set slave address: 0x%02x\n", status);
-#endif
- return (int) status;
- }
-#ifdef DEBUG_I2C
- GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status);
- printf ("address %#x returned %#x\n", chip, i2c_status);
-#endif
- /* issue a stop bit */
- i2c_stop ();
- return 0; /* successful completion */
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Hacked for the marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include "../include/mv_gen_reg.h"
-#include "../include/memory.h"
-#include "intel_flash.h"
-
-
-/*-----------------------------------------------------------------------
- * Protection Flags:
- */
-#define FLAG_PROTECT_SET 0x01
-#define FLAG_PROTECT_CLEAR 0x02
-
-static void bank_reset (flash_info_t * info, int sect)
-{
- bank_addr_t addrw, eaddrw;
-
- addrw = (bank_addr_t) info->start[sect];
- eaddrw = BANK_ADDR_NEXT_WORD (addrw);
-
- while (addrw < eaddrw) {
-#ifdef FLASH_DEBUG
- printf (" writing reset cmd to addr 0x%08lx\n",
- (unsigned long) addrw);
-#endif
- *addrw = BANK_CMD_RST;
- addrw++;
- }
-}
-
-static void bank_erase_init (flash_info_t * info, int sect)
-{
- bank_addr_t addrw, saddrw, eaddrw;
- int flag;
-
-#ifdef FLASH_DEBUG
- printf ("0x%08x BANK_CMD_PROG\n", BANK_CMD_PROG);
- printf ("0x%08x BANK_CMD_ERASE1\n", BANK_CMD_ERASE1);
- printf ("0x%08x BANK_CMD_ERASE2\n", BANK_CMD_ERASE2);
- printf ("0x%08x BANK_CMD_CLR_STAT\n", BANK_CMD_CLR_STAT);
- printf ("0x%08x BANK_CMD_RST\n", BANK_CMD_RST);
- printf ("0x%08x BANK_STAT_RDY\n", BANK_STAT_RDY);
- printf ("0x%08x BANK_STAT_ERR\n", BANK_STAT_ERR);
-#endif
-
- saddrw = (bank_addr_t) info->start[sect];
- eaddrw = BANK_ADDR_NEXT_WORD (saddrw);
-
-#ifdef FLASH_DEBUG
- printf ("erasing sector %d, start addr = 0x%08lx "
- "(bank next word addr = 0x%08lx)\n", sect,
- (unsigned long) saddrw, (unsigned long) eaddrw);
-#endif
-
- /* Disable intrs which might cause a timeout here */
- flag = disable_interrupts ();
-
- for (addrw = saddrw; addrw < eaddrw; addrw++) {
-#ifdef FLASH_DEBUG
- printf (" writing erase cmd to addr 0x%08lx\n",
- (unsigned long) addrw);
-#endif
- *addrw = BANK_CMD_ERASE1;
- *addrw = BANK_CMD_ERASE2;
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-}
-
-static int bank_erase_poll (flash_info_t * info, int sect)
-{
- bank_addr_t addrw, saddrw, eaddrw;
- int sectdone, haderr;
-
- saddrw = (bank_addr_t) info->start[sect];
- eaddrw = BANK_ADDR_NEXT_WORD (saddrw);
-
- sectdone = 1;
- haderr = 0;
-
- for (addrw = saddrw; addrw < eaddrw; addrw++) {
- bank_word_t stat = *addrw;
-
-#ifdef FLASH_DEBUG
- printf (" checking status at addr "
- "0x%08x [0x%08x]\n", (unsigned long) addrw, stat);
-#endif
- if ((stat & BANK_STAT_RDY) != BANK_STAT_RDY)
- sectdone = 0;
- else if ((stat & BANK_STAT_ERR) != 0) {
- printf (" failed on sector %d "
- "(stat = 0x%08x) at "
- "address 0x%p\n", sect, stat, addrw);
- *addrw = BANK_CMD_CLR_STAT;
- haderr = 1;
- }
- }
-
- if (haderr)
- return (-1);
- else
- return (sectdone);
-}
-
-int write_word_intel (bank_addr_t addr, bank_word_t value)
-{
- bank_word_t stat;
- ulong start;
- int flag, retval;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- *addr = BANK_CMD_PROG;
-
- *addr = value;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- retval = 0;
-
- /* data polling for D7 */
- start = get_timer (0);
- do {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- retval = 1;
- goto done;
- }
- stat = *addr;
- } while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY);
-
- if ((stat & BANK_STAT_ERR) != 0) {
- printf ("flash program failed (stat = 0x%08lx) "
- "at address 0x%08lx\n", (ulong) stat, (ulong) addr);
- *addr = BANK_CMD_CLR_STAT;
- retval = 3;
- }
-
- done:
- /* reset to read mode */
- *addr = BANK_CMD_RST;
-
- return (retval);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase_intel (flash_info_t * info, int s_first, int s_last)
-{
- int prot, sect, haderr;
- ulong start, now, last;
-
-#ifdef FLASH_DEBUG
- printf ("\nflash_erase: erase %d sectors (%d to %d incl.) from\n"
- " Bank # %d: ", s_last - s_first + 1, s_first, s_last,
- (info - flash_info) + 1);
- flash_print_info (info);
-#endif
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sector%s will not be erased!\n", prot, (prot > 1 ? "s" : ""));
- }
-
- start = get_timer (0);
- last = 0;
- haderr = 0;
-
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- ulong estart;
- int sectdone;
-
- bank_erase_init (info, sect);
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- estart = get_timer (start);
-
- do {
- now = get_timer (start);
-
- if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout (sect %d)\n", sect);
- haderr = 1;
- break;
- }
-#ifndef FLASH_DEBUG
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
-#endif
-
- sectdone = bank_erase_poll (info, sect);
-
- if (sectdone < 0) {
- haderr = 1;
- break;
- }
-
- } while (!sectdone);
-
- if (haderr)
- break;
- }
- }
-
- if (haderr > 0)
- printf (" failed\n");
- else
- printf (" done\n");
-
- /* reset to read mode */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- bank_reset (info, sect);
- }
- }
- return haderr;
-}
+++ /dev/null
-#include <config.h>
-#include <74xx_7xx.h>
-#include "version.h"
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#include "../include/mv_gen_reg.h"
-
-#ifdef CONFIG_ECC
- /* Galileo specific asm code for initializing ECC */
- .globl board_relocate_rom
-board_relocate_rom:
- mflr r7
- /* update the location of the GT registers */
- lis r11, CONFIG_SYS_GT_REGS@h
- /* if we're using ECC, we must use the DMA engine to copy ourselves */
- bl start_idma_transfer_0
- bl wait_for_idma_0
- bl stop_idma_engine_0
-
- mtlr r7
- blr
-
- .globl board_init_ecc
-board_init_ecc:
- mflr r7
- /* NOTE: r10 still contains the location we've been relocated to
- * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
-
- /* now that we're running from ram, init the rest of main memory
- * for ECC use */
- lis r8, CONFIG_SYS_MONITOR_LEN@h
- ori r8, r8, CONFIG_SYS_MONITOR_LEN@l
-
- divw r3, r10, r8
-
- /* set up the counter, and init the starting address */
- mtctr r3
- li r12, 0
-
- /* bytes per transfer */
- mr r5, r8
-about_to_init_ecc:
-1: mr r3, r12
- mr r4, r12
- bl start_idma_transfer_0
- bl wait_for_idma_0
- bl stop_idma_engine_0
- add r12, r12, r8
- bdnz 1b
-
- mtlr r7
- blr
-
- /* r3: dest addr
- * r4: source addr
- * r5: byte count
- * r11: gt regbase
- * trashes: r6, r5
- */
-start_idma_transfer_0:
- /* set the byte count, including the OWN bit */
- mr r6, r11
- ori r6, r6, CHANNEL0_DMA_BYTE_COUNT
- stwbrx r5, 0, (r6)
-
- /* set the source address */
- mr r6, r11
- ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
- stwbrx r4, 0, (r6)
-
- /* set the dest address */
- mr r6, r11
- ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
- stwbrx r3, 0, (r6)
-
- /* set the next record pointer */
- li r5, 0
- mr r6, r11
- ori r6, r6, CHANNEL0NEXT_RECORD_POINTER
- stwbrx r5, 0, (r6)
-
- /* set the low control register */
- /* bit 9 is NON chained mode, bit 31 is new style descriptors.
- bit 12 is channel enable */
- ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
- /* 15 shifted by 16 (oris) == bit 31 */
- oris r5, r5, (1 << 15)
- mr r6, r11
- ori r6, r6, CHANNEL0CONTROL
- stwbrx r5, 0, (r6)
-
- blr
-
- /* this waits for the bytecount to return to zero, indicating
- * that the trasfer is complete */
-wait_for_idma_0:
- mr r5, r11
- lis r6, 0xff
- ori r6, r6, 0xffff
- ori r5, r5, CHANNEL0_DMA_BYTE_COUNT
-1: lwbrx r4, 0, (r5)
- and. r4, r4, r6
- bne 1b
-
- blr
-
- /* this turns off channel 0 of the idma engine */
-stop_idma_engine_0:
- /* shut off the DMA engine */
- li r5, 0
- mr r6, r11
- ori r6, r6, CHANNEL0CONTROL
- stwbrx r5, 0, (r6)
-
- blr
-#endif
-
-#ifdef CONFIG_SYS_BOARD_ASM_INIT
- /* NOTE: trashes r3-r7 */
- .globl board_asm_init
-board_asm_init:
- /* just move the GT registers to where they belong */
- lis r3, CONFIG_SYS_DFL_GT_REGS@h
- ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l
- lis r4, CONFIG_SYS_GT_REGS@h
- ori r4, r4, CONFIG_SYS_GT_REGS@l
- li r5, INTERNAL_SPACE_DECODE
-
- /* test to see if we've already moved */
- lwbrx r6, r5, r4
- andi. r6, r6, 0xffff
- /* check loading of R7 is: 0x0F80 should: 0xf800: DONE */
-/* rlwinm r7, r4, 8, 16, 31
- rlwinm r7, r4, 12, 16, 31 */ /* original */
- rlwinm r7, r4, 16, 16, 31
- /* -----------------------------------------------------*/
- cmp cr0, r7, r6
- beqlr
-
- /* nope, have to move the registers */
- lwbrx r6, r5, r3
- andis. r6, r6, 0xffff
- or r6, r6, r7
- stwbrx r6, r5, r3
-
- /* now, poll for the change */
-1: lwbrx r7, r5, r4
- cmp cr0, r7, r6
- bne 1b
-
- /* done! */
- blr
-#endif
-
-/* For use of the debug LEDs */
- .global led_on0_relocated
-led_on0_relocated:
- xor r21, r21, r21
- xor r18, r18, r18
- lis r18, 0xFC80
- ori r18, r18, 0x8000
- stw r21, 0x0(r18)
-/* stw r18, 0x0(r18) */
- sync
- blr
-
- .global led_off0_relocated
-led_off0_relocated:
- xor r21, r21, r21
- xor r18, r18, r18
- lis r18, 0xFC81
- ori r18, r18, 0x4000
- stw r21, 0x0(r18)
-/* stw r18, 0x0(r18) */
- sync
- blr
-
- .global led_on0
-led_on0:
- xor r18, r18, r18
- lis r18, 0x1c80
- ori r18, r18, 0x8000
- stw r18, 0x0(r18)
- sync
- blr
-
- .global led_off0
-led_off0:
- xor r18, r18, r18
- lis r18, 0x1c81
- ori r18, r18, 0x4000
- stw r18, 0x0(r18)
- sync
- blr
-
- .global led_on1
-led_on1:
- xor r18, r18, r18
- lis r18, 0x1c80
- ori r18, r18, 0xc000
- stw r18, 0x0(r18)
- sync
- blr
-
- .global led_off1
-led_off1:
- xor r18, r18, r18
- lis r18, 0x1c81
- ori r18, r18, 0x8000
- stw r18, 0x0(r18)
- sync
- blr
-
- .global led_on2
-led_on2:
- xor r18, r18, r18
- lis r18, 0x1c81
- ori r18, r18, 0x0000
- stw r18, 0x0(r18)
- sync
- blr
-
- .global led_off2
-led_off2:
- xor r18, r18, r18
- lis r18, 0x1c81
- ori r18, r18, 0xc000
- stw r18, 0x0(r18)
- sync
- blr
#include "../include/memory.h"
-#ifdef CONFIG_DB64360
-#include "../db64360/mpsc.h"
-#endif
-
-#ifdef CONFIG_DB64460
-#include "../db64460/mpsc.h"
-#endif
-
#include "ns16550.h"
DECLARE_GLOBAL_DATA_PTR;
--- /dev/null
+--------
+WARNING:
+--------
+This file should contain the bin_hdr generated by the original Marvell
+U-Boot implementation. As this is currently not included in this
+U-Boot version, we have added this placeholder, so that the U-Boot
+image can be generated without errors.
+
+If you have a known to be working bin_hdr for your board, then you
+just need to replace this text file here with the binary header
+and recompile U-Boot.
+
+In a few weeks, mainline U-Boot will get support to generate the
+bin_hdr with the DDR training code itself. By implementing this code
+as SPL U-Boot. Then this file will not be needed any more and will
+get removed.
+
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * main board support/init for the Galileo Eval board DB64360.
- */
-
-#ifndef __64360_H__
-#define __64360_H__
-
-/* CPU Configuration bits */
-#define CPU_CONF_ADDR_MISS_EN (1 << 8)
-#define CPU_CONF_SINGLE_CPU (1 << 11)
-#define CPU_CONF_ENDIANESS (1 << 12)
-#define CPU_CONF_PIPELINE (1 << 13)
-#define CPU_CONF_STOP_RETRY (1 << 17)
-#define CPU_CONF_MULTI_DECODE (1 << 18)
-#define CPU_CONF_DP_VALID (1 << 19)
-#define CPU_CONF_PERR_PROP (1 << 22)
-#define CPU_CONF_AACK_DELAY_2 (1 << 25)
-#define CPU_CONF_AP_VALID (1 << 26)
-#define CPU_CONF_REMAP_WR_DIS (1 << 27)
-
-/* CPU Master Control bits */
-#define CPU_MAST_CTL_ARB_EN (1 << 8)
-#define CPU_MAST_CTL_MASK_BR_1 (1 << 9)
-#define CPU_MAST_CTL_M_WR_TRIG (1 << 10)
-#define CPU_MAST_CTL_M_RD_TRIG (1 << 11)
-#define CPU_MAST_CTL_CLEAN_BLK (1 << 12)
-#define CPU_MAST_CTL_FLUSH_BLK (1 << 13)
-
-#endif /* __64360_H__ */
+++ /dev/null
-if TARGET_DB64360
-
-config SYS_BOARD
- default "db64360"
-
-config SYS_VENDOR
- default "Marvell"
-
-config SYS_CONFIG_NAME
- default "DB64360"
-
-endif
+++ /dev/null
-DB64360 BOARD
-#M: -
-S: Maintained
-F: board/Marvell/db64360/
-F: include/configs/DB64360.h
-F: configs/DB64360_defconfig
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2001
-# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = db64360.o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
- mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
- sdram_init.o ../common/intel_flash.o ../common/misc.o
+++ /dev/null
-This file contains status information for the port of the U-Boot to the Marvell Development Board DB64360.
-
-Author: Ronen Shitrit <rshitrit@il.marvell.com>
-
-This U-Boot version is based on the work of Brian Waite and his team from Sky Computers, THANKS A LOT.
-
-Supported CPU Types :
-+++++++++++++++++++++
- IBM750FX (ver 2.3)
- MPC7455 (ver 2.1)
-
-Supported CPU Cache Library:
-++++++++++++++++++++++++++++
- L1 and L2 only.
-
-CPU Control:
-++++++++++++
- Marvell optimized CPU control settings:
- Big Endian
- Enable CPU pipeline
- Data and address parity checking
- AACK# assert after 2 cycles
-
-U-Boot I/O Interface Support:
-+++++++++++++++++++++++++++++
-- Serial Interface (UART)
- This version of U-Boot supports the SIO U-Boot interface driver, with a PC standard baud rate up to 115200 BPS on the ST16C2552 DUART device located on DB-64360-BP device module.
-- Network Interface
- This LSP supports the following network devices:
- o MV64360 Gigabit Ethernet Controller device
- o Intel 82559 PCI NIC device
-- PCI Interface
- This LSP supports the following capabilities over the Marvell(r) device PCI0/1 units:
- o Local PCI configuration header control.
- o External PCI configuration header control (for other agents on the bus).
- o PCI configuration application. Scans and configures the PCI agents on the bus.
- o PCI Internal Arbiter activation and configuration.
-
-Memory Interface Support:
-+++++++++++++++++++++++++
-- DDR
- o DDR auto-detection and configuration. Enables access up to 256 MB, due to the limitations of using only four Base Address Translations (BATs).
- o Enable DDR ECC in case both DIMM support ECC, and initialize the entire DDR memory by using the idma.
-
-- Devices
- o Initializes the MV64360 device's chip-selects 0-3 to enable access to the boot flash, main flash, real time clock (RTC), and external SRAM.
- o JFFS2
- JFFS2 is a crash/power down safe file system for disk-less embedded devices.
- This version of U-Boot supports scanning a JFFS2 file system on the large flash and loading files from it.
-
-Unsupported Features:
-+++++++++++++++++++++
- Messaging unit - No support for MV64360 Messaging unit.
- Watchdog Timer - No support for MV64360 Watchdog unit.
- L3 cache - No support for L3 cache on MPC7455
- Dual PCU - No support for Dual CPU
- PCI-X was never tested
- IDMA driver - No support for MV64360 IDMA unit.
-
-BSP Special Considerations:
-+++++++++++++++++++++++++++
-- DDR DIMM location: Due to PCI specifications, place the larger DIMM module in the MAIN DIMM slot, in order to have full access from the PCI to the DDR while using both DDR slots.
-- DDR DIMM types: Due to architectural and software limitations, the registration, CAS Latency, and ECC of both DIMMS should be identical.
-
-Test Cases:
-###########
-UART:
-+++++
-Check that the UART baud rate is configured to 57600 and 115200, and check:
- Transmit (to the hyper terminal) and Receive (using the keyboard) using Linux minicom.
- Load S-Record file over the UART using Windows HyperTerminal.
-
-Network:
-++++++++
-Use TFTP application to load a debugged executable and execute it.
-Insert Intel PCI NIC 82557 rev 08 to PCI slots 0-3 Check correct detection of the PCI NIC, correct configuration of the NIC BARs , and load files by using tftp through the PCI NIC.
-
-Memory:
-+++++++
-Test DDR DIMMs on DB-64360-BP. See that Uboot report their correct parameters:
-o 128MB DIMM consist of 16 x 64Mbit devices
-o 128MB DIMM consist of 09 x 128Mbit devices @ 266MHz.
-o 256MB DIMM consist of 16 x 128Mbit devices @ 266MHz.
-o 256MB DIMM consist of 09 x 256Mbit devices @ 400MHz.
-o 512MB DIMM consist of 16 x 256Mbit devices @ 333MHz.
-o 512MB DIMM consist of 18 x 256Mbit devices @ 266MHz.
-o GigaB DIMM consist of 36 x 256Mbit devices @ 266MHz registered
-
-For each chip select device perform data access to verify its accessibility.
-
-Create a JFFS2 on the large flash through the Linux holding few files, few dirs and a uImage.
-Load the U-Boot and:
-use the ls command to check correct scan of the JFFS2 on the large flash.
-Use the floads command to copy the uImage from the JFFS2 on the large flash to the DIMM SDRAM, and boot the uImage.
-
-PCI:
-++++
-1)Insert different PCI cards:
-Galileo 64120A rev 10 and 12, Intel Nic 82557 rev 08 and Real Tech NIC 8139 rev10
-on different slots (0-3) of the PCI and check:
-o Correct detection of the PCI devices.
-o Correct address mapping of the PCI devices.
-2)Insert Galileo 64120A rev 10 on different slots (0-3) of the PCI and check writing and reading pci configuration register through the U-Boot.
-
-Booting Linux through the U-Boot (use the bootargs of the U-Boot as a bootcmd to the kernal)
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
- */
-
-/*
- * db64360.c - main board support/init for the Galileo Eval board.
- */
-
-#include <common.h>
-#include <74xx_7xx.h>
-#include "../include/memory.h"
-#include "../include/pci.h"
-#include "../include/mv_gen_reg.h"
-#include <net.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-
-#include "eth.h"
-#include "mpsc.h"
-#include "i2c.h"
-#include "64360.h"
-#include "mv_regs.h"
-
-#undef DEBUG
-/*#define DEBUG */
-
-#define MAP_PCI
-
-#ifdef DEBUG
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-/* ------------------------------------------------------------------------- */
-
-/* this is the current GT register space location */
-/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
-
-/* Unfortunately, we cant change it while we are in flash, so we initialize it
- * to the "final" value. This means that any debug_led calls before
- * board_early_init_f wont work right (like in cpu_init_f).
- * See also my_remap_gt_regs below. (NTL)
- */
-
-void board_prebootm_init (void);
-unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
-int display_mem_map (void);
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * This is a version of the GT register space remapping function that
- * doesn't touch globals (meaning, it's ok to run from flash.)
- *
- * Unfortunately, this has the side effect that a writable
- * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
- */
-
-void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
-{
- u32 temp;
-
- /* check and see if it's already moved */
-
-/* original ppcboot 1.1.6 source
-
- temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
- if ((temp & 0xffff) == new_loc >> 20)
- return;
-
- temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
- 0xffff0000) | (new_loc >> 20);
-
- out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
-
- while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
-original ppcboot 1.1.6 source end */
-
- temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
- if ((temp & 0xffff) == new_loc >> 16)
- return;
-
- temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
- 0xffff0000) | (new_loc >> 16);
-
- out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
-
- while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
-}
-
-#ifdef CONFIG_PCI
-
-static void gt_pci_config (void)
-{
- unsigned int stat;
- unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
-
- /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
- * config registers by writing ones to the bus and device.
- * We then update the Virtual register with the correct value for the bus and device.
- */
- if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
- GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
-
- GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
-
- GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
- GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
- (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
-
- }
- if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
- GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
- GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
-
- GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
- GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
- (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
- }
-
- /* Enable master */
- PCI_MASTER_ENABLE (0, SELF);
- PCI_MASTER_ENABLE (1, SELF);
-
- /* Enable PCI0/1 Mem0 and IO 0 disable all others */
- GT_REG_READ (BASE_ADDR_ENABLE, &stat);
- stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
- <<
- 18);
- stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
- GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
-
- /* ronen- add write to pci remap registers for 64460.
- in 64360 when writing to pci base go and overide remap automaticaly,
- in 64460 it doesn't */
- GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16);
- GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16);
- GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
-
- GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
-
- GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16);
- GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16);
- GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
-
- GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
-
- /* PCI interface settings */
- /* Timeout set to retry forever */
- GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
- GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
-
- /* ronen - enable only CS0 and Internal reg!! */
- GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
- GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
-
-/*ronen update the pci internal registers base address.*/
-#ifdef MAP_PCI
- for (stat = 0; stat <= PCI_HOST1; stat++)
- pciWriteConfigReg (stat,
- PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
- SELF, CONFIG_SYS_GT_REGS);
-#endif
-
-}
-#endif
-
-/* Setup CPU interface paramaters */
-static void gt_cpu_config (void)
-{
- cpu_t cpu = get_cpu_type ();
- ulong tmp;
-
- /* cpu configuration register */
- tmp = GTREGREAD (CPU_CONFIGURATION);
-
- /* set the SINGLE_CPU bit see MV64360 P.399 */
-#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
- tmp |= CPU_CONF_SINGLE_CPU;
-#endif
-
- tmp &= ~CPU_CONF_AACK_DELAY_2;
-
- tmp |= CPU_CONF_DP_VALID;
- tmp |= CPU_CONF_AP_VALID;
-
- tmp |= CPU_CONF_PIPELINE;
-
- GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */
-
- /* CPU master control register */
- tmp = GTREGREAD (CPU_MASTER_CONTROL);
-
- tmp |= CPU_MAST_CTL_ARB_EN;
-
- if ((cpu == CPU_7400) ||
- (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
-
- tmp |= CPU_MAST_CTL_CLEAN_BLK;
- tmp |= CPU_MAST_CTL_FLUSH_BLK;
-
- } else {
- /* cleanblock must be cleared for CPUs
- * that do not support this command (603e, 750)
- * see Res#1 */
- tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
- tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
- }
- GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
-}
-
-/*
- * board_early_init_f.
- *
- * set up gal. device mappings, etc.
- */
-int board_early_init_f (void)
-{
- uchar sram_boot = 0;
-
- /*
- * set up the GT the way the kernel wants it
- * the call to move the GT register space will obviously
- * fail if it has already been done, but we're going to assume
- * that if it's not at the power-on location, it's where we put
- * it last time. (huber)
- */
-
- my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
-
- /* No PCI in first release of Port To_do: enable it. */
-#ifdef CONFIG_PCI
- gt_pci_config ();
-#endif
- /* mask all external interrupt sources */
- GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
- GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
- /* new in MV6436x */
- GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
- GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
- /* --------------------- */
- GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
- GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
- GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
- GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
- /* does not exist in MV6436x
- GT_REG_WRITE(CPU_INT_0_MASK, 0);
- GT_REG_WRITE(CPU_INT_1_MASK, 0);
- GT_REG_WRITE(CPU_INT_2_MASK, 0);
- GT_REG_WRITE(CPU_INT_3_MASK, 0);
- --------------------- */
-
-
- /* ----- DEVICE BUS SETTINGS ------ */
-
- /*
- * EVB
- * 0 - SRAM ????
- * 1 - RTC ????
- * 2 - UART ????
- * 3 - Flash checked 32Bit Intel Strata
- * boot - BootCS checked 8Bit 29LV040B
- *
- * Zuma
- * 0 - Flash
- * boot - BootCS
- */
-
- /*
- * the dual 7450 module requires burst access to the boot
- * device, so the serial rom copies the boot device to the
- * on-board sram on the eval board, and updates the correct
- * registers to boot from the sram. (device0)
- */
- if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE)
- sram_boot = 1;
- if (!sram_boot)
- memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
-
- memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
- memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
- memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
-
-
- /* configure device timing */
-#ifdef CONFIG_SYS_DEV0_PAR /* set port parameters for SRAM device module access */
- if (!sram_boot)
- GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
-#endif
-
-#ifdef CONFIG_SYS_DEV1_PAR /* set port parameters for RTC device module access */
- GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
-#endif
-#ifdef CONFIG_SYS_DEV2_PAR /* set port parameters for DUART device module access */
- GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
-#endif
-
-#ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */
- /* detect if we are booting from the 32 bit flash */
- if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
- /* 32 bit boot flash */
- GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
- GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
- CONFIG_SYS_32BIT_BOOT_PAR);
- } else {
- /* 8 bit boot flash */
- GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
- GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
- }
-#else
- /* 8 bit boot flash only */
-/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
-#endif
-
-
- gt_cpu_config ();
-
- /* MPP setup */
- GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
- GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
- GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
- GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
-
- GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
- DEBUG_LED0_ON ();
- DEBUG_LED1_ON ();
- DEBUG_LED2_ON ();
-
- return 0;
-}
-
-/* various things to do after relocation */
-
-int misc_init_r ()
-{
- icache_enable ();
-#ifdef CONFIG_SYS_L2
- l2cache_enable ();
-#endif
-#ifdef CONFIG_MPSC
-
- mpsc_sdma_init ();
- mpsc_init2 ();
-#endif
-
-#if 0
- /* disable the dcache and MMU */
- dcache_lock ();
-#endif
- return 0;
-}
-
-void after_reloc (ulong dest_addr, gd_t * gd)
-{
- /* check to see if we booted from the sram. If so, move things
- * back to the way they should be. (we're running from main
- * memory at this point now */
- if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) {
- memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
- memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M);
- }
- display_mem_map ();
- /* now, jump to the main ppcboot board init code */
- board_init_r (gd, dest_addr);
- /* NOTREACHED */
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- *
- * right now, assume borad type. (there is just one...after all)
- */
-
-int checkboard (void)
-{
- int l_type = 0;
-
- printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
- return (l_type);
-}
-
-/* utility functions */
-void debug_led (int led, int mode)
-{
- volatile int *addr = 0;
- __maybe_unused int dummy;
-
- if (mode == 1) {
- switch (led) {
- case 0:
- addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
- 0x08000);
- break;
-
- case 1:
- addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
- 0x0c000);
- break;
-
- case 2:
- addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
- 0x10000);
- break;
- }
- } else if (mode == 0) {
- switch (led) {
- case 0:
- addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
- 0x14000);
- break;
-
- case 1:
- addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
- 0x18000);
- break;
-
- case 2:
- addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
- 0x1c000);
- break;
- }
- }
-
- dummy = *addr;
-}
-
-int display_mem_map (void)
-{
- int i, j;
- unsigned int base, size, width;
-
- /* SDRAM */
- printf ("SD (DDR) RAM\n");
- for (i = 0; i <= BANK3; i++) {
- base = memoryGetBankBaseAddress (i);
- size = memoryGetBankSize (i);
- if (size != 0) {
- printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
- i, base, size >> 20);
- }
- }
-
- /* CPU's PCI windows */
- for (i = 0; i <= PCI_HOST1; i++) {
- printf ("\nCPU's PCI %d windows\n", i);
- base = pciGetSpaceBase (i, PCI_IO);
- size = pciGetSpaceSize (i, PCI_IO);
- printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base,
- size >> 20);
- for (j = 0;
- j <=
- PCI_REGION0
- /*ronen currently only first PCI MEM is used 3 */ ;
- j++) {
- base = pciGetSpaceBase (i, j);
- size = pciGetSpaceSize (i, j);
- printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
- }
- }
-
- /* Devices */
- printf ("\nDEVICES\n");
- for (i = 0; i <= DEVICE3; i++) {
- base = memoryGetDeviceBaseAddress (i);
- size = memoryGetDeviceSize (i);
- width = memoryGetDeviceWidth (i) * 8;
- printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
- if (i == 0)
- printf ("\t- EXT SRAM (actual - 1M)\n");
- else if (i == 1)
- printf ("\t- RTC\n");
- else if (i == 2)
- printf ("\t- UART\n");
- else
- printf ("\t- LARGE FLASH\n");
- }
-
- /* Bootrom */
- base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */
- size = memoryGetDeviceSize (BOOT_DEVICE);
- width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
- printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\n",
- base, size >> 20, width);
- return (0);
-}
-
-/* DRAM check routines copied from gw8260 */
-
-#if defined (CONFIG_SYS_DRAM_TEST)
-
-/*********************************************************************/
-/* NAME: move64() - moves a double word (64-bit) */
-/* */
-/* DESCRIPTION: */
-/* this function performs a double word move from the data at */
-/* the source pointer to the location at the destination pointer. */
-/* */
-/* INPUTS: */
-/* unsigned long long *src - pointer to data to move */
-/* */
-/* OUTPUTS: */
-/* unsigned long long *dest - pointer to locate to move data */
-/* */
-/* RETURNS: */
-/* None */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* May cloober fr0. */
-/* */
-/*********************************************************************/
-static void move64 (unsigned long long *src, unsigned long long *dest)
-{
- asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
- "stfd 0, 0(4)" /* *dest = fpr0 */
- : : : "fr0"); /* Clobbers fr0 */
- return;
-}
-
-
-#if defined (CONFIG_SYS_DRAM_TEST_DATA)
-
-unsigned long long pattern[] = {
- 0xaaaaaaaaaaaaaaaaULL,
- 0xccccccccccccccccULL,
- 0xf0f0f0f0f0f0f0f0ULL,
- 0xff00ff00ff00ff00ULL,
- 0xffff0000ffff0000ULL,
- 0xffffffff00000000ULL,
- 0x00000000ffffffffULL,
- 0x0000ffff0000ffffULL,
- 0x00ff00ff00ff00ffULL,
- 0x0f0f0f0f0f0f0f0fULL,
- 0x3333333333333333ULL,
- 0x5555555555555555ULL,
-};
-
-/*********************************************************************/
-/* NAME: mem_test_data() - test data lines for shorts and opens */
-/* */
-/* DESCRIPTION: */
-/* Tests data lines for shorts and opens by forcing adjacent data */
-/* to opposite states. Because the data lines could be routed in */
-/* an arbitrary manner the must ensure test patterns ensure that */
-/* every case is tested. By using the following series of binary */
-/* patterns every combination of adjacent bits is test regardless */
-/* of routing. */
-/* */
-/* ...101010101010101010101010 */
-/* ...110011001100110011001100 */
-/* ...111100001111000011110000 */
-/* ...111111110000000011111111 */
-/* */
-/* Carrying this out, gives us six hex patterns as follows: */
-/* */
-/* 0xaaaaaaaaaaaaaaaa */
-/* 0xcccccccccccccccc */
-/* 0xf0f0f0f0f0f0f0f0 */
-/* 0xff00ff00ff00ff00 */
-/* 0xffff0000ffff0000 */
-/* 0xffffffff00000000 */
-/* */
-/* The number test patterns will always be given by: */
-/* */
-/* log(base 2)(number data bits) = log2 (64) = 6 */
-/* */
-/* To test for short and opens to other signals on our boards. we */
-/* simply */
-/* test with the 1's complemnt of the paterns as well. */
-/* */
-/* OUTPUTS: */
-/* Displays failing test pattern */
-/* */
-/* RETURNS: */
-/* 0 - Passed test */
-/* 1 - Failed test */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* Assumes only one one SDRAM bank */
-/* */
-/*********************************************************************/
-int mem_test_data (void)
-{
- unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
- unsigned long long temp64 = 0;
- int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
- int i;
- unsigned int hi, lo;
-
- for (i = 0; i < num_patterns; i++) {
- move64 (&(pattern[i]), pmem);
- move64 (pmem, &temp64);
-
- /* hi = (temp64>>32) & 0xffffffff; */
- /* lo = temp64 & 0xffffffff; */
- /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
-
- hi = (pattern[i] >> 32) & 0xffffffff;
- lo = pattern[i] & 0xffffffff;
- /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
-
- if (temp64 != pattern[i]) {
- printf ("\n Data Test Failed, pattern 0x%08x%08x",
- hi, lo);
- return 1;
- }
- }
-
- return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_DATA */
-
-#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
-/*********************************************************************/
-/* NAME: mem_test_address() - test address lines */
-/* */
-/* DESCRIPTION: */
-/* This function performs a test to verify that each word im */
-/* memory is uniquly addressable. The test sequence is as follows: */
-/* */
-/* 1) write the address of each word to each word. */
-/* 2) verify that each location equals its address */
-/* */
-/* OUTPUTS: */
-/* Displays failing test pattern and address */
-/* */
-/* RETURNS: */
-/* 0 - Passed test */
-/* 1 - Failed test */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/* */
-/*********************************************************************/
-int mem_test_address (void)
-{
- volatile unsigned int *pmem =
- (volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
- const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
- unsigned int i;
-
- /* write address to each location */
- for (i = 0; i < size; i++) {
- pmem[i] = i;
- }
-
- /* verify each loaction */
- for (i = 0; i < size; i++) {
- if (pmem[i] != i) {
- printf ("\n Address Test Failed at 0x%x", i);
- return 1;
- }
- }
- return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
-
-#if defined (CONFIG_SYS_DRAM_TEST_WALK)
-/*********************************************************************/
-/* NAME: mem_march() - memory march */
-/* */
-/* DESCRIPTION: */
-/* Marches up through memory. At each location verifies rmask if */
-/* read = 1. At each location write wmask if write = 1. Displays */
-/* failing address and pattern. */
-/* */
-/* INPUTS: */
-/* volatile unsigned long long * base - start address of test */
-/* unsigned int size - number of dwords(64-bit) to test */
-/* unsigned long long rmask - read verify mask */
-/* unsigned long long wmask - wrtie verify mask */
-/* short read - verifies rmask if read = 1 */
-/* short write - writes wmask if write = 1 */
-/* */
-/* OUTPUTS: */
-/* Displays failing test pattern and address */
-/* */
-/* RETURNS: */
-/* 0 - Passed test */
-/* 1 - Failed test */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/* */
-/*********************************************************************/
-int mem_march (volatile unsigned long long *base,
- unsigned int size,
- unsigned long long rmask,
- unsigned long long wmask, short read, short write)
-{
- unsigned int i;
- unsigned long long temp = 0;
- unsigned int hitemp, lotemp, himask, lomask;
-
- for (i = 0; i < size; i++) {
- if (read != 0) {
- /* temp = base[i]; */
- move64 ((unsigned long long *) &(base[i]), &temp);
- if (rmask != temp) {
- hitemp = (temp >> 32) & 0xffffffff;
- lotemp = temp & 0xffffffff;
- himask = (rmask >> 32) & 0xffffffff;
- lomask = rmask & 0xffffffff;
-
- printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
- return 1;
- }
- }
- if (write != 0) {
- /* base[i] = wmask; */
- move64 (&wmask, (unsigned long long *) &(base[i]));
- }
- }
- return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_WALK */
-
-/*********************************************************************/
-/* NAME: mem_test_walk() - a simple walking ones test */
-/* */
-/* DESCRIPTION: */
-/* Performs a walking ones through entire physical memory. The */
-/* test uses as series of memory marches, mem_march(), to verify */
-/* and write the test patterns to memory. The test sequence is as */
-/* follows: */
-/* 1) march writing 0000...0001 */
-/* 2) march verifying 0000...0001 , writing 0000...0010 */
-/* 3) repeat step 2 shifting masks left 1 bit each time unitl */
-/* the write mask equals 1000...0000 */
-/* 4) march verifying 1000...0000 */
-/* The test fails if any of the memory marches return a failure. */
-/* */
-/* OUTPUTS: */
-/* Displays which pass on the memory test is executing */
-/* */
-/* RETURNS: */
-/* 0 - Passed test */
-/* 1 - Failed test */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/* */
-/*********************************************************************/
-int mem_test_walk (void)
-{
- unsigned long long mask;
- volatile unsigned long long *pmem =
- (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
- const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
-
- unsigned int i;
-
- mask = 0x01;
-
- printf ("Initial Pass");
- mem_march (pmem, size, 0x0, 0x1, 0, 1);
-
- printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
- printf (" ");
- printf (" ");
- printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
-
- for (i = 0; i < 63; i++) {
- printf ("Pass %2d", i + 2);
- if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
- /*printf("mask: 0x%x, pass: %d, ", mask, i); */
- return 1;
- }
- mask = mask << 1;
- printf ("\b\b\b\b\b\b\b");
- }
-
- printf ("Last Pass");
- if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
- /* printf("mask: 0x%x", mask); */
- return 1;
- }
- printf ("\b\b\b\b\b\b\b\b\b");
- printf (" ");
- printf ("\b\b\b\b\b\b\b\b\b");
-
- return 0;
-}
-
-/*********************************************************************/
-/* NAME: testdram() - calls any enabled memory tests */
-/* */
-/* DESCRIPTION: */
-/* Runs memory tests if the environment test variables are set to */
-/* 'y'. */
-/* */
-/* INPUTS: */
-/* testdramdata - If set to 'y', data test is run. */
-/* testdramaddress - If set to 'y', address test is run. */
-/* testdramwalk - If set to 'y', walking ones test is run */
-/* */
-/* OUTPUTS: */
-/* None */
-/* */
-/* RETURNS: */
-/* 0 - Passed test */
-/* 1 - Failed test */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/* */
-/*********************************************************************/
-int testdram (void)
-{
- int rundata, runaddress, runwalk;
-
- rundata = getenv_yesno("testdramdata") == 1;
- runaddress = getenv_yesno("testdramaddress") == 1;
- runwalk = getenv_yesno("testdramwalk") == 1;
-
-/* rundata = 1; */
-/* runaddress = 0; */
-/* runwalk = 0; */
-
- if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
- printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
- }
-#ifdef CONFIG_SYS_DRAM_TEST_DATA
- if (rundata == 1) {
- printf ("Test DATA ... ");
- if (mem_test_data () == 1) {
- printf ("failed \n");
- return 1;
- } else
- printf ("ok \n");
- }
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
- if (runaddress == 1) {
- printf ("Test ADDRESS ... ");
- if (mem_test_address () == 1) {
- printf ("failed \n");
- return 1;
- } else
- printf ("ok \n");
- }
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_WALK
- if (runwalk == 1) {
- printf ("Test WALKING ONEs ... ");
- if (mem_test_walk () == 1) {
- printf ("failed \n");
- return 1;
- } else
- printf ("ok \n");
- }
-#endif
- if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
- printf ("passed\n");
- }
- return 0;
-
-}
-#endif /* CONFIG_SYS_DRAM_TEST */
-
-/* ronen - the below functions are used by the bootm function */
-/* - we map the base register to fbe00000 (same mapping as in the LSP) */
-/* - we turn off the RX gig dmas - to prevent the dma from overunning */
-/* the kernel data areas. */
-/* - we diable and invalidate the icache and dcache. */
-void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
-{
- u32 temp;
-
- temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
- if ((temp & 0xffff) == new_loc >> 16)
- return;
-
- temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
- 0xffff0000) | (new_loc >> 16);
-
- out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
-
- while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
- new_loc |
- (INTERNAL_SPACE_DECODE)))))
- != temp);
-
-}
-
-void board_prebootm_init ()
-{
-
-/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
- GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
-
-/* Stop GigE Rx DMA engines */
- GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
- GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00);
-/* MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0x0000ff00); */
-
-/* Relocate MV64360 internal regs */
- my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM);
-
- icache_disable ();
- dcache_disable ();
-}
-
-int board_eth_init(bd_t *bis)
-{
- int ret;
- ret = pci_eth_init(bis);
- if (!ret)
- ret = mv6436x_eth_initialize(bis);
- return ret;
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * eth.h - header file for the polled mode GT ethernet driver
- */
-
-#ifndef __EVB64360_ETH_H__
-#define __EVB64360_ETH_H__
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-#include <common.h>
-
-
-int db64360_eth0_poll(void);
-int db64360_eth0_transmit(unsigned int s, volatile char *p);
-void db64360_eth0_disable(void);
-bool network_start(bd_t *bis);
-
-int mv6436x_eth_initialize(bd_t *);
-
-#endif /* __EVB64360_ETH_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*************************************************************************
- * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
- *
- ************************************************************************/
-
-/*
- * mpsc.c - driver for console over the MPSC.
- */
-
-
-#include <common.h>
-#include <config.h>
-#include <asm/cache.h>
-
-#include <malloc.h>
-#include "mpsc.h"
-
-#include "mv_regs.h"
-
-#include "../include/memory.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Define this if you wish to use the MPSC as a register based UART.
- * This will force the serial port to not use the SDMA engine at all.
- */
-#undef CONFIG_MPSC_DEBUG_PORT
-
-
-int (*mpsc_putchar) (char ch) = mpsc_putchar_early;
-char (*mpsc_getchar) (void) = mpsc_getchar_debug;
-int (*mpsc_test_char) (void) = mpsc_test_char_debug;
-
-
-static volatile unsigned int *rx_desc_base = NULL;
-static unsigned int rx_desc_index = 0;
-static volatile unsigned int *tx_desc_base = NULL;
-static unsigned int tx_desc_index = 0;
-
-/* local function declarations */
-static int galmpsc_connect (int channel, int connect);
-static int galmpsc_route_rx_clock (int channel, int brg);
-static int galmpsc_route_tx_clock (int channel, int brg);
-static int galmpsc_write_config_regs (int mpsc, int mode);
-static int galmpsc_config_channel_regs (int mpsc);
-static int galmpsc_set_char_length (int mpsc, int value);
-static int galmpsc_set_stop_bit_length (int mpsc, int value);
-static int galmpsc_set_parity (int mpsc, int value);
-static int galmpsc_enter_hunt (int mpsc);
-static int galmpsc_set_brkcnt (int mpsc, int value);
-static int galmpsc_set_tcschar (int mpsc, int value);
-static int galmpsc_set_snoop (int mpsc, int value);
-static int galmpsc_shutdown (int mpsc);
-
-static int galsdma_set_RFT (int channel);
-static int galsdma_set_SFM (int channel);
-static int galsdma_set_rxle (int channel);
-static int galsdma_set_txle (int channel);
-static int galsdma_set_burstsize (int channel, unsigned int value);
-static int galsdma_set_RC (int channel, unsigned int value);
-
-static int galbrg_set_CDV (int channel, int value);
-static int galbrg_enable (int channel);
-static int galbrg_disable (int channel);
-static int galbrg_set_clksrc (int channel, int value);
-static int galbrg_set_CUV (int channel, int value);
-
-static void galsdma_enable_rx (void);
-static int galsdma_set_mem_space (unsigned int memSpace,
- unsigned int memSpaceTarget,
- unsigned int memSpaceAttr,
- unsigned int baseAddress,
- unsigned int size);
-
-
-#define SOFTWARE_CACHE_MANAGEMENT
-
-#ifdef SOFTWARE_CACHE_MANAGEMENT
-#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
-#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
-#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
-#else
-#define FLUSH_DCACHE(a,b)
-#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
-#define INVALIDATE_DCACHE(a,b)
-#endif
-
-#ifdef CONFIG_MPSC_DEBUG_PORT
-static void mpsc_debug_init (void)
-{
-
- volatile unsigned int temp;
-
- /* Clear the CFR (CHR4) */
- /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
- temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
- temp &= 0xffffff00;
- temp |= BIT29;
- GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
- temp);
-
- /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */
- temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP));
- temp |= (BIT12 | BIT15);
- GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP),
- temp);
-
- /* Set int mask */
- temp = GTREGREAD (GALMPSC_0_INT_MASK);
- temp |= BIT6;
- GT_REG_WRITE (GALMPSC_0_INT_MASK, temp);
-}
-#endif
-
-char mpsc_getchar_debug (void)
-{
- volatile int temp;
- volatile unsigned int cause;
-
- cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
- while ((cause & BIT6) == 0) {
- cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
- }
-
- temp = GTREGREAD (GALMPSC_CHANNELREG_10 +
- (CHANNEL * GALMPSC_REG_GAP));
- /* By writing 1's to the set bits, the register is cleared */
- GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP),
- temp);
- GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6);
- return (temp >> 16) & 0xff;
-}
-
-/* special function for running out of flash. doesn't modify any
- * global variables [josh] */
-int mpsc_putchar_early (char ch)
-{
- int mpsc = CHANNEL;
- int temp =
- GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
- galmpsc_set_tcschar (mpsc, ch);
- GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP),
- temp | 0x200);
-
-#define MAGIC_FACTOR (10*1000000)
-
- udelay (MAGIC_FACTOR / gd->baudrate);
- return 0;
-}
-
-/* This is used after relocation, see serial.c and mpsc_init2 */
-static int mpsc_putchar_sdma (char ch)
-{
- volatile unsigned int *p;
- unsigned int temp;
-
-
- /* align the descriptor */
- p = tx_desc_base;
- memset ((void *) p, 0, 8 * sizeof (unsigned int));
-
- /* fill one 64 bit buffer */
- /* word swap, pad with 0 */
- p[4] = 0; /* x */
- p[5] = (unsigned int) ch; /* x */
-
- /* CHANGED completely according to GT64260A dox - NTL */
- p[0] = 0x00010001; /* 0 */
- p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* 4 */
- p[2] = 0; /* 8 */
- p[3] = (unsigned int) &p[4]; /* c */
-
-#if 0
- p[9] = DESC_FIRST | DESC_LAST;
- p[10] = (unsigned int) &p[0];
- p[11] = (unsigned int) &p[12];
-#endif
-
- FLUSH_DCACHE (&p[0], &p[8]);
-
- GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
- (unsigned int) &p[0]);
- GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
- (unsigned int) &p[0]);
-
- temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
- temp |= (TX_DEMAND | TX_STOP);
- GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
-
- INVALIDATE_DCACHE (&p[1], &p[2]);
-
- while (p[1] & DESC_OWNER_BIT) {
- udelay (100);
- INVALIDATE_DCACHE (&p[1], &p[2]);
- }
- return 0;
-}
-
-char mpsc_getchar_sdma (void)
-{
- static unsigned int done = 0;
- volatile char ch;
- unsigned int len = 0, idx = 0, temp;
-
- volatile unsigned int *p;
-
-
- do {
- p = &rx_desc_base[rx_desc_index * 8];
-
- INVALIDATE_DCACHE (&p[0], &p[1]);
- /* Wait for character */
- while (p[1] & DESC_OWNER_BIT) {
- udelay (100);
- INVALIDATE_DCACHE (&p[0], &p[1]);
- }
-
- /* Handle error case */
- if (p[1] & (1 << 15)) {
- printf ("oops, error: %08x\n", p[1]);
-
- temp = GTREGREAD (GALMPSC_CHANNELREG_2 +
- (CHANNEL * GALMPSC_REG_GAP));
- temp |= (1 << 23);
- GT_REG_WRITE (GALMPSC_CHANNELREG_2 +
- (CHANNEL * GALMPSC_REG_GAP), temp);
-
- /* Can't poll on abort bit, so we just wait. */
- udelay (100);
-
- galsdma_enable_rx ();
- }
-
- /* Number of bytes left in this descriptor */
- len = p[0] & 0xffff;
-
- if (len) {
- /* Where to look */
- idx = 5;
- if (done > 3)
- idx = 4;
- if (done > 7)
- idx = 7;
- if (done > 11)
- idx = 6;
-
- INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
- ch = p[idx] & 0xff;
- done++;
- }
-
- if (done < len) {
- /* this descriptor has more bytes still
- * shift down the char we just read, and leave the
- * buffer in place for the next time around
- */
- p[idx] = p[idx] >> 8;
- FLUSH_DCACHE (&p[idx], &p[idx + 1]);
- }
-
- if (done == len) {
- /* nothing left in this descriptor.
- * go to next one
- */
- p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
- p[0] = 0x00100000;
- FLUSH_DCACHE (&p[0], &p[1]);
- /* Next descriptor */
- rx_desc_index = (rx_desc_index + 1) % RX_DESC;
- done = 0;
- }
- } while (len == 0); /* galileo bug.. len might be zero */
-
- return ch;
-}
-
-
-int mpsc_test_char_debug (void)
-{
- if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0)
- return 0;
- else {
- return 1;
- }
-}
-
-
-int mpsc_test_char_sdma (void)
-{
- volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8];
-
- INVALIDATE_DCACHE (&p[1], &p[2]);
-
- if (p[1] & DESC_OWNER_BIT)
- return 0;
- else
- return 1;
-}
-
-int mpsc_init (int baud)
-{
- /* BRG CONFIG */
- galbrg_set_baudrate (CHANNEL, baud);
- galbrg_set_clksrc (CHANNEL, 8); /* set source=Tclk */
- galbrg_set_CUV (CHANNEL, 0); /* set up CountUpValue */
- galbrg_enable (CHANNEL); /* Enable BRG */
-
- /* Set up clock routing */
- galmpsc_connect (CHANNEL, GALMPSC_CONNECT); /* connect it */
-
- galmpsc_route_rx_clock (CHANNEL, CHANNEL); /* chosse BRG0 for Rx */
- galmpsc_route_tx_clock (CHANNEL, CHANNEL); /* chose BRG0 for Tx */
-
- /* reset MPSC state */
- galmpsc_shutdown (CHANNEL);
-
- /* SDMA CONFIG */
- galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8); /* in 64 bit words (8 bytes) */
- galsdma_set_txle (CHANNEL);
- galsdma_set_rxle (CHANNEL);
- galsdma_set_RC (CHANNEL, 0xf);
- galsdma_set_SFM (CHANNEL);
- galsdma_set_RFT (CHANNEL);
-
- /* MPSC CONFIG */
- galmpsc_write_config_regs (CHANNEL, GALMPSC_UART);
- galmpsc_config_channel_regs (CHANNEL);
- galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */
- galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE); /* N */
- galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */
-
-#ifdef CONFIG_MPSC_DEBUG_PORT
- mpsc_debug_init ();
-#endif
-
- /* COMM_MPSC CONFIG */
-#ifdef SOFTWARE_CACHE_MANAGEMENT
- galmpsc_set_snoop (CHANNEL, 0); /* disable snoop */
-#else
- galmpsc_set_snoop (CHANNEL, 1); /* enable snoop */
-#endif
-
- return 0;
-}
-
-
-void mpsc_sdma_init (void)
-{
-/* Setup SDMA channel0 SDMA_CONFIG_REG*/
- GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff);
-
-/* Enable MPSC-Window0 for DRAM Bank0 */
- if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT,
- MV64360_SDMA_DRAM_CS_0_TARGET,
- 0,
- memoryGetBankBaseAddress
- (CS_0_LOW_DECODE_ADDRESS),
- memoryGetBankSize (BANK0)) != true)
- printf ("%s: SDMA_Window0 memory setup failed !!! \n",
- __FUNCTION__);
-
-
-/* Disable MPSC-Window1 */
- if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_1_BIT,
- MV64360_SDMA_DRAM_CS_0_TARGET,
- 0,
- memoryGetBankBaseAddress
- (CS_1_LOW_DECODE_ADDRESS),
- memoryGetBankSize (BANK3)) != true)
- printf ("%s: SDMA_Window1 memory setup failed !!! \n",
- __FUNCTION__);
-
-
-/* Disable MPSC-Window2 */
- if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_2_BIT,
- MV64360_SDMA_DRAM_CS_0_TARGET,
- 0,
- memoryGetBankBaseAddress
- (CS_2_LOW_DECODE_ADDRESS),
- memoryGetBankSize (BANK3)) != true)
- printf ("%s: SDMA_Window2 memory setup failed !!! \n",
- __FUNCTION__);
-
-
-/* Disable MPSC-Window3 */
- if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_3_BIT,
- MV64360_SDMA_DRAM_CS_0_TARGET,
- 0,
- memoryGetBankBaseAddress
- (CS_3_LOW_DECODE_ADDRESS),
- memoryGetBankSize (BANK3)) != true)
- printf ("%s: SDMA_Window3 memory setup failed !!! \n",
- __FUNCTION__);
-
-/* Setup MPSC0 access mode Window0 full access */
- GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG,
- (MV64360_SDMA_WIN_ACCESS_FULL <<
- (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
-
-/* Setup MPSC1 access mode Window1 full access */
- GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG,
- (MV64360_SDMA_WIN_ACCESS_FULL <<
- (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
-
-/* Setup MPSC internal address space base address */
- GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
-
-/* no high address remap*/
- GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
- GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00);
-
-/* clear interrupt cause register for MPSC (fault register)*/
- GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00);
-}
-
-
-void mpsc_init2 (void)
-{
- int i;
-
-#ifndef CONFIG_MPSC_DEBUG_PORT
- mpsc_putchar = mpsc_putchar_sdma;
- mpsc_getchar = mpsc_getchar_sdma;
- mpsc_test_char = mpsc_test_char_sdma;
-#endif
- /* RX descriptors */
- rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) *
- sizeof (unsigned int));
-
- /* align descriptors */
- rx_desc_base = (unsigned int *)
- (((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0);
-
- rx_desc_index = 0;
-
- memset ((void *) rx_desc_base, 0,
- (RX_DESC * 8) * sizeof (unsigned int));
-
- for (i = 0; i < RX_DESC; i++) {
- rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4]; /* Buffer */
- rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8]; /* Next descriptor */
- rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* Command & control */
- rx_desc_base[i * 8] = 0x00100000;
- }
- rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0];
-
- FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]);
- GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
- (unsigned int) &rx_desc_base[0]);
-
- /* TX descriptors */
- tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) *
- sizeof (unsigned int));
-
- /* align descriptors */
- tx_desc_base = (unsigned int *)
- (((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0);
-
- tx_desc_index = -1;
-
- memset ((void *) tx_desc_base, 0,
- (TX_DESC * 8) * sizeof (unsigned int));
-
- for (i = 0; i < TX_DESC; i++) {
- tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323;
- tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323;
- tx_desc_base[i * 8 + 3] =
- (unsigned int) &tx_desc_base[i * 8 + 4];
- tx_desc_base[i * 8 + 2] =
- (unsigned int) &tx_desc_base[(i + 1) * 8];
- tx_desc_base[i * 8 + 1] =
- DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
-
- /* set sbytecnt and shadow byte cnt to 1 */
- tx_desc_base[i * 8] = 0x00010001;
- }
- tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0];
-
- FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]);
-
- udelay (100);
-
- galsdma_enable_rx ();
-
- return;
-}
-
-int galbrg_set_baudrate (int channel, int rate)
-{
- int clock;
-
- galbrg_disable (channel); /*ok */
-
-#ifdef ZUMA_NTL
- /* from tclk */
- clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
-#else
- clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
-#endif
-
- galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */
-
- galbrg_enable (channel);
-
- gd->baudrate = rate;
-
- return 0;
-}
-
-/* ------------------------------------------------------------------ */
-
-/* Below are all the private functions that no one else needs */
-
-static int galbrg_set_CDV (int channel, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
- temp &= 0xFFFF0000;
- temp |= (value & 0x0000FFFF);
- GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
- return 0;
-}
-
-static int galbrg_enable (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
- temp |= 0x00010000;
- GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
- return 0;
-}
-
-static int galbrg_disable (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
- temp &= 0xFFFEFFFF;
- GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
- return 0;
-}
-
-static int galbrg_set_clksrc (int channel, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
- temp &= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */
- temp |= (value << 18);
- GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
- return 0;
-}
-
-static int galbrg_set_CUV (int channel, int value)
-{
- /* set CountUpValue */
- GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
-
- return 0;
-}
-
-#if 0
-static int galbrg_reset (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
- temp |= 0x20000;
- GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
- return 0;
-}
-#endif
-
-static int galsdma_set_RFT (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
- temp |= 0x00000001;
- GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
- temp);
-
- return 0;
-}
-
-static int galsdma_set_SFM (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
- temp |= 0x00000002;
- GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
- temp);
-
- return 0;
-}
-
-static int galsdma_set_rxle (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
- temp |= 0x00000040;
- GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
- temp);
-
- return 0;
-}
-
-static int galsdma_set_txle (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
- temp |= 0x00000080;
- GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
- temp);
-
- return 0;
-}
-
-static int galsdma_set_RC (int channel, unsigned int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
- temp &= ~0x0000003c;
- temp |= (value << 2);
- GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
- temp);
-
- return 0;
-}
-
-static int galsdma_set_burstsize (int channel, unsigned int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
- temp &= 0xFFFFCFFF;
- switch (value) {
- case 8:
- GT_REG_WRITE (GALSDMA_0_CONF_REG +
- (channel * GALSDMA_REG_DIFF),
- (temp | (0x3 << 12)));
- break;
-
- case 4:
- GT_REG_WRITE (GALSDMA_0_CONF_REG +
- (channel * GALSDMA_REG_DIFF),
- (temp | (0x2 << 12)));
- break;
-
- case 2:
- GT_REG_WRITE (GALSDMA_0_CONF_REG +
- (channel * GALSDMA_REG_DIFF),
- (temp | (0x1 << 12)));
- break;
-
- case 1:
- GT_REG_WRITE (GALSDMA_0_CONF_REG +
- (channel * GALSDMA_REG_DIFF),
- (temp | (0x0 << 12)));
- break;
-
- default:
- return -1;
- break;
- }
-
- return 0;
-}
-
-static int galmpsc_connect (int channel, int connect)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_ROUTING_REGISTER);
-
- if ((channel == 0) && connect)
- temp &= ~0x00000007;
- else if ((channel == 1) && connect)
- temp &= ~(0x00000007 << 6);
- else if ((channel == 0) && !connect)
- temp |= 0x00000007;
- else
- temp |= (0x00000007 << 6);
-
- /* Just in case... */
- temp &= 0x3fffffff;
-
- GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp);
-
- return 0;
-}
-
-static int galmpsc_route_rx_clock (int channel, int brg)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_RxC_ROUTE);
-
- if (channel == 0) {
- temp &= ~0x0000000F;
- temp |= brg;
- } else {
- temp &= ~0x00000F00;
- temp |= (brg << 8);
- }
-
- GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp);
-
- return 0;
-}
-
-static int galmpsc_route_tx_clock (int channel, int brg)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_TxC_ROUTE);
-
- if (channel == 0) {
- temp &= ~0x0000000F;
- temp |= brg;
- } else {
- temp &= ~0x00000F00;
- temp |= (brg << 8);
- }
-
- GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp);
-
- return 0;
-}
-
-static int galmpsc_write_config_regs (int mpsc, int mode)
-{
- if (mode == GALMPSC_UART) {
- /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
- GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP),
- 0x000004c4);
-
- /* Main config reg High (32x Rx/Tx clock mode, width=8bits */
- GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP),
- 0x024003f8);
- /* 22 2222 1111 */
- /* 54 3210 9876 */
- /* 0000 0010 0000 0000 */
- /* 1 */
- /* 098 7654 3210 */
- /* 0000 0011 1111 1000 */
- } else
- return -1;
-
- return 0;
-}
-
-static int galmpsc_config_channel_regs (int mpsc)
-{
- GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1);
- GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0);
-
- galmpsc_set_brkcnt (mpsc, 0x3);
- galmpsc_set_tcschar (mpsc, 0xab);
-
- return 0;
-}
-
-static int galmpsc_set_brkcnt (int mpsc, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
- temp &= 0x0000FFFF;
- temp |= (value << 16);
- GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
-
- return 0;
-}
-
-static int galmpsc_set_tcschar (int mpsc, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
- temp &= 0xFFFF0000;
- temp |= value;
- GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
-
- return 0;
-}
-
-static int galmpsc_set_char_length (int mpsc, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
- temp &= 0xFFFFCFFF;
- temp |= (value << 12);
- GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
-
- return 0;
-}
-
-static int galmpsc_set_stop_bit_length (int mpsc, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
- temp &= 0xFFFFBFFF;
- temp |= (value << 14);
- GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
-
- return 0;
-}
-
-static int galmpsc_set_parity (int mpsc, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
- if (value != -1) {
- temp &= 0xFFF3FFF3;
- temp |= ((value << 18) | (value << 2));
- temp |= ((value << 17) | (value << 1));
- } else {
- temp &= 0xFFF1FFF1;
- }
-
- GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
-
- return 0;
-}
-
-static int galmpsc_enter_hunt (int mpsc)
-{
- int temp;
-
- temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
- temp |= 0x80000000;
- GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
-
- while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) &
- MPSC_ENTER_HUNT) {
- udelay (1);
- }
- return 0;
-}
-
-
-static int galmpsc_shutdown (int mpsc)
-{
- unsigned int temp;
-
- /* cause RX abort (clears RX) */
- temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
- temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
- temp &= ~MPSC_ENTER_HUNT;
- GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
-
- GT_REG_WRITE (GALSDMA_0_COM_REG, 0);
- GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT);
-
- /* shut down the MPSC */
- GT_REG_WRITE (GALMPSC_MCONF_LOW, 0);
- GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0);
- GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0);
-
- udelay (100);
-
- /* shut down the sdma engines. */
- /* reset config to default */
- GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc);
-
- udelay (100);
-
- /* clear the SDMA current and first TX and RX pointers */
- GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0);
- GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0);
- GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0);
-
- udelay (100);
-
- return 0;
-}
-
-static void galsdma_enable_rx (void)
-{
- int temp;
-
- /* Enable RX processing */
- temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
- temp |= RX_ENABLE;
- GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
-
- galmpsc_enter_hunt (CHANNEL);
-}
-
-static int galmpsc_set_snoop (int mpsc, int value)
-{
- int reg =
- mpsc ? MPSC_1_ADDRESS_CONTROL_LOW :
- MPSC_0_ADDRESS_CONTROL_LOW;
- int temp = GTREGREAD (reg);
-
- if (value)
- temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);
- else
- temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));
- GT_REG_WRITE (reg, temp);
- return 0;
-}
-
-/*******************************************************************************
-* galsdma_set_mem_space - Set MV64360 IDMA memory decoding map.
-*
-* DESCRIPTION:
-* the MV64360 SDMA has its own address decoding map that is de-coupled
-* from the CPU interface address decoding windows. The SDMA channels
-* share four address windows. Each region can be individually configured
-* by this function by associating it to a target interface and setting
-* base and size values.
-*
-* NOTE!!!
-* The size must be in 64Kbyte granularity.
-* The base address must be aligned to the size.
-* The size must be a series of 1s followed by a series of zeros
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* true for success, false otherwise.
-*
-*******************************************************************************/
-
-static int galsdma_set_mem_space (unsigned int memSpace,
- unsigned int memSpaceTarget,
- unsigned int memSpaceAttr,
- unsigned int baseAddress, unsigned int size)
-{
- unsigned int temp;
-
- if (size == 0) {
- GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
- 1 << memSpace);
- return true;
- }
-
- /* The base address must be aligned to the size. */
- if (baseAddress % size != 0) {
- return false;
- }
- if (size < 0x10000) {
- return false;
- }
-
- /* Align size and base to 64K */
- baseAddress &= 0xffff0000;
- size &= 0xffff0000;
- temp = size >> 16;
-
- /* Checking that the size is a sequence of '1' followed by a
- sequence of '0' starting from LSB to MSB. */
- while ((temp > 0) && (temp & 0x1)) {
- temp = temp >> 1;
- }
-
- if (temp != 0) {
- GT_REG_WRITE (MV64360_CUNIT_BASE_ADDR_REG0 + memSpace * 8,
- (baseAddress | memSpaceTarget | memSpaceAttr));
- GT_REG_WRITE ((MV64360_CUNIT_SIZE0 + memSpace * 8),
- (size - 1) & 0xffff0000);
- GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
- 1 << memSpace);
- } else {
- /* An invalid size was specified */
- return false;
- }
- return true;
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*************************************************************************
- * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
- *
- ************************************************************************/
-
-
-/*
- * mpsc.h - header file for MPSC in uart mode (console driver)
- */
-
-#ifndef __MPSC_H__
-#define __MPSC_H__
-
-/* include actual Galileo defines */
-#include "../include/mv_gen_reg.h"
-
-/* driver related defines */
-
-int mpsc_init(int baud);
-void mpsc_sdma_init(void);
-void mpsc_init2(void);
-int galbrg_set_baudrate(int channel, int rate);
-
-int mpsc_putchar_early(char ch);
-char mpsc_getchar_debug(void);
-int mpsc_test_char_debug(void);
-
-int mpsc_test_char_sdma(void);
-
-extern int (*mpsc_putchar)(char ch);
-extern char (*mpsc_getchar)(void);
-extern int (*mpsc_test_char)(void);
-
-#define CHANNEL CONFIG_MPSC_PORT
-
-#define TX_DESC 5
-#define RX_DESC 20
-
-#define DESC_FIRST 0x00010000
-#define DESC_LAST 0x00020000
-#define DESC_OWNER_BIT 0x80000000
-
-#define TX_DEMAND 0x00800000
-#define TX_STOP 0x00010000
-#define RX_ENABLE 0x00000080
-
-#define SDMA_RX_ABORT (1 << 15)
-#define SDMA_TX_ABORT (1 << 31)
-#define MPSC_TX_ABORT (1 << 7)
-#define MPSC_RX_ABORT (1 << 23)
-#define MPSC_ENTER_HUNT (1 << 31)
-
-/* MPSC defines */
-
-#define GALMPSC_CONNECT 0x1
-#define GALMPSC_DISCONNECT 0x0
-
-#define GALMPSC_UART 0x1
-
-#define GALMPSC_STOP_BITS_1 0x0
-#define GALMPSC_STOP_BITS_2 0x1
-#define GALMPSC_CHAR_LENGTH_8 0x3
-#define GALMPSC_CHAR_LENGTH_7 0x2
-
-#define GALMPSC_PARITY_ODD 0x0
-#define GALMPSC_PARITY_EVEN 0x2
-#define GALMPSC_PARITY_MARK 0x3
-#define GALMPSC_PARITY_SPACE 0x1
-#define GALMPSC_PARITY_NONE -1
-
-#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */
-#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */
-#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */
-#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
-#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */
-#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */
-#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */
-
-#define GALMPSC_REG_GAP 0x1000
-
-#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */
-#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */
-#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */
-#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */
-#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */
-#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */
-#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */
-#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */
-#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */
-#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */
-#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */
-#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */
-
-#define GALSDMA_COMMAND_FIRST (1 << 16)
-#define GALSDMA_COMMAND_LAST (1 << 17)
-#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
-#define GALSDMA_COMMAND_AUTO (1 << 30)
-#define GALSDMA_COMMAND_OWNER (1 << 31)
-
-#define GALSDMA_RX 0
-#define GALSDMA_TX 1
-
-/* CHANNEL2 should be CHANNEL1, according to documentation,
- * but to work with the current GTREGS file...
- */
-#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */
-#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */
-#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */
-#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */
-#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */
-#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */
-#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */
-#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */
-#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */
-#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */
-#define GALSDMA_REG_DIFF 0x2000
-
-/* WRONG in gt64260R.h */
-#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */
-#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */
-#define GALMPSC_0_INT_CAUSE 0xb804
-#define GALMPSC_0_INT_MASK 0xb884
-
-#define GALSDMA_MODE_UART 0
-#define GALSDMA_MODE_BISYNC 1
-#define GALSDMA_MODE_HDLC 2
-#define GALSDMA_MODE_TRANSPARENT 3
-
-#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */
-#define GALBRG_REG_GAP 0x0008
-#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */
-
-#endif /* __MPSC_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64360X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * mv_eth.c - header file for the polled mode GT ethernet driver
- */
-#include <common.h>
-#include <net.h>
-#include <malloc.h>
-
-#include "mv_eth.h"
-
-/* enable Debug outputs */
-
-#undef DEBUG_MV_ETH
-
-#ifdef DEBUG_MV_ETH
-#define DEBUG
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-#undef MV64360_CHECKSUM_OFFLOAD
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-* The first part is the high level driver of the gigE ethernet ports. *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-
-/* Definition for configuring driver */
-/* #define UPDATE_STATS_BY_SOFTWARE */
-#undef MV64360_RX_QUEUE_FILL_ON_TASK
-
-
-/* Constants */
-#define MAGIC_ETH_RUNNING 8031971
-#define MV64360_INTERNAL_SRAM_SIZE _256K
-#define EXTRA_BYTES 32
-#define WRAP ETH_HLEN + 2 + 4 + 16
-#define BUFFER_MTU dev->mtu + WRAP
-#define INT_CAUSE_UNMASK_ALL 0x0007ffff
-#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
-#ifdef MV64360_RX_FILL_ON_TASK
-#define INT_CAUSE_MASK_ALL 0x00000000
-#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
-#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
-#endif
-
-/* Read/Write to/from MV64360 internal registers */
-#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
-#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
-#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
-#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
-
-/* Static function declarations */
-static int mv64360_eth_real_open (struct eth_device *eth);
-static int mv64360_eth_real_stop (struct eth_device *eth);
-static struct net_device_stats *mv64360_eth_get_stats (struct eth_device
- *dev);
-static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
-static void mv64360_eth_update_stat (struct eth_device *dev);
-bool db64360_eth_start (struct eth_device *eth);
-unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
- unsigned int mib_offset);
-int mv64360_eth_receive (struct eth_device *dev);
-
-int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length);
-
-#ifndef UPDATE_STATS_BY_SOFTWARE
-static void mv64360_eth_print_stat (struct eth_device *dev);
-#endif
-
-extern unsigned int INTERNAL_REG_BASE_ADDR;
-
-/*************************************************
- *Helper functions - used inside the driver only *
- *************************************************/
-#ifdef DEBUG_MV_ETH
-void print_globals (struct eth_device *dev)
-{
- printf ("Ethernet PRINT_Globals-Debug function\n");
- printf ("Base Address for ETH_PORT_INFO: %08x\n",
- (unsigned int) dev->priv);
- printf ("Base Address for mv64360_eth_priv: %08x\n",
- (unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
- port_private));
-
- printf ("GT Internal Base Address: %08x\n",
- INTERNAL_REG_BASE_ADDR);
- printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE);
- printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE);
- printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n",
- (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
- p_rx_buffer_base[0],
- (MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32);
- printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n",
- (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
- p_tx_buffer_base[0],
- (MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32);
-}
-#endif
-
-#define my_cpu_to_le32(x) my_le32_to_cpu((x))
-
-unsigned long my_le32_to_cpu (unsigned long x)
-{
- return (((x & 0x000000ffU) << 24) |
- ((x & 0x0000ff00U) << 8) |
- ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
-}
-
-
-/**********************************************************************
- * mv64360_eth_print_phy_status
- *
- * Prints gigabit ethenret phy status
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- **********************************************************************/
-
-static void mv64360_eth_print_phy_status (struct eth_device *dev)
-{
- struct mv64360_eth_priv *port_private;
- unsigned int port_num;
- ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
- unsigned int port_status, phy_reg_data;
-
- port_private =
- (struct mv64360_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
-
- /* Check Link status on phy */
- eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
- if (!(phy_reg_data & 0x20)) {
- printf ("Ethernet port changed link status to DOWN\n");
- } else {
- port_status =
- MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
- printf ("Ethernet status port %d: Link up", port_num);
- printf (", %s",
- (port_status & BIT2) ? "Full Duplex" : "Half Duplex");
- if (port_status & BIT4)
- printf (", Speed 1 Gbps");
- else
- printf (", %s",
- (port_status & BIT5) ? "Speed 100 Mbps" :
- "Speed 10 Mbps");
- printf ("\n");
- }
-}
-
-/**********************************************************************
- * u-boot entry functions for mv64360_eth
- *
- **********************************************************************/
-int db64360_eth_probe (struct eth_device *dev)
-{
- return ((int) db64360_eth_start (dev));
-}
-
-int db64360_eth_poll (struct eth_device *dev)
-{
- return mv64360_eth_receive (dev);
-}
-
-int db64360_eth_transmit(struct eth_device *dev, void *packet, int length)
-{
- mv64360_eth_xmit (dev, packet, length);
- return 0;
-}
-
-void db64360_eth_disable (struct eth_device *dev)
-{
- mv64360_eth_stop (dev);
-}
-
-
-void mv6436x_eth_initialize (bd_t * bis)
-{
- struct eth_device *dev;
- ETH_PORT_INFO *ethernet_private;
- struct mv64360_eth_priv *port_private;
- int devnum, x, temp;
- char *s, *e, buf[64];
-
- for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
- dev = calloc (sizeof (*dev), 1);
- if (!dev) {
- printf ("%s: mv_enet%d allocation failure, %s\n",
- __FUNCTION__, devnum, "eth_device structure");
- return;
- }
-
- /* must be less than sizeof(dev->name) */
- sprintf (dev->name, "mv_enet%d", devnum);
-
-#ifdef DEBUG
- printf ("Initializing %s\n", dev->name);
-#endif
-
- /* Extract the MAC address from the environment */
- switch (devnum) {
- case 0:
- s = "ethaddr";
- break;
-
- case 1:
- s = "eth1addr";
- break;
-
- case 2:
- s = "eth2addr";
- break;
-
- default: /* this should never happen */
- printf ("%s: Invalid device number %d\n",
- __FUNCTION__, devnum);
- return;
- }
-
- temp = getenv_f(s, buf, sizeof (buf));
- s = (temp > 0) ? buf : NULL;
-
-#ifdef DEBUG
- printf ("Setting MAC %d to %s\n", devnum, s);
-#endif
- for (x = 0; x < 6; ++x) {
- dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
- if (s)
- s = (*e) ? e + 1 : e;
- }
- /* ronen - set the MAC addr in the HW */
- eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
-
- dev->init = (void *) db64360_eth_probe;
- dev->halt = (void *) ethernet_phy_reset;
- dev->send = (void *) db64360_eth_transmit;
- dev->recv = (void *) db64360_eth_poll;
-
- ethernet_private = calloc (sizeof (*ethernet_private), 1);
- dev->priv = (void *) ethernet_private;
-
- if (!ethernet_private) {
- printf ("%s: %s allocation failure, %s\n",
- __FUNCTION__, dev->name,
- "Private Device Structure");
- free (dev);
- return;
- }
- /* start with an zeroed ETH_PORT_INFO */
- memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
- memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
-
- /* set pointer to memory for stats data structure etc... */
- port_private = calloc (sizeof (*ethernet_private), 1);
- ethernet_private->port_private = (void *)port_private;
- if (!port_private) {
- printf ("%s: %s allocation failure, %s\n",
- __FUNCTION__, dev->name,
- "Port Private Device Structure");
-
- free (ethernet_private);
- free (dev);
- return;
- }
-
- port_private->stats =
- calloc (sizeof (struct net_device_stats), 1);
- if (!port_private->stats) {
- printf ("%s: %s allocation failure, %s\n",
- __FUNCTION__, dev->name,
- "Net stat Structure");
-
- free (port_private);
- free (ethernet_private);
- free (dev);
- return;
- }
- memset (ethernet_private->port_private, 0,
- sizeof (struct mv64360_eth_priv));
- switch (devnum) {
- case 0:
- ethernet_private->port_num = ETH_0;
- break;
- case 1:
- ethernet_private->port_num = ETH_1;
- break;
- case 2:
- ethernet_private->port_num = ETH_2;
- break;
- default:
- printf ("Invalid device number %d\n", devnum);
- break;
- };
-
- port_private->port_num = devnum;
- /*
- * Read MIB counter on the GT in order to reset them,
- * then zero all the stats fields in memory
- */
- mv64360_eth_update_stat (dev);
- memset (port_private->stats, 0,
- sizeof (struct net_device_stats));
- /* Extract the MAC address from the environment */
- switch (devnum) {
- case 0:
- s = "ethaddr";
- break;
-
- case 1:
- s = "eth1addr";
- break;
-
- case 2:
- s = "eth2addr";
- break;
-
- default: /* this should never happen */
- printf ("%s: Invalid device number %d\n",
- __FUNCTION__, devnum);
- return;
- }
-
- temp = getenv_f(s, buf, sizeof (buf));
- s = (temp > 0) ? buf : NULL;
-
-#ifdef DEBUG
- printf ("Setting MAC %d to %s\n", devnum, s);
-#endif
- for (x = 0; x < 6; ++x) {
- dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
- if (s)
- s = (*e) ? e + 1 : e;
- }
-
- DP (printf ("Allocating descriptor and buffer rings\n"));
-
- ethernet_private->p_rx_desc_area_base[0] =
- (ETH_RX_DESC *) memalign (16,
- RX_DESC_ALIGNED_SIZE *
- MV64360_RX_QUEUE_SIZE + 1);
- ethernet_private->p_tx_desc_area_base[0] =
- (ETH_TX_DESC *) memalign (16,
- TX_DESC_ALIGNED_SIZE *
- MV64360_TX_QUEUE_SIZE + 1);
-
- ethernet_private->p_rx_buffer_base[0] =
- (char *) memalign (16,
- MV64360_RX_QUEUE_SIZE *
- MV64360_TX_BUFFER_SIZE + 1);
- ethernet_private->p_tx_buffer_base[0] =
- (char *) memalign (16,
- MV64360_RX_QUEUE_SIZE *
- MV64360_TX_BUFFER_SIZE + 1);
-
-#ifdef DEBUG_MV_ETH
- /* DEBUG OUTPUT prints adresses of globals */
- print_globals (dev);
-#endif
- eth_register (dev);
-
- }
- DP (printf ("%s: exit\n", __FUNCTION__));
-
-}
-
-/**********************************************************************
- * mv64360_eth_open
- *
- * This function is called when openning the network device. The function
- * should initialize all the hardware, initialize cyclic Rx/Tx
- * descriptors chain and buffers and allocate an IRQ to the network
- * device.
- *
- * Input : a pointer to the network device structure
- * / / ronen - changed the output to match net/eth.c needs
- * Output : nonzero of success , zero if fails.
- * under construction
- **********************************************************************/
-
-int mv64360_eth_open (struct eth_device *dev)
-{
- return (mv64360_eth_real_open (dev));
-}
-
-/* Helper function for mv64360_eth_open */
-static int mv64360_eth_real_open (struct eth_device *dev)
-{
-
- unsigned int queue;
- ETH_PORT_INFO *ethernet_private;
- struct mv64360_eth_priv *port_private;
- unsigned int port_num;
- u32 phy_reg_data;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- /* ronen - when we update the MAC env params we only update dev->enetaddr
- see ./net/eth.c eth_set_enetaddr() */
- memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
-
- port_private =
- (struct mv64360_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
-
- /* Stop RX Queues */
- MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
- 0x0000ff00);
-
- /* Clear the ethernet port interrupts */
- MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
- MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
-
- /* Unmask RX buffer and TX end interrupt */
- MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num),
- INT_CAUSE_UNMASK_ALL);
-
- /* Unmask phy and link status changes interrupts */
- MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
- INT_CAUSE_UNMASK_ALL_EXT);
-
- /* Set phy address of the port */
- ethernet_private->port_phy_addr = 0x8 + port_num;
-
- /* Activate the DMA channels etc */
- eth_port_init (ethernet_private);
-
-
- /* "Allocate" setup TX rings */
-
- for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
- unsigned int size;
-
- port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE;
- size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */
- ethernet_private->tx_desc_area_size[queue] = size;
-
- /* first clear desc area completely */
- memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
- 0, ethernet_private->tx_desc_area_size[queue]);
-
- /* initialize tx desc ring with low level driver */
- if (ether_init_tx_desc_ring
- (ethernet_private, ETH_Q0,
- port_private->tx_ring_size[queue],
- MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
- (unsigned int) ethernet_private->
- p_tx_desc_area_base[queue],
- (unsigned int) ethernet_private->
- p_tx_buffer_base[queue]) == false)
- printf ("### Error initializing TX Ring\n");
- }
-
- /* "Allocate" setup RX rings */
- for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
- unsigned int size;
-
- /* Meantime RX Ring are fixed - but must be configurable by user */
- port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE;
- size = (port_private->rx_ring_size[queue] *
- RX_DESC_ALIGNED_SIZE);
- ethernet_private->rx_desc_area_size[queue] = size;
-
- /* first clear desc area completely */
- memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
- 0, ethernet_private->rx_desc_area_size[queue]);
- if ((ether_init_rx_desc_ring
- (ethernet_private, ETH_Q0,
- port_private->rx_ring_size[queue],
- MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
- (unsigned int) ethernet_private->
- p_rx_desc_area_base[queue],
- (unsigned int) ethernet_private->
- p_rx_buffer_base[queue])) == false)
- printf ("### Error initializing RX Ring\n");
- }
-
- eth_port_start (ethernet_private);
-
- /* Set maximum receive buffer to 9700 bytes */
- MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num),
- (0x5 << 17) |
- (MV_REG_READ
- (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num))
- & 0xfff1ffff));
-
- /*
- * Set ethernet MTU for leaky bucket mechanism to 0 - this will
- * disable the leaky bucket mechanism .
- */
-
- MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
- MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
-
- /* Check Link status on phy */
- eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
- if (!(phy_reg_data & 0x20)) {
- /* Reset PHY */
- if ((ethernet_phy_reset (port_num)) != true) {
- printf ("$$ Warnning: No link on port %d \n",
- port_num);
- return 0;
- } else {
- eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
- if (!(phy_reg_data & 0x20)) {
- printf ("### Error: Phy is not active\n");
- return 0;
- }
- }
- } else {
- mv64360_eth_print_phy_status (dev);
- }
- port_private->eth_running = MAGIC_ETH_RUNNING;
- return 1;
-}
-
-
-static int mv64360_eth_free_tx_rings (struct eth_device *dev)
-{
- unsigned int queue;
- ETH_PORT_INFO *ethernet_private;
- struct mv64360_eth_priv *port_private;
- unsigned int port_num;
- volatile ETH_TX_DESC *p_tx_curr_desc;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64360_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
-
- /* Stop Tx Queues */
- MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
- 0x0000ff00);
-
- /* Free TX rings */
- DP (printf ("Clearing previously allocated TX queues... "));
- for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
- /* Free on TX rings */
- for (p_tx_curr_desc =
- ethernet_private->p_tx_desc_area_base[queue];
- ((unsigned int) p_tx_curr_desc <= (unsigned int)
- ethernet_private->p_tx_desc_area_base[queue] +
- ethernet_private->tx_desc_area_size[queue]);
- p_tx_curr_desc =
- (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
- TX_DESC_ALIGNED_SIZE)) {
- /* this is inside for loop */
- if (p_tx_curr_desc->return_info != 0) {
- p_tx_curr_desc->return_info = 0;
- DP (printf ("freed\n"));
- }
- }
- DP (printf ("Done\n"));
- }
- return 0;
-}
-
-static int mv64360_eth_free_rx_rings (struct eth_device *dev)
-{
- unsigned int queue;
- ETH_PORT_INFO *ethernet_private;
- struct mv64360_eth_priv *port_private;
- unsigned int port_num;
- volatile ETH_RX_DESC *p_rx_curr_desc;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64360_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
-
-
- /* Stop RX Queues */
- MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
- 0x0000ff00);
-
- /* Free RX rings */
- DP (printf ("Clearing previously allocated RX queues... "));
- for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
- /* Free preallocated skb's on RX rings */
- for (p_rx_curr_desc =
- ethernet_private->p_rx_desc_area_base[queue];
- (((unsigned int) p_rx_curr_desc <
- ((unsigned int) ethernet_private->
- p_rx_desc_area_base[queue] +
- ethernet_private->rx_desc_area_size[queue])));
- p_rx_curr_desc =
- (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
- RX_DESC_ALIGNED_SIZE)) {
- if (p_rx_curr_desc->return_info != 0) {
- p_rx_curr_desc->return_info = 0;
- DP (printf ("freed\n"));
- }
- }
- DP (printf ("Done\n"));
- }
- return 0;
-}
-
-/**********************************************************************
- * mv64360_eth_stop
- *
- * This function is used when closing the network device.
- * It updates the hardware,
- * release all memory that holds buffers and descriptors and release the IRQ.
- * Input : a pointer to the device structure
- * Output : zero if success , nonzero if fails
- *********************************************************************/
-
-int mv64360_eth_stop (struct eth_device *dev)
-{
- /* Disable all gigE address decoder */
- MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
- DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
- mv64360_eth_real_stop (dev);
-
- return 0;
-};
-
-/* Helper function for mv64360_eth_stop */
-
-static int mv64360_eth_real_stop (struct eth_device *dev)
-{
- ETH_PORT_INFO *ethernet_private;
- struct mv64360_eth_priv *port_private;
- unsigned int port_num;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64360_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
-
-
- mv64360_eth_free_tx_rings (dev);
- mv64360_eth_free_rx_rings (dev);
-
- eth_port_reset (ethernet_private->port_num);
- /* Disable ethernet port interrupts */
- MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
- MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
- /* Mask RX buffer and TX end interrupt */
- MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0);
- /* Mask phy and link status changes interrupts */
- MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
- MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH,
- BIT0 << port_num);
- /* Print Network statistics */
-#ifndef UPDATE_STATS_BY_SOFTWARE
- /*
- * Print statistics (only if ethernet is running),
- * then zero all the stats fields in memory
- */
- if (port_private->eth_running == MAGIC_ETH_RUNNING) {
- port_private->eth_running = 0;
- mv64360_eth_print_stat (dev);
- }
- memset (port_private->stats, 0, sizeof (struct net_device_stats));
-#endif
- DP (printf ("\nEthernet stopped ... \n"));
- return 0;
-}
-
-
-/**********************************************************************
- * mv64360_eth_start_xmit
- *
- * This function is queues a packet in the Tx descriptor for
- * required port.
- *
- * Input : skb - a pointer to socket buffer
- * dev - a pointer to the required port
- *
- * Output : zero upon success
- **********************************************************************/
-
-int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
- int dataSize)
-{
- ETH_PORT_INFO *ethernet_private;
- struct mv64360_eth_priv *port_private;
- PKT_INFO pkt_info;
- ETH_FUNC_RET_STATUS status;
- struct net_device_stats *stats;
- ETH_FUNC_RET_STATUS release_result;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64360_eth_priv *) ethernet_private->port_private;
-
- stats = port_private->stats;
-
- /* Update packet info data structure */
- pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */
- pkt_info.byte_cnt = dataSize;
- pkt_info.buf_ptr = (unsigned int) dataPtr;
- pkt_info.return_info = 0;
-
- status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
- if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
- printf ("Error on transmitting packet ..");
- if (status == ETH_QUEUE_FULL)
- printf ("ETH Queue is full. \n");
- if (status == ETH_QUEUE_LAST_RESOURCE)
- printf ("ETH Queue: using last available resource. \n");
- goto error;
- }
-
- /* Update statistics and start of transmittion time */
- stats->tx_bytes += dataSize;
- stats->tx_packets++;
-
- /* Check if packet(s) is(are) transmitted correctly (release everything) */
- do {
- release_result =
- eth_tx_return_desc (ethernet_private, ETH_Q0,
- &pkt_info);
- switch (release_result) {
- case ETH_OK:
- DP (printf ("descriptor released\n"));
- if (pkt_info.cmd_sts & BIT0) {
- printf ("Error in TX\n");
- stats->tx_errors++;
-
- }
- break;
- case ETH_RETRY:
- DP (printf ("transmission still in process\n"));
- break;
-
- case ETH_ERROR:
- printf ("routine can not access Tx desc ring\n");
- break;
-
- case ETH_END_OF_JOB:
- DP (printf ("the routine has nothing to release\n"));
- break;
- default: /* should not happen */
- break;
- }
- } while (release_result == ETH_OK);
-
-
- return 0; /* success */
- error:
- return 1; /* Failed - higher layers will free the skb */
-}
-
-/**********************************************************************
- * mv64360_eth_receive
- *
- * This function is forward packets that are received from the port's
- * queues toward kernel core or FastRoute them to another interface.
- *
- * Input : dev - a pointer to the required interface
- * max - maximum number to receive (0 means unlimted)
- *
- * Output : number of served packets
- **********************************************************************/
-
-int mv64360_eth_receive (struct eth_device *dev)
-{
- ETH_PORT_INFO *ethernet_private;
- struct mv64360_eth_priv *port_private;
- PKT_INFO pkt_info;
- struct net_device_stats *stats;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64360_eth_priv *) ethernet_private->port_private;
- stats = port_private->stats;
-
- while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
- ETH_OK)) {
-
-#ifdef DEBUG_MV_ETH
- if (pkt_info.byte_cnt != 0) {
- printf ("%s: Received %d byte Packet @ 0x%x\n",
- __FUNCTION__, pkt_info.byte_cnt,
- pkt_info.buf_ptr);
- }
-#endif
- /* Update statistics. Note byte count includes 4 byte CRC count */
- stats->rx_packets++;
- stats->rx_bytes += pkt_info.byte_cnt;
-
- /*
- * In case received a packet without first / last bits on OR the error
- * summary bit is on, the packets needs to be dropeed.
- */
- if (((pkt_info.
- cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
- (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
- || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
- stats->rx_dropped++;
-
- printf ("Received packet spread on multiple descriptors\n");
-
- /* Is this caused by an error ? */
- if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
- stats->rx_errors++;
- }
-
- /* free these descriptors again without forwarding them to the higher layers */
- pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
- pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
-
- if (eth_rx_return_buff
- (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
- printf ("Error while returning the RX Desc to Ring\n");
- } else {
- DP (printf ("RX Desc returned to Ring\n"));
- }
- /* /free these descriptors again */
- } else {
-
-/* !!! call higher layer processing */
-#ifdef DEBUG_MV_ETH
- printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
-#endif
- /* let the upper layer handle the packet */
- NetReceive ((uchar *) pkt_info.buf_ptr,
- (int) pkt_info.byte_cnt);
-
-/* **************************************************************** */
-/* free descriptor */
- pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
- pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
- DP (printf
- ("RX: pkt_info.buf_ptr = %x\n",
- pkt_info.buf_ptr));
- if (eth_rx_return_buff
- (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
- printf ("Error while returning the RX Desc to Ring\n");
- } else {
- DP (printf ("RX Desc returned to Ring\n"));
- }
-
-/* **************************************************************** */
-
- }
- }
- mv64360_eth_get_stats (dev); /* update statistics */
- return 1;
-}
-
-/**********************************************************************
- * mv64360_eth_get_stats
- *
- * Returns a pointer to the interface statistics.
- *
- * Input : dev - a pointer to the required interface
- *
- * Output : a pointer to the interface's statistics
- **********************************************************************/
-
-static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev)
-{
- ETH_PORT_INFO *ethernet_private;
- struct mv64360_eth_priv *port_private;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64360_eth_priv *) ethernet_private->port_private;
-
- mv64360_eth_update_stat (dev);
-
- return port_private->stats;
-}
-
-
-/**********************************************************************
- * mv64360_eth_update_stat
- *
- * Update the statistics structure in the private data structure
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- **********************************************************************/
-
-static void mv64360_eth_update_stat (struct eth_device *dev)
-{
- ETH_PORT_INFO *ethernet_private;
- struct mv64360_eth_priv *port_private;
- struct net_device_stats *stats;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64360_eth_priv *) ethernet_private->port_private;
- stats = port_private->stats;
-
- /* These are false updates */
- stats->rx_packets += (unsigned long)
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_GOOD_FRAMES_RECEIVED);
- stats->tx_packets += (unsigned long)
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_GOOD_FRAMES_SENT);
- stats->rx_bytes += (unsigned long)
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
- /*
- * Ideally this should be as follows -
- *
- * stats->rx_bytes += stats->rx_bytes +
- * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
- * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
- *
- * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
- * is just a dummy read for proper work of the GigE port
- */
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
- stats->tx_bytes += (unsigned long)
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_GOOD_OCTETS_SENT_LOW);
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_GOOD_OCTETS_SENT_HIGH);
- stats->rx_errors += (unsigned long)
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_MAC_RECEIVE_ERROR);
-
- /* Rx dropped is for received packet with CRC error */
- stats->rx_dropped +=
- (unsigned long) eth_read_mib_counter (ethernet_private->
- port_num,
- ETH_MIB_BAD_CRC_EVENT);
- stats->multicast += (unsigned long)
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_MULTICAST_FRAMES_RECEIVED);
- stats->collisions +=
- (unsigned long) eth_read_mib_counter (ethernet_private->
- port_num,
- ETH_MIB_COLLISION) +
- (unsigned long) eth_read_mib_counter (ethernet_private->
- port_num,
- ETH_MIB_LATE_COLLISION);
- /* detailed rx errors */
- stats->rx_length_errors +=
- (unsigned long) eth_read_mib_counter (ethernet_private->
- port_num,
- ETH_MIB_UNDERSIZE_RECEIVED)
- +
- (unsigned long) eth_read_mib_counter (ethernet_private->
- port_num,
- ETH_MIB_OVERSIZE_RECEIVED);
- /* detailed tx errors */
-}
-
-#ifndef UPDATE_STATS_BY_SOFTWARE
-/**********************************************************************
- * mv64360_eth_print_stat
- *
- * Update the statistics structure in the private data structure
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- **********************************************************************/
-
-static void mv64360_eth_print_stat (struct eth_device *dev)
-{
- ETH_PORT_INFO *ethernet_private;
- struct mv64360_eth_priv *port_private;
- struct net_device_stats *stats;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64360_eth_priv *) ethernet_private->port_private;
- stats = port_private->stats;
-
- /* These are false updates */
- printf ("\n### Network statistics: ###\n");
- printf ("--------------------------\n");
- printf (" Packets received: %ld\n", stats->rx_packets);
- printf (" Packets send: %ld\n", stats->tx_packets);
- printf (" Received bytes: %ld\n", stats->rx_bytes);
- printf (" Send bytes: %ld\n", stats->tx_bytes);
- if (stats->rx_errors != 0)
- printf (" Rx Errors: %ld\n",
- stats->rx_errors);
- if (stats->rx_dropped != 0)
- printf (" Rx dropped (CRC Errors): %ld\n",
- stats->rx_dropped);
- if (stats->multicast != 0)
- printf (" Rx mulicast frames: %ld\n",
- stats->multicast);
- if (stats->collisions != 0)
- printf (" No. of collisions: %ld\n",
- stats->collisions);
- if (stats->rx_length_errors != 0)
- printf (" Rx length errors: %ld\n",
- stats->rx_length_errors);
-}
-#endif
-
-/**************************************************************************
- *network_start - Network Kick Off Routine UBoot
- *Inputs :
- *Outputs :
- **************************************************************************/
-
-bool db64360_eth_start (struct eth_device *dev)
-{
- return (mv64360_eth_open (dev)); /* calls real open */
-}
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-* The second part is the low level driver of the gigE ethernet ports. *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-/*
- * based on Linux code
- * arch/powerpc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/********************************************************************************
- * Marvell's Gigabit Ethernet controller low level driver
- *
- * DESCRIPTION:
- * This file introduce low level API to Marvell's Gigabit Ethernet
- * controller. This Gigabit Ethernet Controller driver API controls
- * 1) Operations (i.e. port init, start, reset etc').
- * 2) Data flow (i.e. port send, receive etc').
- * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
- * struct.
- * This struct includes user configuration information as well as
- * driver internal data needed for its operations.
- *
- * Supported Features:
- * - This low level driver is OS independent. Allocating memory for
- * the descriptor rings and buffers are not within the scope of
- * this driver.
- * - The user is free from Rx/Tx queue managing.
- * - This low level driver introduce functionality API that enable
- * the to operate Marvell's Gigabit Ethernet Controller in a
- * convenient way.
- * - Simple Gigabit Ethernet port operation API.
- * - Simple Gigabit Ethernet port data flow API.
- * - Data flow and operation API support per queue functionality.
- * - Support cached descriptors for better performance.
- * - Enable access to all four DRAM banks and internal SRAM memory
- * spaces.
- * - PHY access and control API.
- * - Port control register configuration API.
- * - Full control over Unicast and Multicast MAC configurations.
- *
- * Operation flow:
- *
- * Initialization phase
- * This phase complete the initialization of the ETH_PORT_INFO
- * struct.
- * User information regarding port configuration has to be set
- * prior to calling the port initialization routine. For example,
- * the user has to assign the port_phy_addr field which is board
- * depended parameter.
- * In this phase any port Tx/Rx activity is halted, MIB counters
- * are cleared, PHY address is set according to user parameter and
- * access to DRAM and internal SRAM memory spaces.
- *
- * Driver ring initialization
- * Allocating memory for the descriptor rings and buffers is not
- * within the scope of this driver. Thus, the user is required to
- * allocate memory for the descriptors ring and buffers. Those
- * memory parameters are used by the Rx and Tx ring initialization
- * routines in order to curve the descriptor linked list in a form
- * of a ring.
- * Note: Pay special attention to alignment issues when using
- * cached descriptors/buffers. In this phase the driver store
- * information in the ETH_PORT_INFO struct regarding each queue
- * ring.
- *
- * Driver start
- * This phase prepares the Ethernet port for Rx and Tx activity.
- * It uses the information stored in the ETH_PORT_INFO struct to
- * initialize the various port registers.
- *
- * Data flow:
- * All packet references to/from the driver are done using PKT_INFO
- * struct.
- * This struct is a unified struct used with Rx and Tx operations.
- * This way the user is not required to be familiar with neither
- * Tx nor Rx descriptors structures.
- * The driver's descriptors rings are management by indexes.
- * Those indexes controls the ring resources and used to indicate
- * a SW resource error:
- * 'current'
- * This index points to the current available resource for use. For
- * example in Rx process this index will point to the descriptor
- * that will be passed to the user upon calling the receive routine.
- * In Tx process, this index will point to the descriptor
- * that will be assigned with the user packet info and transmitted.
- * 'used'
- * This index points to the descriptor that need to restore its
- * resources. For example in Rx process, using the Rx buffer return
- * API will attach the buffer returned in packet info to the
- * descriptor pointed by 'used'. In Tx process, using the Tx
- * descriptor return will merely return the user packet info with
- * the command status of the transmitted buffer pointed by the
- * 'used' index. Nevertheless, it is essential to use this routine
- * to update the 'used' index.
- * 'first'
- * This index supports Tx Scatter-Gather. It points to the first
- * descriptor of a packet assembled of multiple buffers. For example
- * when in middle of Such packet we have a Tx resource error the
- * 'curr' index get the value of 'first' to indicate that the ring
- * returned to its state before trying to transmit this packet.
- *
- * Receive operation:
- * The eth_port_receive API set the packet information struct,
- * passed by the caller, with received information from the
- * 'current' SDMA descriptor.
- * It is the user responsibility to return this resource back
- * to the Rx descriptor ring to enable the reuse of this source.
- * Return Rx resource is done using the eth_rx_return_buff API.
- *
- * Transmit operation:
- * The eth_port_send API supports Scatter-Gather which enables to
- * send a packet spanned over multiple buffers. This means that
- * for each packet info structure given by the user and put into
- * the Tx descriptors ring, will be transmitted only if the 'LAST'
- * bit will be set in the packet info command status field. This
- * API also consider restriction regarding buffer alignments and
- * sizes.
- * The user must return a Tx resource after ensuring the buffer
- * has been transmitted to enable the Tx ring indexes to update.
- *
- * BOARD LAYOUT
- * This device is on-board. No jumper diagram is necessary.
- *
- * EXTERNAL INTERFACE
- *
- * Prior to calling the initialization routine eth_port_init() the user
- * must set the following fields under ETH_PORT_INFO struct:
- * port_num User Ethernet port number.
- * port_phy_addr User PHY address of Ethernet port.
- * port_mac_addr[6] User defined port MAC address.
- * port_config User port configuration value.
- * port_config_extend User port config extend value.
- * port_sdma_config User port SDMA config value.
- * port_serial_control User port serial control value.
- * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr.
- * *port_private User scratch pad for user specific data structures.
- *
- * This driver introduce a set of default values:
- * PORT_CONFIG_VALUE Default port configuration value
- * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value
- * PORT_SDMA_CONFIG_VALUE Default sdma control value
- * PORT_SERIAL_CONTROL_VALUE Default port serial control value
- *
- * This driver data flow is done using the PKT_INFO struct which is
- * a unified struct for Rx and Tx operations:
- * byte_cnt Tx/Rx descriptor buffer byte count.
- * l4i_chk CPU provided TCP Checksum. For Tx operation only.
- * cmd_sts Tx/Rx descriptor command status.
- * buf_ptr Tx/Rx descriptor buffer pointer.
- * return_info Tx/Rx user resource return information.
- *
- *
- * EXTERNAL SUPPORT REQUIREMENTS
- *
- * This driver requires the following external support:
- *
- * D_CACHE_FLUSH_LINE (address, address offset)
- *
- * This macro applies assembly code to flush and invalidate cache
- * line.
- * address - address base.
- * address offset - address offset
- *
- *
- * CPU_PIPE_FLUSH
- *
- * This macro applies assembly code to flush the CPU pipeline.
- *
- *******************************************************************************/
-/* includes */
-
-/* defines */
-/* SDMA command macros */
-#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
- MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
-
-#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
- MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
- (1 << (8 + tx_queue)))
-
-#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
-MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
-
-#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
-MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
-
-#define CURR_RFD_GET(p_curr_desc, queue) \
- ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
-
-#define CURR_RFD_SET(p_curr_desc, queue) \
- (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
-
-#define USED_RFD_GET(p_used_desc, queue) \
- ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
-
-#define USED_RFD_SET(p_used_desc, queue)\
-(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
-
-
-#define CURR_TFD_GET(p_curr_desc, queue) \
- ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
-
-#define CURR_TFD_SET(p_curr_desc, queue) \
- (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
-
-#define USED_TFD_GET(p_used_desc, queue) \
- ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
-
-#define USED_TFD_SET(p_used_desc, queue) \
- (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
-
-#define FIRST_TFD_GET(p_first_desc, queue) \
- ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
-
-#define FIRST_TFD_SET(p_first_desc, queue) \
- (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
-
-
-/* Macros that save access to desc in order to find next desc pointer */
-#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
-
-#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
-
-#define LINK_UP_TIMEOUT 100000
-#define PHY_BUSY_TIMEOUT 10000000
-
-/* locals */
-
-/* PHY routines */
-static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
-static int ethernet_phy_get (ETH_PORT eth_port_num);
-
-/* Ethernet Port routines */
-static void eth_set_access_control (ETH_PORT eth_port_num,
- ETH_WIN_PARAM * param);
-static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
- ETH_QUEUE queue, int option);
-#if 0 /* FIXME */
-static bool eth_port_smc_addr (ETH_PORT eth_port_num,
- unsigned char mc_byte,
- ETH_QUEUE queue, int option);
-static bool eth_port_omc_addr (ETH_PORT eth_port_num,
- unsigned char crc8,
- ETH_QUEUE queue, int option);
-#endif
-
-static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
- int byte_count);
-
-void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
-
-
-typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
-u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
-{
- u32 result = 0;
- u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
-
- if (enable & (1 << bank))
- return 0;
- if (bank == BANK0)
- result = MV_REG_READ (MV64360_CS_0_BASE_ADDR);
- if (bank == BANK1)
- result = MV_REG_READ (MV64360_CS_1_BASE_ADDR);
- if (bank == BANK2)
- result = MV_REG_READ (MV64360_CS_2_BASE_ADDR);
- if (bank == BANK3)
- result = MV_REG_READ (MV64360_CS_3_BASE_ADDR);
- result &= 0x0000ffff;
- result = result << 16;
- return result;
-}
-
-u32 mv_get_dram_bank_size (MEMORY_BANK bank)
-{
- u32 result = 0;
- u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
-
- if (enable & (1 << bank))
- return 0;
- if (bank == BANK0)
- result = MV_REG_READ (MV64360_CS_0_SIZE);
- if (bank == BANK1)
- result = MV_REG_READ (MV64360_CS_1_SIZE);
- if (bank == BANK2)
- result = MV_REG_READ (MV64360_CS_2_SIZE);
- if (bank == BANK3)
- result = MV_REG_READ (MV64360_CS_3_SIZE);
- result += 1;
- result &= 0x0000ffff;
- result = result << 16;
- return result;
-}
-
-u32 mv_get_internal_sram_base (void)
-{
- u32 result;
-
- result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR);
- result &= 0x0000ffff;
- result = result << 16;
- return result;
-}
-
-/*******************************************************************************
-* eth_port_init - Initialize the Ethernet port driver
-*
-* DESCRIPTION:
-* This function prepares the ethernet port to start its activity:
-* 1) Completes the ethernet port driver struct initialization toward port
-* start routine.
-* 2) Resets the device to a quiescent state in case of warm reboot.
-* 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
-* 4) Clean MAC tables. The reset status of those tables is unknown.
-* 5) Set PHY address.
-* Note: Call this routine prior to eth_port_start routine and after setting
-* user values in the user fields of Ethernet port control struct (i.e.
-* port_phy_addr).
-*
-* INPUT:
-* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
-*
-* OUTPUT:
-* See description.
-*
-* RETURN:
-* None.
-*
-*******************************************************************************/
-static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
-{
- int queue;
- ETH_WIN_PARAM win_param;
-
- p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
- p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
- p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
- p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
-
- p_eth_port_ctrl->port_rx_queue_command = 0;
- p_eth_port_ctrl->port_tx_queue_command = 0;
-
- /* Zero out SW structs */
- for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
- CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
- USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
- p_eth_port_ctrl->rx_resource_err[queue] = false;
- }
-
- for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
- CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
- USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
- FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
- p_eth_port_ctrl->tx_resource_err[queue] = false;
- }
-
- eth_port_reset (p_eth_port_ctrl->port_num);
-
- /* Set access parameters for DRAM bank 0 */
- win_param.win = ETH_WIN0; /* Use Ethernet window 0 */
- win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
- win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
- win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
- win_param.high_addr = 0;
- /* Get bank base */
- win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
- win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */
- if (win_param.size == 0)
- win_param.enable = 0;
- else
- win_param.enable = 1; /* Enable the access */
- win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
-
- /* Set the access control for address window (EPAPR) READ & WRITE */
- eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
- /* Set access parameters for DRAM bank 1 */
- win_param.win = ETH_WIN1; /* Use Ethernet window 1 */
- win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
- win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
- win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
- win_param.high_addr = 0;
- /* Get bank base */
- win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
- win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */
- if (win_param.size == 0)
- win_param.enable = 0;
- else
- win_param.enable = 1; /* Enable the access */
- win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
-
- /* Set the access control for address window (EPAPR) READ & WRITE */
- eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
- /* Set access parameters for DRAM bank 2 */
- win_param.win = ETH_WIN2; /* Use Ethernet window 2 */
- win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
- win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
- win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
- win_param.high_addr = 0;
- /* Get bank base */
- win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
- win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */
- if (win_param.size == 0)
- win_param.enable = 0;
- else
- win_param.enable = 1; /* Enable the access */
- win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
-
- /* Set the access control for address window (EPAPR) READ & WRITE */
- eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
- /* Set access parameters for DRAM bank 3 */
- win_param.win = ETH_WIN3; /* Use Ethernet window 3 */
- win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
- win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
- win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
- win_param.high_addr = 0;
- /* Get bank base */
- win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
- win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */
- if (win_param.size == 0)
- win_param.enable = 0;
- else
- win_param.enable = 1; /* Enable the access */
- win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
-
- /* Set the access control for address window (EPAPR) READ & WRITE */
- eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
- /* Set access parameters for Internal SRAM */
- win_param.win = ETH_WIN4; /* Use Ethernet window 0 */
- win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */
- win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
- win_param.high_addr = 0;
- win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */
- win_param.size = MV64360_INTERNAL_SRAM_SIZE; /* Get bank size */
- win_param.enable = 1; /* Enable the access */
- win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
-
- /* Set the access control for address window (EPAPR) READ & WRITE */
- eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
- eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
-
- ethernet_phy_set (p_eth_port_ctrl->port_num,
- p_eth_port_ctrl->port_phy_addr);
-
- return;
-
-}
-
-/*******************************************************************************
-* eth_port_start - Start the Ethernet port activity.
-*
-* DESCRIPTION:
-* This routine prepares the Ethernet port for Rx and Tx activity:
-* 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
-* has been initialized a descriptor's ring (using ether_init_tx_desc_ring
-* for Tx and ether_init_rx_desc_ring for Rx)
-* 2. Initialize and enable the Ethernet configuration port by writing to
-* the port's configuration and command registers.
-* 3. Initialize and enable the SDMA by writing to the SDMA's
-* configuration and command registers.
-* After completing these steps, the ethernet port SDMA can starts to
-* perform Rx and Tx activities.
-*
-* Note: Each Rx and Tx queue descriptor's list must be initialized prior
-* to calling this function (use ether_init_tx_desc_ring for Tx queues and
-* ether_init_rx_desc_ring for Rx queues).
-*
-* INPUT:
-* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
-*
-* OUTPUT:
-* Ethernet port is ready to receive and transmit.
-*
-* RETURN:
-* false if the port PHY is not up.
-* true otherwise.
-*
-*******************************************************************************/
-static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
-{
- int queue;
- volatile ETH_TX_DESC *p_tx_curr_desc;
- volatile ETH_RX_DESC *p_rx_curr_desc;
- unsigned int phy_reg_data;
- ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
-
-
- /* Assignment of Tx CTRP of given queue */
- for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
- CURR_TFD_GET (p_tx_curr_desc, queue);
- MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
- (eth_port_num)
- + (4 * queue)),
- ((unsigned int) p_tx_curr_desc));
-
- }
-
- /* Assignment of Rx CRDP of given queue */
- for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
- CURR_RFD_GET (p_rx_curr_desc, queue);
- MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
- (eth_port_num)
- + (4 * queue)),
- ((unsigned int) p_rx_curr_desc));
-
- if (p_rx_curr_desc != NULL)
- /* Add the assigned Ethernet address to the port's address table */
- eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
- p_eth_port_ctrl->port_mac_addr,
- queue);
- }
-
- /* Assign port configuration and command. */
- MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
- p_eth_port_ctrl->port_config);
-
- MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
- p_eth_port_ctrl->port_config_extend);
-
- MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
- p_eth_port_ctrl->port_serial_control);
-
- MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
- ETH_SERIAL_PORT_ENABLE);
-
- /* Assign port SDMA configuration */
- MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
- p_eth_port_ctrl->port_sdma_config);
-
- MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
- (eth_port_num), 0x3fffffff);
- MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
- (eth_port_num), 0x03fffcff);
- /* Turn off the port/queue bandwidth limitation */
- MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
-
- /* Enable port Rx. */
- MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
- p_eth_port_ctrl->port_rx_queue_command);
-
- /* Check if link is up */
- eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
-
- if (!(phy_reg_data & 0x20))
- return false;
-
- return true;
-}
-
-/*******************************************************************************
-* eth_port_uc_addr_set - This function Set the port Unicast address.
-*
-* DESCRIPTION:
-* This function Set the port Ethernet MAC address.
-*
-* INPUT:
-* ETH_PORT eth_port_num Port number.
-* char * p_addr Address to be set
-* ETH_QUEUE queue Rx queue number for this MAC address.
-*
-* OUTPUT:
-* Set MAC address low and high registers. also calls eth_port_uc_addr()
-* To set the unicast table with the proper information.
-*
-* RETURN:
-* N/A.
-*
-*******************************************************************************/
-static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
- unsigned char *p_addr, ETH_QUEUE queue)
-{
- unsigned int mac_h;
- unsigned int mac_l;
-
- mac_l = (p_addr[4] << 8) | (p_addr[5]);
- mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
- (p_addr[2] << 8) | (p_addr[3] << 0);
-
- MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
- MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
-
- /* Accept frames of this address */
- eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
-
- return;
-}
-
-/*******************************************************************************
-* eth_port_uc_addr - This function Set the port unicast address table
-*
-* DESCRIPTION:
-* This function locates the proper entry in the Unicast table for the
-* specified MAC nibble and sets its properties according to function
-* parameters.
-*
-* INPUT:
-* ETH_PORT eth_port_num Port number.
-* unsigned char uc_nibble Unicast MAC Address last nibble.
-* ETH_QUEUE queue Rx queue number for this MAC address.
-* int option 0 = Add, 1 = remove address.
-*
-* OUTPUT:
-* This function add/removes MAC addresses from the port unicast address
-* table.
-*
-* RETURN:
-* true is output succeeded.
-* false if option parameter is invalid.
-*
-*******************************************************************************/
-static bool eth_port_uc_addr (ETH_PORT eth_port_num,
- unsigned char uc_nibble,
- ETH_QUEUE queue, int option)
-{
- unsigned int unicast_reg;
- unsigned int tbl_offset;
- unsigned int reg_offset;
-
- /* Locate the Unicast table entry */
- uc_nibble = (0xf & uc_nibble);
- tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
- reg_offset = uc_nibble % 4; /* Entry offset within the above register */
-
- switch (option) {
- case REJECT_MAC_ADDR:
- /* Clear accepts frame bit at specified unicast DA table entry */
- unicast_reg =
- MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
- (eth_port_num)
- + tbl_offset));
-
- unicast_reg &= (0x0E << (8 * reg_offset));
-
- MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
- (eth_port_num)
- + tbl_offset), unicast_reg);
- break;
-
- case ACCEPT_MAC_ADDR:
- /* Set accepts frame bit at unicast DA filter table entry */
- unicast_reg =
- MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
- (eth_port_num)
- + tbl_offset));
-
- unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
-
- MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
- (eth_port_num)
- + tbl_offset), unicast_reg);
-
- break;
-
- default:
- return false;
- }
- return true;
-}
-
-#if 0 /* FIXME */
-/*******************************************************************************
-* eth_port_mc_addr - Multicast address settings.
-*
-* DESCRIPTION:
-* This API controls the MV device MAC multicast support.
-* The MV device supports multicast using two tables:
-* 1) Special Multicast Table for MAC addresses of the form
-* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
-* The MAC DA[7:0] bits are used as a pointer to the Special Multicast
-* Table entries in the DA-Filter table.
-* In this case, the function calls eth_port_smc_addr() routine to set the
-* Special Multicast Table.
-* 2) Other Multicast Table for multicast of another type. A CRC-8bit
-* is used as an index to the Other Multicast Table entries in the
-* DA-Filter table.
-* In this case, the function calculates the CRC-8bit value and calls
-* eth_port_omc_addr() routine to set the Other Multicast Table.
-* INPUT:
-* ETH_PORT eth_port_num Port number.
-* unsigned char *p_addr Unicast MAC Address.
-* ETH_QUEUE queue Rx queue number for this MAC address.
-* int option 0 = Add, 1 = remove address.
-*
-* OUTPUT:
-* See description.
-*
-* RETURN:
-* true is output succeeded.
-* false if add_address_table_entry( ) failed.
-*
-*******************************************************************************/
-static void eth_port_mc_addr (ETH_PORT eth_port_num,
- unsigned char *p_addr,
- ETH_QUEUE queue, int option)
-{
- unsigned int mac_h;
- unsigned int mac_l;
- unsigned char crc_result = 0;
- int mac_array[48];
- int crc[8];
- int i;
-
-
- if ((p_addr[0] == 0x01) &&
- (p_addr[1] == 0x00) &&
- (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00))
-
- eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
- else {
- /* Calculate CRC-8 out of the given address */
- mac_h = (p_addr[0] << 8) | (p_addr[1]);
- mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
- (p_addr[4] << 8) | (p_addr[5] << 0);
-
- for (i = 0; i < 32; i++)
- mac_array[i] = (mac_l >> i) & 0x1;
- for (i = 32; i < 48; i++)
- mac_array[i] = (mac_h >> (i - 32)) & 0x1;
-
-
- crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
- mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
- mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
- mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
- mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
- mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
- mac_array[6] ^ mac_array[0];
-
- crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
- mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
- mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
- mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
- mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
- mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
- mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
- mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
- mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
- mac_array[0];
-
- crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
- mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
- mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
- mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
- mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
- mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
- mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
- mac_array[2] ^ mac_array[1] ^ mac_array[0];
-
- crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
- mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
- mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
- mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
- mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
- mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
- mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
- mac_array[2] ^ mac_array[1];
-
- crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
- mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
- mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
- mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
- mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
- mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
- mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
- mac_array[2];
-
- crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
- mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
- mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
- mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
- mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
- mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
- mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
- mac_array[3];
-
- crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
- mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
- mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
- mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
- mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
- mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
- mac_array[6] ^ mac_array[5] ^ mac_array[4];
-
- crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
- mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
- mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
- mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
- mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
- mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
- mac_array[6] ^ mac_array[5];
-
- for (i = 0; i < 8; i++)
- crc_result = crc_result | (crc[i] << i);
-
- eth_port_omc_addr (eth_port_num, crc_result, queue, option);
- }
- return;
-}
-
-/*******************************************************************************
-* eth_port_smc_addr - Special Multicast address settings.
-*
-* DESCRIPTION:
-* This routine controls the MV device special MAC multicast support.
-* The Special Multicast Table for MAC addresses supports MAC of the form
-* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
-* The MAC DA[7:0] bits are used as a pointer to the Special Multicast
-* Table entries in the DA-Filter table.
-* This function set the Special Multicast Table appropriate entry
-* according to the argument given.
-*
-* INPUT:
-* ETH_PORT eth_port_num Port number.
-* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits).
-* ETH_QUEUE queue Rx queue number for this MAC address.
-* int option 0 = Add, 1 = remove address.
-*
-* OUTPUT:
-* See description.
-*
-* RETURN:
-* true is output succeeded.
-* false if option parameter is invalid.
-*
-*******************************************************************************/
-static bool eth_port_smc_addr (ETH_PORT eth_port_num,
- unsigned char mc_byte,
- ETH_QUEUE queue, int option)
-{
- unsigned int smc_table_reg;
- unsigned int tbl_offset;
- unsigned int reg_offset;
-
- /* Locate the SMC table entry */
- tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */
- reg_offset = mc_byte % 4; /* Entry offset within the above register */
- queue &= 0x7;
-
- switch (option) {
- case REJECT_MAC_ADDR:
- /* Clear accepts frame bit at specified Special DA table entry */
- smc_table_reg =
- MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
- smc_table_reg &= (0x0E << (8 * reg_offset));
-
- MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
- break;
-
- case ACCEPT_MAC_ADDR:
- /* Set accepts frame bit at specified Special DA table entry */
- smc_table_reg =
- MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
- smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
-
- MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
- break;
-
- default:
- return false;
- }
- return true;
-}
-
-/*******************************************************************************
-* eth_port_omc_addr - Multicast address settings.
-*
-* DESCRIPTION:
-* This routine controls the MV device Other MAC multicast support.
-* The Other Multicast Table is used for multicast of another type.
-* A CRC-8bit is used as an index to the Other Multicast Table entries
-* in the DA-Filter table.
-* The function gets the CRC-8bit value from the calling routine and
-* set the Other Multicast Table appropriate entry according to the
-* CRC-8 argument given.
-*
-* INPUT:
-* ETH_PORT eth_port_num Port number.
-* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
-* ETH_QUEUE queue Rx queue number for this MAC address.
-* int option 0 = Add, 1 = remove address.
-*
-* OUTPUT:
-* See description.
-*
-* RETURN:
-* true is output succeeded.
-* false if option parameter is invalid.
-*
-*******************************************************************************/
-static bool eth_port_omc_addr (ETH_PORT eth_port_num,
- unsigned char crc8,
- ETH_QUEUE queue, int option)
-{
- unsigned int omc_table_reg;
- unsigned int tbl_offset;
- unsigned int reg_offset;
-
- /* Locate the OMC table entry */
- tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
- reg_offset = crc8 % 4; /* Entry offset within the above register */
- queue &= 0x7;
-
- switch (option) {
- case REJECT_MAC_ADDR:
- /* Clear accepts frame bit at specified Other DA table entry */
- omc_table_reg =
- MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
- omc_table_reg &= (0x0E << (8 * reg_offset));
-
- MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
- break;
-
- case ACCEPT_MAC_ADDR:
- /* Set accepts frame bit at specified Other DA table entry */
- omc_table_reg =
- MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
- omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
-
- MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
- break;
-
- default:
- return false;
- }
- return true;
-}
-#endif
-
-/*******************************************************************************
-* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
-*
-* DESCRIPTION:
-* Go through all the DA filter tables (Unicast, Special Multicast & Other
-* Multicast) and set each entry to 0.
-*
-* INPUT:
-* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
-*
-* OUTPUT:
-* Multicast and Unicast packets are rejected.
-*
-* RETURN:
-* None.
-*
-*******************************************************************************/
-static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
-{
- int table_index;
-
- /* Clear DA filter unicast table (Ex_dFUT) */
- for (table_index = 0; table_index <= 0xC; table_index += 4)
- MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
- (eth_port_num) + table_index), 0);
-
- for (table_index = 0; table_index <= 0xFC; table_index += 4) {
- /* Clear DA filter special multicast table (Ex_dFSMT) */
- MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
- /* Clear DA filter other multicast table (Ex_dFOMT) */
- MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
- }
-}
-
-/*******************************************************************************
-* eth_clear_mib_counters - Clear all MIB counters
-*
-* DESCRIPTION:
-* This function clears all MIB counters of a specific ethernet port.
-* A read from the MIB counter will reset the counter.
-*
-* INPUT:
-* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
-*
-* OUTPUT:
-* After reading all MIB counters, the counters resets.
-*
-* RETURN:
-* MIB counter value.
-*
-*******************************************************************************/
-static void eth_clear_mib_counters (ETH_PORT eth_port_num)
-{
- int i;
-
- /* Perform dummy reads from MIB counters */
- for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
- i += 4)
- MV_REG_READ((MV64360_ETH_MIB_COUNTERS_BASE(eth_port_num) + i));
-
- return;
-}
-
-/*******************************************************************************
-* eth_read_mib_counter - Read a MIB counter
-*
-* DESCRIPTION:
-* This function reads a MIB counter of a specific ethernet port.
-* NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
-* following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
-* register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
-* ETH_MIB_GOOD_OCTETS_SENT_HIGH
-*
-* INPUT:
-* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
-* unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros).
-*
-* OUTPUT:
-* After reading the MIB counter, the counter resets.
-*
-* RETURN:
-* MIB counter value.
-*
-*******************************************************************************/
-unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
- unsigned int mib_offset)
-{
- return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num)
- + mib_offset));
-}
-
-/*******************************************************************************
-* ethernet_phy_set - Set the ethernet port PHY address.
-*
-* DESCRIPTION:
-* This routine set the ethernet port PHY address according to given
-* parameter.
-*
-* INPUT:
-* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
-*
-* OUTPUT:
-* Set PHY Address Register with given PHY address parameter.
-*
-* RETURN:
-* None.
-*
-*******************************************************************************/
-static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
-{
- unsigned int reg_data;
-
- reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
-
- reg_data &= ~(0x1F << (5 * eth_port_num));
- reg_data |= (phy_addr << (5 * eth_port_num));
-
- MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data);
-
- return;
-}
-
-/*******************************************************************************
- * ethernet_phy_get - Get the ethernet port PHY address.
- *
- * DESCRIPTION:
- * This routine returns the given ethernet port PHY address.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- * None.
- *
- * RETURN:
- * PHY address.
- *
- *******************************************************************************/
-static int ethernet_phy_get (ETH_PORT eth_port_num)
-{
- unsigned int reg_data;
-
- reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
-
- return ((reg_data >> (5 * eth_port_num)) & 0x1f);
-}
-
-/*******************************************************************************
- * ethernet_phy_reset - Reset Ethernet port PHY.
- *
- * DESCRIPTION:
- * This routine utilize the SMI interface to reset the ethernet port PHY.
- * The routine waits until the link is up again or link up is timeout.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- * The ethernet port PHY renew its link.
- *
- * RETURN:
- * None.
- *
-*******************************************************************************/
-static bool ethernet_phy_reset (ETH_PORT eth_port_num)
-{
- unsigned int time_out = 50;
- unsigned int phy_reg_data;
-
- /* Reset the PHY */
- eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
- phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
- eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
-
- /* Poll on the PHY LINK */
- do {
- eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
-
- if (time_out-- == 0)
- return false;
- }
- while (!(phy_reg_data & 0x20));
-
- return true;
-}
-
-/*******************************************************************************
- * eth_port_reset - Reset Ethernet port
- *
- * DESCRIPTION:
- * This routine resets the chip by aborting any SDMA engine activity and
- * clearing the MIB counters. The Receiver and the Transmit unit are in
- * idle state after this command is performed and the port is disabled.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- * Channel activity is halted.
- *
- * RETURN:
- * None.
- *
- *******************************************************************************/
-static void eth_port_reset (ETH_PORT eth_port_num)
-{
- unsigned int reg_data;
-
- /* Stop Tx port activity. Check port Tx activity. */
- reg_data =
- MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
- (eth_port_num));
-
- if (reg_data & 0xFF) {
- /* Issue stop command for active channels only */
- MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
- (eth_port_num), (reg_data << 8));
-
- /* Wait for all Tx activity to terminate. */
- do {
- /* Check port cause register that all Tx queues are stopped */
- reg_data =
- MV_REG_READ
- (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
- (eth_port_num));
- }
- while (reg_data & 0xFF);
- }
-
- /* Stop Rx port activity. Check port Rx activity. */
- reg_data =
- MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
- (eth_port_num));
-
- if (reg_data & 0xFF) {
- /* Issue stop command for active channels only */
- MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
- (eth_port_num), (reg_data << 8));
-
- /* Wait for all Rx activity to terminate. */
- do {
- /* Check port cause register that all Rx queues are stopped */
- reg_data =
- MV_REG_READ
- (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
- (eth_port_num));
- }
- while (reg_data & 0xFF);
- }
-
-
- /* Clear all MIB counters */
- eth_clear_mib_counters (eth_port_num);
-
- /* Reset the Enable bit in the Configuration Register */
- reg_data =
- MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG
- (eth_port_num));
- reg_data &= ~ETH_SERIAL_PORT_ENABLE;
- MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
- reg_data);
-
- return;
-}
-
-#if 0 /* Not needed here */
-/*******************************************************************************
- * ethernet_set_config_reg - Set specified bits in configuration register.
- *
- * DESCRIPTION:
- * This function sets specified bits in the given ethernet
- * configuration register.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- * unsigned int value 32 bit value.
- *
- * OUTPUT:
- * The set bits in the value parameter are set in the configuration
- * register.
- *
- * RETURN:
- * None.
- *
- *******************************************************************************/
-static void ethernet_set_config_reg (ETH_PORT eth_port_num,
- unsigned int value)
-{
- unsigned int eth_config_reg;
-
- eth_config_reg =
- MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num));
- eth_config_reg |= value;
- MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
- eth_config_reg);
-
- return;
-}
-#endif
-
-#if 0 /* FIXME */
-/*******************************************************************************
- * ethernet_reset_config_reg - Reset specified bits in configuration register.
- *
- * DESCRIPTION:
- * This function resets specified bits in the given Ethernet
- * configuration register.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- * unsigned int value 32 bit value.
- *
- * OUTPUT:
- * The set bits in the value parameter are reset in the configuration
- * register.
- *
- * RETURN:
- * None.
- *
- *******************************************************************************/
-static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
- unsigned int value)
-{
- unsigned int eth_config_reg;
-
- eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
- (eth_port_num));
- eth_config_reg &= ~value;
- MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
- eth_config_reg);
-
- return;
-}
-#endif
-
-#if 0 /* Not needed here */
-/*******************************************************************************
- * ethernet_get_config_reg - Get the port configuration register
- *
- * DESCRIPTION:
- * This function returns the configuration register value of the given
- * ethernet port.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- * None.
- *
- * RETURN:
- * Port configuration register value.
- *
- *******************************************************************************/
-static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
-{
- unsigned int eth_config_reg;
-
- eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
- (eth_port_num));
- return eth_config_reg;
-}
-
-#endif
-
-/*******************************************************************************
- * eth_port_read_smi_reg - Read PHY registers
- *
- * DESCRIPTION:
- * This routine utilize the SMI interface to interact with the PHY in
- * order to perform PHY register read.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- * unsigned int phy_reg PHY register address offset.
- * unsigned int *value Register value buffer.
- *
- * OUTPUT:
- * Write the value of a specified PHY register into given buffer.
- *
- * RETURN:
- * false if the PHY is busy or read data is not in valid state.
- * true otherwise.
- *
- *******************************************************************************/
-static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
- unsigned int phy_reg, unsigned int *value)
-{
- unsigned int reg_value;
- unsigned int time_out = PHY_BUSY_TIMEOUT;
- int phy_addr;
-
- phy_addr = ethernet_phy_get (eth_port_num);
-/* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/
-
- /* first check that it is not busy */
- do {
- reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
- if (time_out-- == 0) {
- return false;
- }
- }
- while (reg_value & ETH_SMI_BUSY);
-
- /* not busy */
-
- MV_REG_WRITE (MV64360_ETH_SMI_REG,
- (phy_addr << 16) | (phy_reg << 21) |
- ETH_SMI_OPCODE_READ);
-
- time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */
-
- do {
- reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
- if (time_out-- == 0) {
- return false;
- }
- }
- while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */
-
- /* Wait for the data to update in the SMI register */
-#define PHY_UPDATE_TIMEOUT 10000
- for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
-
- reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
-
- *value = reg_value & 0xffff;
-
- return true;
-}
-
-/*******************************************************************************
- * eth_port_write_smi_reg - Write to PHY registers
- *
- * DESCRIPTION:
- * This routine utilize the SMI interface to interact with the PHY in
- * order to perform writes to PHY registers.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- * unsigned int phy_reg PHY register address offset.
- * unsigned int value Register value.
- *
- * OUTPUT:
- * Write the given value to the specified PHY register.
- *
- * RETURN:
- * false if the PHY is busy.
- * true otherwise.
- *
- *******************************************************************************/
-static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
- unsigned int phy_reg, unsigned int value)
-{
- unsigned int reg_value;
- unsigned int time_out = PHY_BUSY_TIMEOUT;
- int phy_addr;
-
- phy_addr = ethernet_phy_get (eth_port_num);
-
- /* first check that it is not busy */
- do {
- reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
- if (time_out-- == 0) {
- return false;
- }
- }
- while (reg_value & ETH_SMI_BUSY);
-
- /* not busy */
- MV_REG_WRITE (MV64360_ETH_SMI_REG,
- (phy_addr << 16) | (phy_reg << 21) |
- ETH_SMI_OPCODE_WRITE | (value & 0xffff));
- return true;
-}
-
-/*******************************************************************************
- * eth_set_access_control - Config address decode parameters for Ethernet unit
- *
- * DESCRIPTION:
- * This function configures the address decode parameters for the Gigabit
- * Ethernet Controller according the given parameters struct.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- * ETH_WIN_PARAM *param Address decode parameter struct.
- *
- * OUTPUT:
- * An access window is opened using the given access parameters.
- *
- * RETURN:
- * None.
- *
- *******************************************************************************/
-static void eth_set_access_control (ETH_PORT eth_port_num,
- ETH_WIN_PARAM * param)
-{
- unsigned int access_prot_reg;
-
- /* Set access control register */
- access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG
- (eth_port_num));
- access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */
- access_prot_reg |= (param->access_ctrl << (param->win * 2));
- MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num),
- access_prot_reg);
-
- /* Set window Size reg (SR) */
- MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 +
- (ETH_SIZE_REG_GAP * param->win)),
- (((param->size / 0x10000) - 1) << 16));
-
- /* Set window Base address reg (BA) */
- MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
- (param->target | param->attributes | param->base_addr));
- /* High address remap reg (HARR) */
- if (param->win < 4)
- MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 +
- (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
- param->high_addr);
-
- /* Base address enable reg (BARER) */
- if (param->enable == 1)
- MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
- (1 << param->win));
- else
- MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
- (1 << param->win));
-}
-
-/*******************************************************************************
- * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
- *
- * DESCRIPTION:
- * This function prepares a Rx chained list of descriptors and packet
- * buffers in a form of a ring. The routine must be called after port
- * initialization routine and before port start routine.
- * The Ethernet SDMA engine uses CPU bus addresses to access the various
- * devices in the system (i.e. DRAM). This function uses the ethernet
- * struct 'virtual to physical' routine (set by the user) to set the ring
- * with physical addresses.
- *
- * INPUT:
- * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
- * ETH_QUEUE rx_queue Number of Rx queue.
- * int rx_desc_num Number of Rx descriptors
- * int rx_buff_size Size of Rx buffer
- * unsigned int rx_desc_base_addr Rx descriptors memory area base addr.
- * unsigned int rx_buff_base_addr Rx buffer memory area base addr.
- *
- * OUTPUT:
- * The routine updates the Ethernet port control struct with information
- * regarding the Rx descriptors and buffers.
- *
- * RETURN:
- * false if the given descriptors memory area is not aligned according to
- * Ethernet SDMA specifications.
- * true otherwise.
- *
- *******************************************************************************/
-static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
- ETH_QUEUE rx_queue,
- int rx_desc_num,
- int rx_buff_size,
- unsigned int rx_desc_base_addr,
- unsigned int rx_buff_base_addr)
-{
- ETH_RX_DESC *p_rx_desc;
- ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */
- unsigned int buffer_addr;
- int ix; /* a counter */
-
-
- p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
- p_rx_prev_desc = p_rx_desc;
- buffer_addr = rx_buff_base_addr;
-
- /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
- if (rx_buff_base_addr & 0xF)
- return false;
-
- /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */
- if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
- return false;
-
- /* Rx buffers must be 64-bit aligned. */
- if ((rx_buff_base_addr + rx_buff_size) & 0x7)
- return false;
-
- /* initialize the Rx descriptors ring */
- for (ix = 0; ix < rx_desc_num; ix++) {
- p_rx_desc->buf_size = rx_buff_size;
- p_rx_desc->byte_cnt = 0x0000;
- p_rx_desc->cmd_sts =
- ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
- p_rx_desc->next_desc_ptr =
- ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
- p_rx_desc->buf_ptr = buffer_addr;
- p_rx_desc->return_info = 0x00000000;
- D_CACHE_FLUSH_LINE (p_rx_desc, 0);
- buffer_addr += rx_buff_size;
- p_rx_prev_desc = p_rx_desc;
- p_rx_desc = (ETH_RX_DESC *)
- ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
- }
-
- /* Closing Rx descriptors ring */
- p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
- D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
-
- /* Save Rx desc pointer to driver struct. */
- CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
- USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
-
- p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
- (ETH_RX_DESC *) rx_desc_base_addr;
- p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
- rx_desc_num * RX_DESC_ALIGNED_SIZE;
-
- p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
-
- return true;
-}
-
-/*******************************************************************************
- * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
- *
- * DESCRIPTION:
- * This function prepares a Tx chained list of descriptors and packet
- * buffers in a form of a ring. The routine must be called after port
- * initialization routine and before port start routine.
- * The Ethernet SDMA engine uses CPU bus addresses to access the various
- * devices in the system (i.e. DRAM). This function uses the ethernet
- * struct 'virtual to physical' routine (set by the user) to set the ring
- * with physical addresses.
- *
- * INPUT:
- * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
- * ETH_QUEUE tx_queue Number of Tx queue.
- * int tx_desc_num Number of Tx descriptors
- * int tx_buff_size Size of Tx buffer
- * unsigned int tx_desc_base_addr Tx descriptors memory area base addr.
- * unsigned int tx_buff_base_addr Tx buffer memory area base addr.
- *
- * OUTPUT:
- * The routine updates the Ethernet port control struct with information
- * regarding the Tx descriptors and buffers.
- *
- * RETURN:
- * false if the given descriptors memory area is not aligned according to
- * Ethernet SDMA specifications.
- * true otherwise.
- *
- *******************************************************************************/
-static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
- ETH_QUEUE tx_queue,
- int tx_desc_num,
- int tx_buff_size,
- unsigned int tx_desc_base_addr,
- unsigned int tx_buff_base_addr)
-{
-
- ETH_TX_DESC *p_tx_desc;
- ETH_TX_DESC *p_tx_prev_desc;
- unsigned int buffer_addr;
- int ix; /* a counter */
-
-
- /* save the first desc pointer to link with the last descriptor */
- p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
- p_tx_prev_desc = p_tx_desc;
- buffer_addr = tx_buff_base_addr;
-
- /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
- if (tx_buff_base_addr & 0xF)
- return false;
-
- /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */
- if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
- || (tx_buff_size < TX_BUFFER_MIN_SIZE))
- return false;
-
- /* Initialize the Tx descriptors ring */
- for (ix = 0; ix < tx_desc_num; ix++) {
- p_tx_desc->byte_cnt = 0x0000;
- p_tx_desc->l4i_chk = 0x0000;
- p_tx_desc->cmd_sts = 0x00000000;
- p_tx_desc->next_desc_ptr =
- ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
-
- p_tx_desc->buf_ptr = buffer_addr;
- p_tx_desc->return_info = 0x00000000;
- D_CACHE_FLUSH_LINE (p_tx_desc, 0);
- buffer_addr += tx_buff_size;
- p_tx_prev_desc = p_tx_desc;
- p_tx_desc = (ETH_TX_DESC *)
- ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
-
- }
- /* Closing Tx descriptors ring */
- p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
- D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
- /* Set Tx desc pointer in driver struct. */
- CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
- USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
-
- /* Init Tx ring base and size parameters */
- p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
- (ETH_TX_DESC *) tx_desc_base_addr;
- p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
- (tx_desc_num * TX_DESC_ALIGNED_SIZE);
-
- /* Add the queue to the list of Tx queues of this port */
- p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
-
- return true;
-}
-
-/*******************************************************************************
- * eth_port_send - Send an Ethernet packet
- *
- * DESCRIPTION:
- * This routine send a given packet described by p_pktinfo parameter. It
- * supports transmitting of a packet spaned over multiple buffers. The
- * routine updates 'curr' and 'first' indexes according to the packet
- * segment passed to the routine. In case the packet segment is first,
- * the 'first' index is update. In any case, the 'curr' index is updated.
- * If the routine get into Tx resource error it assigns 'curr' index as
- * 'first'. This way the function can abort Tx process of multiple
- * descriptors per packet.
- *
- * INPUT:
- * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
- * ETH_QUEUE tx_queue Number of Tx queue.
- * PKT_INFO *p_pkt_info User packet buffer.
- *
- * OUTPUT:
- * Tx ring 'curr' and 'first' indexes are updated.
- *
- * RETURN:
- * ETH_QUEUE_FULL in case of Tx resource error.
- * ETH_ERROR in case the routine can not access Tx desc ring.
- * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
- * ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
- ETH_QUEUE tx_queue,
- PKT_INFO * p_pkt_info)
-{
- volatile ETH_TX_DESC *p_tx_desc_first;
- volatile ETH_TX_DESC *p_tx_desc_curr;
- volatile ETH_TX_DESC *p_tx_next_desc_curr;
- volatile ETH_TX_DESC *p_tx_desc_used;
- unsigned int command_status;
-
- /* Do not process Tx ring in case of Tx ring resource error */
- if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
- return ETH_QUEUE_FULL;
-
- /* Get the Tx Desc ring indexes */
- CURR_TFD_GET (p_tx_desc_curr, tx_queue);
- USED_TFD_GET (p_tx_desc_used, tx_queue);
-
- if (p_tx_desc_curr == NULL)
- return ETH_ERROR;
-
- /* The following parameters are used to save readings from memory */
- p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
- command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
-
- if (command_status & (ETH_TX_FIRST_DESC)) {
- /* Update first desc */
- FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
- p_tx_desc_first = p_tx_desc_curr;
- } else {
- FIRST_TFD_GET (p_tx_desc_first, tx_queue);
- command_status |= ETH_BUFFER_OWNED_BY_DMA;
- }
-
- /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
- /* boundary. We use the memory allocated for Tx descriptor. This memory */
- /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
- if (p_pkt_info->byte_cnt <= 8) {
- printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */
- return ETH_ERROR;
-
- p_tx_desc_curr->buf_ptr =
- (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
- eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
- p_pkt_info->byte_cnt);
- } else
- p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
-
- p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
- p_tx_desc_curr->return_info = p_pkt_info->return_info;
-
- if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
- /* Set last desc with DMA ownership and interrupt enable. */
- p_tx_desc_curr->cmd_sts = command_status |
- ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
-
- if (p_tx_desc_curr != p_tx_desc_first)
- p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
-
- /* Flush CPU pipe */
-
- D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
- D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
- CPU_PIPE_FLUSH;
-
- /* Apply send command */
- ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
-
- /* Finish Tx packet. Update first desc in case of Tx resource error */
- p_tx_desc_first = p_tx_next_desc_curr;
- FIRST_TFD_SET (p_tx_desc_first, tx_queue);
-
- } else {
- p_tx_desc_curr->cmd_sts = command_status;
- D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
- }
-
- /* Check for ring index overlap in the Tx desc ring */
- if (p_tx_next_desc_curr == p_tx_desc_used) {
- /* Update the current descriptor */
- CURR_TFD_SET (p_tx_desc_first, tx_queue);
-
- p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
- return ETH_QUEUE_LAST_RESOURCE;
- } else {
- /* Update the current descriptor */
- CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
- return ETH_OK;
- }
-}
-
-/*******************************************************************************
- * eth_tx_return_desc - Free all used Tx descriptors
- *
- * DESCRIPTION:
- * This routine returns the transmitted packet information to the caller.
- * It uses the 'first' index to support Tx desc return in case a transmit
- * of a packet spanned over multiple buffer still in process.
- * In case the Tx queue was in "resource error" condition, where there are
- * no available Tx resources, the function resets the resource error flag.
- *
- * INPUT:
- * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
- * ETH_QUEUE tx_queue Number of Tx queue.
- * PKT_INFO *p_pkt_info User packet buffer.
- *
- * OUTPUT:
- * Tx ring 'first' and 'used' indexes are updated.
- *
- * RETURN:
- * ETH_ERROR in case the routine can not access Tx desc ring.
- * ETH_RETRY in case there is transmission in process.
- * ETH_END_OF_JOB if the routine has nothing to release.
- * ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
- p_eth_port_ctrl,
- ETH_QUEUE tx_queue,
- PKT_INFO * p_pkt_info)
-{
- volatile ETH_TX_DESC *p_tx_desc_used = NULL;
- volatile ETH_TX_DESC *p_tx_desc_first = NULL;
- unsigned int command_status;
-
-
- /* Get the Tx Desc ring indexes */
- USED_TFD_GET (p_tx_desc_used, tx_queue);
- FIRST_TFD_GET (p_tx_desc_first, tx_queue);
-
-
- /* Sanity check */
- if (p_tx_desc_used == NULL)
- return ETH_ERROR;
-
- command_status = p_tx_desc_used->cmd_sts;
-
- /* Still transmitting... */
- if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
- D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
- return ETH_RETRY;
- }
-
- /* Stop release. About to overlap the current available Tx descriptor */
- if ((p_tx_desc_used == p_tx_desc_first) &&
- (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
- D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
- return ETH_END_OF_JOB;
- }
-
- /* Pass the packet information to the caller */
- p_pkt_info->cmd_sts = command_status;
- p_pkt_info->return_info = p_tx_desc_used->return_info;
- p_tx_desc_used->return_info = 0;
-
- /* Update the next descriptor to release. */
- USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
-
- /* Any Tx return cancels the Tx resource error status */
- if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
- p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
-
- D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
-
- return ETH_OK;
-
-}
-
-/*******************************************************************************
- * eth_port_receive - Get received information from Rx ring.
- *
- * DESCRIPTION:
- * This routine returns the received data to the caller. There is no
- * data copying during routine operation. All information is returned
- * using pointer to packet information struct passed from the caller.
- * If the routine exhausts Rx ring resources then the resource error flag
- * is set.
- *
- * INPUT:
- * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
- * ETH_QUEUE rx_queue Number of Rx queue.
- * PKT_INFO *p_pkt_info User packet buffer.
- *
- * OUTPUT:
- * Rx ring current and used indexes are updated.
- *
- * RETURN:
- * ETH_ERROR in case the routine can not access Rx desc ring.
- * ETH_QUEUE_FULL if Rx ring resources are exhausted.
- * ETH_END_OF_JOB if there is no received data.
- * ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
- ETH_QUEUE rx_queue,
- PKT_INFO * p_pkt_info)
-{
- volatile ETH_RX_DESC *p_rx_curr_desc;
- volatile ETH_RX_DESC *p_rx_next_curr_desc;
- volatile ETH_RX_DESC *p_rx_used_desc;
- unsigned int command_status;
-
- /* Do not process Rx ring in case of Rx ring resource error */
- if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
- printf ("\nRx Queue is full ...\n");
- return ETH_QUEUE_FULL;
- }
-
- /* Get the Rx Desc ring 'curr and 'used' indexes */
- CURR_RFD_GET (p_rx_curr_desc, rx_queue);
- USED_RFD_GET (p_rx_used_desc, rx_queue);
-
- /* Sanity check */
- if (p_rx_curr_desc == NULL)
- return ETH_ERROR;
-
- /* The following parameters are used to save readings from memory */
- p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
- command_status = p_rx_curr_desc->cmd_sts;
-
- /* Nothing to receive... */
- if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
-/* DP(printf("Rx: command_status: %08x\n", command_status)); */
- D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
-/* DP(printf("\nETH_END_OF_JOB ...\n"));*/
- return ETH_END_OF_JOB;
- }
-
- p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
- p_pkt_info->cmd_sts = command_status;
- p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
- p_pkt_info->return_info = p_rx_curr_desc->return_info;
- p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */
-
- /* Clean the return info field to indicate that the packet has been */
- /* moved to the upper layers */
- p_rx_curr_desc->return_info = 0;
-
- /* Update 'curr' in data structure */
- CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
-
- /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
- if (p_rx_next_curr_desc == p_rx_used_desc)
- p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
-
- D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
- CPU_PIPE_FLUSH;
- return ETH_OK;
-}
-
-/*******************************************************************************
- * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
- *
- * DESCRIPTION:
- * This routine returns a Rx buffer back to the Rx ring. It retrieves the
- * next 'used' descriptor and attached the returned buffer to it.
- * In case the Rx ring was in "resource error" condition, where there are
- * no available Rx resources, the function resets the resource error flag.
- *
- * INPUT:
- * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
- * ETH_QUEUE rx_queue Number of Rx queue.
- * PKT_INFO *p_pkt_info Information on the returned buffer.
- *
- * OUTPUT:
- * New available Rx resource in Rx descriptor ring.
- *
- * RETURN:
- * ETH_ERROR in case the routine can not access Rx desc ring.
- * ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
- p_eth_port_ctrl,
- ETH_QUEUE rx_queue,
- PKT_INFO * p_pkt_info)
-{
- volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */
-
- /* Get 'used' Rx descriptor */
- USED_RFD_GET (p_used_rx_desc, rx_queue);
-
- /* Sanity check */
- if (p_used_rx_desc == NULL)
- return ETH_ERROR;
-
- p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
- p_used_rx_desc->return_info = p_pkt_info->return_info;
- p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
- p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE; /* Reset Buffer size */
-
- /* Flush the write pipe */
- CPU_PIPE_FLUSH;
-
- /* Return the descriptor to DMA ownership */
- p_used_rx_desc->cmd_sts =
- ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
-
- /* Flush descriptor and CPU pipe */
- D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
- CPU_PIPE_FLUSH;
-
- /* Move the used descriptor pointer to the next descriptor */
- USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
-
- /* Any Rx return cancels the Rx resource error status */
- if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
- p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
-
- return ETH_OK;
-}
-
-/*******************************************************************************
- * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
- *
- * DESCRIPTION:
- * This routine sets the RX coalescing interrupt mechanism parameter.
- * This parameter is a timeout counter, that counts in 64 t_clk
- * chunks ; that when timeout event occurs a maskable interrupt
- * occurs.
- * The parameter is calculated using the tClk of the MV-643xx chip
- * , and the required delay of the interrupt in usec.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet port number
- * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
- * unsigned int delay Delay in usec
- *
- * OUTPUT:
- * Interrupt coalescing mechanism value is set in MV-643xx chip.
- *
- * RETURN:
- * The interrupt coalescing value set in the gigE port.
- *
- *******************************************************************************/
-#if 0 /* FIXME */
-static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
- unsigned int t_clk,
- unsigned int delay)
-{
- unsigned int coal;
-
- coal = ((t_clk / 1000000) * delay) / 64;
- /* Set RX Coalescing mechanism */
- MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
- ((coal & 0x3fff) << 8) |
- (MV_REG_READ
- (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num))
- & 0xffc000ff));
- return coal;
-}
-
-#endif
-/*******************************************************************************
- * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
- *
- * DESCRIPTION:
- * This routine sets the TX coalescing interrupt mechanism parameter.
- * This parameter is a timeout counter, that counts in 64 t_clk
- * chunks ; that when timeout event occurs a maskable interrupt
- * occurs.
- * The parameter is calculated using the t_cLK frequency of the
- * MV-643xx chip and the required delay in the interrupt in uSec
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet port number
- * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
- * unsigned int delay Delay in uSeconds
- *
- * OUTPUT:
- * Interrupt coalescing mechanism value is set in MV-643xx chip.
- *
- * RETURN:
- * The interrupt coalescing value set in the gigE port.
- *
- *******************************************************************************/
-#if 0 /* FIXME */
-static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
- unsigned int t_clk,
- unsigned int delay)
-{
- unsigned int coal;
-
- coal = ((t_clk / 1000000) * delay) / 64;
- /* Set TX Coalescing mechanism */
- MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
- coal << 4);
- return coal;
-}
-#endif
-
-/*******************************************************************************
- * eth_b_copy - Copy bytes from source to destination
- *
- * DESCRIPTION:
- * This function supports the eight bytes limitation on Tx buffer size.
- * The routine will zero eight bytes starting from the destination address
- * followed by copying bytes from the source address to the destination.
- *
- * INPUT:
- * unsigned int src_addr 32 bit source address.
- * unsigned int dst_addr 32 bit destination address.
- * int byte_count Number of bytes to copy.
- *
- * OUTPUT:
- * See description.
- *
- * RETURN:
- * None.
- *
- *******************************************************************************/
-static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
- int byte_count)
-{
- /* Zero the dst_addr area */
- *(unsigned int *) dst_addr = 0x0;
-
- while (byte_count != 0) {
- *(char *) dst_addr = *(char *) src_addr;
- dst_addr++;
- src_addr++;
- byte_count--;
- }
-}
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64360X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * mv_eth.h - header file for the polled mode GT ethernet driver
- */
-
-#ifndef __DB64360_ETH_H__
-#define __DB64360_ETH_H__
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-#include <common.h>
-#include <net.h>
-#include "mv_regs.h"
-#include <asm/errno.h>
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-* The first part is the high level driver of the gigE ethernet ports. *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
-#ifndef MAX_SKB_FRAGS
-#define MAX_SKB_FRAGS 0
-#endif
-
-/* Port attributes */
-/*#define MAX_RX_QUEUE_NUM 8*/
-/*#define MAX_TX_QUEUE_NUM 8*/
-#define MAX_RX_QUEUE_NUM 1
-#define MAX_TX_QUEUE_NUM 1
-
-
-/* Use one TX queue and one RX queue */
-#define MV64360_TX_QUEUE_NUM 1
-#define MV64360_RX_QUEUE_NUM 1
-
-/*
- * Number of RX / TX descriptors on RX / TX rings.
- * Note that allocating RX descriptors is done by allocating the RX
- * ring AND a preallocated RX buffers (skb's) for each descriptor.
- * The TX descriptors only allocates the TX descriptors ring,
- * with no pre allocated TX buffers (skb's are allocated by higher layers.
- */
-
-/* Default TX ring size is 10 descriptors */
-#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE
-#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE
-#else
-#define MV64360_TX_QUEUE_SIZE 4
-#endif
-
-/* Default RX ring size is 4 descriptors */
-#ifdef CONFIG_MV64360_ETH_RXQUEUE_SIZE
-#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE
-#else
-#define MV64360_RX_QUEUE_SIZE 4
-#endif
-
-#ifdef CONFIG_RX_BUFFER_SIZE
-#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
-#else
-#define MV64360_RX_BUFFER_SIZE 1600
-#endif
-
-#ifdef CONFIG_TX_BUFFER_SIZE
-#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
-#else
-#define MV64360_TX_BUFFER_SIZE 1600
-#endif
-
-
-/*
- * Network device statistics. Akin to the 2.0 ether stats but
- * with byte counters.
- */
-
-struct net_device_stats
-{
- unsigned long rx_packets; /* total packets received */
- unsigned long tx_packets; /* total packets transmitted */
- unsigned long rx_bytes; /* total bytes received */
- unsigned long tx_bytes; /* total bytes transmitted */
- unsigned long rx_errors; /* bad packets received */
- unsigned long tx_errors; /* packet transmit problems */
- unsigned long rx_dropped; /* no space in linux buffers */
- unsigned long tx_dropped; /* no space available in linux */
- unsigned long multicast; /* multicast packets received */
- unsigned long collisions;
-
- /* detailed rx_errors: */
- unsigned long rx_length_errors;
- unsigned long rx_over_errors; /* receiver ring buff overflow */
- unsigned long rx_crc_errors; /* recved pkt with crc error */
- unsigned long rx_frame_errors; /* recv'd frame alignment error */
- unsigned long rx_fifo_errors; /* recv'r fifo overrun */
- unsigned long rx_missed_errors; /* receiver missed packet */
-
- /* detailed tx_errors */
- unsigned long tx_aborted_errors;
- unsigned long tx_carrier_errors;
- unsigned long tx_fifo_errors;
- unsigned long tx_heartbeat_errors;
- unsigned long tx_window_errors;
-
- /* for cslip etc */
- unsigned long rx_compressed;
- unsigned long tx_compressed;
-};
-
-
-/* Private data structure used for ethernet device */
-struct mv64360_eth_priv {
- unsigned int port_num;
- struct net_device_stats *stats;
-
-/* to buffer area aligned */
- char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */
- char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */
-
- /* Size of Tx Ring per queue */
- unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
-
-
- /* Size of Rx Ring per queue */
- unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
-
- /* Magic Number for Ethernet running */
- unsigned int eth_running;
-
-};
-
-
-int mv64360_eth_init (struct eth_device *dev);
-int mv64360_eth_stop (struct eth_device *dev);
-int mv64360_eth_start_xmit(struct eth_device *dev, void *packet, int length);
-int mv64360_eth_open (struct eth_device *dev);
-
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-* The second part is the low level driver of the gigE ethernet ports. *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-
-
-/********************************************************************************
- * Header File for : MV-643xx network interface header
- *
- * DESCRIPTION:
- * This header file contains macros typedefs and function declaration for
- * the Marvell Gig Bit Ethernet Controller.
- *
- * DEPENDENCIES:
- * None.
- *
- *******************************************************************************/
-
-
-#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
-#ifdef CONFIG_MV64360_SRAM_CACHEABLE
-/* In case SRAM is cacheable but not cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset) \
-{ \
- __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
-}
-#else
-/* In case SRAM is cache coherent or non-cacheable */
-#define D_CACHE_FLUSH_LINE(addr, offset) ;
-#endif
-#else
-#ifdef CONFIG_NOT_COHERENT_CACHE
-/* In case of descriptors on DDR but not cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset) \
-{ \
- __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
-}
-#else
-/* In case of descriptors on DDR and cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset) ;
-#endif /* CONFIG_NOT_COHERENT_CACHE */
-#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
-
-
-#define CPU_PIPE_FLUSH \
-{ \
- __asm__ __volatile__ ("eieio"); \
-}
-
-
-/* defines */
-
-/* Default port configuration value */
-#define PORT_CONFIG_VALUE \
- ETH_UNICAST_NORMAL_MODE | \
- ETH_DEFAULT_RX_QUEUE_0 | \
- ETH_DEFAULT_RX_ARP_QUEUE_0 | \
- ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
- ETH_RECEIVE_BC_IF_IP | \
- ETH_RECEIVE_BC_IF_ARP | \
- ETH_CAPTURE_TCP_FRAMES_DIS | \
- ETH_CAPTURE_UDP_FRAMES_DIS | \
- ETH_DEFAULT_RX_TCP_QUEUE_0 | \
- ETH_DEFAULT_RX_UDP_QUEUE_0 | \
- ETH_DEFAULT_RX_BPDU_QUEUE_0
-
-/* Default port extend configuration value */
-#define PORT_CONFIG_EXTEND_VALUE \
- ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
- ETH_PARTITION_DISABLE
-
-
-/* Default sdma control value */
-#ifdef CONFIG_NOT_COHERENT_CACHE
-#define PORT_SDMA_CONFIG_VALUE \
- ETH_RX_BURST_SIZE_16_64BIT | \
- GT_ETH_IPG_INT_RX(0) | \
- ETH_TX_BURST_SIZE_16_64BIT;
-#else
-#define PORT_SDMA_CONFIG_VALUE \
- ETH_RX_BURST_SIZE_4_64BIT | \
- GT_ETH_IPG_INT_RX(0) | \
- ETH_TX_BURST_SIZE_4_64BIT;
-#endif
-
-#define GT_ETH_IPG_INT_RX(value) \
- ((value & 0x3fff) << 8)
-
-/* Default port serial control value */
-#define PORT_SERIAL_CONTROL_VALUE \
- ETH_FORCE_LINK_PASS | \
- ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
- ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
- ETH_ADV_SYMMETRIC_FLOW_CTRL | \
- ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
- ETH_FORCE_BP_MODE_NO_JAM | \
- BIT9 | \
- ETH_DO_NOT_FORCE_LINK_FAIL | \
- ETH_RETRANSMIT_16_ETTEMPTS | \
- ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
- ETH_DTE_ADV_0 | \
- ETH_DISABLE_AUTO_NEG_BYPASS | \
- ETH_AUTO_NEG_NO_CHANGE | \
- ETH_MAX_RX_PACKET_1552BYTE | \
- ETH_CLR_EXT_LOOPBACK | \
- ETH_SET_FULL_DUPLEX_MODE | \
- ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
-
-#define RX_BUFFER_MAX_SIZE 0xFFFF
-#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */
-
-#define RX_BUFFER_MIN_SIZE 0x8
-#define TX_BUFFER_MIN_SIZE 0x8
-
-/* Tx WRR confoguration macros */
-#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
-#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */
-#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */
-
-/* MAC accepet/reject macros */
-#define ACCEPT_MAC_ADDR 0
-#define REJECT_MAC_ADDR 1
-
-/* Size of a Tx/Rx descriptor used in chain list data structure */
-#define RX_DESC_ALIGNED_SIZE 0x20
-#define TX_DESC_ALIGNED_SIZE 0x20
-
-/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
-#define TX_BUF_OFFSET_IN_DESC 0x18
-/* Buffer offset from buffer pointer */
-#define RX_BUF_OFFSET 0x2
-
-/* Gap define */
-#define ETH_BAR_GAP 0x8
-#define ETH_SIZE_REG_GAP 0x8
-#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4
-#define ETH_PORT_ACCESS_CTRL_GAP 0x4
-
-/* Gigabit Ethernet Unit Global Registers */
-
-/* MIB Counters register definitions */
-#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
-#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
-#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
-#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
-#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
-#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
-#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
-#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
-#define ETH_MIB_FRAMES_64_OCTETS 0x20
-#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
-#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
-#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
-#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
-#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
-#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
-#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
-#define ETH_MIB_GOOD_FRAMES_SENT 0x40
-#define ETH_MIB_EXCESSIVE_COLLISION 0x44
-#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
-#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
-#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
-#define ETH_MIB_FC_SENT 0x54
-#define ETH_MIB_GOOD_FC_RECEIVED 0x58
-#define ETH_MIB_BAD_FC_RECEIVED 0x5c
-#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
-#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
-#define ETH_MIB_OVERSIZE_RECEIVED 0x68
-#define ETH_MIB_JABBER_RECEIVED 0x6c
-#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
-#define ETH_MIB_BAD_CRC_EVENT 0x74
-#define ETH_MIB_COLLISION 0x78
-#define ETH_MIB_LATE_COLLISION 0x7c
-
-/* Port serial status reg (PSR) */
-#define ETH_INTERFACE_GMII_MII 0
-#define ETH_INTERFACE_PCM BIT0
-#define ETH_LINK_IS_DOWN 0
-#define ETH_LINK_IS_UP BIT1
-#define ETH_PORT_AT_HALF_DUPLEX 0
-#define ETH_PORT_AT_FULL_DUPLEX BIT2
-#define ETH_RX_FLOW_CTRL_DISABLED 0
-#define ETH_RX_FLOW_CTRL_ENBALED BIT3
-#define ETH_GMII_SPEED_100_10 0
-#define ETH_GMII_SPEED_1000 BIT4
-#define ETH_MII_SPEED_10 0
-#define ETH_MII_SPEED_100 BIT5
-#define ETH_NO_TX 0
-#define ETH_TX_IN_PROGRESS BIT7
-#define ETH_BYPASS_NO_ACTIVE 0
-#define ETH_BYPASS_ACTIVE BIT8
-#define ETH_PORT_NOT_AT_PARTITION_STATE 0
-#define ETH_PORT_AT_PARTITION_STATE BIT9
-#define ETH_PORT_TX_FIFO_NOT_EMPTY 0
-#define ETH_PORT_TX_FIFO_EMPTY BIT10
-
-
-/* These macros describes the Port configuration reg (Px_cR) bits */
-#define ETH_UNICAST_NORMAL_MODE 0
-#define ETH_UNICAST_PROMISCUOUS_MODE BIT0
-#define ETH_DEFAULT_RX_QUEUE_0 0
-#define ETH_DEFAULT_RX_QUEUE_1 BIT1
-#define ETH_DEFAULT_RX_QUEUE_2 BIT2
-#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1)
-#define ETH_DEFAULT_RX_QUEUE_4 BIT3
-#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1)
-#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2)
-#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1)
-#define ETH_DEFAULT_RX_ARP_QUEUE_0 0
-#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4
-#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5
-#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4)
-#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6
-#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4)
-#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5)
-#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4)
-#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
-#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7
-#define ETH_RECEIVE_BC_IF_IP 0
-#define ETH_REJECT_BC_IF_IP BIT8
-#define ETH_RECEIVE_BC_IF_ARP 0
-#define ETH_REJECT_BC_IF_ARP BIT9
-#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12
-#define ETH_CAPTURE_TCP_FRAMES_DIS 0
-#define ETH_CAPTURE_TCP_FRAMES_EN BIT14
-#define ETH_CAPTURE_UDP_FRAMES_DIS 0
-#define ETH_CAPTURE_UDP_FRAMES_EN BIT15
-#define ETH_DEFAULT_RX_TCP_QUEUE_0 0
-#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16
-#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17
-#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16)
-#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18
-#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16)
-#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17)
-#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16)
-#define ETH_DEFAULT_RX_UDP_QUEUE_0 0
-#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19
-#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20
-#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19)
-#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21
-#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19)
-#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20)
-#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0
-#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22
-#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23
-#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
-#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
-
-
-/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
-#define ETH_CLASSIFY_EN BIT0
-#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
-#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1
-#define ETH_PARTITION_DISABLE 0
-#define ETH_PARTITION_ENABLE BIT2
-
-
-/* Tx/Rx queue command reg (RQCR/TQCR)*/
-#define ETH_QUEUE_0_ENABLE BIT0
-#define ETH_QUEUE_1_ENABLE BIT1
-#define ETH_QUEUE_2_ENABLE BIT2
-#define ETH_QUEUE_3_ENABLE BIT3
-#define ETH_QUEUE_4_ENABLE BIT4
-#define ETH_QUEUE_5_ENABLE BIT5
-#define ETH_QUEUE_6_ENABLE BIT6
-#define ETH_QUEUE_7_ENABLE BIT7
-#define ETH_QUEUE_0_DISABLE BIT8
-#define ETH_QUEUE_1_DISABLE BIT9
-#define ETH_QUEUE_2_DISABLE BIT10
-#define ETH_QUEUE_3_DISABLE BIT11
-#define ETH_QUEUE_4_DISABLE BIT12
-#define ETH_QUEUE_5_DISABLE BIT13
-#define ETH_QUEUE_6_DISABLE BIT14
-#define ETH_QUEUE_7_DISABLE BIT15
-
-
-/* These macros describes the Port Sdma configuration reg (SDCR) bits */
-#define ETH_RIFB BIT0
-#define ETH_RX_BURST_SIZE_1_64BIT 0
-#define ETH_RX_BURST_SIZE_2_64BIT BIT1
-#define ETH_RX_BURST_SIZE_4_64BIT BIT2
-#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1)
-#define ETH_RX_BURST_SIZE_16_64BIT BIT3
-#define ETH_BLM_RX_NO_SWAP BIT4
-#define ETH_BLM_RX_BYTE_SWAP 0
-#define ETH_BLM_TX_NO_SWAP BIT5
-#define ETH_BLM_TX_BYTE_SWAP 0
-#define ETH_DESCRIPTORS_BYTE_SWAP BIT6
-#define ETH_DESCRIPTORS_NO_SWAP 0
-#define ETH_TX_BURST_SIZE_1_64BIT 0
-#define ETH_TX_BURST_SIZE_2_64BIT BIT22
-#define ETH_TX_BURST_SIZE_4_64BIT BIT23
-#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22)
-#define ETH_TX_BURST_SIZE_16_64BIT BIT24
-
-
-/* These macros describes the Port serial control reg (PSCR) bits */
-#define ETH_SERIAL_PORT_DISABLE 0
-#define ETH_SERIAL_PORT_ENABLE BIT0
-#define ETH_FORCE_LINK_PASS BIT1
-#define ETH_DO_NOT_FORCE_LINK_PASS 0
-#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
-#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2
-#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
-#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3
-#define ETH_ADV_NO_FLOW_CTRL 0
-#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4
-#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
-#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5
-#define ETH_FORCE_BP_MODE_NO_JAM 0
-#define ETH_FORCE_BP_MODE_JAM_TX BIT7
-#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8
-#define ETH_FORCE_LINK_FAIL 0
-#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10
-#define ETH_RETRANSMIT_16_ETTEMPTS 0
-#define ETH_RETRANSMIT_FOREVER BIT11
-#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13
-#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
-#define ETH_DTE_ADV_0 0
-#define ETH_DTE_ADV_1 BIT14
-#define ETH_DISABLE_AUTO_NEG_BYPASS 0
-#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15
-#define ETH_AUTO_NEG_NO_CHANGE 0
-#define ETH_RESTART_AUTO_NEG BIT16
-#define ETH_MAX_RX_PACKET_1518BYTE 0
-#define ETH_MAX_RX_PACKET_1522BYTE BIT17
-#define ETH_MAX_RX_PACKET_1552BYTE BIT18
-#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17)
-#define ETH_MAX_RX_PACKET_9192BYTE BIT19
-#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17)
-#define ETH_SET_EXT_LOOPBACK BIT20
-#define ETH_CLR_EXT_LOOPBACK 0
-#define ETH_SET_FULL_DUPLEX_MODE BIT21
-#define ETH_SET_HALF_DUPLEX_MODE 0
-#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22
-#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
-#define ETH_SET_GMII_SPEED_TO_10_100 0
-#define ETH_SET_GMII_SPEED_TO_1000 BIT23
-#define ETH_SET_MII_SPEED_TO_10 0
-#define ETH_SET_MII_SPEED_TO_100 BIT24
-
-
-/* SMI reg */
-#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
-#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
-#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
-#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
-
-/* SDMA command status fields macros */
-
-/* Tx & Rx descriptors status */
-#define ETH_ERROR_SUMMARY (BIT0)
-
-/* Tx & Rx descriptors command */
-#define ETH_BUFFER_OWNED_BY_DMA (BIT31)
-
-/* Tx descriptors status */
-#define ETH_LC_ERROR (0 )
-#define ETH_UR_ERROR (BIT1 )
-#define ETH_RL_ERROR (BIT2 )
-#define ETH_LLC_SNAP_FORMAT (BIT9 )
-
-/* Rx descriptors status */
-#define ETH_CRC_ERROR (0 )
-#define ETH_OVERRUN_ERROR (BIT1 )
-#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
-#define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
-#define ETH_VLAN_TAGGED (BIT19)
-#define ETH_BPDU_FRAME (BIT20)
-#define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
-#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
-#define ETH_OTHER_FRAME_TYPE (BIT22)
-#define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
-#define ETH_FRAME_TYPE_IP_V_4 (BIT24)
-#define ETH_FRAME_HEADER_OK (BIT25)
-#define ETH_RX_LAST_DESC (BIT26)
-#define ETH_RX_FIRST_DESC (BIT27)
-#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
-#define ETH_RX_ENABLE_INTERRUPT (BIT29)
-#define ETH_LAYER_4_CHECKSUM_OK (BIT30)
-
-/* Rx descriptors byte count */
-#define ETH_FRAME_FRAGMENTED (BIT2)
-
-/* Tx descriptors command */
-#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
-#define ETH_FRAME_SET_TO_VLAN (BIT15)
-#define ETH_TCP_FRAME (0 )
-#define ETH_UDP_FRAME (BIT16)
-#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
-#define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
-#define ETH_ZERO_PADDING (BIT19)
-#define ETH_TX_LAST_DESC (BIT20)
-#define ETH_TX_FIRST_DESC (BIT21)
-#define ETH_GEN_CRC (BIT22)
-#define ETH_TX_ENABLE_INTERRUPT (BIT23)
-#define ETH_AUTO_MODE (BIT30)
-
-/* Address decode parameters */
-/* Ethernet Base Address Register bits */
-#define EBAR_TARGET_DRAM 0x00000000
-#define EBAR_TARGET_DEVICE 0x00000001
-#define EBAR_TARGET_CBS 0x00000002
-#define EBAR_TARGET_PCI0 0x00000003
-#define EBAR_TARGET_PCI1 0x00000004
-#define EBAR_TARGET_CUNIT 0x00000005
-#define EBAR_TARGET_AUNIT 0x00000006
-#define EBAR_TARGET_GUNIT 0x00000007
-
-/* Window attributes */
-#define EBAR_ATTR_DRAM_CS0 0x00000E00
-#define EBAR_ATTR_DRAM_CS1 0x00000D00
-#define EBAR_ATTR_DRAM_CS2 0x00000B00
-#define EBAR_ATTR_DRAM_CS3 0x00000700
-
-/* DRAM Target interface */
-#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000
-#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000
-#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000
-
-/* Device Bus Target interface */
-#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00
-#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00
-#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00
-#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700
-#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00
-
-/* PCI Target interface */
-#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000
-#define EBAR_ATTR_PCI_NO_SWAP 0x00000100
-#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200
-#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300
-#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
-#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400
-#define EBAR_ATTR_PCI_IO_SPACE 0x00000000
-#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800
-#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000
-#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000
-
-/* CPU 60x bus or internal SRAM interface */
-#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000
-#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100
-#define EBAR_ATTR_CBS_SRAM 0x00000000
-#define EBAR_ATTR_CBS_CPU_BUS 0x00000800
-
-/* Window access control */
-#define EWIN_ACCESS_NOT_ALLOWED 0
-#define EWIN_ACCESS_READ_ONLY BIT0
-#define EWIN_ACCESS_FULL (BIT1 | BIT0)
-#define EWIN0_ACCESS_MASK 0x0003
-#define EWIN1_ACCESS_MASK 0x000C
-#define EWIN2_ACCESS_MASK 0x0030
-#define EWIN3_ACCESS_MASK 0x00C0
-
-/* typedefs */
-
-typedef enum _eth_port
-{
- ETH_0 = 0,
- ETH_1 = 1,
- ETH_2 = 2
-}ETH_PORT;
-
-typedef enum _eth_func_ret_status
-{
- ETH_OK, /* Returned as expected. */
- ETH_ERROR, /* Fundamental error. */
- ETH_RETRY, /* Could not process request. Try later. */
- ETH_END_OF_JOB, /* Ring has nothing to process. */
- ETH_QUEUE_FULL, /* Ring resource error. */
- ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
-}ETH_FUNC_RET_STATUS;
-
-typedef enum _eth_queue
-{
- ETH_Q0 = 0,
- ETH_Q1 = 1,
- ETH_Q2 = 2,
- ETH_Q3 = 3,
- ETH_Q4 = 4,
- ETH_Q5 = 5,
- ETH_Q6 = 6,
- ETH_Q7 = 7
-} ETH_QUEUE;
-
-typedef enum _addr_win
-{
- ETH_WIN0,
- ETH_WIN1,
- ETH_WIN2,
- ETH_WIN3,
- ETH_WIN4,
- ETH_WIN5
-} ETH_ADDR_WIN;
-
-typedef enum _eth_target
-{
- ETH_TARGET_DRAM ,
- ETH_TARGET_DEVICE,
- ETH_TARGET_CBS ,
- ETH_TARGET_PCI0 ,
- ETH_TARGET_PCI1
-}ETH_TARGET;
-
-typedef struct _eth_rx_desc
-{
- unsigned short byte_cnt ; /* Descriptor buffer byte count */
- unsigned short buf_size ; /* Buffer size */
- unsigned int cmd_sts ; /* Descriptor command status */
- unsigned int next_desc_ptr; /* Next descriptor pointer */
- unsigned int buf_ptr ; /* Descriptor buffer pointer */
- unsigned int return_info ; /* User resource return information */
-} ETH_RX_DESC;
-
-
-typedef struct _eth_tx_desc
-{
- unsigned short byte_cnt ; /* Descriptor buffer byte count */
- unsigned short l4i_chk ; /* CPU provided TCP Checksum */
- unsigned int cmd_sts ; /* Descriptor command status */
- unsigned int next_desc_ptr; /* Next descriptor pointer */
- unsigned int buf_ptr ; /* Descriptor buffer pointer */
- unsigned int return_info ; /* User resource return information */
-} ETH_TX_DESC;
-
-/* Unified struct for Rx and Tx operations. The user is not required to */
-/* be familier with neither Tx nor Rx descriptors. */
-typedef struct _pkt_info
-{
- unsigned short byte_cnt ; /* Descriptor buffer byte count */
- unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */
- unsigned int cmd_sts ; /* Descriptor command status */
- unsigned int buf_ptr ; /* Descriptor buffer pointer */
- unsigned int return_info ; /* User resource return information */
-} PKT_INFO;
-
-
-typedef struct _eth_win_param
-{
- ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */
- ETH_TARGET target; /* System targets. See ETH_TARGET enum */
- unsigned short attributes; /* BAR attributes. See above macros. */
- unsigned int base_addr; /* Window base address in unsigned int form */
- unsigned int high_addr; /* Window high address in unsigned int form */
- unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
- bool enable; /* Enable/disable access to the window. */
- unsigned short access_ctrl; /* Access ctrl register. see above macros */
-} ETH_WIN_PARAM;
-
-
-/* Ethernet port specific infomation */
-
-typedef struct _eth_port_ctrl
-{
- ETH_PORT port_num; /* User Ethernet port number */
- int port_phy_addr; /* User phy address of Ethrnet port */
- unsigned char port_mac_addr[6]; /* User defined port MAC address. */
- unsigned int port_config; /* User port configuration value */
- unsigned int port_config_extend; /* User port config extend value */
- unsigned int port_sdma_config; /* User port SDMA config value */
- unsigned int port_serial_control; /* User port serial control value */
- unsigned int port_tx_queue_command; /* Port active Tx queues summary */
- unsigned int port_rx_queue_command; /* Port active Rx queues summary */
-
- /* User function to cast virtual address to CPU bus address */
- unsigned int (*port_virt_to_phys)(unsigned int addr);
- /* User scratch pad for user specific data structures */
- void *port_private;
-
- bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
- bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
-
- /* Tx/Rx rings managment indexes fields. For driver use */
-
- /* Next available Rx resource */
- volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
- /* Returning Rx resource */
- volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
-
- /* Next available Tx resource */
- volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
- /* Returning Tx resource */
- volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
- /* An extra Tx index to support transmit of multiple buffers per packet */
- volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
-
- /* Tx/Rx rings size and base variables fields. For driver use */
-
- volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
- unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM];
- char *p_rx_buffer_base[MAX_RX_QUEUE_NUM];
-
- volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
- unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM];
- char *p_tx_buffer_base[MAX_TX_QUEUE_NUM];
-
-} ETH_PORT_INFO;
-
-
-/* ethernet.h API list */
-
-/* Port operation control routines */
-static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
-static void eth_port_reset(ETH_PORT eth_port_num);
-static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
-
-
-/* Port MAC address routines */
-static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
- unsigned char *p_addr,
- ETH_QUEUE queue);
-#if 0 /* FIXME */
-static void eth_port_mc_addr (ETH_PORT eth_port_num,
- unsigned char *p_addr,
- ETH_QUEUE queue,
- int option);
-#endif
-
-/* PHY and MIB routines */
-static bool ethernet_phy_reset(ETH_PORT eth_port_num);
-
-static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
- unsigned int phy_reg,
- unsigned int value);
-
-static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
- unsigned int phy_reg,
- unsigned int* value);
-
-static void eth_clear_mib_counters(ETH_PORT eth_port_num);
-
-/* Port data flow control routines */
-static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl,
- ETH_QUEUE tx_queue,
- PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
- ETH_QUEUE tx_queue,
- PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
- ETH_QUEUE rx_queue,
- PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
- ETH_QUEUE rx_queue,
- PKT_INFO *p_pkt_info);
-
-
-static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
- ETH_QUEUE tx_queue,
- int tx_desc_num,
- int tx_buff_size,
- unsigned int tx_desc_base_addr,
- unsigned int tx_buff_base_addr);
-
-static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
- ETH_QUEUE rx_queue,
- int rx_desc_num,
- int rx_buff_size,
- unsigned int rx_desc_base_addr,
- unsigned int rx_buff_base_addr);
-
-#endif /* MV64360_ETH_ */
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64360X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/********************************************************************************
-* gt64360r.h - GT-64360 Internal registers definition file.
-*
-* DESCRIPTION:
-* None.
-*
-* DEPENDENCIES:
-* None.
-*
-*******************************************************************************/
-
-#ifndef __INCmv_regsh
-#define __INCmv_regsh
-
-#define MV64360
-
-/* Supported by the Atlantis */
-#define MV64360_INCLUDE_PCI_1
-#define MV64360_INCLUDE_PCI_0_ARBITER
-#define MV64360_INCLUDE_PCI_1_ARBITER
-#define MV64360_INCLUDE_SNOOP_SUPPORT
-#define MV64360_INCLUDE_P2P
-#define MV64360_INCLUDE_ETH_PORT_2
-#define MV64360_INCLUDE_CPU_MAPPING
-#define MV64360_INCLUDE_MPSC
-
-/* Not supported features */
-#undef INCLUDE_CNTMR_4_7
-#undef INCLUDE_DMA_4_7
-
-/****************************************/
-/* Processor Address Space */
-/****************************************/
-
-/* DDR SDRAM BAR and size registers */
-
-#define MV64360_CS_0_BASE_ADDR 0x008
-#define MV64360_CS_0_SIZE 0x010
-#define MV64360_CS_1_BASE_ADDR 0x208
-#define MV64360_CS_1_SIZE 0x210
-#define MV64360_CS_2_BASE_ADDR 0x018
-#define MV64360_CS_2_SIZE 0x020
-#define MV64360_CS_3_BASE_ADDR 0x218
-#define MV64360_CS_3_SIZE 0x220
-
-/* Devices BAR and size registers */
-
-#define MV64360_DEV_CS0_BASE_ADDR 0x028
-#define MV64360_DEV_CS0_SIZE 0x030
-#define MV64360_DEV_CS1_BASE_ADDR 0x228
-#define MV64360_DEV_CS1_SIZE 0x230
-#define MV64360_DEV_CS2_BASE_ADDR 0x248
-#define MV64360_DEV_CS2_SIZE 0x250
-#define MV64360_DEV_CS3_BASE_ADDR 0x038
-#define MV64360_DEV_CS3_SIZE 0x040
-#define MV64360_BOOTCS_BASE_ADDR 0x238
-#define MV64360_BOOTCS_SIZE 0x240
-
-/* PCI 0 BAR and size registers */
-
-#define MV64360_PCI_0_IO_BASE_ADDR 0x048
-#define MV64360_PCI_0_IO_SIZE 0x050
-#define MV64360_PCI_0_MEMORY0_BASE_ADDR 0x058
-#define MV64360_PCI_0_MEMORY0_SIZE 0x060
-#define MV64360_PCI_0_MEMORY1_BASE_ADDR 0x080
-#define MV64360_PCI_0_MEMORY1_SIZE 0x088
-#define MV64360_PCI_0_MEMORY2_BASE_ADDR 0x258
-#define MV64360_PCI_0_MEMORY2_SIZE 0x260
-#define MV64360_PCI_0_MEMORY3_BASE_ADDR 0x280
-#define MV64360_PCI_0_MEMORY3_SIZE 0x288
-
-/* PCI 1 BAR and size registers */
-#define MV64360_PCI_1_IO_BASE_ADDR 0x090
-#define MV64360_PCI_1_IO_SIZE 0x098
-#define MV64360_PCI_1_MEMORY0_BASE_ADDR 0x0a0
-#define MV64360_PCI_1_MEMORY0_SIZE 0x0a8
-#define MV64360_PCI_1_MEMORY1_BASE_ADDR 0x0b0
-#define MV64360_PCI_1_MEMORY1_SIZE 0x0b8
-#define MV64360_PCI_1_MEMORY2_BASE_ADDR 0x2a0
-#define MV64360_PCI_1_MEMORY2_SIZE 0x2a8
-#define MV64360_PCI_1_MEMORY3_BASE_ADDR 0x2b0
-#define MV64360_PCI_1_MEMORY3_SIZE 0x2b8
-
-/* SRAM base address */
-#define MV64360_INTEGRATED_SRAM_BASE_ADDR 0x268
-
-/* internal registers space base address */
-#define MV64360_INTERNAL_SPACE_BASE_ADDR 0x068
-
-/* Enables the CS , DEV_CS , PCI 0 and PCI 1
- windows above */
-#define MV64360_BASE_ADDR_ENABLE 0x278
-
-/****************************************/
-/* PCI remap registers */
-/****************************************/
- /* PCI 0 */
-#define MV64360_PCI_0_IO_ADDR_REMAP 0x0f0
-#define MV64360_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8
-#define MV64360_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320
-#define MV64360_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100
-#define MV64360_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328
-#define MV64360_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8
-#define MV64360_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330
-#define MV64360_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300
-#define MV64360_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338
- /* PCI 1 */
-#define MV64360_PCI_1_IO_ADDR_REMAP 0x108
-#define MV64360_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110
-#define MV64360_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340
-#define MV64360_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118
-#define MV64360_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348
-#define MV64360_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310
-#define MV64360_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350
-#define MV64360_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318
-#define MV64360_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358
-
-#define MV64360_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0
-#define MV64360_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8
-#define MV64360_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0
-#define MV64360_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8
-#define MV64360_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0
-#define MV64360_CPU_GE_HEADERS_RETARGET_BASE 0x3d8
-#define MV64360_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0
-#define MV64360_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8
-
-/****************************************/
-/* CPU Control Registers */
-/****************************************/
-
-#define MV64360_CPU_CONFIG 0x000
-#define MV64360_CPU_MODE 0x120
-#define MV64360_CPU_MASTER_CONTROL 0x160
-#define MV64360_CPU_CROSS_BAR_CONTROL_LOW 0x150
-#define MV64360_CPU_CROSS_BAR_CONTROL_HIGH 0x158
-#define MV64360_CPU_CROSS_BAR_TIMEOUT 0x168
-
-/****************************************/
-/* SMP RegisterS */
-/****************************************/
-
-#define MV64360_SMP_WHO_AM_I 0x200
-#define MV64360_SMP_CPU0_DOORBELL 0x214
-#define MV64360_SMP_CPU0_DOORBELL_CLEAR 0x21C
-#define MV64360_SMP_CPU1_DOORBELL 0x224
-#define MV64360_SMP_CPU1_DOORBELL_CLEAR 0x22C
-#define MV64360_SMP_CPU0_DOORBELL_MASK 0x234
-#define MV64360_SMP_CPU1_DOORBELL_MASK 0x23C
-#define MV64360_SMP_SEMAPHOR0 0x244
-#define MV64360_SMP_SEMAPHOR1 0x24c
-#define MV64360_SMP_SEMAPHOR2 0x254
-#define MV64360_SMP_SEMAPHOR3 0x25c
-#define MV64360_SMP_SEMAPHOR4 0x264
-#define MV64360_SMP_SEMAPHOR5 0x26c
-#define MV64360_SMP_SEMAPHOR6 0x274
-#define MV64360_SMP_SEMAPHOR7 0x27c
-
-/****************************************/
-/* CPU Sync Barrier Register */
-/****************************************/
-
-#define MV64360_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0
-#define MV64360_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8
-#define MV64360_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0
-#define MV64360_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8
-
-/****************************************/
-/* CPU Access Protect */
-/****************************************/
-
-#define MV64360_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180
-#define MV64360_CPU_PROTECT_WINDOW_0_SIZE 0x188
-#define MV64360_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190
-#define MV64360_CPU_PROTECT_WINDOW_1_SIZE 0x198
-#define MV64360_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0
-#define MV64360_CPU_PROTECT_WINDOW_2_SIZE 0x1a8
-#define MV64360_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0
-#define MV64360_CPU_PROTECT_WINDOW_3_SIZE 0x1b8
-
-
-/****************************************/
-/* CPU Error Report */
-/****************************************/
-
-#define MV64360_CPU_ERROR_ADDR_LOW 0x070
-#define MV64360_CPU_ERROR_ADDR_HIGH 0x078
-#define MV64360_CPU_ERROR_DATA_LOW 0x128
-#define MV64360_CPU_ERROR_DATA_HIGH 0x130
-#define MV64360_CPU_ERROR_PARITY 0x138
-#define MV64360_CPU_ERROR_CAUSE 0x140
-#define MV64360_CPU_ERROR_MASK 0x148
-
-/****************************************/
-/* CPU Interface Debug Registers */
-/****************************************/
-
-#define MV64360_PUNIT_SLAVE_DEBUG_LOW 0x360
-#define MV64360_PUNIT_SLAVE_DEBUG_HIGH 0x368
-#define MV64360_PUNIT_MASTER_DEBUG_LOW 0x370
-#define MV64360_PUNIT_MASTER_DEBUG_HIGH 0x378
-#define MV64360_PUNIT_MMASK 0x3e4
-
-/****************************************/
-/* Integrated SRAM Registers */
-/****************************************/
-
-#define MV64360_SRAM_CONFIG 0x380
-#define MV64360_SRAM_TEST_MODE 0X3F4
-#define MV64360_SRAM_ERROR_CAUSE 0x388
-#define MV64360_SRAM_ERROR_ADDR 0x390
-#define MV64360_SRAM_ERROR_ADDR_HIGH 0X3F8
-#define MV64360_SRAM_ERROR_DATA_LOW 0x398
-#define MV64360_SRAM_ERROR_DATA_HIGH 0x3a0
-#define MV64360_SRAM_ERROR_DATA_PARITY 0x3a8
-
-/****************************************/
-/* SDRAM Configuration */
-/****************************************/
-
-#define MV64360_SDRAM_CONFIG 0x1400
-#define MV64360_D_UNIT_CONTROL_LOW 0x1404
-#define MV64360_D_UNIT_CONTROL_HIGH 0x1424
-#define MV64360_SDRAM_TIMING_CONTROL_LOW 0x1408
-#define MV64360_SDRAM_TIMING_CONTROL_HIGH 0x140c
-#define MV64360_SDRAM_ADDR_CONTROL 0x1410
-#define MV64360_SDRAM_OPEN_PAGES_CONTROL 0x1414
-#define MV64360_SDRAM_OPERATION 0x1418
-#define MV64360_SDRAM_MODE 0x141c
-#define MV64360_EXTENDED_DRAM_MODE 0x1420
-#define MV64360_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430
-#define MV64360_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434
-#define MV64360_SDRAM_CROSS_BAR_TIMEOUT 0x1438
-#define MV64360_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0
-#define MV64360_SDRAM_DATA_PADS_CALIBRATION 0x14c4
-
-/****************************************/
-/* SDRAM Error Report */
-/****************************************/
-
-#define MV64360_SDRAM_ERROR_DATA_LOW 0x1444
-#define MV64360_SDRAM_ERROR_DATA_HIGH 0x1440
-#define MV64360_SDRAM_ERROR_ADDR 0x1450
-#define MV64360_SDRAM_RECEIVED_ECC 0x1448
-#define MV64360_SDRAM_CALCULATED_ECC 0x144c
-#define MV64360_SDRAM_ECC_CONTROL 0x1454
-#define MV64360_SDRAM_ECC_ERROR_COUNTER 0x1458
-
-/******************************************/
-/* Controlled Delay Line (CDL) Registers */
-/******************************************/
-
-#define MV64360_DFCDL_CONFIG0 0x1480
-#define MV64360_DFCDL_CONFIG1 0x1484
-#define MV64360_DLL_WRITE 0x1488
-#define MV64360_DLL_READ 0x148c
-#define MV64360_SRAM_ADDR 0x1490
-#define MV64360_SRAM_DATA0 0x1494
-#define MV64360_SRAM_DATA1 0x1498
-#define MV64360_SRAM_DATA2 0x149c
-#define MV64360_DFCL_PROBE 0x14a0
-
-/******************************************/
-/* Debug Registers */
-/******************************************/
-
-#define MV64360_DUNIT_DEBUG_LOW 0x1460
-#define MV64360_DUNIT_DEBUG_HIGH 0x1464
-#define MV64360_DUNIT_MMASK 0X1b40
-
-/****************************************/
-/* Device Parameters */
-/****************************************/
-
-#define MV64360_DEVICE_BANK0_PARAMETERS 0x45c
-#define MV64360_DEVICE_BANK1_PARAMETERS 0x460
-#define MV64360_DEVICE_BANK2_PARAMETERS 0x464
-#define MV64360_DEVICE_BANK3_PARAMETERS 0x468
-#define MV64360_DEVICE_BOOT_BANK_PARAMETERS 0x46c
-#define MV64360_DEVICE_INTERFACE_CONTROL 0x4c0
-#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8
-#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc
-#define MV64360_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4
-
-/****************************************/
-/* Device interrupt registers */
-/****************************************/
-
-#define MV64360_DEVICE_INTERRUPT_CAUSE 0x4d0
-#define MV64360_DEVICE_INTERRUPT_MASK 0x4d4
-#define MV64360_DEVICE_ERROR_ADDR 0x4d8
-#define MV64360_DEVICE_ERROR_DATA 0x4dc
-#define MV64360_DEVICE_ERROR_PARITY 0x4e0
-
-/****************************************/
-/* Device debug registers */
-/****************************************/
-
-#define MV64360_DEVICE_DEBUG_LOW 0x4e4
-#define MV64360_DEVICE_DEBUG_HIGH 0x4e8
-#define MV64360_RUNIT_MMASK 0x4f0
-
-/****************************************/
-/* PCI Slave Address Decoding registers */
-/****************************************/
-
-#define MV64360_PCI_0_CS_0_BANK_SIZE 0xc08
-#define MV64360_PCI_1_CS_0_BANK_SIZE 0xc88
-#define MV64360_PCI_0_CS_1_BANK_SIZE 0xd08
-#define MV64360_PCI_1_CS_1_BANK_SIZE 0xd88
-#define MV64360_PCI_0_CS_2_BANK_SIZE 0xc0c
-#define MV64360_PCI_1_CS_2_BANK_SIZE 0xc8c
-#define MV64360_PCI_0_CS_3_BANK_SIZE 0xd0c
-#define MV64360_PCI_1_CS_3_BANK_SIZE 0xd8c
-#define MV64360_PCI_0_DEVCS_0_BANK_SIZE 0xc10
-#define MV64360_PCI_1_DEVCS_0_BANK_SIZE 0xc90
-#define MV64360_PCI_0_DEVCS_1_BANK_SIZE 0xd10
-#define MV64360_PCI_1_DEVCS_1_BANK_SIZE 0xd90
-#define MV64360_PCI_0_DEVCS_2_BANK_SIZE 0xd18
-#define MV64360_PCI_1_DEVCS_2_BANK_SIZE 0xd98
-#define MV64360_PCI_0_DEVCS_3_BANK_SIZE 0xc14
-#define MV64360_PCI_1_DEVCS_3_BANK_SIZE 0xc94
-#define MV64360_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14
-#define MV64360_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94
-#define MV64360_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c
-#define MV64360_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c
-#define MV64360_PCI_0_P2P_MEM1_BAR_SIZE 0xd20
-#define MV64360_PCI_1_P2P_MEM1_BAR_SIZE 0xda0
-#define MV64360_PCI_0_P2P_I_O_BAR_SIZE 0xd24
-#define MV64360_PCI_1_P2P_I_O_BAR_SIZE 0xda4
-#define MV64360_PCI_0_CPU_BAR_SIZE 0xd28
-#define MV64360_PCI_1_CPU_BAR_SIZE 0xda8
-#define MV64360_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00
-#define MV64360_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80
-#define MV64360_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c
-#define MV64360_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c
-#define MV64360_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c
-#define MV64360_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc
-#define MV64360_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48
-#define MV64360_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8
-#define MV64360_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48
-#define MV64360_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8
-#define MV64360_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c
-#define MV64360_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc
-#define MV64360_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c
-#define MV64360_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc
-#define MV64360_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04
-#define MV64360_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84
-#define MV64360_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08
-#define MV64360_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88
-#define MV64360_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C
-#define MV64360_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C
-#define MV64360_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10
-#define MV64360_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90
-#define MV64360_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50
-#define MV64360_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0
-#define MV64360_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50
-#define MV64360_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0
-#define MV64360_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58
-#define MV64360_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8
-#define MV64360_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54
-#define MV64360_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4
-#define MV64360_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54
-#define MV64360_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4
-#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c
-#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc
-#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60
-#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0
-#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64
-#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4
-#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68
-#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8
-#define MV64360_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c
-#define MV64360_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec
-#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70
-#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0
-#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74
-#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4
-#define MV64360_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00
-#define MV64360_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80
-#define MV64360_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38
-#define MV64360_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8
-#define MV64360_PCI_0_ADDR_DECODE_CONTROL 0xd3c
-#define MV64360_PCI_1_ADDR_DECODE_CONTROL 0xdbc
-#define MV64360_PCI_0_HEADERS_RETARGET_CONTROL 0xF40
-#define MV64360_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0
-#define MV64360_PCI_0_HEADERS_RETARGET_BASE 0xF44
-#define MV64360_PCI_1_HEADERS_RETARGET_BASE 0xFc4
-#define MV64360_PCI_0_HEADERS_RETARGET_HIGH 0xF48
-#define MV64360_PCI_1_HEADERS_RETARGET_HIGH 0xFc8
-
-/***********************************/
-/* PCI Control Register Map */
-/***********************************/
-
-#define MV64360_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20
-#define MV64360_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0
-#define MV64360_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C
-#define MV64360_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C
-#define MV64360_PCI_0_COMMAND 0xc00
-#define MV64360_PCI_1_COMMAND 0xc80
-#define MV64360_PCI_0_MODE 0xd00
-#define MV64360_PCI_1_MODE 0xd80
-#define MV64360_PCI_0_RETRY 0xc04
-#define MV64360_PCI_1_RETRY 0xc84
-#define MV64360_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04
-#define MV64360_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84
-#define MV64360_PCI_0_MSI_TRIGGER_TIMER 0xc38
-#define MV64360_PCI_1_MSI_TRIGGER_TIMER 0xcb8
-#define MV64360_PCI_0_ARBITER_CONTROL 0x1d00
-#define MV64360_PCI_1_ARBITER_CONTROL 0x1d80
-#define MV64360_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08
-#define MV64360_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88
-#define MV64360_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c
-#define MV64360_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c
-#define MV64360_PCI_0_CROSS_BAR_TIMEOUT 0x1d04
-#define MV64360_PCI_1_CROSS_BAR_TIMEOUT 0x1d84
-#define MV64360_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18
-#define MV64360_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98
-#define MV64360_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10
-#define MV64360_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90
-#define MV64360_PCI_0_P2P_CONFIG 0x1d14
-#define MV64360_PCI_1_P2P_CONFIG 0x1d94
-
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04
-#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14
-#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24
-#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34
-#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44
-#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54
-#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58
-
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84
-#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94
-#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
-#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
-#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
-#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
-#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8
-
-/****************************************/
-/* PCI Configuration Access Registers */
-/****************************************/
-
-#define MV64360_PCI_0_CONFIG_ADDR 0xcf8
-#define MV64360_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc
-#define MV64360_PCI_1_CONFIG_ADDR 0xc78
-#define MV64360_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c
-#define MV64360_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34
-#define MV64360_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4
-
-/****************************************/
-/* PCI Error Report Registers */
-/****************************************/
-
-#define MV64360_PCI_0_SERR_MASK 0xc28
-#define MV64360_PCI_1_SERR_MASK 0xca8
-#define MV64360_PCI_0_ERROR_ADDR_LOW 0x1d40
-#define MV64360_PCI_1_ERROR_ADDR_LOW 0x1dc0
-#define MV64360_PCI_0_ERROR_ADDR_HIGH 0x1d44
-#define MV64360_PCI_1_ERROR_ADDR_HIGH 0x1dc4
-#define MV64360_PCI_0_ERROR_ATTRIBUTE 0x1d48
-#define MV64360_PCI_1_ERROR_ATTRIBUTE 0x1dc8
-#define MV64360_PCI_0_ERROR_COMMAND 0x1d50
-#define MV64360_PCI_1_ERROR_COMMAND 0x1dd0
-#define MV64360_PCI_0_ERROR_CAUSE 0x1d58
-#define MV64360_PCI_1_ERROR_CAUSE 0x1dd8
-#define MV64360_PCI_0_ERROR_MASK 0x1d5c
-#define MV64360_PCI_1_ERROR_MASK 0x1ddc
-
-/****************************************/
-/* PCI Debug Registers */
-/****************************************/
-
-#define MV64360_PCI_0_MMASK 0X1D24
-#define MV64360_PCI_1_MMASK 0X1DA4
-
-/*********************************************/
-/* PCI Configuration, Function 0, Registers */
-/*********************************************/
-
-#define MV64360_PCI_DEVICE_AND_VENDOR_ID 0x000
-#define MV64360_PCI_STATUS_AND_COMMAND 0x004
-#define MV64360_PCI_CLASS_CODE_AND_REVISION_ID 0x008
-#define MV64360_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
-
-#define MV64360_PCI_SCS_0_BASE_ADDR_LOW 0x010
-#define MV64360_PCI_SCS_0_BASE_ADDR_HIGH 0x014
-#define MV64360_PCI_SCS_1_BASE_ADDR_LOW 0x018
-#define MV64360_PCI_SCS_1_BASE_ADDR_HIGH 0x01C
-#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020
-#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024
-#define MV64360_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c
-#define MV64360_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030
-#define MV64360_PCI_CAPABILTY_LIST_POINTER 0x034
-#define MV64360_PCI_INTERRUPT_PIN_AND_LINE 0x03C
- /* capability list */
-#define MV64360_PCI_POWER_MANAGEMENT_CAPABILITY 0x040
-#define MV64360_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
-#define MV64360_PCI_VPD_ADDR 0x048
-#define MV64360_PCI_VPD_DATA 0x04c
-#define MV64360_PCI_MSI_MESSAGE_CONTROL 0x050
-#define MV64360_PCI_MSI_MESSAGE_ADDR 0x054
-#define MV64360_PCI_MSI_MESSAGE_UPPER_ADDR 0x058
-#define MV64360_PCI_MSI_MESSAGE_DATA 0x05c
-#define MV64360_PCI_X_COMMAND 0x060
-#define MV64360_PCI_X_STATUS 0x064
-#define MV64360_PCI_COMPACT_PCI_HOT_SWAP 0x068
-
-/***********************************************/
-/* PCI Configuration, Function 1, Registers */
-/***********************************************/
-
-#define MV64360_PCI_SCS_2_BASE_ADDR_LOW 0x110
-#define MV64360_PCI_SCS_2_BASE_ADDR_HIGH 0x114
-#define MV64360_PCI_SCS_3_BASE_ADDR_LOW 0x118
-#define MV64360_PCI_SCS_3_BASE_ADDR_HIGH 0x11c
-#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120
-#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124
-
-/***********************************************/
-/* PCI Configuration, Function 2, Registers */
-/***********************************************/
-
-#define MV64360_PCI_DEVCS_0_BASE_ADDR_LOW 0x210
-#define MV64360_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214
-#define MV64360_PCI_DEVCS_1_BASE_ADDR_LOW 0x218
-#define MV64360_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c
-#define MV64360_PCI_DEVCS_2_BASE_ADDR_LOW 0x220
-#define MV64360_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224
-
-/***********************************************/
-/* PCI Configuration, Function 3, Registers */
-/***********************************************/
-
-#define MV64360_PCI_DEVCS_3_BASE_ADDR_LOW 0x310
-#define MV64360_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314
-#define MV64360_PCI_BOOT_CS_BASE_ADDR_LOW 0x318
-#define MV64360_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c
-#define MV64360_PCI_CPU_BASE_ADDR_LOW 0x220
-#define MV64360_PCI_CPU_BASE_ADDR_HIGH 0x224
-
-/***********************************************/
-/* PCI Configuration, Function 4, Registers */
-/***********************************************/
-
-#define MV64360_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410
-#define MV64360_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414
-#define MV64360_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418
-#define MV64360_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c
-#define MV64360_PCI_P2P_I_O_BASE_ADDR 0x420
-#define MV64360_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424
-
-/****************************************/
-/* Messaging Unit Registers (I20) */
-/****************************************/
-
-#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010
-#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C
-#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020
-#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024
-#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028
-#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C
-#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030
-#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034
-#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040
-#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044
-#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050
-#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054
-#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060
-#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064
-#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068
-#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C
-#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070
-#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074
-#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8
-#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC
-
-#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090
-#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C
-#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0
-#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4
-#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8
-#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC
-#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0
-#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4
-#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0
-#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4
-#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0
-#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4
-#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0
-#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4
-#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8
-#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC
-#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0
-#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4
-#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078
-#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C
-
-#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10
-#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C
-#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20
-#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24
-#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28
-#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C
-#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30
-#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34
-#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40
-#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44
-#define MV64360_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50
-#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54
-#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60
-#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64
-#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68
-#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C
-#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70
-#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74
-#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8
-#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC
-#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90
-#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C
-#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0
-#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4
-#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8
-#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC
-#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0
-#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4
-#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0
-#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4
-#define MV64360_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0
-#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4
-#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0
-#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4
-#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8
-#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC
-#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0
-#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4
-#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78
-#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C
-
-/****************************************/
-/* Ethernet Unit Registers */
-/****************************************/
-
-#define MV64360_ETH_PHY_ADDR_REG 0x2000
-#define MV64360_ETH_SMI_REG 0x2004
-#define MV64360_ETH_UNIT_DEFAULT_ADDR_REG 0x2008
-#define MV64360_ETH_UNIT_DEFAULTID_REG 0x200c
-#define MV64360_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080
-#define MV64360_ETH_UNIT_INTERRUPT_MASK_REG 0x2084
-#define MV64360_ETH_UNIT_INTERNAL_USE_REG 0x24fc
-#define MV64360_ETH_UNIT_ERROR_ADDR_REG 0x2094
-#define MV64360_ETH_BAR_0 0x2200
-#define MV64360_ETH_BAR_1 0x2208
-#define MV64360_ETH_BAR_2 0x2210
-#define MV64360_ETH_BAR_3 0x2218
-#define MV64360_ETH_BAR_4 0x2220
-#define MV64360_ETH_BAR_5 0x2228
-#define MV64360_ETH_SIZE_REG_0 0x2204
-#define MV64360_ETH_SIZE_REG_1 0x220c
-#define MV64360_ETH_SIZE_REG_2 0x2214
-#define MV64360_ETH_SIZE_REG_3 0x221c
-#define MV64360_ETH_SIZE_REG_4 0x2224
-#define MV64360_ETH_SIZE_REG_5 0x222c
-#define MV64360_ETH_HEADERS_RETARGET_BASE_REG 0x2230
-#define MV64360_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234
-#define MV64360_ETH_HIGH_ADDR_REMAP_REG_0 0x2280
-#define MV64360_ETH_HIGH_ADDR_REMAP_REG_1 0x2284
-#define MV64360_ETH_HIGH_ADDR_REMAP_REG_2 0x2288
-#define MV64360_ETH_HIGH_ADDR_REMAP_REG_3 0x228c
-#define MV64360_ETH_BASE_ADDR_ENABLE_REG 0x2290
-#define MV64360_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2))
-#define MV64360_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7))
-#define MV64360_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10))
-#define MV64360_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10))
-#define MV64360_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10))
-#define MV64360_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10))
-#define MV64360_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10))
-#define MV64360_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10))
-#define MV64360_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10))
-#define MV64360_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10))
-#define MV64360_ETH_DSCP_0(port) (0x2420 + (port<<10))
-#define MV64360_ETH_DSCP_1(port) (0x2424 + (port<<10))
-#define MV64360_ETH_DSCP_2(port) (0x2428 + (port<<10))
-#define MV64360_ETH_DSCP_3(port) (0x242c + (port<<10))
-#define MV64360_ETH_DSCP_4(port) (0x2430 + (port<<10))
-#define MV64360_ETH_DSCP_5(port) (0x2434 + (port<<10))
-#define MV64360_ETH_DSCP_6(port) (0x2438 + (port<<10))
-#define MV64360_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10))
-#define MV64360_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10))
-#define MV64360_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10))
-#define MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10))
-#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10))
-#define MV64360_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10))
-#define MV64360_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10))
-#define MV64360_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10))
-#define MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10))
-#define MV64360_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10))
-#define MV64360_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10))
-#define MV64360_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
-#define MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
-#define MV64360_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
-#define MV64360_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10)
-#define MV64360_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
-#define MV64360_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
-#define MV64360_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
-#define MV64360_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10))
-#define MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10))
-#define MV64360_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10))
-#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10))
-#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10))
-#define MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10))
-#define MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
-#define MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
-
-/*******************************************/
-/* CUNIT Registers */
-/*******************************************/
-
- /* Address Decoding Register Map */
-
-#define MV64360_CUNIT_BASE_ADDR_REG0 0xf200
-#define MV64360_CUNIT_BASE_ADDR_REG1 0xf208
-#define MV64360_CUNIT_BASE_ADDR_REG2 0xf210
-#define MV64360_CUNIT_BASE_ADDR_REG3 0xf218
-#define MV64360_CUNIT_SIZE0 0xf204
-#define MV64360_CUNIT_SIZE1 0xf20c
-#define MV64360_CUNIT_SIZE2 0xf214
-#define MV64360_CUNIT_SIZE3 0xf21c
-#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240
-#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244
-#define MV64360_CUNIT_BASE_ADDR_ENABLE_REG 0xf250
-#define MV64360_MPSC0_ACCESS_PROTECTION_REG 0xf254
-#define MV64360_MPSC1_ACCESS_PROTECTION_REG 0xf258
-#define MV64360_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C
-
- /* Error Report Registers */
-
-#define MV64360_CUNIT_INTERRUPT_CAUSE_REG 0xf310
-#define MV64360_CUNIT_INTERRUPT_MASK_REG 0xf314
-#define MV64360_CUNIT_ERROR_ADDR 0xf318
-
- /* Cunit Control Registers */
-
-#define MV64360_CUNIT_ARBITER_CONTROL_REG 0xf300
-#define MV64360_CUNIT_CONFIG_REG 0xb40c
-#define MV64360_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304
-
- /* Cunit Debug Registers */
-
-#define MV64360_CUNIT_DEBUG_LOW 0xf340
-#define MV64360_CUNIT_DEBUG_HIGH 0xf344
-#define MV64360_CUNIT_MMASK 0xf380
-
- /* Cunit Base Address Enable Window Bits*/
-#define MV64360_CUNIT_BASE_ADDR_WIN_0_BIT 0x0
-#define MV64360_CUNIT_BASE_ADDR_WIN_1_BIT 0x1
-#define MV64360_CUNIT_BASE_ADDR_WIN_2_BIT 0x2
-#define MV64360_CUNIT_BASE_ADDR_WIN_3_BIT 0x3
-
- /* MPSCs Clocks Routing Registers */
-
-#define MV64360_MPSC_ROUTING_REG 0xb400
-#define MV64360_MPSC_RX_CLOCK_ROUTING_REG 0xb404
-#define MV64360_MPSC_TX_CLOCK_ROUTING_REG 0xb408
-
- /* MPSCs Interrupts Registers */
-
-#define MV64360_MPSC_CAUSE_REG(port) (0xb804 + (port<<3))
-#define MV64360_MPSC_MASK_REG(port) (0xb884 + (port<<3))
-
-#define MV64360_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12))
-#define MV64360_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12))
-#define MV64360_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12))
-
- /* MPSC0 Registers */
-
-
-/***************************************/
-/* SDMA Registers */
-/***************************************/
-
-#define MV64360_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13))
-#define MV64360_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13))
-#define MV64360_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13))
-#define MV64360_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13))
-#define MV64360_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13))
-
-#define MV64360_SDMA_CAUSE_REG 0xb800
-#define MV64360_SDMA_MASK_REG 0xb880
-
-
-/****************************************/
-/* SDMA Address Space Targets */
-/****************************************/
-
-#define MV64360_SDMA_DRAM_CS_0_TARGET 0x0e00
-#define MV64360_SDMA_DRAM_CS_1_TARGET 0x0d00
-#define MV64360_SDMA_DRAM_CS_2_TARGET 0x0b00
-#define MV64360_SDMA_DRAM_CS_3_TARGET 0x0700
-
-#define MV64360_SDMA_DEV_CS_0_TARGET 0x1e01
-#define MV64360_SDMA_DEV_CS_1_TARGET 0x1d01
-#define MV64360_SDMA_DEV_CS_2_TARGET 0x1b01
-#define MV64360_SDMA_DEV_CS_3_TARGET 0x1701
-
-#define MV64360_SDMA_BOOT_CS_TARGET 0x0f00
-
-#define MV64360_SDMA_SRAM_TARGET 0x0003
-#define MV64360_SDMA_60X_BUS_TARGET 0x4003
-
-#define MV64360_PCI_0_TARGET 0x0003
-#define MV64360_PCI_1_TARGET 0x0004
-
-
-/* Devices BAR and size registers */
-
-#define MV64360_DEV_CS0_BASE_ADDR 0x028
-#define MV64360_DEV_CS0_SIZE 0x030
-#define MV64360_DEV_CS1_BASE_ADDR 0x228
-#define MV64360_DEV_CS1_SIZE 0x230
-#define MV64360_DEV_CS2_BASE_ADDR 0x248
-#define MV64360_DEV_CS2_SIZE 0x250
-#define MV64360_DEV_CS3_BASE_ADDR 0x038
-#define MV64360_DEV_CS3_SIZE 0x040
-#define MV64360_BOOTCS_BASE_ADDR 0x238
-#define MV64360_BOOTCS_SIZE 0x240
-
-/* SDMA Window access protection */
-#define MV64360_SDMA_WIN_ACCESS_NOT_ALLOWED 0
-#define MV64360_SDMA_WIN_ACCESS_READ_ONLY 1
-#define MV64360_SDMA_WIN_ACCESS_FULL 2
-
-/* BRG Interrupts */
-
-#define MV64360_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3))
-#define MV64360_BRG_BAUDE_TUNING_REG(brg) (0xb204 + (brg<<3))
-#define MV64360_BRG_CAUSE_REG 0xb834
-#define MV64360_BRG_MASK_REG 0xb8b4
-
-/****************************************/
-/* DMA Channel Control */
-/****************************************/
-
-#define MV64360_DMA_CHANNEL0_CONTROL 0x840
-#define MV64360_DMA_CHANNEL0_CONTROL_HIGH 0x880
-#define MV64360_DMA_CHANNEL1_CONTROL 0x844
-#define MV64360_DMA_CHANNEL1_CONTROL_HIGH 0x884
-#define MV64360_DMA_CHANNEL2_CONTROL 0x848
-#define MV64360_DMA_CHANNEL2_CONTROL_HIGH 0x888
-#define MV64360_DMA_CHANNEL3_CONTROL 0x84C
-#define MV64360_DMA_CHANNEL3_CONTROL_HIGH 0x88C
-
-
-/****************************************/
-/* IDMA Registers */
-/****************************************/
-
-#define MV64360_DMA_CHANNEL0_BYTE_COUNT 0x800
-#define MV64360_DMA_CHANNEL1_BYTE_COUNT 0x804
-#define MV64360_DMA_CHANNEL2_BYTE_COUNT 0x808
-#define MV64360_DMA_CHANNEL3_BYTE_COUNT 0x80C
-#define MV64360_DMA_CHANNEL0_SOURCE_ADDR 0x810
-#define MV64360_DMA_CHANNEL1_SOURCE_ADDR 0x814
-#define MV64360_DMA_CHANNEL2_SOURCE_ADDR 0x818
-#define MV64360_DMA_CHANNEL3_SOURCE_ADDR 0x81c
-#define MV64360_DMA_CHANNEL0_DESTINATION_ADDR 0x820
-#define MV64360_DMA_CHANNEL1_DESTINATION_ADDR 0x824
-#define MV64360_DMA_CHANNEL2_DESTINATION_ADDR 0x828
-#define MV64360_DMA_CHANNEL3_DESTINATION_ADDR 0x82C
-#define MV64360_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830
-#define MV64360_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834
-#define MV64360_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838
-#define MV64360_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C
-#define MV64360_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870
-#define MV64360_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874
-#define MV64360_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878
-#define MV64360_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C
-
- /* IDMA Address Decoding Base Address Registers */
-
-#define MV64360_DMA_BASE_ADDR_REG0 0xa00
-#define MV64360_DMA_BASE_ADDR_REG1 0xa08
-#define MV64360_DMA_BASE_ADDR_REG2 0xa10
-#define MV64360_DMA_BASE_ADDR_REG3 0xa18
-#define MV64360_DMA_BASE_ADDR_REG4 0xa20
-#define MV64360_DMA_BASE_ADDR_REG5 0xa28
-#define MV64360_DMA_BASE_ADDR_REG6 0xa30
-#define MV64360_DMA_BASE_ADDR_REG7 0xa38
-
- /* IDMA Address Decoding Size Address Register */
-
-#define MV64360_DMA_SIZE_REG0 0xa04
-#define MV64360_DMA_SIZE_REG1 0xa0c
-#define MV64360_DMA_SIZE_REG2 0xa14
-#define MV64360_DMA_SIZE_REG3 0xa1c
-#define MV64360_DMA_SIZE_REG4 0xa24
-#define MV64360_DMA_SIZE_REG5 0xa2c
-#define MV64360_DMA_SIZE_REG6 0xa34
-#define MV64360_DMA_SIZE_REG7 0xa3C
-
- /* IDMA Address Decoding High Address Remap and Access
- Protection Registers */
-
-#define MV64360_DMA_HIGH_ADDR_REMAP_REG0 0xa60
-#define MV64360_DMA_HIGH_ADDR_REMAP_REG1 0xa64
-#define MV64360_DMA_HIGH_ADDR_REMAP_REG2 0xa68
-#define MV64360_DMA_HIGH_ADDR_REMAP_REG3 0xa6C
-#define MV64360_DMA_BASE_ADDR_ENABLE_REG 0xa80
-#define MV64360_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70
-#define MV64360_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74
-#define MV64360_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78
-#define MV64360_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c
-#define MV64360_DMA_ARBITER_CONTROL 0x860
-#define MV64360_DMA_CROSS_BAR_TIMEOUT 0x8d0
-
- /* IDMA Headers Retarget Registers */
-
-#define MV64360_DMA_HEADERS_RETARGET_CONTROL 0xa84
-#define MV64360_DMA_HEADERS_RETARGET_BASE 0xa88
-
- /* IDMA Interrupt Register */
-
-#define MV64360_DMA_INTERRUPT_CAUSE_REG 0x8c0
-#define MV64360_DMA_INTERRUPT_CAUSE_MASK 0x8c4
-#define MV64360_DMA_ERROR_ADDR 0x8c8
-#define MV64360_DMA_ERROR_SELECT 0x8cc
-
- /* IDMA Debug Register ( for internal use ) */
-
-#define MV64360_DMA_DEBUG_LOW 0x8e0
-#define MV64360_DMA_DEBUG_HIGH 0x8e4
-#define MV64360_DMA_SPARE 0xA8C
-
-/****************************************/
-/* Timer_Counter */
-/****************************************/
-
-#define MV64360_TIMER_COUNTER0 0x850
-#define MV64360_TIMER_COUNTER1 0x854
-#define MV64360_TIMER_COUNTER2 0x858
-#define MV64360_TIMER_COUNTER3 0x85C
-#define MV64360_TIMER_COUNTER_0_3_CONTROL 0x864
-#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868
-#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c
-
-/****************************************/
-/* Watchdog registers */
-/****************************************/
-
-#define MV64360_WATCHDOG_CONFIG_REG 0xb410
-#define MV64360_WATCHDOG_VALUE_REG 0xb414
-
-/****************************************/
-/* I2C Registers */
-/****************************************/
-
-#define MV64360_I2C_SLAVE_ADDR 0xc000
-#define MV64360_I2C_EXTENDED_SLAVE_ADDR 0xc010
-#define MV64360_I2C_DATA 0xc004
-#define MV64360_I2C_CONTROL 0xc008
-#define MV64360_I2C_STATUS_BAUDE_RATE 0xc00C
-#define MV64360_I2C_SOFT_RESET 0xc01c
-
-/****************************************/
-/* GPP Interface Registers */
-/****************************************/
-
-#define MV64360_GPP_IO_CONTROL 0xf100
-#define MV64360_GPP_LEVEL_CONTROL 0xf110
-#define MV64360_GPP_VALUE 0xf104
-#define MV64360_GPP_INTERRUPT_CAUSE 0xf108
-#define MV64360_GPP_INTERRUPT_MASK0 0xf10c
-#define MV64360_GPP_INTERRUPT_MASK1 0xf114
-#define MV64360_GPP_VALUE_SET 0xf118
-#define MV64360_GPP_VALUE_CLEAR 0xf11c
-
-/****************************************/
-/* Interrupt Controller Registers */
-/****************************************/
-
-/****************************************/
-/* Interrupts */
-/****************************************/
-
-#define MV64360_MAIN_INTERRUPT_CAUSE_LOW 0x004
-#define MV64360_MAIN_INTERRUPT_CAUSE_HIGH 0x00c
-#define MV64360_CPU_INTERRUPT0_MASK_LOW 0x014
-#define MV64360_CPU_INTERRUPT0_MASK_HIGH 0x01c
-#define MV64360_CPU_INTERRUPT0_SELECT_CAUSE 0x024
-#define MV64360_CPU_INTERRUPT1_MASK_LOW 0x034
-#define MV64360_CPU_INTERRUPT1_MASK_HIGH 0x03c
-#define MV64360_CPU_INTERRUPT1_SELECT_CAUSE 0x044
-#define MV64360_INTERRUPT0_MASK_0_LOW 0x054
-#define MV64360_INTERRUPT0_MASK_0_HIGH 0x05c
-#define MV64360_INTERRUPT0_SELECT_CAUSE 0x064
-#define MV64360_INTERRUPT1_MASK_0_LOW 0x074
-#define MV64360_INTERRUPT1_MASK_0_HIGH 0x07c
-#define MV64360_INTERRUPT1_SELECT_CAUSE 0x084
-
-/****************************************/
-/* MPP Interface Registers */
-/****************************************/
-
-#define MV64360_MPP_CONTROL0 0xf000
-#define MV64360_MPP_CONTROL1 0xf004
-#define MV64360_MPP_CONTROL2 0xf008
-#define MV64360_MPP_CONTROL3 0xf00c
-
-/****************************************/
-/* Serial Initialization registers */
-/****************************************/
-
-#define MV64360_SERIAL_INIT_LAST_DATA 0xf324
-#define MV64360_SERIAL_INIT_CONTROL 0xf328
-#define MV64360_SERIAL_INIT_STATUS 0xf32c
-
-
-#endif /* __INCgt64360rh */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-/* PCI.c - PCI functions */
-
-
-#include <common.h>
-#include <pci.h>
-
-#include "../include/pci.h"
-
-#undef DEBUG
-#undef IDE_SET_NATIVE_MODE
-static unsigned int local_buses[] = { 0, 0 };
-
-static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
- {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
- {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
-};
-
-
-#ifdef DEBUG
-static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
-static void gt_pci_bus_mode_display (PCI_HOST host)
-{
- unsigned int mode;
-
-
- mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
- switch (mode) {
- case 0:
- printf ("PCI %d bus mode: Conventional PCI\n", host);
- break;
- case 1:
- printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
- break;
- case 2:
- printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
- break;
- case 3:
- printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
- break;
- default:
- printf ("Unknown BUS %d\n", mode);
- }
-}
-#endif
-
-static const unsigned int pci_p2p_configuration_reg[] = {
- PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
-};
-
-static const unsigned int pci_configuration_address[] = {
- PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
-};
-
-static const unsigned int pci_configuration_data[] = {
- PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
- PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
-};
-
-static const unsigned int pci_error_cause_reg[] = {
- PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
-};
-
-static const unsigned int pci_arbiter_control[] = {
- PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
-};
-
-static const unsigned int pci_address_space_en[] = {
- PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
-};
-
-static const unsigned int pci_snoop_control_base_0_low[] = {
- PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
-};
-static const unsigned int pci_snoop_control_top_0[] = {
- PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
-};
-
-static const unsigned int pci_access_control_base_0_low[] = {
- PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
-};
-static const unsigned int pci_access_control_top_0[] = {
- PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
-};
-
-static const unsigned int pci_scs_bank_size[2][4] = {
- {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
- PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
- {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
- PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
-};
-
-static const unsigned int pci_p2p_configuration[] = {
- PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
-};
-
-
-/********************************************************************
-* pciWriteConfigReg - Write to a PCI configuration register
-* - Make sure the GT is configured as a master before writing
-* to another device on the PCI.
-* - The function takes care of Big/Little endian conversion.
-*
-*
-* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec
-* (or any other PCI device spec)
-* pciDevNum: The device number needs to be addressed.
-*
-* Configuration Address 0xCF8:
-*
-* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
-* |congif|Reserved| Bus |Device|Function|Register|00|
-* |Enable| |Number|Number| Number | Number | | <=field Name
-*
-*********************************************************************/
-void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
- unsigned int pciDevNum, unsigned int data)
-{
- volatile unsigned int DataForAddrReg;
- unsigned int functionNum;
- unsigned int busNum = 0;
- unsigned int addr;
-
- if (pciDevNum > 32) /* illegal device Number */
- return;
- if (pciDevNum == SELF) { /* configure our configuration space. */
- pciDevNum =
- (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
- 0x1f;
- busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
- 0xff0000;
- }
- functionNum = regOffset & 0x00000700;
- pciDevNum = pciDevNum << 11;
- regOffset = regOffset & 0xfc;
- DataForAddrReg =
- (regOffset | pciDevNum | functionNum | busNum) | BIT31;
- GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
- GT_REG_READ (pci_configuration_address[host], &addr);
- if (addr != DataForAddrReg)
- return;
- GT_REG_WRITE (pci_configuration_data[host], data);
-}
-
-/********************************************************************
-* pciReadConfigReg - Read from a PCI0 configuration register
-* - Make sure the GT is configured as a master before reading
-* from another device on the PCI.
-* - The function takes care of Big/Little endian conversion.
-* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
-* spec)
-* pciDevNum: The device number needs to be addressed.
-* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
-* cause register to make sure the data is valid
-*
-* Configuration Address 0xCF8:
-*
-* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
-* |congif|Reserved| Bus |Device|Function|Register|00|
-* |Enable| |Number|Number| Number | Number | | <=field Name
-*
-*********************************************************************/
-unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
- unsigned int pciDevNum)
-{
- volatile unsigned int DataForAddrReg;
- unsigned int data;
- unsigned int functionNum;
- unsigned int busNum = 0;
-
- if (pciDevNum > 32) /* illegal device Number */
- return 0xffffffff;
- if (pciDevNum == SELF) { /* configure our configuration space. */
- pciDevNum =
- (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
- 0x1f;
- busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
- 0xff0000;
- }
- functionNum = regOffset & 0x00000700;
- pciDevNum = pciDevNum << 11;
- regOffset = regOffset & 0xfc;
- DataForAddrReg =
- (regOffset | pciDevNum | functionNum | busNum) | BIT31;
- GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
- GT_REG_READ (pci_configuration_address[host], &data);
- if (data != DataForAddrReg)
- return 0xffffffff;
- GT_REG_READ (pci_configuration_data[host], &data);
- return data;
-}
-
-/********************************************************************
-* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
-* the agent is placed on another Bus. For more
-* information read P2P in the PCI spec.
-*
-* Inputs: unsigned int regOffset - The register offset as it apears in the
-* GT spec (or any other PCI device spec).
-* unsigned int pciDevNum - The device number needs to be addressed.
-* unsigned int busNum - On which bus does the Target agent connect
-* to.
-* unsigned int data - data to be written.
-*
-* Configuration Address 0xCF8:
-*
-* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
-* |congif|Reserved| Bus |Device|Function|Register|01|
-* |Enable| |Number|Number| Number | Number | | <=field Name
-*
-* The configuration Address is configure as type-I (bits[1:0] = '01') due to
-* PCI spec referring to P2P.
-*
-*********************************************************************/
-void pciOverBridgeWriteConfigReg (PCI_HOST host,
- unsigned int regOffset,
- unsigned int pciDevNum,
- unsigned int busNum, unsigned int data)
-{
- unsigned int DataForReg;
- unsigned int functionNum;
-
- functionNum = regOffset & 0x00000700;
- pciDevNum = pciDevNum << 11;
- regOffset = regOffset & 0xff;
- busNum = busNum << 16;
- if (pciDevNum == SELF) { /* This board */
- DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
- } else {
- DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
- BIT31 | BIT0;
- }
- GT_REG_WRITE (pci_configuration_address[host], DataForReg);
- GT_REG_WRITE (pci_configuration_data[host], data);
-}
-
-
-/********************************************************************
-* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where
-* the agent target locate on another PCI bus.
-* - Make sure the GT is configured as a master
-* before reading from another device on the PCI.
-* - The function takes care of Big/Little endian
-* conversion.
-* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
-* spec). (configuration register offset.)
-* pciDevNum: The device number needs to be addressed.
-* busNum: the Bus number where the agent is place.
-* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
-* cause register to make sure the data is valid
-*
-* Configuration Address 0xCF8:
-*
-* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
-* |congif|Reserved| Bus |Device|Function|Register|01|
-* |Enable| |Number|Number| Number | Number | | <=field Name
-*
-*********************************************************************/
-unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
- unsigned int regOffset,
- unsigned int pciDevNum,
- unsigned int busNum)
-{
- unsigned int DataForReg;
- unsigned int data;
- unsigned int functionNum;
-
- functionNum = regOffset & 0x00000700;
- pciDevNum = pciDevNum << 11;
- regOffset = regOffset & 0xff;
- busNum = busNum << 16;
- if (pciDevNum == SELF) { /* This board */
- DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
- } else { /* agent on another bus */
-
- DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
- BIT0 | BIT31;
- }
- GT_REG_WRITE (pci_configuration_address[host], DataForReg);
- GT_REG_READ (pci_configuration_data[host], &data);
- return data;
-}
-
-
-/********************************************************************
-* pciGetRegOffset - Gets the register offset for this region config.
-*
-* INPUT: Bus, Region - The bus and region we ask for its base address.
-* OUTPUT: N/A
-* RETURNS: PCI register base address
-*********************************************************************/
-static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
-{
- switch (host) {
- case PCI_HOST0:
- switch (region) {
- case PCI_IO:
- return PCI_0I_O_LOW_DECODE_ADDRESS;
- case PCI_REGION0:
- return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
- case PCI_REGION1:
- return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
- case PCI_REGION2:
- return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
- case PCI_REGION3:
- return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
- }
- case PCI_HOST1:
- switch (region) {
- case PCI_IO:
- return PCI_1I_O_LOW_DECODE_ADDRESS;
- case PCI_REGION0:
- return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
- case PCI_REGION1:
- return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
- case PCI_REGION2:
- return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
- case PCI_REGION3:
- return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
- }
- }
- return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
-}
-
-static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
-{
- switch (host) {
- case PCI_HOST0:
- switch (region) {
- case PCI_IO:
- return PCI_0I_O_ADDRESS_REMAP;
- case PCI_REGION0:
- return PCI_0MEMORY0_ADDRESS_REMAP;
- case PCI_REGION1:
- return PCI_0MEMORY1_ADDRESS_REMAP;
- case PCI_REGION2:
- return PCI_0MEMORY2_ADDRESS_REMAP;
- case PCI_REGION3:
- return PCI_0MEMORY3_ADDRESS_REMAP;
- }
- case PCI_HOST1:
- switch (region) {
- case PCI_IO:
- return PCI_1I_O_ADDRESS_REMAP;
- case PCI_REGION0:
- return PCI_1MEMORY0_ADDRESS_REMAP;
- case PCI_REGION1:
- return PCI_1MEMORY1_ADDRESS_REMAP;
- case PCI_REGION2:
- return PCI_1MEMORY2_ADDRESS_REMAP;
- case PCI_REGION3:
- return PCI_1MEMORY3_ADDRESS_REMAP;
- }
- }
- return PCI_0MEMORY0_ADDRESS_REMAP;
-}
-
-/********************************************************************
-* pciGetBaseAddress - Gets the base address of a PCI.
-* - If the PCI size is 0 then this base address has no meaning!!!
-*
-*
-* INPUT: Bus, Region - The bus and region we ask for its base address.
-* OUTPUT: N/A
-* RETURNS: PCI base address.
-*********************************************************************/
-unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
-{
- unsigned int regBase;
- unsigned int regEnd;
- unsigned int regOffset = pciGetRegOffset (host, region);
-
- GT_REG_READ (regOffset, ®Base);
- GT_REG_READ (regOffset + 8, ®End);
-
- if (regEnd <= regBase)
- return 0xffffffff; /* ERROR !!! */
-
- regBase = regBase << 16;
- return regBase;
-}
-
-bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
- unsigned int bankBase, unsigned int bankLength)
-{
- unsigned int low = 0xfff;
- unsigned int high = 0x0;
- unsigned int regOffset = pciGetRegOffset (host, region);
- unsigned int remapOffset = pciGetRemapOffset (host, region);
-
- if (bankLength != 0) {
- low = (bankBase >> 16) & 0xffff;
- high = ((bankBase + bankLength) >> 16) - 1;
- }
-
- GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */
- GT_REG_WRITE (regOffset + 8, high);
-
- if (bankLength != 0) { /* must do AFTER writing maps */
- GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only.
- dont support upper 32
- in this driver */
- }
- return true;
-}
-
-unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
-{
- unsigned int low;
- unsigned int regOffset = pciGetRegOffset (host, region);
-
- GT_REG_READ (regOffset, &low);
- return (low & 0xffff) << 16;
-}
-
-unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
-{
- unsigned int low, high;
- unsigned int regOffset = pciGetRegOffset (host, region);
-
- GT_REG_READ (regOffset, &low);
- GT_REG_READ (regOffset + 8, &high);
- return ((high & 0xffff) + 1) << 16;
-}
-
-
-/* ronen - 7/Dec/03*/
-/********************************************************************
-* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
-* Inputs: one of the PCI BAR
-*********************************************************************/
-void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
-{
- RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
-}
-
-void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
-{
- SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
-}
-
-/********************************************************************
-* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
-*
-* Inputs: base and size of PCI SCS
-*********************************************************************/
-void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
- unsigned int pciDramBase, unsigned int pciDramSize)
-{
- /*ronen different function for 3rd bank. */
- unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
-
- pciDramBase = pciDramBase & 0xfffff000;
- pciDramBase = pciDramBase | (pciReadConfigReg (host,
- PCI_SCS_0_BASE_ADDRESS
- + offset,
- SELF) & 0x00000fff);
- pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
- pciDramBase);
- if (pciDramSize == 0)
- pciDramSize++;
- GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
- gtPciEnableInternalBAR (host, bank);
-}
-
-/********************************************************************
-* pciSetRegionFeatures - This function modifys one of the 8 regions with
-* feature bits given as an input.
-* - Be advised to check the spec before modifying them.
-* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
-* unsigned int features - See file: pci.h there are defintion for those
-* region features.
-* unsigned int baseAddress - The region base Address.
-* unsigned int topAddress - The region top Address.
-* Returns: false if one of the parameters is erroneous true otherwise.
-*********************************************************************/
-bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
- unsigned int features, unsigned int baseAddress,
- unsigned int regionLength)
-{
- unsigned int accessLow;
- unsigned int accessHigh;
- unsigned int accessTop = baseAddress + regionLength;
-
- if (regionLength == 0) { /* close the region. */
- pciDisableAccessRegion (host, region);
- return true;
- }
- /* base Address is store is bits [11:0] */
- accessLow = (baseAddress & 0xfff00000) >> 20;
- /* All the features are update according to the defines in pci.h (to be on
- the safe side we disable bits: [11:0] */
- accessLow = accessLow | (features & 0xfffff000);
- /* write to the Low Access Region register */
- GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
- accessLow);
-
- accessHigh = (accessTop & 0xfff00000) >> 20;
-
- /* write to the High Access Region register */
- GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
- accessHigh - 1);
- return true;
-}
-
-/********************************************************************
-* pciDisableAccessRegion - Disable The given Region by writing MAX size
-* to its low Address and MIN size to its high Address.
-*
-* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled.
-* Returns: N/A.
-*********************************************************************/
-void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
-{
- /* writing back the registers default values. */
- GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
- 0x01001fff);
- GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
-}
-
-/********************************************************************
-* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
-*
-* Inputs: N/A
-* Returns: true.
-*********************************************************************/
-bool pciArbiterEnable (PCI_HOST host)
-{
- unsigned int regData;
-
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
- return true;
-}
-
-/********************************************************************
-* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
-*
-* Inputs: N/A
-* Returns: true
-*********************************************************************/
-bool pciArbiterDisable (PCI_HOST host)
-{
- unsigned int regData;
-
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
- return true;
-}
-
-/********************************************************************
-* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
-*
-* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent.
-* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
-* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
-* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
-* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
-* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
-* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
-* Returns: true
-*********************************************************************/
-bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
- PCI_AGENT_PRIO externalAgent0,
- PCI_AGENT_PRIO externalAgent1,
- PCI_AGENT_PRIO externalAgent2,
- PCI_AGENT_PRIO externalAgent3,
- PCI_AGENT_PRIO externalAgent4,
- PCI_AGENT_PRIO externalAgent5)
-{
- unsigned int regData;
- unsigned int writeData;
-
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- writeData = (internalAgent << 7) + (externalAgent0 << 8) +
- (externalAgent1 << 9) + (externalAgent2 << 10) +
- (externalAgent3 << 11) + (externalAgent4 << 12) +
- (externalAgent5 << 13);
- regData = (regData & 0xffffc07f) | writeData;
- GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
- return true;
-}
-
-/********************************************************************
-* pciParkingDisable - Park on last option disable, with this function you can
-* disable the park on last mechanism for each agent.
-* disabling this option for all agents results parking
-* on the internal master.
-*
-* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent.
-* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
-* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
-* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
-* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
-* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
-* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
-* Returns: true
-*********************************************************************/
-bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
- PCI_AGENT_PARK externalAgent0,
- PCI_AGENT_PARK externalAgent1,
- PCI_AGENT_PARK externalAgent2,
- PCI_AGENT_PARK externalAgent3,
- PCI_AGENT_PARK externalAgent4,
- PCI_AGENT_PARK externalAgent5)
-{
- unsigned int regData;
- unsigned int writeData;
-
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- writeData = (internalAgent << 14) + (externalAgent0 << 15) +
- (externalAgent1 << 16) + (externalAgent2 << 17) +
- (externalAgent3 << 18) + (externalAgent4 << 19) +
- (externalAgent5 << 20);
- regData = (regData & ~(0x7f << 14)) | writeData;
- GT_REG_WRITE (pci_arbiter_control[host], regData);
- return true;
-}
-
-/********************************************************************
-* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
-* respond to grant assertion within a window specified in
-* the input value: 'brokenValue'.
-*
-* Inputs: unsigned char brokenValue - A value which limits the Master to hold the
-* grant without asserting frame.
-* Returns: Error for illegal broken value otherwise true.
-*********************************************************************/
-bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
-{
- unsigned int data;
- unsigned int regData;
-
- if (brokenValue > 0xf)
- return false; /* brokenValue must be 4 bit */
- data = brokenValue << 3;
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- regData = (regData & 0xffffff87) | data;
- GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
- return true;
-}
-
-/********************************************************************
-* pciDisableBrokenAgentDetection - This function disable the Broken agent
-* Detection mechanism.
-* NOTE: This operation may cause a dead lock on the
-* pci0 arbitration.
-*
-* Inputs: N/A
-* Returns: true.
-*********************************************************************/
-bool pciDisableBrokenAgentDetection (PCI_HOST host)
-{
- unsigned int regData;
-
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- regData = regData & 0xfffffffd;
- GT_REG_WRITE (pci_arbiter_control[host], regData);
- return true;
-}
-
-/********************************************************************
-* pciP2PConfig - This function set the PCI_n P2P configurate.
-* For more information on the P2P read PCI spec.
-*
-* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
-* Boundry.
-* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
-* Boundry.
-* unsigned int busNum - The CPI bus number to which the PCI interface
-* is connected.
-* unsigned int devNum - The PCI interface's device number.
-*
-* Returns: true.
-*********************************************************************/
-bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
- unsigned int SecondBusHigh,
- unsigned int busNum, unsigned int devNum)
-{
- unsigned int regData;
-
- regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
- ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
- GT_REG_WRITE (pci_p2p_configuration[host], regData);
- return true;
-}
-
-/********************************************************************
-* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
-* supports Cache Coherency in the PCI_n interface.
-* Inputs: region - One of the four regions.
-* snoopType - There is four optional Types:
-* 1. No Snoop.
-* 2. Snoop to WT region.
-* 3. Snoop to WB region.
-* 4. Snoop & Invalidate to WB region.
-* baseAddress - Base Address of this region.
-* regionLength - Region length.
-* Returns: false if one of the parameters is wrong otherwise return true.
-*********************************************************************/
-bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
- PCI_SNOOP_TYPE snoopType,
- unsigned int baseAddress,
- unsigned int regionLength)
-{
- unsigned int snoopXbaseAddress;
- unsigned int snoopXtopAddress;
- unsigned int data;
- unsigned int snoopHigh = baseAddress + regionLength;
-
- if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
- return false;
- snoopXbaseAddress =
- pci_snoop_control_base_0_low[host] + 0x10 * region;
- snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
- if (regionLength == 0) { /* closing the region */
- GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
- GT_REG_WRITE (snoopXtopAddress, 0);
- return true;
- }
- baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
- data = (baseAddress >> 20) | snoopType << 12;
- GT_REG_WRITE (snoopXbaseAddress, data);
- snoopHigh = (snoopHigh & 0xfff00000) >> 20;
- GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
- return true;
-}
-
-static int gt_read_config_dword (struct pci_controller *hose,
- pci_dev_t dev, int offset, u32 * value)
-{
- int bus = PCI_BUS (dev);
-
- if ((bus == local_buses[0]) || (bus == local_buses[1])) {
- *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
- PCI_DEV (dev));
- } else {
- *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
- cfg_addr, offset,
- PCI_DEV (dev), bus);
- }
-
- return 0;
-}
-
-static int gt_write_config_dword (struct pci_controller *hose,
- pci_dev_t dev, int offset, u32 value)
-{
- int bus = PCI_BUS (dev);
-
- if ((bus == local_buses[0]) || (bus == local_buses[1])) {
- pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
- PCI_DEV (dev), value);
- } else {
- pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
- offset, PCI_DEV (dev), bus,
- value);
- }
- return 0;
-}
-
-
-static void gt_setup_ide (struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *entry)
-{
- static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
- u32 bar_response, bar_value;
- int bar;
-
- for (bar = 0; bar < 6; bar++) {
- /*ronen different function for 3rd bank. */
- unsigned int offset =
- (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
-
- pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
- 0x0);
- pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
- &bar_response);
-
- pciauto_region_allocate (bar_response &
- PCI_BASE_ADDRESS_SPACE_IO ? hose->
- pci_io : hose->pci_mem, ide_bar[bar],
- &bar_value);
-
- pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
- bar_value);
- }
-}
-
-
-/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */
-/* and is curently not called *. */
-#if 0
-static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
-{
- unsigned char pin, irq;
-
- pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
-
- if (pin == 1) { /* only allow INT A */
- irq = pci_irq_swizzle[(PCI_HOST) hose->
- cfg_addr][PCI_DEV (dev)];
- if (irq)
- pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
- }
-}
-#endif
-
-struct pci_config_table gt_config_table[] = {
- {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
-
- {}
-};
-
-struct pci_controller pci0_hose = {
-/* fixup_irq: gt_fixup_irq, */
- config_table:gt_config_table,
-};
-
-struct pci_controller pci1_hose = {
-/* fixup_irq: gt_fixup_irq, */
- config_table:gt_config_table,
-};
-
-void pci_init_board (void)
-{
- unsigned int command;
-
-#ifdef DEBUG
- gt_pci_bus_mode_display (PCI_HOST0);
-#endif
-
- pci0_hose.first_busno = 0;
- pci0_hose.last_busno = 0xff;
- local_buses[0] = pci0_hose.first_busno;
-
- /* PCI memory space */
- pci_set_region (pci0_hose.regions + 0,
- CONFIG_SYS_PCI0_0_MEM_SPACE,
- CONFIG_SYS_PCI0_0_MEM_SPACE,
- CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region (pci0_hose.regions + 1,
- CONFIG_SYS_PCI0_IO_SPACE_PCI,
- CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
-
- pci_set_ops (&pci0_hose,
- pci_hose_read_config_byte_via_dword,
- pci_hose_read_config_word_via_dword,
- gt_read_config_dword,
- pci_hose_write_config_byte_via_dword,
- pci_hose_write_config_word_via_dword,
- gt_write_config_dword);
- pci0_hose.region_count = 2;
-
- pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
-
- pci_register_hose (&pci0_hose);
- pciArbiterEnable (PCI_HOST0);
- pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
- command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MASTER;
- pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
- command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MEMORY;
- pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
-
- pci0_hose.last_busno = pci_hose_scan (&pci0_hose);
-
-#ifdef DEBUG
- gt_pci_bus_mode_display (PCI_HOST1);
-#endif
- pci1_hose.first_busno = pci0_hose.last_busno + 1;
- pci1_hose.last_busno = 0xff;
- pci1_hose.current_busno = pci1_hose.first_busno;
- local_buses[1] = pci1_hose.first_busno;
-
- /* PCI memory space */
- pci_set_region (pci1_hose.regions + 0,
- CONFIG_SYS_PCI1_0_MEM_SPACE,
- CONFIG_SYS_PCI1_0_MEM_SPACE,
- CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region (pci1_hose.regions + 1,
- CONFIG_SYS_PCI1_IO_SPACE_PCI,
- CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
-
- pci_set_ops (&pci1_hose,
- pci_hose_read_config_byte_via_dword,
- pci_hose_read_config_word_via_dword,
- gt_read_config_dword,
- pci_hose_write_config_byte_via_dword,
- pci_hose_write_config_word_via_dword,
- gt_write_config_dword);
-
- pci1_hose.region_count = 2;
-
- pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
-
- pci_register_hose (&pci1_hose);
-
- pciArbiterEnable (PCI_HOST1);
- pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
-
- command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MASTER;
- pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
-
- pci1_hose.last_busno = pci_hose_scan (&pci1_hose);
-
- command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MEMORY;
- pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
-
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*************************************************************************
- * adaption for the Marvell DB64360 Board
- * Ingo Assmus (ingo.assmus@keymile.com)
- ************************************************************************/
-
-
-/* sdram_init.c - automatic memory sizing */
-
-#include <common.h>
-#include <74xx_7xx.h>
-#include "../include/memory.h"
-#include "../include/pci.h"
-#include "../include/mv_gen_reg.h"
-#include <net.h>
-
-#include "eth.h"
-#include "mpsc.h"
-#include "../common/i2c.h"
-#include "64360.h"
-#include "mv_regs.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define MAP_PCI
-
-int set_dfcdlInit (void); /* setup delay line of Mv64360 */
-int mvDmaIsChannelActive (int);
-int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong);
-int mvDmaTransfer (int, ulong, ulong, ulong, ulong);
-
-/* ------------------------------------------------------------------------- */
-
-int
-memory_map_bank (unsigned int bankNo,
- unsigned int bankBase, unsigned int bankLength)
-{
-#ifdef MAP_PCI
- PCI_HOST host;
-#endif
-
-
-#ifdef DEBUG
- if (bankLength > 0) {
- printf ("mapping bank %d at %08x - %08x\n",
- bankNo, bankBase, bankBase + bankLength - 1);
- } else {
- printf ("unmapping bank %d\n", bankNo);
- }
-#endif
-
- memoryMapBank (bankNo, bankBase, bankLength);
-
-#ifdef MAP_PCI
- for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
- const int features =
- PREFETCH_ENABLE |
- DELAYED_READ_ENABLE |
- AGGRESSIVE_PREFETCH |
- READ_LINE_AGGRESSIVE_PREFETCH |
- READ_MULTI_AGGRESSIVE_PREFETCH |
- MAX_BURST_4 | PCI_NO_SWAP;
-
- pciMapMemoryBank (host, bankNo, bankBase, bankLength);
-
- pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
- bankLength);
-
- pciSetRegionFeatures (host, bankNo, features, bankBase,
- bankLength);
- }
-#endif
- return 0;
-}
-
-#define GB (1 << 30)
-
-/* much of this code is based on (or is) the code in the pip405 port */
-/* thanks go to the authors of said port - Josh */
-
-/* structure to store the relevant information about an sdram bank */
-typedef struct sdram_info {
- uchar drb_size;
- uchar registered, ecc;
- uchar tpar;
- uchar tras_clocks;
- uchar burst_len;
- uchar banks, slot;
-} sdram_info_t;
-
-/* Typedefs for 'gtAuxilGetDIMMinfo' function */
-
-typedef enum _memoryType { SDRAM, DDR } MEMORY_TYPE;
-
-typedef enum _voltageInterface { TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
- SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
-} VOLTAGE_INTERFACE;
-
-typedef enum _max_CL_supported_DDR { DDR_CL_1 = 1, DDR_CL_1_5 = 2, DDR_CL_2 =
- 4, DDR_CL_2_5 = 8, DDR_CL_3 = 16, DDR_CL_3_5 =
- 32, DDR_CL_FAULT } MAX_CL_SUPPORTED_DDR;
-typedef enum _max_CL_supported_SD { SD_CL_1 =
- 1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7,
- SD_FAULT } MAX_CL_SUPPORTED_SD;
-
-
-/* SDRAM/DDR information struct */
-typedef struct _gtMemoryDimmInfo {
- MEMORY_TYPE memoryType;
- unsigned int numOfRowAddresses;
- unsigned int numOfColAddresses;
- unsigned int numOfModuleBanks;
- unsigned int dataWidth;
- VOLTAGE_INTERFACE voltageInterface;
- unsigned int errorCheckType; /* ECC , PARITY.. */
- unsigned int sdramWidth; /* 4,8,16 or 32 */ ;
- unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */
- unsigned int minClkDelay;
- unsigned int burstLengthSupported;
- unsigned int numOfBanksOnEachDevice;
- unsigned int suportedCasLatencies;
- unsigned int RefreshInterval;
- unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */
- unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns) */
- MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
- MAX_CL_SUPPORTED_SD maxClSupported_SD;
- unsigned int moduleBankDensity;
- /* module attributes (true for yes) */
- bool bufferedAddrAndControlInputs;
- bool registeredAddrAndControlInputs;
- bool onCardPLL;
- bool bufferedDQMBinputs;
- bool registeredDQMBinputs;
- bool differentialClockInput;
- bool redundantRowAddressing;
-
- /* module general attributes */
- bool suportedAutoPreCharge;
- bool suportedPreChargeAll;
- bool suportedEarlyRasPreCharge;
- bool suportedWrite1ReadBurst;
- bool suported5PercentLowVCC;
- bool suported5PercentUpperVCC;
- /* module timing parameters */
- unsigned int minRasToCasDelay;
- unsigned int minRowActiveRowActiveDelay;
- unsigned int minRasPulseWidth;
- unsigned int minRowPrechargeTime; /* measured in ns */
-
- int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */
- int addrAndCommandSetupTime; /* (measured in ns/100) */
- int dataInputSetupTime; /* LoP left of point (measured in ns) */
- int dataInputHoldTime; /* LoP left of point (measured in ns) */
-/* tAC times for highest 2nd and 3rd highest CAS Latency values */
- unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */
- unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns) */
- unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */
- unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns) */
- unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */
- unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns) */
-
- unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */
- unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns) */
-
- unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */
- unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */
-
- unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */
- unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */
-
- /* Parameters calculated from
- the extracted DIMM information */
- unsigned int size;
- unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */
- unsigned int numberOfDevices;
- uchar drb_size; /* DRAM size in n*64Mbit */
- uchar slot; /* Slot Number this module is inserted in */
- uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */
-#ifdef DEBUG
- uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */
- uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */
- uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */
- unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */
- unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */
- unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */
- uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */
-
-#endif
-} AUX_MEM_DIMM_INFO;
-
-
-/*
- * translate ns.ns/10 coding of SPD timing values
- * into 10 ps unit values
- */
-static inline unsigned short NS10to10PS (unsigned char spd_byte)
-{
- unsigned short ns, ns10;
-
- /* isolate upper nibble */
- ns = (spd_byte >> 4) & 0x0F;
- /* isolate lower nibble */
- ns10 = (spd_byte & 0x0F);
-
- return (ns * 100 + ns10 * 10);
-}
-
-/*
- * translate ns coding of SPD timing values
- * into 10 ps unit values
- */
-static inline unsigned short NSto10PS (unsigned char spd_byte)
-{
- return (spd_byte * 100);
-}
-
-/* This code reads the SPD chip on the sdram and populates
- * the array which is passed in with the relevant information */
-/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
-static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
-{
- unsigned long spd_checksum;
-
-#ifdef ZUMA_NTL
- /* zero all the values */
- memset (info, 0, sizeof (*info));
-
-/*
- if (!slot) {
- info->slot = 0;
- info->banks = 1;
- info->registered = 0;
- info->drb_size = 16;*/ /* 16 - 256MBit, 32 - 512MBit */
-/* info->tpar = 3;
- info->tras_clocks = 5;
- info->burst_len = 4;
-*/
-#ifdef CONFIG_MV64360_ECC
- /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
- dimmInfo->errorCheckType = 2;
-/* info->ecc = 2;*/
-#endif
-}
-
-return 0;
-
-#else
- uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
- int ret;
- unsigned int i, j, density = 1;
-
-#ifdef DEBUG
- unsigned int k;
-#endif
- unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
- int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
- uchar supp_cal, cal_val;
- ulong memclk, tmemclk;
- ulong tmp;
- uchar trp_clocks = 0, tras_clocks;
- uchar data[128];
-
- memclk = gd->bus_clk;
- tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
-
- debug("before i2c read\n");
-
- ret = i2c_read (addr, 0, 1, data, 128);
-
- debug("after i2c read\n");
-
- /* zero all the values */
- memset (dimmInfo, 0, sizeof (*dimmInfo));
-
- /* copy the SPD content 1:1 into the dimmInfo structure */
- for (i = 0; i <= 127; i++) {
- dimmInfo->spd_raw_data[i] = data[i];
- }
-
- if (ret) {
- debug("No DIMM in slot %d [err = %x]\n", slot, ret);
- return 0;
- } else
- dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */
-
-#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
-
- for (i = 0; i <= 127; i++) {
- printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
- data[i]);
- }
-
-#endif
-#ifdef DEBUG
-/* find Manufactura of Dimm Module */
- for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
- dimmInfo->manufactura[i] = data[64 + i];
- }
- printf ("\nThis RAM-Module is produced by: %s\n",
- dimmInfo->manufactura);
-
-/* find Manul-ID of Dimm Module */
- for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
- dimmInfo->modul_id[i] = data[73 + i];
- }
- printf ("The Module-ID of this RAM-Module is: %s\n",
- dimmInfo->modul_id);
-
-/* find Vendor-Data of Dimm Module */
- for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
- dimmInfo->vendor_data[i] = data[99 + i];
- }
- printf ("Vendor Data of this RAM-Module is: %s\n",
- dimmInfo->vendor_data);
-
-/* find modul_serial_no of Dimm Module */
- dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
- printf ("Serial No. of this RAM-Module is: %ld (%lx)\n",
- dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
-
-/* find Manufac-Data of Dimm Module */
- dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
- printf ("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data[94]); /*dimmInfo->manufac_date */
-
-/* find modul_revision of Dimm Module */
- dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
- printf ("Module Revision of this RAM-Module is: %d.%d\n", data[91], data[92]); /* dimmInfo->modul_revision */
-
-/* find manufac_place of Dimm Module */
- dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
- printf ("manufac_place of this RAM-Module is: %d\n",
- dimmInfo->manufac_place);
-
-#endif
-
-/*------------------------------------------------------------------------------------------------------------------------------*/
-/* calculate SPD checksum */
-/*------------------------------------------------------------------------------------------------------------------------------*/
- spd_checksum = 0;
-
- for (i = 0; i <= 62; i++) {
- spd_checksum += data[i];
- }
-
- if ((spd_checksum & 0xff) != data[63]) {
- printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
- hang ();
- }
-
- else
- printf ("SPD Checksum ok!\n");
-
-
-/*------------------------------------------------------------------------------------------------------------------------------*/
- for (i = 2; i <= 35; i++) {
- switch (i) {
- case 2: /* Memory type (DDR / SDRAM) */
- dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
- if (dimmInfo->memoryType == 0)
- debug
- ("Dram_type in slot %d is: SDRAM\n",
- dimmInfo->slot);
- if (dimmInfo->memoryType == 1)
- debug
- ("Dram_type in slot %d is: DDRAM\n",
- dimmInfo->slot);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 3: /* Number Of Row Addresses */
- dimmInfo->numOfRowAddresses = data[i];
- debug
- ("Module Number of row addresses: %d\n",
- dimmInfo->numOfRowAddresses);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 4: /* Number Of Column Addresses */
- dimmInfo->numOfColAddresses = data[i];
- debug
- ("Module Number of col addresses: %d\n",
- dimmInfo->numOfColAddresses);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 5: /* Number Of Module Banks */
- dimmInfo->numOfModuleBanks = data[i];
- debug
- ("Number of Banks on Mod. : %d\n",
- dimmInfo->numOfModuleBanks);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 6: /* Data Width */
- dimmInfo->dataWidth = data[i];
- debug
- ("Module Data Width: %d\n",
- dimmInfo->dataWidth);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 8: /* Voltage Interface */
- switch (data[i]) {
- case 0x0:
- dimmInfo->voltageInterface = TTL_5V_TOLERANT;
- debug
- ("Module is TTL_5V_TOLERANT\n");
- break;
- case 0x1:
- dimmInfo->voltageInterface = LVTTL;
- debug
- ("Module is LVTTL\n");
- break;
- case 0x2:
- dimmInfo->voltageInterface = HSTL_1_5V;
- debug
- ("Module is TTL_5V_TOLERANT\n");
- break;
- case 0x3:
- dimmInfo->voltageInterface = SSTL_3_3V;
- debug
- ("Module is HSTL_1_5V\n");
- break;
- case 0x4:
- dimmInfo->voltageInterface = SSTL_2_5V;
- debug
- ("Module is SSTL_2_5V\n");
- break;
- default:
- dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
- debug
- ("Module is VOLTAGE_UNKNOWN\n");
- break;
- }
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 9: /* Minimum Cycle Time At Max CasLatancy */
- shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
- mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
- maskLeftOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
- maskRightOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
- leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
- rightOfPoint = (data[i] & maskRightOfPoint) * mult;
- dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
- leftOfPoint;
- dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
- rightOfPoint;
- debug
- ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n",
- leftOfPoint, rightOfPoint);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 10: /* Clock To Data Out */
- div = (dimmInfo->memoryType == DDR) ? 100 : 10;
- time_tmp =
- (((data[i] & 0xf0) >> 4) * 10) +
- ((data[i] & 0x0f));
- leftOfPoint = time_tmp / div;
- rightOfPoint = time_tmp % div;
- dimmInfo->clockToDataOut_LoP = leftOfPoint;
- dimmInfo->clockToDataOut_RoP = rightOfPoint;
- debug("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->clockToDataOut */
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-/*#ifdef CONFIG_ECC */
- case 11: /* Error Check Type */
- dimmInfo->errorCheckType = data[i];
- debug
- ("Error Check Type (0=NONE): %d\n",
- dimmInfo->errorCheckType);
- break;
-/* #endif */
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 12: /* Refresh Interval */
- dimmInfo->RefreshInterval = data[i];
- debug
- ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
- dimmInfo->RefreshInterval);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 13: /* Sdram Width */
- dimmInfo->sdramWidth = data[i];
- debug
- ("Sdram Width: %d\n",
- dimmInfo->sdramWidth);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 14: /* Error Check Data Width */
- dimmInfo->errorCheckDataWidth = data[i];
- debug
- ("Error Check Data Width: %d\n",
- dimmInfo->errorCheckDataWidth);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 15: /* Minimum Clock Delay */
- dimmInfo->minClkDelay = data[i];
- debug
- ("Minimum Clock Delay: %d\n",
- dimmInfo->minClkDelay);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 16: /* Burst Length Supported */
- /******-******-******-*******
- * bit3 | bit2 | bit1 | bit0 *
- *******-******-******-*******
- burst length = * 8 | 4 | 2 | 1 *
- *****************************
-
- If for example bit0 and bit2 are set, the burst
- length supported are 1 and 4. */
-
- dimmInfo->burstLengthSupported = data[i];
-#ifdef DEBUG
- debug
- ("Burst Length Supported: ");
- if (dimmInfo->burstLengthSupported & 0x01)
- debug("1, ");
- if (dimmInfo->burstLengthSupported & 0x02)
- debug("2, ");
- if (dimmInfo->burstLengthSupported & 0x04)
- debug("4, ");
- if (dimmInfo->burstLengthSupported & 0x08)
- debug("8, ");
- debug(" Bit \n");
-#endif
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 17: /* Number Of Banks On Each Device */
- dimmInfo->numOfBanksOnEachDevice = data[i];
- debug
- ("Number Of Banks On Each Chip: %d\n",
- dimmInfo->numOfBanksOnEachDevice);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 18: /* Suported Cas Latencies */
-
- /* DDR:
- *******-******-******-******-******-******-******-*******
- * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
- *******-******-******-******-******-******-******-*******
- CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 *
- *********************************************************
- SDRAM:
- *******-******-******-******-******-******-******-*******
- * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
- *******-******-******-******-******-******-******-*******
- CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 *
- ********************************************************/
- dimmInfo->suportedCasLatencies = data[i];
-#ifdef DEBUG
- debug
- ("Suported Cas Latencies: (CL) ");
- if (dimmInfo->memoryType == 0) { /* SDRAM */
- for (k = 0; k <= 7; k++) {
- if (dimmInfo->
- suportedCasLatencies & (1 << k))
- debug
- ("%d, ",
- k + 1);
- }
-
- } else { /* DDR-RAM */
-
- if (dimmInfo->suportedCasLatencies & 1)
- debug("1, ");
- if (dimmInfo->suportedCasLatencies & 2)
- debug("1.5, ");
- if (dimmInfo->suportedCasLatencies & 4)
- debug("2, ");
- if (dimmInfo->suportedCasLatencies & 8)
- debug("2.5, ");
- if (dimmInfo->suportedCasLatencies & 16)
- debug("3, ");
- if (dimmInfo->suportedCasLatencies & 32)
- debug("3.5, ");
-
- }
- debug("\n");
-#endif
- /* Calculating MAX CAS latency */
- for (j = 7; j > 0; j--) {
- if (((dimmInfo->
- suportedCasLatencies >> j) & 0x1) ==
- 1) {
- switch (dimmInfo->memoryType) {
- case DDR:
- /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
- switch (j) {
- case 7:
- debug
- ("Max. Cas Latencies (DDR): ERROR !!!\n");
- dimmInfo->
- maxClSupported_DDR
- =
- DDR_CL_FAULT;
- hang ();
- break;
- case 6:
- debug
- ("Max. Cas Latencies (DDR): ERROR !!!\n");
- dimmInfo->
- maxClSupported_DDR
- =
- DDR_CL_FAULT;
- hang ();
- break;
- case 5:
- debug
- ("Max. Cas Latencies (DDR): 3.5 clk's\n");
- dimmInfo->
- maxClSupported_DDR
- = DDR_CL_3_5;
- break;
- case 4:
- debug
- ("Max. Cas Latencies (DDR): 3 clk's \n");
- dimmInfo->
- maxClSupported_DDR
- = DDR_CL_3;
- break;
- case 3:
- debug
- ("Max. Cas Latencies (DDR): 2.5 clk's \n");
- dimmInfo->
- maxClSupported_DDR
- = DDR_CL_2_5;
- break;
- case 2:
- debug
- ("Max. Cas Latencies (DDR): 2 clk's \n");
- dimmInfo->
- maxClSupported_DDR
- = DDR_CL_2;
- break;
- case 1:
- debug
- ("Max. Cas Latencies (DDR): 1.5 clk's \n");
- dimmInfo->
- maxClSupported_DDR
- = DDR_CL_1_5;
- break;
- }
-
- /* ronen - in case we have a DIMM with minimumCycleTimeAtMaxCasLatancy
- lower then our SDRAM cycle count, we won't be able to support this CAL
- and we will have to use lower CAL. (minus - means from 3.0 to 2.5) */
- if ((dimmInfo->
- minimumCycleTimeAtMaxCasLatancy_LoP
- <
- CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
- ||
- ((dimmInfo->
- minimumCycleTimeAtMaxCasLatancy_LoP
- ==
- CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
- && (dimmInfo->
- minimumCycleTimeAtMaxCasLatancy_RoP
- <
- CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
- {
- dimmInfo->
- maxClSupported_DDR
- =
- dimmInfo->
- maxClSupported_DDR
- >> 1;
- debug
- ("*** Change actual Cas Latencies cause of minimumCycleTime n");
- }
- /* ronen - checkif the Dimm frequency compared to the Sysclock. */
- if ((dimmInfo->
- minimumCycleTimeAtMaxCasLatancy_LoP
- >
- CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
- ||
- ((dimmInfo->
- minimumCycleTimeAtMaxCasLatancy_LoP
- ==
- CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
- && (dimmInfo->
- minimumCycleTimeAtMaxCasLatancy_RoP
- >
- CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
- {
- printf ("*********************************************************\n");
- printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n");
- printf ("*********************************************************\n");
- hang ();
- }
-
- dimmInfo->
- maxCASlatencySupported_LoP
- =
- 1 +
- (int) (5 * j / 10);
- if (((5 * j) % 10) != 0)
- dimmInfo->
- maxCASlatencySupported_RoP
- = 5;
- else
- dimmInfo->
- maxCASlatencySupported_RoP
- = 0;
- debug
- ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
- dimmInfo->
- maxCASlatencySupported_LoP,
- dimmInfo->
- maxCASlatencySupported_RoP);
- break;
- case SDRAM:
- /* CAS latency 1, 2, 3, 4, 5, 6, 7 */
- dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */
- debug
- ("Max. Cas Latencies (SD): %d\n",
- dimmInfo->
- maxClSupported_SD);
- dimmInfo->
- maxCASlatencySupported_LoP
- = j;
- dimmInfo->
- maxCASlatencySupported_RoP
- = 0;
- debug
- ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
- dimmInfo->
- maxCASlatencySupported_LoP,
- dimmInfo->
- maxCASlatencySupported_RoP);
- break;
- }
- break;
- }
- }
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 21: /* Buffered Address And Control Inputs */
- debug("\nModul Attributes (SPD Byte 21): \n");
- dimmInfo->bufferedAddrAndControlInputs =
- data[i] & BIT0;
- dimmInfo->registeredAddrAndControlInputs =
- (data[i] & BIT1) >> 1;
- dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
- dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
- dimmInfo->registeredDQMBinputs =
- (data[i] & BIT4) >> 4;
- dimmInfo->differentialClockInput =
- (data[i] & BIT5) >> 5;
- dimmInfo->redundantRowAddressing =
- (data[i] & BIT6) >> 6;
-#ifdef DEBUG
- if (dimmInfo->bufferedAddrAndControlInputs == 1)
- debug
- (" - Buffered Address/Control Input: Yes \n");
- else
- debug
- (" - Buffered Address/Control Input: No \n");
-
- if (dimmInfo->registeredAddrAndControlInputs == 1)
- debug
- (" - Registered Address/Control Input: Yes \n");
- else
- debug
- (" - Registered Address/Control Input: No \n");
-
- if (dimmInfo->onCardPLL == 1)
- debug
- (" - On-Card PLL (clock): Yes \n");
- else
- debug
- (" - On-Card PLL (clock): No \n");
-
- if (dimmInfo->bufferedDQMBinputs == 1)
- debug
- (" - Bufferd DQMB Inputs: Yes \n");
- else
- debug
- (" - Bufferd DQMB Inputs: No \n");
-
- if (dimmInfo->registeredDQMBinputs == 1)
- debug
- (" - Registered DQMB Inputs: Yes \n");
- else
- debug
- (" - Registered DQMB Inputs: No \n");
-
- if (dimmInfo->differentialClockInput == 1)
- debug
- (" - Differential Clock Input: Yes \n");
- else
- debug
- (" - Differential Clock Input: No \n");
-
- if (dimmInfo->redundantRowAddressing == 1)
- debug
- (" - redundant Row Addressing: Yes \n");
- else
- debug
- (" - redundant Row Addressing: No \n");
-
-#endif
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 22: /* Suported AutoPreCharge */
- debug("\nModul Attributes (SPD Byte 22): \n");
- dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
- dimmInfo->suportedAutoPreCharge =
- (data[i] & BIT1) >> 1;
- dimmInfo->suportedPreChargeAll =
- (data[i] & BIT2) >> 2;
- dimmInfo->suportedWrite1ReadBurst =
- (data[i] & BIT3) >> 3;
- dimmInfo->suported5PercentLowVCC =
- (data[i] & BIT4) >> 4;
- dimmInfo->suported5PercentUpperVCC =
- (data[i] & BIT5) >> 5;
-#ifdef DEBUG
- if (dimmInfo->suportedEarlyRasPreCharge == 1)
- debug
- (" - Early Ras Precharge: Yes \n");
- else
- debug
- (" - Early Ras Precharge: No \n");
-
- if (dimmInfo->suportedAutoPreCharge == 1)
- debug
- (" - AutoPreCharge: Yes \n");
- else
- debug
- (" - AutoPreCharge: No \n");
-
- if (dimmInfo->suportedPreChargeAll == 1)
- debug
- (" - Precharge All: Yes \n");
- else
- debug
- (" - Precharge All: No \n");
-
- if (dimmInfo->suportedWrite1ReadBurst == 1)
- debug
- (" - Write 1/ReadBurst: Yes \n");
- else
- debug
- (" - Write 1/ReadBurst: No \n");
-
- if (dimmInfo->suported5PercentLowVCC == 1)
- debug
- (" - lower VCC tolerance: 5 Percent \n");
- else
- debug
- (" - lower VCC tolerance: 10 Percent \n");
-
- if (dimmInfo->suported5PercentUpperVCC == 1)
- debug
- (" - upper VCC tolerance: 5 Percent \n");
- else
- debug
- (" - upper VCC tolerance: 10 Percent \n");
-
-#endif
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
- shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
- mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
- maskLeftOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
- maskRightOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
- leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
- rightOfPoint = (data[i] & maskRightOfPoint) * mult;
- dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
- leftOfPoint;
- dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
- rightOfPoint;
- debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 24: /* Clock To Data Out 2nd highest Cas Latency Value */
- div = (dimmInfo->memoryType == DDR) ? 100 : 10;
- time_tmp =
- (((data[i] & 0xf0) >> 4) * 10) +
- ((data[i] & 0x0f));
- leftOfPoint = time_tmp / div;
- rightOfPoint = time_tmp % div;
- dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
- dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
- debug
- ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n",
- leftOfPoint, rightOfPoint);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
- shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
- mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
- maskLeftOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
- maskRightOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
- leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
- rightOfPoint = (data[i] & maskRightOfPoint) * mult;
- dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
- leftOfPoint;
- dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
- rightOfPoint;
- debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 26: /* Clock To Data Out 3rd highest Cas Latency Value */
- div = (dimmInfo->memoryType == DDR) ? 100 : 10;
- time_tmp =
- (((data[i] & 0xf0) >> 4) * 10) +
- ((data[i] & 0x0f));
- leftOfPoint = time_tmp / div;
- rightOfPoint = time_tmp % div;
- dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
- dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
- debug
- ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n",
- leftOfPoint, rightOfPoint);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 27: /* Minimum Row Precharge Time */
- shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
- maskLeftOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
- maskRightOfPoint =
- (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
- leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
- rightOfPoint = (data[i] & maskRightOfPoint) * 25;
-
- dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint); /* measured in n times 10ps Intervals */
- trp_clocks =
- (dimmInfo->minRowPrechargeTime +
- (tmemclk - 1)) / tmemclk;
- debug
- ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n",
- tmemclk, tmemclk / 100, tmemclk % 100);
- debug
- ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n",
- leftOfPoint, rightOfPoint, trp_clocks);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 28: /* Minimum Row Active to Row Active Time */
- shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
- maskLeftOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
- maskRightOfPoint =
- (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
- leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
- rightOfPoint = (data[i] & maskRightOfPoint) * 25;
-
- dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
- debug
- ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n",
- leftOfPoint, rightOfPoint, trp_clocks);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 29: /* Minimum Ras-To-Cas Delay */
- shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
- maskLeftOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
- maskRightOfPoint =
- (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
- leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
- rightOfPoint = (data[i] & maskRightOfPoint) * 25;
-
- dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
- debug
- ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n",
- leftOfPoint, rightOfPoint, trp_clocks);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 30: /* Minimum Ras Pulse Width */
- dimmInfo->minRasPulseWidth = data[i];
- tras_clocks =
- (NSto10PS (data[i]) +
- (tmemclk - 1)) / tmemclk;
- debug
- ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n",
- dimmInfo->minRasPulseWidth, tras_clocks);
-
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 31: /* Module Bank Density */
- dimmInfo->moduleBankDensity = data[i];
- debug
- ("Module Bank Density: %d\n",
- dimmInfo->moduleBankDensity);
-#ifdef DEBUG
- debug
- ("*** Offered Densities (more than 1 = Multisize-Module): ");
- {
- if (dimmInfo->moduleBankDensity & 1)
- debug("4MB, ");
- if (dimmInfo->moduleBankDensity & 2)
- debug("8MB, ");
- if (dimmInfo->moduleBankDensity & 4)
- debug("16MB, ");
- if (dimmInfo->moduleBankDensity & 8)
- debug("32MB, ");
- if (dimmInfo->moduleBankDensity & 16)
- debug("64MB, ");
- if (dimmInfo->moduleBankDensity & 32)
- debug("128MB, ");
- if ((dimmInfo->moduleBankDensity & 64)
- || (dimmInfo->moduleBankDensity & 128)) {
- debug("ERROR, ");
- hang ();
- }
- }
- debug("\n");
-#endif
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 32: /* Address And Command Setup Time (measured in ns/1000) */
- sign = 1;
- switch (dimmInfo->memoryType) {
- case DDR:
- time_tmp =
- (((data[i] & 0xf0) >> 4) * 10) +
- ((data[i] & 0x0f));
- leftOfPoint = time_tmp / 100;
- rightOfPoint = time_tmp % 100;
- break;
- case SDRAM:
- leftOfPoint = (data[i] & 0xf0) >> 4;
- if (leftOfPoint > 7) {
- leftOfPoint = data[i] & 0x70 >> 4;
- sign = -1;
- }
- rightOfPoint = (data[i] & 0x0f);
- break;
- }
- dimmInfo->addrAndCommandSetupTime =
- (leftOfPoint * 100 + rightOfPoint) * sign;
- debug
- ("Address And Command Setup Time [ns]: %d.%d\n",
- sign * leftOfPoint, rightOfPoint);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 33: /* Address And Command Hold Time */
- sign = 1;
- switch (dimmInfo->memoryType) {
- case DDR:
- time_tmp =
- (((data[i] & 0xf0) >> 4) * 10) +
- ((data[i] & 0x0f));
- leftOfPoint = time_tmp / 100;
- rightOfPoint = time_tmp % 100;
- break;
- case SDRAM:
- leftOfPoint = (data[i] & 0xf0) >> 4;
- if (leftOfPoint > 7) {
- leftOfPoint = data[i] & 0x70 >> 4;
- sign = -1;
- }
- rightOfPoint = (data[i] & 0x0f);
- break;
- }
- dimmInfo->addrAndCommandHoldTime =
- (leftOfPoint * 100 + rightOfPoint) * sign;
- debug
- ("Address And Command Hold Time [ns]: %d.%d\n",
- sign * leftOfPoint, rightOfPoint);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 34: /* Data Input Setup Time */
- sign = 1;
- switch (dimmInfo->memoryType) {
- case DDR:
- time_tmp =
- (((data[i] & 0xf0) >> 4) * 10) +
- ((data[i] & 0x0f));
- leftOfPoint = time_tmp / 100;
- rightOfPoint = time_tmp % 100;
- break;
- case SDRAM:
- leftOfPoint = (data[i] & 0xf0) >> 4;
- if (leftOfPoint > 7) {
- leftOfPoint = data[i] & 0x70 >> 4;
- sign = -1;
- }
- rightOfPoint = (data[i] & 0x0f);
- break;
- }
- dimmInfo->dataInputSetupTime =
- (leftOfPoint * 100 + rightOfPoint) * sign;
- debug
- ("Data Input Setup Time [ns]: %d.%d\n",
- sign * leftOfPoint, rightOfPoint);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 35: /* Data Input Hold Time */
- sign = 1;
- switch (dimmInfo->memoryType) {
- case DDR:
- time_tmp =
- (((data[i] & 0xf0) >> 4) * 10) +
- ((data[i] & 0x0f));
- leftOfPoint = time_tmp / 100;
- rightOfPoint = time_tmp % 100;
- break;
- case SDRAM:
- leftOfPoint = (data[i] & 0xf0) >> 4;
- if (leftOfPoint > 7) {
- leftOfPoint = data[i] & 0x70 >> 4;
- sign = -1;
- }
- rightOfPoint = (data[i] & 0x0f);
- break;
- }
- dimmInfo->dataInputHoldTime =
- (leftOfPoint * 100 + rightOfPoint) * sign;
- debug
- ("Data Input Hold Time [ns]: %d.%d\n\n",
- sign * leftOfPoint, rightOfPoint);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
- }
- }
- /* calculating the sdram density */
- for (i = 0;
- i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
- i++) {
- density = density * 2;
- }
- dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
- dimmInfo->sdramWidth;
- dimmInfo->numberOfDevices =
- (dimmInfo->dataWidth / dimmInfo->sdramWidth) *
- dimmInfo->numOfModuleBanks;
- if ((dimmInfo->errorCheckType == 0x1)
- || (dimmInfo->errorCheckType == 0x2)
- || (dimmInfo->errorCheckType == 0x3)) {
- dimmInfo->size =
- (dimmInfo->deviceDensity / 8) *
- (dimmInfo->numberOfDevices -
- /* ronen on the 1G dimm we get wrong value. (was devicesForErrCheck) */
- dimmInfo->numberOfDevices / 8);
- } else {
- dimmInfo->size =
- (dimmInfo->deviceDensity / 8) *
- dimmInfo->numberOfDevices;
- }
-
- /* compute the module DRB size */
- tmp = (1 <<
- (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
- tmp *= dimmInfo->numOfModuleBanks;
- tmp *= dimmInfo->sdramWidth;
- tmp = tmp >> 24; /* div by 0x4000000 (64M) */
- dimmInfo->drb_size = (uchar) tmp;
- debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size);
-
- /* try a CAS latency of 3 first... */
-
- /* bit 1 is CL2, bit 2 is CL3 */
- supp_cal = (dimmInfo->suportedCasLatencies & 0x6) >> 1;
-
- cal_val = 0;
- if (supp_cal & 3) {
- if (NS10to10PS (data[9]) <= tmemclk)
- cal_val = 3;
- }
-
- /* then 2... */
- if (supp_cal & 2) {
- if (NS10to10PS (data[23]) <= tmemclk)
- cal_val = 2;
- }
-
- debug("cal_val = %d\n", cal_val);
-
- /* bummer, did't work... */
- if (cal_val == 0) {
- debug("Couldn't find a good CAS latency\n");
- hang ();
- return 0;
- }
-
- return true;
-
-#endif
-}
-
-/* sets up the GT properly with information passed in */
-int setup_sdram (AUX_MEM_DIMM_INFO * info)
-{
- ulong tmp, check;
- ulong tmp_sdram_mode = 0; /* 0x141c */
- ulong tmp_dunit_control_low = 0; /* 0x1404 */
- int i;
-
- /* added 8/21/2003 P. Marchese */
- unsigned int sdram_config_reg;
-
- /* added 10/10/2003 P. Marchese */
- ulong sdram_chip_size;
-
- /* sanity checking */
- if (!info->numOfModuleBanks) {
- printf ("setup_sdram called with 0 banks\n");
- return 1;
- }
-
- /* delay line */
- set_dfcdlInit (); /* may be its not needed */
- debug("Delay line set done\n");
-
- /* set SDRAM mode NOP */ /* To_do check it */
- GT_REG_WRITE (SDRAM_OPERATION, 0x5);
- while (GTREGREAD (SDRAM_OPERATION) != 0) {
- debug
- ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n");
- }
-
- /* SDRAM configuration */
-/* added 8/21/2003 P. Marchese */
-/* code allows usage of registered DIMMS */
-
- /* figure out the memory refresh internal */
- switch (info->RefreshInterval) {
- case 0x0:
- case 0x80: /* refresh period is 15.625 usec */
- sdram_config_reg =
- (unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_CLK)
- / (float) 1000000.0);
- break;
- case 0x1:
- case 0x81: /* refresh period is 3.9 usec */
- sdram_config_reg =
- (unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_CLK) /
- (float) 1000000.0);
- break;
- case 0x2:
- case 0x82: /* refresh period is 7.8 usec */
- sdram_config_reg =
- (unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_CLK) /
- (float) 1000000.0);
- break;
- case 0x3:
- case 0x83: /* refresh period is 31.3 usec */
- sdram_config_reg =
- (unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_CLK) /
- (float) 1000000.0);
- break;
- case 0x4:
- case 0x84: /* refresh period is 62.5 usec */
- sdram_config_reg =
- (unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_CLK) /
- (float) 1000000.0);
- break;
- case 0x5:
- case 0x85: /* refresh period is 125 usec */
- sdram_config_reg =
- (unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_CLK) /
- (float) 1000000.0);
- break;
- default: /* refresh period undefined */
- printf ("DRAM refresh period is unknown!\n");
- printf ("Aborting DRAM setup with an error\n");
- hang ();
- break;
- }
- debug("calculated refresh interval %0x\n", sdram_config_reg);
-
- /* make sure the refresh value is only 14 bits */
- if (sdram_config_reg > 0x1fff)
- sdram_config_reg = 0x1fff;
- debug("adjusted refresh interval %0x\n", sdram_config_reg);
-
- /* we want physical bank interleaving and */
- /* virtual bank interleaving enabled so do nothing */
- /* since these bits need to be zero to enable the interleaving */
-
- /* registered DRAM ? */
- if (info->registeredAddrAndControlInputs == 1) {
- /* it's registered DRAM, so set the reg. DRAM bit */
- sdram_config_reg = sdram_config_reg | BIT17;
- debug("Enabling registered DRAM bit\n");
- }
- /* turn on DRAM ECC? */
-#ifdef CONFIG_MV64360_ECC
- if (info->errorCheckType == 0x2) {
- /* DRAM has ECC, so turn it on */
- sdram_config_reg = sdram_config_reg | BIT18;
- debug("Enabling ECC\n");
- }
-#endif
- /* set the data DQS pin configuration */
- switch (info->sdramWidth) {
- case 0x4: /* memory is x4 */
- sdram_config_reg = sdram_config_reg | BIT20 | BIT21;
- debug("Data DQS pins set for 16 pins\n");
- break;
- case 0x8: /* memory is x8 or x16 */
- case 0x10:
- sdram_config_reg = sdram_config_reg | BIT21;
- debug("Data DQS pins set for 8 pins\n");
- break;
- case 0x20: /* memory is x32 */
- /* both bits are cleared for x32 so nothing to do */
- debug("Data DQS pins set for 2 pins\n");
- break;
- default: /* memory width unsupported */
- printf ("DRAM chip width is unknown!\n");
- printf ("Aborting DRAM setup with an error\n");
- hang ();
- break;
- }
-
- /* perform read buffer assignments */
- /* we are going to use the Power-up defaults */
- /* bit 26 = CPU = buffer 1 */
- /* bit 27 = PCI bus #0 = buffer 0 */
- /* bit 28 = PCI bus #1 = buffer 0 */
- /* bit 29 = MPSC = buffer 0 */
- /* bit 30 = IDMA = buffer 0 */
- /* bit 31 = Gigabit = buffer 0 */
- sdram_config_reg = sdram_config_reg | BIT26;
- /* sdram_config_reg = sdram_config_reg | 0x58000000; */
- /* sdram_config_reg = sdram_config_reg & 0xffffff00; */
-
- /* write the value into the SDRAM configuration register */
- GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg);
- debug
- ("OOOOOOOOO sdram_conf 0x1400: %08x\n",
- GTREGREAD (SDRAM_CONFIG));
-
- /* SDRAM open pages control keep open as much as I can */
- GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
- debug
- ("sdram_open_pages_controll 0x1414: %08x\n",
- GTREGREAD (SDRAM_OPEN_PAGES_CONTROL));
-
- /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
- tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */
- if (tmp == 0)
- debug("Core Signals are sync (by HW-Setting)!!!\n");
- else
- debug
- ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n");
-
- /* SDRAM set CAS Latency according to SPD information */
- switch (info->memoryType) {
- case SDRAM:
- printf ("### SD-RAM not supported !!!\n");
- printf ("Aborting!!!\n");
- hang ();
- /* ToDo fill SD-RAM if needed !!!!! */
- break;
- /* Calculate the settings for SDRAM mode and Dunit control low registers */
- /* Values set according to technical bulletin TB-92 rev. c */
- case DDR:
- debug("### SET-CL for DDR-RAM\n");
- switch (info->maxClSupported_DDR) {
- case DDR_CL_3:
- tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */
- if (tmp == 1) { /* clocks sync */
- if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
- tmp_dunit_control_low = 0x05110051;
- else
- tmp_dunit_control_low = 0x24110051;
- debug
- ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low);
- } else { /* clk sync. bypassed */
-
- if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
- tmp_dunit_control_low = 0x2C1107F2;
- else
- tmp_dunit_control_low = 0x3C1107d2;
- debug
- ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low);
- }
- break;
- case DDR_CL_2_5:
- tmp_sdram_mode = 0x62; /* CL=2.5 Burstlength = 4 */
- if (tmp == 1) { /* clocks sync */
- if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
- tmp_dunit_control_low = 0x25110051;
- else
- tmp_dunit_control_low = 0x24110051;
- debug
- ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low);
- } else { /* clk sync. bypassed */
-
- if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */
- printf ("CL = 2.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");
- printf ("Aborting!!!\n");
- hang ();
- } else
- tmp_dunit_control_low = 0x1B1107d2;
- debug
- ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low);
- }
- break;
- case DDR_CL_2:
- tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */
- if (tmp == 1) { /* clocks sync */
- if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
- tmp_dunit_control_low = 0x04110051;
- else
- tmp_dunit_control_low = 0x03110051;
- debug
- ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low);
- } else { /* clk sync. bypassed */
-
- if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */
- printf ("CL = 2, Clock Unsync'ed, Dunit Control Low register setting undefined\n");
- printf ("Aborting!!!\n");
- hang ();
- } else
- tmp_dunit_control_low = 0x3B1107d2;
- debug
- ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low);
- }
- break;
- case DDR_CL_1_5:
- tmp_sdram_mode = 0x52; /* CL=1.5 Burstlength = 4 */
- if (tmp == 1) { /* clocks sync */
- if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
- tmp_dunit_control_low = 0x24110051;
- else
- tmp_dunit_control_low = 0x23110051;
- debug
- ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low);
- } else { /* clk sync. bypassed */
-
- if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */
- printf ("CL = 1.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");
- printf ("Aborting!!!\n");
- hang ();
- } else
- tmp_dunit_control_low = 0x1A1107d2;
- debug
- ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low);
- }
- break;
-
- default:
- printf ("Max. CL is out of range %d\n",
- info->maxClSupported_DDR);
- hang ();
- break;
- } /* end DDR switch */
- break;
- } /* end CL switch */
-
- /* Write results of CL detection procedure */
- /* set SDRAM mode reg. 0x141c */
- GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
-
- /* set SDRAM mode SetCommand 0x1418 */
- GT_REG_WRITE (SDRAM_OPERATION, 0x3);
- while (GTREGREAD (SDRAM_OPERATION) != 0) {
- debug
- ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
- }
-
- /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
- GT_REG_WRITE (D_UNIT_CONTROL_LOW, tmp_dunit_control_low);
-
- /* set SDRAM mode SetCommand 0x1418 */
- GT_REG_WRITE (SDRAM_OPERATION, 0x3);
- while (GTREGREAD (SDRAM_OPERATION) != 0) {
- debug
- ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n");
- }
-
-/*------------------------------------------------------------------------------ */
-
- /* bank parameters */
- /* SDRAM address decode register 0x1410 */
- /* program this with the default value */
- tmp = 0x02; /* power-up default address select decoding value */
-
- debug("drb_size (n*64Mbit): %d\n", info->drb_size);
-/* figure out the DRAM chip size */
- sdram_chip_size =
- (1 << (info->numOfRowAddresses + info->numOfColAddresses));
- sdram_chip_size *= info->sdramWidth;
- sdram_chip_size *= 4;
- debug("computed sdram chip size is %#lx\n", sdram_chip_size);
- /* divide sdram chip size by 64 Mbits */
- sdram_chip_size = sdram_chip_size / 0x4000000;
- switch (sdram_chip_size) {
- case 1: /* 64 Mbit */
- case 2: /* 128 Mbit */
- debug("RAM-Device_size 64Mbit or 128Mbit)\n");
- tmp |= (0x00 << 4);
- break;
- case 4: /* 256 Mbit */
- case 8: /* 512 Mbit */
- debug("RAM-Device_size 256Mbit or 512Mbit)\n");
- tmp |= (0x01 << 4);
- break;
- case 16: /* 1 Gbit */
- case 32: /* 2 Gbit */
- debug("RAM-Device_size 1Gbit or 2Gbit)\n");
- tmp |= (0x02 << 4);
- break;
- default:
- printf ("Error in dram size calculation\n");
- printf ("RAM-Device_size is unsupported\n");
- hang ();
- }
-
- /* SDRAM address control */
- GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
- debug
- ("setting up sdram address control (0x1410) with: %08lx \n",
- tmp);
-
-/* ------------------------------------------------------------------------------ */
-/* same settings for registerd & non-registerd DDR SDRAM */
- debug
- ("setting up sdram_timing_control_low (0x1408) with: %08x \n",
- 0x11511220);
- GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220);
-
-
-/* ------------------------------------------------------------------------------ */
-
- /* SDRAM configuration */
- tmp = GTREGREAD (SDRAM_CONFIG);
-
- if (info->registeredAddrAndControlInputs
- || info->registeredDQMBinputs) {
- tmp |= (1 << 17);
- debug
- ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
- info->registeredAddrAndControlInputs,
- info->registeredDQMBinputs);
- }
-
- /* Use buffer 1 to return read data to the CPU
- * Page 426 MV64360 */
- tmp |= (1 << 26);
- debug
- ("Before Buffer assignment - sdram_conf (0x1400): %08x\n",
- GTREGREAD (SDRAM_CONFIG));
- debug
- ("After Buffer assignment - sdram_conf (0x1400): %08x\n",
- GTREGREAD (SDRAM_CONFIG));
-
- /* SDRAM timing To_do: */
-/* ------------------------------------------------------------------------------ */
-
- debug
- ("setting up sdram_timing_control_high (0x140c) with: %08x \n",
- 0x9);
- GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0x9);
-
- debug
- ("setting up sdram address pads control (0x14c0) with: %08x \n",
- 0x7d5014a);
- GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a);
-
- debug
- ("setting up sdram data pads control (0x14c4) with: %08x \n",
- 0x7d5014a);
- GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a);
-
-/* ------------------------------------------------------------------------------ */
-
- /* set the SDRAM configuration for each bank */
-
-/* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
- {
- i = info->slot;
- debug
- ("\n*** Running a MRS cycle for bank %d ***\n", i);
-
- /* map the bank */
- memory_map_bank (i, 0, GB / 4);
-
- /* set SDRAM mode */ /* To_do check it */
- GT_REG_WRITE (SDRAM_OPERATION, 0x3);
- check = GTREGREAD (SDRAM_OPERATION);
- debug
- ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
- check);
-
-
- /* switch back to normal operation mode */
- GT_REG_WRITE (SDRAM_OPERATION, 0);
- check = GTREGREAD (SDRAM_OPERATION);
- debug
- ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
- check);
-
- /* unmap the bank */
- memory_map_bank (i, 0, 0);
- }
-
- return 0;
-
-}
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-long int dram_size (long int *base, long int maxsize)
-{
- volatile long int *addr, *b = base;
- long int cnt, val, save1, save2;
-
-#define STARTVAL (1<<20) /* start test at 1M */
- for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
- cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save1 = *addr; /* save contents of addr */
- save2 = *b; /* save contents of base */
-
- *addr = cnt; /* write cnt to addr */
- *b = 0; /* put null at base */
-
- /* check at base address */
- if ((*b) != 0) {
- *addr = save1; /* restore *addr */
- *b = save2; /* restore *b */
- return (0);
- }
- val = *addr; /* read *addr */
- val = *addr; /* read *addr */
-
- *addr = save1;
- *b = save2;
-
- if (val != cnt) {
- debug
- ("Found %08x at Address %08x (failure)\n",
- (unsigned int) val, (unsigned int) addr);
- /* fix boundary condition.. STARTVAL means zero */
- if (cnt == STARTVAL / sizeof (long))
- cnt = 0;
- return (cnt * sizeof (long));
- }
- }
- return maxsize;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* ppcboot interface function to SDRAM init - this is where all the
- * controlling logic happens */
-phys_size_t initdram (int board_type)
-{
- int checkbank[4] = {[0 ... 3] = 0 };
- ulong realsize, total;
- AUX_MEM_DIMM_INFO dimmInfo1;
- AUX_MEM_DIMM_INFO dimmInfo2;
- int nhr, bank_no;
- ulong dest, memSpaceAttr;
-
- /* first, use the SPD to get info about the SDRAM/ DDRRAM */
-
- /* check the NHR bit and skip mem init if it's already done */
- nhr = get_hid0 () & (1 << 16);
-
- if (nhr) {
- printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n");
- } else {
- /* DIMM0 */
- check_dimm (0, &dimmInfo1);
-
- /* DIMM1 */
- check_dimm (1, &dimmInfo2);
-
- memory_map_bank (0, 0, 0);
- memory_map_bank (1, 0, 0);
- memory_map_bank (2, 0, 0);
- memory_map_bank (3, 0, 0);
-
- /* ronen check correct set of DIMMS */
- if (dimmInfo1.numOfModuleBanks && dimmInfo2.numOfModuleBanks) {
- if (dimmInfo1.errorCheckType !=
- dimmInfo2.errorCheckType)
- printf ("***WARNNING***!!!! different ECC support of the DIMMS\n");
- if (dimmInfo1.maxClSupported_DDR !=
- dimmInfo2.maxClSupported_DDR)
- printf ("***WARNNING***!!!! different CAL setting of the DIMMS\n");
- if (dimmInfo1.registeredAddrAndControlInputs !=
- dimmInfo2.registeredAddrAndControlInputs)
- printf ("***WARNNING***!!!! different Registration setting of the DIMMS\n");
- }
-
- if (dimmInfo1.numOfModuleBanks && setup_sdram (&dimmInfo1)) {
- printf ("Setup for DIMM1 failed.\n");
- }
-
- if (dimmInfo2.numOfModuleBanks && setup_sdram (&dimmInfo2)) {
- printf ("Setup for DIMM2 failed.\n");
- }
-
- /* set the NHR bit */
- set_hid0 (get_hid0 () | (1 << 16));
- }
- /* next, size the SDRAM banks */
-
- realsize = total = 0;
- if (dimmInfo1.numOfModuleBanks > 0) {
- checkbank[0] = 1;
- }
- if (dimmInfo1.numOfModuleBanks > 1) {
- checkbank[1] = 1;
- }
- if (dimmInfo1.numOfModuleBanks > 2)
- printf ("Error, SPD claims DIMM1 has >2 banks\n");
-
- printf ("-- DIMM1 has %d banks\n", dimmInfo1.numOfModuleBanks);
-
- if (dimmInfo2.numOfModuleBanks > 0) {
- checkbank[2] = 1;
- }
- if (dimmInfo2.numOfModuleBanks > 1) {
- checkbank[3] = 1;
- }
- if (dimmInfo2.numOfModuleBanks > 2)
- printf ("Error, SPD claims DIMM2 has >2 banks\n");
-
- printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks);
-
- for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
- /* skip over banks that are not populated */
- if (!checkbank[bank_no])
- continue;
-
- /* ronen - realsize = dram_size((long int *)total, check); */
- if (bank_no == 0 || bank_no == 1) {
- if (checkbank[1] == 1)
- realsize = dimmInfo1.size / 2;
- else
- realsize = dimmInfo1.size;
- }
- if (bank_no == 2 || bank_no == 3) {
- if (checkbank[3] == 1)
- realsize = dimmInfo2.size / 2;
- else
- realsize = dimmInfo2.size;
- }
- memory_map_bank (bank_no, total, realsize);
-
- /* ronen - initialize the DRAM for ECC */
-#ifdef CONFIG_MV64360_ECC
- if ((dimmInfo1.errorCheckType != 0) &&
- ((dimmInfo2.errorCheckType != 0)
- || (dimmInfo2.numOfModuleBanks == 0))) {
- printf ("ECC Initialization of Bank %d:", bank_no);
- memSpaceAttr = ((~(BIT0 << bank_no)) & 0xf) << 8;
- mvDmaSetMemorySpace (0, 0, memSpaceAttr, total,
- realsize);
- for (dest = total; dest < total + realsize;
- dest += _8M) {
- mvDmaTransfer (0, total, dest, _8M,
- BIT8 /*DMA_DTL_128BYTES */ |
- BIT3 /*DMA_HOLD_SOURCE_ADDR */
- |
- BIT11
- /*DMA_BLOCK_TRANSFER_MODE */ );
- while (mvDmaIsChannelActive (0));
- }
- printf (" PASS\n");
- }
-#endif
-
- total += realsize;
- }
-
- /* ronen- add DRAM conf prints */
- switch ((GTREGREAD (0x141c) >> 4) & 0x7) {
- case 0x2:
- printf ("CAS Latency = 2");
- break;
- case 0x3:
- printf ("CAS Latency = 3");
- break;
- case 0x5:
- printf ("CAS Latency = 1.5");
- break;
- case 0x6:
- printf ("CAS Latency = 2.5");
- break;
- }
- printf (" tRP = %d tRAS = %d tRCD=%d\n",
- ((GTREGREAD (0x1408) >> 8) & 0xf) + 1,
- ((GTREGREAD (0x1408) >> 20) & 0xf) + 1,
- ((GTREGREAD (0x1408) >> 4) & 0xf) + 1);
-
-/* Setup Ethernet DMA Adress window to DRAM Area */
- if (total > _256M)
- printf ("*** ONLY the first 256MB DRAM memory are used out of the ");
- else
- printf ("Total SDRAM memory is ");
- /* (cause all the 4 BATS are taken) */
- return (total);
-}
-
-
-/* ronen- add Idma functions for usage of the ecc dram init. */
-/*******************************************************************************
-* mvDmaIsChannelActive - Checks if a engine is busy.
-********************************************************************************/
-int mvDmaIsChannelActive (int engine)
-{
- ulong data;
-
- data = GTREGREAD (MV64360_DMA_CHANNEL0_CONTROL + 4 * engine);
- if (data & BIT14 /*activity status */ ) {
- return 1;
- }
- return 0;
-}
-
-/*******************************************************************************
-* mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding
-* map.
-*******************************************************************************/
-int mvDmaSetMemorySpace (ulong memSpace,
- ulong memSpaceTarget,
- ulong memSpaceAttr, ulong baseAddress, ulong size)
-{
- ulong temp;
-
- /* The base address must be aligned to the size. */
- if (baseAddress % size != 0) {
- return 0;
- }
- if (size >= 0x10000 /*64K */ ) {
- size &= 0xffff0000;
- baseAddress = (baseAddress & 0xffff0000);
- /* Set the new attributes */
- GT_REG_WRITE (MV64360_DMA_BASE_ADDR_REG0 + memSpace * 8,
- (baseAddress | memSpaceTarget | memSpaceAttr));
- GT_REG_WRITE ((MV64360_DMA_SIZE_REG0 + memSpace * 8),
- (size - 1) & 0xffff0000);
- temp = GTREGREAD (MV64360_DMA_BASE_ADDR_ENABLE_REG);
- GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG,
- (temp & ~(BIT0 << memSpace)));
- return 1;
- }
- return 0;
-}
-
-
-/*******************************************************************************
-* mvDmaTransfer - Transfer data from sourceAddr to destAddr on one of the 4
-* DMA channels.
-********************************************************************************/
-int mvDmaTransfer (int engine, ulong sourceAddr,
- ulong destAddr, ulong numOfBytes, ulong command)
-{
- ulong engOffReg = 0; /* Engine Offset Register */
-
- if (numOfBytes > 0xffff) {
- command = command | BIT31 /*DMA_16M_DESCRIPTOR_MODE */ ;
- }
- command = command | ((command >> 6) & 0x7);
- engOffReg = engine * 4;
- GT_REG_WRITE (MV64360_DMA_CHANNEL0_BYTE_COUNT + engOffReg,
- numOfBytes);
- GT_REG_WRITE (MV64360_DMA_CHANNEL0_SOURCE_ADDR + engOffReg,
- sourceAddr);
- GT_REG_WRITE (MV64360_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg,
- destAddr);
- command =
- command | BIT12 /*DMA_CHANNEL_ENABLE */ | BIT9
- /*DMA_NON_CHAIN_MODE */ ;
- /* Activate DMA engine By writting to mvDmaControlRegister */
- GT_REG_WRITE (MV64360_DMA_CHANNEL0_CONTROL + engOffReg, command);
- return 1;
-}
-
-/****************************************************************************************
- * SDRAM INIT *
- * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb *
- * This procedure fits only the Atlantis *
- * *
- ***************************************************************************************/
-
-
-/****************************************************************************************
- * DFCDL initialize MV643xx Design Considerations *
- * *
- ***************************************************************************************/
-int set_dfcdlInit (void)
-{
- int i;
- unsigned int dfcdl_word = 0x391; /* 0x14f; ronen new dfcdl */
-
- for (i = 0; i < 64; i++) {
- GT_REG_WRITE (SRAM_DATA0, dfcdl_word);
-/* dfcdl_word += 0x41; - ronen new dfcdl */
- }
- GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000); /* enable dynamic delay line updating */
-
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * main board support/init for the Galileo Eval board DB64460.
- */
-
-#ifndef __64460_H__
-#define __64460_H__
-
-/* CPU Configuration bits */
-#define CPU_CONF_ADDR_MISS_EN (1 << 8)
-#define CPU_CONF_SINGLE_CPU (1 << 11)
-#define CPU_CONF_ENDIANESS (1 << 12)
-#define CPU_CONF_PIPELINE (1 << 13)
-#define CPU_CONF_STOP_RETRY (1 << 17)
-#define CPU_CONF_MULTI_DECODE (1 << 18)
-#define CPU_CONF_DP_VALID (1 << 19)
-#define CPU_CONF_PERR_PROP (1 << 22)
-#define CPU_CONF_AACK_DELAY_2 (1 << 25)
-#define CPU_CONF_AP_VALID (1 << 26)
-#define CPU_CONF_REMAP_WR_DIS (1 << 27)
-
-/* CPU Master Control bits */
-#define CPU_MAST_CTL_ARB_EN (1 << 8)
-#define CPU_MAST_CTL_MASK_BR_1 (1 << 9)
-#define CPU_MAST_CTL_M_WR_TRIG (1 << 10)
-#define CPU_MAST_CTL_M_RD_TRIG (1 << 11)
-#define CPU_MAST_CTL_CLEAN_BLK (1 << 12)
-#define CPU_MAST_CTL_FLUSH_BLK (1 << 13)
-
-#endif /* __64460_H__ */
+++ /dev/null
-if TARGET_DB64460
-
-config SYS_BOARD
- default "db64460"
-
-config SYS_VENDOR
- default "Marvell"
-
-config SYS_CONFIG_NAME
- default "DB64460"
-
-endif
+++ /dev/null
-DB64460 BOARD
-#M: -
-S: Maintained
-F: board/Marvell/db64460/
-F: include/configs/DB64460.h
-F: configs/DB64460_defconfig
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2001
-# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += db64460.o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
- mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
- sdram_init.o ../common/intel_flash.o ../common/misc.o
+++ /dev/null
-This file contains status information for the port of the U-Boot to the Marvell Development Board DB64460.
-
-Author: Ronen Shitrit <rshitrit@il.marvell.com>
-
-
-Supported CPU Types :
-+++++++++++++++++++++
-IBM750Gx Rev 1.0
-MPC7457 Rev 1.1
-
-Supported CPU Cache Library:
-++++++++++++++++++++++++++++
- L1 and L2 only.
-
-CPU Control:
-++++++++++++
- Marvell optimized CPU control settings:
- Big Endian
- Enable CPU pipeline
- Data and address parity checking
- AACK# assert after 2 cycles
-
-U-Boot I/O Interface Support:
-+++++++++++++++++++++++++++++
-- Serial Interface (UART)
- This version of U-Boot supports the SIO U-Boot interface driver, with a PC standard baud rate up to 115200 BPS on the ST16C2552 DUART device located on DB-64360-BP device module.
-- Network Interface
- This LSP supports the following network devices:
- o MV64360 Gigabit Ethernet Controller device
- o Intel 82559 PCI NIC device
-- PCI Interface
- This LSP supports the following capabilities over the Marvell(r) device PCI0/1 units:
- o Local PCI configuration header control.
- o External PCI configuration header control (for other agents on the bus).
- o PCI configuration application. Scans and configures the PCI agents on the bus.
- o PCI Internal Arbiter activation and configuration.
-
-Memory Interface Support:
-+++++++++++++++++++++++++
-- DDR
- o DDR auto-detection and configuration. Enables access up to 256 MB, due to the limitations of using only four Base Address Translations (BATs).
- o Enable DDR ECC in case both DIMM support ECC, and initialize the entire DDR memory by using the idma.
-
-- Devices
- o Initializes the MV64360 device's chip-selects 0-3 to enable access to the boot flash, main flash, real time clock (RTC), and external SRAM.
- o JFFS2
- JFFS2 is a crash/power down safe file system for disk-less embedded devices.
- This version of U-Boot supports scanning a JFFS2 file system on the large flash and loading files from it.
-
-Unsupported Features:
-+++++++++++++++++++++
- Messaging unit - No support for MV64360 Messaging unit.
- Watchdog Timer - No support for MV64360 Watchdog unit.
- L3 cache - No support for L3 cache on MPC7455
- Dual PCU - No support for Dual CPU
- PCI-X was never tested
- IDMA driver - No support for MV64360 IDMA unit.
- XOR Engine - No support for MV64460 XOR Engine
-
-BSP Special Considerations:
-+++++++++++++++++++++++++++
-- DDR DIMM location: Due to PCI specifications, place the larger DIMM module in the MAIN DIMM slot, in order to have full access from the PCI to the DDR while using both DDR slots.
-- DDR DIMM types: Due to architectural and software limitations, the registration, CAS Latency, and ECC of both DIMMS should be identical.
-
-Test Cases:
-###########
-UART:
-+++++
-Check that the UART baud rate is configured to 57600 and 115200, and check:
- Transmit (to the hyper terminal) and Receive (using the keyboard) using Linux minicom.
- Load S-Record file over the UART using Windows HyperTerminal.
-
-Network:
-++++++++
-Use TFTP application to load a debugged executable and execute it.
-Insert Intel PCI NIC 82557 rev 08 to PCI slots 0-3 Check correct detection of the PCI NIC, correct configuration of the NIC BARs , and load files by using tftp through the PCI NIC.
-
-Memory:
-+++++++
-Test DDR DIMMs on DB-64360-BP. See that Uboot report their correct parameters:
-o 128MB DIMM consist of 16 x 64Mbit devices
-o 128MB DIMM consist of 09 x 128Mbit devices @ 266MHz.
-o 256MB DIMM consist of 16 x 128Mbit devices @ 266MHz.
-o 256MB DIMM consist of 09 x 256Mbit devices @ 400MHz.
-o 512MB DIMM consist of 16 x 256Mbit devices @ 333MHz.
-o 512MB DIMM consist of 18 x 256Mbit devices @ 266MHz.
-o GigaB DIMM consist of 36 x 256Mbit devices @ 266MHz registered
-
-For each chip select device perform data access to verify its accessibility.
-
-Create a JFFS2 on the large flash through the Linux holding few files, few dirs and a uImage.
-Load the U-Boot and:
-use the ls command to check correct scan of the JFFS2 on the large flash.
-Use the floads command to copy the uImage from the JFFS2 on the large flash to the DIMM SDRAM, and boot the uImage.
-
-PCI:
-++++
-1)Insert different PCI cards:
-Galileo 64120A rev 10 and 12, Intel Nic 82557 rev 08 and Real Tech NIC 8139 rev10
-on different slots (0-3) of the PCI and check:
-o Correct detection of the PCI devices.
-o Correct address mapping of the PCI devices.
-2)Insert Galileo 64120A rev 10 on different slots (0-3) of the PCI and check writing and reading pci configuration register through the U-Boot.
-
-Booting Linux through the U-Boot (use the bootargs of the U-Boot as a bootcmd to the kernal)
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * modifications for the DB64460 eval board based by Ingo.Assmus@keymile.com
- */
-
-/*
- * db64460.c - main board support/init for the Galileo Eval board.
- */
-
-#include <common.h>
-#include <74xx_7xx.h>
-#include "../include/memory.h"
-#include "../include/pci.h"
-#include "../include/mv_gen_reg.h"
-#include <net.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-
-#include "eth.h"
-#include "mpsc.h"
-#include "i2c.h"
-#include "64460.h"
-#include "mv_regs.h"
-
-#undef DEBUG
-/*#define DEBUG */
-
-#define MAP_PCI
-
-#ifdef DEBUG
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-/* ------------------------------------------------------------------------- */
-
-/* this is the current GT register space location */
-/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
-
-/* Unfortunately, we cant change it while we are in flash, so we initialize it
- * to the "final" value. This means that any debug_led calls before
- * board_early_init_f wont work right (like in cpu_init_f).
- * See also my_remap_gt_regs below. (NTL)
- */
-
-void board_prebootm_init (void);
-unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
-int display_mem_map (void);
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * This is a version of the GT register space remapping function that
- * doesn't touch globals (meaning, it's ok to run from flash.)
- *
- * Unfortunately, this has the side effect that a writable
- * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
- */
-
-void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
-{
- u32 temp;
-
- /* check and see if it's already moved */
-
-/* original ppcboot 1.1.6 source
-
- temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
- if ((temp & 0xffff) == new_loc >> 20)
- return;
-
- temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
- 0xffff0000) | (new_loc >> 20);
-
- out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
-
- while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
-original ppcboot 1.1.6 source end */
-
- temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
- if ((temp & 0xffff) == new_loc >> 16)
- return;
-
- temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
- 0xffff0000) | (new_loc >> 16);
-
- out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
-
- while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
-}
-
-#ifdef CONFIG_PCI
-
-static void gt_pci_config (void)
-{
- unsigned int stat;
- unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
-
- /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
- * config registers by writing ones to the bus and device.
- * We then update the Virtual register with the correct value for the bus and device.
- */
- if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
- GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
-
- GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
-
- GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
- GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
- (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
-
- }
- if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
- GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
- GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
-
- GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
- GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
- (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
- }
-
- /* Enable master */
- PCI_MASTER_ENABLE (0, SELF);
- PCI_MASTER_ENABLE (1, SELF);
-
- /* Enable PCI0/1 Mem0 and IO 0 disable all others */
- GT_REG_READ (BASE_ADDR_ENABLE, &stat);
- stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
- <<
- 18);
- stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
- GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
-
- /* ronen- add write to pci remap registers for 64460.
- in 64360 when writing to pci base go and overide remap automaticaly,
- in 64460 it doesn't */
- GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16);
- GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16);
- GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
-
- GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
-
- GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16);
- GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16);
- GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
-
- GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
-
- /* PCI interface settings */
- /* Timeout set to retry forever */
- GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
- GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
-
- /* ronen - enable only CS0 and Internal reg!! */
- GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
- GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
-
-/*ronen update the pci internal registers base address.*/
-#ifdef MAP_PCI
- for (stat = 0; stat <= PCI_HOST1; stat++)
- pciWriteConfigReg (stat,
- PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
- SELF, CONFIG_SYS_GT_REGS);
-#endif
-
-}
-#endif
-
-/* Setup CPU interface paramaters */
-static void gt_cpu_config (void)
-{
- cpu_t cpu = get_cpu_type ();
- ulong tmp;
-
- /* cpu configuration register */
- tmp = GTREGREAD (CPU_CONFIGURATION);
-
- /* set the SINGLE_CPU bit see MV64460 P.399 */
-#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
- tmp |= CPU_CONF_SINGLE_CPU;
-#endif
-
- tmp &= ~CPU_CONF_AACK_DELAY_2;
-
- tmp |= CPU_CONF_DP_VALID;
- tmp |= CPU_CONF_AP_VALID;
-
- tmp |= CPU_CONF_PIPELINE;
-
- GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */
-
- /* CPU master control register */
- tmp = GTREGREAD (CPU_MASTER_CONTROL);
-
- tmp |= CPU_MAST_CTL_ARB_EN;
-
- if ((cpu == CPU_7400) ||
- (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
-
- tmp |= CPU_MAST_CTL_CLEAN_BLK;
- tmp |= CPU_MAST_CTL_FLUSH_BLK;
-
- } else {
- /* cleanblock must be cleared for CPUs
- * that do not support this command (603e, 750)
- * see Res#1 */
- tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
- tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
- }
- GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
-}
-
-/*
- * board_early_init_f.
- *
- * set up gal. device mappings, etc.
- */
-int board_early_init_f (void)
-{
- uchar sram_boot = 0;
-
- /*
- * set up the GT the way the kernel wants it
- * the call to move the GT register space will obviously
- * fail if it has already been done, but we're going to assume
- * that if it's not at the power-on location, it's where we put
- * it last time. (huber)
- */
-
- my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
-
- /* No PCI in first release of Port To_do: enable it. */
-#ifdef CONFIG_PCI
- gt_pci_config ();
-#endif
- /* mask all external interrupt sources */
- GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
- GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
- /* new in MV6446x */
- GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
- GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
- /* --------------------- */
- GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
- GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
- GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
- GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
- /* does not exist in MV6446x
- GT_REG_WRITE(CPU_INT_0_MASK, 0);
- GT_REG_WRITE(CPU_INT_1_MASK, 0);
- GT_REG_WRITE(CPU_INT_2_MASK, 0);
- GT_REG_WRITE(CPU_INT_3_MASK, 0);
- --------------------- */
-
-
- /* ----- DEVICE BUS SETTINGS ------ */
-
- /*
- * EVB
- * 0 - SRAM ????
- * 1 - RTC ????
- * 2 - UART ????
- * 3 - Flash checked 32Bit Intel Strata
- * boot - BootCS checked 8Bit 29LV040B
- *
- * Zuma
- * 0 - Flash
- * boot - BootCS
- */
-
- /*
- * the dual 7450 module requires burst access to the boot
- * device, so the serial rom copies the boot device to the
- * on-board sram on the eval board, and updates the correct
- * registers to boot from the sram. (device0)
- */
- if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE)
- sram_boot = 1;
- if (!sram_boot)
- memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
-
- memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
- memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
- memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
-
-
- /* configure device timing */
-#ifdef CONFIG_SYS_DEV0_PAR /* set port parameters for SRAM device module access */
- if (!sram_boot)
- GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
-#endif
-
-#ifdef CONFIG_SYS_DEV1_PAR /* set port parameters for RTC device module access */
- GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
-#endif
-#ifdef CONFIG_SYS_DEV2_PAR /* set port parameters for DUART device module access */
- GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
-#endif
-
-#ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */
- /* detect if we are booting from the 32 bit flash */
- if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
- /* 32 bit boot flash */
- GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
- GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
- CONFIG_SYS_32BIT_BOOT_PAR);
- } else {
- /* 8 bit boot flash */
- GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
- GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
- }
-#else
- /* 8 bit boot flash only */
-/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
-#endif
-
-
- gt_cpu_config ();
-
- /* MPP setup */
- GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
- GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
- GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
- GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
-
- GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
- DEBUG_LED0_ON ();
- DEBUG_LED1_ON ();
- DEBUG_LED2_ON ();
-
- return 0;
-}
-
-/* various things to do after relocation */
-
-int misc_init_r ()
-{
- icache_enable ();
-#ifdef CONFIG_SYS_L2
- l2cache_enable ();
-#endif
-#ifdef CONFIG_MPSC
-
- mpsc_sdma_init ();
- mpsc_init2 ();
-#endif
-
-#if 0
- /* disable the dcache and MMU */
- dcache_lock ();
-#endif
- return 0;
-}
-
-void after_reloc (ulong dest_addr, gd_t * gd)
-{
- /* check to see if we booted from the sram. If so, move things
- * back to the way they should be. (we're running from main
- * memory at this point now */
- if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) {
- memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
- memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M);
- }
- display_mem_map ();
- /* now, jump to the main ppcboot board init code */
- board_init_r (gd, dest_addr);
- /* NOTREACHED */
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- *
- * right now, assume borad type. (there is just one...after all)
- */
-
-int checkboard (void)
-{
- int l_type = 0;
-
- printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
- return (l_type);
-}
-
-/* utility functions */
-void debug_led (int led, int mode)
-{
- volatile int *addr = 0;
- __maybe_unused int dummy;
-
- if (mode == 1) {
- switch (led) {
- case 0:
- addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
- 0x08000);
- break;
-
- case 1:
- addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
- 0x0c000);
- break;
-
- case 2:
- addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
- 0x10000);
- break;
- }
- } else if (mode == 0) {
- switch (led) {
- case 0:
- addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
- 0x14000);
- break;
-
- case 1:
- addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
- 0x18000);
- break;
-
- case 2:
- addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
- 0x1c000);
- break;
- }
- }
-
- dummy = *addr;
-}
-
-int display_mem_map (void)
-{
- int i, j;
- unsigned int base, size, width;
-
- /* SDRAM */
- printf ("SD (DDR) RAM\n");
- for (i = 0; i <= BANK3; i++) {
- base = memoryGetBankBaseAddress (i);
- size = memoryGetBankSize (i);
- if (size != 0) {
- printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
- i, base, size >> 20);
- }
- }
-
- /* CPU's PCI windows */
- for (i = 0; i <= PCI_HOST1; i++) {
- printf ("\nCPU's PCI %d windows\n", i);
- base = pciGetSpaceBase (i, PCI_IO);
- size = pciGetSpaceSize (i, PCI_IO);
- printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base,
- size >> 20);
- for (j = 0;
- j <=
- PCI_REGION0
- /*ronen currently only first PCI MEM is used 3 */ ;
- j++) {
- base = pciGetSpaceBase (i, j);
- size = pciGetSpaceSize (i, j);
- printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
- }
- }
-
- /* Devices */
- printf ("\nDEVICES\n");
- for (i = 0; i <= DEVICE3; i++) {
- base = memoryGetDeviceBaseAddress (i);
- size = memoryGetDeviceSize (i);
- width = memoryGetDeviceWidth (i) * 8;
- printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
- if (i == 0)
- printf ("\t- EXT SRAM (actual - 1M)\n");
- else if (i == 1)
- printf ("\t- RTC\n");
- else if (i == 2)
- printf ("\t- UART\n");
- else
- printf ("\t- LARGE FLASH\n");
- }
-
- /* Bootrom */
- base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */
- size = memoryGetDeviceSize (BOOT_DEVICE);
- width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
- printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\n",
- base, size >> 20, width);
- return (0);
-}
-
-/* DRAM check routines copied from gw8260 */
-
-#if defined (CONFIG_SYS_DRAM_TEST)
-
-/*********************************************************************/
-/* NAME: move64() - moves a double word (64-bit) */
-/* */
-/* DESCRIPTION: */
-/* this function performs a double word move from the data at */
-/* the source pointer to the location at the destination pointer. */
-/* */
-/* INPUTS: */
-/* unsigned long long *src - pointer to data to move */
-/* */
-/* OUTPUTS: */
-/* unsigned long long *dest - pointer to locate to move data */
-/* */
-/* RETURNS: */
-/* None */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* May cloober fr0. */
-/* */
-/*********************************************************************/
-static void move64 (unsigned long long *src, unsigned long long *dest)
-{
- asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
- "stfd 0, 0(4)" /* *dest = fpr0 */
- : : : "fr0"); /* Clobbers fr0 */
- return;
-}
-
-
-#if defined (CONFIG_SYS_DRAM_TEST_DATA)
-
-unsigned long long pattern[] = {
- 0xaaaaaaaaaaaaaaaaULL,
- 0xccccccccccccccccULL,
- 0xf0f0f0f0f0f0f0f0ULL,
- 0xff00ff00ff00ff00ULL,
- 0xffff0000ffff0000ULL,
- 0xffffffff00000000ULL,
- 0x00000000ffffffffULL,
- 0x0000ffff0000ffffULL,
- 0x00ff00ff00ff00ffULL,
- 0x0f0f0f0f0f0f0f0fULL,
- 0x3333333333333333ULL,
- 0x5555555555555555ULL,
-};
-
-/*********************************************************************/
-/* NAME: mem_test_data() - test data lines for shorts and opens */
-/* */
-/* DESCRIPTION: */
-/* Tests data lines for shorts and opens by forcing adjacent data */
-/* to opposite states. Because the data lines could be routed in */
-/* an arbitrary manner the must ensure test patterns ensure that */
-/* every case is tested. By using the following series of binary */
-/* patterns every combination of adjacent bits is test regardless */
-/* of routing. */
-/* */
-/* ...101010101010101010101010 */
-/* ...110011001100110011001100 */
-/* ...111100001111000011110000 */
-/* ...111111110000000011111111 */
-/* */
-/* Carrying this out, gives us six hex patterns as follows: */
-/* */
-/* 0xaaaaaaaaaaaaaaaa */
-/* 0xcccccccccccccccc */
-/* 0xf0f0f0f0f0f0f0f0 */
-/* 0xff00ff00ff00ff00 */
-/* 0xffff0000ffff0000 */
-/* 0xffffffff00000000 */
-/* */
-/* The number test patterns will always be given by: */
-/* */
-/* log(base 2)(number data bits) = log2 (64) = 6 */
-/* */
-/* To test for short and opens to other signals on our boards. we */
-/* simply */
-/* test with the 1's complemnt of the paterns as well. */
-/* */
-/* OUTPUTS: */
-/* Displays failing test pattern */
-/* */
-/* RETURNS: */
-/* 0 - Passed test */
-/* 1 - Failed test */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* Assumes only one one SDRAM bank */
-/* */
-/*********************************************************************/
-int mem_test_data (void)
-{
- unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
- unsigned long long temp64 = 0;
- int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
- int i;
- unsigned int hi, lo;
-
- for (i = 0; i < num_patterns; i++) {
- move64 (&(pattern[i]), pmem);
- move64 (pmem, &temp64);
-
- /* hi = (temp64>>32) & 0xffffffff; */
- /* lo = temp64 & 0xffffffff; */
- /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
-
- hi = (pattern[i] >> 32) & 0xffffffff;
- lo = pattern[i] & 0xffffffff;
- /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
-
- if (temp64 != pattern[i]) {
- printf ("\n Data Test Failed, pattern 0x%08x%08x",
- hi, lo);
- return 1;
- }
- }
-
- return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_DATA */
-
-#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
-/*********************************************************************/
-/* NAME: mem_test_address() - test address lines */
-/* */
-/* DESCRIPTION: */
-/* This function performs a test to verify that each word im */
-/* memory is uniquly addressable. The test sequence is as follows: */
-/* */
-/* 1) write the address of each word to each word. */
-/* 2) verify that each location equals its address */
-/* */
-/* OUTPUTS: */
-/* Displays failing test pattern and address */
-/* */
-/* RETURNS: */
-/* 0 - Passed test */
-/* 1 - Failed test */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/* */
-/*********************************************************************/
-int mem_test_address (void)
-{
- volatile unsigned int *pmem =
- (volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
- const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
- unsigned int i;
-
- /* write address to each location */
- for (i = 0; i < size; i++) {
- pmem[i] = i;
- }
-
- /* verify each loaction */
- for (i = 0; i < size; i++) {
- if (pmem[i] != i) {
- printf ("\n Address Test Failed at 0x%x", i);
- return 1;
- }
- }
- return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
-
-#if defined (CONFIG_SYS_DRAM_TEST_WALK)
-/*********************************************************************/
-/* NAME: mem_march() - memory march */
-/* */
-/* DESCRIPTION: */
-/* Marches up through memory. At each location verifies rmask if */
-/* read = 1. At each location write wmask if write = 1. Displays */
-/* failing address and pattern. */
-/* */
-/* INPUTS: */
-/* volatile unsigned long long * base - start address of test */
-/* unsigned int size - number of dwords(64-bit) to test */
-/* unsigned long long rmask - read verify mask */
-/* unsigned long long wmask - wrtie verify mask */
-/* short read - verifies rmask if read = 1 */
-/* short write - writes wmask if write = 1 */
-/* */
-/* OUTPUTS: */
-/* Displays failing test pattern and address */
-/* */
-/* RETURNS: */
-/* 0 - Passed test */
-/* 1 - Failed test */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/* */
-/*********************************************************************/
-int mem_march (volatile unsigned long long *base,
- unsigned int size,
- unsigned long long rmask,
- unsigned long long wmask, short read, short write)
-{
- unsigned int i;
- unsigned long long temp = 0;
- unsigned int hitemp, lotemp, himask, lomask;
-
- for (i = 0; i < size; i++) {
- if (read != 0) {
- /* temp = base[i]; */
- move64 ((unsigned long long *) &(base[i]), &temp);
- if (rmask != temp) {
- hitemp = (temp >> 32) & 0xffffffff;
- lotemp = temp & 0xffffffff;
- himask = (rmask >> 32) & 0xffffffff;
- lomask = rmask & 0xffffffff;
-
- printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
- return 1;
- }
- }
- if (write != 0) {
- /* base[i] = wmask; */
- move64 (&wmask, (unsigned long long *) &(base[i]));
- }
- }
- return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_WALK */
-
-/*********************************************************************/
-/* NAME: mem_test_walk() - a simple walking ones test */
-/* */
-/* DESCRIPTION: */
-/* Performs a walking ones through entire physical memory. The */
-/* test uses as series of memory marches, mem_march(), to verify */
-/* and write the test patterns to memory. The test sequence is as */
-/* follows: */
-/* 1) march writing 0000...0001 */
-/* 2) march verifying 0000...0001 , writing 0000...0010 */
-/* 3) repeat step 2 shifting masks left 1 bit each time unitl */
-/* the write mask equals 1000...0000 */
-/* 4) march verifying 1000...0000 */
-/* The test fails if any of the memory marches return a failure. */
-/* */
-/* OUTPUTS: */
-/* Displays which pass on the memory test is executing */
-/* */
-/* RETURNS: */
-/* 0 - Passed test */
-/* 1 - Failed test */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/* */
-/*********************************************************************/
-int mem_test_walk (void)
-{
- unsigned long long mask;
- volatile unsigned long long *pmem =
- (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
- const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
-
- unsigned int i;
-
- mask = 0x01;
-
- printf ("Initial Pass");
- mem_march (pmem, size, 0x0, 0x1, 0, 1);
-
- printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
- printf (" ");
- printf (" ");
- printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
-
- for (i = 0; i < 63; i++) {
- printf ("Pass %2d", i + 2);
- if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
- /*printf("mask: 0x%x, pass: %d, ", mask, i); */
- return 1;
- }
- mask = mask << 1;
- printf ("\b\b\b\b\b\b\b");
- }
-
- printf ("Last Pass");
- if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
- /* printf("mask: 0x%x", mask); */
- return 1;
- }
- printf ("\b\b\b\b\b\b\b\b\b");
- printf (" ");
- printf ("\b\b\b\b\b\b\b\b\b");
-
- return 0;
-}
-
-/*********************************************************************/
-/* NAME: testdram() - calls any enabled memory tests */
-/* */
-/* DESCRIPTION: */
-/* Runs memory tests if the environment test variables are set to */
-/* 'y'. */
-/* */
-/* INPUTS: */
-/* testdramdata - If set to 'y', data test is run. */
-/* testdramaddress - If set to 'y', address test is run. */
-/* testdramwalk - If set to 'y', walking ones test is run */
-/* */
-/* OUTPUTS: */
-/* None */
-/* */
-/* RETURNS: */
-/* 0 - Passed test */
-/* 1 - Failed test */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/* */
-/*********************************************************************/
-int testdram (void)
-{
- int rundata, runaddress, runwalk;
-
- rundata = getenv_yesno("testdramdata") == 1;
- runaddress = getenv_yesno("testdramaddress") == 1;
- runwalk = getenv_yesno("testdramwalk") == 1;
-
-/* rundata = 1; */
-/* runaddress = 0; */
-/* runwalk = 0; */
-
- if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
- printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
- }
-#ifdef CONFIG_SYS_DRAM_TEST_DATA
- if (rundata == 1) {
- printf ("Test DATA ... ");
- if (mem_test_data () == 1) {
- printf ("failed \n");
- return 1;
- } else
- printf ("ok \n");
- }
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
- if (runaddress == 1) {
- printf ("Test ADDRESS ... ");
- if (mem_test_address () == 1) {
- printf ("failed \n");
- return 1;
- } else
- printf ("ok \n");
- }
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_WALK
- if (runwalk == 1) {
- printf ("Test WALKING ONEs ... ");
- if (mem_test_walk () == 1) {
- printf ("failed \n");
- return 1;
- } else
- printf ("ok \n");
- }
-#endif
- if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
- printf ("passed\n");
- }
- return 0;
-
-}
-#endif /* CONFIG_SYS_DRAM_TEST */
-
-/* ronen - the below functions are used by the bootm function */
-/* - we map the base register to fbe00000 (same mapping as in the LSP) */
-/* - we turn off the RX gig dmas - to prevent the dma from overunning */
-/* the kernel data areas. */
-/* - we diable and invalidate the icache and dcache. */
-void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
-{
- u32 temp;
-
- temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
- if ((temp & 0xffff) == new_loc >> 16)
- return;
-
- temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
- 0xffff0000) | (new_loc >> 16);
-
- out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
-
- while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
- new_loc |
- (INTERNAL_SPACE_DECODE)))))
- != temp);
-
-}
-
-void board_prebootm_init ()
-{
-
-/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
- GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
-
-/* Stop GigE Rx DMA engines */
- GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
- GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00);
- GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00);
-
-/* Relocate MV64460 internal regs */
- my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM);
-
- icache_disable ();
- dcache_disable ();
-}
-
-int board_eth_init(bd_t *bis)
-{
- int ret;
- ret = pci_eth_init(bis);
- if (!ret)
- ret = mv6446x_eth_initialize(bis);
- return ret;
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * eth.h - header file for the polled mode GT ethernet driver
- */
-
-#ifndef __EVB64460_ETH_H__
-#define __EVB64460_ETH_H__
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-#include <common.h>
-
-int db64460_eth0_poll(void);
-int db64460_eth0_transmit(unsigned int s, volatile char *p);
-void db64460_eth0_disable(void);
-bool network_start(bd_t *bis);
-
-int mv6446x_eth_initialize(bd_t *);
-
-#endif /* __EVB64460_ETH_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*************************************************************************
- * changes for Marvell DB64460 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
- *
- ************************************************************************/
-
-/*
- * mpsc.c - driver for console over the MPSC.
- */
-
-
-#include <common.h>
-#include <config.h>
-#include <asm/cache.h>
-
-#include <malloc.h>
-#include "mpsc.h"
-
-#include "mv_regs.h"
-
-#include "../include/memory.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Define this if you wish to use the MPSC as a register based UART.
- * This will force the serial port to not use the SDMA engine at all.
- */
-#undef CONFIG_MPSC_DEBUG_PORT
-
-
-int (*mpsc_putchar) (char ch) = mpsc_putchar_early;
-char (*mpsc_getchar) (void) = mpsc_getchar_debug;
-int (*mpsc_test_char) (void) = mpsc_test_char_debug;
-
-
-static volatile unsigned int *rx_desc_base = NULL;
-static unsigned int rx_desc_index = 0;
-static volatile unsigned int *tx_desc_base = NULL;
-static unsigned int tx_desc_index = 0;
-
-/* local function declarations */
-static int galmpsc_connect (int channel, int connect);
-static int galmpsc_route_rx_clock (int channel, int brg);
-static int galmpsc_route_tx_clock (int channel, int brg);
-static int galmpsc_write_config_regs (int mpsc, int mode);
-static int galmpsc_config_channel_regs (int mpsc);
-static int galmpsc_set_char_length (int mpsc, int value);
-static int galmpsc_set_stop_bit_length (int mpsc, int value);
-static int galmpsc_set_parity (int mpsc, int value);
-static int galmpsc_enter_hunt (int mpsc);
-static int galmpsc_set_brkcnt (int mpsc, int value);
-static int galmpsc_set_tcschar (int mpsc, int value);
-static int galmpsc_set_snoop (int mpsc, int value);
-static int galmpsc_shutdown (int mpsc);
-
-static int galsdma_set_RFT (int channel);
-static int galsdma_set_SFM (int channel);
-static int galsdma_set_rxle (int channel);
-static int galsdma_set_txle (int channel);
-static int galsdma_set_burstsize (int channel, unsigned int value);
-static int galsdma_set_RC (int channel, unsigned int value);
-
-static int galbrg_set_CDV (int channel, int value);
-static int galbrg_enable (int channel);
-static int galbrg_disable (int channel);
-static int galbrg_set_clksrc (int channel, int value);
-static int galbrg_set_CUV (int channel, int value);
-
-static void galsdma_enable_rx (void);
-static int galsdma_set_mem_space (unsigned int memSpace,
- unsigned int memSpaceTarget,
- unsigned int memSpaceAttr,
- unsigned int baseAddress,
- unsigned int size);
-
-
-#define SOFTWARE_CACHE_MANAGEMENT
-
-#ifdef SOFTWARE_CACHE_MANAGEMENT
-#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
-#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
-#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
-#else
-#define FLUSH_DCACHE(a,b)
-#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
-#define INVALIDATE_DCACHE(a,b)
-#endif
-
-#ifdef CONFIG_MPSC_DEBUG_PORT
-static void mpsc_debug_init (void)
-{
-
- volatile unsigned int temp;
-
- /* Clear the CFR (CHR4) */
- /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
- temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
- temp &= 0xffffff00;
- temp |= BIT29;
- GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
- temp);
-
- /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */
- temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP));
- temp |= (BIT12 | BIT15);
- GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP),
- temp);
-
- /* Set int mask */
- temp = GTREGREAD (GALMPSC_0_INT_MASK);
- temp |= BIT6;
- GT_REG_WRITE (GALMPSC_0_INT_MASK, temp);
-}
-#endif
-
-char mpsc_getchar_debug (void)
-{
- volatile int temp;
- volatile unsigned int cause;
-
- cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
- while ((cause & BIT6) == 0) {
- cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
- }
-
- temp = GTREGREAD (GALMPSC_CHANNELREG_10 +
- (CHANNEL * GALMPSC_REG_GAP));
- /* By writing 1's to the set bits, the register is cleared */
- GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP),
- temp);
- GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6);
- return (temp >> 16) & 0xff;
-}
-
-/* special function for running out of flash. doesn't modify any
- * global variables [josh] */
-int mpsc_putchar_early (char ch)
-{
- int mpsc = CHANNEL;
- int temp =
- GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
- galmpsc_set_tcschar (mpsc, ch);
- GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP),
- temp | 0x200);
-
-#define MAGIC_FACTOR (10*1000000)
-
- udelay (MAGIC_FACTOR / gd->baudrate);
- return 0;
-}
-
-/* This is used after relocation, see serial.c and mpsc_init2 */
-static int mpsc_putchar_sdma (char ch)
-{
- volatile unsigned int *p;
- unsigned int temp;
-
-
- /* align the descriptor */
- p = tx_desc_base;
- memset ((void *) p, 0, 8 * sizeof (unsigned int));
-
- /* fill one 64 bit buffer */
- /* word swap, pad with 0 */
- p[4] = 0; /* x */
- p[5] = (unsigned int) ch; /* x */
-
- /* CHANGED completely according to GT64260A dox - NTL */
- p[0] = 0x00010001; /* 0 */
- p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* 4 */
- p[2] = 0; /* 8 */
- p[3] = (unsigned int) &p[4]; /* c */
-
-#if 0
- p[9] = DESC_FIRST | DESC_LAST;
- p[10] = (unsigned int) &p[0];
- p[11] = (unsigned int) &p[12];
-#endif
-
- FLUSH_DCACHE (&p[0], &p[8]);
-
- GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
- (unsigned int) &p[0]);
- GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
- (unsigned int) &p[0]);
-
- temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
- temp |= (TX_DEMAND | TX_STOP);
- GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
-
- INVALIDATE_DCACHE (&p[1], &p[2]);
-
- while (p[1] & DESC_OWNER_BIT) {
- udelay (100);
- INVALIDATE_DCACHE (&p[1], &p[2]);
- }
- return 0;
-}
-
-char mpsc_getchar_sdma (void)
-{
- static unsigned int done = 0;
- volatile char ch;
- unsigned int len = 0, idx = 0, temp;
-
- volatile unsigned int *p;
-
-
- do {
- p = &rx_desc_base[rx_desc_index * 8];
-
- INVALIDATE_DCACHE (&p[0], &p[1]);
- /* Wait for character */
- while (p[1] & DESC_OWNER_BIT) {
- udelay (100);
- INVALIDATE_DCACHE (&p[0], &p[1]);
- }
-
- /* Handle error case */
- if (p[1] & (1 << 15)) {
- printf ("oops, error: %08x\n", p[1]);
-
- temp = GTREGREAD (GALMPSC_CHANNELREG_2 +
- (CHANNEL * GALMPSC_REG_GAP));
- temp |= (1 << 23);
- GT_REG_WRITE (GALMPSC_CHANNELREG_2 +
- (CHANNEL * GALMPSC_REG_GAP), temp);
-
- /* Can't poll on abort bit, so we just wait. */
- udelay (100);
-
- galsdma_enable_rx ();
- }
-
- /* Number of bytes left in this descriptor */
- len = p[0] & 0xffff;
-
- if (len) {
- /* Where to look */
- idx = 5;
- if (done > 3)
- idx = 4;
- if (done > 7)
- idx = 7;
- if (done > 11)
- idx = 6;
-
- INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
- ch = p[idx] & 0xff;
- done++;
- }
-
- if (done < len) {
- /* this descriptor has more bytes still
- * shift down the char we just read, and leave the
- * buffer in place for the next time around
- */
- p[idx] = p[idx] >> 8;
- FLUSH_DCACHE (&p[idx], &p[idx + 1]);
- }
-
- if (done == len) {
- /* nothing left in this descriptor.
- * go to next one
- */
- p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
- p[0] = 0x00100000;
- FLUSH_DCACHE (&p[0], &p[1]);
- /* Next descriptor */
- rx_desc_index = (rx_desc_index + 1) % RX_DESC;
- done = 0;
- }
- } while (len == 0); /* galileo bug.. len might be zero */
-
- return ch;
-}
-
-
-int mpsc_test_char_debug (void)
-{
- if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0)
- return 0;
- else {
- return 1;
- }
-}
-
-
-int mpsc_test_char_sdma (void)
-{
- volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8];
-
- INVALIDATE_DCACHE (&p[1], &p[2]);
-
- if (p[1] & DESC_OWNER_BIT)
- return 0;
- else
- return 1;
-}
-
-int mpsc_init (int baud)
-{
- /* BRG CONFIG */
- galbrg_set_baudrate (CHANNEL, baud);
- galbrg_set_clksrc (CHANNEL, 8); /* set source=Tclk */
- galbrg_set_CUV (CHANNEL, 0); /* set up CountUpValue */
- galbrg_enable (CHANNEL); /* Enable BRG */
-
- /* Set up clock routing */
- galmpsc_connect (CHANNEL, GALMPSC_CONNECT); /* connect it */
-
- galmpsc_route_rx_clock (CHANNEL, CHANNEL); /* chosse BRG0 for Rx */
- galmpsc_route_tx_clock (CHANNEL, CHANNEL); /* chose BRG0 for Tx */
-
- /* reset MPSC state */
- galmpsc_shutdown (CHANNEL);
-
- /* SDMA CONFIG */
- galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8); /* in 64 bit words (8 bytes) */
- galsdma_set_txle (CHANNEL);
- galsdma_set_rxle (CHANNEL);
- galsdma_set_RC (CHANNEL, 0xf);
- galsdma_set_SFM (CHANNEL);
- galsdma_set_RFT (CHANNEL);
-
- /* MPSC CONFIG */
- galmpsc_write_config_regs (CHANNEL, GALMPSC_UART);
- galmpsc_config_channel_regs (CHANNEL);
- galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */
- galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE); /* N */
- galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */
-
-#ifdef CONFIG_MPSC_DEBUG_PORT
- mpsc_debug_init ();
-#endif
-
- /* COMM_MPSC CONFIG */
-#ifdef SOFTWARE_CACHE_MANAGEMENT
- galmpsc_set_snoop (CHANNEL, 0); /* disable snoop */
-#else
- galmpsc_set_snoop (CHANNEL, 1); /* enable snoop */
-#endif
-
- return 0;
-}
-
-
-void mpsc_sdma_init (void)
-{
-/* Setup SDMA channel0 SDMA_CONFIG_REG*/
- GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff);
-
-/* Enable MPSC-Window0 for DRAM Bank0 */
- if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT,
- MV64460_SDMA_DRAM_CS_0_TARGET,
- 0,
- memoryGetBankBaseAddress
- (CS_0_LOW_DECODE_ADDRESS),
- memoryGetBankSize (BANK0)) != true)
- printf ("%s: SDMA_Window0 memory setup failed !!! \n",
- __FUNCTION__);
-
-
-/* Disable MPSC-Window1 */
- if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_1_BIT,
- MV64460_SDMA_DRAM_CS_0_TARGET,
- 0,
- memoryGetBankBaseAddress
- (CS_1_LOW_DECODE_ADDRESS),
- memoryGetBankSize (BANK3)) != true)
- printf ("%s: SDMA_Window1 memory setup failed !!! \n",
- __FUNCTION__);
-
-
-/* Disable MPSC-Window2 */
- if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_2_BIT,
- MV64460_SDMA_DRAM_CS_0_TARGET,
- 0,
- memoryGetBankBaseAddress
- (CS_2_LOW_DECODE_ADDRESS),
- memoryGetBankSize (BANK3)) != true)
- printf ("%s: SDMA_Window2 memory setup failed !!! \n",
- __FUNCTION__);
-
-
-/* Disable MPSC-Window3 */
- if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_3_BIT,
- MV64460_SDMA_DRAM_CS_0_TARGET,
- 0,
- memoryGetBankBaseAddress
- (CS_3_LOW_DECODE_ADDRESS),
- memoryGetBankSize (BANK3)) != true)
- printf ("%s: SDMA_Window3 memory setup failed !!! \n",
- __FUNCTION__);
-
-/* Setup MPSC0 access mode Window0 full access */
- GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG,
- (MV64460_SDMA_WIN_ACCESS_FULL <<
- (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
-
-/* Setup MPSC1 access mode Window1 full access */
- GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG,
- (MV64460_SDMA_WIN_ACCESS_FULL <<
- (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
-
-/* Setup MPSC internal address space base address */
- GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
-
-/* no high address remap*/
- GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
- GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00);
-
-/* clear interrupt cause register for MPSC (fault register)*/
- GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00);
-}
-
-
-void mpsc_init2 (void)
-{
- int i;
-
-#ifndef CONFIG_MPSC_DEBUG_PORT
- mpsc_putchar = mpsc_putchar_sdma;
- mpsc_getchar = mpsc_getchar_sdma;
- mpsc_test_char = mpsc_test_char_sdma;
-#endif
- /* RX descriptors */
- rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) *
- sizeof (unsigned int));
-
- /* align descriptors */
- rx_desc_base = (unsigned int *)
- (((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0);
-
- rx_desc_index = 0;
-
- memset ((void *) rx_desc_base, 0,
- (RX_DESC * 8) * sizeof (unsigned int));
-
- for (i = 0; i < RX_DESC; i++) {
- rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4]; /* Buffer */
- rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8]; /* Next descriptor */
- rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* Command & control */
- rx_desc_base[i * 8] = 0x00100000;
- }
- rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0];
-
- FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]);
- GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
- (unsigned int) &rx_desc_base[0]);
-
- /* TX descriptors */
- tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) *
- sizeof (unsigned int));
-
- /* align descriptors */
- tx_desc_base = (unsigned int *)
- (((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0);
-
- tx_desc_index = -1;
-
- memset ((void *) tx_desc_base, 0,
- (TX_DESC * 8) * sizeof (unsigned int));
-
- for (i = 0; i < TX_DESC; i++) {
- tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323;
- tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323;
- tx_desc_base[i * 8 + 3] =
- (unsigned int) &tx_desc_base[i * 8 + 4];
- tx_desc_base[i * 8 + 2] =
- (unsigned int) &tx_desc_base[(i + 1) * 8];
- tx_desc_base[i * 8 + 1] =
- DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
-
- /* set sbytecnt and shadow byte cnt to 1 */
- tx_desc_base[i * 8] = 0x00010001;
- }
- tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0];
-
- FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]);
-
- udelay (100);
-
- galsdma_enable_rx ();
-
- return;
-}
-
-int galbrg_set_baudrate (int channel, int rate)
-{
- int clock;
-
- galbrg_disable (channel); /*ok */
-
-#ifdef ZUMA_NTL
- /* from tclk */
- clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
-#else
- clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
-#endif
-
- galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */
-
- galbrg_enable (channel);
-
- gd->baudrate = rate;
-
- return 0;
-}
-
-/* ------------------------------------------------------------------ */
-
-/* Below are all the private functions that no one else needs */
-
-static int galbrg_set_CDV (int channel, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
- temp &= 0xFFFF0000;
- temp |= (value & 0x0000FFFF);
- GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
- return 0;
-}
-
-static int galbrg_enable (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
- temp |= 0x00010000;
- GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
- return 0;
-}
-
-static int galbrg_disable (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
- temp &= 0xFFFEFFFF;
- GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
- return 0;
-}
-
-static int galbrg_set_clksrc (int channel, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
- temp &= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */
- temp |= (value << 18);
- GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
- return 0;
-}
-
-static int galbrg_set_CUV (int channel, int value)
-{
- /* set CountUpValue */
- GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
-
- return 0;
-}
-
-#if 0
-static int galbrg_reset (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
- temp |= 0x20000;
- GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
- return 0;
-}
-#endif
-
-static int galsdma_set_RFT (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
- temp |= 0x00000001;
- GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
- temp);
-
- return 0;
-}
-
-static int galsdma_set_SFM (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
- temp |= 0x00000002;
- GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
- temp);
-
- return 0;
-}
-
-static int galsdma_set_rxle (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
- temp |= 0x00000040;
- GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
- temp);
-
- return 0;
-}
-
-static int galsdma_set_txle (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
- temp |= 0x00000080;
- GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
- temp);
-
- return 0;
-}
-
-static int galsdma_set_RC (int channel, unsigned int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
- temp &= ~0x0000003c;
- temp |= (value << 2);
- GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
- temp);
-
- return 0;
-}
-
-static int galsdma_set_burstsize (int channel, unsigned int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
- temp &= 0xFFFFCFFF;
- switch (value) {
- case 8:
- GT_REG_WRITE (GALSDMA_0_CONF_REG +
- (channel * GALSDMA_REG_DIFF),
- (temp | (0x3 << 12)));
- break;
-
- case 4:
- GT_REG_WRITE (GALSDMA_0_CONF_REG +
- (channel * GALSDMA_REG_DIFF),
- (temp | (0x2 << 12)));
- break;
-
- case 2:
- GT_REG_WRITE (GALSDMA_0_CONF_REG +
- (channel * GALSDMA_REG_DIFF),
- (temp | (0x1 << 12)));
- break;
-
- case 1:
- GT_REG_WRITE (GALSDMA_0_CONF_REG +
- (channel * GALSDMA_REG_DIFF),
- (temp | (0x0 << 12)));
- break;
-
- default:
- return -1;
- break;
- }
-
- return 0;
-}
-
-static int galmpsc_connect (int channel, int connect)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_ROUTING_REGISTER);
-
- if ((channel == 0) && connect)
- temp &= ~0x00000007;
- else if ((channel == 1) && connect)
- temp &= ~(0x00000007 << 6);
- else if ((channel == 0) && !connect)
- temp |= 0x00000007;
- else
- temp |= (0x00000007 << 6);
-
- /* Just in case... */
- temp &= 0x3fffffff;
-
- GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp);
-
- return 0;
-}
-
-static int galmpsc_route_rx_clock (int channel, int brg)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_RxC_ROUTE);
-
- if (channel == 0) {
- temp &= ~0x0000000F;
- temp |= brg;
- } else {
- temp &= ~0x00000F00;
- temp |= (brg << 8);
- }
-
- GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp);
-
- return 0;
-}
-
-static int galmpsc_route_tx_clock (int channel, int brg)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_TxC_ROUTE);
-
- if (channel == 0) {
- temp &= ~0x0000000F;
- temp |= brg;
- } else {
- temp &= ~0x00000F00;
- temp |= (brg << 8);
- }
-
- GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp);
-
- return 0;
-}
-
-static int galmpsc_write_config_regs (int mpsc, int mode)
-{
- if (mode == GALMPSC_UART) {
- /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
- GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP),
- 0x000004c4);
-
- /* Main config reg High (32x Rx/Tx clock mode, width=8bits */
- GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP),
- 0x024003f8);
- /* 22 2222 1111 */
- /* 54 3210 9876 */
- /* 0000 0010 0000 0000 */
- /* 1 */
- /* 098 7654 3210 */
- /* 0000 0011 1111 1000 */
- } else
- return -1;
-
- return 0;
-}
-
-static int galmpsc_config_channel_regs (int mpsc)
-{
- GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1);
- GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0);
-
- galmpsc_set_brkcnt (mpsc, 0x3);
- galmpsc_set_tcschar (mpsc, 0xab);
-
- return 0;
-}
-
-static int galmpsc_set_brkcnt (int mpsc, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
- temp &= 0x0000FFFF;
- temp |= (value << 16);
- GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
-
- return 0;
-}
-
-static int galmpsc_set_tcschar (int mpsc, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
- temp &= 0xFFFF0000;
- temp |= value;
- GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
-
- return 0;
-}
-
-static int galmpsc_set_char_length (int mpsc, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
- temp &= 0xFFFFCFFF;
- temp |= (value << 12);
- GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
-
- return 0;
-}
-
-static int galmpsc_set_stop_bit_length (int mpsc, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
- temp &= 0xFFFFBFFF;
- temp |= (value << 14);
- GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
-
- return 0;
-}
-
-static int galmpsc_set_parity (int mpsc, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
- if (value != -1) {
- temp &= 0xFFF3FFF3;
- temp |= ((value << 18) | (value << 2));
- temp |= ((value << 17) | (value << 1));
- } else {
- temp &= 0xFFF1FFF1;
- }
-
- GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
-
- return 0;
-}
-
-static int galmpsc_enter_hunt (int mpsc)
-{
- int temp;
-
- temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
- temp |= 0x80000000;
- GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
-
- while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) &
- MPSC_ENTER_HUNT) {
- udelay (1);
- }
- return 0;
-}
-
-
-static int galmpsc_shutdown (int mpsc)
-{
- unsigned int temp;
-
- /* cause RX abort (clears RX) */
- temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
- temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
- temp &= ~MPSC_ENTER_HUNT;
- GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
-
- GT_REG_WRITE (GALSDMA_0_COM_REG, 0);
- GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT);
-
- /* shut down the MPSC */
- GT_REG_WRITE (GALMPSC_MCONF_LOW, 0);
- GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0);
- GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0);
-
- udelay (100);
-
- /* shut down the sdma engines. */
- /* reset config to default */
- GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc);
-
- udelay (100);
-
- /* clear the SDMA current and first TX and RX pointers */
- GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0);
- GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0);
- GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0);
-
- udelay (100);
-
- return 0;
-}
-
-static void galsdma_enable_rx (void)
-{
- int temp;
-
- /* Enable RX processing */
- temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
- temp |= RX_ENABLE;
- GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
-
- galmpsc_enter_hunt (CHANNEL);
-}
-
-static int galmpsc_set_snoop (int mpsc, int value)
-{
- int reg =
- mpsc ? MPSC_1_ADDRESS_CONTROL_LOW :
- MPSC_0_ADDRESS_CONTROL_LOW;
- int temp = GTREGREAD (reg);
-
- if (value)
- temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);
- else
- temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));
- GT_REG_WRITE (reg, temp);
- return 0;
-}
-
-/*******************************************************************************
-* galsdma_set_mem_space - Set MV64460 IDMA memory decoding map.
-*
-* DESCRIPTION:
-* the MV64460 SDMA has its own address decoding map that is de-coupled
-* from the CPU interface address decoding windows. The SDMA channels
-* share four address windows. Each region can be individually configured
-* by this function by associating it to a target interface and setting
-* base and size values.
-*
-* NOTE!!!
-* The size must be in 64Kbyte granularity.
-* The base address must be aligned to the size.
-* The size must be a series of 1s followed by a series of zeros
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* true for success, false otherwise.
-*
-*******************************************************************************/
-
-static int galsdma_set_mem_space (unsigned int memSpace,
- unsigned int memSpaceTarget,
- unsigned int memSpaceAttr,
- unsigned int baseAddress, unsigned int size)
-{
- unsigned int temp;
-
- if (size == 0) {
- GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG,
- 1 << memSpace);
- return true;
- }
-
- /* The base address must be aligned to the size. */
- if (baseAddress % size != 0) {
- return false;
- }
- if (size < 0x10000) {
- return false;
- }
-
- /* Align size and base to 64K */
- baseAddress &= 0xffff0000;
- size &= 0xffff0000;
- temp = size >> 16;
-
- /* Checking that the size is a sequence of '1' followed by a
- sequence of '0' starting from LSB to MSB. */
- while ((temp > 0) && (temp & 0x1)) {
- temp = temp >> 1;
- }
-
- if (temp != 0) {
- GT_REG_WRITE (MV64460_CUNIT_BASE_ADDR_REG0 + memSpace * 8,
- (baseAddress | memSpaceTarget | memSpaceAttr));
- GT_REG_WRITE ((MV64460_CUNIT_SIZE0 + memSpace * 8),
- (size - 1) & 0xffff0000);
- GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG,
- 1 << memSpace);
- } else {
- /* An invalid size was specified */
- return false;
- }
- return true;
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*************************************************************************
- * changes for Marvell DB64460 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
- *
- ************************************************************************/
-
-
-/*
- * mpsc.h - header file for MPSC in uart mode (console driver)
- */
-
-#ifndef __MPSC_H__
-#define __MPSC_H__
-
-/* include actual Galileo defines */
-#include "../include/mv_gen_reg.h"
-
-/* driver related defines */
-
-int mpsc_init(int baud);
-void mpsc_sdma_init(void);
-void mpsc_init2(void);
-int galbrg_set_baudrate(int channel, int rate);
-
-int mpsc_putchar_early(char ch);
-char mpsc_getchar_debug(void);
-int mpsc_test_char_debug(void);
-
-int mpsc_test_char_sdma(void);
-
-extern int (*mpsc_putchar)(char ch);
-extern char (*mpsc_getchar)(void);
-extern int (*mpsc_test_char)(void);
-
-#define CHANNEL CONFIG_MPSC_PORT
-
-#define TX_DESC 5
-#define RX_DESC 20
-
-#define DESC_FIRST 0x00010000
-#define DESC_LAST 0x00020000
-#define DESC_OWNER_BIT 0x80000000
-
-#define TX_DEMAND 0x00800000
-#define TX_STOP 0x00010000
-#define RX_ENABLE 0x00000080
-
-#define SDMA_RX_ABORT (1 << 15)
-#define SDMA_TX_ABORT (1 << 31)
-#define MPSC_TX_ABORT (1 << 7)
-#define MPSC_RX_ABORT (1 << 23)
-#define MPSC_ENTER_HUNT (1 << 31)
-
-/* MPSC defines */
-
-#define GALMPSC_CONNECT 0x1
-#define GALMPSC_DISCONNECT 0x0
-
-#define GALMPSC_UART 0x1
-
-#define GALMPSC_STOP_BITS_1 0x0
-#define GALMPSC_STOP_BITS_2 0x1
-#define GALMPSC_CHAR_LENGTH_8 0x3
-#define GALMPSC_CHAR_LENGTH_7 0x2
-
-#define GALMPSC_PARITY_ODD 0x0
-#define GALMPSC_PARITY_EVEN 0x2
-#define GALMPSC_PARITY_MARK 0x3
-#define GALMPSC_PARITY_SPACE 0x1
-#define GALMPSC_PARITY_NONE -1
-
-#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */
-#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */
-#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */
-#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
-#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */
-#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */
-#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */
-
-#define GALMPSC_REG_GAP 0x1000
-
-#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */
-#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */
-#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */
-#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */
-#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */
-#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */
-#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */
-#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */
-#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */
-#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */
-#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */
-#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */
-
-#define GALSDMA_COMMAND_FIRST (1 << 16)
-#define GALSDMA_COMMAND_LAST (1 << 17)
-#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
-#define GALSDMA_COMMAND_AUTO (1 << 30)
-#define GALSDMA_COMMAND_OWNER (1 << 31)
-
-#define GALSDMA_RX 0
-#define GALSDMA_TX 1
-
-/* CHANNEL2 should be CHANNEL1, according to documentation,
- * but to work with the current GTREGS file...
- */
-#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */
-#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */
-#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */
-#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */
-#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */
-#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */
-#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */
-#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */
-#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */
-#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */
-#define GALSDMA_REG_DIFF 0x2000
-
-/* WRONG in gt64260R.h */
-#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */
-#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */
-#define GALMPSC_0_INT_CAUSE 0xb804
-#define GALMPSC_0_INT_MASK 0xb884
-
-#define GALSDMA_MODE_UART 0
-#define GALSDMA_MODE_BISYNC 1
-#define GALSDMA_MODE_HDLC 2
-#define GALSDMA_MODE_TRANSPARENT 3
-
-#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */
-#define GALBRG_REG_GAP 0x0008
-#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */
-
-#endif /* __MPSC_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64460X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * mv_eth.c - header file for the polled mode GT ethernet driver
- */
-#include <common.h>
-#include <net.h>
-#include <malloc.h>
-
-#include "mv_eth.h"
-
-/* enable Debug outputs */
-
-#undef DEBUG_MV_ETH
-
-#ifdef DEBUG_MV_ETH
-#define DEBUG
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-#undef MV64460_CHECKSUM_OFFLOAD
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-* The first part is the high level driver of the gigE ethernet ports. *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-
-/* Definition for configuring driver */
-/* #define UPDATE_STATS_BY_SOFTWARE */
-#undef MV64460_RX_QUEUE_FILL_ON_TASK
-
-
-/* Constants */
-#define MAGIC_ETH_RUNNING 8031971
-#define MV64460_INTERNAL_SRAM_SIZE _256K
-#define EXTRA_BYTES 32
-#define WRAP ETH_HLEN + 2 + 4 + 16
-#define BUFFER_MTU dev->mtu + WRAP
-#define INT_CAUSE_UNMASK_ALL 0x0007ffff
-#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
-#ifdef MV64460_RX_FILL_ON_TASK
-#define INT_CAUSE_MASK_ALL 0x00000000
-#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
-#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
-#endif
-
-/* Read/Write to/from MV64460 internal registers */
-#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
-#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
-#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
-#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
-
-/* Static function declarations */
-static int mv64460_eth_real_open (struct eth_device *eth);
-static int mv64460_eth_real_stop (struct eth_device *eth);
-static struct net_device_stats *mv64460_eth_get_stats (struct eth_device
- *dev);
-static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
-static void mv64460_eth_update_stat (struct eth_device *dev);
-bool db64460_eth_start (struct eth_device *eth);
-unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
- unsigned int mib_offset);
-int mv64460_eth_receive (struct eth_device *dev);
-
-int mv64460_eth_xmit (struct eth_device *, volatile void *packet, int length);
-
-#ifndef UPDATE_STATS_BY_SOFTWARE
-static void mv64460_eth_print_stat (struct eth_device *dev);
-#endif
-
-extern unsigned int INTERNAL_REG_BASE_ADDR;
-
-/*************************************************
- *Helper functions - used inside the driver only *
- *************************************************/
-#ifdef DEBUG_MV_ETH
-void print_globals (struct eth_device *dev)
-{
- printf ("Ethernet PRINT_Globals-Debug function\n");
- printf ("Base Address for ETH_PORT_INFO: %08x\n",
- (unsigned int) dev->priv);
- printf ("Base Address for mv64460_eth_priv: %08x\n",
- (unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
- port_private));
-
- printf ("GT Internal Base Address: %08x\n",
- INTERNAL_REG_BASE_ADDR);
- printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64460_TX_QUEUE_SIZE);
- printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64460_RX_QUEUE_SIZE);
- printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n",
- (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
- p_rx_buffer_base[0],
- (MV64460_RX_QUEUE_SIZE * MV64460_RX_BUFFER_SIZE) + 32);
- printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n",
- (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
- p_tx_buffer_base[0],
- (MV64460_TX_QUEUE_SIZE * MV64460_TX_BUFFER_SIZE) + 32);
-}
-#endif
-
-#define my_cpu_to_le32(x) my_le32_to_cpu((x))
-
-unsigned long my_le32_to_cpu (unsigned long x)
-{
- return (((x & 0x000000ffU) << 24) |
- ((x & 0x0000ff00U) << 8) |
- ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
-}
-
-
-/**********************************************************************
- * mv64460_eth_print_phy_status
- *
- * Prints gigabit ethenret phy status
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- **********************************************************************/
-
-static void mv64460_eth_print_phy_status (struct eth_device *dev)
-{
- struct mv64460_eth_priv *port_private;
- unsigned int port_num;
- ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
- unsigned int port_status, phy_reg_data;
-
- port_private =
- (struct mv64460_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
-
- /* Check Link status on phy */
- eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
- if (!(phy_reg_data & 0x20)) {
- printf ("Ethernet port changed link status to DOWN\n");
- } else {
- port_status =
- MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
- printf ("Ethernet status port %d: Link up", port_num);
- printf (", %s",
- (port_status & BIT2) ? "Full Duplex" : "Half Duplex");
- if (port_status & BIT4)
- printf (", Speed 1 Gbps");
- else
- printf (", %s",
- (port_status & BIT5) ? "Speed 100 Mbps" :
- "Speed 10 Mbps");
- printf ("\n");
- }
-}
-
-/**********************************************************************
- * u-boot entry functions for mv64460_eth
- *
- **********************************************************************/
-int db64460_eth_probe (struct eth_device *dev)
-{
- return ((int) db64460_eth_start (dev));
-}
-
-int db64460_eth_poll (struct eth_device *dev)
-{
- return mv64460_eth_receive (dev);
-}
-
-int db64460_eth_transmit(struct eth_device *dev, void *packet, int length)
-{
- mv64460_eth_xmit (dev, packet, length);
- return 0;
-}
-
-void db64460_eth_disable (struct eth_device *dev)
-{
- mv64460_eth_stop (dev);
-}
-
-
-void mv6446x_eth_initialize (bd_t * bis)
-{
- struct eth_device *dev;
- ETH_PORT_INFO *ethernet_private;
- struct mv64460_eth_priv *port_private;
- int devnum, x, temp;
- char *s, *e, buf[64];
-
- for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
- dev = calloc (sizeof (*dev), 1);
- if (!dev) {
- printf ("%s: mv_enet%d allocation failure, %s\n",
- __FUNCTION__, devnum, "eth_device structure");
- return;
- }
-
- /* must be less than sizeof(dev->name) */
- sprintf (dev->name, "mv_enet%d", devnum);
-
-#ifdef DEBUG
- printf ("Initializing %s\n", dev->name);
-#endif
-
- /* Extract the MAC address from the environment */
- switch (devnum) {
- case 0:
- s = "ethaddr";
- break;
-
- case 1:
- s = "eth1addr";
- break;
-
- case 2:
- s = "eth2addr";
- break;
-
- default: /* this should never happen */
- printf ("%s: Invalid device number %d\n",
- __FUNCTION__, devnum);
- return;
- }
-
- temp = getenv_f(s, buf, sizeof (buf));
- s = (temp > 0) ? buf : NULL;
-
-#ifdef DEBUG
- printf ("Setting MAC %d to %s\n", devnum, s);
-#endif
- for (x = 0; x < 6; ++x) {
- dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
- if (s)
- s = (*e) ? e + 1 : e;
- }
- /* ronen - set the MAC addr in the HW */
- eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
-
- dev->init = (void *) db64460_eth_probe;
- dev->halt = (void *) ethernet_phy_reset;
- dev->send = (void *) db64460_eth_transmit;
- dev->recv = (void *) db64460_eth_poll;
-
- ethernet_private = calloc (sizeof (*ethernet_private), 1);
- dev->priv = (void *)ethernet_private;
- if (!ethernet_private) {
- printf ("%s: %s allocation failure, %s\n",
- __FUNCTION__, dev->name,
- "Private Device Structure");
- free (dev);
- return;
- }
- /* start with an zeroed ETH_PORT_INFO */
- memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
- memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
-
- /* set pointer to memory for stats data structure etc... */
- port_private = calloc (sizeof (*ethernet_private), 1);
- ethernet_private->port_private = (void *)port_private;
- if (!port_private) {
- printf ("%s: %s allocation failure, %s\n",
- __FUNCTION__, dev->name,
- "Port Private Device Structure");
-
- free (ethernet_private);
- free (dev);
- return;
- }
-
- port_private->stats =
- calloc (sizeof (struct net_device_stats), 1);
- if (!port_private->stats) {
- printf ("%s: %s allocation failure, %s\n",
- __FUNCTION__, dev->name,
- "Net stat Structure");
-
- free (port_private);
- free (ethernet_private);
- free (dev);
- return;
- }
- memset (ethernet_private->port_private, 0,
- sizeof (struct mv64460_eth_priv));
- switch (devnum) {
- case 0:
- ethernet_private->port_num = ETH_0;
- break;
- case 1:
- ethernet_private->port_num = ETH_1;
- break;
- case 2:
- ethernet_private->port_num = ETH_2;
- break;
- default:
- printf ("Invalid device number %d\n", devnum);
- break;
- };
-
- port_private->port_num = devnum;
- /*
- * Read MIB counter on the GT in order to reset them,
- * then zero all the stats fields in memory
- */
- mv64460_eth_update_stat (dev);
- memset (port_private->stats, 0,
- sizeof (struct net_device_stats));
- /* Extract the MAC address from the environment */
- switch (devnum) {
- case 0:
- s = "ethaddr";
- break;
-
- case 1:
- s = "eth1addr";
- break;
-
- case 2:
- s = "eth2addr";
- break;
-
- default: /* this should never happen */
- printf ("%s: Invalid device number %d\n",
- __FUNCTION__, devnum);
- return;
- }
-
- temp = getenv_f(s, buf, sizeof (buf));
- s = (temp > 0) ? buf : NULL;
-
-#ifdef DEBUG
- printf ("Setting MAC %d to %s\n", devnum, s);
-#endif
- for (x = 0; x < 6; ++x) {
- dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
- if (s)
- s = (*e) ? e + 1 : e;
- }
-
- DP (printf ("Allocating descriptor and buffer rings\n"));
-
- ethernet_private->p_rx_desc_area_base[0] =
- (ETH_RX_DESC *) memalign (16,
- RX_DESC_ALIGNED_SIZE *
- MV64460_RX_QUEUE_SIZE + 1);
- ethernet_private->p_tx_desc_area_base[0] =
- (ETH_TX_DESC *) memalign (16,
- TX_DESC_ALIGNED_SIZE *
- MV64460_TX_QUEUE_SIZE + 1);
-
- ethernet_private->p_rx_buffer_base[0] =
- (char *) memalign (16,
- MV64460_RX_QUEUE_SIZE *
- MV64460_TX_BUFFER_SIZE + 1);
- ethernet_private->p_tx_buffer_base[0] =
- (char *) memalign (16,
- MV64460_RX_QUEUE_SIZE *
- MV64460_TX_BUFFER_SIZE + 1);
-
-#ifdef DEBUG_MV_ETH
- /* DEBUG OUTPUT prints adresses of globals */
- print_globals (dev);
-#endif
- eth_register (dev);
-
- }
- DP (printf ("%s: exit\n", __FUNCTION__));
-
-}
-
-/**********************************************************************
- * mv64460_eth_open
- *
- * This function is called when openning the network device. The function
- * should initialize all the hardware, initialize cyclic Rx/Tx
- * descriptors chain and buffers and allocate an IRQ to the network
- * device.
- *
- * Input : a pointer to the network device structure
- * / / ronen - changed the output to match net/eth.c needs
- * Output : nonzero of success , zero if fails.
- * under construction
- **********************************************************************/
-
-int mv64460_eth_open (struct eth_device *dev)
-{
- return (mv64460_eth_real_open (dev));
-}
-
-/* Helper function for mv64460_eth_open */
-static int mv64460_eth_real_open (struct eth_device *dev)
-{
-
- unsigned int queue;
- ETH_PORT_INFO *ethernet_private;
- struct mv64460_eth_priv *port_private;
- unsigned int port_num;
- u32 phy_reg_data;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- /* ronen - when we update the MAC env params we only update dev->enetaddr
- see ./net/eth.c eth_set_enetaddr() */
- memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
-
- port_private =
- (struct mv64460_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
-
- /* Stop RX Queues */
- MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
- 0x0000ff00);
-
- /* Clear the ethernet port interrupts */
- MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
- MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
-
- /* Unmask RX buffer and TX end interrupt */
- MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num),
- INT_CAUSE_UNMASK_ALL);
-
- /* Unmask phy and link status changes interrupts */
- MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
- INT_CAUSE_UNMASK_ALL_EXT);
-
- /* Set phy address of the port */
- ethernet_private->port_phy_addr = 0x8 + port_num;
-
- /* Activate the DMA channels etc */
- eth_port_init (ethernet_private);
-
-
- /* "Allocate" setup TX rings */
-
- for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {
- unsigned int size;
-
- port_private->tx_ring_size[queue] = MV64460_TX_QUEUE_SIZE;
- size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */
- ethernet_private->tx_desc_area_size[queue] = size;
-
- /* first clear desc area completely */
- memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
- 0, ethernet_private->tx_desc_area_size[queue]);
-
- /* initialize tx desc ring with low level driver */
- if (ether_init_tx_desc_ring
- (ethernet_private, ETH_Q0,
- port_private->tx_ring_size[queue],
- MV64460_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
- (unsigned int) ethernet_private->
- p_tx_desc_area_base[queue],
- (unsigned int) ethernet_private->
- p_tx_buffer_base[queue]) == false)
- printf ("### Error initializing TX Ring\n");
- }
-
- /* "Allocate" setup RX rings */
- for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {
- unsigned int size;
-
- /* Meantime RX Ring are fixed - but must be configurable by user */
- port_private->rx_ring_size[queue] = MV64460_RX_QUEUE_SIZE;
- size = (port_private->rx_ring_size[queue] *
- RX_DESC_ALIGNED_SIZE);
- ethernet_private->rx_desc_area_size[queue] = size;
-
- /* first clear desc area completely */
- memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
- 0, ethernet_private->rx_desc_area_size[queue]);
- if ((ether_init_rx_desc_ring
- (ethernet_private, ETH_Q0,
- port_private->rx_ring_size[queue],
- MV64460_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
- (unsigned int) ethernet_private->
- p_rx_desc_area_base[queue],
- (unsigned int) ethernet_private->
- p_rx_buffer_base[queue])) == false)
- printf ("### Error initializing RX Ring\n");
- }
-
- eth_port_start (ethernet_private);
-
- /* Set maximum receive buffer to 9700 bytes */
- MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num),
- (0x5 << 17) |
- (MV_REG_READ
- (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num))
- & 0xfff1ffff));
-
- /*
- * Set ethernet MTU for leaky bucket mechanism to 0 - this will
- * disable the leaky bucket mechanism .
- */
-
- MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
- MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
-
- /* Check Link status on phy */
- eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
- if (!(phy_reg_data & 0x20)) {
- /* Reset PHY */
- if ((ethernet_phy_reset (port_num)) != true) {
- printf ("$$ Warnning: No link on port %d \n",
- port_num);
- return 0;
- } else {
- eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
- if (!(phy_reg_data & 0x20)) {
- printf ("### Error: Phy is not active\n");
- return 0;
- }
- }
- } else {
- mv64460_eth_print_phy_status (dev);
- }
- port_private->eth_running = MAGIC_ETH_RUNNING;
- return 1;
-}
-
-
-static int mv64460_eth_free_tx_rings (struct eth_device *dev)
-{
- unsigned int queue;
- ETH_PORT_INFO *ethernet_private;
- struct mv64460_eth_priv *port_private;
- unsigned int port_num;
- volatile ETH_TX_DESC *p_tx_curr_desc;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64460_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
-
- /* Stop Tx Queues */
- MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
- 0x0000ff00);
-
- /* Free TX rings */
- DP (printf ("Clearing previously allocated TX queues... "));
- for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {
- /* Free on TX rings */
- for (p_tx_curr_desc =
- ethernet_private->p_tx_desc_area_base[queue];
- ((unsigned int) p_tx_curr_desc <= (unsigned int)
- ethernet_private->p_tx_desc_area_base[queue] +
- ethernet_private->tx_desc_area_size[queue]);
- p_tx_curr_desc =
- (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
- TX_DESC_ALIGNED_SIZE)) {
- /* this is inside for loop */
- if (p_tx_curr_desc->return_info != 0) {
- p_tx_curr_desc->return_info = 0;
- DP (printf ("freed\n"));
- }
- }
- DP (printf ("Done\n"));
- }
- return 0;
-}
-
-static int mv64460_eth_free_rx_rings (struct eth_device *dev)
-{
- unsigned int queue;
- ETH_PORT_INFO *ethernet_private;
- struct mv64460_eth_priv *port_private;
- unsigned int port_num;
- volatile ETH_RX_DESC *p_rx_curr_desc;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64460_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
-
-
- /* Stop RX Queues */
- MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
- 0x0000ff00);
-
- /* Free RX rings */
- DP (printf ("Clearing previously allocated RX queues... "));
- for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {
- /* Free preallocated skb's on RX rings */
- for (p_rx_curr_desc =
- ethernet_private->p_rx_desc_area_base[queue];
- (((unsigned int) p_rx_curr_desc <
- ((unsigned int) ethernet_private->
- p_rx_desc_area_base[queue] +
- ethernet_private->rx_desc_area_size[queue])));
- p_rx_curr_desc =
- (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
- RX_DESC_ALIGNED_SIZE)) {
- if (p_rx_curr_desc->return_info != 0) {
- p_rx_curr_desc->return_info = 0;
- DP (printf ("freed\n"));
- }
- }
- DP (printf ("Done\n"));
- }
- return 0;
-}
-
-/**********************************************************************
- * mv64460_eth_stop
- *
- * This function is used when closing the network device.
- * It updates the hardware,
- * release all memory that holds buffers and descriptors and release the IRQ.
- * Input : a pointer to the device structure
- * Output : zero if success , nonzero if fails
- *********************************************************************/
-
-int mv64460_eth_stop (struct eth_device *dev)
-{
- /* Disable all gigE address decoder */
- MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
- DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
- mv64460_eth_real_stop (dev);
-
- return 0;
-};
-
-/* Helper function for mv64460_eth_stop */
-
-static int mv64460_eth_real_stop (struct eth_device *dev)
-{
- ETH_PORT_INFO *ethernet_private;
- struct mv64460_eth_priv *port_private;
- unsigned int port_num;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64460_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
-
-
- mv64460_eth_free_tx_rings (dev);
- mv64460_eth_free_rx_rings (dev);
-
- eth_port_reset (ethernet_private->port_num);
- /* Disable ethernet port interrupts */
- MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
- MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
- /* Mask RX buffer and TX end interrupt */
- MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), 0);
- /* Mask phy and link status changes interrupts */
- MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
- MV_RESET_REG_BITS (MV64460_CPU_INTERRUPT0_MASK_HIGH,
- BIT0 << port_num);
- /* Print Network statistics */
-#ifndef UPDATE_STATS_BY_SOFTWARE
- /*
- * Print statistics (only if ethernet is running),
- * then zero all the stats fields in memory
- */
- if (port_private->eth_running == MAGIC_ETH_RUNNING) {
- port_private->eth_running = 0;
- mv64460_eth_print_stat (dev);
- }
- memset (port_private->stats, 0, sizeof (struct net_device_stats));
-#endif
- DP (printf ("\nEthernet stopped ... \n"));
- return 0;
-}
-
-
-/**********************************************************************
- * mv64460_eth_start_xmit
- *
- * This function is queues a packet in the Tx descriptor for
- * required port.
- *
- * Input : skb - a pointer to socket buffer
- * dev - a pointer to the required port
- *
- * Output : zero upon success
- **********************************************************************/
-
-int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
- int dataSize)
-{
- ETH_PORT_INFO *ethernet_private;
- struct mv64460_eth_priv *port_private;
- PKT_INFO pkt_info;
- ETH_FUNC_RET_STATUS status;
- struct net_device_stats *stats;
- ETH_FUNC_RET_STATUS release_result;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64460_eth_priv *) ethernet_private->port_private;
-
- stats = port_private->stats;
-
- /* Update packet info data structure */
- pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */
- pkt_info.byte_cnt = dataSize;
- pkt_info.buf_ptr = (unsigned int) dataPtr;
- pkt_info.return_info = 0;
-
- status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
- if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
- printf ("Error on transmitting packet ..");
- if (status == ETH_QUEUE_FULL)
- printf ("ETH Queue is full. \n");
- if (status == ETH_QUEUE_LAST_RESOURCE)
- printf ("ETH Queue: using last available resource. \n");
- goto error;
- }
-
- /* Update statistics and start of transmittion time */
- stats->tx_bytes += dataSize;
- stats->tx_packets++;
-
- /* Check if packet(s) is(are) transmitted correctly (release everything) */
- do {
- release_result =
- eth_tx_return_desc (ethernet_private, ETH_Q0,
- &pkt_info);
- switch (release_result) {
- case ETH_OK:
- DP (printf ("descriptor released\n"));
- if (pkt_info.cmd_sts & BIT0) {
- printf ("Error in TX\n");
- stats->tx_errors++;
-
- }
- break;
- case ETH_RETRY:
- DP (printf ("transmission still in process\n"));
- break;
-
- case ETH_ERROR:
- printf ("routine can not access Tx desc ring\n");
- break;
-
- case ETH_END_OF_JOB:
- DP (printf ("the routine has nothing to release\n"));
- break;
- default: /* should not happen */
- break;
- }
- } while (release_result == ETH_OK);
-
-
- return 0; /* success */
- error:
- return 1; /* Failed - higher layers will free the skb */
-}
-
-/**********************************************************************
- * mv64460_eth_receive
- *
- * This function is forward packets that are received from the port's
- * queues toward kernel core or FastRoute them to another interface.
- *
- * Input : dev - a pointer to the required interface
- * max - maximum number to receive (0 means unlimted)
- *
- * Output : number of served packets
- **********************************************************************/
-
-int mv64460_eth_receive (struct eth_device *dev)
-{
- ETH_PORT_INFO *ethernet_private;
- struct mv64460_eth_priv *port_private;
- PKT_INFO pkt_info;
- struct net_device_stats *stats;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64460_eth_priv *) ethernet_private->port_private;
- stats = port_private->stats;
-
- while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
- ETH_OK)) {
-
-#ifdef DEBUG_MV_ETH
- if (pkt_info.byte_cnt != 0) {
- printf ("%s: Received %d byte Packet @ 0x%x\n",
- __FUNCTION__, pkt_info.byte_cnt,
- pkt_info.buf_ptr);
- }
-#endif
- /* Update statistics. Note byte count includes 4 byte CRC count */
- stats->rx_packets++;
- stats->rx_bytes += pkt_info.byte_cnt;
-
- /*
- * In case received a packet without first / last bits on OR the error
- * summary bit is on, the packets needs to be dropeed.
- */
- if (((pkt_info.
- cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
- (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
- || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
- stats->rx_dropped++;
-
- printf ("Received packet spread on multiple descriptors\n");
-
- /* Is this caused by an error ? */
- if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
- stats->rx_errors++;
- }
-
- /* free these descriptors again without forwarding them to the higher layers */
- pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
- pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
-
- if (eth_rx_return_buff
- (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
- printf ("Error while returning the RX Desc to Ring\n");
- } else {
- DP (printf ("RX Desc returned to Ring\n"));
- }
- /* /free these descriptors again */
- } else {
-
-/* !!! call higher layer processing */
-#ifdef DEBUG_MV_ETH
- printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
-#endif
- /* let the upper layer handle the packet */
- NetReceive ((uchar *) pkt_info.buf_ptr,
- (int) pkt_info.byte_cnt);
-
-/* **************************************************************** */
-/* free descriptor */
- pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
- pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
- DP (printf
- ("RX: pkt_info.buf_ptr = %x\n",
- pkt_info.buf_ptr));
- if (eth_rx_return_buff
- (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
- printf ("Error while returning the RX Desc to Ring\n");
- } else {
- DP (printf ("RX Desc returned to Ring\n"));
- }
-
-/* **************************************************************** */
-
- }
- }
- mv64460_eth_get_stats (dev); /* update statistics */
- return 1;
-}
-
-/**********************************************************************
- * mv64460_eth_get_stats
- *
- * Returns a pointer to the interface statistics.
- *
- * Input : dev - a pointer to the required interface
- *
- * Output : a pointer to the interface's statistics
- **********************************************************************/
-
-static struct net_device_stats *mv64460_eth_get_stats (struct eth_device *dev)
-{
- ETH_PORT_INFO *ethernet_private;
- struct mv64460_eth_priv *port_private;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64460_eth_priv *) ethernet_private->port_private;
-
- mv64460_eth_update_stat (dev);
-
- return port_private->stats;
-}
-
-
-/**********************************************************************
- * mv64460_eth_update_stat
- *
- * Update the statistics structure in the private data structure
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- **********************************************************************/
-
-static void mv64460_eth_update_stat (struct eth_device *dev)
-{
- ETH_PORT_INFO *ethernet_private;
- struct mv64460_eth_priv *port_private;
- struct net_device_stats *stats;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64460_eth_priv *) ethernet_private->port_private;
- stats = port_private->stats;
-
- /* These are false updates */
- stats->rx_packets += (unsigned long)
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_GOOD_FRAMES_RECEIVED);
- stats->tx_packets += (unsigned long)
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_GOOD_FRAMES_SENT);
- stats->rx_bytes += (unsigned long)
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
- /*
- * Ideally this should be as follows -
- *
- * stats->rx_bytes += stats->rx_bytes +
- * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
- * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
- *
- * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
- * is just a dummy read for proper work of the GigE port
- */
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
- stats->tx_bytes += (unsigned long)
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_GOOD_OCTETS_SENT_LOW);
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_GOOD_OCTETS_SENT_HIGH);
- stats->rx_errors += (unsigned long)
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_MAC_RECEIVE_ERROR);
-
- /* Rx dropped is for received packet with CRC error */
- stats->rx_dropped +=
- (unsigned long) eth_read_mib_counter (ethernet_private->
- port_num,
- ETH_MIB_BAD_CRC_EVENT);
- stats->multicast += (unsigned long)
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_MULTICAST_FRAMES_RECEIVED);
- stats->collisions +=
- (unsigned long) eth_read_mib_counter (ethernet_private->
- port_num,
- ETH_MIB_COLLISION) +
- (unsigned long) eth_read_mib_counter (ethernet_private->
- port_num,
- ETH_MIB_LATE_COLLISION);
- /* detailed rx errors */
- stats->rx_length_errors +=
- (unsigned long) eth_read_mib_counter (ethernet_private->
- port_num,
- ETH_MIB_UNDERSIZE_RECEIVED)
- +
- (unsigned long) eth_read_mib_counter (ethernet_private->
- port_num,
- ETH_MIB_OVERSIZE_RECEIVED);
- /* detailed tx errors */
-}
-
-#ifndef UPDATE_STATS_BY_SOFTWARE
-/**********************************************************************
- * mv64460_eth_print_stat
- *
- * Update the statistics structure in the private data structure
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- **********************************************************************/
-
-static void mv64460_eth_print_stat (struct eth_device *dev)
-{
- ETH_PORT_INFO *ethernet_private;
- struct mv64460_eth_priv *port_private;
- struct net_device_stats *stats;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64460_eth_priv *) ethernet_private->port_private;
- stats = port_private->stats;
-
- /* These are false updates */
- printf ("\n### Network statistics: ###\n");
- printf ("--------------------------\n");
- printf (" Packets received: %ld\n", stats->rx_packets);
- printf (" Packets send: %ld\n", stats->tx_packets);
- printf (" Received bytes: %ld\n", stats->rx_bytes);
- printf (" Send bytes: %ld\n", stats->tx_bytes);
- if (stats->rx_errors != 0)
- printf (" Rx Errors: %ld\n",
- stats->rx_errors);
- if (stats->rx_dropped != 0)
- printf (" Rx dropped (CRC Errors): %ld\n",
- stats->rx_dropped);
- if (stats->multicast != 0)
- printf (" Rx mulicast frames: %ld\n",
- stats->multicast);
- if (stats->collisions != 0)
- printf (" No. of collisions: %ld\n",
- stats->collisions);
- if (stats->rx_length_errors != 0)
- printf (" Rx length errors: %ld\n",
- stats->rx_length_errors);
-}
-#endif
-
-/**************************************************************************
- *network_start - Network Kick Off Routine UBoot
- *Inputs :
- *Outputs :
- **************************************************************************/
-
-bool db64460_eth_start (struct eth_device *dev)
-{
- return (mv64460_eth_open (dev)); /* calls real open */
-}
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-* The second part is the low level driver of the gigE ethernet ports. *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-/*
- * based on Linux code
- * arch/powerpc/galileo/EVB64460/mv64460_eth.c - Driver for MV64460X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/********************************************************************************
- * Marvell's Gigabit Ethernet controller low level driver
- *
- * DESCRIPTION:
- * This file introduce low level API to Marvell's Gigabit Ethernet
- * controller. This Gigabit Ethernet Controller driver API controls
- * 1) Operations (i.e. port init, start, reset etc').
- * 2) Data flow (i.e. port send, receive etc').
- * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
- * struct.
- * This struct includes user configuration information as well as
- * driver internal data needed for its operations.
- *
- * Supported Features:
- * - This low level driver is OS independent. Allocating memory for
- * the descriptor rings and buffers are not within the scope of
- * this driver.
- * - The user is free from Rx/Tx queue managing.
- * - This low level driver introduce functionality API that enable
- * the to operate Marvell's Gigabit Ethernet Controller in a
- * convenient way.
- * - Simple Gigabit Ethernet port operation API.
- * - Simple Gigabit Ethernet port data flow API.
- * - Data flow and operation API support per queue functionality.
- * - Support cached descriptors for better performance.
- * - Enable access to all four DRAM banks and internal SRAM memory
- * spaces.
- * - PHY access and control API.
- * - Port control register configuration API.
- * - Full control over Unicast and Multicast MAC configurations.
- *
- * Operation flow:
- *
- * Initialization phase
- * This phase complete the initialization of the ETH_PORT_INFO
- * struct.
- * User information regarding port configuration has to be set
- * prior to calling the port initialization routine. For example,
- * the user has to assign the port_phy_addr field which is board
- * depended parameter.
- * In this phase any port Tx/Rx activity is halted, MIB counters
- * are cleared, PHY address is set according to user parameter and
- * access to DRAM and internal SRAM memory spaces.
- *
- * Driver ring initialization
- * Allocating memory for the descriptor rings and buffers is not
- * within the scope of this driver. Thus, the user is required to
- * allocate memory for the descriptors ring and buffers. Those
- * memory parameters are used by the Rx and Tx ring initialization
- * routines in order to curve the descriptor linked list in a form
- * of a ring.
- * Note: Pay special attention to alignment issues when using
- * cached descriptors/buffers. In this phase the driver store
- * information in the ETH_PORT_INFO struct regarding each queue
- * ring.
- *
- * Driver start
- * This phase prepares the Ethernet port for Rx and Tx activity.
- * It uses the information stored in the ETH_PORT_INFO struct to
- * initialize the various port registers.
- *
- * Data flow:
- * All packet references to/from the driver are done using PKT_INFO
- * struct.
- * This struct is a unified struct used with Rx and Tx operations.
- * This way the user is not required to be familiar with neither
- * Tx nor Rx descriptors structures.
- * The driver's descriptors rings are management by indexes.
- * Those indexes controls the ring resources and used to indicate
- * a SW resource error:
- * 'current'
- * This index points to the current available resource for use. For
- * example in Rx process this index will point to the descriptor
- * that will be passed to the user upon calling the receive routine.
- * In Tx process, this index will point to the descriptor
- * that will be assigned with the user packet info and transmitted.
- * 'used'
- * This index points to the descriptor that need to restore its
- * resources. For example in Rx process, using the Rx buffer return
- * API will attach the buffer returned in packet info to the
- * descriptor pointed by 'used'. In Tx process, using the Tx
- * descriptor return will merely return the user packet info with
- * the command status of the transmitted buffer pointed by the
- * 'used' index. Nevertheless, it is essential to use this routine
- * to update the 'used' index.
- * 'first'
- * This index supports Tx Scatter-Gather. It points to the first
- * descriptor of a packet assembled of multiple buffers. For example
- * when in middle of Such packet we have a Tx resource error the
- * 'curr' index get the value of 'first' to indicate that the ring
- * returned to its state before trying to transmit this packet.
- *
- * Receive operation:
- * The eth_port_receive API set the packet information struct,
- * passed by the caller, with received information from the
- * 'current' SDMA descriptor.
- * It is the user responsibility to return this resource back
- * to the Rx descriptor ring to enable the reuse of this source.
- * Return Rx resource is done using the eth_rx_return_buff API.
- *
- * Transmit operation:
- * The eth_port_send API supports Scatter-Gather which enables to
- * send a packet spanned over multiple buffers. This means that
- * for each packet info structure given by the user and put into
- * the Tx descriptors ring, will be transmitted only if the 'LAST'
- * bit will be set in the packet info command status field. This
- * API also consider restriction regarding buffer alignments and
- * sizes.
- * The user must return a Tx resource after ensuring the buffer
- * has been transmitted to enable the Tx ring indexes to update.
- *
- * BOARD LAYOUT
- * This device is on-board. No jumper diagram is necessary.
- *
- * EXTERNAL INTERFACE
- *
- * Prior to calling the initialization routine eth_port_init() the user
- * must set the following fields under ETH_PORT_INFO struct:
- * port_num User Ethernet port number.
- * port_phy_addr User PHY address of Ethernet port.
- * port_mac_addr[6] User defined port MAC address.
- * port_config User port configuration value.
- * port_config_extend User port config extend value.
- * port_sdma_config User port SDMA config value.
- * port_serial_control User port serial control value.
- * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr.
- * *port_private User scratch pad for user specific data structures.
- *
- * This driver introduce a set of default values:
- * PORT_CONFIG_VALUE Default port configuration value
- * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value
- * PORT_SDMA_CONFIG_VALUE Default sdma control value
- * PORT_SERIAL_CONTROL_VALUE Default port serial control value
- *
- * This driver data flow is done using the PKT_INFO struct which is
- * a unified struct for Rx and Tx operations:
- * byte_cnt Tx/Rx descriptor buffer byte count.
- * l4i_chk CPU provided TCP Checksum. For Tx operation only.
- * cmd_sts Tx/Rx descriptor command status.
- * buf_ptr Tx/Rx descriptor buffer pointer.
- * return_info Tx/Rx user resource return information.
- *
- *
- * EXTERNAL SUPPORT REQUIREMENTS
- *
- * This driver requires the following external support:
- *
- * D_CACHE_FLUSH_LINE (address, address offset)
- *
- * This macro applies assembly code to flush and invalidate cache
- * line.
- * address - address base.
- * address offset - address offset
- *
- *
- * CPU_PIPE_FLUSH
- *
- * This macro applies assembly code to flush the CPU pipeline.
- *
- *******************************************************************************/
-/* includes */
-
-/* defines */
-/* SDMA command macros */
-#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
- MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
-
-#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
- MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
- (1 << (8 + tx_queue)))
-
-#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
-MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
-
-#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
-MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
-
-#define CURR_RFD_GET(p_curr_desc, queue) \
- ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
-
-#define CURR_RFD_SET(p_curr_desc, queue) \
- (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
-
-#define USED_RFD_GET(p_used_desc, queue) \
- ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
-
-#define USED_RFD_SET(p_used_desc, queue)\
-(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
-
-
-#define CURR_TFD_GET(p_curr_desc, queue) \
- ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
-
-#define CURR_TFD_SET(p_curr_desc, queue) \
- (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
-
-#define USED_TFD_GET(p_used_desc, queue) \
- ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
-
-#define USED_TFD_SET(p_used_desc, queue) \
- (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
-
-#define FIRST_TFD_GET(p_first_desc, queue) \
- ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
-
-#define FIRST_TFD_SET(p_first_desc, queue) \
- (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
-
-
-/* Macros that save access to desc in order to find next desc pointer */
-#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
-
-#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
-
-#define LINK_UP_TIMEOUT 100000
-#define PHY_BUSY_TIMEOUT 10000000
-
-/* locals */
-
-/* PHY routines */
-static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
-static int ethernet_phy_get (ETH_PORT eth_port_num);
-
-/* Ethernet Port routines */
-static void eth_set_access_control (ETH_PORT eth_port_num,
- ETH_WIN_PARAM * param);
-static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
- ETH_QUEUE queue, int option);
-#if 0 /* FIXME */
-static bool eth_port_smc_addr (ETH_PORT eth_port_num,
- unsigned char mc_byte,
- ETH_QUEUE queue, int option);
-static bool eth_port_omc_addr (ETH_PORT eth_port_num,
- unsigned char crc8,
- ETH_QUEUE queue, int option);
-#endif
-
-static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
- int byte_count);
-
-void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
-
-
-typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
-u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
-{
- u32 result = 0;
- u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);
-
- if (enable & (1 << bank))
- return 0;
- if (bank == BANK0)
- result = MV_REG_READ (MV64460_CS_0_BASE_ADDR);
- if (bank == BANK1)
- result = MV_REG_READ (MV64460_CS_1_BASE_ADDR);
- if (bank == BANK2)
- result = MV_REG_READ (MV64460_CS_2_BASE_ADDR);
- if (bank == BANK3)
- result = MV_REG_READ (MV64460_CS_3_BASE_ADDR);
- result &= 0x0000ffff;
- result = result << 16;
- return result;
-}
-
-u32 mv_get_dram_bank_size (MEMORY_BANK bank)
-{
- u32 result = 0;
- u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);
-
- if (enable & (1 << bank))
- return 0;
- if (bank == BANK0)
- result = MV_REG_READ (MV64460_CS_0_SIZE);
- if (bank == BANK1)
- result = MV_REG_READ (MV64460_CS_1_SIZE);
- if (bank == BANK2)
- result = MV_REG_READ (MV64460_CS_2_SIZE);
- if (bank == BANK3)
- result = MV_REG_READ (MV64460_CS_3_SIZE);
- result += 1;
- result &= 0x0000ffff;
- result = result << 16;
- return result;
-}
-
-u32 mv_get_internal_sram_base (void)
-{
- u32 result;
-
- result = MV_REG_READ (MV64460_INTEGRATED_SRAM_BASE_ADDR);
- result &= 0x0000ffff;
- result = result << 16;
- return result;
-}
-
-/*******************************************************************************
-* eth_port_init - Initialize the Ethernet port driver
-*
-* DESCRIPTION:
-* This function prepares the ethernet port to start its activity:
-* 1) Completes the ethernet port driver struct initialization toward port
-* start routine.
-* 2) Resets the device to a quiescent state in case of warm reboot.
-* 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
-* 4) Clean MAC tables. The reset status of those tables is unknown.
-* 5) Set PHY address.
-* Note: Call this routine prior to eth_port_start routine and after setting
-* user values in the user fields of Ethernet port control struct (i.e.
-* port_phy_addr).
-*
-* INPUT:
-* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
-*
-* OUTPUT:
-* See description.
-*
-* RETURN:
-* None.
-*
-*******************************************************************************/
-static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
-{
- int queue;
- ETH_WIN_PARAM win_param;
-
- p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
- p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
- p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
- p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
-
- p_eth_port_ctrl->port_rx_queue_command = 0;
- p_eth_port_ctrl->port_tx_queue_command = 0;
-
- /* Zero out SW structs */
- for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
- CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
- USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
- p_eth_port_ctrl->rx_resource_err[queue] = false;
- }
-
- for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
- CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
- USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
- FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
- p_eth_port_ctrl->tx_resource_err[queue] = false;
- }
-
- eth_port_reset (p_eth_port_ctrl->port_num);
-
- /* Set access parameters for DRAM bank 0 */
- win_param.win = ETH_WIN0; /* Use Ethernet window 0 */
- win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
- win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
- win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
- win_param.high_addr = 0;
- /* Get bank base */
- win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
- win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */
- if (win_param.size == 0)
- win_param.enable = 0;
- else
- win_param.enable = 1; /* Enable the access */
- win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
-
- /* Set the access control for address window (EPAPR) READ & WRITE */
- eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
- /* Set access parameters for DRAM bank 1 */
- win_param.win = ETH_WIN1; /* Use Ethernet window 1 */
- win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
- win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
- win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
- win_param.high_addr = 0;
- /* Get bank base */
- win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
- win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */
- if (win_param.size == 0)
- win_param.enable = 0;
- else
- win_param.enable = 1; /* Enable the access */
- win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
-
- /* Set the access control for address window (EPAPR) READ & WRITE */
- eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
- /* Set access parameters for DRAM bank 2 */
- win_param.win = ETH_WIN2; /* Use Ethernet window 2 */
- win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
- win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
- win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
- win_param.high_addr = 0;
- /* Get bank base */
- win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
- win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */
- if (win_param.size == 0)
- win_param.enable = 0;
- else
- win_param.enable = 1; /* Enable the access */
- win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
-
- /* Set the access control for address window (EPAPR) READ & WRITE */
- eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
- /* Set access parameters for DRAM bank 3 */
- win_param.win = ETH_WIN3; /* Use Ethernet window 3 */
- win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
- win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
- win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
- win_param.high_addr = 0;
- /* Get bank base */
- win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
- win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */
- if (win_param.size == 0)
- win_param.enable = 0;
- else
- win_param.enable = 1; /* Enable the access */
- win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
-
- /* Set the access control for address window (EPAPR) READ & WRITE */
- eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
- /* Set access parameters for Internal SRAM */
- win_param.win = ETH_WIN4; /* Use Ethernet window 0 */
- win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */
- win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
- win_param.high_addr = 0;
- win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */
- win_param.size = MV64460_INTERNAL_SRAM_SIZE; /* Get bank size */
- win_param.enable = 1; /* Enable the access */
- win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
-
- /* Set the access control for address window (EPAPR) READ & WRITE */
- eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
- eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
-
- ethernet_phy_set (p_eth_port_ctrl->port_num,
- p_eth_port_ctrl->port_phy_addr);
-
- return;
-
-}
-
-/*******************************************************************************
-* eth_port_start - Start the Ethernet port activity.
-*
-* DESCRIPTION:
-* This routine prepares the Ethernet port for Rx and Tx activity:
-* 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
-* has been initialized a descriptor's ring (using ether_init_tx_desc_ring
-* for Tx and ether_init_rx_desc_ring for Rx)
-* 2. Initialize and enable the Ethernet configuration port by writing to
-* the port's configuration and command registers.
-* 3. Initialize and enable the SDMA by writing to the SDMA's
-* configuration and command registers.
-* After completing these steps, the ethernet port SDMA can starts to
-* perform Rx and Tx activities.
-*
-* Note: Each Rx and Tx queue descriptor's list must be initialized prior
-* to calling this function (use ether_init_tx_desc_ring for Tx queues and
-* ether_init_rx_desc_ring for Rx queues).
-*
-* INPUT:
-* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
-*
-* OUTPUT:
-* Ethernet port is ready to receive and transmit.
-*
-* RETURN:
-* false if the port PHY is not up.
-* true otherwise.
-*
-*******************************************************************************/
-static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
-{
- int queue;
- volatile ETH_TX_DESC *p_tx_curr_desc;
- volatile ETH_RX_DESC *p_rx_curr_desc;
- unsigned int phy_reg_data;
- ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
-
-
- /* Assignment of Tx CTRP of given queue */
- for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
- CURR_TFD_GET (p_tx_curr_desc, queue);
- MV_REG_WRITE ((MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
- (eth_port_num)
- + (4 * queue)),
- ((unsigned int) p_tx_curr_desc));
-
- }
-
- /* Assignment of Rx CRDP of given queue */
- for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
- CURR_RFD_GET (p_rx_curr_desc, queue);
- MV_REG_WRITE ((MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
- (eth_port_num)
- + (4 * queue)),
- ((unsigned int) p_rx_curr_desc));
-
- if (p_rx_curr_desc != NULL)
- /* Add the assigned Ethernet address to the port's address table */
- eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
- p_eth_port_ctrl->port_mac_addr,
- queue);
- }
-
- /* Assign port configuration and command. */
- MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),
- p_eth_port_ctrl->port_config);
-
- MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
- p_eth_port_ctrl->port_config_extend);
-
- MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
- p_eth_port_ctrl->port_serial_control);
-
- MV_SET_REG_BITS (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
- ETH_SERIAL_PORT_ENABLE);
-
- /* Assign port SDMA configuration */
- MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),
- p_eth_port_ctrl->port_sdma_config);
-
- MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
- (eth_port_num), 0x3fffffff);
- MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
- (eth_port_num), 0x03fffcff);
- /* Turn off the port/queue bandwidth limitation */
- MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
-
- /* Enable port Rx. */
- MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
- p_eth_port_ctrl->port_rx_queue_command);
-
- /* Check if link is up */
- eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
-
- if (!(phy_reg_data & 0x20))
- return false;
-
- return true;
-}
-
-/*******************************************************************************
-* eth_port_uc_addr_set - This function Set the port Unicast address.
-*
-* DESCRIPTION:
-* This function Set the port Ethernet MAC address.
-*
-* INPUT:
-* ETH_PORT eth_port_num Port number.
-* char * p_addr Address to be set
-* ETH_QUEUE queue Rx queue number for this MAC address.
-*
-* OUTPUT:
-* Set MAC address low and high registers. also calls eth_port_uc_addr()
-* To set the unicast table with the proper information.
-*
-* RETURN:
-* N/A.
-*
-*******************************************************************************/
-static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
- unsigned char *p_addr, ETH_QUEUE queue)
-{
- unsigned int mac_h;
- unsigned int mac_l;
-
- mac_l = (p_addr[4] << 8) | (p_addr[5]);
- mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
- (p_addr[2] << 8) | (p_addr[3] << 0);
-
- MV_REG_WRITE (MV64460_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
- MV_REG_WRITE (MV64460_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
-
- /* Accept frames of this address */
- eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
-
- return;
-}
-
-/*******************************************************************************
-* eth_port_uc_addr - This function Set the port unicast address table
-*
-* DESCRIPTION:
-* This function locates the proper entry in the Unicast table for the
-* specified MAC nibble and sets its properties according to function
-* parameters.
-*
-* INPUT:
-* ETH_PORT eth_port_num Port number.
-* unsigned char uc_nibble Unicast MAC Address last nibble.
-* ETH_QUEUE queue Rx queue number for this MAC address.
-* int option 0 = Add, 1 = remove address.
-*
-* OUTPUT:
-* This function add/removes MAC addresses from the port unicast address
-* table.
-*
-* RETURN:
-* true is output succeeded.
-* false if option parameter is invalid.
-*
-*******************************************************************************/
-static bool eth_port_uc_addr (ETH_PORT eth_port_num,
- unsigned char uc_nibble,
- ETH_QUEUE queue, int option)
-{
- unsigned int unicast_reg;
- unsigned int tbl_offset;
- unsigned int reg_offset;
-
- /* Locate the Unicast table entry */
- uc_nibble = (0xf & uc_nibble);
- tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
- reg_offset = uc_nibble % 4; /* Entry offset within the above register */
-
- switch (option) {
- case REJECT_MAC_ADDR:
- /* Clear accepts frame bit at specified unicast DA table entry */
- unicast_reg =
- MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
- (eth_port_num)
- + tbl_offset));
-
- unicast_reg &= (0x0E << (8 * reg_offset));
-
- MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
- (eth_port_num)
- + tbl_offset), unicast_reg);
- break;
-
- case ACCEPT_MAC_ADDR:
- /* Set accepts frame bit at unicast DA filter table entry */
- unicast_reg =
- MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
- (eth_port_num)
- + tbl_offset));
-
- unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
-
- MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
- (eth_port_num)
- + tbl_offset), unicast_reg);
-
- break;
-
- default:
- return false;
- }
- return true;
-}
-
-#if 0 /* FIXME */
-/*******************************************************************************
-* eth_port_mc_addr - Multicast address settings.
-*
-* DESCRIPTION:
-* This API controls the MV device MAC multicast support.
-* The MV device supports multicast using two tables:
-* 1) Special Multicast Table for MAC addresses of the form
-* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
-* The MAC DA[7:0] bits are used as a pointer to the Special Multicast
-* Table entries in the DA-Filter table.
-* In this case, the function calls eth_port_smc_addr() routine to set the
-* Special Multicast Table.
-* 2) Other Multicast Table for multicast of another type. A CRC-8bit
-* is used as an index to the Other Multicast Table entries in the
-* DA-Filter table.
-* In this case, the function calculates the CRC-8bit value and calls
-* eth_port_omc_addr() routine to set the Other Multicast Table.
-* INPUT:
-* ETH_PORT eth_port_num Port number.
-* unsigned char *p_addr Unicast MAC Address.
-* ETH_QUEUE queue Rx queue number for this MAC address.
-* int option 0 = Add, 1 = remove address.
-*
-* OUTPUT:
-* See description.
-*
-* RETURN:
-* true is output succeeded.
-* false if add_address_table_entry( ) failed.
-*
-*******************************************************************************/
-static void eth_port_mc_addr (ETH_PORT eth_port_num,
- unsigned char *p_addr,
- ETH_QUEUE queue, int option)
-{
- unsigned int mac_h;
- unsigned int mac_l;
- unsigned char crc_result = 0;
- int mac_array[48];
- int crc[8];
- int i;
-
-
- if ((p_addr[0] == 0x01) &&
- (p_addr[1] == 0x00) &&
- (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00))
-
- eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
- else {
- /* Calculate CRC-8 out of the given address */
- mac_h = (p_addr[0] << 8) | (p_addr[1]);
- mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
- (p_addr[4] << 8) | (p_addr[5] << 0);
-
- for (i = 0; i < 32; i++)
- mac_array[i] = (mac_l >> i) & 0x1;
- for (i = 32; i < 48; i++)
- mac_array[i] = (mac_h >> (i - 32)) & 0x1;
-
-
- crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
- mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
- mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
- mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
- mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
- mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
- mac_array[6] ^ mac_array[0];
-
- crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
- mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
- mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
- mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
- mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
- mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
- mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
- mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
- mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
- mac_array[0];
-
- crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
- mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
- mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
- mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
- mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
- mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
- mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
- mac_array[2] ^ mac_array[1] ^ mac_array[0];
-
- crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
- mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
- mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
- mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
- mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
- mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
- mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
- mac_array[2] ^ mac_array[1];
-
- crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
- mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
- mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
- mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
- mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
- mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
- mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
- mac_array[2];
-
- crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
- mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
- mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
- mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
- mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
- mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
- mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
- mac_array[3];
-
- crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
- mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
- mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
- mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
- mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
- mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
- mac_array[6] ^ mac_array[5] ^ mac_array[4];
-
- crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
- mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
- mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
- mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
- mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
- mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
- mac_array[6] ^ mac_array[5];
-
- for (i = 0; i < 8; i++)
- crc_result = crc_result | (crc[i] << i);
-
- eth_port_omc_addr (eth_port_num, crc_result, queue, option);
- }
- return;
-}
-
-/*******************************************************************************
-* eth_port_smc_addr - Special Multicast address settings.
-*
-* DESCRIPTION:
-* This routine controls the MV device special MAC multicast support.
-* The Special Multicast Table for MAC addresses supports MAC of the form
-* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
-* The MAC DA[7:0] bits are used as a pointer to the Special Multicast
-* Table entries in the DA-Filter table.
-* This function set the Special Multicast Table appropriate entry
-* according to the argument given.
-*
-* INPUT:
-* ETH_PORT eth_port_num Port number.
-* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits).
-* ETH_QUEUE queue Rx queue number for this MAC address.
-* int option 0 = Add, 1 = remove address.
-*
-* OUTPUT:
-* See description.
-*
-* RETURN:
-* true is output succeeded.
-* false if option parameter is invalid.
-*
-*******************************************************************************/
-static bool eth_port_smc_addr (ETH_PORT eth_port_num,
- unsigned char mc_byte,
- ETH_QUEUE queue, int option)
-{
- unsigned int smc_table_reg;
- unsigned int tbl_offset;
- unsigned int reg_offset;
-
- /* Locate the SMC table entry */
- tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */
- reg_offset = mc_byte % 4; /* Entry offset within the above register */
- queue &= 0x7;
-
- switch (option) {
- case REJECT_MAC_ADDR:
- /* Clear accepts frame bit at specified Special DA table entry */
- smc_table_reg =
- MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
- smc_table_reg &= (0x0E << (8 * reg_offset));
-
- MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
- break;
-
- case ACCEPT_MAC_ADDR:
- /* Set accepts frame bit at specified Special DA table entry */
- smc_table_reg =
- MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
- smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
-
- MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
- break;
-
- default:
- return false;
- }
- return true;
-}
-
-/*******************************************************************************
-* eth_port_omc_addr - Multicast address settings.
-*
-* DESCRIPTION:
-* This routine controls the MV device Other MAC multicast support.
-* The Other Multicast Table is used for multicast of another type.
-* A CRC-8bit is used as an index to the Other Multicast Table entries
-* in the DA-Filter table.
-* The function gets the CRC-8bit value from the calling routine and
-* set the Other Multicast Table appropriate entry according to the
-* CRC-8 argument given.
-*
-* INPUT:
-* ETH_PORT eth_port_num Port number.
-* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
-* ETH_QUEUE queue Rx queue number for this MAC address.
-* int option 0 = Add, 1 = remove address.
-*
-* OUTPUT:
-* See description.
-*
-* RETURN:
-* true is output succeeded.
-* false if option parameter is invalid.
-*
-*******************************************************************************/
-static bool eth_port_omc_addr (ETH_PORT eth_port_num,
- unsigned char crc8,
- ETH_QUEUE queue, int option)
-{
- unsigned int omc_table_reg;
- unsigned int tbl_offset;
- unsigned int reg_offset;
-
- /* Locate the OMC table entry */
- tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
- reg_offset = crc8 % 4; /* Entry offset within the above register */
- queue &= 0x7;
-
- switch (option) {
- case REJECT_MAC_ADDR:
- /* Clear accepts frame bit at specified Other DA table entry */
- omc_table_reg =
- MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
- omc_table_reg &= (0x0E << (8 * reg_offset));
-
- MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
- break;
-
- case ACCEPT_MAC_ADDR:
- /* Set accepts frame bit at specified Other DA table entry */
- omc_table_reg =
- MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
- omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
-
- MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
- break;
-
- default:
- return false;
- }
- return true;
-}
-#endif
-
-/*******************************************************************************
-* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
-*
-* DESCRIPTION:
-* Go through all the DA filter tables (Unicast, Special Multicast & Other
-* Multicast) and set each entry to 0.
-*
-* INPUT:
-* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
-*
-* OUTPUT:
-* Multicast and Unicast packets are rejected.
-*
-* RETURN:
-* None.
-*
-*******************************************************************************/
-static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
-{
- int table_index;
-
- /* Clear DA filter unicast table (Ex_dFUT) */
- for (table_index = 0; table_index <= 0xC; table_index += 4)
- MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
- (eth_port_num) + table_index), 0);
-
- for (table_index = 0; table_index <= 0xFC; table_index += 4) {
- /* Clear DA filter special multicast table (Ex_dFSMT) */
- MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
- /* Clear DA filter other multicast table (Ex_dFOMT) */
- MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
- }
-}
-
-/*******************************************************************************
-* eth_clear_mib_counters - Clear all MIB counters
-*
-* DESCRIPTION:
-* This function clears all MIB counters of a specific ethernet port.
-* A read from the MIB counter will reset the counter.
-*
-* INPUT:
-* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
-*
-* OUTPUT:
-* After reading all MIB counters, the counters resets.
-*
-* RETURN:
-* MIB counter value.
-*
-*******************************************************************************/
-static void eth_clear_mib_counters (ETH_PORT eth_port_num)
-{
- int i;
-
- /* Perform dummy reads from MIB counters */
- for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
- i += 4)
- MV_REG_READ((MV64460_ETH_MIB_COUNTERS_BASE(eth_port_num) + i));
-
- return;
-}
-
-/*******************************************************************************
-* eth_read_mib_counter - Read a MIB counter
-*
-* DESCRIPTION:
-* This function reads a MIB counter of a specific ethernet port.
-* NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
-* following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
-* register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
-* ETH_MIB_GOOD_OCTETS_SENT_HIGH
-*
-* INPUT:
-* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
-* unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros).
-*
-* OUTPUT:
-* After reading the MIB counter, the counter resets.
-*
-* RETURN:
-* MIB counter value.
-*
-*******************************************************************************/
-unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
- unsigned int mib_offset)
-{
- return (MV_REG_READ (MV64460_ETH_MIB_COUNTERS_BASE (eth_port_num)
- + mib_offset));
-}
-
-/*******************************************************************************
-* ethernet_phy_set - Set the ethernet port PHY address.
-*
-* DESCRIPTION:
-* This routine set the ethernet port PHY address according to given
-* parameter.
-*
-* INPUT:
-* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
-*
-* OUTPUT:
-* Set PHY Address Register with given PHY address parameter.
-*
-* RETURN:
-* None.
-*
-*******************************************************************************/
-static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
-{
- unsigned int reg_data;
-
- reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);
-
- reg_data &= ~(0x1F << (5 * eth_port_num));
- reg_data |= (phy_addr << (5 * eth_port_num));
-
- MV_REG_WRITE (MV64460_ETH_PHY_ADDR_REG, reg_data);
-
- return;
-}
-
-/*******************************************************************************
- * ethernet_phy_get - Get the ethernet port PHY address.
- *
- * DESCRIPTION:
- * This routine returns the given ethernet port PHY address.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- * None.
- *
- * RETURN:
- * PHY address.
- *
- *******************************************************************************/
-static int ethernet_phy_get (ETH_PORT eth_port_num)
-{
- unsigned int reg_data;
-
- reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);
-
- return ((reg_data >> (5 * eth_port_num)) & 0x1f);
-}
-
-/*******************************************************************************
- * ethernet_phy_reset - Reset Ethernet port PHY.
- *
- * DESCRIPTION:
- * This routine utilize the SMI interface to reset the ethernet port PHY.
- * The routine waits until the link is up again or link up is timeout.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- * The ethernet port PHY renew its link.
- *
- * RETURN:
- * None.
- *
-*******************************************************************************/
-static bool ethernet_phy_reset (ETH_PORT eth_port_num)
-{
- unsigned int time_out = 50;
- unsigned int phy_reg_data;
-
- /* Reset the PHY */
- eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
- phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
- eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
-
- /* Poll on the PHY LINK */
- do {
- eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
-
- if (time_out-- == 0)
- return false;
- }
- while (!(phy_reg_data & 0x20));
-
- return true;
-}
-
-/*******************************************************************************
- * eth_port_reset - Reset Ethernet port
- *
- * DESCRIPTION:
- * This routine resets the chip by aborting any SDMA engine activity and
- * clearing the MIB counters. The Receiver and the Transmit unit are in
- * idle state after this command is performed and the port is disabled.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- * Channel activity is halted.
- *
- * RETURN:
- * None.
- *
- *******************************************************************************/
-static void eth_port_reset (ETH_PORT eth_port_num)
-{
- unsigned int reg_data;
-
- /* Stop Tx port activity. Check port Tx activity. */
- reg_data =
- MV_REG_READ (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
- (eth_port_num));
-
- if (reg_data & 0xFF) {
- /* Issue stop command for active channels only */
- MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
- (eth_port_num), (reg_data << 8));
-
- /* Wait for all Tx activity to terminate. */
- do {
- /* Check port cause register that all Tx queues are stopped */
- reg_data =
- MV_REG_READ
- (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
- (eth_port_num));
- }
- while (reg_data & 0xFF);
- }
-
- /* Stop Rx port activity. Check port Rx activity. */
- reg_data =
- MV_REG_READ (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
- (eth_port_num));
-
- if (reg_data & 0xFF) {
- /* Issue stop command for active channels only */
- MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
- (eth_port_num), (reg_data << 8));
-
- /* Wait for all Rx activity to terminate. */
- do {
- /* Check port cause register that all Rx queues are stopped */
- reg_data =
- MV_REG_READ
- (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
- (eth_port_num));
- }
- while (reg_data & 0xFF);
- }
-
-
- /* Clear all MIB counters */
- eth_clear_mib_counters (eth_port_num);
-
- /* Reset the Enable bit in the Configuration Register */
- reg_data =
- MV_REG_READ (MV64460_ETH_PORT_SERIAL_CONTROL_REG
- (eth_port_num));
- reg_data &= ~ETH_SERIAL_PORT_ENABLE;
- MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
- reg_data);
-
- return;
-}
-
-#if 0 /* Not needed here */
-/*******************************************************************************
- * ethernet_set_config_reg - Set specified bits in configuration register.
- *
- * DESCRIPTION:
- * This function sets specified bits in the given ethernet
- * configuration register.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- * unsigned int value 32 bit value.
- *
- * OUTPUT:
- * The set bits in the value parameter are set in the configuration
- * register.
- *
- * RETURN:
- * None.
- *
- *******************************************************************************/
-static void ethernet_set_config_reg (ETH_PORT eth_port_num,
- unsigned int value)
-{
- unsigned int eth_config_reg;
-
- eth_config_reg =
- MV_REG_READ (MV64460_ETH_PORT_CONFIG_REG (eth_port_num));
- eth_config_reg |= value;
- MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),
- eth_config_reg);
-
- return;
-}
-#endif
-
-#if 0 /* FIXME */
-/*******************************************************************************
- * ethernet_reset_config_reg - Reset specified bits in configuration register.
- *
- * DESCRIPTION:
- * This function resets specified bits in the given Ethernet
- * configuration register.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- * unsigned int value 32 bit value.
- *
- * OUTPUT:
- * The set bits in the value parameter are reset in the configuration
- * register.
- *
- * RETURN:
- * None.
- *
- *******************************************************************************/
-static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
- unsigned int value)
-{
- unsigned int eth_config_reg;
-
- eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG
- (eth_port_num));
- eth_config_reg &= ~value;
- MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
- eth_config_reg);
-
- return;
-}
-#endif
-
-#if 0 /* Not needed here */
-/*******************************************************************************
- * ethernet_get_config_reg - Get the port configuration register
- *
- * DESCRIPTION:
- * This function returns the configuration register value of the given
- * ethernet port.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- * None.
- *
- * RETURN:
- * Port configuration register value.
- *
- *******************************************************************************/
-static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
-{
- unsigned int eth_config_reg;
-
- eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG
- (eth_port_num));
- return eth_config_reg;
-}
-
-#endif
-
-/*******************************************************************************
- * eth_port_read_smi_reg - Read PHY registers
- *
- * DESCRIPTION:
- * This routine utilize the SMI interface to interact with the PHY in
- * order to perform PHY register read.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- * unsigned int phy_reg PHY register address offset.
- * unsigned int *value Register value buffer.
- *
- * OUTPUT:
- * Write the value of a specified PHY register into given buffer.
- *
- * RETURN:
- * false if the PHY is busy or read data is not in valid state.
- * true otherwise.
- *
- *******************************************************************************/
-static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
- unsigned int phy_reg, unsigned int *value)
-{
- unsigned int reg_value;
- unsigned int time_out = PHY_BUSY_TIMEOUT;
- int phy_addr;
-
- phy_addr = ethernet_phy_get (eth_port_num);
-/* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/
-
- /* first check that it is not busy */
- do {
- reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
- if (time_out-- == 0) {
- return false;
- }
- }
- while (reg_value & ETH_SMI_BUSY);
-
- /* not busy */
-
- MV_REG_WRITE (MV64460_ETH_SMI_REG,
- (phy_addr << 16) | (phy_reg << 21) |
- ETH_SMI_OPCODE_READ);
-
- time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */
-
- do {
- reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
- if (time_out-- == 0) {
- return false;
- }
- }
- while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */
-
- /* Wait for the data to update in the SMI register */
-#define PHY_UPDATE_TIMEOUT 10000
- for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
-
- reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
-
- *value = reg_value & 0xffff;
-
- return true;
-}
-
-/*******************************************************************************
- * eth_port_write_smi_reg - Write to PHY registers
- *
- * DESCRIPTION:
- * This routine utilize the SMI interface to interact with the PHY in
- * order to perform writes to PHY registers.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- * unsigned int phy_reg PHY register address offset.
- * unsigned int value Register value.
- *
- * OUTPUT:
- * Write the given value to the specified PHY register.
- *
- * RETURN:
- * false if the PHY is busy.
- * true otherwise.
- *
- *******************************************************************************/
-static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
- unsigned int phy_reg, unsigned int value)
-{
- unsigned int reg_value;
- unsigned int time_out = PHY_BUSY_TIMEOUT;
- int phy_addr;
-
- phy_addr = ethernet_phy_get (eth_port_num);
-
- /* first check that it is not busy */
- do {
- reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
- if (time_out-- == 0) {
- return false;
- }
- }
- while (reg_value & ETH_SMI_BUSY);
-
- /* not busy */
- MV_REG_WRITE (MV64460_ETH_SMI_REG,
- (phy_addr << 16) | (phy_reg << 21) |
- ETH_SMI_OPCODE_WRITE | (value & 0xffff));
- return true;
-}
-
-/*******************************************************************************
- * eth_set_access_control - Config address decode parameters for Ethernet unit
- *
- * DESCRIPTION:
- * This function configures the address decode parameters for the Gigabit
- * Ethernet Controller according the given parameters struct.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- * ETH_WIN_PARAM *param Address decode parameter struct.
- *
- * OUTPUT:
- * An access window is opened using the given access parameters.
- *
- * RETURN:
- * None.
- *
- *******************************************************************************/
-static void eth_set_access_control (ETH_PORT eth_port_num,
- ETH_WIN_PARAM * param)
-{
- unsigned int access_prot_reg;
-
- /* Set access control register */
- access_prot_reg = MV_REG_READ (MV64460_ETH_ACCESS_PROTECTION_REG
- (eth_port_num));
- access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */
- access_prot_reg |= (param->access_ctrl << (param->win * 2));
- MV_REG_WRITE (MV64460_ETH_ACCESS_PROTECTION_REG (eth_port_num),
- access_prot_reg);
-
- /* Set window Size reg (SR) */
- MV_REG_WRITE ((MV64460_ETH_SIZE_REG_0 +
- (ETH_SIZE_REG_GAP * param->win)),
- (((param->size / 0x10000) - 1) << 16));
-
- /* Set window Base address reg (BA) */
- MV_REG_WRITE ((MV64460_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
- (param->target | param->attributes | param->base_addr));
- /* High address remap reg (HARR) */
- if (param->win < 4)
- MV_REG_WRITE ((MV64460_ETH_HIGH_ADDR_REMAP_REG_0 +
- (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
- param->high_addr);
-
- /* Base address enable reg (BARER) */
- if (param->enable == 1)
- MV_RESET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,
- (1 << param->win));
- else
- MV_SET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,
- (1 << param->win));
-}
-
-/*******************************************************************************
- * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
- *
- * DESCRIPTION:
- * This function prepares a Rx chained list of descriptors and packet
- * buffers in a form of a ring. The routine must be called after port
- * initialization routine and before port start routine.
- * The Ethernet SDMA engine uses CPU bus addresses to access the various
- * devices in the system (i.e. DRAM). This function uses the ethernet
- * struct 'virtual to physical' routine (set by the user) to set the ring
- * with physical addresses.
- *
- * INPUT:
- * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
- * ETH_QUEUE rx_queue Number of Rx queue.
- * int rx_desc_num Number of Rx descriptors
- * int rx_buff_size Size of Rx buffer
- * unsigned int rx_desc_base_addr Rx descriptors memory area base addr.
- * unsigned int rx_buff_base_addr Rx buffer memory area base addr.
- *
- * OUTPUT:
- * The routine updates the Ethernet port control struct with information
- * regarding the Rx descriptors and buffers.
- *
- * RETURN:
- * false if the given descriptors memory area is not aligned according to
- * Ethernet SDMA specifications.
- * true otherwise.
- *
- *******************************************************************************/
-static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
- ETH_QUEUE rx_queue,
- int rx_desc_num,
- int rx_buff_size,
- unsigned int rx_desc_base_addr,
- unsigned int rx_buff_base_addr)
-{
- ETH_RX_DESC *p_rx_desc;
- ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */
- unsigned int buffer_addr;
- int ix; /* a counter */
-
-
- p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
- p_rx_prev_desc = p_rx_desc;
- buffer_addr = rx_buff_base_addr;
-
- /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
- if (rx_buff_base_addr & 0xF)
- return false;
-
- /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */
- if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
- return false;
-
- /* Rx buffers must be 64-bit aligned. */
- if ((rx_buff_base_addr + rx_buff_size) & 0x7)
- return false;
-
- /* initialize the Rx descriptors ring */
- for (ix = 0; ix < rx_desc_num; ix++) {
- p_rx_desc->buf_size = rx_buff_size;
- p_rx_desc->byte_cnt = 0x0000;
- p_rx_desc->cmd_sts =
- ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
- p_rx_desc->next_desc_ptr =
- ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
- p_rx_desc->buf_ptr = buffer_addr;
- p_rx_desc->return_info = 0x00000000;
- D_CACHE_FLUSH_LINE (p_rx_desc, 0);
- buffer_addr += rx_buff_size;
- p_rx_prev_desc = p_rx_desc;
- p_rx_desc = (ETH_RX_DESC *)
- ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
- }
-
- /* Closing Rx descriptors ring */
- p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
- D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
-
- /* Save Rx desc pointer to driver struct. */
- CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
- USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
-
- p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
- (ETH_RX_DESC *) rx_desc_base_addr;
- p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
- rx_desc_num * RX_DESC_ALIGNED_SIZE;
-
- p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
-
- return true;
-}
-
-/*******************************************************************************
- * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
- *
- * DESCRIPTION:
- * This function prepares a Tx chained list of descriptors and packet
- * buffers in a form of a ring. The routine must be called after port
- * initialization routine and before port start routine.
- * The Ethernet SDMA engine uses CPU bus addresses to access the various
- * devices in the system (i.e. DRAM). This function uses the ethernet
- * struct 'virtual to physical' routine (set by the user) to set the ring
- * with physical addresses.
- *
- * INPUT:
- * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
- * ETH_QUEUE tx_queue Number of Tx queue.
- * int tx_desc_num Number of Tx descriptors
- * int tx_buff_size Size of Tx buffer
- * unsigned int tx_desc_base_addr Tx descriptors memory area base addr.
- * unsigned int tx_buff_base_addr Tx buffer memory area base addr.
- *
- * OUTPUT:
- * The routine updates the Ethernet port control struct with information
- * regarding the Tx descriptors and buffers.
- *
- * RETURN:
- * false if the given descriptors memory area is not aligned according to
- * Ethernet SDMA specifications.
- * true otherwise.
- *
- *******************************************************************************/
-static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
- ETH_QUEUE tx_queue,
- int tx_desc_num,
- int tx_buff_size,
- unsigned int tx_desc_base_addr,
- unsigned int tx_buff_base_addr)
-{
-
- ETH_TX_DESC *p_tx_desc;
- ETH_TX_DESC *p_tx_prev_desc;
- unsigned int buffer_addr;
- int ix; /* a counter */
-
-
- /* save the first desc pointer to link with the last descriptor */
- p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
- p_tx_prev_desc = p_tx_desc;
- buffer_addr = tx_buff_base_addr;
-
- /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
- if (tx_buff_base_addr & 0xF)
- return false;
-
- /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */
- if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
- || (tx_buff_size < TX_BUFFER_MIN_SIZE))
- return false;
-
- /* Initialize the Tx descriptors ring */
- for (ix = 0; ix < tx_desc_num; ix++) {
- p_tx_desc->byte_cnt = 0x0000;
- p_tx_desc->l4i_chk = 0x0000;
- p_tx_desc->cmd_sts = 0x00000000;
- p_tx_desc->next_desc_ptr =
- ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
-
- p_tx_desc->buf_ptr = buffer_addr;
- p_tx_desc->return_info = 0x00000000;
- D_CACHE_FLUSH_LINE (p_tx_desc, 0);
- buffer_addr += tx_buff_size;
- p_tx_prev_desc = p_tx_desc;
- p_tx_desc = (ETH_TX_DESC *)
- ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
-
- }
- /* Closing Tx descriptors ring */
- p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
- D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
- /* Set Tx desc pointer in driver struct. */
- CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
- USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
-
- /* Init Tx ring base and size parameters */
- p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
- (ETH_TX_DESC *) tx_desc_base_addr;
- p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
- (tx_desc_num * TX_DESC_ALIGNED_SIZE);
-
- /* Add the queue to the list of Tx queues of this port */
- p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
-
- return true;
-}
-
-/*******************************************************************************
- * eth_port_send - Send an Ethernet packet
- *
- * DESCRIPTION:
- * This routine send a given packet described by p_pktinfo parameter. It
- * supports transmitting of a packet spaned over multiple buffers. The
- * routine updates 'curr' and 'first' indexes according to the packet
- * segment passed to the routine. In case the packet segment is first,
- * the 'first' index is update. In any case, the 'curr' index is updated.
- * If the routine get into Tx resource error it assigns 'curr' index as
- * 'first'. This way the function can abort Tx process of multiple
- * descriptors per packet.
- *
- * INPUT:
- * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
- * ETH_QUEUE tx_queue Number of Tx queue.
- * PKT_INFO *p_pkt_info User packet buffer.
- *
- * OUTPUT:
- * Tx ring 'curr' and 'first' indexes are updated.
- *
- * RETURN:
- * ETH_QUEUE_FULL in case of Tx resource error.
- * ETH_ERROR in case the routine can not access Tx desc ring.
- * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
- * ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
- ETH_QUEUE tx_queue,
- PKT_INFO * p_pkt_info)
-{
- volatile ETH_TX_DESC *p_tx_desc_first;
- volatile ETH_TX_DESC *p_tx_desc_curr;
- volatile ETH_TX_DESC *p_tx_next_desc_curr;
- volatile ETH_TX_DESC *p_tx_desc_used;
- unsigned int command_status;
-
- /* Do not process Tx ring in case of Tx ring resource error */
- if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
- return ETH_QUEUE_FULL;
-
- /* Get the Tx Desc ring indexes */
- CURR_TFD_GET (p_tx_desc_curr, tx_queue);
- USED_TFD_GET (p_tx_desc_used, tx_queue);
-
- if (p_tx_desc_curr == NULL)
- return ETH_ERROR;
-
- /* The following parameters are used to save readings from memory */
- p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
- command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
-
- if (command_status & (ETH_TX_FIRST_DESC)) {
- /* Update first desc */
- FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
- p_tx_desc_first = p_tx_desc_curr;
- } else {
- FIRST_TFD_GET (p_tx_desc_first, tx_queue);
- command_status |= ETH_BUFFER_OWNED_BY_DMA;
- }
-
- /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
- /* boundary. We use the memory allocated for Tx descriptor. This memory */
- /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
- if (p_pkt_info->byte_cnt <= 8) {
- printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */
- return ETH_ERROR;
-
- p_tx_desc_curr->buf_ptr =
- (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
- eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
- p_pkt_info->byte_cnt);
- } else
- p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
-
- p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
- p_tx_desc_curr->return_info = p_pkt_info->return_info;
-
- if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
- /* Set last desc with DMA ownership and interrupt enable. */
- p_tx_desc_curr->cmd_sts = command_status |
- ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
-
- if (p_tx_desc_curr != p_tx_desc_first)
- p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
-
- /* Flush CPU pipe */
-
- D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
- D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
- CPU_PIPE_FLUSH;
-
- /* Apply send command */
- ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
-
- /* Finish Tx packet. Update first desc in case of Tx resource error */
- p_tx_desc_first = p_tx_next_desc_curr;
- FIRST_TFD_SET (p_tx_desc_first, tx_queue);
-
- } else {
- p_tx_desc_curr->cmd_sts = command_status;
- D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
- }
-
- /* Check for ring index overlap in the Tx desc ring */
- if (p_tx_next_desc_curr == p_tx_desc_used) {
- /* Update the current descriptor */
- CURR_TFD_SET (p_tx_desc_first, tx_queue);
-
- p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
- return ETH_QUEUE_LAST_RESOURCE;
- } else {
- /* Update the current descriptor */
- CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
- return ETH_OK;
- }
-}
-
-/*******************************************************************************
- * eth_tx_return_desc - Free all used Tx descriptors
- *
- * DESCRIPTION:
- * This routine returns the transmitted packet information to the caller.
- * It uses the 'first' index to support Tx desc return in case a transmit
- * of a packet spanned over multiple buffer still in process.
- * In case the Tx queue was in "resource error" condition, where there are
- * no available Tx resources, the function resets the resource error flag.
- *
- * INPUT:
- * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
- * ETH_QUEUE tx_queue Number of Tx queue.
- * PKT_INFO *p_pkt_info User packet buffer.
- *
- * OUTPUT:
- * Tx ring 'first' and 'used' indexes are updated.
- *
- * RETURN:
- * ETH_ERROR in case the routine can not access Tx desc ring.
- * ETH_RETRY in case there is transmission in process.
- * ETH_END_OF_JOB if the routine has nothing to release.
- * ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
- p_eth_port_ctrl,
- ETH_QUEUE tx_queue,
- PKT_INFO * p_pkt_info)
-{
- volatile ETH_TX_DESC *p_tx_desc_used = NULL;
- volatile ETH_TX_DESC *p_tx_desc_first = NULL;
- unsigned int command_status;
-
-
- /* Get the Tx Desc ring indexes */
- USED_TFD_GET (p_tx_desc_used, tx_queue);
- FIRST_TFD_GET (p_tx_desc_first, tx_queue);
-
-
- /* Sanity check */
- if (p_tx_desc_used == NULL)
- return ETH_ERROR;
-
- command_status = p_tx_desc_used->cmd_sts;
-
- /* Still transmitting... */
- if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
- D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
- return ETH_RETRY;
- }
-
- /* Stop release. About to overlap the current available Tx descriptor */
- if ((p_tx_desc_used == p_tx_desc_first) &&
- (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
- D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
- return ETH_END_OF_JOB;
- }
-
- /* Pass the packet information to the caller */
- p_pkt_info->cmd_sts = command_status;
- p_pkt_info->return_info = p_tx_desc_used->return_info;
- p_tx_desc_used->return_info = 0;
-
- /* Update the next descriptor to release. */
- USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
-
- /* Any Tx return cancels the Tx resource error status */
- if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
- p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
-
- D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
-
- return ETH_OK;
-
-}
-
-/*******************************************************************************
- * eth_port_receive - Get received information from Rx ring.
- *
- * DESCRIPTION:
- * This routine returns the received data to the caller. There is no
- * data copying during routine operation. All information is returned
- * using pointer to packet information struct passed from the caller.
- * If the routine exhausts Rx ring resources then the resource error flag
- * is set.
- *
- * INPUT:
- * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
- * ETH_QUEUE rx_queue Number of Rx queue.
- * PKT_INFO *p_pkt_info User packet buffer.
- *
- * OUTPUT:
- * Rx ring current and used indexes are updated.
- *
- * RETURN:
- * ETH_ERROR in case the routine can not access Rx desc ring.
- * ETH_QUEUE_FULL if Rx ring resources are exhausted.
- * ETH_END_OF_JOB if there is no received data.
- * ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
- ETH_QUEUE rx_queue,
- PKT_INFO * p_pkt_info)
-{
- volatile ETH_RX_DESC *p_rx_curr_desc;
- volatile ETH_RX_DESC *p_rx_next_curr_desc;
- volatile ETH_RX_DESC *p_rx_used_desc;
- unsigned int command_status;
-
- /* Do not process Rx ring in case of Rx ring resource error */
- if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
- printf ("\nRx Queue is full ...\n");
- return ETH_QUEUE_FULL;
- }
-
- /* Get the Rx Desc ring 'curr and 'used' indexes */
- CURR_RFD_GET (p_rx_curr_desc, rx_queue);
- USED_RFD_GET (p_rx_used_desc, rx_queue);
-
- /* Sanity check */
- if (p_rx_curr_desc == NULL)
- return ETH_ERROR;
-
- /* The following parameters are used to save readings from memory */
- p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
- command_status = p_rx_curr_desc->cmd_sts;
-
- /* Nothing to receive... */
- if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
-/* DP(printf("Rx: command_status: %08x\n", command_status)); */
- D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
-/* DP(printf("\nETH_END_OF_JOB ...\n"));*/
- return ETH_END_OF_JOB;
- }
-
- p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
- p_pkt_info->cmd_sts = command_status;
- p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
- p_pkt_info->return_info = p_rx_curr_desc->return_info;
- p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */
-
- /* Clean the return info field to indicate that the packet has been */
- /* moved to the upper layers */
- p_rx_curr_desc->return_info = 0;
-
- /* Update 'curr' in data structure */
- CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
-
- /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
- if (p_rx_next_curr_desc == p_rx_used_desc)
- p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
-
- D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
- CPU_PIPE_FLUSH;
- return ETH_OK;
-}
-
-/*******************************************************************************
- * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
- *
- * DESCRIPTION:
- * This routine returns a Rx buffer back to the Rx ring. It retrieves the
- * next 'used' descriptor and attached the returned buffer to it.
- * In case the Rx ring was in "resource error" condition, where there are
- * no available Rx resources, the function resets the resource error flag.
- *
- * INPUT:
- * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
- * ETH_QUEUE rx_queue Number of Rx queue.
- * PKT_INFO *p_pkt_info Information on the returned buffer.
- *
- * OUTPUT:
- * New available Rx resource in Rx descriptor ring.
- *
- * RETURN:
- * ETH_ERROR in case the routine can not access Rx desc ring.
- * ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
- p_eth_port_ctrl,
- ETH_QUEUE rx_queue,
- PKT_INFO * p_pkt_info)
-{
- volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */
-
- /* Get 'used' Rx descriptor */
- USED_RFD_GET (p_used_rx_desc, rx_queue);
-
- /* Sanity check */
- if (p_used_rx_desc == NULL)
- return ETH_ERROR;
-
- p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
- p_used_rx_desc->return_info = p_pkt_info->return_info;
- p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
- p_used_rx_desc->buf_size = MV64460_RX_BUFFER_SIZE; /* Reset Buffer size */
-
- /* Flush the write pipe */
- CPU_PIPE_FLUSH;
-
- /* Return the descriptor to DMA ownership */
- p_used_rx_desc->cmd_sts =
- ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
-
- /* Flush descriptor and CPU pipe */
- D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
- CPU_PIPE_FLUSH;
-
- /* Move the used descriptor pointer to the next descriptor */
- USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
-
- /* Any Rx return cancels the Rx resource error status */
- if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
- p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
-
- return ETH_OK;
-}
-
-/*******************************************************************************
- * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
- *
- * DESCRIPTION:
- * This routine sets the RX coalescing interrupt mechanism parameter.
- * This parameter is a timeout counter, that counts in 64 t_clk
- * chunks ; that when timeout event occurs a maskable interrupt
- * occurs.
- * The parameter is calculated using the tClk of the MV-643xx chip
- * , and the required delay of the interrupt in usec.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet port number
- * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
- * unsigned int delay Delay in usec
- *
- * OUTPUT:
- * Interrupt coalescing mechanism value is set in MV-643xx chip.
- *
- * RETURN:
- * The interrupt coalescing value set in the gigE port.
- *
- *******************************************************************************/
-#if 0 /* FIXME */
-static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
- unsigned int t_clk,
- unsigned int delay)
-{
- unsigned int coal;
-
- coal = ((t_clk / 1000000) * delay) / 64;
- /* Set RX Coalescing mechanism */
- MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),
- ((coal & 0x3fff) << 8) |
- (MV_REG_READ
- (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num))
- & 0xffc000ff));
- return coal;
-}
-
-#endif
-/*******************************************************************************
- * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
- *
- * DESCRIPTION:
- * This routine sets the TX coalescing interrupt mechanism parameter.
- * This parameter is a timeout counter, that counts in 64 t_clk
- * chunks ; that when timeout event occurs a maskable interrupt
- * occurs.
- * The parameter is calculated using the t_cLK frequency of the
- * MV-643xx chip and the required delay in the interrupt in uSec
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet port number
- * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
- * unsigned int delay Delay in uSeconds
- *
- * OUTPUT:
- * Interrupt coalescing mechanism value is set in MV-643xx chip.
- *
- * RETURN:
- * The interrupt coalescing value set in the gigE port.
- *
- *******************************************************************************/
-#if 0 /* FIXME */
-static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
- unsigned int t_clk,
- unsigned int delay)
-{
- unsigned int coal;
-
- coal = ((t_clk / 1000000) * delay) / 64;
- /* Set TX Coalescing mechanism */
- MV_REG_WRITE (MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
- coal << 4);
- return coal;
-}
-#endif
-
-/*******************************************************************************
- * eth_b_copy - Copy bytes from source to destination
- *
- * DESCRIPTION:
- * This function supports the eight bytes limitation on Tx buffer size.
- * The routine will zero eight bytes starting from the destination address
- * followed by copying bytes from the source address to the destination.
- *
- * INPUT:
- * unsigned int src_addr 32 bit source address.
- * unsigned int dst_addr 32 bit destination address.
- * int byte_count Number of bytes to copy.
- *
- * OUTPUT:
- * See description.
- *
- * RETURN:
- * None.
- *
- *******************************************************************************/
-static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
- int byte_count)
-{
- /* Zero the dst_addr area */
- *(unsigned int *) dst_addr = 0x0;
-
- while (byte_count != 0) {
- *(char *) dst_addr = *(char *) src_addr;
- dst_addr++;
- src_addr++;
- byte_count--;
- }
-}
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64460X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * mv_eth.h - header file for the polled mode GT ethernet driver
- */
-
-#ifndef __DB64460_ETH_H__
-#define __DB64460_ETH_H__
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-#include <common.h>
-#include <net.h>
-#include "mv_regs.h"
-#include <asm/errno.h>
-
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-* The first part is the high level driver of the gigE ethernet ports. *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
-#ifndef MAX_SKB_FRAGS
-#define MAX_SKB_FRAGS 0
-#endif
-
-/* Port attributes */
-/*#define MAX_RX_QUEUE_NUM 8*/
-/*#define MAX_TX_QUEUE_NUM 8*/
-#define MAX_RX_QUEUE_NUM 1
-#define MAX_TX_QUEUE_NUM 1
-
-
-/* Use one TX queue and one RX queue */
-#define MV64460_TX_QUEUE_NUM 1
-#define MV64460_RX_QUEUE_NUM 1
-
-/*
- * Number of RX / TX descriptors on RX / TX rings.
- * Note that allocating RX descriptors is done by allocating the RX
- * ring AND a preallocated RX buffers (skb's) for each descriptor.
- * The TX descriptors only allocates the TX descriptors ring,
- * with no pre allocated TX buffers (skb's are allocated by higher layers.
- */
-
-/* Default TX ring size is 10 descriptors */
-#ifdef CONFIG_MV64460_ETH_TXQUEUE_SIZE
-#define MV64460_TX_QUEUE_SIZE CONFIG_MV64460_ETH_TXQUEUE_SIZE
-#else
-#define MV64460_TX_QUEUE_SIZE 4
-#endif
-
-/* Default RX ring size is 4 descriptors */
-#ifdef CONFIG_MV64460_ETH_RXQUEUE_SIZE
-#define MV64460_RX_QUEUE_SIZE CONFIG_MV64460_ETH_RXQUEUE_SIZE
-#else
-#define MV64460_RX_QUEUE_SIZE 4
-#endif
-
-#ifdef CONFIG_RX_BUFFER_SIZE
-#define MV64460_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
-#else
-#define MV64460_RX_BUFFER_SIZE 1600
-#endif
-
-#ifdef CONFIG_TX_BUFFER_SIZE
-#define MV64460_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
-#else
-#define MV64460_TX_BUFFER_SIZE 1600
-#endif
-
-/*
- * Network device statistics. Akin to the 2.0 ether stats but
- * with byte counters.
- */
-
-struct net_device_stats
-{
- unsigned long rx_packets; /* total packets received */
- unsigned long tx_packets; /* total packets transmitted */
- unsigned long rx_bytes; /* total bytes received */
- unsigned long tx_bytes; /* total bytes transmitted */
- unsigned long rx_errors; /* bad packets received */
- unsigned long tx_errors; /* packet transmit problems */
- unsigned long rx_dropped; /* no space in linux buffers */
- unsigned long tx_dropped; /* no space available in linux */
- unsigned long multicast; /* multicast packets received */
- unsigned long collisions;
-
- /* detailed rx_errors: */
- unsigned long rx_length_errors;
- unsigned long rx_over_errors; /* receiver ring buff overflow */
- unsigned long rx_crc_errors; /* recved pkt with crc error */
- unsigned long rx_frame_errors; /* recv'd frame alignment error */
- unsigned long rx_fifo_errors; /* recv'r fifo overrun */
- unsigned long rx_missed_errors; /* receiver missed packet */
-
- /* detailed tx_errors */
- unsigned long tx_aborted_errors;
- unsigned long tx_carrier_errors;
- unsigned long tx_fifo_errors;
- unsigned long tx_heartbeat_errors;
- unsigned long tx_window_errors;
-
- /* for cslip etc */
- unsigned long rx_compressed;
- unsigned long tx_compressed;
-};
-
-
-/* Private data structure used for ethernet device */
-struct mv64460_eth_priv {
- unsigned int port_num;
- struct net_device_stats *stats;
-
-/* to buffer area aligned */
- char * p_eth_tx_buffer[MV64460_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */
- char * p_eth_rx_buffer[MV64460_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */
-
- /* Size of Tx Ring per queue */
- unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
-
-
- /* Size of Rx Ring per queue */
- unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
-
- /* Magic Number for Ethernet running */
- unsigned int eth_running;
-
-};
-
-int mv64460_eth_init (struct eth_device *dev);
-int mv64460_eth_stop (struct eth_device *dev);
-int mv64460_eth_start_xmit(struct eth_device *dev, void *packet, int length);
-int mv64460_eth_open (struct eth_device *dev);
-
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-* The second part is the low level driver of the gigE ethernet ports. *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-
-
-/********************************************************************************
- * Header File for : MV-643xx network interface header
- *
- * DESCRIPTION:
- * This header file contains macros typedefs and function declaration for
- * the Marvell Gig Bit Ethernet Controller.
- *
- * DEPENDENCIES:
- * None.
- *
- *******************************************************************************/
-
-
-#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
-#ifdef CONFIG_MV64460_SRAM_CACHEABLE
-/* In case SRAM is cacheable but not cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset) \
-{ \
- __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
-}
-#else
-/* In case SRAM is cache coherent or non-cacheable */
-#define D_CACHE_FLUSH_LINE(addr, offset) ;
-#endif
-#else
-#ifdef CONFIG_NOT_COHERENT_CACHE
-/* In case of descriptors on DDR but not cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset) \
-{ \
- __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
-}
-#else
-/* In case of descriptors on DDR and cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset) ;
-#endif /* CONFIG_NOT_COHERENT_CACHE */
-#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
-
-
-#define CPU_PIPE_FLUSH \
-{ \
- __asm__ __volatile__ ("eieio"); \
-}
-
-
-/* defines */
-
-/* Default port configuration value */
-#define PORT_CONFIG_VALUE \
- ETH_UNICAST_NORMAL_MODE | \
- ETH_DEFAULT_RX_QUEUE_0 | \
- ETH_DEFAULT_RX_ARP_QUEUE_0 | \
- ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
- ETH_RECEIVE_BC_IF_IP | \
- ETH_RECEIVE_BC_IF_ARP | \
- ETH_CAPTURE_TCP_FRAMES_DIS | \
- ETH_CAPTURE_UDP_FRAMES_DIS | \
- ETH_DEFAULT_RX_TCP_QUEUE_0 | \
- ETH_DEFAULT_RX_UDP_QUEUE_0 | \
- ETH_DEFAULT_RX_BPDU_QUEUE_0
-
-/* Default port extend configuration value */
-#define PORT_CONFIG_EXTEND_VALUE \
- ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
- ETH_PARTITION_DISABLE
-
-
-/* Default sdma control value */
-#ifdef CONFIG_NOT_COHERENT_CACHE
-#define PORT_SDMA_CONFIG_VALUE \
- ETH_RX_BURST_SIZE_16_64BIT | \
- GT_ETH_IPG_INT_RX(0) | \
- ETH_TX_BURST_SIZE_16_64BIT;
-#else
-#define PORT_SDMA_CONFIG_VALUE \
- ETH_RX_BURST_SIZE_4_64BIT | \
- GT_ETH_IPG_INT_RX(0) | \
- ETH_TX_BURST_SIZE_4_64BIT;
-#endif
-
-#define GT_ETH_IPG_INT_RX(value) \
- ((value & 0x3fff) << 8)
-
-/* Default port serial control value */
-#define PORT_SERIAL_CONTROL_VALUE \
- ETH_FORCE_LINK_PASS | \
- ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
- ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
- ETH_ADV_SYMMETRIC_FLOW_CTRL | \
- ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
- ETH_FORCE_BP_MODE_NO_JAM | \
- BIT9 | \
- ETH_DO_NOT_FORCE_LINK_FAIL | \
- ETH_RETRANSMIT_16_ETTEMPTS | \
- ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
- ETH_DTE_ADV_0 | \
- ETH_DISABLE_AUTO_NEG_BYPASS | \
- ETH_AUTO_NEG_NO_CHANGE | \
- ETH_MAX_RX_PACKET_1552BYTE | \
- ETH_CLR_EXT_LOOPBACK | \
- ETH_SET_FULL_DUPLEX_MODE | \
- ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
-
-#define RX_BUFFER_MAX_SIZE 0xFFFF
-#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */
-
-#define RX_BUFFER_MIN_SIZE 0x8
-#define TX_BUFFER_MIN_SIZE 0x8
-
-/* Tx WRR confoguration macros */
-#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
-#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */
-#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */
-
-/* MAC accepet/reject macros */
-#define ACCEPT_MAC_ADDR 0
-#define REJECT_MAC_ADDR 1
-
-/* Size of a Tx/Rx descriptor used in chain list data structure */
-#define RX_DESC_ALIGNED_SIZE 0x20
-#define TX_DESC_ALIGNED_SIZE 0x20
-
-/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
-#define TX_BUF_OFFSET_IN_DESC 0x18
-/* Buffer offset from buffer pointer */
-#define RX_BUF_OFFSET 0x2
-
-/* Gap define */
-#define ETH_BAR_GAP 0x8
-#define ETH_SIZE_REG_GAP 0x8
-#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4
-#define ETH_PORT_ACCESS_CTRL_GAP 0x4
-
-/* Gigabit Ethernet Unit Global Registers */
-
-/* MIB Counters register definitions */
-#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
-#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
-#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
-#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
-#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
-#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
-#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
-#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
-#define ETH_MIB_FRAMES_64_OCTETS 0x20
-#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
-#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
-#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
-#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
-#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
-#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
-#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
-#define ETH_MIB_GOOD_FRAMES_SENT 0x40
-#define ETH_MIB_EXCESSIVE_COLLISION 0x44
-#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
-#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
-#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
-#define ETH_MIB_FC_SENT 0x54
-#define ETH_MIB_GOOD_FC_RECEIVED 0x58
-#define ETH_MIB_BAD_FC_RECEIVED 0x5c
-#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
-#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
-#define ETH_MIB_OVERSIZE_RECEIVED 0x68
-#define ETH_MIB_JABBER_RECEIVED 0x6c
-#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
-#define ETH_MIB_BAD_CRC_EVENT 0x74
-#define ETH_MIB_COLLISION 0x78
-#define ETH_MIB_LATE_COLLISION 0x7c
-
-/* Port serial status reg (PSR) */
-#define ETH_INTERFACE_GMII_MII 0
-#define ETH_INTERFACE_PCM BIT0
-#define ETH_LINK_IS_DOWN 0
-#define ETH_LINK_IS_UP BIT1
-#define ETH_PORT_AT_HALF_DUPLEX 0
-#define ETH_PORT_AT_FULL_DUPLEX BIT2
-#define ETH_RX_FLOW_CTRL_DISABLED 0
-#define ETH_RX_FLOW_CTRL_ENBALED BIT3
-#define ETH_GMII_SPEED_100_10 0
-#define ETH_GMII_SPEED_1000 BIT4
-#define ETH_MII_SPEED_10 0
-#define ETH_MII_SPEED_100 BIT5
-#define ETH_NO_TX 0
-#define ETH_TX_IN_PROGRESS BIT7
-#define ETH_BYPASS_NO_ACTIVE 0
-#define ETH_BYPASS_ACTIVE BIT8
-#define ETH_PORT_NOT_AT_PARTITION_STATE 0
-#define ETH_PORT_AT_PARTITION_STATE BIT9
-#define ETH_PORT_TX_FIFO_NOT_EMPTY 0
-#define ETH_PORT_TX_FIFO_EMPTY BIT10
-
-
-/* These macros describes the Port configuration reg (Px_cR) bits */
-#define ETH_UNICAST_NORMAL_MODE 0
-#define ETH_UNICAST_PROMISCUOUS_MODE BIT0
-#define ETH_DEFAULT_RX_QUEUE_0 0
-#define ETH_DEFAULT_RX_QUEUE_1 BIT1
-#define ETH_DEFAULT_RX_QUEUE_2 BIT2
-#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1)
-#define ETH_DEFAULT_RX_QUEUE_4 BIT3
-#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1)
-#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2)
-#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1)
-#define ETH_DEFAULT_RX_ARP_QUEUE_0 0
-#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4
-#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5
-#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4)
-#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6
-#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4)
-#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5)
-#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4)
-#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
-#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7
-#define ETH_RECEIVE_BC_IF_IP 0
-#define ETH_REJECT_BC_IF_IP BIT8
-#define ETH_RECEIVE_BC_IF_ARP 0
-#define ETH_REJECT_BC_IF_ARP BIT9
-#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12
-#define ETH_CAPTURE_TCP_FRAMES_DIS 0
-#define ETH_CAPTURE_TCP_FRAMES_EN BIT14
-#define ETH_CAPTURE_UDP_FRAMES_DIS 0
-#define ETH_CAPTURE_UDP_FRAMES_EN BIT15
-#define ETH_DEFAULT_RX_TCP_QUEUE_0 0
-#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16
-#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17
-#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16)
-#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18
-#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16)
-#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17)
-#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16)
-#define ETH_DEFAULT_RX_UDP_QUEUE_0 0
-#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19
-#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20
-#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19)
-#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21
-#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19)
-#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20)
-#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0
-#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22
-#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23
-#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
-#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
-
-
-/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
-#define ETH_CLASSIFY_EN BIT0
-#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
-#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1
-#define ETH_PARTITION_DISABLE 0
-#define ETH_PARTITION_ENABLE BIT2
-
-
-/* Tx/Rx queue command reg (RQCR/TQCR)*/
-#define ETH_QUEUE_0_ENABLE BIT0
-#define ETH_QUEUE_1_ENABLE BIT1
-#define ETH_QUEUE_2_ENABLE BIT2
-#define ETH_QUEUE_3_ENABLE BIT3
-#define ETH_QUEUE_4_ENABLE BIT4
-#define ETH_QUEUE_5_ENABLE BIT5
-#define ETH_QUEUE_6_ENABLE BIT6
-#define ETH_QUEUE_7_ENABLE BIT7
-#define ETH_QUEUE_0_DISABLE BIT8
-#define ETH_QUEUE_1_DISABLE BIT9
-#define ETH_QUEUE_2_DISABLE BIT10
-#define ETH_QUEUE_3_DISABLE BIT11
-#define ETH_QUEUE_4_DISABLE BIT12
-#define ETH_QUEUE_5_DISABLE BIT13
-#define ETH_QUEUE_6_DISABLE BIT14
-#define ETH_QUEUE_7_DISABLE BIT15
-
-/* These macros describes the Port Sdma configuration reg (SDCR) bits */
-#define ETH_RIFB BIT0
-#define ETH_RX_BURST_SIZE_1_64BIT 0
-#define ETH_RX_BURST_SIZE_2_64BIT BIT1
-#define ETH_RX_BURST_SIZE_4_64BIT BIT2
-#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1)
-#define ETH_RX_BURST_SIZE_16_64BIT BIT3
-#define ETH_BLM_RX_NO_SWAP BIT4
-#define ETH_BLM_RX_BYTE_SWAP 0
-#define ETH_BLM_TX_NO_SWAP BIT5
-#define ETH_BLM_TX_BYTE_SWAP 0
-#define ETH_DESCRIPTORS_BYTE_SWAP BIT6
-#define ETH_DESCRIPTORS_NO_SWAP 0
-#define ETH_TX_BURST_SIZE_1_64BIT 0
-#define ETH_TX_BURST_SIZE_2_64BIT BIT22
-#define ETH_TX_BURST_SIZE_4_64BIT BIT23
-#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22)
-#define ETH_TX_BURST_SIZE_16_64BIT BIT24
-
-/* These macros describes the Port serial control reg (PSCR) bits */
-#define ETH_SERIAL_PORT_DISABLE 0
-#define ETH_SERIAL_PORT_ENABLE BIT0
-#define ETH_FORCE_LINK_PASS BIT1
-#define ETH_DO_NOT_FORCE_LINK_PASS 0
-#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
-#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2
-#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
-#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3
-#define ETH_ADV_NO_FLOW_CTRL 0
-#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4
-#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
-#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5
-#define ETH_FORCE_BP_MODE_NO_JAM 0
-#define ETH_FORCE_BP_MODE_JAM_TX BIT7
-#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8
-#define ETH_FORCE_LINK_FAIL 0
-#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10
-#define ETH_RETRANSMIT_16_ETTEMPTS 0
-#define ETH_RETRANSMIT_FOREVER BIT11
-#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13
-#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
-#define ETH_DTE_ADV_0 0
-#define ETH_DTE_ADV_1 BIT14
-#define ETH_DISABLE_AUTO_NEG_BYPASS 0
-#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15
-#define ETH_AUTO_NEG_NO_CHANGE 0
-#define ETH_RESTART_AUTO_NEG BIT16
-#define ETH_MAX_RX_PACKET_1518BYTE 0
-#define ETH_MAX_RX_PACKET_1522BYTE BIT17
-#define ETH_MAX_RX_PACKET_1552BYTE BIT18
-#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17)
-#define ETH_MAX_RX_PACKET_9192BYTE BIT19
-#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17)
-#define ETH_SET_EXT_LOOPBACK BIT20
-#define ETH_CLR_EXT_LOOPBACK 0
-#define ETH_SET_FULL_DUPLEX_MODE BIT21
-#define ETH_SET_HALF_DUPLEX_MODE 0
-#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22
-#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
-#define ETH_SET_GMII_SPEED_TO_10_100 0
-#define ETH_SET_GMII_SPEED_TO_1000 BIT23
-#define ETH_SET_MII_SPEED_TO_10 0
-#define ETH_SET_MII_SPEED_TO_100 BIT24
-
-
-/* SMI reg */
-#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
-#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
-#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
-#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
-
-/* SDMA command status fields macros */
-
-/* Tx & Rx descriptors status */
-#define ETH_ERROR_SUMMARY (BIT0)
-
-/* Tx & Rx descriptors command */
-#define ETH_BUFFER_OWNED_BY_DMA (BIT31)
-
-/* Tx descriptors status */
-#define ETH_LC_ERROR (0 )
-#define ETH_UR_ERROR (BIT1 )
-#define ETH_RL_ERROR (BIT2 )
-#define ETH_LLC_SNAP_FORMAT (BIT9 )
-
-/* Rx descriptors status */
-#define ETH_CRC_ERROR (0 )
-#define ETH_OVERRUN_ERROR (BIT1 )
-#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
-#define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
-#define ETH_VLAN_TAGGED (BIT19)
-#define ETH_BPDU_FRAME (BIT20)
-#define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
-#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
-#define ETH_OTHER_FRAME_TYPE (BIT22)
-#define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
-#define ETH_FRAME_TYPE_IP_V_4 (BIT24)
-#define ETH_FRAME_HEADER_OK (BIT25)
-#define ETH_RX_LAST_DESC (BIT26)
-#define ETH_RX_FIRST_DESC (BIT27)
-#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
-#define ETH_RX_ENABLE_INTERRUPT (BIT29)
-#define ETH_LAYER_4_CHECKSUM_OK (BIT30)
-
-/* Rx descriptors byte count */
-#define ETH_FRAME_FRAGMENTED (BIT2)
-
-/* Tx descriptors command */
-#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
-#define ETH_FRAME_SET_TO_VLAN (BIT15)
-#define ETH_TCP_FRAME (0 )
-#define ETH_UDP_FRAME (BIT16)
-#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
-#define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
-#define ETH_ZERO_PADDING (BIT19)
-#define ETH_TX_LAST_DESC (BIT20)
-#define ETH_TX_FIRST_DESC (BIT21)
-#define ETH_GEN_CRC (BIT22)
-#define ETH_TX_ENABLE_INTERRUPT (BIT23)
-#define ETH_AUTO_MODE (BIT30)
-
-/* Address decode parameters */
-/* Ethernet Base Address Register bits */
-#define EBAR_TARGET_DRAM 0x00000000
-#define EBAR_TARGET_DEVICE 0x00000001
-#define EBAR_TARGET_CBS 0x00000002
-#define EBAR_TARGET_PCI0 0x00000003
-#define EBAR_TARGET_PCI1 0x00000004
-#define EBAR_TARGET_CUNIT 0x00000005
-#define EBAR_TARGET_AUNIT 0x00000006
-#define EBAR_TARGET_GUNIT 0x00000007
-
-/* Window attributes */
-#define EBAR_ATTR_DRAM_CS0 0x00000E00
-#define EBAR_ATTR_DRAM_CS1 0x00000D00
-#define EBAR_ATTR_DRAM_CS2 0x00000B00
-#define EBAR_ATTR_DRAM_CS3 0x00000700
-
-/* DRAM Target interface */
-#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000
-#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000
-#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000
-
-/* Device Bus Target interface */
-#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00
-#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00
-#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00
-#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700
-#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00
-
-/* PCI Target interface */
-#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000
-#define EBAR_ATTR_PCI_NO_SWAP 0x00000100
-#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200
-#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300
-#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
-#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400
-#define EBAR_ATTR_PCI_IO_SPACE 0x00000000
-#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800
-#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000
-#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000
-
-/* CPU 60x bus or internal SRAM interface */
-#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000
-#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100
-#define EBAR_ATTR_CBS_SRAM 0x00000000
-#define EBAR_ATTR_CBS_CPU_BUS 0x00000800
-
-/* Window access control */
-#define EWIN_ACCESS_NOT_ALLOWED 0
-#define EWIN_ACCESS_READ_ONLY BIT0
-#define EWIN_ACCESS_FULL (BIT1 | BIT0)
-#define EWIN0_ACCESS_MASK 0x0003
-#define EWIN1_ACCESS_MASK 0x000C
-#define EWIN2_ACCESS_MASK 0x0030
-#define EWIN3_ACCESS_MASK 0x00C0
-
-/* typedefs */
-
-typedef enum _eth_port
-{
- ETH_0 = 0,
- ETH_1 = 1,
- ETH_2 = 2
-}ETH_PORT;
-
-typedef enum _eth_func_ret_status
-{
- ETH_OK, /* Returned as expected. */
- ETH_ERROR, /* Fundamental error. */
- ETH_RETRY, /* Could not process request. Try later. */
- ETH_END_OF_JOB, /* Ring has nothing to process. */
- ETH_QUEUE_FULL, /* Ring resource error. */
- ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
-}ETH_FUNC_RET_STATUS;
-
-typedef enum _eth_queue
-{
- ETH_Q0 = 0,
- ETH_Q1 = 1,
- ETH_Q2 = 2,
- ETH_Q3 = 3,
- ETH_Q4 = 4,
- ETH_Q5 = 5,
- ETH_Q6 = 6,
- ETH_Q7 = 7
-} ETH_QUEUE;
-
-typedef enum _addr_win
-{
- ETH_WIN0,
- ETH_WIN1,
- ETH_WIN2,
- ETH_WIN3,
- ETH_WIN4,
- ETH_WIN5
-} ETH_ADDR_WIN;
-
-typedef enum _eth_target
-{
- ETH_TARGET_DRAM ,
- ETH_TARGET_DEVICE,
- ETH_TARGET_CBS ,
- ETH_TARGET_PCI0 ,
- ETH_TARGET_PCI1
-}ETH_TARGET;
-
-typedef struct _eth_rx_desc
-{
- unsigned short byte_cnt ; /* Descriptor buffer byte count */
- unsigned short buf_size ; /* Buffer size */
- unsigned int cmd_sts ; /* Descriptor command status */
- unsigned int next_desc_ptr; /* Next descriptor pointer */
- unsigned int buf_ptr ; /* Descriptor buffer pointer */
- unsigned int return_info ; /* User resource return information */
-} ETH_RX_DESC;
-
-
-typedef struct _eth_tx_desc
-{
- unsigned short byte_cnt ; /* Descriptor buffer byte count */
- unsigned short l4i_chk ; /* CPU provided TCP Checksum */
- unsigned int cmd_sts ; /* Descriptor command status */
- unsigned int next_desc_ptr; /* Next descriptor pointer */
- unsigned int buf_ptr ; /* Descriptor buffer pointer */
- unsigned int return_info ; /* User resource return information */
-} ETH_TX_DESC;
-
-/* Unified struct for Rx and Tx operations. The user is not required to */
-/* be familier with neither Tx nor Rx descriptors. */
-typedef struct _pkt_info
-{
- unsigned short byte_cnt ; /* Descriptor buffer byte count */
- unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */
- unsigned int cmd_sts ; /* Descriptor command status */
- unsigned int buf_ptr ; /* Descriptor buffer pointer */
- unsigned int return_info ; /* User resource return information */
-} PKT_INFO;
-
-
-typedef struct _eth_win_param
-{
- ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */
- ETH_TARGET target; /* System targets. See ETH_TARGET enum */
- unsigned short attributes; /* BAR attributes. See above macros. */
- unsigned int base_addr; /* Window base address in unsigned int form */
- unsigned int high_addr; /* Window high address in unsigned int form */
- unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
- bool enable; /* Enable/disable access to the window. */
- unsigned short access_ctrl; /* Access ctrl register. see above macros */
-} ETH_WIN_PARAM;
-
-
-/* Ethernet port specific infomation */
-
-typedef struct _eth_port_ctrl
-{
- ETH_PORT port_num; /* User Ethernet port number */
- int port_phy_addr; /* User phy address of Ethrnet port */
- unsigned char port_mac_addr[6]; /* User defined port MAC address. */
- unsigned int port_config; /* User port configuration value */
- unsigned int port_config_extend; /* User port config extend value */
- unsigned int port_sdma_config; /* User port SDMA config value */
- unsigned int port_serial_control; /* User port serial control value */
- unsigned int port_tx_queue_command; /* Port active Tx queues summary */
- unsigned int port_rx_queue_command; /* Port active Rx queues summary */
-
- /* User function to cast virtual address to CPU bus address */
- unsigned int (*port_virt_to_phys)(unsigned int addr);
- /* User scratch pad for user specific data structures */
- void *port_private;
-
- bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
- bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
-
- /* Tx/Rx rings managment indexes fields. For driver use */
-
- /* Next available Rx resource */
- volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
- /* Returning Rx resource */
- volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
-
- /* Next available Tx resource */
- volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
- /* Returning Tx resource */
- volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
- /* An extra Tx index to support transmit of multiple buffers per packet */
- volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
-
- /* Tx/Rx rings size and base variables fields. For driver use */
-
- volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
- unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM];
- char *p_rx_buffer_base[MAX_RX_QUEUE_NUM];
-
- volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
- unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM];
- char *p_tx_buffer_base[MAX_TX_QUEUE_NUM];
-
-} ETH_PORT_INFO;
-
-
-/* ethernet.h API list */
-
-/* Port operation control routines */
-static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
-static void eth_port_reset(ETH_PORT eth_port_num);
-static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
-
-
-/* Port MAC address routines */
-static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
- unsigned char *p_addr,
- ETH_QUEUE queue);
-#if 0 /* FIXME */
-static void eth_port_mc_addr (ETH_PORT eth_port_num,
- unsigned char *p_addr,
- ETH_QUEUE queue,
- int option);
-#endif
-
-/* PHY and MIB routines */
-static bool ethernet_phy_reset(ETH_PORT eth_port_num);
-
-static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
- unsigned int phy_reg,
- unsigned int value);
-
-static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
- unsigned int phy_reg,
- unsigned int* value);
-
-static void eth_clear_mib_counters(ETH_PORT eth_port_num);
-
-/* Port data flow control routines */
-static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl,
- ETH_QUEUE tx_queue,
- PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
- ETH_QUEUE tx_queue,
- PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
- ETH_QUEUE rx_queue,
- PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
- ETH_QUEUE rx_queue,
- PKT_INFO *p_pkt_info);
-
-
-static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
- ETH_QUEUE tx_queue,
- int tx_desc_num,
- int tx_buff_size,
- unsigned int tx_desc_base_addr,
- unsigned int tx_buff_base_addr);
-
-static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
- ETH_QUEUE rx_queue,
- int rx_desc_num,
- int rx_buff_size,
- unsigned int rx_desc_base_addr,
- unsigned int rx_buff_base_addr);
-
-#endif /* MV64460_ETH_ */
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64460X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/********************************************************************************
-* gt64460r.h - GT-64460 Internal registers definition file.
-*
-* DESCRIPTION:
-* None.
-*
-* DEPENDENCIES:
-* None.
-*
-*******************************************************************************/
-
-#ifndef __INCmv_regsh
-#define __INCmv_regsh
-
-#define MV64460
-
-/* Supported by the Atlantis */
-#define MV64460_INCLUDE_PCI_1
-#define MV64460_INCLUDE_PCI_0_ARBITER
-#define MV64460_INCLUDE_PCI_1_ARBITER
-#define MV64460_INCLUDE_SNOOP_SUPPORT
-#define MV64460_INCLUDE_P2P
-#define MV64460_INCLUDE_ETH_PORT_2
-#define MV64460_INCLUDE_CPU_MAPPING
-#define MV64460_INCLUDE_MPSC
-
-/* Not supported features */
-#undef INCLUDE_CNTMR_4_7
-#undef INCLUDE_DMA_4_7
-
-/****************************************/
-/* Processor Address Space */
-/****************************************/
-
-/* DDR SDRAM BAR and size registers */
-
-#define MV64460_CS_0_BASE_ADDR 0x008
-#define MV64460_CS_0_SIZE 0x010
-#define MV64460_CS_1_BASE_ADDR 0x208
-#define MV64460_CS_1_SIZE 0x210
-#define MV64460_CS_2_BASE_ADDR 0x018
-#define MV64460_CS_2_SIZE 0x020
-#define MV64460_CS_3_BASE_ADDR 0x218
-#define MV64460_CS_3_SIZE 0x220
-
-/* Devices BAR and size registers */
-
-#define MV64460_DEV_CS0_BASE_ADDR 0x028
-#define MV64460_DEV_CS0_SIZE 0x030
-#define MV64460_DEV_CS1_BASE_ADDR 0x228
-#define MV64460_DEV_CS1_SIZE 0x230
-#define MV64460_DEV_CS2_BASE_ADDR 0x248
-#define MV64460_DEV_CS2_SIZE 0x250
-#define MV64460_DEV_CS3_BASE_ADDR 0x038
-#define MV64460_DEV_CS3_SIZE 0x040
-#define MV64460_BOOTCS_BASE_ADDR 0x238
-#define MV64460_BOOTCS_SIZE 0x240
-
-/* PCI 0 BAR and size registers */
-
-#define MV64460_PCI_0_IO_BASE_ADDR 0x048
-#define MV64460_PCI_0_IO_SIZE 0x050
-#define MV64460_PCI_0_MEMORY0_BASE_ADDR 0x058
-#define MV64460_PCI_0_MEMORY0_SIZE 0x060
-#define MV64460_PCI_0_MEMORY1_BASE_ADDR 0x080
-#define MV64460_PCI_0_MEMORY1_SIZE 0x088
-#define MV64460_PCI_0_MEMORY2_BASE_ADDR 0x258
-#define MV64460_PCI_0_MEMORY2_SIZE 0x260
-#define MV64460_PCI_0_MEMORY3_BASE_ADDR 0x280
-#define MV64460_PCI_0_MEMORY3_SIZE 0x288
-
-/* PCI 1 BAR and size registers */
-#define MV64460_PCI_1_IO_BASE_ADDR 0x090
-#define MV64460_PCI_1_IO_SIZE 0x098
-#define MV64460_PCI_1_MEMORY0_BASE_ADDR 0x0a0
-#define MV64460_PCI_1_MEMORY0_SIZE 0x0a8
-#define MV64460_PCI_1_MEMORY1_BASE_ADDR 0x0b0
-#define MV64460_PCI_1_MEMORY1_SIZE 0x0b8
-#define MV64460_PCI_1_MEMORY2_BASE_ADDR 0x2a0
-#define MV64460_PCI_1_MEMORY2_SIZE 0x2a8
-#define MV64460_PCI_1_MEMORY3_BASE_ADDR 0x2b0
-#define MV64460_PCI_1_MEMORY3_SIZE 0x2b8
-
-/* SRAM base address */
-#define MV64460_INTEGRATED_SRAM_BASE_ADDR 0x268
-
-/* internal registers space base address */
-#define MV64460_INTERNAL_SPACE_BASE_ADDR 0x068
-
-/* Enables the CS , DEV_CS , PCI 0 and PCI 1
- windows above */
-#define MV64460_BASE_ADDR_ENABLE 0x278
-
-/****************************************/
-/* PCI remap registers */
-/****************************************/
- /* PCI 0 */
-#define MV64460_PCI_0_IO_ADDR_REMAP 0x0f0
-#define MV64460_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8
-#define MV64460_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320
-#define MV64460_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100
-#define MV64460_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328
-#define MV64460_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8
-#define MV64460_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330
-#define MV64460_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300
-#define MV64460_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338
- /* PCI 1 */
-#define MV64460_PCI_1_IO_ADDR_REMAP 0x108
-#define MV64460_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110
-#define MV64460_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340
-#define MV64460_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118
-#define MV64460_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348
-#define MV64460_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310
-#define MV64460_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350
-#define MV64460_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318
-#define MV64460_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358
-
-#define MV64460_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0
-#define MV64460_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8
-#define MV64460_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0
-#define MV64460_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8
-#define MV64460_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0
-#define MV64460_CPU_GE_HEADERS_RETARGET_BASE 0x3d8
-#define MV64460_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0
-#define MV64460_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8
-
-/****************************************/
-/* CPU Control Registers */
-/****************************************/
-
-#define MV64460_CPU_CONFIG 0x000
-#define MV64460_CPU_MODE 0x120
-#define MV64460_CPU_MASTER_CONTROL 0x160
-#define MV64460_CPU_CROSS_BAR_CONTROL_LOW 0x150
-#define MV64460_CPU_CROSS_BAR_CONTROL_HIGH 0x158
-#define MV64460_CPU_CROSS_BAR_TIMEOUT 0x168
-
-/****************************************/
-/* SMP RegisterS */
-/****************************************/
-
-#define MV64460_SMP_WHO_AM_I 0x200
-#define MV64460_SMP_CPU0_DOORBELL 0x214
-#define MV64460_SMP_CPU0_DOORBELL_CLEAR 0x21C
-#define MV64460_SMP_CPU1_DOORBELL 0x224
-#define MV64460_SMP_CPU1_DOORBELL_CLEAR 0x22C
-#define MV64460_SMP_CPU0_DOORBELL_MASK 0x234
-#define MV64460_SMP_CPU1_DOORBELL_MASK 0x23C
-#define MV64460_SMP_SEMAPHOR0 0x244
-#define MV64460_SMP_SEMAPHOR1 0x24c
-#define MV64460_SMP_SEMAPHOR2 0x254
-#define MV64460_SMP_SEMAPHOR3 0x25c
-#define MV64460_SMP_SEMAPHOR4 0x264
-#define MV64460_SMP_SEMAPHOR5 0x26c
-#define MV64460_SMP_SEMAPHOR6 0x274
-#define MV64460_SMP_SEMAPHOR7 0x27c
-
-/****************************************/
-/* CPU Sync Barrier Register */
-/****************************************/
-
-#define MV64460_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0
-#define MV64460_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8
-#define MV64460_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0
-#define MV64460_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8
-
-/****************************************/
-/* CPU Access Protect */
-/****************************************/
-
-#define MV64460_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180
-#define MV64460_CPU_PROTECT_WINDOW_0_SIZE 0x188
-#define MV64460_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190
-#define MV64460_CPU_PROTECT_WINDOW_1_SIZE 0x198
-#define MV64460_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0
-#define MV64460_CPU_PROTECT_WINDOW_2_SIZE 0x1a8
-#define MV64460_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0
-#define MV64460_CPU_PROTECT_WINDOW_3_SIZE 0x1b8
-
-
-/****************************************/
-/* CPU Error Report */
-/****************************************/
-
-#define MV64460_CPU_ERROR_ADDR_LOW 0x070
-#define MV64460_CPU_ERROR_ADDR_HIGH 0x078
-#define MV64460_CPU_ERROR_DATA_LOW 0x128
-#define MV64460_CPU_ERROR_DATA_HIGH 0x130
-#define MV64460_CPU_ERROR_PARITY 0x138
-#define MV64460_CPU_ERROR_CAUSE 0x140
-#define MV64460_CPU_ERROR_MASK 0x148
-
-/****************************************/
-/* CPU Interface Debug Registers */
-/****************************************/
-
-#define MV64460_PUNIT_SLAVE_DEBUG_LOW 0x360
-#define MV64460_PUNIT_SLAVE_DEBUG_HIGH 0x368
-#define MV64460_PUNIT_MASTER_DEBUG_LOW 0x370
-#define MV64460_PUNIT_MASTER_DEBUG_HIGH 0x378
-#define MV64460_PUNIT_MMASK 0x3e4
-
-/****************************************/
-/* Integrated SRAM Registers */
-/****************************************/
-
-#define MV64460_SRAM_CONFIG 0x380
-#define MV64460_SRAM_TEST_MODE 0X3F4
-#define MV64460_SRAM_ERROR_CAUSE 0x388
-#define MV64460_SRAM_ERROR_ADDR 0x390
-#define MV64460_SRAM_ERROR_ADDR_HIGH 0X3F8
-#define MV64460_SRAM_ERROR_DATA_LOW 0x398
-#define MV64460_SRAM_ERROR_DATA_HIGH 0x3a0
-#define MV64460_SRAM_ERROR_DATA_PARITY 0x3a8
-
-/****************************************/
-/* SDRAM Configuration */
-/****************************************/
-
-#define MV64460_SDRAM_CONFIG 0x1400
-#define MV64460_D_UNIT_CONTROL_LOW 0x1404
-#define MV64460_D_UNIT_CONTROL_HIGH 0x1424
-#define MV64460_SDRAM_TIMING_CONTROL_LOW 0x1408
-#define MV64460_SDRAM_TIMING_CONTROL_HIGH 0x140c
-#define MV64460_SDRAM_ADDR_CONTROL 0x1410
-#define MV64460_SDRAM_OPEN_PAGES_CONTROL 0x1414
-#define MV64460_SDRAM_OPERATION 0x1418
-#define MV64460_SDRAM_MODE 0x141c
-#define MV64460_EXTENDED_DRAM_MODE 0x1420
-#define MV64460_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430
-#define MV64460_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434
-#define MV64460_SDRAM_CROSS_BAR_TIMEOUT 0x1438
-#define MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0
-#define MV64460_SDRAM_DATA_PADS_CALIBRATION 0x14c4
-
-/****************************************/
-/* SDRAM Error Report */
-/****************************************/
-
-#define MV64460_SDRAM_ERROR_DATA_LOW 0x1444
-#define MV64460_SDRAM_ERROR_DATA_HIGH 0x1440
-#define MV64460_SDRAM_ERROR_ADDR 0x1450
-#define MV64460_SDRAM_RECEIVED_ECC 0x1448
-#define MV64460_SDRAM_CALCULATED_ECC 0x144c
-#define MV64460_SDRAM_ECC_CONTROL 0x1454
-#define MV64460_SDRAM_ECC_ERROR_COUNTER 0x1458
-
-/******************************************/
-/* Controlled Delay Line (CDL) Registers */
-/******************************************/
-
-#define MV64460_DFCDL_CONFIG0 0x1480
-#define MV64460_DFCDL_CONFIG1 0x1484
-#define MV64460_DLL_WRITE 0x1488
-#define MV64460_DLL_READ 0x148c
-#define MV64460_SRAM_ADDR 0x1490
-#define MV64460_SRAM_DATA0 0x1494
-#define MV64460_SRAM_DATA1 0x1498
-#define MV64460_SRAM_DATA2 0x149c
-#define MV64460_DFCL_PROBE 0x14a0
-
-/******************************************/
-/* Debug Registers */
-/******************************************/
-
-#define MV64460_DUNIT_DEBUG_LOW 0x1460
-#define MV64460_DUNIT_DEBUG_HIGH 0x1464
-#define MV64460_DUNIT_MMASK 0X1b40
-
-/****************************************/
-/* Device Parameters */
-/****************************************/
-
-#define MV64460_DEVICE_BANK0_PARAMETERS 0x45c
-#define MV64460_DEVICE_BANK1_PARAMETERS 0x460
-#define MV64460_DEVICE_BANK2_PARAMETERS 0x464
-#define MV64460_DEVICE_BANK3_PARAMETERS 0x468
-#define MV64460_DEVICE_BOOT_BANK_PARAMETERS 0x46c
-#define MV64460_DEVICE_INTERFACE_CONTROL 0x4c0
-#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8
-#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc
-#define MV64460_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4
-
-/****************************************/
-/* Device interrupt registers */
-/****************************************/
-
-#define MV64460_DEVICE_INTERRUPT_CAUSE 0x4d0
-#define MV64460_DEVICE_INTERRUPT_MASK 0x4d4
-#define MV64460_DEVICE_ERROR_ADDR 0x4d8
-#define MV64460_DEVICE_ERROR_DATA 0x4dc
-#define MV64460_DEVICE_ERROR_PARITY 0x4e0
-
-/****************************************/
-/* Device debug registers */
-/****************************************/
-
-#define MV64460_DEVICE_DEBUG_LOW 0x4e4
-#define MV64460_DEVICE_DEBUG_HIGH 0x4e8
-#define MV64460_RUNIT_MMASK 0x4f0
-
-/****************************************/
-/* PCI Slave Address Decoding registers */
-/****************************************/
-
-#define MV64460_PCI_0_CS_0_BANK_SIZE 0xc08
-#define MV64460_PCI_1_CS_0_BANK_SIZE 0xc88
-#define MV64460_PCI_0_CS_1_BANK_SIZE 0xd08
-#define MV64460_PCI_1_CS_1_BANK_SIZE 0xd88
-#define MV64460_PCI_0_CS_2_BANK_SIZE 0xc0c
-#define MV64460_PCI_1_CS_2_BANK_SIZE 0xc8c
-#define MV64460_PCI_0_CS_3_BANK_SIZE 0xd0c
-#define MV64460_PCI_1_CS_3_BANK_SIZE 0xd8c
-#define MV64460_PCI_0_DEVCS_0_BANK_SIZE 0xc10
-#define MV64460_PCI_1_DEVCS_0_BANK_SIZE 0xc90
-#define MV64460_PCI_0_DEVCS_1_BANK_SIZE 0xd10
-#define MV64460_PCI_1_DEVCS_1_BANK_SIZE 0xd90
-#define MV64460_PCI_0_DEVCS_2_BANK_SIZE 0xd18
-#define MV64460_PCI_1_DEVCS_2_BANK_SIZE 0xd98
-#define MV64460_PCI_0_DEVCS_3_BANK_SIZE 0xc14
-#define MV64460_PCI_1_DEVCS_3_BANK_SIZE 0xc94
-#define MV64460_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14
-#define MV64460_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94
-#define MV64460_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c
-#define MV64460_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c
-#define MV64460_PCI_0_P2P_MEM1_BAR_SIZE 0xd20
-#define MV64460_PCI_1_P2P_MEM1_BAR_SIZE 0xda0
-#define MV64460_PCI_0_P2P_I_O_BAR_SIZE 0xd24
-#define MV64460_PCI_1_P2P_I_O_BAR_SIZE 0xda4
-#define MV64460_PCI_0_CPU_BAR_SIZE 0xd28
-#define MV64460_PCI_1_CPU_BAR_SIZE 0xda8
-#define MV64460_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00
-#define MV64460_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80
-#define MV64460_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c
-#define MV64460_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c
-#define MV64460_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c
-#define MV64460_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc
-#define MV64460_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48
-#define MV64460_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8
-#define MV64460_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48
-#define MV64460_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8
-#define MV64460_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c
-#define MV64460_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc
-#define MV64460_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c
-#define MV64460_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc
-#define MV64460_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04
-#define MV64460_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84
-#define MV64460_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08
-#define MV64460_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88
-#define MV64460_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C
-#define MV64460_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C
-#define MV64460_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10
-#define MV64460_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90
-#define MV64460_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50
-#define MV64460_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0
-#define MV64460_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50
-#define MV64460_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0
-#define MV64460_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58
-#define MV64460_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8
-#define MV64460_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54
-#define MV64460_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4
-#define MV64460_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54
-#define MV64460_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4
-#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c
-#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc
-#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60
-#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0
-#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64
-#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4
-#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68
-#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8
-#define MV64460_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c
-#define MV64460_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec
-#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70
-#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0
-#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74
-#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4
-#define MV64460_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00
-#define MV64460_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80
-#define MV64460_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38
-#define MV64460_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8
-#define MV64460_PCI_0_ADDR_DECODE_CONTROL 0xd3c
-#define MV64460_PCI_1_ADDR_DECODE_CONTROL 0xdbc
-#define MV64460_PCI_0_HEADERS_RETARGET_CONTROL 0xF40
-#define MV64460_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0
-#define MV64460_PCI_0_HEADERS_RETARGET_BASE 0xF44
-#define MV64460_PCI_1_HEADERS_RETARGET_BASE 0xFc4
-#define MV64460_PCI_0_HEADERS_RETARGET_HIGH 0xF48
-#define MV64460_PCI_1_HEADERS_RETARGET_HIGH 0xFc8
-
-/***********************************/
-/* PCI Control Register Map */
-/***********************************/
-
-#define MV64460_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20
-#define MV64460_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0
-#define MV64460_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C
-#define MV64460_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C
-#define MV64460_PCI_0_COMMAND 0xc00
-#define MV64460_PCI_1_COMMAND 0xc80
-#define MV64460_PCI_0_MODE 0xd00
-#define MV64460_PCI_1_MODE 0xd80
-#define MV64460_PCI_0_RETRY 0xc04
-#define MV64460_PCI_1_RETRY 0xc84
-#define MV64460_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04
-#define MV64460_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84
-#define MV64460_PCI_0_MSI_TRIGGER_TIMER 0xc38
-#define MV64460_PCI_1_MSI_TRIGGER_TIMER 0xcb8
-#define MV64460_PCI_0_ARBITER_CONTROL 0x1d00
-#define MV64460_PCI_1_ARBITER_CONTROL 0x1d80
-#define MV64460_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08
-#define MV64460_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88
-#define MV64460_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c
-#define MV64460_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c
-#define MV64460_PCI_0_CROSS_BAR_TIMEOUT 0x1d04
-#define MV64460_PCI_1_CROSS_BAR_TIMEOUT 0x1d84
-#define MV64460_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18
-#define MV64460_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98
-#define MV64460_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10
-#define MV64460_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90
-#define MV64460_PCI_0_P2P_CONFIG 0x1d14
-#define MV64460_PCI_1_P2P_CONFIG 0x1d94
-
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04
-#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14
-#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24
-#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34
-#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44
-#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54
-#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58
-
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84
-#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94
-#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
-#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
-#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
-#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
-#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8
-
-/****************************************/
-/* PCI Configuration Access Registers */
-/****************************************/
-
-#define MV64460_PCI_0_CONFIG_ADDR 0xcf8
-#define MV64460_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc
-#define MV64460_PCI_1_CONFIG_ADDR 0xc78
-#define MV64460_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c
-#define MV64460_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34
-#define MV64460_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4
-
-/****************************************/
-/* PCI Error Report Registers */
-/****************************************/
-
-#define MV64460_PCI_0_SERR_MASK 0xc28
-#define MV64460_PCI_1_SERR_MASK 0xca8
-#define MV64460_PCI_0_ERROR_ADDR_LOW 0x1d40
-#define MV64460_PCI_1_ERROR_ADDR_LOW 0x1dc0
-#define MV64460_PCI_0_ERROR_ADDR_HIGH 0x1d44
-#define MV64460_PCI_1_ERROR_ADDR_HIGH 0x1dc4
-#define MV64460_PCI_0_ERROR_ATTRIBUTE 0x1d48
-#define MV64460_PCI_1_ERROR_ATTRIBUTE 0x1dc8
-#define MV64460_PCI_0_ERROR_COMMAND 0x1d50
-#define MV64460_PCI_1_ERROR_COMMAND 0x1dd0
-#define MV64460_PCI_0_ERROR_CAUSE 0x1d58
-#define MV64460_PCI_1_ERROR_CAUSE 0x1dd8
-#define MV64460_PCI_0_ERROR_MASK 0x1d5c
-#define MV64460_PCI_1_ERROR_MASK 0x1ddc
-
-/****************************************/
-/* PCI Debug Registers */
-/****************************************/
-
-#define MV64460_PCI_0_MMASK 0X1D24
-#define MV64460_PCI_1_MMASK 0X1DA4
-
-/*********************************************/
-/* PCI Configuration, Function 0, Registers */
-/*********************************************/
-
-#define MV64460_PCI_DEVICE_AND_VENDOR_ID 0x000
-#define MV64460_PCI_STATUS_AND_COMMAND 0x004
-#define MV64460_PCI_CLASS_CODE_AND_REVISION_ID 0x008
-#define MV64460_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
-
-#define MV64460_PCI_SCS_0_BASE_ADDR_LOW 0x010
-#define MV64460_PCI_SCS_0_BASE_ADDR_HIGH 0x014
-#define MV64460_PCI_SCS_1_BASE_ADDR_LOW 0x018
-#define MV64460_PCI_SCS_1_BASE_ADDR_HIGH 0x01C
-#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020
-#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024
-#define MV64460_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c
-#define MV64460_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030
-#define MV64460_PCI_CAPABILTY_LIST_POINTER 0x034
-#define MV64460_PCI_INTERRUPT_PIN_AND_LINE 0x03C
- /* capability list */
-#define MV64460_PCI_POWER_MANAGEMENT_CAPABILITY 0x040
-#define MV64460_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
-#define MV64460_PCI_VPD_ADDR 0x048
-#define MV64460_PCI_VPD_DATA 0x04c
-#define MV64460_PCI_MSI_MESSAGE_CONTROL 0x050
-#define MV64460_PCI_MSI_MESSAGE_ADDR 0x054
-#define MV64460_PCI_MSI_MESSAGE_UPPER_ADDR 0x058
-#define MV64460_PCI_MSI_MESSAGE_DATA 0x05c
-#define MV64460_PCI_X_COMMAND 0x060
-#define MV64460_PCI_X_STATUS 0x064
-#define MV64460_PCI_COMPACT_PCI_HOT_SWAP 0x068
-
-/***********************************************/
-/* PCI Configuration, Function 1, Registers */
-/***********************************************/
-
-#define MV64460_PCI_SCS_2_BASE_ADDR_LOW 0x110
-#define MV64460_PCI_SCS_2_BASE_ADDR_HIGH 0x114
-#define MV64460_PCI_SCS_3_BASE_ADDR_LOW 0x118
-#define MV64460_PCI_SCS_3_BASE_ADDR_HIGH 0x11c
-#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120
-#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124
-
-/***********************************************/
-/* PCI Configuration, Function 2, Registers */
-/***********************************************/
-
-#define MV64460_PCI_DEVCS_0_BASE_ADDR_LOW 0x210
-#define MV64460_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214
-#define MV64460_PCI_DEVCS_1_BASE_ADDR_LOW 0x218
-#define MV64460_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c
-#define MV64460_PCI_DEVCS_2_BASE_ADDR_LOW 0x220
-#define MV64460_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224
-
-/***********************************************/
-/* PCI Configuration, Function 3, Registers */
-/***********************************************/
-
-#define MV64460_PCI_DEVCS_3_BASE_ADDR_LOW 0x310
-#define MV64460_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314
-#define MV64460_PCI_BOOT_CS_BASE_ADDR_LOW 0x318
-#define MV64460_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c
-#define MV64460_PCI_CPU_BASE_ADDR_LOW 0x220
-#define MV64460_PCI_CPU_BASE_ADDR_HIGH 0x224
-
-/***********************************************/
-/* PCI Configuration, Function 4, Registers */
-/***********************************************/
-
-#define MV64460_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410
-#define MV64460_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414
-#define MV64460_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418
-#define MV64460_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c
-#define MV64460_PCI_P2P_I_O_BASE_ADDR 0x420
-#define MV64460_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424
-
-/****************************************/
-/* Messaging Unit Registers (I20) */
-/****************************************/
-
-#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010
-#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C
-#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020
-#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024
-#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028
-#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C
-#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030
-#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034
-#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040
-#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044
-#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050
-#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054
-#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060
-#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064
-#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068
-#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C
-#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070
-#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074
-#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8
-#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC
-
-#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090
-#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C
-#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0
-#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4
-#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8
-#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC
-#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0
-#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4
-#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0
-#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4
-#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0
-#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4
-#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0
-#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4
-#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8
-#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC
-#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0
-#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4
-#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078
-#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C
-
-#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10
-#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C
-#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20
-#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24
-#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28
-#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C
-#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30
-#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34
-#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40
-#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44
-#define MV64460_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50
-#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54
-#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60
-#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64
-#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68
-#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C
-#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70
-#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74
-#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8
-#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC
-#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90
-#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C
-#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0
-#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4
-#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8
-#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC
-#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0
-#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4
-#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0
-#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4
-#define MV64460_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0
-#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4
-#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0
-#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4
-#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8
-#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC
-#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0
-#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4
-#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78
-#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C
-
-/****************************************/
-/* Ethernet Unit Registers */
-/****************************************/
-
-#define MV64460_ETH_PHY_ADDR_REG 0x2000
-#define MV64460_ETH_SMI_REG 0x2004
-#define MV64460_ETH_UNIT_DEFAULT_ADDR_REG 0x2008
-#define MV64460_ETH_UNIT_DEFAULTID_REG 0x200c
-#define MV64460_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080
-#define MV64460_ETH_UNIT_INTERRUPT_MASK_REG 0x2084
-#define MV64460_ETH_UNIT_INTERNAL_USE_REG 0x24fc
-#define MV64460_ETH_UNIT_ERROR_ADDR_REG 0x2094
-#define MV64460_ETH_BAR_0 0x2200
-#define MV64460_ETH_BAR_1 0x2208
-#define MV64460_ETH_BAR_2 0x2210
-#define MV64460_ETH_BAR_3 0x2218
-#define MV64460_ETH_BAR_4 0x2220
-#define MV64460_ETH_BAR_5 0x2228
-#define MV64460_ETH_SIZE_REG_0 0x2204
-#define MV64460_ETH_SIZE_REG_1 0x220c
-#define MV64460_ETH_SIZE_REG_2 0x2214
-#define MV64460_ETH_SIZE_REG_3 0x221c
-#define MV64460_ETH_SIZE_REG_4 0x2224
-#define MV64460_ETH_SIZE_REG_5 0x222c
-#define MV64460_ETH_HEADERS_RETARGET_BASE_REG 0x2230
-#define MV64460_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234
-#define MV64460_ETH_HIGH_ADDR_REMAP_REG_0 0x2280
-#define MV64460_ETH_HIGH_ADDR_REMAP_REG_1 0x2284
-#define MV64460_ETH_HIGH_ADDR_REMAP_REG_2 0x2288
-#define MV64460_ETH_HIGH_ADDR_REMAP_REG_3 0x228c
-#define MV64460_ETH_BASE_ADDR_ENABLE_REG 0x2290
-#define MV64460_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2))
-#define MV64460_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7))
-#define MV64460_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10))
-#define MV64460_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10))
-#define MV64460_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10))
-#define MV64460_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10))
-#define MV64460_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10))
-#define MV64460_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10))
-#define MV64460_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10))
-#define MV64460_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10))
-#define MV64460_ETH_DSCP_0(port) (0x2420 + (port<<10))
-#define MV64460_ETH_DSCP_1(port) (0x2424 + (port<<10))
-#define MV64460_ETH_DSCP_2(port) (0x2428 + (port<<10))
-#define MV64460_ETH_DSCP_3(port) (0x242c + (port<<10))
-#define MV64460_ETH_DSCP_4(port) (0x2430 + (port<<10))
-#define MV64460_ETH_DSCP_5(port) (0x2434 + (port<<10))
-#define MV64460_ETH_DSCP_6(port) (0x2438 + (port<<10))
-#define MV64460_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10))
-#define MV64460_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10))
-#define MV64460_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10))
-#define MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10))
-#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10))
-#define MV64460_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10))
-#define MV64460_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10))
-#define MV64460_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10))
-#define MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10))
-#define MV64460_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10))
-#define MV64460_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10))
-#define MV64460_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
-#define MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
-#define MV64460_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
-#define MV64460_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10)
-#define MV64460_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
-#define MV64460_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
-#define MV64460_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
-#define MV64460_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10))
-#define MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10))
-#define MV64460_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10))
-#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10))
-#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10))
-#define MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10))
-#define MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
-#define MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
-
-/*******************************************/
-/* CUNIT Registers */
-/*******************************************/
-
- /* Address Decoding Register Map */
-
-#define MV64460_CUNIT_BASE_ADDR_REG0 0xf200
-#define MV64460_CUNIT_BASE_ADDR_REG1 0xf208
-#define MV64460_CUNIT_BASE_ADDR_REG2 0xf210
-#define MV64460_CUNIT_BASE_ADDR_REG3 0xf218
-#define MV64460_CUNIT_SIZE0 0xf204
-#define MV64460_CUNIT_SIZE1 0xf20c
-#define MV64460_CUNIT_SIZE2 0xf214
-#define MV64460_CUNIT_SIZE3 0xf21c
-#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240
-#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244
-#define MV64460_CUNIT_BASE_ADDR_ENABLE_REG 0xf250
-#define MV64460_MPSC0_ACCESS_PROTECTION_REG 0xf254
-#define MV64460_MPSC1_ACCESS_PROTECTION_REG 0xf258
-#define MV64460_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C
-
- /* Error Report Registers */
-
-#define MV64460_CUNIT_INTERRUPT_CAUSE_REG 0xf310
-#define MV64460_CUNIT_INTERRUPT_MASK_REG 0xf314
-#define MV64460_CUNIT_ERROR_ADDR 0xf318
-
- /* Cunit Control Registers */
-
-#define MV64460_CUNIT_ARBITER_CONTROL_REG 0xf300
-#define MV64460_CUNIT_CONFIG_REG 0xb40c
-#define MV64460_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304
-
- /* Cunit Debug Registers */
-
-#define MV64460_CUNIT_DEBUG_LOW 0xf340
-#define MV64460_CUNIT_DEBUG_HIGH 0xf344
-#define MV64460_CUNIT_MMASK 0xf380
-
- /* Cunit Base Address Enable Window Bits*/
-#define MV64460_CUNIT_BASE_ADDR_WIN_0_BIT 0x0
-#define MV64460_CUNIT_BASE_ADDR_WIN_1_BIT 0x1
-#define MV64460_CUNIT_BASE_ADDR_WIN_2_BIT 0x2
-#define MV64460_CUNIT_BASE_ADDR_WIN_3_BIT 0x3
-
- /* MPSCs Clocks Routing Registers */
-
-#define MV64460_MPSC_ROUTING_REG 0xb400
-#define MV64460_MPSC_RX_CLOCK_ROUTING_REG 0xb404
-#define MV64460_MPSC_TX_CLOCK_ROUTING_REG 0xb408
-
- /* MPSCs Interrupts Registers */
-
-#define MV64460_MPSC_CAUSE_REG(port) (0xb804 + (port<<3))
-#define MV64460_MPSC_MASK_REG(port) (0xb884 + (port<<3))
-
-#define MV64460_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12))
-#define MV64460_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12))
-#define MV64460_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12))
-
- /* MPSC0 Registers */
-
-
-/***************************************/
-/* SDMA Registers */
-/***************************************/
-
-#define MV64460_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13))
-#define MV64460_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13))
-#define MV64460_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13))
-#define MV64460_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13))
-#define MV64460_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13))
-
-#define MV64460_SDMA_CAUSE_REG 0xb800
-#define MV64460_SDMA_MASK_REG 0xb880
-
-
-/****************************************/
-/* SDMA Address Space Targets */
-/****************************************/
-
-#define MV64460_SDMA_DRAM_CS_0_TARGET 0x0e00
-#define MV64460_SDMA_DRAM_CS_1_TARGET 0x0d00
-#define MV64460_SDMA_DRAM_CS_2_TARGET 0x0b00
-#define MV64460_SDMA_DRAM_CS_3_TARGET 0x0700
-
-#define MV64460_SDMA_DEV_CS_0_TARGET 0x1e01
-#define MV64460_SDMA_DEV_CS_1_TARGET 0x1d01
-#define MV64460_SDMA_DEV_CS_2_TARGET 0x1b01
-#define MV64460_SDMA_DEV_CS_3_TARGET 0x1701
-
-#define MV64460_SDMA_BOOT_CS_TARGET 0x0f00
-
-#define MV64460_SDMA_SRAM_TARGET 0x0003
-#define MV64460_SDMA_60X_BUS_TARGET 0x4003
-
-#define MV64460_PCI_0_TARGET 0x0003
-#define MV64460_PCI_1_TARGET 0x0004
-
-
-/* Devices BAR and size registers */
-
-#define MV64460_DEV_CS0_BASE_ADDR 0x028
-#define MV64460_DEV_CS0_SIZE 0x030
-#define MV64460_DEV_CS1_BASE_ADDR 0x228
-#define MV64460_DEV_CS1_SIZE 0x230
-#define MV64460_DEV_CS2_BASE_ADDR 0x248
-#define MV64460_DEV_CS2_SIZE 0x250
-#define MV64460_DEV_CS3_BASE_ADDR 0x038
-#define MV64460_DEV_CS3_SIZE 0x040
-#define MV64460_BOOTCS_BASE_ADDR 0x238
-#define MV64460_BOOTCS_SIZE 0x240
-
-/* SDMA Window access protection */
-#define MV64460_SDMA_WIN_ACCESS_NOT_ALLOWED 0
-#define MV64460_SDMA_WIN_ACCESS_READ_ONLY 1
-#define MV64460_SDMA_WIN_ACCESS_FULL 2
-
-/* BRG Interrupts */
-
-#define MV64460_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3))
-#define MV64460_BRG_BAUDE_TUNING_REG(brg) (0xb204 + (brg<<3))
-#define MV64460_BRG_CAUSE_REG 0xb834
-#define MV64460_BRG_MASK_REG 0xb8b4
-
-/****************************************/
-/* DMA Channel Control */
-/****************************************/
-
-#define MV64460_DMA_CHANNEL0_CONTROL 0x840
-#define MV64460_DMA_CHANNEL0_CONTROL_HIGH 0x880
-#define MV64460_DMA_CHANNEL1_CONTROL 0x844
-#define MV64460_DMA_CHANNEL1_CONTROL_HIGH 0x884
-#define MV64460_DMA_CHANNEL2_CONTROL 0x848
-#define MV64460_DMA_CHANNEL2_CONTROL_HIGH 0x888
-#define MV64460_DMA_CHANNEL3_CONTROL 0x84C
-#define MV64460_DMA_CHANNEL3_CONTROL_HIGH 0x88C
-
-
-/****************************************/
-/* IDMA Registers */
-/****************************************/
-
-#define MV64460_DMA_CHANNEL0_BYTE_COUNT 0x800
-#define MV64460_DMA_CHANNEL1_BYTE_COUNT 0x804
-#define MV64460_DMA_CHANNEL2_BYTE_COUNT 0x808
-#define MV64460_DMA_CHANNEL3_BYTE_COUNT 0x80C
-#define MV64460_DMA_CHANNEL0_SOURCE_ADDR 0x810
-#define MV64460_DMA_CHANNEL1_SOURCE_ADDR 0x814
-#define MV64460_DMA_CHANNEL2_SOURCE_ADDR 0x818
-#define MV64460_DMA_CHANNEL3_SOURCE_ADDR 0x81c
-#define MV64460_DMA_CHANNEL0_DESTINATION_ADDR 0x820
-#define MV64460_DMA_CHANNEL1_DESTINATION_ADDR 0x824
-#define MV64460_DMA_CHANNEL2_DESTINATION_ADDR 0x828
-#define MV64460_DMA_CHANNEL3_DESTINATION_ADDR 0x82C
-#define MV64460_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830
-#define MV64460_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834
-#define MV64460_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838
-#define MV64460_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C
-#define MV64460_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870
-#define MV64460_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874
-#define MV64460_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878
-#define MV64460_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C
-
- /* IDMA Address Decoding Base Address Registers */
-
-#define MV64460_DMA_BASE_ADDR_REG0 0xa00
-#define MV64460_DMA_BASE_ADDR_REG1 0xa08
-#define MV64460_DMA_BASE_ADDR_REG2 0xa10
-#define MV64460_DMA_BASE_ADDR_REG3 0xa18
-#define MV64460_DMA_BASE_ADDR_REG4 0xa20
-#define MV64460_DMA_BASE_ADDR_REG5 0xa28
-#define MV64460_DMA_BASE_ADDR_REG6 0xa30
-#define MV64460_DMA_BASE_ADDR_REG7 0xa38
-
- /* IDMA Address Decoding Size Address Register */
-
-#define MV64460_DMA_SIZE_REG0 0xa04
-#define MV64460_DMA_SIZE_REG1 0xa0c
-#define MV64460_DMA_SIZE_REG2 0xa14
-#define MV64460_DMA_SIZE_REG3 0xa1c
-#define MV64460_DMA_SIZE_REG4 0xa24
-#define MV64460_DMA_SIZE_REG5 0xa2c
-#define MV64460_DMA_SIZE_REG6 0xa34
-#define MV64460_DMA_SIZE_REG7 0xa3C
-
- /* IDMA Address Decoding High Address Remap and Access
- Protection Registers */
-
-#define MV64460_DMA_HIGH_ADDR_REMAP_REG0 0xa60
-#define MV64460_DMA_HIGH_ADDR_REMAP_REG1 0xa64
-#define MV64460_DMA_HIGH_ADDR_REMAP_REG2 0xa68
-#define MV64460_DMA_HIGH_ADDR_REMAP_REG3 0xa6C
-#define MV64460_DMA_BASE_ADDR_ENABLE_REG 0xa80
-#define MV64460_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70
-#define MV64460_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74
-#define MV64460_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78
-#define MV64460_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c
-#define MV64460_DMA_ARBITER_CONTROL 0x860
-#define MV64460_DMA_CROSS_BAR_TIMEOUT 0x8d0
-
- /* IDMA Headers Retarget Registers */
-
-#define MV64460_DMA_HEADERS_RETARGET_CONTROL 0xa84
-#define MV64460_DMA_HEADERS_RETARGET_BASE 0xa88
-
- /* IDMA Interrupt Register */
-
-#define MV64460_DMA_INTERRUPT_CAUSE_REG 0x8c0
-#define MV64460_DMA_INTERRUPT_CAUSE_MASK 0x8c4
-#define MV64460_DMA_ERROR_ADDR 0x8c8
-#define MV64460_DMA_ERROR_SELECT 0x8cc
-
- /* IDMA Debug Register ( for internal use ) */
-
-#define MV64460_DMA_DEBUG_LOW 0x8e0
-#define MV64460_DMA_DEBUG_HIGH 0x8e4
-#define MV64460_DMA_SPARE 0xA8C
-
-/****************************************/
-/* Timer_Counter */
-/****************************************/
-
-#define MV64460_TIMER_COUNTER0 0x850
-#define MV64460_TIMER_COUNTER1 0x854
-#define MV64460_TIMER_COUNTER2 0x858
-#define MV64460_TIMER_COUNTER3 0x85C
-#define MV64460_TIMER_COUNTER_0_3_CONTROL 0x864
-#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868
-#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c
-
-/****************************************/
-/* Watchdog registers */
-/****************************************/
-
-#define MV64460_WATCHDOG_CONFIG_REG 0xb410
-#define MV64460_WATCHDOG_VALUE_REG 0xb414
-
-/****************************************/
-/* I2C Registers */
-/****************************************/
-
-#define MV64460_I2C_SLAVE_ADDR 0xc000
-#define MV64460_I2C_EXTENDED_SLAVE_ADDR 0xc010
-#define MV64460_I2C_DATA 0xc004
-#define MV64460_I2C_CONTROL 0xc008
-#define MV64460_I2C_STATUS_BAUDE_RATE 0xc00C
-#define MV64460_I2C_SOFT_RESET 0xc01c
-
-/****************************************/
-/* GPP Interface Registers */
-/****************************************/
-
-#define MV64460_GPP_IO_CONTROL 0xf100
-#define MV64460_GPP_LEVEL_CONTROL 0xf110
-#define MV64460_GPP_VALUE 0xf104
-#define MV64460_GPP_INTERRUPT_CAUSE 0xf108
-#define MV64460_GPP_INTERRUPT_MASK0 0xf10c
-#define MV64460_GPP_INTERRUPT_MASK1 0xf114
-#define MV64460_GPP_VALUE_SET 0xf118
-#define MV64460_GPP_VALUE_CLEAR 0xf11c
-
-/****************************************/
-/* Interrupt Controller Registers */
-/****************************************/
-
-/****************************************/
-/* Interrupts */
-/****************************************/
-
-#define MV64460_MAIN_INTERRUPT_CAUSE_LOW 0x004
-#define MV64460_MAIN_INTERRUPT_CAUSE_HIGH 0x00c
-#define MV64460_CPU_INTERRUPT0_MASK_LOW 0x014
-#define MV64460_CPU_INTERRUPT0_MASK_HIGH 0x01c
-#define MV64460_CPU_INTERRUPT0_SELECT_CAUSE 0x024
-#define MV64460_CPU_INTERRUPT1_MASK_LOW 0x034
-#define MV64460_CPU_INTERRUPT1_MASK_HIGH 0x03c
-#define MV64460_CPU_INTERRUPT1_SELECT_CAUSE 0x044
-#define MV64460_INTERRUPT0_MASK_0_LOW 0x054
-#define MV64460_INTERRUPT0_MASK_0_HIGH 0x05c
-#define MV64460_INTERRUPT0_SELECT_CAUSE 0x064
-#define MV64460_INTERRUPT1_MASK_0_LOW 0x074
-#define MV64460_INTERRUPT1_MASK_0_HIGH 0x07c
-#define MV64460_INTERRUPT1_SELECT_CAUSE 0x084
-
-/****************************************/
-/* MPP Interface Registers */
-/****************************************/
-
-#define MV64460_MPP_CONTROL0 0xf000
-#define MV64460_MPP_CONTROL1 0xf004
-#define MV64460_MPP_CONTROL2 0xf008
-#define MV64460_MPP_CONTROL3 0xf00c
-
-/****************************************/
-/* Serial Initialization registers */
-/****************************************/
-
-#define MV64460_SERIAL_INIT_LAST_DATA 0xf324
-#define MV64460_SERIAL_INIT_CONTROL 0xf328
-#define MV64460_SERIAL_INIT_STATUS 0xf32c
-
-
-#endif /* __INCgt64460rh */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-/* PCI.c - PCI functions */
-
-
-#include <common.h>
-#include <pci.h>
-
-#include "../include/pci.h"
-
-#undef DEBUG
-#undef IDE_SET_NATIVE_MODE
-static unsigned int local_buses[] = { 0, 0 };
-
-static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
- {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
- {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
-};
-
-
-#ifdef DEBUG
-static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
-static void gt_pci_bus_mode_display (PCI_HOST host)
-{
- unsigned int mode;
-
-
- mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
- switch (mode) {
- case 0:
- printf ("PCI %d bus mode: Conventional PCI\n", host);
- break;
- case 1:
- printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
- break;
- case 2:
- printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
- break;
- case 3:
- printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
- break;
- default:
- printf ("Unknown BUS %d\n", mode);
- }
-}
-#endif
-
-static const unsigned int pci_p2p_configuration_reg[] = {
- PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
-};
-
-static const unsigned int pci_configuration_address[] = {
- PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
-};
-
-static const unsigned int pci_configuration_data[] = {
- PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
- PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
-};
-
-static const unsigned int pci_error_cause_reg[] = {
- PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
-};
-
-static const unsigned int pci_arbiter_control[] = {
- PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
-};
-
-static const unsigned int pci_address_space_en[] = {
- PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
-};
-
-static const unsigned int pci_snoop_control_base_0_low[] = {
- PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
-};
-static const unsigned int pci_snoop_control_top_0[] = {
- PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
-};
-
-static const unsigned int pci_access_control_base_0_low[] = {
- PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
-};
-static const unsigned int pci_access_control_top_0[] = {
- PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
-};
-
-static const unsigned int pci_scs_bank_size[2][4] = {
- {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
- PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
- {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
- PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
-};
-
-static const unsigned int pci_p2p_configuration[] = {
- PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
-};
-
-
-/********************************************************************
-* pciWriteConfigReg - Write to a PCI configuration register
-* - Make sure the GT is configured as a master before writing
-* to another device on the PCI.
-* - The function takes care of Big/Little endian conversion.
-*
-*
-* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec
-* (or any other PCI device spec)
-* pciDevNum: The device number needs to be addressed.
-*
-* Configuration Address 0xCF8:
-*
-* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
-* |congif|Reserved| Bus |Device|Function|Register|00|
-* |Enable| |Number|Number| Number | Number | | <=field Name
-*
-*********************************************************************/
-void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
- unsigned int pciDevNum, unsigned int data)
-{
- volatile unsigned int DataForAddrReg;
- unsigned int functionNum;
- unsigned int busNum = 0;
- unsigned int addr;
-
- if (pciDevNum > 32) /* illegal device Number */
- return;
- if (pciDevNum == SELF) { /* configure our configuration space. */
- pciDevNum =
- (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
- 0x1f;
- busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
- 0xff0000;
- }
- functionNum = regOffset & 0x00000700;
- pciDevNum = pciDevNum << 11;
- regOffset = regOffset & 0xfc;
- DataForAddrReg =
- (regOffset | pciDevNum | functionNum | busNum) | BIT31;
- GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
- GT_REG_READ (pci_configuration_address[host], &addr);
- if (addr != DataForAddrReg)
- return;
- GT_REG_WRITE (pci_configuration_data[host], data);
-}
-
-/********************************************************************
-* pciReadConfigReg - Read from a PCI0 configuration register
-* - Make sure the GT is configured as a master before reading
-* from another device on the PCI.
-* - The function takes care of Big/Little endian conversion.
-* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
-* spec)
-* pciDevNum: The device number needs to be addressed.
-* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
-* cause register to make sure the data is valid
-*
-* Configuration Address 0xCF8:
-*
-* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
-* |congif|Reserved| Bus |Device|Function|Register|00|
-* |Enable| |Number|Number| Number | Number | | <=field Name
-*
-*********************************************************************/
-unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
- unsigned int pciDevNum)
-{
- volatile unsigned int DataForAddrReg;
- unsigned int data;
- unsigned int functionNum;
- unsigned int busNum = 0;
-
- if (pciDevNum > 32) /* illegal device Number */
- return 0xffffffff;
- if (pciDevNum == SELF) { /* configure our configuration space. */
- pciDevNum =
- (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
- 0x1f;
- busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
- 0xff0000;
- }
- functionNum = regOffset & 0x00000700;
- pciDevNum = pciDevNum << 11;
- regOffset = regOffset & 0xfc;
- DataForAddrReg =
- (regOffset | pciDevNum | functionNum | busNum) | BIT31;
- GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
- GT_REG_READ (pci_configuration_address[host], &data);
- if (data != DataForAddrReg)
- return 0xffffffff;
- GT_REG_READ (pci_configuration_data[host], &data);
- return data;
-}
-
-/********************************************************************
-* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
-* the agent is placed on another Bus. For more
-* information read P2P in the PCI spec.
-*
-* Inputs: unsigned int regOffset - The register offset as it apears in the
-* GT spec (or any other PCI device spec).
-* unsigned int pciDevNum - The device number needs to be addressed.
-* unsigned int busNum - On which bus does the Target agent connect
-* to.
-* unsigned int data - data to be written.
-*
-* Configuration Address 0xCF8:
-*
-* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
-* |congif|Reserved| Bus |Device|Function|Register|01|
-* |Enable| |Number|Number| Number | Number | | <=field Name
-*
-* The configuration Address is configure as type-I (bits[1:0] = '01') due to
-* PCI spec referring to P2P.
-*
-*********************************************************************/
-void pciOverBridgeWriteConfigReg (PCI_HOST host,
- unsigned int regOffset,
- unsigned int pciDevNum,
- unsigned int busNum, unsigned int data)
-{
- unsigned int DataForReg;
- unsigned int functionNum;
-
- functionNum = regOffset & 0x00000700;
- pciDevNum = pciDevNum << 11;
- regOffset = regOffset & 0xff;
- busNum = busNum << 16;
- if (pciDevNum == SELF) { /* This board */
- DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
- } else {
- DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
- BIT31 | BIT0;
- }
- GT_REG_WRITE (pci_configuration_address[host], DataForReg);
- GT_REG_WRITE (pci_configuration_data[host], data);
-}
-
-
-/********************************************************************
-* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where
-* the agent target locate on another PCI bus.
-* - Make sure the GT is configured as a master
-* before reading from another device on the PCI.
-* - The function takes care of Big/Little endian
-* conversion.
-* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
-* spec). (configuration register offset.)
-* pciDevNum: The device number needs to be addressed.
-* busNum: the Bus number where the agent is place.
-* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
-* cause register to make sure the data is valid
-*
-* Configuration Address 0xCF8:
-*
-* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
-* |congif|Reserved| Bus |Device|Function|Register|01|
-* |Enable| |Number|Number| Number | Number | | <=field Name
-*
-*********************************************************************/
-unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
- unsigned int regOffset,
- unsigned int pciDevNum,
- unsigned int busNum)
-{
- unsigned int DataForReg;
- unsigned int data;
- unsigned int functionNum;
-
- functionNum = regOffset & 0x00000700;
- pciDevNum = pciDevNum << 11;
- regOffset = regOffset & 0xff;
- busNum = busNum << 16;
- if (pciDevNum == SELF) { /* This board */
- DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
- } else { /* agent on another bus */
-
- DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
- BIT0 | BIT31;
- }
- GT_REG_WRITE (pci_configuration_address[host], DataForReg);
- GT_REG_READ (pci_configuration_data[host], &data);
- return data;
-}
-
-
-/********************************************************************
-* pciGetRegOffset - Gets the register offset for this region config.
-*
-* INPUT: Bus, Region - The bus and region we ask for its base address.
-* OUTPUT: N/A
-* RETURNS: PCI register base address
-*********************************************************************/
-static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
-{
- switch (host) {
- case PCI_HOST0:
- switch (region) {
- case PCI_IO:
- return PCI_0I_O_LOW_DECODE_ADDRESS;
- case PCI_REGION0:
- return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
- case PCI_REGION1:
- return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
- case PCI_REGION2:
- return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
- case PCI_REGION3:
- return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
- }
- case PCI_HOST1:
- switch (region) {
- case PCI_IO:
- return PCI_1I_O_LOW_DECODE_ADDRESS;
- case PCI_REGION0:
- return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
- case PCI_REGION1:
- return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
- case PCI_REGION2:
- return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
- case PCI_REGION3:
- return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
- }
- }
- return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
-}
-
-static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
-{
- switch (host) {
- case PCI_HOST0:
- switch (region) {
- case PCI_IO:
- return PCI_0I_O_ADDRESS_REMAP;
- case PCI_REGION0:
- return PCI_0MEMORY0_ADDRESS_REMAP;
- case PCI_REGION1:
- return PCI_0MEMORY1_ADDRESS_REMAP;
- case PCI_REGION2:
- return PCI_0MEMORY2_ADDRESS_REMAP;
- case PCI_REGION3:
- return PCI_0MEMORY3_ADDRESS_REMAP;
- }
- case PCI_HOST1:
- switch (region) {
- case PCI_IO:
- return PCI_1I_O_ADDRESS_REMAP;
- case PCI_REGION0:
- return PCI_1MEMORY0_ADDRESS_REMAP;
- case PCI_REGION1:
- return PCI_1MEMORY1_ADDRESS_REMAP;
- case PCI_REGION2:
- return PCI_1MEMORY2_ADDRESS_REMAP;
- case PCI_REGION3:
- return PCI_1MEMORY3_ADDRESS_REMAP;
- }
- }
- return PCI_0MEMORY0_ADDRESS_REMAP;
-}
-
-/********************************************************************
-* pciGetBaseAddress - Gets the base address of a PCI.
-* - If the PCI size is 0 then this base address has no meaning!!!
-*
-*
-* INPUT: Bus, Region - The bus and region we ask for its base address.
-* OUTPUT: N/A
-* RETURNS: PCI base address.
-*********************************************************************/
-unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
-{
- unsigned int regBase;
- unsigned int regEnd;
- unsigned int regOffset = pciGetRegOffset (host, region);
-
- GT_REG_READ (regOffset, ®Base);
- GT_REG_READ (regOffset + 8, ®End);
-
- if (regEnd <= regBase)
- return 0xffffffff; /* ERROR !!! */
-
- regBase = regBase << 16;
- return regBase;
-}
-
-bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
- unsigned int bankBase, unsigned int bankLength)
-{
- unsigned int low = 0xfff;
- unsigned int high = 0x0;
- unsigned int regOffset = pciGetRegOffset (host, region);
- unsigned int remapOffset = pciGetRemapOffset (host, region);
-
- if (bankLength != 0) {
- low = (bankBase >> 16) & 0xffff;
- high = ((bankBase + bankLength) >> 16) - 1;
- }
-
- GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */
- GT_REG_WRITE (regOffset + 8, high);
-
- if (bankLength != 0) { /* must do AFTER writing maps */
- GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only.
- dont support upper 32
- in this driver */
- }
- return true;
-}
-
-unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
-{
- unsigned int low;
- unsigned int regOffset = pciGetRegOffset (host, region);
-
- GT_REG_READ (regOffset, &low);
- return (low & 0xffff) << 16;
-}
-
-unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
-{
- unsigned int low, high;
- unsigned int regOffset = pciGetRegOffset (host, region);
-
- GT_REG_READ (regOffset, &low);
- GT_REG_READ (regOffset + 8, &high);
- return ((high & 0xffff) + 1) << 16;
-}
-
-
-/* ronen - 7/Dec/03*/
-/********************************************************************
-* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
-* Inputs: one of the PCI BAR
-*********************************************************************/
-void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
-{
- RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
-}
-
-void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
-{
- SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
-}
-
-/********************************************************************
-* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
-*
-* Inputs: base and size of PCI SCS
-*********************************************************************/
-void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
- unsigned int pciDramBase, unsigned int pciDramSize)
-{
- /*ronen different function for 3rd bank. */
- unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
-
- pciDramBase = pciDramBase & 0xfffff000;
- pciDramBase = pciDramBase | (pciReadConfigReg (host,
- PCI_SCS_0_BASE_ADDRESS
- + offset,
- SELF) & 0x00000fff);
- pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
- pciDramBase);
- if (pciDramSize == 0)
- pciDramSize++;
- GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
- gtPciEnableInternalBAR (host, bank);
-}
-
-/********************************************************************
-* pciSetRegionFeatures - This function modifys one of the 8 regions with
-* feature bits given as an input.
-* - Be advised to check the spec before modifying them.
-* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
-* unsigned int features - See file: pci.h there are defintion for those
-* region features.
-* unsigned int baseAddress - The region base Address.
-* unsigned int topAddress - The region top Address.
-* Returns: false if one of the parameters is erroneous true otherwise.
-*********************************************************************/
-bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
- unsigned int features, unsigned int baseAddress,
- unsigned int regionLength)
-{
- unsigned int accessLow;
- unsigned int accessHigh;
- unsigned int accessTop = baseAddress + regionLength;
-
- if (regionLength == 0) { /* close the region. */
- pciDisableAccessRegion (host, region);
- return true;
- }
- /* base Address is store is bits [11:0] */
- accessLow = (baseAddress & 0xfff00000) >> 20;
- /* All the features are update according to the defines in pci.h (to be on
- the safe side we disable bits: [11:0] */
- accessLow = accessLow | (features & 0xfffff000);
- /* write to the Low Access Region register */
- GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
- accessLow);
-
- accessHigh = (accessTop & 0xfff00000) >> 20;
-
- /* write to the High Access Region register */
- GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
- accessHigh - 1);
- return true;
-}
-
-/********************************************************************
-* pciDisableAccessRegion - Disable The given Region by writing MAX size
-* to its low Address and MIN size to its high Address.
-*
-* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled.
-* Returns: N/A.
-*********************************************************************/
-void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
-{
- /* writing back the registers default values. */
- GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
- 0x01001fff);
- GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
-}
-
-/********************************************************************
-* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
-*
-* Inputs: N/A
-* Returns: true.
-*********************************************************************/
-bool pciArbiterEnable (PCI_HOST host)
-{
- unsigned int regData;
-
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
- return true;
-}
-
-/********************************************************************
-* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
-*
-* Inputs: N/A
-* Returns: true
-*********************************************************************/
-bool pciArbiterDisable (PCI_HOST host)
-{
- unsigned int regData;
-
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
- return true;
-}
-
-/********************************************************************
-* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
-*
-* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent.
-* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
-* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
-* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
-* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
-* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
-* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
-* Returns: true
-*********************************************************************/
-bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
- PCI_AGENT_PRIO externalAgent0,
- PCI_AGENT_PRIO externalAgent1,
- PCI_AGENT_PRIO externalAgent2,
- PCI_AGENT_PRIO externalAgent3,
- PCI_AGENT_PRIO externalAgent4,
- PCI_AGENT_PRIO externalAgent5)
-{
- unsigned int regData;
- unsigned int writeData;
-
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- writeData = (internalAgent << 7) + (externalAgent0 << 8) +
- (externalAgent1 << 9) + (externalAgent2 << 10) +
- (externalAgent3 << 11) + (externalAgent4 << 12) +
- (externalAgent5 << 13);
- regData = (regData & 0xffffc07f) | writeData;
- GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
- return true;
-}
-
-/********************************************************************
-* pciParkingDisable - Park on last option disable, with this function you can
-* disable the park on last mechanism for each agent.
-* disabling this option for all agents results parking
-* on the internal master.
-*
-* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent.
-* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
-* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
-* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
-* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
-* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
-* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
-* Returns: true
-*********************************************************************/
-bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
- PCI_AGENT_PARK externalAgent0,
- PCI_AGENT_PARK externalAgent1,
- PCI_AGENT_PARK externalAgent2,
- PCI_AGENT_PARK externalAgent3,
- PCI_AGENT_PARK externalAgent4,
- PCI_AGENT_PARK externalAgent5)
-{
- unsigned int regData;
- unsigned int writeData;
-
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- writeData = (internalAgent << 14) + (externalAgent0 << 15) +
- (externalAgent1 << 16) + (externalAgent2 << 17) +
- (externalAgent3 << 18) + (externalAgent4 << 19) +
- (externalAgent5 << 20);
- regData = (regData & ~(0x7f << 14)) | writeData;
- GT_REG_WRITE (pci_arbiter_control[host], regData);
- return true;
-}
-
-/********************************************************************
-* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
-* respond to grant assertion within a window specified in
-* the input value: 'brokenValue'.
-*
-* Inputs: unsigned char brokenValue - A value which limits the Master to hold the
-* grant without asserting frame.
-* Returns: Error for illegal broken value otherwise true.
-*********************************************************************/
-bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
-{
- unsigned int data;
- unsigned int regData;
-
- if (brokenValue > 0xf)
- return false; /* brokenValue must be 4 bit */
- data = brokenValue << 3;
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- regData = (regData & 0xffffff87) | data;
- GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
- return true;
-}
-
-/********************************************************************
-* pciDisableBrokenAgentDetection - This function disable the Broken agent
-* Detection mechanism.
-* NOTE: This operation may cause a dead lock on the
-* pci0 arbitration.
-*
-* Inputs: N/A
-* Returns: true.
-*********************************************************************/
-bool pciDisableBrokenAgentDetection (PCI_HOST host)
-{
- unsigned int regData;
-
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- regData = regData & 0xfffffffd;
- GT_REG_WRITE (pci_arbiter_control[host], regData);
- return true;
-}
-
-/********************************************************************
-* pciP2PConfig - This function set the PCI_n P2P configurate.
-* For more information on the P2P read PCI spec.
-*
-* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
-* Boundry.
-* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
-* Boundry.
-* unsigned int busNum - The CPI bus number to which the PCI interface
-* is connected.
-* unsigned int devNum - The PCI interface's device number.
-*
-* Returns: true.
-*********************************************************************/
-bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
- unsigned int SecondBusHigh,
- unsigned int busNum, unsigned int devNum)
-{
- unsigned int regData;
-
- regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
- ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
- GT_REG_WRITE (pci_p2p_configuration[host], regData);
- return true;
-}
-
-/********************************************************************
-* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
-* supports Cache Coherency in the PCI_n interface.
-* Inputs: region - One of the four regions.
-* snoopType - There is four optional Types:
-* 1. No Snoop.
-* 2. Snoop to WT region.
-* 3. Snoop to WB region.
-* 4. Snoop & Invalidate to WB region.
-* baseAddress - Base Address of this region.
-* regionLength - Region length.
-* Returns: false if one of the parameters is wrong otherwise return true.
-*********************************************************************/
-bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
- PCI_SNOOP_TYPE snoopType,
- unsigned int baseAddress,
- unsigned int regionLength)
-{
- unsigned int snoopXbaseAddress;
- unsigned int snoopXtopAddress;
- unsigned int data;
- unsigned int snoopHigh = baseAddress + regionLength;
-
- if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
- return false;
- snoopXbaseAddress =
- pci_snoop_control_base_0_low[host] + 0x10 * region;
- snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
- if (regionLength == 0) { /* closing the region */
- GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
- GT_REG_WRITE (snoopXtopAddress, 0);
- return true;
- }
- baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
- data = (baseAddress >> 20) | snoopType << 12;
- GT_REG_WRITE (snoopXbaseAddress, data);
- snoopHigh = (snoopHigh & 0xfff00000) >> 20;
- GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
- return true;
-}
-
-static int gt_read_config_dword (struct pci_controller *hose,
- pci_dev_t dev, int offset, u32 * value)
-{
- int bus = PCI_BUS (dev);
-
- if ((bus == local_buses[0]) || (bus == local_buses[1])) {
- *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
- PCI_DEV (dev));
- } else {
- *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
- cfg_addr, offset,
- PCI_DEV (dev), bus);
- }
-
- return 0;
-}
-
-static int gt_write_config_dword (struct pci_controller *hose,
- pci_dev_t dev, int offset, u32 value)
-{
- int bus = PCI_BUS (dev);
-
- if ((bus == local_buses[0]) || (bus == local_buses[1])) {
- pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
- PCI_DEV (dev), value);
- } else {
- pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
- offset, PCI_DEV (dev), bus,
- value);
- }
- return 0;
-}
-
-
-static void gt_setup_ide (struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *entry)
-{
- static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
- u32 bar_response, bar_value;
- int bar;
-
- for (bar = 0; bar < 6; bar++) {
- /*ronen different function for 3rd bank. */
- unsigned int offset =
- (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
-
- pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
- 0x0);
- pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
- &bar_response);
-
- pciauto_region_allocate (bar_response &
- PCI_BASE_ADDRESS_SPACE_IO ? hose->
- pci_io : hose->pci_mem, ide_bar[bar],
- &bar_value);
-
- pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
- bar_value);
- }
-}
-
-
-/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */
-/* and is curently not called *. */
-#if 0
-static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
-{
- unsigned char pin, irq;
-
- pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
-
- if (pin == 1) { /* only allow INT A */
- irq = pci_irq_swizzle[(PCI_HOST) hose->
- cfg_addr][PCI_DEV (dev)];
- if (irq)
- pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
- }
-}
-#endif
-
-struct pci_config_table gt_config_table[] = {
- {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
-
- {}
-};
-
-struct pci_controller pci0_hose = {
-/* fixup_irq: gt_fixup_irq, */
- config_table:gt_config_table,
-};
-
-struct pci_controller pci1_hose = {
-/* fixup_irq: gt_fixup_irq, */
- config_table:gt_config_table,
-};
-
-void pci_init_board (void)
-{
- unsigned int command;
-
-#ifdef DEBUG
- gt_pci_bus_mode_display (PCI_HOST0);
-#endif
-
- pci0_hose.first_busno = 0;
- pci0_hose.last_busno = 0xff;
- local_buses[0] = pci0_hose.first_busno;
-
- /* PCI memory space */
- pci_set_region (pci0_hose.regions + 0,
- CONFIG_SYS_PCI0_0_MEM_SPACE,
- CONFIG_SYS_PCI0_0_MEM_SPACE,
- CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region (pci0_hose.regions + 1,
- CONFIG_SYS_PCI0_IO_SPACE_PCI,
- CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
-
- pci_set_ops (&pci0_hose,
- pci_hose_read_config_byte_via_dword,
- pci_hose_read_config_word_via_dword,
- gt_read_config_dword,
- pci_hose_write_config_byte_via_dword,
- pci_hose_write_config_word_via_dword,
- gt_write_config_dword);
- pci0_hose.region_count = 2;
-
- pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
-
- pci_register_hose (&pci0_hose);
- pciArbiterEnable (PCI_HOST0);
- pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
- command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MASTER;
- pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
- command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MEMORY;
- pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
-
- pci0_hose.last_busno = pci_hose_scan (&pci0_hose);
-
-#ifdef DEBUG
- gt_pci_bus_mode_display (PCI_HOST1);
-#endif
- pci1_hose.first_busno = pci0_hose.last_busno + 1;
- pci1_hose.last_busno = 0xff;
- pci1_hose.current_busno = pci1_hose.first_busno;
- local_buses[1] = pci1_hose.first_busno;
-
- /* PCI memory space */
- pci_set_region (pci1_hose.regions + 0,
- CONFIG_SYS_PCI1_0_MEM_SPACE,
- CONFIG_SYS_PCI1_0_MEM_SPACE,
- CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region (pci1_hose.regions + 1,
- CONFIG_SYS_PCI1_IO_SPACE_PCI,
- CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
-
- pci_set_ops (&pci1_hose,
- pci_hose_read_config_byte_via_dword,
- pci_hose_read_config_word_via_dword,
- gt_read_config_dword,
- pci_hose_write_config_byte_via_dword,
- pci_hose_write_config_word_via_dword,
- gt_write_config_dword);
-
- pci1_hose.region_count = 2;
-
- pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
-
- pci_register_hose (&pci1_hose);
-
- pciArbiterEnable (PCI_HOST1);
- pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
-
- command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MASTER;
- pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
-
- pci1_hose.last_busno = pci_hose_scan (&pci1_hose);
-
- command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MEMORY;
- pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
-
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*************************************************************************
- * adaption for the Marvell DB64460 Board
- * Ingo Assmus (ingo.assmus@keymile.com)
- ************************************************************************/
-
-
-/* sdram_init.c - automatic memory sizing */
-
-#include <common.h>
-#include <74xx_7xx.h>
-#include "../include/memory.h"
-#include "../include/pci.h"
-#include "../include/mv_gen_reg.h"
-#include <net.h>
-
-#include "eth.h"
-#include "mpsc.h"
-#include "../common/i2c.h"
-#include "64460.h"
-#include "mv_regs.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define MAP_PCI
-
-int set_dfcdlInit (void); /* setup delay line of Mv64460 */
-int mvDmaIsChannelActive (int);
-int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong);
-int mvDmaTransfer (int, ulong, ulong, ulong, ulong);
-
-/* ------------------------------------------------------------------------- */
-
-int
-memory_map_bank (unsigned int bankNo,
- unsigned int bankBase, unsigned int bankLength)
-{
-#ifdef MAP_PCI
- PCI_HOST host;
-#endif
-
-
- if (bankLength > 0) {
- debug("mapping bank %d at %08x - %08x\n",
- bankNo, bankBase, bankBase + bankLength - 1);
- } else {
- debug("unmapping bank %d\n", bankNo);
- }
-
- memoryMapBank (bankNo, bankBase, bankLength);
-
-#ifdef MAP_PCI
- for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
- const int features =
- PREFETCH_ENABLE |
- DELAYED_READ_ENABLE |
- AGGRESSIVE_PREFETCH |
- READ_LINE_AGGRESSIVE_PREFETCH |
- READ_MULTI_AGGRESSIVE_PREFETCH |
- MAX_BURST_4 | PCI_NO_SWAP;
-
- pciMapMemoryBank (host, bankNo, bankBase, bankLength);
-
- pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
- bankLength);
-
- pciSetRegionFeatures (host, bankNo, features, bankBase,
- bankLength);
- }
-#endif
- return 0;
-}
-
-#define GB (1 << 30)
-
-/* much of this code is based on (or is) the code in the pip405 port */
-/* thanks go to the authors of said port - Josh */
-
-/* structure to store the relevant information about an sdram bank */
-typedef struct sdram_info {
- uchar drb_size;
- uchar registered, ecc;
- uchar tpar;
- uchar tras_clocks;
- uchar burst_len;
- uchar banks, slot;
-} sdram_info_t;
-
-/* Typedefs for 'gtAuxilGetDIMMinfo' function */
-
-typedef enum _memoryType { SDRAM, DDR } MEMORY_TYPE;
-
-typedef enum _voltageInterface { TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
- SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
-} VOLTAGE_INTERFACE;
-
-typedef enum _max_CL_supported_DDR { DDR_CL_1 = 1, DDR_CL_1_5 = 2, DDR_CL_2 =
- 4, DDR_CL_2_5 = 8, DDR_CL_3 = 16, DDR_CL_3_5 =
- 32, DDR_CL_FAULT } MAX_CL_SUPPORTED_DDR;
-typedef enum _max_CL_supported_SD { SD_CL_1 =
- 1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7,
- SD_FAULT } MAX_CL_SUPPORTED_SD;
-
-
-/* SDRAM/DDR information struct */
-typedef struct _gtMemoryDimmInfo {
- MEMORY_TYPE memoryType;
- unsigned int numOfRowAddresses;
- unsigned int numOfColAddresses;
- unsigned int numOfModuleBanks;
- unsigned int dataWidth;
- VOLTAGE_INTERFACE voltageInterface;
- unsigned int errorCheckType; /* ECC , PARITY.. */
- unsigned int sdramWidth; /* 4,8,16 or 32 */ ;
- unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */
- unsigned int minClkDelay;
- unsigned int burstLengthSupported;
- unsigned int numOfBanksOnEachDevice;
- unsigned int suportedCasLatencies;
- unsigned int RefreshInterval;
- unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */
- unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns) */
- MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
- MAX_CL_SUPPORTED_SD maxClSupported_SD;
- unsigned int moduleBankDensity;
- /* module attributes (true for yes) */
- bool bufferedAddrAndControlInputs;
- bool registeredAddrAndControlInputs;
- bool onCardPLL;
- bool bufferedDQMBinputs;
- bool registeredDQMBinputs;
- bool differentialClockInput;
- bool redundantRowAddressing;
-
- /* module general attributes */
- bool suportedAutoPreCharge;
- bool suportedPreChargeAll;
- bool suportedEarlyRasPreCharge;
- bool suportedWrite1ReadBurst;
- bool suported5PercentLowVCC;
- bool suported5PercentUpperVCC;
- /* module timing parameters */
- unsigned int minRasToCasDelay;
- unsigned int minRowActiveRowActiveDelay;
- unsigned int minRasPulseWidth;
- unsigned int minRowPrechargeTime; /* measured in ns */
-
- int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */
- int addrAndCommandSetupTime; /* (measured in ns/100) */
- int dataInputSetupTime; /* LoP left of point (measured in ns) */
- int dataInputHoldTime; /* LoP left of point (measured in ns) */
-/* tAC times for highest 2nd and 3rd highest CAS Latency values */
- unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */
- unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns) */
- unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */
- unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns) */
- unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */
- unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns) */
-
- unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */
- unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns) */
-
- unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */
- unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */
-
- unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */
- unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */
-
- /* Parameters calculated from
- the extracted DIMM information */
- unsigned int size;
- unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */
- unsigned int numberOfDevices;
- uchar drb_size; /* DRAM size in n*64Mbit */
- uchar slot; /* Slot Number this module is inserted in */
- uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */
-#ifdef DEBUG
- uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */
- uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */
- uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */
- unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */
- unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */
- unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */
- uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */
-
-#endif
-} AUX_MEM_DIMM_INFO;
-
-
-/*
- * translate ns.ns/10 coding of SPD timing values
- * into 10 ps unit values
- */
-static inline unsigned short NS10to10PS (unsigned char spd_byte)
-{
- unsigned short ns, ns10;
-
- /* isolate upper nibble */
- ns = (spd_byte >> 4) & 0x0F;
- /* isolate lower nibble */
- ns10 = (spd_byte & 0x0F);
-
- return (ns * 100 + ns10 * 10);
-}
-
-/*
- * translate ns coding of SPD timing values
- * into 10 ps unit values
- */
-static inline unsigned short NSto10PS (unsigned char spd_byte)
-{
- return (spd_byte * 100);
-}
-
-/* This code reads the SPD chip on the sdram and populates
- * the array which is passed in with the relevant information */
-/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
-static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
-{
- unsigned long spd_checksum;
-
-#ifdef ZUMA_NTL
- /* zero all the values */
- memset (info, 0, sizeof (*info));
-
-/*
- if (!slot) {
- info->slot = 0;
- info->banks = 1;
- info->registered = 0;
- info->drb_size = 16;*/ /* 16 - 256MBit, 32 - 512MBit */
-/* info->tpar = 3;
- info->tras_clocks = 5;
- info->burst_len = 4;
-*/
-#ifdef CONFIG_MV64460_ECC
- /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
- dimmInfo->errorCheckType = 2;
-/* info->ecc = 2;*/
-#endif
-}
-
-return 0;
-
-#else
- uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
- int ret;
- unsigned int i, j, density = 1;
-
-#ifdef DEBUG
- unsigned int k;
-#endif
- unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
- int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
- uchar supp_cal, cal_val;
- ulong memclk, tmemclk;
- ulong tmp;
- uchar trp_clocks = 0, tras_clocks;
- uchar data[128];
-
- memclk = gd->bus_clk;
- tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
-
- debug("before i2c read\n");
-
- ret = i2c_read (addr, 0, 1, data, 128);
-
- debug("after i2c read\n");
-
- /* zero all the values */
- memset (dimmInfo, 0, sizeof (*dimmInfo));
-
- /* copy the SPD content 1:1 into the dimmInfo structure */
- for (i = 0; i <= 127; i++) {
- dimmInfo->spd_raw_data[i] = data[i];
- }
-
- if (ret) {
- debug("No DIMM in slot %d [err = %x]\n", slot, ret);
- return 0;
- } else
- dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */
-
-#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
-
- for (i = 0; i <= 127; i++) {
- printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
- data[i]);
- }
-
-#endif
-#ifdef DEBUG
-/* find Manufactura of Dimm Module */
- for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
- dimmInfo->manufactura[i] = data[64 + i];
- }
- printf ("\nThis RAM-Module is produced by: %s\n",
- dimmInfo->manufactura);
-
-/* find Manul-ID of Dimm Module */
- for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
- dimmInfo->modul_id[i] = data[73 + i];
- }
- printf ("The Module-ID of this RAM-Module is: %s\n",
- dimmInfo->modul_id);
-
-/* find Vendor-Data of Dimm Module */
- for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
- dimmInfo->vendor_data[i] = data[99 + i];
- }
- printf ("Vendor Data of this RAM-Module is: %s\n",
- dimmInfo->vendor_data);
-
-/* find modul_serial_no of Dimm Module */
- dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
- printf ("Serial No. of this RAM-Module is: %ld (%lx)\n",
- dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
-
-/* find Manufac-Data of Dimm Module */
- dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
- printf ("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data[94]); /*dimmInfo->manufac_date */
-
-/* find modul_revision of Dimm Module */
- dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
- printf ("Module Revision of this RAM-Module is: %d.%d\n", data[91], data[92]); /* dimmInfo->modul_revision */
-
-/* find manufac_place of Dimm Module */
- dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
- printf ("manufac_place of this RAM-Module is: %d\n",
- dimmInfo->manufac_place);
-
-#endif
-
-/*------------------------------------------------------------------------------------------------------------------------------*/
-/* calculate SPD checksum */
-/*------------------------------------------------------------------------------------------------------------------------------*/
- spd_checksum = 0;
-
- for (i = 0; i <= 62; i++) {
- spd_checksum += data[i];
- }
-
- if ((spd_checksum & 0xff) != data[63]) {
- printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
- hang ();
- }
-
- else
- printf ("SPD Checksum ok!\n");
-
-
-/*------------------------------------------------------------------------------------------------------------------------------*/
- for (i = 2; i <= 35; i++) {
- switch (i) {
- case 2: /* Memory type (DDR / SDRAM) */
- dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
-#ifdef DEBUG
- if (dimmInfo->memoryType == 0)
- debug
- ("Dram_type in slot %d is: SDRAM\n",
- dimmInfo->slot);
- if (dimmInfo->memoryType == 1)
- debug
- ("Dram_type in slot %d is: DDRAM\n",
- dimmInfo->slot);
-#endif
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 3: /* Number Of Row Addresses */
- dimmInfo->numOfRowAddresses = data[i];
- debug
- ("Module Number of row addresses: %d\n",
- dimmInfo->numOfRowAddresses);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 4: /* Number Of Column Addresses */
- dimmInfo->numOfColAddresses = data[i];
- debug
- ("Module Number of col addresses: %d\n",
- dimmInfo->numOfColAddresses);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 5: /* Number Of Module Banks */
- dimmInfo->numOfModuleBanks = data[i];
- debug
- ("Number of Banks on Mod. : %d\n",
- dimmInfo->numOfModuleBanks);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 6: /* Data Width */
- dimmInfo->dataWidth = data[i];
- debug
- ("Module Data Width: %d\n",
- dimmInfo->dataWidth);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 8: /* Voltage Interface */
- switch (data[i]) {
- case 0x0:
- dimmInfo->voltageInterface = TTL_5V_TOLERANT;
- debug
- ("Module is TTL_5V_TOLERANT\n");
- break;
- case 0x1:
- dimmInfo->voltageInterface = LVTTL;
- debug
- ("Module is LVTTL\n");
- break;
- case 0x2:
- dimmInfo->voltageInterface = HSTL_1_5V;
- debug
- ("Module is TTL_5V_TOLERANT\n");
- break;
- case 0x3:
- dimmInfo->voltageInterface = SSTL_3_3V;
- debug
- ("Module is HSTL_1_5V\n");
- break;
- case 0x4:
- dimmInfo->voltageInterface = SSTL_2_5V;
- debug
- ("Module is SSTL_2_5V\n");
- break;
- default:
- dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
- debug
- ("Module is VOLTAGE_UNKNOWN\n");
- break;
- }
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 9: /* Minimum Cycle Time At Max CasLatancy */
- shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
- mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
- maskLeftOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
- maskRightOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
- leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
- rightOfPoint = (data[i] & maskRightOfPoint) * mult;
- dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
- leftOfPoint;
- dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
- rightOfPoint;
- debug
- ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n",
- leftOfPoint, rightOfPoint);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 10: /* Clock To Data Out */
- div = (dimmInfo->memoryType == DDR) ? 100 : 10;
- time_tmp =
- (((data[i] & 0xf0) >> 4) * 10) +
- ((data[i] & 0x0f));
- leftOfPoint = time_tmp / div;
- rightOfPoint = time_tmp % div;
- dimmInfo->clockToDataOut_LoP = leftOfPoint;
- dimmInfo->clockToDataOut_RoP = rightOfPoint;
- debug("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->clockToDataOut */
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-/*#ifdef CONFIG_ECC */
- case 11: /* Error Check Type */
- dimmInfo->errorCheckType = data[i];
- debug
- ("Error Check Type (0=NONE): %d\n",
- dimmInfo->errorCheckType);
- break;
-/* #endif */
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 12: /* Refresh Interval */
- dimmInfo->RefreshInterval = data[i];
- debug
- ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
- dimmInfo->RefreshInterval);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 13: /* Sdram Width */
- dimmInfo->sdramWidth = data[i];
- debug
- ("Sdram Width: %d\n",
- dimmInfo->sdramWidth);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 14: /* Error Check Data Width */
- dimmInfo->errorCheckDataWidth = data[i];
- debug
- ("Error Check Data Width: %d\n",
- dimmInfo->errorCheckDataWidth);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 15: /* Minimum Clock Delay */
- dimmInfo->minClkDelay = data[i];
- debug
- ("Minimum Clock Delay: %d\n",
- dimmInfo->minClkDelay);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 16: /* Burst Length Supported */
- /******-******-******-*******
- * bit3 | bit2 | bit1 | bit0 *
- *******-******-******-*******
- burst length = * 8 | 4 | 2 | 1 *
- *****************************
-
- If for example bit0 and bit2 are set, the burst
- length supported are 1 and 4. */
-
- dimmInfo->burstLengthSupported = data[i];
-#ifdef DEBUG
- debug
- ("Burst Length Supported: ");
- if (dimmInfo->burstLengthSupported & 0x01)
- debug("1, ");
- if (dimmInfo->burstLengthSupported & 0x02)
- debug("2, ");
- if (dimmInfo->burstLengthSupported & 0x04)
- debug("4, ");
- if (dimmInfo->burstLengthSupported & 0x08)
- debug("8, ");
- debug(" Bit \n");
-#endif
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 17: /* Number Of Banks On Each Device */
- dimmInfo->numOfBanksOnEachDevice = data[i];
- debug
- ("Number Of Banks On Each Chip: %d\n",
- dimmInfo->numOfBanksOnEachDevice);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 18: /* Suported Cas Latencies */
-
- /* DDR:
- *******-******-******-******-******-******-******-*******
- * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
- *******-******-******-******-******-******-******-*******
- CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 *
- *********************************************************
- SDRAM:
- *******-******-******-******-******-******-******-*******
- * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
- *******-******-******-******-******-******-******-*******
- CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 *
- ********************************************************/
- dimmInfo->suportedCasLatencies = data[i];
-#ifdef DEBUG
- debug
- ("Suported Cas Latencies: (CL) ");
- if (dimmInfo->memoryType == 0) { /* SDRAM */
- for (k = 0; k <= 7; k++) {
- if (dimmInfo->
- suportedCasLatencies & (1 << k))
- debug
- ("%d, ",
- k + 1);
- }
-
- } else { /* DDR-RAM */
-
- if (dimmInfo->suportedCasLatencies & 1)
- debug("1, ");
- if (dimmInfo->suportedCasLatencies & 2)
- debug("1.5, ");
- if (dimmInfo->suportedCasLatencies & 4)
- debug("2, ");
- if (dimmInfo->suportedCasLatencies & 8)
- debug("2.5, ");
- if (dimmInfo->suportedCasLatencies & 16)
- debug("3, ");
- if (dimmInfo->suportedCasLatencies & 32)
- debug("3.5, ");
-
- }
- debug("\n");
-#endif
- /* Calculating MAX CAS latency */
- for (j = 7; j > 0; j--) {
- if (((dimmInfo->
- suportedCasLatencies >> j) & 0x1) ==
- 1) {
- switch (dimmInfo->memoryType) {
- case DDR:
- /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
- switch (j) {
- case 7:
- debug
- ("Max. Cas Latencies (DDR): ERROR !!!\n");
- dimmInfo->
- maxClSupported_DDR
- =
- DDR_CL_FAULT;
- hang ();
- break;
- case 6:
- debug
- ("Max. Cas Latencies (DDR): ERROR !!!\n");
- dimmInfo->
- maxClSupported_DDR
- =
- DDR_CL_FAULT;
- hang ();
- break;
- case 5:
- debug
- ("Max. Cas Latencies (DDR): 3.5 clk's\n");
- dimmInfo->
- maxClSupported_DDR
- = DDR_CL_3_5;
- break;
- case 4:
- debug
- ("Max. Cas Latencies (DDR): 3 clk's \n");
- dimmInfo->
- maxClSupported_DDR
- = DDR_CL_3;
- break;
- case 3:
- debug
- ("Max. Cas Latencies (DDR): 2.5 clk's \n");
- dimmInfo->
- maxClSupported_DDR
- = DDR_CL_2_5;
- break;
- case 2:
- debug
- ("Max. Cas Latencies (DDR): 2 clk's \n");
- dimmInfo->
- maxClSupported_DDR
- = DDR_CL_2;
- break;
- case 1:
- debug
- ("Max. Cas Latencies (DDR): 1.5 clk's \n");
- dimmInfo->
- maxClSupported_DDR
- = DDR_CL_1_5;
- break;
- }
-
- /* ronen - in case we have a DIMM with minimumCycleTimeAtMaxCasLatancy
- lower then our SDRAM cycle count, we won't be able to support this CAL
- and we will have to use lower CAL. (minus - means from 3.0 to 2.5) */
- if ((dimmInfo->
- minimumCycleTimeAtMaxCasLatancy_LoP
- <
- CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
- ||
- ((dimmInfo->
- minimumCycleTimeAtMaxCasLatancy_LoP
- ==
- CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
- && (dimmInfo->
- minimumCycleTimeAtMaxCasLatancy_RoP
- <
- CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
- {
- dimmInfo->
- maxClSupported_DDR
- =
- dimmInfo->
- maxClSupported_DDR
- >> 1;
- debug
- ("*** Change actual Cas Latencies cause of minimumCycleTime n");
- }
- /* ronen - checkif the Dimm frequency compared to the Sysclock. */
- if ((dimmInfo->
- minimumCycleTimeAtMaxCasLatancy_LoP
- >
- CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
- ||
- ((dimmInfo->
- minimumCycleTimeAtMaxCasLatancy_LoP
- ==
- CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
- && (dimmInfo->
- minimumCycleTimeAtMaxCasLatancy_RoP
- >
- CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
- {
- printf ("*********************************************************\n");
- printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n");
- printf ("*********************************************************\n");
- hang ();
- }
-
- dimmInfo->
- maxCASlatencySupported_LoP
- =
- 1 +
- (int) (5 * j / 10);
- if (((5 * j) % 10) != 0)
- dimmInfo->
- maxCASlatencySupported_RoP
- = 5;
- else
- dimmInfo->
- maxCASlatencySupported_RoP
- = 0;
- debug
- ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
- dimmInfo->
- maxCASlatencySupported_LoP,
- dimmInfo->
- maxCASlatencySupported_RoP);
- break;
- case SDRAM:
- /* CAS latency 1, 2, 3, 4, 5, 6, 7 */
- dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */
- debug
- ("Max. Cas Latencies (SD): %d\n",
- dimmInfo->
- maxClSupported_SD);
- dimmInfo->
- maxCASlatencySupported_LoP
- = j;
- dimmInfo->
- maxCASlatencySupported_RoP
- = 0;
- debug
- ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
- dimmInfo->
- maxCASlatencySupported_LoP,
- dimmInfo->
- maxCASlatencySupported_RoP);
- break;
- }
- break;
- }
- }
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 21: /* Buffered Address And Control Inputs */
- debug("\nModul Attributes (SPD Byte 21): \n");
- dimmInfo->bufferedAddrAndControlInputs =
- data[i] & BIT0;
- dimmInfo->registeredAddrAndControlInputs =
- (data[i] & BIT1) >> 1;
- dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
- dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
- dimmInfo->registeredDQMBinputs =
- (data[i] & BIT4) >> 4;
- dimmInfo->differentialClockInput =
- (data[i] & BIT5) >> 5;
- dimmInfo->redundantRowAddressing =
- (data[i] & BIT6) >> 6;
-#ifdef DEBUG
- if (dimmInfo->bufferedAddrAndControlInputs == 1)
- debug
- (" - Buffered Address/Control Input: Yes \n");
- else
- debug
- (" - Buffered Address/Control Input: No \n");
-
- if (dimmInfo->registeredAddrAndControlInputs == 1)
- debug
- (" - Registered Address/Control Input: Yes \n");
- else
- debug
- (" - Registered Address/Control Input: No \n");
-
- if (dimmInfo->onCardPLL == 1)
- debug
- (" - On-Card PLL (clock): Yes \n");
- else
- debug
- (" - On-Card PLL (clock): No \n");
-
- if (dimmInfo->bufferedDQMBinputs == 1)
- debug
- (" - Bufferd DQMB Inputs: Yes \n");
- else
- debug
- (" - Bufferd DQMB Inputs: No \n");
-
- if (dimmInfo->registeredDQMBinputs == 1)
- debug
- (" - Registered DQMB Inputs: Yes \n");
- else
- debug
- (" - Registered DQMB Inputs: No \n");
-
- if (dimmInfo->differentialClockInput == 1)
- debug
- (" - Differential Clock Input: Yes \n");
- else
- debug
- (" - Differential Clock Input: No \n");
-
- if (dimmInfo->redundantRowAddressing == 1)
- debug
- (" - redundant Row Addressing: Yes \n");
- else
- debug
- (" - redundant Row Addressing: No \n");
-
-#endif
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 22: /* Suported AutoPreCharge */
- debug("\nModul Attributes (SPD Byte 22): \n");
- dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
- dimmInfo->suportedAutoPreCharge =
- (data[i] & BIT1) >> 1;
- dimmInfo->suportedPreChargeAll =
- (data[i] & BIT2) >> 2;
- dimmInfo->suportedWrite1ReadBurst =
- (data[i] & BIT3) >> 3;
- dimmInfo->suported5PercentLowVCC =
- (data[i] & BIT4) >> 4;
- dimmInfo->suported5PercentUpperVCC =
- (data[i] & BIT5) >> 5;
-#ifdef DEBUG
- if (dimmInfo->suportedEarlyRasPreCharge == 1)
- debug
- (" - Early Ras Precharge: Yes \n");
- else
- debug
- (" - Early Ras Precharge: No \n");
-
- if (dimmInfo->suportedAutoPreCharge == 1)
- debug
- (" - AutoPreCharge: Yes \n");
- else
- debug
- (" - AutoPreCharge: No \n");
-
- if (dimmInfo->suportedPreChargeAll == 1)
- debug
- (" - Precharge All: Yes \n");
- else
- debug
- (" - Precharge All: No \n");
-
- if (dimmInfo->suportedWrite1ReadBurst == 1)
- debug
- (" - Write 1/ReadBurst: Yes \n");
- else
- debug
- (" - Write 1/ReadBurst: No \n");
-
- if (dimmInfo->suported5PercentLowVCC == 1)
- debug
- (" - lower VCC tolerance: 5 Percent \n");
- else
- debug
- (" - lower VCC tolerance: 10 Percent \n");
-
- if (dimmInfo->suported5PercentUpperVCC == 1)
- debug
- (" - upper VCC tolerance: 5 Percent \n");
- else
- debug
- (" - upper VCC tolerance: 10 Percent \n");
-
-#endif
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
- shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
- mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
- maskLeftOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
- maskRightOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
- leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
- rightOfPoint = (data[i] & maskRightOfPoint) * mult;
- dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
- leftOfPoint;
- dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
- rightOfPoint;
- debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 24: /* Clock To Data Out 2nd highest Cas Latency Value */
- div = (dimmInfo->memoryType == DDR) ? 100 : 10;
- time_tmp =
- (((data[i] & 0xf0) >> 4) * 10) +
- ((data[i] & 0x0f));
- leftOfPoint = time_tmp / div;
- rightOfPoint = time_tmp % div;
- dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
- dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
- debug
- ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n",
- leftOfPoint, rightOfPoint);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
- shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
- mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
- maskLeftOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
- maskRightOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
- leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
- rightOfPoint = (data[i] & maskRightOfPoint) * mult;
- dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
- leftOfPoint;
- dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
- rightOfPoint;
- debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 26: /* Clock To Data Out 3rd highest Cas Latency Value */
- div = (dimmInfo->memoryType == DDR) ? 100 : 10;
- time_tmp =
- (((data[i] & 0xf0) >> 4) * 10) +
- ((data[i] & 0x0f));
- leftOfPoint = time_tmp / div;
- rightOfPoint = time_tmp % div;
- dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
- dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
- debug
- ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n",
- leftOfPoint, rightOfPoint);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 27: /* Minimum Row Precharge Time */
- shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
- maskLeftOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
- maskRightOfPoint =
- (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
- leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
- rightOfPoint = (data[i] & maskRightOfPoint) * 25;
-
- dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint); /* measured in n times 10ps Intervals */
- trp_clocks =
- (dimmInfo->minRowPrechargeTime +
- (tmemclk - 1)) / tmemclk;
- debug
- ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n",
- tmemclk, tmemclk / 100, tmemclk % 100);
- debug
- ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n",
- leftOfPoint, rightOfPoint, trp_clocks);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 28: /* Minimum Row Active to Row Active Time */
- shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
- maskLeftOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
- maskRightOfPoint =
- (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
- leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
- rightOfPoint = (data[i] & maskRightOfPoint) * 25;
-
- dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
- debug
- ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n",
- leftOfPoint, rightOfPoint, trp_clocks);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 29: /* Minimum Ras-To-Cas Delay */
- shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
- maskLeftOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
- maskRightOfPoint =
- (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
- leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
- rightOfPoint = (data[i] & maskRightOfPoint) * 25;
-
- dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
- debug
- ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n",
- leftOfPoint, rightOfPoint, trp_clocks);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 30: /* Minimum Ras Pulse Width */
- dimmInfo->minRasPulseWidth = data[i];
- tras_clocks =
- (NSto10PS (data[i]) +
- (tmemclk - 1)) / tmemclk;
- debug
- ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n",
- dimmInfo->minRasPulseWidth, tras_clocks);
-
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 31: /* Module Bank Density */
- dimmInfo->moduleBankDensity = data[i];
- debug
- ("Module Bank Density: %d\n",
- dimmInfo->moduleBankDensity);
-#ifdef DEBUG
- debug
- ("*** Offered Densities (more than 1 = Multisize-Module): ");
- {
- if (dimmInfo->moduleBankDensity & 1)
- debug("4MB, ");
- if (dimmInfo->moduleBankDensity & 2)
- debug("8MB, ");
- if (dimmInfo->moduleBankDensity & 4)
- debug("16MB, ");
- if (dimmInfo->moduleBankDensity & 8)
- debug("32MB, ");
- if (dimmInfo->moduleBankDensity & 16)
- debug("64MB, ");
- if (dimmInfo->moduleBankDensity & 32)
- debug("128MB, ");
- if ((dimmInfo->moduleBankDensity & 64)
- || (dimmInfo->moduleBankDensity & 128)) {
- debug("ERROR, ");
- hang ();
- }
- }
- debug("\n");
-#endif
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 32: /* Address And Command Setup Time (measured in ns/1000) */
- sign = 1;
- switch (dimmInfo->memoryType) {
- case DDR:
- time_tmp =
- (((data[i] & 0xf0) >> 4) * 10) +
- ((data[i] & 0x0f));
- leftOfPoint = time_tmp / 100;
- rightOfPoint = time_tmp % 100;
- break;
- case SDRAM:
- leftOfPoint = (data[i] & 0xf0) >> 4;
- if (leftOfPoint > 7) {
- leftOfPoint = data[i] & 0x70 >> 4;
- sign = -1;
- }
- rightOfPoint = (data[i] & 0x0f);
- break;
- }
- dimmInfo->addrAndCommandSetupTime =
- (leftOfPoint * 100 + rightOfPoint) * sign;
- debug
- ("Address And Command Setup Time [ns]: %d.%d\n",
- sign * leftOfPoint, rightOfPoint);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 33: /* Address And Command Hold Time */
- sign = 1;
- switch (dimmInfo->memoryType) {
- case DDR:
- time_tmp =
- (((data[i] & 0xf0) >> 4) * 10) +
- ((data[i] & 0x0f));
- leftOfPoint = time_tmp / 100;
- rightOfPoint = time_tmp % 100;
- break;
- case SDRAM:
- leftOfPoint = (data[i] & 0xf0) >> 4;
- if (leftOfPoint > 7) {
- leftOfPoint = data[i] & 0x70 >> 4;
- sign = -1;
- }
- rightOfPoint = (data[i] & 0x0f);
- break;
- }
- dimmInfo->addrAndCommandHoldTime =
- (leftOfPoint * 100 + rightOfPoint) * sign;
- debug
- ("Address And Command Hold Time [ns]: %d.%d\n",
- sign * leftOfPoint, rightOfPoint);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 34: /* Data Input Setup Time */
- sign = 1;
- switch (dimmInfo->memoryType) {
- case DDR:
- time_tmp =
- (((data[i] & 0xf0) >> 4) * 10) +
- ((data[i] & 0x0f));
- leftOfPoint = time_tmp / 100;
- rightOfPoint = time_tmp % 100;
- break;
- case SDRAM:
- leftOfPoint = (data[i] & 0xf0) >> 4;
- if (leftOfPoint > 7) {
- leftOfPoint = data[i] & 0x70 >> 4;
- sign = -1;
- }
- rightOfPoint = (data[i] & 0x0f);
- break;
- }
- dimmInfo->dataInputSetupTime =
- (leftOfPoint * 100 + rightOfPoint) * sign;
- debug
- ("Data Input Setup Time [ns]: %d.%d\n",
- sign * leftOfPoint, rightOfPoint);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 35: /* Data Input Hold Time */
- sign = 1;
- switch (dimmInfo->memoryType) {
- case DDR:
- time_tmp =
- (((data[i] & 0xf0) >> 4) * 10) +
- ((data[i] & 0x0f));
- leftOfPoint = time_tmp / 100;
- rightOfPoint = time_tmp % 100;
- break;
- case SDRAM:
- leftOfPoint = (data[i] & 0xf0) >> 4;
- if (leftOfPoint > 7) {
- leftOfPoint = data[i] & 0x70 >> 4;
- sign = -1;
- }
- rightOfPoint = (data[i] & 0x0f);
- break;
- }
- dimmInfo->dataInputHoldTime =
- (leftOfPoint * 100 + rightOfPoint) * sign;
- debug
- ("Data Input Hold Time [ns]: %d.%d\n\n",
- sign * leftOfPoint, rightOfPoint);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
- }
- }
- /* calculating the sdram density */
- for (i = 0;
- i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
- i++) {
- density = density * 2;
- }
- dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
- dimmInfo->sdramWidth;
- dimmInfo->numberOfDevices =
- (dimmInfo->dataWidth / dimmInfo->sdramWidth) *
- dimmInfo->numOfModuleBanks;
- if ((dimmInfo->errorCheckType == 0x1)
- || (dimmInfo->errorCheckType == 0x2)
- || (dimmInfo->errorCheckType == 0x3)) {
- dimmInfo->size =
- (dimmInfo->deviceDensity / 8) *
- (dimmInfo->numberOfDevices -
- /* ronen on the 1G dimm we get wrong value. (was devicesForErrCheck) */
- dimmInfo->numberOfDevices / 8);
- } else {
- dimmInfo->size =
- (dimmInfo->deviceDensity / 8) *
- dimmInfo->numberOfDevices;
- }
-
- /* compute the module DRB size */
- tmp = (1 <<
- (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
- tmp *= dimmInfo->numOfModuleBanks;
- tmp *= dimmInfo->sdramWidth;
- tmp = tmp >> 24; /* div by 0x4000000 (64M) */
- dimmInfo->drb_size = (uchar) tmp;
- debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size);
-
- /* try a CAS latency of 3 first... */
-
- /* bit 1 is CL2, bit 2 is CL3 */
- supp_cal = (dimmInfo->suportedCasLatencies & 0x6) >> 1;
-
- cal_val = 0;
- if (supp_cal & 3) {
- if (NS10to10PS (data[9]) <= tmemclk)
- cal_val = 3;
- }
-
- /* then 2... */
- if (supp_cal & 2) {
- if (NS10to10PS (data[23]) <= tmemclk)
- cal_val = 2;
- }
-
- debug("cal_val = %d\n", cal_val);
-
- /* bummer, did't work... */
- if (cal_val == 0) {
- debug("Couldn't find a good CAS latency\n");
- hang ();
- return 0;
- }
-
- return true;
-#endif
-}
-
-/* sets up the GT properly with information passed in */
-int setup_sdram (AUX_MEM_DIMM_INFO * info)
-{
- ulong tmp, check;
- ulong tmp_sdram_mode = 0; /* 0x141c */
- ulong tmp_dunit_control_low = 0; /* 0x1404 */
- int i;
-
- /* added 8/21/2003 P. Marchese */
- unsigned int sdram_config_reg;
-
- /* added 10/10/2003 P. Marchese */
- ulong sdram_chip_size;
-
- /* sanity checking */
- if (!info->numOfModuleBanks) {
- printf ("setup_sdram called with 0 banks\n");
- return 1;
- }
-
- /* delay line */
- set_dfcdlInit (); /* may be its not needed */
- debug("Delay line set done\n");
-
- /* set SDRAM mode NOP */ /* To_do check it */
- GT_REG_WRITE (SDRAM_OPERATION, 0x5);
- while (GTREGREAD (SDRAM_OPERATION) != 0) {
- debug
- ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n");
- }
-
- /* SDRAM configuration */
-/* added 8/21/2003 P. Marchese */
-/* code allows usage of registered DIMMS */
-
- /* figure out the memory refresh internal */
- switch (info->RefreshInterval) {
- case 0x0:
- case 0x80: /* refresh period is 15.625 usec */
- sdram_config_reg =
- (unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_CLK)
- / (float) 1000000.0);
- break;
- case 0x1:
- case 0x81: /* refresh period is 3.9 usec */
- sdram_config_reg =
- (unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_CLK) /
- (float) 1000000.0);
- break;
- case 0x2:
- case 0x82: /* refresh period is 7.8 usec */
- sdram_config_reg =
- (unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_CLK) /
- (float) 1000000.0);
- break;
- case 0x3:
- case 0x83: /* refresh period is 31.3 usec */
- sdram_config_reg =
- (unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_CLK) /
- (float) 1000000.0);
- break;
- case 0x4:
- case 0x84: /* refresh period is 62.5 usec */
- sdram_config_reg =
- (unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_CLK) /
- (float) 1000000.0);
- break;
- case 0x5:
- case 0x85: /* refresh period is 125 usec */
- sdram_config_reg =
- (unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_CLK) /
- (float) 1000000.0);
- break;
- default: /* refresh period undefined */
- printf ("DRAM refresh period is unknown!\n");
- printf ("Aborting DRAM setup with an error\n");
- hang ();
- break;
- }
- debug("calculated refresh interval %0x\n", sdram_config_reg);
-
- /* make sure the refresh value is only 14 bits */
- if (sdram_config_reg > 0x1fff)
- sdram_config_reg = 0x1fff;
- debug("adjusted refresh interval %0x\n", sdram_config_reg);
-
- /* we want physical bank interleaving and */
- /* virtual bank interleaving enabled so do nothing */
- /* since these bits need to be zero to enable the interleaving */
-
- /* registered DRAM ? */
- if (info->registeredAddrAndControlInputs == 1) {
- /* it's registered DRAM, so set the reg. DRAM bit */
- sdram_config_reg = sdram_config_reg | BIT17;
- debug("Enabling registered DRAM bit\n");
- }
- /* turn on DRAM ECC? */
-#ifdef CONFIG_MV64460_ECC
- if (info->errorCheckType == 0x2) {
- /* DRAM has ECC, so turn it on */
- sdram_config_reg = sdram_config_reg | BIT18;
- debug("Enabling ECC\n");
- }
-#endif
- /* set the data DQS pin configuration */
- switch (info->sdramWidth) {
- case 0x4: /* memory is x4 */
- sdram_config_reg = sdram_config_reg | BIT20 | BIT21;
- debug("Data DQS pins set for 16 pins\n");
- break;
- case 0x8: /* memory is x8 or x16 */
- case 0x10:
- sdram_config_reg = sdram_config_reg | BIT21;
- debug("Data DQS pins set for 8 pins\n");
- break;
- case 0x20: /* memory is x32 */
- /* both bits are cleared for x32 so nothing to do */
- debug("Data DQS pins set for 2 pins\n");
- break;
- default: /* memory width unsupported */
- printf ("DRAM chip width is unknown!\n");
- printf ("Aborting DRAM setup with an error\n");
- hang ();
- break;
- }
-
- /*ronen db64460 */
- /* perform read buffer assignments */
- /* we are going to use the Power-up defaults */
- /* bit 27 = PCI bus #0 = buffer 0 */
- /* bit 28 = PCI bus #1 = buffer 0 */
- /* bit 29 = MPSC = buffer 0 */
- /* bit 30 = IDMA = buffer 0 */
- /* bit 31 = Gigabit = buffer 0 */
- sdram_config_reg = sdram_config_reg | 0x58000000;
- sdram_config_reg = sdram_config_reg & 0xffffff00;
- /* bit 14 FBSplit = FCRAM controller bsplit enable. */
- /* bit 15 vw = FCRAM Variable write length enable. */
- /* bit 16 DType = Dram Type (0 = FCRAM,1 = Standard) */
- sdram_config_reg = sdram_config_reg | BIT14 | BIT15;
-
- /* write the value into the SDRAM configuration register */
- GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg);
- debug("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG));
-
- /* SDRAM open pages control keep open as much as I can */
- GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
- debug
- ("sdram_open_pages_controll 0x1414: %08x\n",
- GTREGREAD (SDRAM_OPEN_PAGES_CONTROL));
-
- /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
- tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */
- if (tmp == 0)
- debug("Core Signals are sync (by HW-Setting)!!!\n");
- else
- debug
- ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n");
-
- /* SDRAM set CAS Latency according to SPD information */
- switch (info->memoryType) {
- case SDRAM:
- printf ("### SD-RAM not supported !!!\n");
- printf ("Aborting!!!\n");
- hang ();
- /* ToDo fill SD-RAM if needed !!!!! */
- break;
- /* Calculate the settings for SDRAM mode and Dunit control low registers */
- /* Values set according to technical bulletin TB-92 rev. c */
- case DDR:
- debug("### SET-CL for DDR-RAM\n");
- /* ronen db64460 - change the tmp_dunit_control_low setting!!! */
- switch (info->maxClSupported_DDR) {
- case DDR_CL_3:
- tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */
- if (tmp == 1) { /* clocks sync */
- if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
- tmp_dunit_control_low = 0x05110051;
- else
- tmp_dunit_control_low = 0x24110051;
- debug
- ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low);
- printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
- } else { /* clk sync. bypassed */
-
- if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
- tmp_dunit_control_low = 0xC5000540;
- else
- tmp_dunit_control_low = 0xC4000540;
- debug
- ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low);
- }
- break;
- case DDR_CL_2_5:
- tmp_sdram_mode = 0x62; /* CL=2.5 Burstlength = 4 */
- if (tmp == 1) { /* clocks sync */
- if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
- tmp_dunit_control_low = 0x25110051;
- else
- tmp_dunit_control_low = 0x24110051;
- debug
- ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low);
- printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
- } else { /* clk sync. bypassed */
-
- if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */
- tmp_dunit_control_low = 0xC5000540;
- /* printf("CL = 2.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */
- /* printf("Aborting!!!\n");1 */
- /* hang();1 */
- } else
- tmp_dunit_control_low = 0xC4000540;
- debug
- ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low);
- }
- break;
- case DDR_CL_2:
- tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */
- if (tmp == 1) { /* clocks sync */
- if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
- tmp_dunit_control_low = 0x04110051;
- else
- tmp_dunit_control_low = 0x03110051;
- debug
- ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low);
- printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
- } else { /* clk sync. bypassed */
-
- if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */
- /*printf("CL = 2, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */
- /*printf("Aborting!!!\n");1 */
- /*hang();1 */
- tmp_dunit_control_low = 0xC4000540;
- } else
- tmp_dunit_control_low = 0xC3000540;;
- debug
- ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low);
- }
- break;
- case DDR_CL_1_5:
- tmp_sdram_mode = 0x52; /* CL=1.5 Burstlength = 4 */
- if (tmp == 1) { /* clocks sync */
- if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
- tmp_dunit_control_low = 0x24110051;
- else
- tmp_dunit_control_low = 0x23110051;
- debug
- ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low);
- printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
- } else { /* clk sync. bypassed */
-
- if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */
- /*printf("CL = 1.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */
- /*printf("Aborting!!!\n");1 */
- /*hang();1 */
- tmp_dunit_control_low = 0xC4000540;
- } else
- tmp_dunit_control_low = 0xC3000540;
- debug
- ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low);
- }
- break;
-
- default:
- printf ("Max. CL is out of range %d\n",
- info->maxClSupported_DDR);
- hang ();
- break;
- } /* end DDR switch */
- break;
- } /* end CL switch */
-
- /* Write results of CL detection procedure */
- /* set SDRAM mode reg. 0x141c */
- GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
-
- /* set SDRAM mode SetCommand 0x1418 */
- GT_REG_WRITE (SDRAM_OPERATION, 0x3);
- while (GTREGREAD (SDRAM_OPERATION) != 0) {
- debug
- ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
- }
-
- /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
- GT_REG_WRITE (D_UNIT_CONTROL_LOW, tmp_dunit_control_low);
-
- /* set SDRAM mode SetCommand 0x1418 */
- GT_REG_WRITE (SDRAM_OPERATION, 0x3);
- while (GTREGREAD (SDRAM_OPERATION) != 0) {
- debug
- ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n");
- }
-
-/*------------------------------------------------------------------------------ */
-
- /* bank parameters */
- /* SDRAM address decode register 0x1410 */
- /* program this with the default value */
- tmp = 0x02; /* power-up default address select decoding value */
-
- debug("drb_size (n*64Mbit): %d\n", info->drb_size);
-/* figure out the DRAM chip size */
- sdram_chip_size =
- (1 << (info->numOfRowAddresses + info->numOfColAddresses));
- sdram_chip_size *= info->sdramWidth;
- sdram_chip_size *= 4;
- debug("computed sdram chip size is %#lx\n", sdram_chip_size);
- /* divide sdram chip size by 64 Mbits */
- sdram_chip_size = sdram_chip_size / 0x4000000;
- switch (sdram_chip_size) {
- case 1: /* 64 Mbit */
- case 2: /* 128 Mbit */
- debug("RAM-Device_size 64Mbit or 128Mbit)\n");
- tmp |= (0x00 << 4);
- break;
- case 4: /* 256 Mbit */
- case 8: /* 512 Mbit */
- debug("RAM-Device_size 256Mbit or 512Mbit)\n");
- tmp |= (0x01 << 4);
- break;
- case 16: /* 1 Gbit */
- case 32: /* 2 Gbit */
- debug("RAM-Device_size 1Gbit or 2Gbit)\n");
- tmp |= (0x02 << 4);
- break;
- default:
- printf ("Error in dram size calculation\n");
- printf ("RAM-Device_size is unsupported\n");
- hang ();
- }
-
- /* SDRAM address control */
- GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
- debug
- ("setting up sdram address control (0x1410) with: %08lx \n",
- tmp);
-
-/* ------------------------------------------------------------------------------ */
-/* same settings for registerd & non-registerd DDR SDRAM */
- debug
- ("setting up sdram_timing_control_low (0x1408) with: %08x \n",
- 0x01501220);
- /*ronen db64460 */
- GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x01501220);
-
-
-/* ------------------------------------------------------------------------------ */
-
- /* SDRAM configuration */
- tmp = GTREGREAD (SDRAM_CONFIG);
-
- if (info->registeredAddrAndControlInputs
- || info->registeredDQMBinputs) {
- tmp |= (1 << 17);
- debug
- ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
- info->registeredAddrAndControlInputs,
- info->registeredDQMBinputs);
- }
-
- /* Use buffer 1 to return read data to the CPU
- * Page 426 MV6indent: Standard input:1464: Warning:old style assignment ambiguity in "=*". Assuming "= *"
-
-indent: Standard input:1465: Warning:old style assignment ambiguity in "=*". Assuming "= *"
-
-4460 */
- tmp |= (1 << 26);
- debug
- ("Before Buffer assignment - sdram_conf (0x1400): %08x\n",
- GTREGREAD (SDRAM_CONFIG));
- debug
- ("After Buffer assignment - sdram_conf (0x1400): %08x\n",
- GTREGREAD (SDRAM_CONFIG));
-
- /* SDRAM timing To_do: */
-/* ------------------------------------------------------------------------------ */
- /* ronen db64460 */
- debug
- ("setting up sdram_timing_control_high (0x140c) with: %08x \n",
- 0xc);
- GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0xc);
-
- debug
- ("setting up sdram address pads control (0x14c0) with: %08x \n",
- 0x7d5014a);
- GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a);
-
- debug
- ("setting up sdram data pads control (0x14c4) with: %08x \n",
- 0x7d5014a);
- GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a);
-
-/* ------------------------------------------------------------------------------ */
-
- /* set the SDRAM configuration for each bank */
-
-/* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
- {
- i = info->slot;
- debug
- ("\n*** Running a MRS cycle for bank %d ***\n", i);
-
- /* map the bank */
- memory_map_bank (i, 0, GB / 4);
-
- /* set SDRAM mode */ /* To_do check it */
- GT_REG_WRITE (SDRAM_OPERATION, 0x3);
- check = GTREGREAD (SDRAM_OPERATION);
- debug
- ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
- check);
-
-
- /* switch back to normal operation mode */
- GT_REG_WRITE (SDRAM_OPERATION, 0);
- check = GTREGREAD (SDRAM_OPERATION);
- debug
- ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
- check);
-
- /* unmap the bank */
- memory_map_bank (i, 0, 0);
- }
-
- return 0;
-
-}
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-long int dram_size (long int *base, long int maxsize)
-{
- volatile long int *addr, *b = base;
- long int cnt, val, save1, save2;
-
-#define STARTVAL (1<<20) /* start test at 1M */
- for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
- cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save1 = *addr; /* save contents of addr */
- save2 = *b; /* save contents of base */
-
- *addr = cnt; /* write cnt to addr */
- *b = 0; /* put null at base */
-
- /* check at base address */
- if ((*b) != 0) {
- *addr = save1; /* restore *addr */
- *b = save2; /* restore *b */
- return (0);
- }
- val = *addr; /* read *addr */
- val = *addr; /* read *addr */
-
- *addr = save1;
- *b = save2;
-
- if (val != cnt) {
- debug
- ("Found %08x at Address %08x (failure)\n",
- (unsigned int) val, (unsigned int) addr);
- /* fix boundary condition.. STARTVAL means zero */
- if (cnt == STARTVAL / sizeof (long))
- cnt = 0;
- return (cnt * sizeof (long));
- }
- }
- return maxsize;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* ppcboot interface function to SDRAM init - this is where all the
- * controlling logic happens */
-phys_size_t initdram (int board_type)
-{
- int checkbank[4] = {[0 ... 3] = 0 };
- ulong realsize, total;
- AUX_MEM_DIMM_INFO dimmInfo1;
- AUX_MEM_DIMM_INFO dimmInfo2;
- int nhr, bank_no;
- ulong dest, memSpaceAttr;
-
- /* first, use the SPD to get info about the SDRAM/ DDRRAM */
-
- /* check the NHR bit and skip mem init if it's already done */
- nhr = get_hid0 () & (1 << 16);
-
- if (nhr) {
- printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n");
- } else {
- /* DIMM0 */
- check_dimm (0, &dimmInfo1);
-
- /* DIMM1 */
- check_dimm (1, &dimmInfo2);
-
- memory_map_bank (0, 0, 0);
- memory_map_bank (1, 0, 0);
- memory_map_bank (2, 0, 0);
- memory_map_bank (3, 0, 0);
-
- /* ronen check correct set of DIMMS */
- if (dimmInfo1.numOfModuleBanks && dimmInfo2.numOfModuleBanks) {
- if (dimmInfo1.errorCheckType !=
- dimmInfo2.errorCheckType)
- printf ("***WARNNING***!!!! different ECC support of the DIMMS\n");
- if (dimmInfo1.maxClSupported_DDR !=
- dimmInfo2.maxClSupported_DDR)
- printf ("***WARNNING***!!!! different CAL setting of the DIMMS\n");
- if (dimmInfo1.registeredAddrAndControlInputs !=
- dimmInfo2.registeredAddrAndControlInputs)
- printf ("***WARNNING***!!!! different Registration setting of the DIMMS\n");
- }
-
- if (dimmInfo1.numOfModuleBanks && setup_sdram (&dimmInfo1)) {
- printf ("Setup for DIMM1 failed.\n");
- }
-
- if (dimmInfo2.numOfModuleBanks && setup_sdram (&dimmInfo2)) {
- printf ("Setup for DIMM2 failed.\n");
- }
-
- /* set the NHR bit */
- set_hid0 (get_hid0 () | (1 << 16));
- }
- /* next, size the SDRAM banks */
-
- realsize = total = 0;
- if (dimmInfo1.numOfModuleBanks > 0) {
- checkbank[0] = 1;
- }
- if (dimmInfo1.numOfModuleBanks > 1) {
- checkbank[1] = 1;
- }
- if (dimmInfo1.numOfModuleBanks > 2)
- printf ("Error, SPD claims DIMM1 has >2 banks\n");
-
- printf ("-- DIMM1 has %d banks\n", dimmInfo1.numOfModuleBanks);
-
- if (dimmInfo2.numOfModuleBanks > 0) {
- checkbank[2] = 1;
- }
- if (dimmInfo2.numOfModuleBanks > 1) {
- checkbank[3] = 1;
- }
- if (dimmInfo2.numOfModuleBanks > 2)
- printf ("Error, SPD claims DIMM2 has >2 banks\n");
-
- printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks);
-
- for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
- /* skip over banks that are not populated */
- if (!checkbank[bank_no])
- continue;
-
- /* ronen - realsize = dram_size((long int *)total, check); */
- if (bank_no == 0 || bank_no == 1) {
- if (checkbank[1] == 1)
- realsize = dimmInfo1.size / 2;
- else
- realsize = dimmInfo1.size;
- }
- if (bank_no == 2 || bank_no == 3) {
- if (checkbank[3] == 1)
- realsize = dimmInfo2.size / 2;
- else
- realsize = dimmInfo2.size;
- }
- memory_map_bank (bank_no, total, realsize);
-
- /* ronen - initialize the DRAM for ECC */
-#ifdef CONFIG_MV64460_ECC
- if ((dimmInfo1.errorCheckType != 0) &&
- ((dimmInfo2.errorCheckType != 0)
- || (dimmInfo2.numOfModuleBanks == 0))) {
- printf ("ECC Initialization of Bank %d:", bank_no);
- memSpaceAttr = ((~(BIT0 << bank_no)) & 0xf) << 8;
- mvDmaSetMemorySpace (0, 0, memSpaceAttr, total,
- realsize);
- for (dest = total; dest < total + realsize;
- dest += _8M) {
- mvDmaTransfer (0, total, dest, _8M,
- BIT8 /*DMA_DTL_128BYTES */ |
- BIT3 /*DMA_HOLD_SOURCE_ADDR */
- |
- BIT11
- /*DMA_BLOCK_TRANSFER_MODE */ );
- while (mvDmaIsChannelActive (0));
- }
- printf (" PASS\n");
- }
-#endif
-
- total += realsize;
- }
-
- /* ronen */
- switch ((GTREGREAD (0x141c) >> 4) & 0x7) {
- case 0x2:
- printf ("CAS Latency = 2");
- break;
- case 0x3:
- printf ("CAS Latency = 3");
- break;
- case 0x5:
- printf ("CAS Latency = 1.5");
- break;
- case 0x6:
- printf ("CAS Latency = 2.5");
- break;
- }
- printf (" tRP = %d tRAS = %d tRCD=%d\n",
- ((GTREGREAD (0x1408) >> 8) & 0xf) + 1,
- ((GTREGREAD (0x1408) >> 20) & 0xf) + 1,
- ((GTREGREAD (0x1408) >> 4) & 0xf) + 1);
-
-/* Setup Ethernet DMA Adress window to DRAM Area */
- if (total > _256M)
- printf ("*** ONLY the first 256MB DRAM memory are used out of the ");
- else
- printf ("Total SDRAM memory is ");
- /* (cause all the 4 BATS are taken) */
- return (total);
-}
-
-
-/* ronen- add Idma functions for usage of the ecc dram init. */
-/*******************************************************************************
-* mvDmaIsChannelActive - Checks if a engine is busy.
-********************************************************************************/
-int mvDmaIsChannelActive (int engine)
-{
- ulong data;
-
- data = GTREGREAD (MV64460_DMA_CHANNEL0_CONTROL + 4 * engine);
- if (data & BIT14 /*activity status */ ) {
- return 1;
- }
- return 0;
-}
-
-/*******************************************************************************
-* mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding
-* map.
-*******************************************************************************/
-int mvDmaSetMemorySpace (ulong memSpace,
- ulong memSpaceTarget,
- ulong memSpaceAttr, ulong baseAddress, ulong size)
-{
- ulong temp;
-
- /* The base address must be aligned to the size. */
- if (baseAddress % size != 0) {
- return 0;
- }
- if (size >= 0x10000 /*64K */ ) {
- size &= 0xffff0000;
- baseAddress = (baseAddress & 0xffff0000);
- /* Set the new attributes */
- GT_REG_WRITE (MV64460_DMA_BASE_ADDR_REG0 + memSpace * 8,
- (baseAddress | memSpaceTarget | memSpaceAttr));
- GT_REG_WRITE ((MV64460_DMA_SIZE_REG0 + memSpace * 8),
- (size - 1) & 0xffff0000);
- temp = GTREGREAD (MV64460_DMA_BASE_ADDR_ENABLE_REG);
- GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG,
- (temp & ~(BIT0 << memSpace)));
- return 1;
- }
- return 0;
-}
-
-
-/*******************************************************************************
-* mvDmaTransfer - Transfer data from sourceAddr to destAddr on one of the 4
-* DMA channels.
-********************************************************************************/
-int mvDmaTransfer (int engine, ulong sourceAddr,
- ulong destAddr, ulong numOfBytes, ulong command)
-{
- ulong engOffReg = 0; /* Engine Offset Register */
-
- if (numOfBytes > 0xffff) {
- command = command | BIT31 /*DMA_16M_DESCRIPTOR_MODE */ ;
- }
- command = command | ((command >> 6) & 0x7);
- engOffReg = engine * 4;
- GT_REG_WRITE (MV64460_DMA_CHANNEL0_BYTE_COUNT + engOffReg,
- numOfBytes);
- GT_REG_WRITE (MV64460_DMA_CHANNEL0_SOURCE_ADDR + engOffReg,
- sourceAddr);
- GT_REG_WRITE (MV64460_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg,
- destAddr);
- command =
- command | BIT12 /*DMA_CHANNEL_ENABLE */ | BIT9
- /*DMA_NON_CHAIN_MODE */ ;
- /* Activate DMA engine By writting to mvDmaControlRegister */
- GT_REG_WRITE (MV64460_DMA_CHANNEL0_CONTROL + engOffReg, command);
- return 1;
-}
-
-/****************************************************************************************
- * SDRAM INIT *
- * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb *
- * This procedure fits only the Atlantis *
- * *
- ***************************************************************************************/
-
-
-/****************************************************************************************
- * DFCDL initialize MV643xx Design Considerations *
- * *
- ***************************************************************************************/
-int set_dfcdlInit (void)
-{
- /*ronen the dfcdl init are done by the I2C */
- return (0);
-}
if TARGET_DKB
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "dkb"
if TARGET_GPLUGD
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "gplugd"
+++ /dev/null
-/* Core.h - Basic core logic functions and definitions */
-
-/* Copyright Galileo Technology. */
-
-/*
-DESCRIPTION
-This header file contains simple read/write macros for addressing
-the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address
-space). The macros take care of Big/Little endian conversions.
-*/
-
-#ifndef __INCcoreh
-#define __INCcoreh
-
-#include "mv_gen_reg.h"
-
-extern unsigned int INTERNAL_REG_BASE_ADDR;
-
-/****************************************/
-/* GENERAL Definitions */
-/****************************************/
-
-#define NO_BIT 0x00000000
-#define BIT0 0x00000001
-#define BIT1 0x00000002
-#define BIT2 0x00000004
-#define BIT3 0x00000008
-#define BIT4 0x00000010
-#define BIT5 0x00000020
-#define BIT6 0x00000040
-#define BIT7 0x00000080
-#define BIT8 0x00000100
-#define BIT9 0x00000200
-#define BIT10 0x00000400
-#define BIT11 0x00000800
-#define BIT12 0x00001000
-#define BIT13 0x00002000
-#define BIT14 0x00004000
-#define BIT15 0x00008000
-#define BIT16 0x00010000
-#define BIT17 0x00020000
-#define BIT18 0x00040000
-#define BIT19 0x00080000
-#define BIT20 0x00100000
-#define BIT21 0x00200000
-#define BIT22 0x00400000
-#define BIT23 0x00800000
-#define BIT24 0x01000000
-#define BIT25 0x02000000
-#define BIT26 0x04000000
-#define BIT27 0x08000000
-#define BIT28 0x10000000
-#define BIT29 0x20000000
-#define BIT30 0x40000000
-#define BIT31 0x80000000
-
-#define _1K 0x00000400
-#define _2K 0x00000800
-#define _4K 0x00001000
-#define _8K 0x00002000
-#define _16K 0x00004000
-#define _32K 0x00008000
-#define _64K 0x00010000
-#define _128K 0x00020000
-#define _256K 0x00040000
-#define _512K 0x00080000
-
-#define _1M 0x00100000
-#define _2M 0x00200000
-#define _3M 0x00300000
-#define _4M 0x00400000
-#define _5M 0x00500000
-#define _6M 0x00600000
-#define _7M 0x00700000
-#define _8M 0x00800000
-#define _9M 0x00900000
-#define _10M 0x00a00000
-#define _11M 0x00b00000
-#define _12M 0x00c00000
-#define _13M 0x00d00000
-#define _14M 0x00e00000
-#define _15M 0x00f00000
-#define _16M 0x01000000
-
-#define _32M 0x02000000
-#define _64M 0x04000000
-#define _128M 0x08000000
-#define _256M 0x10000000
-#define _512M 0x20000000
-
-#define _1G 0x40000000
-#define _2G 0x80000000
-
-/* Little to Big endian conversion macros */
-
-#ifdef LE /* Little Endian */
-#define SHORT_SWAP(X) (X)
-#define WORD_SWAP(X) (X)
-#define LONG_SWAP(X) ((l64)(X))
-
-#else /* Big Endian */
-#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8))
-
-#define WORD_SWAP(X) (((X)&0xff)<<24)+ \
- (((X)&0xff00)<<8)+ \
- (((X)&0xff0000)>>8)+ \
- (((X)&0xff000000)>>24)
-
-#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+ \
- (((X)&0xff00ULL)<<40)+ \
- (((X)&0xff0000ULL)<<24)+ \
- (((X)&0xff000000ULL)<<8)+ \
- (((X)&0xff00000000ULL)>>8)+ \
- (((X)&0xff0000000000ULL)>>24)+ \
- (((X)&0xff000000000000ULL)>>40)+ \
- (((X)&0xff00000000000000ULL)>>56))
-
-#endif
-
-#ifndef NULL
-#define NULL 0
-#endif
-
-/* Those two definitions were defined to be compatible with MIPS */
-#define NONE_CACHEABLE 0x00000000
-#define CACHEABLE 0x00000000
-
-/* 750 cache line */
-#define CACHE_LINE_SIZE 32
-#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1)
-#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS)
-
-/* Read/Write to/from GT`s internal registers */
-#define GT_REG_READ(offset, pData) \
-*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE | \
- INTERNAL_REG_BASE_ADDR | (offset))) ) ; \
-*pData = WORD_SWAP(*pData)
-
-#define GTREGREAD(offset) \
- (WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE | \
- INTERNAL_REG_BASE_ADDR | (offset))) ))
-
-#define GT_REG_WRITE(offset, data) \
-*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) = \
- WORD_SWAP(data)
-
-/* Write 32/16/8 bit */
-#define WRITE_CHAR(address, data) \
- *((unsigned char *)(address)) = data
-#define WRITE_SHORT(address, data) \
- *((unsigned short *)(address)) = data
-#define WRITE_WORD(address, data) \
- *((unsigned int *)(address)) = data
-
-#define GT_WRITE_CHAR(address, data) WRITE_CHAR(address, data)
-
-/* Write 32/16/8 bit NonCacheable */
-/*
-#define GT_WRITE_CHAR(address, data) \
- (*((unsigned char *)NONE_CACHEABLE(address))) = data
-#define GT_WRITE_SHORT(address, data) \
- (*((unsigned short *)NONE_CACHEABLE(address))) = data
-#define GT_WRITE_WORD(address, data) \
- (*((unsigned int *)NONE_CACHEABLE(address))) = data
-*/
- /*#define GT_WRITE_CHAR(address, data) ((*((volatile unsigned char *)NONE_CACHEABLE((address)))) = ((unsigned char)(data)))1 */
-
- /*#define GT_WRITE_SHORT(address, data) ((*((volatile unsigned short *)NONE_CACHEABLE((address)))) = ((unsigned short)(data)))1 */
-
- /*#define GT_WRITE_WORD(address, data) ((*((volatile unsigned int *)NONE_CACHEABLE((address)))) = ((unsigned int)(data)))1 */
-
-
-/* Read 32/16/8 bits - returns data in variable. */
-#define READ_CHAR(address, pData) \
- *pData = *((volatile unsigned char *)(address))
-
-#define READ_SHORT(address, pData) \
- *pData = *((volatile unsigned short *)(address))
-
-#define READ_WORD(address, pData) \
- *pData = *((volatile unsigned int *)(address))
-
-/* Read 32/16/8 bit - returns data direct. */
-#define READCHAR(address) \
- *((volatile unsigned char *)((address) | NONE_CACHEABLE))
-
-#define READSHORT(address) \
- *((volatile unsigned short *)((address) | NONE_CACHEABLE))
-
-#define READWORD(address) \
- *((volatile unsigned int *)((address) | NONE_CACHEABLE))
-
-/* Those two Macros were defined to be compatible with MIPS */
-#define VIRTUAL_TO_PHY(x) (((unsigned int)x) & 0xffffffff)
-#define PHY_TO_VIRTUAL(x) (((unsigned int)x) | NONE_CACHEABLE)
-
-/* SET_REG_BITS(regOffset,bits) -
- gets register offset and bits: a 32bit value. It set to logic '1' in the
- internal register the bits which given as an input example:
- SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
- '1' in register 0x840 while the other bits stays as is. */
-#define SET_REG_BITS(regOffset,bits) \
- *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | \
- regOffset) |= (unsigned int)WORD_SWAP(bits)
-
-/* RESET_REG_BITS(regOffset,bits) -
- gets register offset and bits: a 32bit value. It set to logic '0' in the
- internal register the bits which given as an input example:
- RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
- '0' in register 0x840 while the other bits stays as is. */
-#define RESET_REG_BITS(regOffset,bits) \
- *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR \
- | regOffset) &= ~( (unsigned int)WORD_SWAP(bits) )
-/* gets register offset and bits: a 32bit value. It set to logic '1' in the
- internal register the bits which given as an input example:
- GT_SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
- '1' in register 0x840 while the other bits stays as is. */
- /*#define GT_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) | (regOffset)))) |= ((unsigned int)WORD_SWAP(bits)))1 */
- /*#define GT_SET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits)1 */
-#define GT_SET_REG_BITS(regOffset,bits) SET_REG_BITS(regOffset,bits)
-/* gets register offset and bits: a 32bit value. It set to logic '0' in the
- internal register the bits which given as an input example:
- GT_RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to
- logic '0' in register 0x840 while the other bits stays as is. */
- /*#define GT_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) | (regOffset)))) &= ~((unsigned int)WORD_SWAP(bits)))1 */
-#define GT_RESET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits)
-
-
-#define DEBUG_LED0_ON() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x8000,0)
-#define DEBUG_LED1_ON() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0xc000,0)
-#define DEBUG_LED2_ON() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x10000,0)
-#define DEBUG_LED0_OFF() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x14000,0)
-#define DEBUG_LED1_OFF() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x18000,0)
-#define DEBUG_LED2_OFF() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x1c000,0)
-
-#endif /* __INCcoreh */
+++ /dev/null
-/* mv_gen_reg.h - Internal registers definition file */
-/* Copyright - Galileo technology. */
-
-
-/*******************************************************************************
-* Copyright 2002, GALILEO TECHNOLOGY, LTD. *
-* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. *
-* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT *
-* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE *
-* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. *
-* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, *
-* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. *
-* *
-* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, *
-* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL *
-* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. *
-* (MJKK), GALILEO TECHNOLOGY LTD. (GTL) AND GALILEO TECHNOLOGY, INC. (GTI). *
-********************************************************************************
-* mv_gen_reg.h - Marvell 64360 and 64460 Internal registers definition file.
-*
-* DESCRIPTION:
-* None.
-*
-* DEPENDENCIES:
-* None.
-*
-*******************************************************************************/
-
-#ifndef __INCmv_gen_regh
-#define __INCmv_gen_regh
-
-
-/* Supported by the Atlantis */
-#define INCLUDE_PCI_1
-#define INCLUDE_PCI_0_ARBITER
-#define INCLUDE_PCI_1_ARBITER
-#define INCLUDE_SNOOP_SUPPORT
-#define INCLUDE_P2P
-#define INCLUDE_ETH_PORT_2
-#define INCLUDE_CPU_MAPPING
-#define INCLUDE_MPSC
-
-/* Not supported features */
-#undef INCLUDE_CNTMR_4_7
-#undef INCLUDE_DMA_4_7
-
-
-/****************************************/
-/* Processor Address Space */
-/****************************************/
-/* DDR SDRAM BAR and size registers */
-
-/* Sdram's BAR'S */
-#define SCS_0_LOW_DECODE_ADDRESS 0x008
-#define SCS_0_HIGH_DECODE_ADDRESS 0x010
-#define SCS_1_LOW_DECODE_ADDRESS 0x208
-#define SCS_1_HIGH_DECODE_ADDRESS 0x210
-#define SCS_2_LOW_DECODE_ADDRESS 0x018
-#define SCS_2_HIGH_DECODE_ADDRESS 0x020
-#define SCS_3_LOW_DECODE_ADDRESS 0x218
-#define SCS_3_HIGH_DECODE_ADDRESS 0x220
-
-/* Make it fit the MV64360 and MV64460 Lowlevel driver */
-#define CS_0_BASE_ADDR SCS_0_LOW_DECODE_ADDRESS
-#define CS_0_SIZE SCS_0_HIGH_DECODE_ADDRESS
-#define CS_1_BASE_ADDR SCS_1_LOW_DECODE_ADDRESS
-#define CS_1_SIZE SCS_1_HIGH_DECODE_ADDRESS
-#define CS_2_BASE_ADDR SCS_2_LOW_DECODE_ADDRESS
-#define CS_2_SIZE SCS_2_HIGH_DECODE_ADDRESS
-#define CS_3_BASE_ADDR SCS_3_LOW_DECODE_ADDRESS
-#define CS_3_SIZE SCS_3_HIGH_DECODE_ADDRESS
-
-/* Devices BAR'S */
-#define CS_0_LOW_DECODE_ADDRESS 0x028
-#define CS_0_HIGH_DECODE_ADDRESS 0x030
-#define CS_1_LOW_DECODE_ADDRESS 0x228
-#define CS_1_HIGH_DECODE_ADDRESS 0x230
-#define CS_2_LOW_DECODE_ADDRESS 0x248
-#define CS_2_HIGH_DECODE_ADDRESS 0x250
-#define CS_3_LOW_DECODE_ADDRESS 0x038
-#define CS_3_HIGH_DECODE_ADDRESS 0x040
-#define BOOTCS_LOW_DECODE_ADDRESS 0x238
-#define BOOTCS_HIGH_DECODE_ADDRESS 0x240
-
-/* Make it fit the MV64360 and MV64460 Lowlevel driver */
-/* Devices BAR and size registers */
-
-#define DEV_CS0_BASE_ADDR CS_0_LOW_DECODE_ADDRESS
-#define DEV_CS0_SIZE CS_0_HIGH_DECODE_ADDRESS
-#define DEV_CS1_BASE_ADDR CS_1_LOW_DECODE_ADDRESS
-#define DEV_CS1_SIZE CS_1_HIGH_DECODE_ADDRESS
-#define DEV_CS2_BASE_ADDR CS_2_LOW_DECODE_ADDRESS
-#define DEV_CS2_SIZE CS_2_HIGH_DECODE_ADDRESS
-#define DEV_CS3_BASE_ADDR CS_3_LOW_DECODE_ADDRESS
-#define DEV_CS3_SIZE CS_3_HIGH_DECODE_ADDRESS
-#define BOOTCS_BASE_ADDR BOOTCS_LOW_DECODE_ADDRESS
-#define BOOTCS_SIZE BOOTCS_HIGH_DECODE_ADDRESS
-
-/* PCI 0 BAR and size registers old names of evb64260*/
-
-#define PCI_0I_O_LOW_DECODE_ADDRESS 0x048
-#define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050
-#define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058
-#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060
-#define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080
-#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088
-#define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258
-#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260
-#define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280
-#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288
-
-/* Make it fit the MV64360 and MV64460 Lowlevel driver */
-#define PCI_0_IO_BASE_ADDR 0x048
-#define PCI_0_IO_SIZE 0x050
-#define PCI_0_MEMORY0_BASE_ADDR 0x058
-#define PCI_0_MEMORY0_SIZE 0x060
-#define PCI_0_MEMORY1_BASE_ADDR 0x080
-#define PCI_0_MEMORY1_SIZE 0x088
-#define PCI_0_MEMORY2_BASE_ADDR 0x258
-#define PCI_0_MEMORY2_SIZE 0x260
-#define PCI_0_MEMORY3_BASE_ADDR 0x280
-#define PCI_0_MEMORY3_SIZE 0x288
-
-/* PCI 1 BAR and size registers old names of evb64260*/
-#define PCI_1I_O_LOW_DECODE_ADDRESS 0x090
-#define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098
-#define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0
-#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8
-#define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0
-#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8
-#define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0
-#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8
-#define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0
-#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8
-
-/* Make it fit the MV64360 and MV64460 Lowlevel driver */
-#define PCI_1_IO_BASE_ADDR 0x090
-#define PCI_1_IO_SIZE 0x098
-#define PCI_1_MEMORY0_BASE_ADDR 0x0a0
-#define PCI_1_MEMORY0_SIZE 0x0a8
-#define PCI_1_MEMORY1_BASE_ADDR 0x0b0
-#define PCI_1_MEMORY1_SIZE 0x0b8
-#define PCI_1_MEMORY2_BASE_ADDR 0x2a0
-#define PCI_1_MEMORY2_SIZE 0x2a8
-#define PCI_1_MEMORY3_BASE_ADDR 0x2b0
-#define PCI_1_MEMORY3_SIZE 0x2b8
-
-/* internal registers space base address */
-#define INTERNAL_SPACE_DECODE 0x068
-#define INTERNAL_SPACE_BASE_ADDR INTERNAL_SPACE_DECODE
-
-/* SRAM base address */
-#define INTEGRATED_SRAM_BASE_ADDR 0x268
-
-/* Enables the CS , DEV_CS , PCI 0 and PCI 1
- windows above */
-#define BASE_ADDR_ENABLE 0x278
-
-
-#define CPU_0_LOW_DECODE_ADDRESS 0x290
-#define CPU_0_HIGH_DECODE_ADDRESS 0x298
-#define CPU_1_LOW_DECODE_ADDRESS 0x2c0
-#define CPU_1_HIGH_DECODE_ADDRESS 0x2c8
-
-/****************************************/
-/* PCI remap registers */
-/****************************************/
-/*****************************************************************************************/
- /* PCI 0 */
-/* old fashion evb 64260 */
-#define PCI_0I_O_ADDRESS_REMAP 0x0f0
-#define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8
-#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320
-#define PCI_0MEMORY1_ADDRESS_REMAP 0x100
-#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328
-#define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8
-#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330
-#define PCI_0MEMORY3_ADDRESS_REMAP 0x300
-#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338
-
-#define PCI_0_IO_ADDR_REMAP PCI_0I_O_ADDRESS_REMAP
-#define PCI_0_MEMORY0_LOW_ADDR_REMAP PCI_0MEMORY0_ADDRESS_REMAP
-#define PCI_0_MEMORY0_HIGH_ADDR_REMAP PCI_0MEMORY0_HIGH_ADDRESS_REMAP
-#define PCI_0_MEMORY1_LOW_ADDR_REMAP PCI_0MEMORY1_ADDRESS_REMAP
-#define PCI_0_MEMORY1_HIGH_ADDR_REMAP PCI_0MEMORY1_HIGH_ADDRESS_REMAP
-#define PCI_0_MEMORY2_LOW_ADDR_REMAP PCI_0MEMORY2_ADDRESS_REMAP
-#define PCI_0_MEMORY2_HIGH_ADDR_REMAP PCI_0MEMORY2_HIGH_ADDRESS_REMAP
-#define PCI_0_MEMORY3_LOW_ADDR_REMAP PCI_0MEMORY3_ADDRESS_REMAP
-#define PCI_0_MEMORY3_HIGH_ADDR_REMAP PCI_0MEMORY3_HIGH_ADDRESS_REMAP
-
- /* PCI 1 */
-/* old fashion evb 64260 */
-#define PCI_1I_O_ADDRESS_REMAP 0x108
-#define PCI_1MEMORY0_ADDRESS_REMAP 0x110
-#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340
-#define PCI_1MEMORY1_ADDRESS_REMAP 0x118
-#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348
-#define PCI_1MEMORY2_ADDRESS_REMAP 0x310
-#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350
-#define PCI_1MEMORY3_ADDRESS_REMAP 0x318
-#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358
-
-#define PCI_1_IO_ADDR_REMAP PCI_1I_O_ADDRESS_REMAP
-#define PCI_1_MEMORY0_LOW_ADDR_REMAP PCI_1MEMORY0_ADDRESS_REMAP
-#define PCI_1_MEMORY0_HIGH_ADDR_REMAP PCI_1MEMORY0_HIGH_ADDRESS_REMAP
-#define PCI_1_MEMORY1_LOW_ADDR_REMAP PCI_1MEMORY1_ADDRESS_REMAP
-#define PCI_1_MEMORY1_HIGH_ADDR_REMAP PCI_1MEMORY1_HIGH_ADDRESS_REMAP
-#define PCI_1_MEMORY2_LOW_ADDR_REMAP PCI_1MEMORY2_ADDRESS_REMAP
-#define PCI_1_MEMORY2_HIGH_ADDR_REMAP PCI_1MEMORY2_HIGH_ADDRESS_REMAP
-#define PCI_1_MEMORY3_LOW_ADDR_REMAP PCI_1MEMORY3_ADDRESS_REMAP
-#define PCI_1_MEMORY3_HIGH_ADDR_REMAP PCI_1MEMORY3_HIGH_ADDRESS_REMAP
-
-/* old fashion evb 64260 */
-#define CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0
-#define CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8
-#define CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0
-#define CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8
-#define CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0
-#define CPU_GE_HEADERS_RETARGET_BASE 0x3d8
-
-/* MV64360 and MV64460 no changes needed*/
-/*****************************************************************************************/
-
-/****************************************/
-/* CPU Control Registers */
-/****************************************/
-/* CPU MASTER CONTROL REGISTER */
-#define CPU_CONFIGURATION 0x000
-#define CPU_MASTER_CONTROL 0x160
-
-#define CPU_CONFIG 0x000
-#define CPU_MODE 0x120
-#define CPU_MASTER_CONTROL 0x160
-/* new in MV64360 and MV64460 */
-#define CPU_CROSS_BAR_CONTROL_LOW 0x150
-#define CPU_CROSS_BAR_CONTROL_HIGH 0x158
-#define CPU_CROSS_BAR_TIMEOUT 0x168
-
-/****************************************/
-/* SMP RegisterS */
-/****************************************/
-
-#define SMP_WHO_AM_I 0x200
-#define SMP_CPU0_DOORBELL 0x214
-#define SMP_CPU0_DOORBELL_CLEAR 0x21C
-#define SMP_CPU1_DOORBELL 0x224
-#define SMP_CPU1_DOORBELL_CLEAR 0x22C
-#define SMP_CPU0_DOORBELL_MASK 0x234
-#define SMP_CPU1_DOORBELL_MASK 0x23C
-#define SMP_SEMAPHOR0 0x244
-#define SMP_SEMAPHOR1 0x24c
-#define SMP_SEMAPHOR2 0x254
-#define SMP_SEMAPHOR3 0x25c
-#define SMP_SEMAPHOR4 0x264
-#define SMP_SEMAPHOR5 0x26c
-#define SMP_SEMAPHOR6 0x274
-#define SMP_SEMAPHOR7 0x27c
-
-
-/****************************************/
-/* CPU Sync Barrier */
-/****************************************/
-#define CPU_0_SYNC_BARRIER_TRIGGER 0x0c0
-#define CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8
-#define CPU_1_SYNC_BARRIER_TRIGGER 0x0d0
-#define CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8
-
-
-/****************************************/
-/* CPU Access Protect */
-/****************************************/
-
-#define CPU_LOW_PROTECT_ADDRESS_0 0x180
-#define CPU_HIGH_PROTECT_ADDRESS_0 0x188
-#define CPU_LOW_PROTECT_ADDRESS_1 0x190
-#define CPU_HIGH_PROTECT_ADDRESS_1 0x198
-#define CPU_LOW_PROTECT_ADDRESS_2 0x1a0
-#define CPU_HIGH_PROTECT_ADDRESS_2 0x1a8
-#define CPU_LOW_PROTECT_ADDRESS_3 0x1b0
-#define CPU_HIGH_PROTECT_ADDRESS_3 0x1b8
-/*#define CPU_LOW_PROTECT_ADDRESS_4 0x1c0
-#define CPU_HIGH_PROTECT_ADDRESS_4 0x1c8
-#define CPU_LOW_PROTECT_ADDRESS_5 0x1d0
-#define CPU_HIGH_PROTECT_ADDRESS_5 0x1d8
-#define CPU_LOW_PROTECT_ADDRESS_6 0x1e0
-#define CPU_HIGH_PROTECT_ADDRESS_6 0x1e8
-#define CPU_LOW_PROTECT_ADDRESS_7 0x1f0
-#define CPU_HIGH_PROTECT_ADDRESS_7 0x1f8
-*/
-
-#define CPU_PROTECT_WINDOW_0_BASE_ADDR CPU_LOW_PROTECT_ADDRESS_0 /* 0x180 */
-#define CPU_PROTECT_WINDOW_0_SIZE CPU_HIGH_PROTECT_ADDRESS_0 /* 0x188 */
-#define CPU_PROTECT_WINDOW_1_BASE_ADDR CPU_LOW_PROTECT_ADDRESS_1 /* 0x190 */
-#define CPU_PROTECT_WINDOW_1_SIZE CPU_HIGH_PROTECT_ADDRESS_1 /* 0x198 */
-#define CPU_PROTECT_WINDOW_2_BASE_ADDR CPU_LOW_PROTECT_ADDRESS_2 /*0x1a0 */
-#define CPU_PROTECT_WINDOW_2_SIZE CPU_HIGH_PROTECT_ADDRESS_2 /* 0x1a8 */
-#define CPU_PROTECT_WINDOW_3_BASE_ADDR CPU_LOW_PROTECT_ADDRESS_3 /* 0x1b0 */
-#define CPU_PROTECT_WINDOW_3_SIZE CPU_HIGH_PROTECT_ADDRESS_3 /* 0x1b8 */
-
-
-/****************************************/
-/* Snoop Control */
-/****************************************/
-
-/*#define SNOOP_BASE_ADDRESS_0 0x380
-#define SNOOP_TOP_ADDRESS_0 0x388
-#define SNOOP_BASE_ADDRESS_1 0x390
-#define SNOOP_TOP_ADDRESS_1 0x398
-#define SNOOP_BASE_ADDRESS_2 0x3a0
-#define SNOOP_TOP_ADDRESS_2 0x3a8
-#define SNOOP_BASE_ADDRESS_3 0x3b0
-#define SNOOP_TOP_ADDRESS_3 0x3b8
-*/
-
-/****************************************/
-/* Integrated SRAM Registers */
-/****************************************/
-
-#define SRAM_CONFIG 0x380
-#define SRAM_TEST_MODE 0x3F4
-#define SRAM_ERROR_CAUSE 0x388
-#define SRAM_ERROR_ADDR 0x390
-#define SRAM_ERROR_ADDR_HIGH 0x3F8
-#define SRAM_ERROR_DATA_LOW 0x398
-#define SRAM_ERROR_DATA_HIGH 0x3a0
-#define SRAM_ERROR_DATA_PARITY 0x3a8
-
-/****************************************/
-/* CPU Error Report */
-/****************************************/
-
-#define CPU_ERROR_ADDRESS_LOW 0x070
-#define CPU_ERROR_ADDRESS_HIGH 0x078
-#define CPU_ERROR_DATA_LOW 0x128
-#define CPU_ERROR_DATA_HIGH 0x130
-#define CPU_ERROR_PARITY 0x138
-#define CPU_ERROR_CAUSE 0x140
-#define CPU_ERROR_MASK 0x148
-
-#define CPU_ERROR_ADDR_LOW CPU_ERROR_ADDRESS_LOW /* 0x0701 */
-#define CPU_ERROR_ADDR_HIGH CPU_ERROR_ADDRESS_HIGH /* 0x0781 */
-
-/****************************************/
-/* Pslave Debug */
-/* CPU Interface Debug Registers */
-/****************************************/
-
-#define X_0_ADDRESS 0x360
-#define X_0_COMMAND_ID 0x368
-#define X_1_ADDRESS 0x370
-#define X_1_COMMAND_ID 0x378
- /*#define WRITE_DATA_LOW 0x3c01 */
- /*#define WRITE_DATA_HIGH 0x3c81 */
- /*#define WRITE_BYTE_ENABLE 0x3e01 */
- /*#define READ_DATA_LOW 0x3d01 */
- /*#define READ_DATA_HIGH 0x3d81 */
- /*#define READ_ID 0x3e81 */
-
-#define PUNIT_SLAVE_DEBUG_LOW X_0_ADDRESS /* 0x3601 */
-#define PUNIT_SLAVE_DEBUG_HIGH X_0_COMMAND_ID /* 0x3681 */
-#define PUNIT_MASTER_DEBUG_LOW X_1_ADDRESS /* 0x3701 */
-#define PUNIT_MASTER_DEBUG_HIGH X_1_COMMAND_ID /* 0x3781 */
-#define PUNIT_MMASK 0x3e4
-
-
-/****************************************/
-/* SDRAM and Device Address Space */
-/****************************************/
-
-/****************************************/
-/* SDRAM Configuration */
-/****************************************/
-#define SDRAM_CONFIG 0x1400 /* MV64260 0x448 some changes*/
-#define D_UNIT_CONTROL_LOW 0x1404 /* NEW in MV64360 and MV64460 */
-#define D_UNIT_CONTROL_HIGH 0x1424 /* NEW in MV64360 and MV64460 */
-#define SDRAM_TIMING_CONTROL_LOW 0x1408 /* MV64260 0x4b4 new SDRAM TIMING REGISTER */
-#define SDRAM_TIMING_CONTROL_HIGH 0x140c /* MV64260 0x4b4 new SDRAM TIMING REGISTER */
-#define SDRAM_ADDR_CONTROL 0x1410 /* MV64260 0x47c some changes*/
-#define SDRAM_OPEN_PAGES_CONTROL 0x1414 /* NEW in MV64360 and MV64460 */
-#define SDRAM_OPERATION 0x1418 /* MV64260 0x474 some changes*/
-#define SDRAM_MODE 0x141c /* NEW in MV64360 and MV64460 */
-#define EXTENDED_DRAM_MODE 0x1420 /* NEW in MV64360 and MV64460 */
-#define SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 /* MV64260 0x4a8 NO changes*/
-#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 /* MV64260 0x4ac NO changes*/
-#define SDRAM_CROSS_BAR_TIMEOUT 0x1438 /* MV64260 0x4b0 NO changes*/
-#define SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 /* what is this ??? */
-#define SDRAM_DATA_PADS_CALIBRATION 0x14c4 /* what is this ??? */
-/****************************************/
-/* SDRAM Configuration MV64260 */
-/****************************************/
- /*#define SDRAM_CONFIGURATION 0x4481 */
- /*#define SDRAM_OPERATION_MODE 0x4741 */
- /*#define SDRAM_ADDRESS_DECODE 0x47c1 */
- /*#define SDRAM_UMA_CONTROL 0x4a4 eliminated in MV64360 and MV64460 */
- /*#define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a81 */
- /*#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac1 */
- /*#define SDRAM_CROSS_BAR_TIMEOUT 0x4b01 */
- /*#define SDRAM_TIMING 0x4b41 */
-
-
-/****************************************/
-/* SDRAM Error Report */
-/****************************************/
-#define SDRAM_ERROR_DATA_LOW 0x1444 /* MV64260 0x484 NO changes*/
-#define SDRAM_ERROR_DATA_HIGH 0x1440 /* MV64260 0x480 NO changes*/
-#define SDRAM_ERROR_ADDR 0x1450 /* MV64260 0x490 NO changes*/
-#define SDRAM_RECEIVED_ECC 0x1448 /* MV64260 0x488 NO changes*/
-#define SDRAM_CALCULATED_ECC 0x144c /* MV64260 0x48c NO changes*/
-#define SDRAM_ECC_CONTROL 0x1454 /* MV64260 0x494 NO changes*/
-#define SDRAM_ECC_ERROR_COUNTER 0x1458 /* MV64260 0x498 NO changes*/
-#define SDRAM_MMASK 0x1B40 /* NEW Register in MV64360 and MV64460 DO NOT USE !!!*/
-/****************************************/
-/* SDRAM Error Report MV64260 */
-/****************************************/
- /*#define SDRAM_ERROR_DATA_LOW 0x4841 */
- /*#define SDRAM_ERROR_DATA_HIGH 0x4801 */
- /*#define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x4901 */
- /*#define SDRAM_RECEIVED_ECC 0x4881 */
- /*#define SDRAM_CALCULATED_ECC 0x48c1 */
- /*#define SDRAM_ECC_CONTROL 0x4941 */
- /*#define SDRAM_ECC_ERROR_COUNTER 0x4981 */
-
-/******************************************/
-/* Controlled Delay Line (CDL) Registers */
-/******************************************/
-#define DFCDL_CONFIG0 0x1480
-#define DFCDL_CONFIG1 0x1484
-#define DLL_WRITE 0x1488
-#define DLL_READ 0x148c
-#define SRAM_ADDR 0x1490
-#define SRAM_DATA0 0x1494
-#define SRAM_DATA1 0x1498
-#define SRAM_DATA2 0x149c
-#define DFCL_PROBE 0x14a0
-
-
-/****************************************/
-/* SDRAM Parameters only in MV64260 */
-/****************************************/
-
- /*#define SDRAM_BANK0PARAMETERS 0x44C eliminated in MV64360 and MV64460 */
- /*#define SDRAM_BANK1PARAMETERS 0x450 eliminated in MV64360 and MV64460 */
- /*#define SDRAM_BANK2PARAMETERS 0x454 eliminated in MV64360 and MV64460 */
- /*#define SDRAM_BANK3PARAMETERS 0x458 eliminated in MV64360 and MV64460 */
-
-/******************************************/
-/* Debug Registers */
-/******************************************/
-
-#define DUNIT_DEBUG_LOW 0x1460
-#define DUNIT_DEBUG_HIGH 0x1464
-#define DUNIT_MMASK 0x1b40
-
-/****************************************/
-/* SDunit Debug (for internal use) */
-/****************************************/
-
-#define X0_ADDRESS 0x500
-#define X0_COMMAND_AND_ID 0x504
-#define X0_WRITE_DATA_LOW 0x508
-#define X0_WRITE_DATA_HIGH 0x50c
-#define X0_WRITE_BYTE_ENABLE 0x518
-#define X0_READ_DATA_LOW 0x510
-#define X0_READ_DATA_HIGH 0x514
-#define X0_READ_ID 0x51c
-#define X1_ADDRESS 0x520
-#define X1_COMMAND_AND_ID 0x524
-#define X1_WRITE_DATA_LOW 0x528
-#define X1_WRITE_DATA_HIGH 0x52c
-#define X1_WRITE_BYTE_ENABLE 0x538
-#define X1_READ_DATA_LOW 0x530
-#define X1_READ_DATA_HIGH 0x534
-#define X1_READ_ID 0x53c
-#define X0_SNOOP_ADDRESS 0x540
-#define X0_SNOOP_COMMAND 0x544
-#define X1_SNOOP_ADDRESS 0x548
-#define X1_SNOOP_COMMAND 0x54c
-
-/****************************************/
-/* Device Parameters */
-/****************************************/
-
-#define DEVICE_BANK0PARAMETERS 0x45c
-#define DEVICE_BANK1PARAMETERS 0x460
-#define DEVICE_BANK2PARAMETERS 0x464
-#define DEVICE_BANK3PARAMETERS 0x468
-#define DEVICE_BOOT_BANK_PARAMETERS 0x46c
-#define DEVICE_CONTROL 0x4c0
-#define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8
-#define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc
-#define DEVICE_CROSS_BAR_TIMEOUT 0x4c4
-
-/****************************************/
-/* Device Parameters */
-/****************************************/
-
-#define DEVICE_BANK0_PARAMETERS DEVICE_BANK0PARAMETERS /* 0x45c1 */
-#define DEVICE_BANK1_PARAMETERS DEVICE_BANK1PARAMETERS /* 0x4601 */
-#define DEVICE_BANK2_PARAMETERS DEVICE_BANK2PARAMETERS /* 0x4641 */
-#define DEVICE_BANK3_PARAMETERS DEVICE_BANK3PARAMETERS /* 0x4681 */
-/*#define DEVICE_BOOT_BANK_PARAMETERS 0x46c1 */
-#define DEVICE_INTERFACE_CONTROL DEVICE_CONTROL /* 0x4c01 */
-#define DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW DEVICE_CROSS_BAR_CONTROL_LOW /* 0x4c81 */
-#define DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH DEVICE_CROSS_BAR_CONTROL_HIGH /* 0x4cc1 */
-#define DEVICE_INTERFACE_CROSS_BAR_TIMEOUT DEVICE_CROSS_BAR_TIMEOUT /* 0x4c41 */
-
-
-/****************************************/
-/* Device Interrupt */
-/****************************************/
-
-#define DEVICE_INTERRUPT_CAUSE 0x4d0
-#define DEVICE_INTERRUPT_MASK 0x4d4
-#define DEVICE_ERROR_ADDRESS 0x4d8
- /*#define DEVICE_INTERRUPT_CAUSE 0x4d01 */
- /*#define DEVICE_INTERRUPT_MASK 0x4d41 */
-#define DEVICE_ERROR_ADDR DEVICE_ERROR_ADDRESS /*0x4d81 */
-#define DEVICE_ERROR_DATA 0x4dc
-#define DEVICE_ERROR_PARITY 0x4e0
-
-/****************************************/
-/* Device debug registers */
-/****************************************/
-
-#define DEVICE_DEBUG_LOW 0x4e4
-#define DEVICE_DEBUG_HIGH 0x4e8
-#define RUNIT_MMASK 0x4f0
-
-/****************************************/
-/* DMA Record */
-/****************************************/
-
- /*#define CHANNEL4_DMA_BYTE_COUNT 0x9001 */
- /*#define CHANNEL5_DMA_BYTE_COUNT 0x9041 */
- /*#define CHANNEL6_DMA_BYTE_COUNT 0x9081 */
- /*#define CHANNEL7_DMA_BYTE_COUNT 0x90C1 */
- /*#define CHANNEL4_DMA_SOURCE_ADDRESS 0x9101 */
- /*#define CHANNEL5_DMA_SOURCE_ADDRESS 0x9141 */
- /*#define CHANNEL6_DMA_SOURCE_ADDRESS 0x9181 */
- /*#define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C1 */
- /*#define CHANNEL4_DMA_DESTINATION_ADDRESS 0x9201 */
- /*#define CHANNEL5_DMA_DESTINATION_ADDRESS 0x9241 */
- /*#define CHANNEL6_DMA_DESTINATION_ADDRESS 0x9281 */
- /*#define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C1 */
- /*#define CHANNEL4NEXT_RECORD_POINTER 0x9301 */
- /*#define CHANNEL5NEXT_RECORD_POINTER 0x9341 */
- /*#define CHANNEL6NEXT_RECORD_POINTER 0x9381 */
- /*#define CHANNEL7NEXT_RECORD_POINTER 0x93C1 */
- /*#define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x9701 */
- /*#define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x9741 */
- /*#define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x9781 */
- /*#define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C1 */
- /*#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x8901 */
- /*#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x8941 */
- /*#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x8981 */
- /*#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c1 */
- /*#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x9901 */
- /*#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x9941 */
- /*#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x9981 */
- /*#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c1 */
- /*#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a01 */
- /*#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a41 */
- /*#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a81 */
- /*#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac1 */
- /*#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a01 */
- /*#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a41 */
- /*#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a81 */
- /*#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac1 */
- /*#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b01 */
- /*#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b41 */
- /*#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b81 */
- /*#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc1 */
- /*#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b01 */
- /*#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b41 */
- /*#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b81 */
- /*#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc1 */
-
-/****************************************/
-/* DMA Channel Control */
-/****************************************/
-
-#define CHANNEL0CONTROL 0x840
-#define CHANNEL0CONTROL_HIGH 0x880
-#define CHANNEL1CONTROL 0x844
-#define CHANNEL1CONTROL_HIGH 0x884
-#define CHANNEL2CONTROL 0x848
-#define CHANNEL2CONTROL_HIGH 0x888
-#define CHANNEL3CONTROL 0x84C
-#define CHANNEL3CONTROL_HIGH 0x88C
-
-#define DMA_CHANNEL0_CONTROL CHANNEL0CONTROL /*0x8401 */
-#define DMA_CHANNEL0_CONTROL_HIGH CHANNEL0CONTROL_HIGH /*0x8801 */
-#define DMA_CHANNEL1_CONTROL CHANNEL1CONTROL /* 0x8441 */
-#define DMA_CHANNEL1_CONTROL_HIGH CHANNEL1CONTROL_HIGH /*0x8841 */
-#define DMA_CHANNEL2_CONTROL CHANNEL2CONTROL /*0x8481 */
-#define DMA_CHANNEL2_CONTROL_HIGH CHANNEL2CONTROL_HIGH /*0x8881 */
-#define DMA_CHANNEL3_CONTROL CHANNEL3CONTROL /*0x84C1 */
-#define DMA_CHANNEL3_CONTROL_HIGH CHANNEL3CONTROL_HIGH /*0x88C1 */
-
- /*#define CHANNEL4CONTROL 0x9401 */
- /*#define CHANNEL4CONTROL_HIGH 0x9801 */
- /*#define CHANNEL5CONTROL 0x9441 */
- /*#define CHANNEL5CONTROL_HIGH 0x9841 */
- /*#define CHANNEL6CONTROL 0x9481 */
- /*#define CHANNEL6CONTROL_HIGH 0x9881 */
- /*#define CHANNEL7CONTROL 0x94C1 */
- /*#define CHANNEL7CONTROL_HIGH 0x98C1 */
-
-
-/****************************************/
-/* DMA Arbiter */
-/****************************************/
-
- /*#define ARBITER_CONTROL_0_3 0x8601 */
-#define ARBITER_CONTROL_4_7 0x960
-/****************************************/
-/* IDMA Registers */
-/****************************************/
-
-#define DMA_CHANNEL0_BYTE_COUNT CHANNEL0_DMA_BYTE_COUNT /*0x8001 */
-#define DMA_CHANNEL1_BYTE_COUNT CHANNEL1_DMA_BYTE_COUNT /*0x8041 */
-#define DMA_CHANNEL2_BYTE_COUNT CHANNEL2_DMA_BYTE_COUNT /*0x8081 */
-#define DMA_CHANNEL3_BYTE_COUNT CHANNEL3_DMA_BYTE_COUNT /*0x80C1 */
-#define DMA_CHANNEL0_SOURCE_ADDR CHANNEL0_DMA_SOURCE_ADDRESS /*0x8101 */
-#define DMA_CHANNEL1_SOURCE_ADDR CHANNEL1_DMA_SOURCE_ADDRESS /*0x8141 */
-#define DMA_CHANNEL2_SOURCE_ADDR CHANNEL2_DMA_SOURCE_ADDRESS /*0x8181 */
-#define DMA_CHANNEL3_SOURCE_ADDR CHANNEL3_DMA_SOURCE_ADDRESS /*0x81c1 */
-#define DMA_CHANNEL0_DESTINATION_ADDR CHANNEL0_DMA_DESTINATION_ADDRESS /*0x8201 */
-#define DMA_CHANNEL1_DESTINATION_ADDR CHANNEL1_DMA_DESTINATION_ADDRESS /*0x8241 */
-#define DMA_CHANNEL2_DESTINATION_ADDR CHANNEL2_DMA_DESTINATION_ADDRESS /*0x8281 */
-#define DMA_CHANNEL3_DESTINATION_ADDR CHANNEL3_DMA_DESTINATION_ADDRESS /*0x82C1 */
-#define DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER CHANNEL0NEXT_RECORD_POINTER /*0x8301 */
-#define DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER CHANNEL1NEXT_RECORD_POINTER /*0x8341 */
-#define DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER CHANNEL2NEXT_RECORD_POINTER /*0x8381 */
-#define DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER CHANNEL3NEXT_RECORD_POINTER /*0x83C1 */
-#define DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER CHANNEL0CURRENT_DESCRIPTOR_POINTER /*0x8701 */
-#define DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER CHANNEL1CURRENT_DESCRIPTOR_POINTER /*0x8741 */
-#define DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER CHANNEL2CURRENT_DESCRIPTOR_POINTER /*0x8781 */
-#define DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER CHANNEL3CURRENT_DESCRIPTOR_POINTER /*0x87C1 */
-
-#define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C
-#define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878
-#define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874
-#define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870
-#define CHANNEL0NEXT_RECORD_POINTER 0x830
-#define CHANNEL1NEXT_RECORD_POINTER 0x834
-#define CHANNEL2NEXT_RECORD_POINTER 0x838
-#define CHANNEL3NEXT_RECORD_POINTER 0x83C
-#define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820
-#define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824
-#define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828
-#define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C
-#define CHANNEL0_DMA_SOURCE_ADDRESS 0x810
-#define CHANNEL1_DMA_SOURCE_ADDRESS 0x814
-#define CHANNEL2_DMA_SOURCE_ADDRESS 0x818
-#define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C
-#define CHANNEL0_DMA_BYTE_COUNT 0x800
-#define CHANNEL1_DMA_BYTE_COUNT 0x804
-#define CHANNEL2_DMA_BYTE_COUNT 0x808
-#define CHANNEL3_DMA_BYTE_COUNT 0x80C
-
- /* IDMA Address Decoding Base Address Registers */
-
-#define DMA_BASE_ADDR_REG0 0xa00
-#define DMA_BASE_ADDR_REG1 0xa08
-#define DMA_BASE_ADDR_REG2 0xa10
-#define DMA_BASE_ADDR_REG3 0xa18
-#define DMA_BASE_ADDR_REG4 0xa20
-#define DMA_BASE_ADDR_REG5 0xa28
-#define DMA_BASE_ADDR_REG6 0xa30
-#define DMA_BASE_ADDR_REG7 0xa38
-
- /* IDMA Address Decoding Size Address Register */
-
-#define DMA_SIZE_REG0 0xa04
-#define DMA_SIZE_REG1 0xa0c
-#define DMA_SIZE_REG2 0xa14
-#define DMA_SIZE_REG3 0xa1c
-#define DMA_SIZE_REG4 0xa24
-#define DMA_SIZE_REG5 0xa2c
-#define DMA_SIZE_REG6 0xa34
-#define DMA_SIZE_REG7 0xa3C
-
- /* IDMA Address Decoding High Address Remap and Access
- Protection Registers */
-
-#define DMA_HIGH_ADDR_REMAP_REG0 0xa60
-#define DMA_HIGH_ADDR_REMAP_REG1 0xa64
-#define DMA_HIGH_ADDR_REMAP_REG2 0xa68
-#define DMA_HIGH_ADDR_REMAP_REG3 0xa6C
-#define DMA_BASE_ADDR_ENABLE_REG 0xa80
-#define DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70
-#define DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74
-#define DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78
-#define DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c
-#define DMA_ARBITER_CONTROL 0x860
-#define DMA_CROSS_BAR_TIMEOUT 0x8d0
-
- /* IDMA Headers Retarget Registers */
-
- /*#define CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e01 */
- /*#define CPU_IDMA_HEADERS_RETARGET_BASE 0x3e81 */
-
-#define DMA_HEADERS_RETARGET_CONTROL 0xa84
-#define DMA_HEADERS_RETARGET_BASE 0xa88
-
-/****************************************/
-/* DMA Interrupt */
-/****************************************/
-
-#define CHANELS0_3_INTERRUPT_CAUSE 0x8c0
-#define CHANELS0_3_INTERRUPT_MASK 0x8c4
-#define CHANELS0_3_ERROR_ADDRESS 0x8c8
-#define CHANELS0_3_ERROR_SELECT 0x8cc
- /*#define CHANELS4_7_INTERRUPT_CAUSE 0x9c01 */
- /*#define CHANELS4_7_INTERRUPT_MASK 0x9c41 */
- /*#define CHANELS4_7_ERROR_ADDRESS 0x9c81 */
- /*#define CHANELS4_7_ERROR_SELECT 0x9cc1 */
-
-#define DMA_INTERRUPT_CAUSE_REG CHANELS0_3_INTERRUPT_CAUSE /*0x8c01 */
-#define DMA_INTERRUPT_CAUSE_MASK CHANELS0_3_INTERRUPT_MASK /*0x8c41 */
-#define DMA_ERROR_ADDR CHANELS0_3_ERROR_ADDRESS /*0x8c81 */
-#define DMA_ERROR_SELECT CHANELS0_3_ERROR_SELECT /*0x8cc1 */
-
-
-/****************************************/
-/* DMA Debug (for internal use) */
-/****************************************/
-
-#define DMA_X0_ADDRESS 0x8e0
-#define DMA_X0_COMMAND_AND_ID 0x8e4
- /*#define DMA_X0_WRITE_DATA_LOW 0x8e81 */
- /*#define DMA_X0_WRITE_DATA_HIGH 0x8ec1 */
- /*#define DMA_X0_WRITE_BYTE_ENABLE 0x8f81 */
- /*#define DMA_X0_READ_DATA_LOW 0x8f01 */
- /*#define DMA_X0_READ_DATA_HIGH 0x8f41 */
- /*#define DMA_X0_READ_ID 0x8fc1 */
- /*#define DMA_X1_ADDRESS 0x9e01 */
- /*#define DMA_X1_COMMAND_AND_ID 0x9e41 */
- /*#define DMA_X1_WRITE_DATA_LOW 0x9e81 */
- /*#define DMA_X1_WRITE_DATA_HIGH 0x9ec1 */
- /*#define DMA_X1_WRITE_BYTE_ENABLE 0x9f81 */
- /*#define DMA_X1_READ_DATA_LOW 0x9f01 */
- /*#define DMA_X1_READ_DATA_HIGH 0x9f41 */
- /*#define DMA_X1_READ_ID 0x9fc1 */
-
- /* IDMA Debug Register ( for internal use ) */
-
-#define DMA_DEBUG_LOW DMA_X0_ADDRESS /* 0x8e01 */
-#define DMA_DEBUG_HIGH DMA_X0_COMMAND_AND_ID /*0x8e41 */
-#define DMA_SPARE 0xA8C
-
-
-/****************************************/
-/* Timer_Counter */
-/****************************************/
-
-#define TIMER_COUNTER0 0x850
-#define TIMER_COUNTER1 0x854
-#define TIMER_COUNTER2 0x858
-#define TIMER_COUNTER3 0x85C
-#define TIMER_COUNTER_0_3_CONTROL 0x864
-#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868
-#define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c
- /*#define TIMER_COUNTER4 0x9501 */
- /*#define TIMER_COUNTER5 0x9541 */
- /*#define TIMER_COUNTER6 0x9581 */
- /*#define TIMER_COUNTER7 0x95C1 */
- /*#define TIMER_COUNTER_4_7_CONTROL 0x9641 */
- /*#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x9681 */
- /*#define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c1 */
-
-/****************************************/
-/* PCI Slave Address Decoding */
-/****************************************/
-/****************************************/
-/* PCI Slave Address Decoding registers */
-/****************************************/
-#define PCI_0_CS_0_BANK_SIZE PCI_0SCS_0_BANK_SIZE /*0xc081 */
-#define PCI_1_CS_0_BANK_SIZE PCI_1SCS_0_BANK_SIZE /* 0xc881 */
-#define PCI_0_CS_1_BANK_SIZE PCI_0SCS_1_BANK_SIZE /*0xd081 */
-#define PCI_1_CS_1_BANK_SIZE PCI_1SCS_1_BANK_SIZE /* 0xd881 */
-#define PCI_0_CS_2_BANK_SIZE PCI_0SCS_2_BANK_SIZE /*0xc0c1 */
-#define PCI_1_CS_2_BANK_SIZE PCI_1SCS_2_BANK_SIZE /*0xc8c1 */
-#define PCI_0_CS_3_BANK_SIZE PCI_0SCS_3_BANK_SIZE /*0xd0c1 */
-#define PCI_1_CS_3_BANK_SIZE PCI_1SCS_3_BANK_SIZE /*0xd8c1 */
-#define PCI_0_DEVCS_0_BANK_SIZE PCI_0CS_0_BANK_SIZE /*0xc101 */
-#define PCI_1_DEVCS_0_BANK_SIZE PCI_1CS_0_BANK_SIZE /*0xc901 */
-#define PCI_0_DEVCS_1_BANK_SIZE PCI_0CS_1_BANK_SIZE /*0xd101 */
-#define PCI_1_DEVCS_1_BANK_SIZE PCI_1CS_1_BANK_SIZE /* 0xd901 */
-#define PCI_0_DEVCS_2_BANK_SIZE PCI_0CS_2_BANK_SIZE /* 0xd181 */
-#define PCI_1_DEVCS_2_BANK_SIZE PCI_1CS_2_BANK_SIZE /*0xd981 */
-#define PCI_0_DEVCS_3_BANK_SIZE PCI_0CS_3_BANK_SIZE /* 0xc141 */
-#define PCI_1_DEVCS_3_BANK_SIZE PCI_1CS_3_BANK_SIZE /*0xc941 */
-#define PCI_0_DEVCS_BOOT_BANK_SIZE PCI_0CS_BOOT_BANK_SIZE /*0xd141 */
-#define PCI_1_DEVCS_BOOT_BANK_SIZE PCI_1CS_BOOT_BANK_SIZE /* 0xd941 */
-#define PCI_0_P2P_MEM0_BAR_SIZE PCI_0P2P_MEM0_BAR_SIZE /*0xd1c1 */
-#define PCI_1_P2P_MEM0_BAR_SIZE PCI_1P2P_MEM0_BAR_SIZE /*0xd9c1 */
-#define PCI_0_P2P_MEM1_BAR_SIZE PCI_0P2P_MEM1_BAR_SIZE /*0xd201 */
-#define PCI_1_P2P_MEM1_BAR_SIZE PCI_1P2P_MEM1_BAR_SIZE /*0xda01 */
-#define PCI_0_P2P_I_O_BAR_SIZE PCI_0P2P_I_O_BAR_SIZE /*0xd241 */
-#define PCI_1_P2P_I_O_BAR_SIZE PCI_1P2P_I_O_BAR_SIZE /*0xda41 */
-#define PCI_0_CPU_BAR_SIZE PCI_0CPU_BAR_SIZE /*0xd281 */
-#define PCI_1_CPU_BAR_SIZE PCI_1CPU_BAR_SIZE /*0xda81 */
-#define PCI_0_INTERNAL_SRAM_BAR_SIZE PCI_0DAC_SCS_0_BANK_SIZE /*0xe001 */
-#define PCI_1_INTERNAL_SRAM_BAR_SIZE PCI_1DAC_SCS_0_BANK_SIZE /*0xe801 */
-#define PCI_0_EXPANSION_ROM_BAR_SIZE PCI_0EXPANSION_ROM_BAR_SIZE /*0xd2c1 */
-#define PCI_1_EXPANSION_ROM_BAR_SIZE PCI_1EXPANSION_ROM_BAR_SIZE /*0xd9c1 */
-#define PCI_0_BASE_ADDR_REG_ENABLE PCI_0BASE_ADDRESS_REGISTERS_ENABLE /*0xc3c1 */
-#define PCI_1_BASE_ADDR_REG_ENABLE PCI_1BASE_ADDRESS_REGISTERS_ENABLE /*0xcbc1 */
-#define PCI_0_CS_0_BASE_ADDR_REMAP PCI_0SCS_0_BASE_ADDRESS_REMAP /*0xc481 */
-#define PCI_1_CS_0_BASE_ADDR_REMAP PCI_1SCS_0_BASE_ADDRESS_REMAP /*0xcc81 */
-#define PCI_0_CS_1_BASE_ADDR_REMAP PCI_0SCS_1_BASE_ADDRESS_REMAP /*0xd481 */
-#define PCI_1_CS_1_BASE_ADDR_REMAP PCI_1SCS_1_BASE_ADDRESS_REMAP /*0xdc81 */
-#define PCI_0_CS_2_BASE_ADDR_REMAP PCI_0SCS_2_BASE_ADDRESS_REMAP /*0xc4c1 */
-#define PCI_1_CS_2_BASE_ADDR_REMAP PCI_1SCS_2_BASE_ADDRESS_REMAP /*0xccc1 */
-#define PCI_0_CS_3_BASE_ADDR_REMAP PCI_0SCS_3_BASE_ADDRESS_REMAP /*0xd4c1 */
-#define PCI_1_CS_3_BASE_ADDR_REMAP PCI_1SCS_3_BASE_ADDRESS_REMAP /* 0xdcc1 */
-#define PCI_0_CS_0_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP
-#define PCI_1_CS_0_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP
-#define PCI_0_CS_1_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP
-#define PCI_1_CS_1_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP
-#define PCI_0_CS_2_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP
-#define PCI_1_CS_2_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP
-#define PCI_0_CS_3_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP
-#define PCI_1_CS_3_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP
-#define PCI_0_DEVCS_0_BASE_ADDR_REMAP PCI_0CS_0_BASE_ADDRESS_REMAP /*0xc501 */
-#define PCI_1_DEVCS_0_BASE_ADDR_REMAP PCI_1CS_0_BASE_ADDRESS_REMAP /*0xcd01 */
-#define PCI_0_DEVCS_1_BASE_ADDR_REMAP PCI_0CS_1_BASE_ADDRESS_REMAP /*0xd501 */
-#define PCI_1_DEVCS_1_BASE_ADDR_REMAP PCI_1CS_1_BASE_ADDRESS_REMAP /*0xdd01 */
-#define PCI_0_DEVCS_2_BASE_ADDR_REMAP PCI_0CS_2_BASE_ADDRESS_REMAP /*0xd581 */
-#define PCI_1_DEVCS_2_BASE_ADDR_REMAP PCI_1CS_2_BASE_ADDRESS_REMAP /*0xdd81 */
-#define PCI_0_DEVCS_3_BASE_ADDR_REMAP PCI_0CS_3_BASE_ADDRESS_REMAP /*0xc541 */
-#define PCI_1_DEVCS_3_BASE_ADDR_REMAP PCI_1CS_3_BASE_ADDRESS_REMAP /*0xcd41 */
-#define PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP /*0xd541 */
-#define PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP /*0xdd41 */
-#define PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW /*0xd5c1 */
-#define PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW /*0xddc1 */
-#define PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH /*0xd601 */
-#define PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH /*0xde01 */
-#define PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW /*0xd641 */
-#define PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW /*0xde41 */
-#define PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH /*0xd681 */
-#define PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH /*0xde81 */
-#define PCI_0_P2P_I_O_BASE_ADDR_REMAP PCI_0P2P_I_O_BASE_ADDRESS_REMAP /*0xd6c1 */
-#define PCI_1_P2P_I_O_BASE_ADDR_REMAP PCI_1P2P_I_O_BASE_ADDRESS_REMAP /*0xdec 1 */
-#define PCI_0_CPU_BASE_ADDR_REMAP_LOW PCI_0CPU_BASE_ADDRESS_REMAP /*0xd701 */
-#define PCI_1_CPU_BASE_ADDR_REMAP_LOW PCI_1CPU_BASE_ADDRESS_REMAP /*0xdf01 */
-#define PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74
-#define PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4
-#define PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP /*0xf001 */
-#define PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80
-#define PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP /*0xf381 */
-#define PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP /*0xfb81 */
-#define PCI_0_ADDR_DECODE_CONTROL PCI_0ADDRESS_DECODE_CONTROL /*0xd3c1 */
-#define PCI_1_ADDR_DECODE_CONTROL PCI_1ADDRESS_DECODE_CONTROL /*0xdbc1 */
-#define PCI_0_HEADERS_RETARGET_CONTROL 0xF40
-#define PCI_1_HEADERS_RETARGET_CONTROL 0xFc0
-#define PCI_0_HEADERS_RETARGET_BASE 0xF44
-#define PCI_1_HEADERS_RETARGET_BASE 0xFc4
-#define PCI_0_HEADERS_RETARGET_HIGH 0xF48
-#define PCI_1_HEADERS_RETARGET_HIGH 0xFc8
-
-#define PCI_0SCS_0_BANK_SIZE 0xc08
-#define PCI_1SCS_0_BANK_SIZE 0xc88
-#define PCI_0SCS_1_BANK_SIZE 0xd08
-#define PCI_1SCS_1_BANK_SIZE 0xd88
-#define PCI_0SCS_2_BANK_SIZE 0xc0c
-#define PCI_1SCS_2_BANK_SIZE 0xc8c
-#define PCI_0SCS_3_BANK_SIZE 0xd0c
-#define PCI_1SCS_3_BANK_SIZE 0xd8c
-#define PCI_0CS_0_BANK_SIZE 0xc10
-#define PCI_1CS_0_BANK_SIZE 0xc90
-#define PCI_0CS_1_BANK_SIZE 0xd10
-#define PCI_1CS_1_BANK_SIZE 0xd90
-#define PCI_0CS_2_BANK_SIZE 0xd18
-#define PCI_1CS_2_BANK_SIZE 0xd98
-#define PCI_0CS_3_BANK_SIZE 0xc14
-#define PCI_1CS_3_BANK_SIZE 0xc94
-#define PCI_0CS_BOOT_BANK_SIZE 0xd14
-#define PCI_1CS_BOOT_BANK_SIZE 0xd94
-#define PCI_0P2P_MEM0_BAR_SIZE 0xd1c
-#define PCI_1P2P_MEM0_BAR_SIZE 0xd9c
-#define PCI_0P2P_MEM1_BAR_SIZE 0xd20
-#define PCI_1P2P_MEM1_BAR_SIZE 0xda0
-#define PCI_0P2P_I_O_BAR_SIZE 0xd24
-#define PCI_1P2P_I_O_BAR_SIZE 0xda4
-#define PCI_0CPU_BAR_SIZE 0xd28
-#define PCI_1CPU_BAR_SIZE 0xda8
-#define PCI_0DAC_SCS_0_BANK_SIZE 0xe00
-#define PCI_1DAC_SCS_0_BANK_SIZE 0xe80
-#define PCI_0DAC_SCS_1_BANK_SIZE 0xe04
-#define PCI_1DAC_SCS_1_BANK_SIZE 0xe84
-#define PCI_0DAC_SCS_2_BANK_SIZE 0xe08
-#define PCI_1DAC_SCS_2_BANK_SIZE 0xe88
-#define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c
-#define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c
-#define PCI_0DAC_CS_0_BANK_SIZE 0xe10
-#define PCI_1DAC_CS_0_BANK_SIZE 0xe90
-#define PCI_0DAC_CS_1_BANK_SIZE 0xe14
-#define PCI_1DAC_CS_1_BANK_SIZE 0xe94
-#define PCI_0DAC_CS_2_BANK_SIZE 0xe18
-#define PCI_1DAC_CS_2_BANK_SIZE 0xe98
-#define PCI_0DAC_CS_3_BANK_SIZE 0xe1c
-#define PCI_1DAC_CS_3_BANK_SIZE 0xe9c
-#define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20
-#define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0
-
-#define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24
-#define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4
-#define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28
-#define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8
-#define PCI_0DAC_CPU_BAR_SIZE 0xe2c
-#define PCI_1DAC_CPU_BAR_SIZE 0xeac
-#define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c
-#define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac
-#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c
-#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc
-#define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48
-#define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8
-#define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48
-#define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8
-#define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c
-#define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc
-#define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c
-#define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc
-#define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50
-#define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0
-#define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50
-#define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0
-#define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58
-#define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8
-#define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54
-#define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4
-#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54
-#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4
-#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c
-#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc
-#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60
-#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0
-#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64
-#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4
-#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68
-#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8
-#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c
-#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec
-#define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70
-#define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0
-#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00
-#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0
-#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04
-#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84
-#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08
-#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88
-#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c
-#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c
-#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10
-#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90
-#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14
-#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94
-#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18
-#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98
-#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c
-#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c
-#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20
-#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0
-#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24
-#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4
-#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28
-#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8
-#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c
-#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac
-#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30
-#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0
-#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34
-#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4
-#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38
-#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8
-#define PCI_0ADDRESS_DECODE_CONTROL 0xd3c
-#define PCI_1ADDRESS_DECODE_CONTROL 0xdbc
-
-/****************************************/
-/* PCI Control */
-/****************************************/
-
-#define PCI_0COMMAND 0xc00
-#define PCI_1COMMAND 0xc80
-#define PCI_0MODE 0xd00
-#define PCI_1MODE 0xd80
-#define PCI_0TIMEOUT_RETRY 0xc04
-#define PCI_1TIMEOUT_RETRY 0xc84
-#define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04
-#define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84
-#define MSI_0TRIGGER_TIMER 0xc38
-#define MSI_1TRIGGER_TIMER 0xcb8
-#define PCI_0ARBITER_CONTROL 0x1d00
-#define PCI_1ARBITER_CONTROL 0x1d80
-/* changing untill here */
-#define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08
-#define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c
-#define PCI_0CROSS_BAR_TIMEOUT 0x1d04
-#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18
-#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c
-#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10
-#define PCI_0P2P_CONFIGURATION 0x1d14
-#define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00
-#define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04
-#define PCI_0ACCESS_CONTROL_TOP_0 0x1e08
-#define PCI_0ACCESS_CONTROL_BASE_1_LOW 0x1e10
-#define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14
-#define PCI_0ACCESS_CONTROL_TOP_1 0x1e18
-#define PCI_0ACCESS_CONTROL_BASE_2_LOW 0x1e20
-#define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24
-#define PCI_0ACCESS_CONTROL_TOP_2 0x1e28
-#define PCI_0ACCESS_CONTROL_BASE_3_LOW 0x1e30
-#define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34
-#define PCI_0ACCESS_CONTROL_TOP_3 0x1e38
-#define PCI_0ACCESS_CONTROL_BASE_4_LOW 0x1e40
-#define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44
-#define PCI_0ACCESS_CONTROL_TOP_4 0x1e48
-#define PCI_0ACCESS_CONTROL_BASE_5_LOW 0x1e50
-#define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54
-#define PCI_0ACCESS_CONTROL_TOP_5 0x1e58
-#define PCI_0ACCESS_CONTROL_BASE_6_LOW 0x1e60
-#define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64
-#define PCI_0ACCESS_CONTROL_TOP_6 0x1e68
-#define PCI_0ACCESS_CONTROL_BASE_7_LOW 0x1e70
-#define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74
-#define PCI_0ACCESS_CONTROL_TOP_7 0x1e78
-#define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88
-#define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c
-#define PCI_1CROSS_BAR_TIMEOUT 0x1d84
-#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98
-#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c
-#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90
-#define PCI_1P2P_CONFIGURATION 0x1d94
-#define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80
-#define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84
-#define PCI_1ACCESS_CONTROL_TOP_0 0x1e88
-#define PCI_1ACCESS_CONTROL_BASE_1_LOW 0x1e90
-#define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94
-#define PCI_1ACCESS_CONTROL_TOP_1 0x1e98
-#define PCI_1ACCESS_CONTROL_BASE_2_LOW 0x1ea0
-#define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
-#define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8
-#define PCI_1ACCESS_CONTROL_BASE_3_LOW 0x1eb0
-#define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
-#define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8
-#define PCI_1ACCESS_CONTROL_BASE_4_LOW 0x1ec0
-#define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
-#define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8
-#define PCI_1ACCESS_CONTROL_BASE_5_LOW 0x1ed0
-#define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
-#define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8
-#define PCI_1ACCESS_CONTROL_BASE_6_LOW 0x1ee0
-#define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4
-#define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8
-#define PCI_1ACCESS_CONTROL_BASE_7_LOW 0x1ef0
-#define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4
-#define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8
-
-/****************************************/
-/* PCI Snoop Control */
-/****************************************/
-
-#define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00
-#define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04
-#define PCI_0SNOOP_CONTROL_TOP_0 0x1f08
-#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10
-#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14
-#define PCI_0SNOOP_CONTROL_TOP_1 0x1f18
-#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20
-#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24
-#define PCI_0SNOOP_CONTROL_TOP_2 0x1f28
-#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30
-#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34
-#define PCI_0SNOOP_CONTROL_TOP_3 0x1f38
-#define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80
-#define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84
-#define PCI_1SNOOP_CONTROL_TOP_0 0x1f88
-#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90
-#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94
-#define PCI_1SNOOP_CONTROL_TOP_1 0x1f98
-#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0
-#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4
-#define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8
-#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0
-#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4
-#define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8
-
-/****************************************/
-/* PCI Configuration Address */
-/****************************************/
-
-#define PCI_0CONFIGURATION_ADDRESS 0xcf8
-#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc
-#define PCI_1CONFIGURATION_ADDRESS 0xc78
-#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c
-#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34
-#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4
-
-/****************************************/
-/* PCI Error Report */
-/****************************************/
-
-#define PCI_0SERR_MASK 0xc28
-#define PCI_0ERROR_ADDRESS_LOW 0x1d40
-#define PCI_0ERROR_ADDRESS_HIGH 0x1d44
-#define PCI_0ERROR_DATA_LOW 0x1d48
-#define PCI_0ERROR_DATA_HIGH 0x1d4c
-#define PCI_0ERROR_COMMAND 0x1d50
-#define PCI_0ERROR_CAUSE 0x1d58
-#define PCI_0ERROR_MASK 0x1d5c
-#define PCI_1SERR_MASK 0xca8
-#define PCI_1ERROR_ADDRESS_LOW 0x1dc0
-#define PCI_1ERROR_ADDRESS_HIGH 0x1dc4
-#define PCI_1ERROR_DATA_LOW 0x1dc8
-#define PCI_1ERROR_DATA_HIGH 0x1dcc
-#define PCI_1ERROR_COMMAND 0x1dd0
-#define PCI_1ERROR_CAUSE 0x1dd8
-#define PCI_1ERROR_MASK 0x1ddc
-
-
-/****************************************/
-/* Lslave Debug (for internal use) */
-/****************************************/
-
-#define L_SLAVE_X0_ADDRESS 0x1d20
-#define L_SLAVE_X0_COMMAND_AND_ID 0x1d24
-#define L_SLAVE_X1_ADDRESS 0x1d28
-#define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c
-#define L_SLAVE_WRITE_DATA_LOW 0x1d30
-#define L_SLAVE_WRITE_DATA_HIGH 0x1d34
-#define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60
-#define L_SLAVE_READ_DATA_LOW 0x1d38
-#define L_SLAVE_READ_DATA_HIGH 0x1d3c
-#define L_SLAVE_READ_ID 0x1d64
-
-/****************************************/
-/* PCI Configuration Function 0 */
-/****************************************/
-
-#define PCI_DEVICE_AND_VENDOR_ID 0x000
-#define PCI_STATUS_AND_COMMAND 0x004
-#define PCI_CLASS_CODE_AND_REVISION_ID 0x008
-#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
-#define PCI_SCS_0_BASE_ADDRESS 0x010
-#define PCI_SCS_1_BASE_ADDRESS 0x014
-#define PCI_SCS_2_BASE_ADDRESS 0x018
-#define PCI_SCS_3_BASE_ADDRESS 0x01C
-#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020
-#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024
-#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C
-#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030
-#define PCI_CAPABILTY_LIST_POINTER 0x034
-#define PCI_INTERRUPT_PIN_AND_LINE 0x03C
-#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040
-#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
-#define PCI_VPD_ADDRESS 0x048
-#define PCI_VPD_DATA 0x04c
-#define PCI_MSI_MESSAGE_CONTROL 0x050
-#define PCI_MSI_MESSAGE_ADDRESS 0x054
-#define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058
-#define PCI_MSI_MESSAGE_DATA 0x05c
-#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058
-
-/****************************************/
-/* PCI Configuration Function 1 */
-/****************************************/
-
-#define PCI_CS_0_BASE_ADDRESS 0x110
-#define PCI_CS_1_BASE_ADDRESS 0x114
-#define PCI_CS_2_BASE_ADDRESS 0x118
-#define PCI_CS_3_BASE_ADDRESS 0x11c
-#define PCI_BOOTCS_BASE_ADDRESS 0x120
-
-/****************************************/
-/* PCI Configuration Function 2 */
-/****************************************/
-
-#define PCI_P2P_MEM0_BASE_ADDRESS 0x210
- /*#define PCI_P2P_MEM1_BASE_ADDRESS 0x2141 */
-#define PCI_P2P_I_O_BASE_ADDRESS 0x218
- /*#define PCI_CPU_BASE_ADDRESS 0x21c1 */
-
-/****************************************/
-/* PCI Configuration Function 4 */
-/****************************************/
-
-#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410
-#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414
-#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418
-#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c
-#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420
-#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424
-
-
-/****************************************/
-/* PCI Configuration Function 5 */
-/****************************************/
-
-#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510
-#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514
-#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518
-#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c
-#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520
-#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524
-
-
-/****************************************/
-/* PCI Configuration Function 6 */
-/****************************************/
-
-#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610
-#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614
-#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618
-#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c
-#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620
-#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624
-
-/****************************************/
-/* PCI Configuration Function 7 */
-/****************************************/
-
-#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710
-#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714
-#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718
-#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c
-#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720
-#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724
-
-/****************************** MV64360 and MV64460 PCI ***************************/
-/***********************************/
-/* PCI Control Register Map */
-/***********************************/
-
-#define PCI_0_DLL_STATUS_AND_COMMAND 0x1d20
-#define PCI_1_DLL_STATUS_AND_COMMAND 0x1da0
-#define PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C
-#define PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C
-#define PCI_0_COMMAND 0xc00
-#define PCI_1_COMMAND 0xc80
-#define PCI_0_MODE 0xd00
-#define PCI_1_MODE 0xd80
-#define PCI_0_RETRY 0xc04
-#define PCI_1_RETRY 0xc84
-#define PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04
-#define PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84
-#define PCI_0_MSI_TRIGGER_TIMER 0xc38
-#define PCI_1_MSI_TRIGGER_TIMER 0xcb8
-#define PCI_0_ARBITER_CONTROL 0x1d00
-#define PCI_1_ARBITER_CONTROL 0x1d80
-#define PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08
-#define PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88
-#define PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c
-#define PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c
-#define PCI_0_CROSS_BAR_TIMEOUT 0x1d04
-#define PCI_1_CROSS_BAR_TIMEOUT 0x1d84
-#define PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18
-#define PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98
-#define PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10
-#define PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90
-#define PCI_0_P2P_CONFIG 0x1d14
-#define PCI_1_P2P_CONFIG 0x1d94
-
-#define PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00
-#define PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04
-#define PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08
-#define PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10
-#define PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14
-#define PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18
-#define PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20
-#define PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24
-#define PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28
-#define PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30
-#define PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34
-#define PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38
-#define PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40
-#define PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44
-#define PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48
-#define PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50
-#define PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54
-#define PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58
-
-#define PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80
-#define PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84
-#define PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88
-#define PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90
-#define PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94
-#define PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98
-#define PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0
-#define PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
-#define PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8
-#define PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0
-#define PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
-#define PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8
-#define PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0
-#define PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
-#define PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8
-#define PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0
-#define PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
-#define PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8
-
-/****************************************/
-/* PCI Configuration Access Registers */
-/****************************************/
-
-#define PCI_0_CONFIG_ADDR 0xcf8
-#define PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc
-#define PCI_1_CONFIG_ADDR 0xc78
-#define PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c
-#define PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34
-#define PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4
-
-/****************************************/
-/* PCI Error Report Registers */
-/****************************************/
-
-#define PCI_0_SERR_MASK 0xc28
-#define PCI_1_SERR_MASK 0xca8
-#define PCI_0_ERROR_ADDR_LOW 0x1d40
-#define PCI_1_ERROR_ADDR_LOW 0x1dc0
-#define PCI_0_ERROR_ADDR_HIGH 0x1d44
-#define PCI_1_ERROR_ADDR_HIGH 0x1dc4
-#define PCI_0_ERROR_ATTRIBUTE 0x1d48
-#define PCI_1_ERROR_ATTRIBUTE 0x1dc8
-#define PCI_0_ERROR_COMMAND 0x1d50
-#define PCI_1_ERROR_COMMAND 0x1dd0
-#define PCI_0_ERROR_CAUSE 0x1d58
-#define PCI_1_ERROR_CAUSE 0x1dd8
-#define PCI_0_ERROR_MASK 0x1d5c
-#define PCI_1_ERROR_MASK 0x1ddc
-
-/****************************************/
-/* PCI Debug Registers */
-/****************************************/
-
-#define PCI_0_MMASK 0X1D24
-#define PCI_1_MMASK 0X1DA4
-
-/*********************************************/
-/* PCI Configuration, Function 0, Registers */
-/*********************************************/
-
-#define PCI_DEVICE_AND_VENDOR_ID 0x000
-#define PCI_STATUS_AND_COMMAND 0x004
-#define PCI_CLASS_CODE_AND_REVISION_ID 0x008
-#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
-
-#define PCI_SCS_0_BASE_ADDR_LOW 0x010
-#define PCI_SCS_0_BASE_ADDR_HIGH 0x014
-#define PCI_SCS_1_BASE_ADDR_LOW 0x018
-#define PCI_SCS_1_BASE_ADDR_HIGH 0x01C
-#define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020
-#define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024
- /*#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c1 */
-#define PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030
-#define PCI_CAPABILTY_LIST_POINTER 0x034
-#define PCI_INTERRUPT_PIN_AND_LINE 0x03C
- /* capability list */
-#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040
-#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
-#define PCI_VPD_ADDR 0x048
-#define PCI_VPD_DATA 0x04c
-#define PCI_MSI_MESSAGE_CONTROL 0x050
-#define PCI_MSI_MESSAGE_ADDR 0x054
-#define PCI_MSI_MESSAGE_UPPER_ADDR 0x058
-#define PCI_MSI_MESSAGE_DATA 0x05c
-#define PCI_X_COMMAND 0x060
-#define PCI_X_STATUS 0x064
-#define PCI_COMPACT_PCI_HOT_SWAP 0x068
-
-/***********************************************/
-/* PCI Configuration, Function 1, Registers */
-/***********************************************/
-
-#define PCI_SCS_2_BASE_ADDR_LOW 0x110
-#define PCI_SCS_2_BASE_ADDR_HIGH 0x114
-#define PCI_SCS_3_BASE_ADDR_LOW 0x118
-#define PCI_SCS_3_BASE_ADDR_HIGH 0x11c
-#define PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120
-#define PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124
-
-/***********************************************/
-/* PCI Configuration, Function 2, Registers */
-/***********************************************/
-
-#define PCI_DEVCS_0_BASE_ADDR_LOW 0x210
-#define PCI_DEVCS_0_BASE_ADDR_HIGH 0x214
-#define PCI_DEVCS_1_BASE_ADDR_LOW 0x218
-#define PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c
-#define PCI_DEVCS_2_BASE_ADDR_LOW 0x220
-#define PCI_DEVCS_2_BASE_ADDR_HIGH 0x224
-
-/***********************************************/
-/* PCI Configuration, Function 3, Registers */
-/***********************************************/
-
-#define PCI_DEVCS_3_BASE_ADDR_LOW 0x310
-#define PCI_DEVCS_3_BASE_ADDR_HIGH 0x314
-#define PCI_BOOT_CS_BASE_ADDR_LOW 0x318
-#define PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c
-#define PCI_CPU_BASE_ADDR_LOW 0x220
-#define PCI_CPU_BASE_ADDR_HIGH 0x224
-
-/***********************************************/
-/* PCI Configuration, Function 4, Registers */
-/***********************************************/
-
-#define PCI_P2P_MEM0_BASE_ADDR_LOW 0x410
-#define PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414
-#define PCI_P2P_MEM1_BASE_ADDR_LOW 0x418
-#define PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c
-#define PCI_P2P_I_O_BASE_ADDR 0x420
-#define PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424
-
-/****************************** MV64360 and MV64460 PCI End ***************************/
-/****************************************/
-/* I20 Support registers */
-/****************************************/
-
-#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010
-#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014
-#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018
-#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01C
-#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020
-#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024
-#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028
-#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02C
-#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030
-#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034
-#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040
-#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044
-#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050
-#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054
-#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060
-#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064
-#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068
-#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06C
-#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070
-#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074
-#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078
-#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07C
-
-#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C10
-#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C14
-#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C18
-#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C1C
-#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C20
-#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C24
-#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C28
-#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C2C
-#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C30
-#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C34
-#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C40
-#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C44
-#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1C50
-#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1C54
-#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C60
-#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C64
-#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C68
-#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C6C
-#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C70
-#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C74
-#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C78
-#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C7C
-
-
-/****************************************/
-/* Messaging Unit Registers (I20) */
-/****************************************/
-
-#define I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010
-#define I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014
-#define I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018
-#define I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C
-#define I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020
-#define I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024
-#define I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028
-#define I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C
-#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030
-#define I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034
-#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040
-#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044
-#define I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050
-#define I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054
-#define I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060
-#define I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064
-#define I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068
-#define I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C
-#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070
-#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074
-#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8
-#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC
-
-#define I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090
-#define I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094
-#define I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098
-#define I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C
-#define I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0
-#define I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4
-#define I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8
-#define I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC
-#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0
-#define I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4
-#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0
-#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4
-#define I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0
-#define I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4
-#define I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0
-#define I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4
-#define I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8
-#define I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC
-#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0
-#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4
-#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078
-#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C
-
-#define I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10
-#define I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14
-#define I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18
-#define I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C
-#define I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20
-#define I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24
-#define I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28
-#define I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C
-#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30
-#define I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34
-#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40
-#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44
-#define I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50
-#define I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54
-#define I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60
-#define I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64
-#define I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68
-#define I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C
-#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70
-#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74
-#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8
-#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC
-#define I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90
-#define I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94
-#define I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98
-#define I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C
-#define I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0
-#define I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4
-#define I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8
-#define I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC
-#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0
-#define I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4
-#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0
-#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4
-#define I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0
-#define I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4
-#define I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0
-#define I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4
-#define I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8
-#define I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC
-#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0
-#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4
-#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78
-#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C
-
-
-/****************************************/
-/* Communication Unit Registers */
-/****************************************/
-/*
-#define ETHERNET_0_ADDRESS_CONTROL_LOW 0xf200
-#define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204
-#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208
-#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c
-#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210
-#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214
-#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218
-#define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220
-#define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224
-#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228
-#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c
-#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230
-#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234
-#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238
-#define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240
-#define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244
-#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248
-#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c
-#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250
-#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254
-#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258
- */
-#define MPSC_0_ADDRESS_CONTROL_LOW 0xf280
-#define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284
-#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288
-#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c
-#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290
-#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294
-#define MPSC_1_ADDRESS_CONTROL_LOW 0xf2c0
-#define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2c4
-#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8
-#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc
-#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0
-#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4
- /*#define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf3201 */
-#define COMM_UNIT_ARBITER_CONTROL 0xf300
-#define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304
-#define COMM_UNIT_INTERRUPT_CAUSE 0xf310
-#define COMM_UNIT_INTERRUPT_MASK 0xf314
-#define COMM_UNIT_ERROR_ADDRESS 0xf314
-/****************************************/
-/* Serial Initialization registers */
-/****************************************/
-
- /*#define SERIAL_INIT_LAST_DATA 0xf3241 */
- /*#define SERIAL_INIT_STATUS_AND_CONTROL 0xf3281 */
-#define SERIAL_INIT_LAST_DATA 0xf324
-#define SERIAL_INIT_CONTROL 0xf328
-#define SERIAL_INIT_STATUS 0xf32c
-
-
-/****************************************/
-/* Ethernet Unit Registers */
-/****************************************/
-
-#define ETH_PHY_ADDR_REG 0x2000
-#define ETH_SMI_REG 0x2004
-#define ETH_UNIT_DEFAULT_ADDR_REG 0x2008
-#define ETH_UNIT_DEFAULTID_REG 0x200c
-#define ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080
-#define ETH_UNIT_INTERRUPT_MASK_REG 0x2084
-#define ETH_UNIT_INTERNAL_USE_REG 0x24fc
-#define ETH_UNIT_ERROR_ADDR_REG 0x2094
-#define ETH_BAR_0 0x2200
-#define ETH_BAR_1 0x2208
-#define ETH_BAR_2 0x2210
-#define ETH_BAR_3 0x2218
-#define ETH_BAR_4 0x2220
-#define ETH_BAR_5 0x2228
-#define ETH_SIZE_REG_0 0x2204
-#define ETH_SIZE_REG_1 0x220c
-#define ETH_SIZE_REG_2 0x2214
-#define ETH_SIZE_REG_3 0x221c
-#define ETH_SIZE_REG_4 0x2224
-#define ETH_SIZE_REG_5 0x222c
-#define ETH_HEADERS_RETARGET_BASE_REG 0x2230
-#define ETH_HEADERS_RETARGET_CONTROL_REG 0x2234
-#define ETH_HIGH_ADDR_REMAP_REG_0 0x2280
-#define ETH_HIGH_ADDR_REMAP_REG_1 0x2284
-#define ETH_HIGH_ADDR_REMAP_REG_2 0x2288
-#define ETH_HIGH_ADDR_REMAP_REG_3 0x228c
-#define ETH_BASE_ADDR_ENABLE_REG 0x2290
-#define ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2))
-#define ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7))
-#define ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10))
-#define ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10))
-#define ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10))
-#define ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10))
-#define ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10))
-#define ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10))
-#define ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10))
-#define ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10))
-#define ETH_DSCP_0(port) (0x2420 + (port<<10))
-#define ETH_DSCP_1(port) (0x2424 + (port<<10))
-#define ETH_DSCP_2(port) (0x2428 + (port<<10))
-#define ETH_DSCP_3(port) (0x242c + (port<<10))
-#define ETH_DSCP_4(port) (0x2430 + (port<<10))
-#define ETH_DSCP_5(port) (0x2434 + (port<<10))
-#define ETH_DSCP_6(port) (0x2438 + (port<<10))
-#define ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10))
-#define ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10))
-#define ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10))
-#define ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10))
-#define ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10))
-#define ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10))
-#define ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10))
-#define ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10))
-#define ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10))
-#define ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10))
-#define ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10))
-#define ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10))
-#define ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
-#define ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
-#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
-#define ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10)
-#define ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
-#define ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
-#define ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
-#define ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10))
-#define ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10))
-#define ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10))
-#define ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10))
-#define ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10))
-#define ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10))
-#define ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10))
-#define ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10))
-#define ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10))
-#define ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10))
-#define ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10))
-#define ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10))
-#define ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10))
-#define ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10))
-#define ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10))
-#define ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10))
-#define ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10))
-#define ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10))
-#define ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10))
-#define ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10))
-#define ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10))
-#define ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10))
-#define ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10))
-#define ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10))
-#define ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10))
-#define ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10))
-#define ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10))
-#define ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10))
-#define ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10))
-#define ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
-#define ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
-
-/****************************************/
-/* Cunit Debug (for internal use) */
-/****************************************/
-
-#define CUNIT_ADDRESS 0xf340
-#define CUNIT_COMMAND_AND_ID 0xf344
-#define CUNIT_WRITE_DATA_LOW 0xf348
-#define CUNIT_WRITE_DATA_HIGH 0xf34c
-#define CUNIT_WRITE_BYTE_ENABLE 0xf358
-#define CUNIT_READ_DATA_LOW 0xf350
-#define CUNIT_READ_DATA_HIGH 0xf354
-#define CUNIT_READ_ID 0xf35c
-
-/****************************************/
-/* Fast Ethernet Unit Registers */
-/****************************************/
-
-/****************************************/
-/* Ethernet Unit Registers */
-/****************************************/
-
-#define ETH_PHY_ADDR_REG 0x2000
-#define ETH_SMI_REG 0x2004
-#define ETH_UNIT_DEFAULT_ADDR_REG 0x2008
-#define ETH_UNIT_DEFAULTID_REG 0x200c
-#define ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080
-#define ETH_UNIT_INTERRUPT_MASK_REG 0x2084
-#define ETH_UNIT_INTERNAL_USE_REG 0x24fc
-#define ETH_UNIT_ERROR_ADDR_REG 0x2094
-#define ETH_BAR_0 0x2200
-#define ETH_BAR_1 0x2208
-#define ETH_BAR_2 0x2210
-#define ETH_BAR_3 0x2218
-#define ETH_BAR_4 0x2220
-#define ETH_BAR_5 0x2228
-#define ETH_SIZE_REG_0 0x2204
-#define ETH_SIZE_REG_1 0x220c
-#define ETH_SIZE_REG_2 0x2214
-#define ETH_SIZE_REG_3 0x221c
-#define ETH_SIZE_REG_4 0x2224
-#define ETH_SIZE_REG_5 0x222c
-#define ETH_HEADERS_RETARGET_BASE_REG 0x2230
-#define ETH_HEADERS_RETARGET_CONTROL_REG 0x2234
-#define ETH_HIGH_ADDR_REMAP_REG_0 0x2280
-#define ETH_HIGH_ADDR_REMAP_REG_1 0x2284
-#define ETH_HIGH_ADDR_REMAP_REG_2 0x2288
-#define ETH_HIGH_ADDR_REMAP_REG_3 0x228c
-#define ETH_BASE_ADDR_ENABLE_REG 0x2290
-#define ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2))
-#define ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7))
-#define ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10))
-#define ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10))
-#define ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10))
-#define ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10))
-#define ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10))
-#define ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10))
-#define ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10))
-#define ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10))
-#define ETH_DSCP_0(port) (0x2420 + (port<<10))
-#define ETH_DSCP_1(port) (0x2424 + (port<<10))
-#define ETH_DSCP_2(port) (0x2428 + (port<<10))
-#define ETH_DSCP_3(port) (0x242c + (port<<10))
-#define ETH_DSCP_4(port) (0x2430 + (port<<10))
-#define ETH_DSCP_5(port) (0x2434 + (port<<10))
-#define ETH_DSCP_6(port) (0x2438 + (port<<10))
-#define ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10))
-#define ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10))
-#define ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10))
-#define ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10))
-#define ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10))
-#define ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10))
-#define ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10))
-#define ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10))
-#define ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10))
-#define ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10))
-#define ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10))
-#define ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10))
-#define ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
-#define ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
-#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
-#define ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10)
-#define ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
-#define ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
-#define ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
-#define ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10))
-#define ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10))
-#define ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10))
-#define ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10))
-#define ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10))
-#define ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10))
-#define ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10))
-#define ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10))
-#define ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10))
-#define ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10))
-#define ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10))
-#define ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10))
-#define ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10))
-#define ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10))
-#define ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10))
-#define ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10))
-#define ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10))
-#define ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10))
-#define ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10))
-#define ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10))
-#define ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10))
-#define ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10))
-#define ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10))
-#define ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10))
-#define ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10))
-#define ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10))
-#define ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10))
-#define ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10))
-#define ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10))
-#define ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10))
-#define ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10))
-#define ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
-#define ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
-
-/* Compat with interrupts.c */
-#define ETHERNET0_INTERRUPT_CAUSE_REGISTER ETH_INTERRUPT_CAUSE_REG(0)
-#define ETHERNET1_INTERRUPT_CAUSE_REGISTER ETH_INTERRUPT_CAUSE_REG(1)
-#define ETHERNET2_INTERRUPT_CAUSE_REGISTER ETH_INTERRUPT_CAUSE_REG(2)
-
-#define ETHERNET0_INTERRUPT_MASK_REGISTER ETH_INTERRUPT_MASK_REG(0)
-#define ETHERNET1_INTERRUPT_MASK_REGISTER ETH_INTERRUPT_MASK_REG(1)
-#define ETHERNET2_INTERRUPT_MASK_REGISTER ETH_INTERRUPT_MASK_REG(2)
-
-/* Ethernet GT64260 */
-/*
-#define ETHERNET_PHY_ADDRESS_REGISTER 0x2000
-#define ETHERNET_SMI_REGISTER 0x2010
-*/
-/* Ethernet 0 */
-/*
-#define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400
-#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408
-#define ETHERNET0_PORT_COMMAND_REGISTER 0x2410
-#define ETHERNET0_PORT_STATUS_REGISTER 0x2418
-#define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420
-#define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428
-#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430
-#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438
-#define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440
-#define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448
-#define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450
-#define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac
-#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0
-#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4
-#define ETHERNET0_MIB_COUNTER_BASE 0x2500
-*/
-/* Ethernet 1 */
-/*
-#define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800
-#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808
-#define ETHERNET1_PORT_COMMAND_REGISTER 0x2810
-#define ETHERNET1_PORT_STATUS_REGISTER 0x2818
-#define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820
-#define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828
-#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830
-#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838
-#define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840
-#define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848
-#define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850
-#define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac
-#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0
-#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4
-#define ETHERNET1_MIB_COUNTER_BASE 0x2900
-*/
-/* Ethernet 2 */
-/*
-#define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00
-#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08
-#define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10
-#define ETHERNET2_PORT_STATUS_REGISTER 0x2c18
-#define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20
-#define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28
-#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30
-#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38
-#define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40
-#define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48
-#define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50
-#define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac
-#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0
-#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4
-#define ETHERNET2_MIB_COUNTER_BASE 0x2d00
-*/
-
-/****************************************/
-/* SDMA Registers */
-/****************************************/
-
-#define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0
-#define CHANNEL0_CONFIGURATION_REGISTER 0x4000
-#define CHANNEL0_COMMAND_REGISTER 0x4008
-#define CHANNEL0_RX_CMD_STATUS 0x4800
-#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804
-#define CHANNEL0_RX_BUFFER_POINTER 0x4808
-#define CHANNEL0_RX_NEXT_POINTER 0x480c
-#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810
-#define CHANNEL0_TX_CMD_STATUS 0x4C00
-#define CHANNEL0_TX_PACKET_SIZE 0x4C04
-#define CHANNEL0_TX_BUFFER_POINTER 0x4C08
-#define CHANNEL0_TX_NEXT_POINTER 0x4C0c
-#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10
-#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14
-/*
-#define CHANNEL1_CONFIGURATION_REGISTER 0x5000
-#define CHANNEL1_COMMAND_REGISTER 0x5008
-#define CHANNEL1_RX_CMD_STATUS 0x5800
-#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x5804
-#define CHANNEL1_RX_BUFFER_POINTER 0x5808
-#define CHANNEL1_RX_NEXT_POINTER 0x580c
-#define CHANNEL1_TX_CMD_STATUS 0x5C00
-#define CHANNEL1_TX_PACKET_SIZE 0x5C04
-#define CHANNEL1_TX_BUFFER_POINTER 0x5C08
-#define CHANNEL1_TX_NEXT_POINTER 0x5C0c
-#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x5810
-#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x5c10
-#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x5c14
-#define CHANNEL2_CONFIGURATION_REGISTER 0x6000
-#define CHANNEL2_COMMAND_REGISTER 0x6008
-#define CHANNEL2_RX_CMD_STATUS 0x6800
-#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES 0x6804
-#define CHANNEL2_RX_BUFFER_POINTER 0x6808
-#define CHANNEL2_RX_NEXT_POINTER 0x680c
-#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
-#define CHANNEL2_TX_CMD_STATUS 0x6C00
-#define CHANNEL2_TX_PACKET_SIZE 0x6C04
-#define CHANNEL2_TX_BUFFER_POINTER 0x6C08
-#define CHANNEL2_TX_NEXT_POINTER 0x6C0c
-#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
-#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10
-#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER 0x6c14
-*/
-/* SDMA Interrupt */
-/*
-#define SDMA_CAUSE 0xb820
-#define SDMA_MASK 0xb8a0
-*/
-/***************************************/
-/* SDMA Registers */
-/***************************************/
-
-#define SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13))
-#define SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13))
-#define SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13))
-#define SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13))
-#define SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13))
-
-#define SDMA_CAUSE_REG 0xb800
-#define SDMA_MASK_REG 0xb880
-
-/****************************************/
-/* Baude Rate Generators Registers */
-/****************************************/
-
-/* BRG 0 */
-#define BRG0_CONFIGURATION_REGISTER 0xb200
-#define BRG0_BAUDE_TUNING_REGISTER 0xb204
-
-/* BRG 1 */
-#define BRG1_CONFIGURATION_REGISTER 0xb208
-#define BRG1_BAUDE_TUNING_REGISTER 0xb20c
-
-/* BRG 2 */
-#define BRG2_CONFIGURATION_REGISTER 0xb210
-#define BRG2_BAUDE_TUNING_REGISTER 0xb214
-
-/* BRG Interrupts */
-#define BRG_CAUSE_REGISTER 0xb834
-#define BRG_MASK_REGISTER 0xb8b4
-#define BRG_CONFIG_REG(brg) (0xb200 + (brg<<3))
-#define BRG_BAUDE_TUNING_REG(brg) (0xb208 + (brg<<3))
-#define BRG_CAUSE_REG BRG_CAUSE_REGISTER /*0xb8341 */
-#define BRG_MASK_REG BRG_MASK_REGISTER /*0xb8b41 */
-
-/* MISC */
-
-#define MAIN_ROUTING_REGISTER 0xb400
-#define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404
-#define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408
-#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c
-
-/****************************************/
-/* Watchdog registers */
-/****************************************/
-#define WATCHDOG_CONFIGURATION_REGISTER 0xb410
-#define WATCHDOG_VALUE_REGISTER 0xb414
-#define WATCHDOG_CONFIG_REG WATCHDOG_CONFIGURATION_REGISTER /*0xb4101 */
-#define WATCHDOG_VALUE_REG WATCHDOG_VALUE_REGISTER /*0xb4141 */
-
-
-/****************************************/
-/* Flex TDM Registers */
-/****************************************/
-
-/* FTDM Port */
-
-#define FLEXTDM_TRANSMIT_READ_POINTER 0xa800
-#define FLEXTDM_RECEIVE_READ_POINTER 0xa804
-#define FLEXTDM_CONFIGURATION_REGISTER 0xa808
-#define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c
-#define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810
-#define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814
-#define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818
-
-/* FTDM Interrupts */
-
-#define FTDM_CAUSE_REGISTER 0xb830
-#define FTDM_MASK_REGISTER 0xb8b0
-
-
-/****************************************/
-/* GPP Interface Registers */
-/****************************************/
-
-#define GPP_IO_CONTROL 0xf100
-#define GPP_LEVEL_CONTROL 0xf110
-#define GPP_VALUE 0xf104
-#define GPP_INTERRUPT_CAUSE 0xf108
-#define GPP_INTERRUPT_MASK 0xf10c
-#define GPP_INTERRUPT_MASK0 GPP_INTERRUPT_MASK /* 0xf10c1 */
-#define GPP_INTERRUPT_MASK1 0xf114
-#define GPP_VALUE_SET 0xf118
-#define GPP_VALUE_CLEAR 0xf11c
-
-/****************************************/
-/* MPP Interface Registers */
-/****************************************/
-#define MPP_CONTROL0 0xf000
-#define MPP_CONTROL1 0xf004
-#define MPP_CONTROL2 0xf008
-#define MPP_CONTROL3 0xf00c
-#define DEBUG_PORT_MULTIPLEX 0xf014
- /*#define SERIAL_PORT_MULTIPLEX 0xf0101 */
-
-/****************************************/
-/* Interrupt Controller Registers */
-/****************************************/
-
-/****************************************/
-/* Interrupts */
-/****************************************/
-/****************************************/
-/* Interrupts (checked I.A. 14.10.02) */
-/****************************************/
-
-#define LOW_INTERRUPT_CAUSE_REGISTER 0x004 /* gt64260: 0xc181 */
-#define HIGH_INTERRUPT_CAUSE_REGISTER 0x00c /* gt64260: 0xc681 */
-#define CPU_INTERRUPT_MASK_REGISTER_LOW 0x014 /* gt64260: 0xc1c1 */
-#define CPU_INTERRUPT_MASK_REGISTER_HIGH 0x01c /* gt64260: 0xc6c1 */
-#define CPU_SELECT_CAUSE_REGISTER 0x024 /* gt64260: 0xc701 */
-#define CPU_INTERRUPT_1_MASK_REGISTER_LOW 0x034 /* new in the MV64360 and MV64460 */
-#define CPU_INTERRUPT_1_MASK_REGISTER_HIGH 0x03c /* new in the MV64360 and MV64460 */
-#define CPU_SELECT_1_CAUSE_REGISTER 0x044 /* new in the MV64360 and MV64460 */
-#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0x054 /* gt64260: 0xc241 */
-#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0x05c /* gt64260: 0xc641 */
-#define PCI_0SELECT_CAUSE 0x064 /* gt64260: 0xc741 */
-#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0x074 /* gt64260: 0xca41 */
-#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0x07c /* gt64260: 0xce41 */
-#define PCI_1SELECT_CAUSE 0x084 /* gt64260: 0xcf41 */
-/*#define CPU_INT_0_MASK 0xe60 signal is not multiplexed on MPP in the MV64360 and MV64460 */
-/*#define CPU_INT_1_MASK 0xe64 signal is not multiplexed on MPP in the MV64360 and MV64460 */
-/*#define CPU_INT_2_MASK 0xe68 signal is not multiplexed on MPP in the MV64360 and MV64460 */
-/*#define CPU_INT_3_MASK 0xe6c signal is not multiplexed on MPP in the MV64360 and MV64460 */
-
-#define MAIN_INTERRUPT_CAUSE_LOW LOW_INTERRUPT_CAUSE_REGISTER /* 0x0041 */
-#define MAIN_INTERRUPT_CAUSE_HIGH HIGH_INTERRUPT_CAUSE_REGISTER /* 0x00c1 */
-#define CPU_INTERRUPT0_MASK_LOW CPU_INTERRUPT_MASK_REGISTER_LOW /* 0x0141 */
-#define CPU_INTERRUPT0_MASK_HIGH CPU_INTERRUPT_MASK_REGISTER_HIGH /*0x01c1 */
-#define CPU_INTERRUPT0_SELECT_CAUSE CPU_SELECT_CAUSE_REGISTER /* 0x0241 */
-#define CPU_INTERRUPT1_MASK_LOW CPU_INTERRUPT_1_MASK_REGISTER_LOW /* 0x0341 */
-#define CPU_INTERRUPT1_MASK_HIGH CPU_INTERRUPT_1_MASK_REGISTER_HIGH /* 0x03c1 */
-#define CPU_INTERRUPT1_SELECT_CAUSE CPU_SELECT_1_CAUSE_REGISTER /* 0x0441 */
-#define INTERRUPT0_MASK_0_LOW PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW /* 0x0541 */
-#define INTERRUPT0_MASK_0_HIGH PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH /* 0x05c1 */
-#define INTERRUPT0_SELECT_CAUSE PCI_0SELECT_CAUSE /* 0x0641 */
-#define INTERRUPT1_MASK_0_LOW PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW /* 0x0741 */
-#define INTERRUPT1_MASK_0_HIGH PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH /* 0x07c1 */
-#define INTERRUPT1_SELECT_CAUSE PCI_1SELECT_CAUSE /* 0x0841 */
-
-/****************************************/
-/* I2C Registers */
-/****************************************/
-
-#define I2C_SLAVE_ADDRESS 0xc000
-#define I2C_EXTENDED_SLAVE_ADDRESS 0xc040
-#define I2C_DATA 0xc004
-#define I2C_CONTROL 0xc008
-#define I2C_STATUS_BAUDE_RATE 0xc00C
-#define I2C_SOFT_RESET 0xc01c
-#define I2C_SLAVE_ADDR I2C_SLAVE_ADDRESS /* 0xc0001 */
-#define I2C_EXTENDED_SLAVE_ADDR I2C_EXTENDED_SLAVE_ADDRESS /*0xc0101 */
-
-/****************************************/
-/* MPSC Registers */
-/****************************************/
-
- /* MPSCs Clocks Routing Registers */
-
-#define MPSC_ROUTING_REG 0xb400
-#define MPSC_RX_CLOCK_ROUTING_REG 0xb404
-#define MPSC_TX_CLOCK_ROUTING_REG 0xb408
-
- /* MPSCs Interrupts Registers */
-
-#define MPSC_CAUSE_REG(port) (0xb804 + (port<<3))
-#define MPSC_MASK_REG(port) (0xb884 + (port<<3))
-
-#define MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12))
-#define MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12))
-#define MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12))
-#define MPSC_CHANNEL_REG1(port) (0x800c + (port<<12))
-#define MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12))
-#define MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12))
-#define MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12))
-#define MPSC_CHANNEL_REG5(port) (0x801c + (port<<12))
-#define MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12))
-#define MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12))
-#define MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12))
-#define MPSC_CHANNEL_REG9(port) (0x802c + (port<<12))
-#define MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12))
-
-
-/* MPSC0 */
-
-#define MPSC0_MAIN_CONFIGURATION_LOW 0x8000
-#define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004
-#define MPSC0_PROTOCOL_CONFIGURATION 0x8008
-#define CHANNEL0_REGISTER1 0x800c
-#define CHANNEL0_REGISTER2 0x8010
-#define CHANNEL0_REGISTER3 0x8014
-#define CHANNEL0_REGISTER4 0x8018
-#define CHANNEL0_REGISTER5 0x801c
-#define CHANNEL0_REGISTER6 0x8020
-#define CHANNEL0_REGISTER7 0x8024
-#define CHANNEL0_REGISTER8 0x8028
-#define CHANNEL0_REGISTER9 0x802c
-#define CHANNEL0_REGISTER10 0x8030
-#define CHANNEL0_REGISTER11 0x8034
-
-/* MPSC1 */
-
-#define MPSC1_MAIN_CONFIGURATION_LOW 0x8840
-#define MPSC1_MAIN_CONFIGURATION_HIGH 0x8844
-#define MPSC1_PROTOCOL_CONFIGURATION 0x8848
-#define CHANNEL1_REGISTER1 0x884c
-#define CHANNEL1_REGISTER2 0x8850
-#define CHANNEL1_REGISTER3 0x8854
-#define CHANNEL1_REGISTER4 0x8858
-#define CHANNEL1_REGISTER5 0x885c
-#define CHANNEL1_REGISTER6 0x8860
-#define CHANNEL1_REGISTER7 0x8864
-#define CHANNEL1_REGISTER8 0x8868
-#define CHANNEL1_REGISTER9 0x886c
-#define CHANNEL1_REGISTER10 0x8870
-#define CHANNEL1_REGISTER11 0x8874
-
-/* MPSC2 */
-
-#define MPSC2_MAIN_CONFIGURATION_LOW 0x9040
-#define MPSC2_MAIN_CONFIGURATION_HIGH 0x9044
-#define MPSC2_PROTOCOL_CONFIGURATION 0x9048
-#define CHANNEL2_REGISTER1 0x904c
-#define CHANNEL2_REGISTER2 0x9050
-#define CHANNEL2_REGISTER3 0x9054
-#define CHANNEL2_REGISTER4 0x9058
-#define CHANNEL2_REGISTER5 0x905c
-#define CHANNEL2_REGISTER6 0x9060
-#define CHANNEL2_REGISTER7 0x9064
-#define CHANNEL2_REGISTER8 0x9068
-#define CHANNEL2_REGISTER9 0x906c
-#define CHANNEL2_REGISTER10 0x9070
-#define CHANNEL2_REGISTER11 0x9074
-
-/* MPSCs Interrupts */
-
-#define MPSC0_CAUSE 0xb824
-#define MPSC0_MASK 0xb8a4
-#define MPSC1_CAUSE 0xb828
-#define MPSC1_MASK 0xb8a8
-#define MPSC2_CAUSE 0xb82c
-#define MPSC2_MASK 0xb8ac
-
-/*******************************************/
-/* CUNIT Registers */
-/*******************************************/
-
- /* Address Decoding Register Map */
-
-#define CUNIT_BASE_ADDR_REG0 0xf200
-#define CUNIT_BASE_ADDR_REG1 0xf208
-#define CUNIT_BASE_ADDR_REG2 0xf210
-#define CUNIT_BASE_ADDR_REG3 0xf218
-#define CUNIT_SIZE0 0xf204
-#define CUNIT_SIZE1 0xf20c
-#define CUNIT_SIZE2 0xf214
-#define CUNIT_SIZE3 0xf21c
-#define CUNIT_HIGH_ADDR_REMAP_REG0 0xf240
-#define CUNIT_HIGH_ADDR_REMAP_REG1 0xf244
-#define CUNIT_BASE_ADDR_ENABLE_REG 0xf250
-#define MPSC0_ACCESS_PROTECTION_REG 0xf254
-#define MPSC1_ACCESS_PROTECTION_REG 0xf258
-#define CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C
-
- /* Error Report Registers */
-
-#define CUNIT_INTERRUPT_CAUSE_REG 0xf310
-#define CUNIT_INTERRUPT_MASK_REG 0xf314
-#define CUNIT_ERROR_ADDR 0xf318
-
- /* Cunit Control Registers */
-
-#define CUNIT_ARBITER_CONTROL_REG 0xf300
-#define CUNIT_CONFIG_REG 0xb40c
-#define CUNIT_CRROSBAR_TIMEOUT_REG 0xf304
-
- /* Cunit Debug Registers */
-
-#define CUNIT_DEBUG_LOW 0xf340
-#define CUNIT_DEBUG_HIGH 0xf344
-#define CUNIT_MMASK 0xf380
-
-#endif /* __INCmv_gen_regh */
if TARGET_AFEB9260
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "afeb9260"
if TARGET_SOCFPGA_CYCLONE5
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "socfpga"
if TARGET_ARISTAINETOS
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "aristainetos"
MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
+ ? (IMX_GPIO_NR(3, 20)) : -1;
+}
+
static void setup_spi(void)
{
int i;
if TARGET_APF27
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "apf27"
if TARGET_INTEGRATORAP_CM720T
-config SYS_CPU
- default "arm720t"
-
config SYS_BOARD
default "integrator"
if TARGET_INTEGRATORAP_CM920T
-config SYS_CPU
- default "arm920t"
-
config SYS_BOARD
default "integrator"
if TARGET_INTEGRATORCP_CM920T
-config SYS_CPU
- default "arm920t"
-
config SYS_BOARD
default "integrator"
if TARGET_INTEGRATORAP_CM926EJS
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "integrator"
if TARGET_INTEGRATORCP_CM926EJS
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "integrator"
if TARGET_INTEGRATORCP_CM1136
-config SYS_CPU
- default "arm1136"
-
config SYS_BOARD
default "integrator"
if TARGET_INTEGRATORAP_CM946ES
-config SYS_CPU
- default "arm946es"
-
config SYS_BOARD
default "integrator"
if TARGET_INTEGRATORCP_CM946ES
-config SYS_CPU
- default "arm946es"
-
config SYS_BOARD
default "integrator"
if TARGET_VEXPRESS_CA15_TC2
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "vexpress"
if TARGET_VEXPRESS_CA5X2
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "vexpress"
if TARGET_VEXPRESS_CA9X4
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "vexpress"
if TARGET_AT91RM9200EK
-config SYS_CPU
- default "arm920t"
-
config SYS_BOARD
default "at91rm9200ek"
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_pio.h>
+#include <status_led.h>
/* bit mask in PIO port B */
#define GREEN_LED (1<<0)
if TARGET_AT91SAM9260EK
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "at91sam9260ek"
#include <common.h>
#include <asm/io.h>
#include <asm/arch/gpio.h>
+#include <status_led.h>
void coloured_LED_init(void)
{
if TARGET_AT91SAM9261EK
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "at91sam9261ek"
if TARGET_AT91SAM9263EK
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "at91sam9263ek"
if TARGET_AT91SAM9M10G45EK
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "at91sam9m10g45ek"
if TARGET_AT91SAM9N12EK
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "at91sam9n12ek"
if TARGET_AT91SAM9RLEK
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "at91sam9rlek"
if TARGET_AT91SAM9X5EK
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "at91sam9x5ek"
if TARGET_SAMA5D3_XPLAINED
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "sama5d3_xplained"
if TARGET_SAMA5D3XEK
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "sama5d3xek"
if TARGET_OT1200
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
- string
default "ot1200"
config SYS_VENDOR
- string
default "bachmann"
config SYS_SOC
- string
default "mx6"
config SYS_CONFIG_NAME
- string
default "ot1200"
endif
#include <malloc.h>
#include <asm/arch/mx6-pins.h>
#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/sata.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/arch/crm_regs.h>
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
}
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1;
+}
+
+static iomux_v3_cfg_t const feature_pads[] = {
+ /* SD card detect */
+ MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN),
+
+ /* eMMC soldered? */
+ MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP),
+};
+
+static void setup_iomux_features(void)
+{
+ imx_iomux_v3_setup_multiple_pads(feature_pads,
+ ARRAY_SIZE(feature_pads));
+}
+
int board_early_init_f(void)
{
setup_iomux_uart();
setup_iomux_spi();
+ setup_iomux_features();
return 0;
}
MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
+iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
int board_mmc_getcd(struct mmc *mmc)
{
- return 1;
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret;
+
+ if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
+ gpio_direction_input(IMX_GPIO_NR(4, 5));
+ ret = gpio_get_value(IMX_GPIO_NR(4, 5));
+ } else {
+ gpio_direction_input(IMX_GPIO_NR(1, 4));
+ ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
+ }
+
+ return ret;
}
-struct fsl_esdhc_cfg usdhc_cfg[] = {
+struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC3_BASE_ADDR},
+ {USDHC4_BASE_ADDR},
};
int board_mmc_init(bd_t *bis)
{
+ s32 status = 0;
+ u32 index = 0;
+
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- usdhc_cfg[0].max_bus_width = 8;
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
- imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ usdhc_cfg[0].max_bus_width = 8;
+ usdhc_cfg[1].max_bus_width = 4;
+
+ for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+ switch (index) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) then supported by the board (%d)\n",
+ index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ return status;
+ }
+
+ status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ }
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+ return status;
}
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* enable ecspi3 clocks */
enable_cspi_clock(1, 2);
+#ifdef CONFIG_CMD_SATA
+ setup_sata();
+#endif
+
return 0;
}
if TARGET_BALLOON3
-config SYS_CPU
- default "pxa"
-
config SYS_BOARD
default "balloon3"
if TARGET_TITANIUM
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "titanium"
if TARGET_APX4DEVKIT
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "apx4devkit"
if TARGET_SNAPPER9260
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "snapper9260"
if TARGET_NITROGEN6X
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "nitrogen6x"
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/sata.h>
+#include <asm/imx-common/spi.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/video.h>
#include <mmc.h>
if TARGET_BCM28155_AP
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "bcm28155_ap"
if TARGET_BCM958300K
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "bcm_ep"
if TARGET_BCM958622HR
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "bcm_ep"
if TARGET_SBC35_A9G20
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "sbc35_a9g20"
if TARGET_TNY_A9260
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "tny_a9260"
if TARGET_USB_A9263
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "usb_a9263"
if TARGET_EDB93XX
-config SYS_CPU
- default "arm920t"
-
config SYS_BOARD
default "edb93xx"
if TARGET_CM4008
-config SYS_CPU
- default "arm920t"
-
config SYS_BOARD
default "cm4008"
if TARGET_CM41XX
-config SYS_CPU
- default "arm920t"
-
config SYS_BOARD
default "cm41xx"
void board_show_activity (ulong timestamp)
{
#ifdef CONFIG_STATUS_LED
- if ((timestamp % (CONFIG_SYS_HZ / 2) == 0)
+ if ((timestamp % (CONFIG_SYS_HZ / 2)) == 0)
lcd_heartbeat ();
#endif
}
if TARGET_CM_FX6
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
- string
default "cm_fx6"
config SYS_VENDOR
- string
default "compulab"
config SYS_SOC
- string
default "mx6"
config SYS_CONFIG_NAME
- string
default "cm_fx6"
endif
#include <netdev.h>
#include <fdt_support.h>
#include <sata.h>
-#include <serial_mxc.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/iomux.h>
#include <asm/imx-common/sata.h>
#include <asm/io.h>
#include <asm/gpio.h>
+#include <dm/platform_data/serial_mxc.h>
#include "common.h"
#include "../common/eeprom.h"
#ifdef CONFIG_DWC_AHSATA
static int cm_fx6_issd_gpios[] = {
/* The order of the GPIOs in the array is important! */
+ CM_FX6_SATA_LDO_EN,
CM_FX6_SATA_PHY_SLP,
CM_FX6_SATA_NRSTDLY,
CM_FX6_SATA_PWREN,
CM_FX6_SATA_NSTANDBY1,
CM_FX6_SATA_NSTANDBY2,
- CM_FX6_SATA_LDO_EN,
};
static void cm_fx6_sata_power(int on)
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
+#include <asm/imx-common/spi.h>
#include <fsl_esdhc.h>
#include "common.h"
spl_mx6s_dram_init(DDR_32BIT_1GB, false);
bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
- if (bank1_size == 0x40000000)
- return 0;
-
+ bank2_size = get_ram_size((long int *)PHYS_SDRAM_2, 0x80000000);
if (bank1_size == 0x20000000) {
+ if (bank2_size == 0x20000000)
+ return 0;
+
spl_mx6s_dram_init(DDR_32BIT_512MB, true);
return 0;
}
if TARGET_CM_T335
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "cm_t335"
#include <i2c.h>
#include <usb.h>
#include <mmc.h>
-#include <nand.h>
#include <twl4030.h>
-#include <bmp_layout.h>
#include <linux/compiler.h>
#include <asm/io.h>
+#include <asm/errno.h>
#include <asm/arch/mem.h>
#include <asm/arch/mux.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/ehci-omap.h>
#include <asm/gpio.h>
+#include "../common/common.h"
#include "../common/eeprom.h"
DECLARE_GLOBAL_DATA_PTR;
"NAND",
};
-static u32 gpmc_net_config[GPMC_MAX_REG] = {
- NET_GPMC_CONFIG1,
- NET_GPMC_CONFIG2,
- NET_GPMC_CONFIG3,
- NET_GPMC_CONFIG4,
- NET_GPMC_CONFIG5,
- NET_GPMC_CONFIG6,
- 0
-};
-
-static u32 gpmc_nand_config[GPMC_MAX_REG] = {
- M_NAND_GPMC_CONFIG1,
- M_NAND_GPMC_CONFIG2,
- M_NAND_GPMC_CONFIG3,
- M_NAND_GPMC_CONFIG4,
- M_NAND_GPMC_CONFIG5,
- M_NAND_GPMC_CONFIG6,
- 0,
-};
-
-#ifdef CONFIG_LCD
-#ifdef CONFIG_CMD_NAND
-static int splash_load_from_nand(u32 bmp_load_addr)
-{
- struct bmp_header *bmp_hdr;
- int res, splash_screen_nand_offset = 0x100000;
- size_t bmp_size, bmp_header_size = sizeof(struct bmp_header);
-
- if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp)
- goto splash_address_too_high;
-
- res = nand_read_skip_bad(&nand_info[nand_curr_device],
- splash_screen_nand_offset, &bmp_header_size,
- NULL, nand_info[nand_curr_device].size,
- (u_char *)bmp_load_addr);
- if (res < 0)
- return res;
-
- bmp_hdr = (struct bmp_header *)bmp_load_addr;
- bmp_size = le32_to_cpu(bmp_hdr->file_size);
-
- if (bmp_load_addr + bmp_size >= gd->start_addr_sp)
- goto splash_address_too_high;
-
- return nand_read_skip_bad(&nand_info[nand_curr_device],
- splash_screen_nand_offset, &bmp_size,
- NULL, nand_info[nand_curr_device].size,
- (u_char *)bmp_load_addr);
-
-splash_address_too_high:
- printf("Error: splashimage address too high. Data overwrites U-Boot "
- "and/or placed beyond DRAM boundaries.\n");
-
- return -1;
-}
-#else
-static inline int splash_load_from_nand(void)
-{
- return -1;
-}
-#endif /* CONFIG_CMD_NAND */
-
#ifdef CONFIG_SPL_BUILD
/*
* Routine: get_board_mem_timings
}
#endif
+#define CM_T35_SPLASH_NAND_OFFSET 0x100000
+
int splash_screen_prepare(void)
{
- char *env_splashimage_value;
- u32 bmp_load_addr;
-
- env_splashimage_value = getenv("splashimage");
- if (env_splashimage_value == NULL)
- return -1;
-
- bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16);
- if (bmp_load_addr == 0) {
- printf("Error: bad splashimage address specified\n");
- return -1;
- }
-
- return splash_load_from_nand(bmp_load_addr);
+ return cl_splash_screen_prepare(CM_T35_SPLASH_NAND_OFFSET);
}
-#endif /* CONFIG_LCD */
/*
* Routine: board_init
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0],
- CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M);
-
/* board id for Linux */
if (get_cpu_family() == CPU_OMAP34XX)
gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
return 0;
}
-static u32 cm_t3x_rev;
-
/*
* Routine: get_board_rev
* Description: read system revision
*/
u32 get_board_rev(void)
{
- if (!cm_t3x_rev)
- cm_t3x_rev = cl_eeprom_get_board_rev();
-
- return cm_t3x_rev;
+ return cl_eeprom_get_board_rev();
};
-/*
- * Routine: misc_init_r
- * Description: display die ID
- */
int misc_init_r(void)
{
- u32 board_rev = get_board_rev();
- u32 rev_major = board_rev / 100;
- u32 rev_minor = board_rev - (rev_major * 100);
-
- if ((rev_minor / 10) * 10 == rev_minor)
- rev_minor = rev_minor / 10;
-
- printf("PCB: %u.%u\n", rev_major, rev_minor);
+ cl_print_pcb_info();
dieid_num_r();
return 0;
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/
MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/
- MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); /*JTAG_nTRST*/
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)); /*JTAG_NTRST*/
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/
}
#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#define SB_T35_WP_GPIO 59
+
int board_mmc_getcd(struct mmc *mmc)
{
u8 val;
int board_mmc_init(bd_t *bis)
{
- return omap_mmc_init(0, 0, 0, -1, 59);
+ return omap_mmc_init(0, 0, 0, -1, SB_T35_WP_GPIO);
}
#endif
-/*
- * Routine: setup_net_chip_gmpc
- * Description: Setting up the configuration GPMC registers specific to the
- * Ethernet hardware.
- */
-static void setup_net_chip_gmpc(void)
-{
- struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
-
- enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5],
- CM_T3X_SMC911X_BASE, GPMC_SIZE_16M);
- enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4],
- SB_T35_SMC911X_BASE, GPMC_SIZE_16M);
-
- /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
- writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
-
- /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
- writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
-
- /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
- writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
- &ctrl_base->gpmc_nadv_ale);
-}
-
#ifdef CONFIG_SYS_I2C_OMAP34XX
/*
* Routine: reset_net_chip
* Description: reset the Ethernet controller via TPS65930 GPIO
*/
-static void reset_net_chip(void)
+static int cm_t3x_reset_net_chip(int gpio)
{
/* Set GPIO1 of TPS65930 as output */
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03,
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C,
0x02);
mdelay(1);
+ return 0;
}
#else
-static inline void reset_net_chip(void) {}
+static inline int cm_t3x_reset_net_chip(int gpio) { return 0; }
#endif
#ifdef CONFIG_SMC911X
return eth_setenv_enetaddr("ethaddr", enetaddr);
}
-
/*
* Routine: board_eth_init
* Description: initialize module and base-board Ethernet chips
{
int rc = 0, rc1 = 0;
- setup_net_chip_gmpc();
- reset_net_chip();
-
rc1 = handle_mac_address();
if (rc1)
printf("No MAC address found! ");
- rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE);
+ rc1 = cl_omap3_smc911x_init(0, 5, CM_T3X_SMC911X_BASE,
+ cm_t3x_reset_net_chip, -EINVAL);
if (rc1 > 0)
rc++;
- rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE);
+ rc1 = cl_omap3_smc911x_init(1, 4, SB_T35_SMC911X_BASE, NULL, -EINVAL);
if (rc1 > 0)
rc++;
}
#endif
-void __weak get_board_serial(struct tag_serialnr *serialnr)
-{
- /*
- * This corresponds to what happens when we can communicate with the
- * eeprom but don't get a valid board serial value.
- */
- serialnr->low = 0;
- serialnr->high = 0;
-};
-
#ifdef CONFIG_USB_EHCI_OMAP
struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
#define SB_T35_USB_HUB_RESET_GPIO 167
int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
u8 val;
int offset;
- if (gpio_request(SB_T35_USB_HUB_RESET_GPIO, "SB-T35 usb hub reset")) {
- printf("Error: can't obtain GPIO %d for SB-T35 usb hub reset",
- SB_T35_USB_HUB_RESET_GPIO);
- return -1;
- }
-
- gpio_direction_output(SB_T35_USB_HUB_RESET_GPIO, 0);
- udelay(10);
- gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1);
- udelay(1000);
+ cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst");
offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1;
twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val);
int ehci_hcd_stop(void)
{
+ cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO);
return omap_ehci_hcd_stop();
}
#endif /* CONFIG_USB_EHCI_OMAP */
--- /dev/null
+if TARGET_CM_T3517
+
+config SYS_BOARD
+ default "cm_t3517"
+
+config SYS_VENDOR
+ default "compulab"
+
+config SYS_CONFIG_NAME
+ default "cm_t3517"
+
+endif
--- /dev/null
+CM_T3517 BOARD
+M: Igor Grinberg <grinberg@compulab.co.il>
+S: Maintained
+F: board/compulab/cm_t3517/
+F: include/configs/cm_t3517.h
+F: configs/cm_t3517_defconfig
--- /dev/null
+#
+# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+#
+# Authors: Igor Grinberg <grinberg@compulab.co.il>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cm_t3517.o mux.o
--- /dev/null
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <status_led.h>
+#include <net.h>
+#include <netdev.h>
+#include <usb.h>
+#include <mmc.h>
+#include <linux/compiler.h>
+#include <linux/usb/musb.h>
+
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/am35x_def.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/musb.h>
+#include <asm/omap_musb.h>
+#include <asm/ehci-omap.h>
+
+#include "../common/common.h"
+#include "../common/eeprom.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "CM-T3517 board",
+ "NAND 128/512M",
+};
+
+#ifdef CONFIG_USB_MUSB_AM35X
+static struct musb_hdrc_config cm_t3517_musb_config = {
+ .multipoint = 1,
+ .dyn_fifo = 1,
+ .num_eps = 16,
+ .ram_bits = 12,
+};
+
+static struct omap_musb_board_data cm_t3517_musb_board_data = {
+ .set_phy_power = am35x_musb_phy_power,
+ .clear_irq = am35x_musb_clear_irq,
+ .reset = am35x_musb_reset,
+};
+
+static struct musb_hdrc_platform_data cm_t3517_musb_pdata = {
+#if defined(CONFIG_MUSB_HOST)
+ .mode = MUSB_HOST,
+#elif defined(CONFIG_MUSB_GADGET)
+ .mode = MUSB_PERIPHERAL,
+#else
+#error "Please define either CONFIG_MUSB_HOST or CONFIG_MUSB_GADGET"
+#endif
+ .config = &cm_t3517_musb_config,
+ .power = 250,
+ .platform_ops = &am35x_ops,
+ .board_data = &cm_t3517_musb_board_data,
+};
+
+static void cm_t3517_musb_init(void)
+{
+ /*
+ * Set up USB clock/mode in the DEVCONF2 register.
+ * USB2.0 PHY reference clock is 13 MHz
+ */
+ clrsetbits_le32(&am35x_scm_general_regs->devconf2,
+ CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE,
+ CONF2_REFFREQ_13MHZ | CONF2_SESENDEN |
+ CONF2_VBDTCTEN | CONF2_DATPOL);
+
+ if (musb_register(&cm_t3517_musb_pdata, &cm_t3517_musb_board_data,
+ (void *)AM35XX_IPSS_USBOTGSS_BASE))
+ printf("Failed initializing AM35x MUSB!\n");
+}
+#else
+static inline void am3517_evm_musb_init(void) {}
+#endif
+
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+#endif
+
+ cm_t3517_musb_init();
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ cl_print_pcb_info();
+ dieid_num_r();
+
+ return 0;
+}
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#define SB_T35_CD_GPIO 144
+#define SB_T35_WP_GPIO 59
+
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, SB_T35_CD_GPIO, SB_T35_WP_GPIO);
+}
+#endif
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONTROL_EFUSE_EMAC_LSB 0x48002380
+#define CONTROL_EFUSE_EMAC_MSB 0x48002384
+
+static int am3517_get_efuse_enetaddr(u8 *enetaddr)
+{
+ u32 lsb = __raw_readl(CONTROL_EFUSE_EMAC_LSB);
+ u32 msb = __raw_readl(CONTROL_EFUSE_EMAC_MSB);
+
+ enetaddr[0] = (u8)((msb >> 16) & 0xff);
+ enetaddr[1] = (u8)((msb >> 8) & 0xff);
+ enetaddr[2] = (u8)(msb & 0xff);
+ enetaddr[3] = (u8)((lsb >> 16) & 0xff);
+ enetaddr[4] = (u8)((lsb >> 8) & 0xff);
+ enetaddr[5] = (u8)(lsb & 0xff);
+
+ return is_valid_ether_addr(enetaddr);
+}
+
+static inline int cm_t3517_init_emac(bd_t *bis)
+{
+ int ret = cpu_eth_init(bis);
+
+ if (ret > 0)
+ return ret;
+
+ printf("Failed initializing EMAC! ");
+ return 0;
+}
+#else /* !CONFIG_DRIVER_TI_EMAC */
+static inline int am3517_get_efuse_enetaddr(u8 *enetaddr) { return 1; }
+static inline int cm_t3517_init_emac(bd_t *bis) { return 0; }
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+/*
+ * Routine: handle_mac_address
+ * Description: prepare MAC address for on-board Ethernet.
+ */
+static int cm_t3517_handle_mac_address(void)
+{
+ unsigned char enetaddr[6];
+ int ret;
+
+ ret = eth_getenv_enetaddr("ethaddr", enetaddr);
+ if (ret)
+ return 0;
+
+ ret = cl_eeprom_read_mac_addr(enetaddr);
+ if (ret) {
+ ret = am3517_get_efuse_enetaddr(enetaddr);
+ if (ret)
+ return ret;
+ }
+
+ if (!is_valid_ether_addr(enetaddr))
+ return -1;
+
+ return eth_setenv_enetaddr("ethaddr", enetaddr);
+}
+
+#define SB_T35_ETH_RST_GPIO 164
+
+/*
+ * Routine: board_eth_init
+ * Description: initialize module and base-board Ethernet chips
+ */
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0, rc1 = 0;
+
+ rc1 = cm_t3517_handle_mac_address();
+ if (rc1)
+ printf("No MAC address found! ");
+
+ rc1 = cm_t3517_init_emac(bis);
+ if (rc1 > 0)
+ rc++;
+
+ rc1 = cl_omap3_smc911x_init(0, 4, CONFIG_SMC911X_BASE,
+ NULL, SB_T35_ETH_RST_GPIO);
+ if (rc1 > 0)
+ rc++;
+
+ return rc;
+}
+
+#ifdef CONFIG_USB_EHCI_OMAP
+static struct omap_usbhs_board_data cm_t3517_usbhs_bdata = {
+ .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
+};
+
+#define CM_T3517_USB_HUB_RESET_GPIO 152
+#define SB_T35_USB_HUB_RESET_GPIO 98
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ cl_usb_hub_init(CM_T3517_USB_HUB_RESET_GPIO, "cm-t3517 hub rst");
+ cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst");
+
+ return omap_ehci_hcd_init(index, &cm_t3517_usbhs_bdata, hccr, hcor);
+}
+
+int ehci_hcd_stop(void)
+{
+ cl_usb_hub_deinit(CM_T3517_USB_HUB_RESET_GPIO);
+ cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO);
+
+ return omap_ehci_hcd_stop();
+}
+#endif /* CONFIG_USB_EHCI_OMAP */
--- /dev/null
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+
+void set_muxconf_regs(void)
+{
+ /* SDRC */
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7));
+
+ /* GPMC */
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));
+
+ /* SB-T35 Ethernet */
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0));
+ /* DVI enable */
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPIO_54*/
+ /* DataImage backlight */
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/
+
+ /* SB-T35 SD/MMC WP GPIO59 */
+ MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)); /*GPIO_59*/
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0));
+ /* SB-T35 Audio Enable GPIO61 */
+ MUX_VAL(CP(GPMC_NBE1), (IDIS | PTU | EN | M4)); /*GPIO_61*/
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0));
+ /* SB-T35 Ethernet IRQ GPIO65 */
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); /*GPIO_65*/
+
+ /* UART3 Console */
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
+ /* RTC V3020 nCS GPIO163 */
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | EN | M4)); /*GPIO_163*/
+ /* SB-T35 Ethernet nRESET GPIO164 */
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)); /*GPIO_164*/
+
+ /* SB-T35 SD/MMC CD GPIO144 */
+ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M4)); /*GPIO_144*/
+ /* WIFI nRESET GPIO145 */
+ MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)); /*GPIO_145*/
+ /* USB1 PHY Reset GPIO 146 */
+ MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)); /*GPIO_146*/
+ /* USB2 PHY Reset GPIO 147 */
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)); /*GPIO_147*/
+
+ /* MMC1 */
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));
+
+ /* DSS */
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0));
+
+ /* I2C */
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0));
+
+ /* SB-T35 USB HUB Reset GPIO98 */
+ MUX_VAL(CP(CCDC_WEN), (IDIS | PTU | EN | M4)); /*GPIO_98*/
+ /* CM-T3517 USB HUB Reset GPIO152 */
+ MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/
+
+ /* RMII */
+ MUX_VAL(CP(RMII_MDIO_DATA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(RMII_MDIO_CLK), (M0));
+ MUX_VAL(CP(RMII_RXD0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(RMII_RXD1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(RMII_RXER), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(RMII_TXD0), (IDIS | M0));
+ MUX_VAL(CP(RMII_TXD1), (IDIS | M0));
+ MUX_VAL(CP(RMII_TXEN), (IDIS | M0));
+ MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTU | DIS | M0));
+
+ /* Green LED GPIO186 */
+ MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*GPIO_186*/
+
+ /* SPI */
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/
+ /* LCD reset GPIO157 */
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/
+
+ /* RTC V3020 CS Enable GPIO160 */
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M4)); /*GPIO_160*/
+ /* SB-T35 LVDS Transmitter SHDN GPIO162 */
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | DIS | M4)); /*GPIO_162*/
+
+ /* USB0 - mUSB */
+ MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0));
+ /* USB1 EHCI */
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/
+ /* USB2 EHCI */
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
+
+ /* SYS_BOOT */
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | DIS | M4)); /*GPIO_2*/
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTU | DIS | M4)); /*GPIO_3*/
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | DIS | M4)); /*GPIO_4*/
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTU | DIS | M4)); /*GPIO_5*/
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTU | DIS | M4)); /*GPIO_6*/
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTU | DIS | M4)); /*GPIO_7*/
+}
#define SB_T54_CD_GPIO 228
#define SB_T54_WP_GPIO 229
-int board_mmc_getcd(struct mmc *mmc)
-{
- return !gpio_get_value(SB_T54_CD_GPIO);
-}
-
int board_mmc_init(bd_t *bis)
{
int ret0, ret1;
- ret0 = omap_mmc_init(0, 0, 0, -1, SB_T54_WP_GPIO);
+ ret0 = omap_mmc_init(0, 0, 0, SB_T54_CD_GPIO, SB_T54_WP_GPIO);
if (ret0)
printf("cm_t54: failed to initialize mmc0\n");
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_SYS_I2C) += eeprom.o
-obj-$(CONFIG_LCD) += omap3_display.o
+obj-y += common.o
+obj-$(CONFIG_SYS_I2C) += eeprom.o
+obj-$(CONFIG_LCD) += omap3_display.o
+obj-$(CONFIG_SPLASH_SCREEN) += splash.o
+obj-$(CONFIG_SMC911X) += omap3_smc911x.o
--- /dev/null
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/bootm.h>
+#include <asm/gpio.h>
+
+#include "common.h"
+#include "eeprom.h"
+
+void cl_print_pcb_info(void)
+{
+ u32 board_rev = get_board_rev();
+ u32 rev_major = board_rev / 100;
+ u32 rev_minor = board_rev - (rev_major * 100);
+
+ if ((rev_minor / 10) * 10 == rev_minor)
+ rev_minor = rev_minor / 10;
+
+ printf("PCB: %u.%u\n", rev_major, rev_minor);
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void __weak get_board_serial(struct tag_serialnr *serialnr)
+{
+ /*
+ * This corresponds to what happens when we can communicate with the
+ * eeprom but don't get a valid board serial value.
+ */
+ serialnr->low = 0;
+ serialnr->high = 0;
+};
+#endif
+
+#ifdef CONFIG_CMD_USB
+int cl_usb_hub_init(int gpio, const char *label)
+{
+ if (gpio_request(gpio, label)) {
+ printf("Error: can't obtain GPIO%d for %s", gpio, label);
+ return -1;
+ }
+
+ gpio_direction_output(gpio, 0);
+ udelay(10);
+ gpio_set_value(gpio, 1);
+ udelay(1000);
+ return 0;
+}
+
+void cl_usb_hub_deinit(int gpio)
+{
+ gpio_free(gpio);
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CL_COMMON_
+#define _CL_COMMON_
+
+#include <asm/errno.h>
+
+void cl_print_pcb_info(void);
+
+#ifdef CONFIG_CMD_USB
+int cl_usb_hub_init(int gpio, const char *label);
+void cl_usb_hub_deinit(int gpio);
+#else /* !CONFIG_CMD_USB */
+static inline int cl_usb_hub_init(int gpio, const char *label)
+{
+ return -ENOSYS;
+}
+static inline void cl_usb_hub_deinit(int gpio) {}
+#endif /* CONFIG_CMD_USB */
+
+#ifdef CONFIG_SPLASH_SCREEN
+int cl_splash_screen_prepare(int nand_offset);
+#else /* !CONFIG_SPLASH_SCREEN */
+static inline int cl_splash_screen_prepare(int nand_offset)
+{
+ return -ENOSYS;
+}
+#endif /* CONFIG_SPLASH_SCREEN */
+
+#ifdef CONFIG_SMC911X
+int cl_omap3_smc911x_init(int id, int cs, u32 base_addr,
+ int (*reset)(int), int rst_gpio);
+#else /* !CONFIG_SMC911X */
+static inline int cl_omap3_smc911x_init(int id, int cs, u32 base_addr,
+ int (*reset)(int), int rst_gpio)
+{
+ return -ENOSYS;
+}
+#endif /* CONFIG_SMC911X */
+
+#endif /* _CL_COMMON_ */
return cl_eeprom_read(offset, buf, 6);
}
+static u32 board_rev;
+
/*
* Routine: cl_eeprom_get_board_rev
* Description: read system revision from eeprom
*/
u32 cl_eeprom_get_board_rev(void)
{
- u32 rev = 0;
char str[5]; /* Legacy representation can contain at most 4 digits */
uint offset = BOARD_REV_OFFSET_LEGACY;
+ if (board_rev)
+ return board_rev;
+
if (cl_eeprom_setup_layout())
return 0;
if (cl_eeprom_layout != LAYOUT_LEGACY)
offset = BOARD_REV_OFFSET;
- if (cl_eeprom_read(offset, (uchar *)&rev, BOARD_REV_SIZE))
+ if (cl_eeprom_read(offset, (uchar *)&board_rev, BOARD_REV_SIZE))
return 0;
/*
* representation. i.e. for rev 1.00: 0x100 --> 0x64
*/
if (cl_eeprom_layout == LAYOUT_LEGACY) {
- sprintf(str, "%x", rev);
- rev = simple_strtoul(str, NULL, 10);
+ sprintf(str, "%x", board_rev);
+ board_rev = simple_strtoul(str, NULL, 10);
}
- return rev;
+ return board_rev;
};
--- /dev/null
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+
+#include "common.h"
+
+static u32 cl_omap3_smc911x_gpmc_net_config[GPMC_MAX_REG] = {
+ NET_GPMC_CONFIG1,
+ NET_GPMC_CONFIG2,
+ NET_GPMC_CONFIG3,
+ NET_GPMC_CONFIG4,
+ NET_GPMC_CONFIG5,
+ NET_GPMC_CONFIG6,
+ 0
+};
+
+static void cl_omap3_smc911x_setup_net_chip_gmpc(int cs, u32 base_addr)
+{
+ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+ enable_gpmc_cs_config(cl_omap3_smc911x_gpmc_net_config,
+ &gpmc_cfg->cs[cs], base_addr, GPMC_SIZE_16M);
+
+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+
+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+
+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+ &ctrl_base->gpmc_nadv_ale);
+}
+
+#ifdef CONFIG_OMAP_GPIO
+static int cl_omap3_smc911x_reset_net_chip(int gpio)
+{
+ int err;
+
+ if (!gpio_is_valid(gpio))
+ return -EINVAL;
+
+ err = gpio_request(gpio, "eth rst");
+ if (err)
+ return err;
+
+ /* Set gpio as output and send a pulse */
+ gpio_direction_output(gpio, 1);
+ udelay(1);
+ gpio_set_value(gpio, 0);
+ mdelay(40);
+ gpio_set_value(gpio, 1);
+ mdelay(1);
+
+ return 0;
+}
+#else /* !CONFIG_OMAP_GPIO */
+static inline int cl_omap3_smc911x_reset_net_chip(int gpio) { return 0; }
+#endif /* CONFIG_OMAP_GPIO */
+
+int cl_omap3_smc911x_init(int id, int cs, u32 base_addr,
+ int (*reset)(int), int rst_gpio)
+{
+ int ret;
+
+ cl_omap3_smc911x_setup_net_chip_gmpc(cs, base_addr);
+
+ if (reset)
+ reset(rst_gpio);
+ else
+ cl_omap3_smc911x_reset_net_chip(rst_gpio);
+
+ ret = smc911x_initialize(id, base_addr);
+ if (ret > 0)
+ return ret;
+
+ printf("Failed initializing SMC911x! ");
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <bmp_layout.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_NAND
+static int splash_load_from_nand(u32 bmp_load_addr, int nand_offset)
+{
+ struct bmp_header *bmp_hdr;
+ int res;
+ size_t bmp_size, bmp_header_size = sizeof(struct bmp_header);
+
+ if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp)
+ goto splash_address_too_high;
+
+ res = nand_read_skip_bad(&nand_info[nand_curr_device],
+ nand_offset, &bmp_header_size,
+ NULL, nand_info[nand_curr_device].size,
+ (u_char *)bmp_load_addr);
+ if (res < 0)
+ return res;
+
+ bmp_hdr = (struct bmp_header *)bmp_load_addr;
+ bmp_size = le32_to_cpu(bmp_hdr->file_size);
+
+ if (bmp_load_addr + bmp_size >= gd->start_addr_sp)
+ goto splash_address_too_high;
+
+ return nand_read_skip_bad(&nand_info[nand_curr_device],
+ nand_offset, &bmp_size,
+ NULL, nand_info[nand_curr_device].size,
+ (u_char *)bmp_load_addr);
+
+splash_address_too_high:
+ printf("Error: splashimage address too high. Data overwrites U-Boot "
+ "and/or placed beyond DRAM boundaries.\n");
+
+ return -1;
+}
+#else
+static inline int splash_load_from_nand(u32 bmp_load_addr, int nand_offset)
+{
+ return -1;
+}
+#endif /* CONFIG_CMD_NAND */
+
+int cl_splash_screen_prepare(int nand_offset)
+{
+ char *env_splashimage_value;
+ u32 bmp_load_addr;
+
+ env_splashimage_value = getenv("splashimage");
+ if (env_splashimage_value == NULL)
+ return -1;
+
+ bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16);
+ if (bmp_load_addr == 0) {
+ printf("Error: bad splashimage address specified\n");
+ return -1;
+ }
+
+ return splash_load_from_nand(bmp_load_addr, nand_offset);
+}
if TARGET_CGTQMX6EVAL
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "cgtqmx6eval"
if TARGET_XFI3
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "xfi3"
if TARGET_QONG
-config SYS_CPU
- default "arm1136"
-
config SYS_BOARD
default "qong"
if TARGET_DBAU1X00
-config SYS_CPU
- default "mips32"
-
config SYS_BOARD
default "dbau1x00"
config SYS_CONFIG_NAME
default "dbau1x00"
+menu "dbau1x00 board options"
+
+choice
+ prompt "Select au1x00 SoC type"
+
+config DBAU1100
+ bool "Select AU1100"
+
+config DBAU1500
+ bool "Select AU1500"
+
+config DBAU1550
+ bool "Select AU1550"
+
+endchoice
+
+endmenu
+
endif
if TARGET_M28EVK
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "m28evk"
if TARGET_M53EVK
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "m53evk"
if TARGET_ETHERNUT5
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "ethernut5"
+++ /dev/null
-if TARGET_MHPC
-
-config SYS_BOARD
- default "mhpc"
-
-config SYS_VENDOR
- default "eltec"
-
-config SYS_CONFIG_NAME
- default "MHPC"
-
-endif
+++ /dev/null
-MHPC BOARD
-M: Frank Gottschling <fgottschling@eltec.de>
-S: Maintained
-F: board/eltec/mhpc/
-F: include/configs/MHPC.h
-F: configs/MHPC_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = mhpc.o flash.o
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <linux/byteorder/swab.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Protection Flags:
- */
-#define FLAG_PROTECT_SET 0x01
-#define FLAG_PROTECT_CLEAR 0x02
-
-/* Board support for 1 or 2 flash devices */
-#undef FLASH_PORT_WIDTH32
-#define FLASH_PORT_WIDTH16
-
-#ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH ushort
-#define FLASH_PORT_WIDTHV vu_short
-#define SWAP(x) __swab16(x)
-#else
-#define FLASH_PORT_WIDTH ulong
-#define FLASH_PORT_WIDTHV vu_long
-#define SWAP(x) __swab32(x)
-#endif
-
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (FPW *addr, flash_info_t *info);
-static int write_data (flash_info_t *info, ulong dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size_b0;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
- size_b0 = flash_get_size((FPW *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
-
- /* Re-do sizing to get full correct info */
- size_b0 = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- /* monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE+monitor_flash_len-1,
- &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000);
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL: printf ("INTEL "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F640J5 :
- printf ("28F640J5 \n"); break;
- default: printf ("Unknown Chip Type=0x%lXh\n",
- info->flash_id & FLASH_TYPEMASK); break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (FPW *addr, flash_info_t *info)
-{
- FPW value;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x5555] = (FPW)0xAA00AA00;
- addr[0x2AAA] = (FPW)0x55005500;
- addr[0x5555] = (FPW)0x90009000;
-
- value = SWAP(addr[0]);
-
- switch (value) {
- case (FPW)INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- addr[0] = (FPW)0xFF00FF00; /* restore read mode */
- return (0); /* no or unknown flash */
- }
-
- value = SWAP(addr[1]); /* device ID no swap !*/
-
- switch (value) {
- case (FPW)INTEL_ID_28F640J5 :
- info->flash_id += FLASH_28F640J5 ;
- info->sector_count = 64;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- break;
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- addr[0] = (FPW)0xFF00FF00; /* restore read mode */
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong type, start, now, last;
- int rc = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- type = (info->flash_id & FLASH_VENDMASK);
- if ((type != FLASH_MAN_INTEL)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- start = get_timer (0);
- last = start;
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- FPWV *addr = (FPWV *)(info->start[sect]);
- FPW status;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- *addr = (FPW)0x50005000; /* clear status register */
- *addr = (FPW)0x20002000; /* erase setup */
- *addr = (FPW)0xD000D000; /* erase confirm */
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) {
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = (FPW)0xB000B000; /* suspend erase */
- *addr = (FPW)0xFF00FF00; /* reset to read mode */
- rc = 1;
- break;
- }
-
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- *addr = (FPW)0xFF00FF00; /* reset to read mode */
- printf (" done\n");
- }
- }
- return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp;
- FPW data;
- int i, l, rc, port_width;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return 4;
- }
-/* get lower word aligned address */
-#ifdef FLASH_PORT_WIDTH16
- wp = (addr & ~1);
- port_width = 2;
-#else
- wp = (addr & ~3);
- port_width = 4;
-#endif
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp)
- data = (data << 8) | (*(uchar *)cp);
-
- for (; i<port_width && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_data(info, wp, data)) != 0) {
- return (rc);
- }
- wp += port_width;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= port_width) {
- data = 0;
- for (i=0; i<port_width; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_data(info, wp, data)) != 0) {
- return (rc);
- }
- wp += port_width;
- cnt -= port_width;
- if ((wp & 0xfff) == 0)
- {
- printf("%08lX",wp);
- printf("\x1b[8D");
- }
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<port_width && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_data(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t *info, ulong dest, FPW data)
-{
- FPWV *addr = (FPWV *)dest;
- ulong status;
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- printf("not erased at %08lx (%x)\n",(ulong)addr,*addr);
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- *addr = (FPW)0x40004000; /* write setup */
- *addr = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer (0);
-
- while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = (FPW)0xFF00FF00; /* restore read mode */
- return (1);
- }
- }
-
- *addr = (FPW)0xFF00FF00; /* restore read mode */
-
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * ELTEC Elektronik AG
- * Frank Gottschling <fgottschling@eltec.de>
- *
- * Board specific routines for the miniHiPerCam
- *
- * - initialisation (eeprom)
- * - memory controller
- * - serial io initialisation
- * - ethernet io initialisation
- *
- * -----------------------------------------------------------------
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <cli.h>
-#include <linux/ctype.h>
-#include <commproc.h>
-#include "mpc8xx.h"
-#include <video_fb.h>
-
-extern void eeprom_init (void);
-extern int eeprom_read (unsigned dev_addr, unsigned offset,
- unsigned char *buffer, unsigned cnt);
-extern int eeprom_write (unsigned dev_addr, unsigned offset,
- unsigned char *buffer, unsigned cnt);
-
-/* globals */
-void *video_hw_init (void);
-void video_set_lut (unsigned int index, /* color number */
- unsigned char r, /* red */
- unsigned char g, /* green */
- unsigned char b /* blue */
- );
-
-GraphicDevice gdev;
-
-/* locals */
-static void video_circle (char *center, int radius, int color, int pitch);
-static void video_test_image (void);
-static void video_default_lut (unsigned int clut_type);
-
-/* revision info foer MHPC EEPROM offset 480 */
-typedef struct {
- char board[12]; /* 000 - Board Revision information */
- char sensor; /* 012 - Sensor Type information */
- char serial[8]; /* 013 - Board serial number */
- char etheraddr[6]; /* 021 - Ethernet node addresse */
- char revision[2]; /* 027 - Revision code */
- char option[3]; /* 029 - resevered for options */
-} revinfo;
-
-/* ------------------------------------------------------------------------- */
-
-static const unsigned int sdram_table[] = {
- /* read single beat cycle */
- 0xef0efc04, 0x0e2dac04, 0x01ba5c04, 0x1ff5fc00,
- 0xfffffc05, 0xeffafc34, 0x0ff0bc34, 0x1ff57c35,
-
- /* read burst cycle */
- 0xef0efc04, 0x0e3dac04, 0x10ff5c04, 0xf0fffc00,
- 0xf0fffc00, 0xf1fffc00, 0xfffffc00, 0xfffffc05,
- 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
- /* write single beat cycle */
- 0xef0efc04, 0x0e29ac00, 0x01b25c04, 0x1ff5fc05,
- 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
- /* write burst cycle */
- 0xef0ef804, 0x0e39a000, 0x10f75000, 0xf0fff440,
- 0xf0fffc40, 0xf1fffc04, 0xfffffc05, 0xfffffc04,
- 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
- /* periodic timer expired */
- 0xeffebc84, 0x1ffd7c04, 0xfffffc04, 0xfffffc84,
- 0xeffebc04, 0x1ffd7c04, 0xfffffc04, 0xfffffc05,
- 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
- /* exception */
- 0xfffffc04, 0xfffffc05, 0xfffffc04, 0xfffffc04
-};
-
-/* ------------------------------------------------------------------------- */
-
-int board_early_init_f (void)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- volatile cpm8xx_t *cp = &(im->im_cpm);
- volatile iop8xx_t *ip = (iop8xx_t *) & (im->im_ioport);
-
- /* reset the port A s.a. cpm-routines */
- ip->iop_padat = 0x0000;
- ip->iop_papar = 0x0000;
- ip->iop_padir = 0x0800;
- ip->iop_paodr = 0x0000;
-
- /* reset the port B for digital and LCD output */
- cp->cp_pbdat = 0x0300;
- cp->cp_pbpar = 0x5001;
- cp->cp_pbdir = 0x5301;
- cp->cp_pbodr = 0x0000;
-
- /* reset the port C configured for SMC1 serial port and aqc. control */
- ip->iop_pcdat = 0x0800;
- ip->iop_pcpar = 0x0000;
- ip->iop_pcdir = 0x0e30;
- ip->iop_pcso = 0x0000;
-
- /* Config port D for LCD output */
- ip->iop_pdpar = 0x1fff;
- ip->iop_pddir = 0x1fff;
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity
- */
-int checkboard (void)
-{
- puts ("Board: ELTEC miniHiperCam\n");
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_r (void)
-{
- revinfo mhpcRevInfo;
- char nid[32];
- char *mhpcSensorTypes[] = { "OMNIVISON OV7610/7620 color",
- "OMNIVISON OV7110 b&w", NULL
- };
- char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
- 0, 0, 0, 0, 10, 11, 12, 13, 14, 15
- };
- int i;
-
- /* check revision data */
- eeprom_read (CONFIG_SYS_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, 32);
-
- if (strncmp ((char *) &mhpcRevInfo.board[2], "MHPC", 4) != 0) {
- printf ("Enter revision number (0-9): %c ",
- mhpcRevInfo.revision[0]);
- if (0 != cli_readline(NULL)) {
- mhpcRevInfo.revision[0] =
- (char) toupper (console_buffer[0]);
- }
-
- printf ("Enter revision character (A-Z): %c ",
- mhpcRevInfo.revision[1]);
- if (1 == cli_readline(NULL)) {
- mhpcRevInfo.revision[1] =
- (char) toupper (console_buffer[0]);
- }
-
- printf ("Enter board name (V-XXXX-XXXX): %s ",
- (char *) &mhpcRevInfo.board);
- if (11 == cli_readline(NULL)) {
- for (i = 0; i < 11; i++) {
- mhpcRevInfo.board[i] =
- (char) toupper (console_buffer[i]);
- mhpcRevInfo.board[11] = '\0';
- }
- }
-
- printf ("Supported sensor types:\n");
- i = 0;
- do {
- printf ("\n \'%d\' : %s\n", i, mhpcSensorTypes[i]);
- } while (mhpcSensorTypes[++i] != NULL);
-
- do {
- printf ("\nEnter sensor number (0-255): %d ",
- (int) mhpcRevInfo.sensor);
- if (0 != cli_readline(NULL)) {
- mhpcRevInfo.sensor =
- (unsigned char)
- simple_strtoul (console_buffer, NULL,
- 10);
- }
- } while (mhpcRevInfo.sensor >= i);
-
- printf ("Enter serial number: %s ",
- (char *) &mhpcRevInfo.serial);
- if (6 == cli_readline(NULL)) {
- for (i = 0; i < 6; i++) {
- mhpcRevInfo.serial[i] = console_buffer[i];
- }
- mhpcRevInfo.serial[6] = '\0';
- }
-
- printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1], mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3], mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
- if (12 == cli_readline(NULL)) {
- for (i = 0; i < 12; i += 2) {
- mhpcRevInfo.etheraddr[i >> 1] =
- (char) (16 *
- hex[toupper
- (console_buffer[i]) -
- '0'] +
- hex[toupper
- (console_buffer[i + 1]) -
- '0']);
- }
- }
-
- /* setup new revision data */
- eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo,
- 32);
- }
-
- /* set environment */
- sprintf (nid, "%02x:%02x:%02x:%02x:%02x:%02x",
- mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1],
- mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3],
- mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
- setenv ("ethaddr", nid);
-
- /* print actual board identification */
- printf ("Ident: %s %s Ser %s Rev %c%c\n",
- mhpcRevInfo.board,
- (mhpcRevInfo.sensor == 0 ? "color" : "b&w"),
- (char *) &mhpcRevInfo.serial, mhpcRevInfo.revision[0],
- mhpcRevInfo.revision[1]);
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- upmconfig (UPMA, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
- memctl->memc_mbmr = MBMR_GPL_B4DIS; /* should this be mamr? - NTL */
- memctl->memc_mptpr = MPTPR_PTP_DIV64;
- memctl->memc_mar = 0x00008800;
-
- /*
- * Map controller SDRAM bank 0
- */
- memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
- memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
- udelay (200);
-
- /*
- * Map controller SDRAM bank 1
- */
- memctl->memc_or2 = CONFIG_SYS_OR2;
- memctl->memc_br2 = CONFIG_SYS_BR2;
-
- /*
- * Perform SDRAM initializsation sequence
- */
- memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
- udelay (1);
- memctl->memc_mcr = 0x80002730; /* SDRAM bank 0 - execute twice */
- udelay (1);
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
-
- udelay (10000);
-
- /* leave place for framebuffers */
- return (SDRAM_MAX_SIZE - SDRAM_RES_SIZE);
-}
-
-/* ------------------------------------------------------------------------- */
-
-static void video_circle (char *center, int radius, int color, int pitch)
-{
- int x, y, d, dE, dSE;
-
- x = 0;
- y = radius;
- d = 1 - radius;
- dE = 3;
- dSE = -2 * radius + 5;
-
- *(center + x + y * pitch) = color;
- *(center + y + x * pitch) = color;
- *(center + y - x * pitch) = color;
- *(center + x - y * pitch) = color;
- *(center - x - y * pitch) = color;
- *(center - y - x * pitch) = color;
- *(center - y + x * pitch) = color;
- *(center - x + y * pitch) = color;
- while (y > x) {
- if (d < 0) {
- d += dE;
- dE += 2;
- dSE += 2;
- x++;
- } else {
- d += dSE;
- dE += 2;
- dSE += 4;
- x++;
- y--;
- }
- *(center + x + y * pitch) = color;
- *(center + y + x * pitch) = color;
- *(center + y - x * pitch) = color;
- *(center + x - y * pitch) = color;
- *(center - x - y * pitch) = color;
- *(center - y - x * pitch) = color;
- *(center - y + x * pitch) = color;
- *(center - x + y * pitch) = color;
- }
-}
-
-/* ------------------------------------------------------------------------- */
-
-static void video_test_image (void)
-{
- char *di;
- int i, n;
-
- /* draw raster */
- for (i = 0; i < LCD_VIDEO_ROWS; i += 32) {
- memset ((char *) (LCD_VIDEO_ADDR + i * LCD_VIDEO_COLS),
- LCD_VIDEO_FG, LCD_VIDEO_COLS);
- for (n = i + 1; n < i + 32; n++)
- memset ((char *) (LCD_VIDEO_ADDR +
- n * LCD_VIDEO_COLS), LCD_VIDEO_BG,
- LCD_VIDEO_COLS);
- }
-
- for (i = 0; i < LCD_VIDEO_COLS; i += 32) {
- for (n = 0; n < LCD_VIDEO_ROWS; n++)
- *(char *) (LCD_VIDEO_ADDR + n * LCD_VIDEO_COLS + i) =
- LCD_VIDEO_FG;
- }
-
- /* draw gray bar */
- di = (char *) (LCD_VIDEO_ADDR + (LCD_VIDEO_COLS - 256) / 64 * 32 +
- 97 * LCD_VIDEO_COLS);
- for (n = 0; n < 63; n++) {
- for (i = 0; i < 256; i++) {
- *di++ = (char) i;
- *(di + LCD_VIDEO_COLS * 64) = (i & 1) * 255;
- }
- di += LCD_VIDEO_COLS - 256;
- }
-
- video_circle ((char *) LCD_VIDEO_ADDR + LCD_VIDEO_COLS / 2 +
- LCD_VIDEO_ROWS / 2 * LCD_VIDEO_COLS, LCD_VIDEO_ROWS / 2,
- LCD_VIDEO_FG, LCD_VIDEO_COLS);
-}
-
-/* ------------------------------------------------------------------------- */
-
-static void video_default_lut (unsigned int clut_type)
-{
- unsigned int i;
- unsigned char RGB[] = {
- 0x00, 0x00, 0x00, /* black */
- 0x80, 0x80, 0x80, /* gray */
- 0xff, 0x00, 0x00, /* red */
- 0x00, 0xff, 0x00, /* green */
- 0x00, 0x00, 0xff, /* blue */
- 0x00, 0xff, 0xff, /* cyan */
- 0xff, 0x00, 0xff, /* magenta */
- 0xff, 0xff, 0x00, /* yellow */
- 0x80, 0x00, 0x00, /* dark red */
- 0x00, 0x80, 0x00, /* dark green */
- 0x00, 0x00, 0x80, /* dark blue */
- 0x00, 0x80, 0x80, /* dark cyan */
- 0x80, 0x00, 0x80, /* dark magenta */
- 0x80, 0x80, 0x00, /* dark yellow */
- 0xc0, 0xc0, 0xc0, /* light gray */
- 0xff, 0xff, 0xff, /* white */
- };
-
- switch (clut_type) {
- case 1:
- for (i = 0; i < 240; i++)
- video_set_lut (i, i, i, i);
- for (i = 0; i < 16; i++)
- video_set_lut (i + 240, RGB[i * 3], RGB[i * 3 + 1],
- RGB[i * 3 + 2]);
- break;
- default:
- for (i = 0; i < 256; i++)
- video_set_lut (i, i, i, i);
- }
-}
-
-/* ------------------------------------------------------------------------- */
-
-void *video_hw_init (void)
-{
- unsigned int clut = 0;
- unsigned char *penv;
- immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-
- /* enable video only on CLUT value */
- if ((penv = (uchar *)getenv ("clut")) != NULL)
- clut = (u_int) simple_strtoul ((char *)penv, NULL, 10);
- else
- return NULL;
-
- /* disable graphic before write LCD regs. */
- immr->im_lcd.lcd_lccr = 0x96000866;
-
- /* config LCD regs. */
- immr->im_lcd.lcd_lcfaa = LCD_VIDEO_ADDR;
- immr->im_lcd.lcd_lchcr = 0x010a0093;
- immr->im_lcd.lcd_lcvcr = 0x900f0024;
-
- printf ("Video: 640x480 8Bit Index Lut %s\n",
- (clut == 1 ? "240/16 (gray/vga)" : "256(gray)"));
-
- video_default_lut (clut);
-
- /* clear framebuffer */
- memset ((char *) (LCD_VIDEO_ADDR), LCD_VIDEO_BG,
- LCD_VIDEO_ROWS * LCD_VIDEO_COLS);
-
- /* enable graphic */
- immr->im_lcd.lcd_lccr = 0x96000867;
-
- /* fill in Graphic Device */
- gdev.frameAdrs = LCD_VIDEO_ADDR;
- gdev.winSizeX = LCD_VIDEO_COLS;
- gdev.winSizeY = LCD_VIDEO_ROWS;
- gdev.gdfBytesPP = 1;
- gdev.gdfIndex = GDF__8BIT_INDEX;
-
- if (clut > 1)
- /* return Graphic Device for console */
- return (void *) &gdev;
- else
- /* just graphic enabled - draw something beautiful */
- video_test_image ();
-
- return NULL; /* this disabels cfb - console */
-}
-
-/* ------------------------------------------------------------------------- */
-
-void video_set_lut (unsigned int index,
- unsigned char r, unsigned char g, unsigned char b)
-{
- unsigned int lum;
- unsigned short *pLut = (unsigned short *) (CONFIG_SYS_IMMR + 0x0e00);
-
- /* 16 bit lut values, 12 bit used, xxxx BBGG RRii iiii */
- /* y = 0.299*R + 0.587*G + 0.114*B */
- lum = (2990 * r + 5870 * g + 1140 * b) / 10000;
- pLut[index] =
- ((b & 0xc0) << 4) | ((g & 0xc0) << 2) | (r & 0xc0) | (lum &
- 0x3f);
-}
-
-/* ------------------------------------------------------------------------- */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
if TARGET_EMBESTMX6BOARDS
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "mx6boards"
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/spi.h>
#include <asm/imx-common/video.h>
#include <i2c.h>
#include <mmc.h>
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-/*****************************************************************************
- * check fiber optic link present, and then copper link present. do auto switch
- * between both
- *****************************************************************************/
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2003
- * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined (CONFIG_TOP860)
- typedef unsigned short FLASH_PORT_WIDTH;
- typedef volatile unsigned short FLASH_PORT_WIDTHV;
- #define FLASH_ID_MASK 0xFF
-
- #define FPW FLASH_PORT_WIDTH
- #define FPWV FLASH_PORT_WIDTHV
-
- #define FLASH_CYCLE1 0x0555
- #define FLASH_CYCLE2 0x02aa
- #define FLASH_ID1 0
- #define FLASH_ID2 1
- #define FLASH_ID3 0x0e
- #define FLASH_ID4 0x0F
-#endif
-
-#if defined (CONFIG_TOP5200) && !defined (CONFIG_LITE5200)
- typedef unsigned char FLASH_PORT_WIDTH;
- typedef volatile unsigned char FLASH_PORT_WIDTHV;
- #define FLASH_ID_MASK 0xFF
-
- #define FPW FLASH_PORT_WIDTH
- #define FPWV FLASH_PORT_WIDTHV
-
- #define FLASH_CYCLE1 0x0aaa
- #define FLASH_CYCLE2 0x0555
- #define FLASH_ID1 0
- #define FLASH_ID2 2
- #define FLASH_ID3 0x1c
- #define FLASH_ID4 0x1E
-#endif
-
-#if defined (CONFIG_TOP5200) && defined (CONFIG_LITE5200)
- typedef unsigned char FLASH_PORT_WIDTH;
- typedef volatile unsigned char FLASH_PORT_WIDTHV;
- #define FLASH_ID_MASK 0xFF
-
- #define FPW FLASH_PORT_WIDTH
- #define FPWV FLASH_PORT_WIDTHV
-
- #define FLASH_CYCLE1 0x0555
- #define FLASH_CYCLE2 0x02aa
- #define FLASH_ID1 0
- #define FLASH_ID2 1
- #define FLASH_ID3 0x0E
- #define FLASH_ID4 0x0F
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(FPWV *addr, flash_info_t *info);
-static void flash_reset(flash_info_t *info);
-static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
-flash_info_t *flash_get_info(ulong base);
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init (void)
-{
- unsigned long size = 0;
- int i = 0;
- extern void flash_preinit(void);
- extern void flash_afterinit(uint, ulong, ulong);
- ulong flashbase = CONFIG_SYS_FLASH_BASE;
-
- flash_preinit();
-
- /* There is only ONE FLASH device */
- memset(&flash_info[i], 0, sizeof(flash_info_t));
- flash_info[i].size =
- flash_get_size((FPW *)flashbase, &flash_info[i]);
- size += flash_info[i].size;
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- flash_get_info(CONFIG_SYS_MONITOR_BASE));
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
- flash_get_info(CONFIG_ENV_ADDR));
-#endif
-
-
- flash_afterinit(i, flash_info[i].start[0], flash_info[i].size);
- return size ? size : 1;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_reset(flash_info_t *info)
-{
- FPWV *base = (FPWV *)(info->start[0]);
-
- /* Put FLASH back in read mode */
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
- *base = (FPW)0x00FF00FF; /* Intel Read Mode */
- else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
- *base = (FPW)0x00F000F0; /* AMD Read Mode */
-}
-
-/*-----------------------------------------------------------------------
- */
-
-flash_info_t *flash_get_info(ulong base)
-{
- int i;
- flash_info_t * info;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
- info = & flash_info[i];
- if (info->size &&
- info->start[0] <= base && base <= info->start[0] + info->size - 1)
- break;
- }
-
- return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-void flash_print_info (flash_info_t *info)
-{
- int i;
- uchar *boottype;
- uchar *bootletter;
- char *fmt;
- uchar botbootletter[] = "B";
- uchar topbootletter[] = "T";
- uchar botboottype[] = "bottom boot sector";
- uchar topboottype[] = "top boot sector";
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
-#if 0
- case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- case FLASH_MAN_STM: printf ("STM "); break;
- case FLASH_MAN_INTEL: printf ("INTEL "); break;
-#endif
- default: printf ("Unknown Vendor "); break;
- }
-
- /* check for top or bottom boot, if it applies */
- if (info->flash_id & FLASH_BTYPE) {
- boottype = botboottype;
- bootletter = botbootletter;
- }
- else {
- boottype = topboottype;
- bootletter = topbootletter;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM160T:
- case FLASH_AM160B:
- fmt = "29LV160%s (16 Mbit, %s)\n";
- break;
- case FLASH_AMLV640U:
- fmt = "29LV640M (64 Mbit)\n";
- break;
- case FLASH_AMDLV065D:
- fmt = "29LV065D (64 Mbit)\n";
- break;
- case FLASH_AMLV256U:
- fmt = "29LV256M (256 Mbit)\n";
- break;
- default:
- fmt = "Unknown Chip Type\n";
- break;
- }
-
- printf (fmt, bootletter, boottype);
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20,
- info->sector_count);
-
- printf (" Sector Start Addresses:");
-
- for (i=0; i<info->sector_count; ++i) {
- ulong size;
- int erased;
- ulong *flash = (unsigned long *) info->start[i];
-
- if ((i % 5) == 0) {
- printf ("\n ");
- }
-
- /*
- * Check if whole sector is erased
- */
- size =
- (i != (info->sector_count - 1)) ?
- (info->start[i + 1] - info->start[i]) >> 2 :
- (info->start[0] + info->size - info->start[i]) >> 2;
-
- for (
- flash = (unsigned long *) info->start[i], erased = 1;
- (flash != (unsigned long *) info->start[i] + size) && erased;
- flash++
- )
- erased = *flash == ~0x0UL;
-
- printf (" %08lX %s %s",
- info->start[i],
- erased ? "E": " ",
- info->protect[i] ? "(RO)" : " ");
- }
-
- printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-ulong flash_get_size (FPWV *addr, flash_info_t *info)
-{
- int i;
-
- /* Write auto select command: read Manufacturer ID */
- /* Write auto select command sequence and test FLASH answer */
- addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
- addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
- addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
-
- /* The manufacturer codes are only 1 byte, so just use 1 byte.
- * This works for any bus width and any FLASH device width.
- */
- udelay(100);
- switch (addr[FLASH_ID1] & 0xff) {
-
- case (uchar)AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
-
-#if 0
- case (uchar)INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
-#endif
-
- default:
- printf ("unknown vendor=%x ", addr[FLASH_ID1] & 0xff);
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- break;
- }
-
- /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
- if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[FLASH_ID2]) {
-
- case (FPW)AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000;
- info->start[0] = (ulong)addr;
- info->start[1] = (ulong)addr + 0x4000;
- info->start[2] = (ulong)addr + 0x6000;
- info->start[3] = (ulong)addr + 0x8000;
- for (i = 4; i < info->sector_count; i++)
- {
- info->start[i] = (ulong)addr + 0x10000 * (i-3);
- }
- break;
-
- case (FPW)AMD_ID_LV065D:
- info->flash_id += FLASH_AMDLV065D;
- info->sector_count = 128;
- info->size = 0x00800000;
- for (i = 0; i < info->sector_count; i++)
- {
- info->start[i] = (ulong)addr + 0x10000 * i;
- }
- break;
-
- case (FPW)AMD_ID_MIRROR:
- /* MIRROR BIT FLASH, read more ID bytes */
- if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV640U_2 &&
- (FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV640U_3)
- {
- info->flash_id += FLASH_AMLV640U;
- info->sector_count = 128;
- info->size = 0x00800000;
- for (i = 0; i < info->sector_count; i++)
- {
- info->start[i] = (ulong)addr + 0x10000 * i;
- }
- break;
- }
- if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV256U_2 &&
- (FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV256U_3)
- {
- /* attention: only the first 16 MB will be used in u-boot */
- info->flash_id += FLASH_AMLV256U;
- info->sector_count = 256;
- info->size = 0x01000000;
- for (i = 0; i < info->sector_count; i++)
- {
- info->start[i] = (ulong)addr + 0x10000 * i;
- }
- break;
- }
-
- /* fall thru to here ! */
- default:
- printf ("unknown AMD device=%x %x %x",
- (FPW)addr[FLASH_ID2],
- (FPW)addr[FLASH_ID3],
- (FPW)addr[FLASH_ID4]);
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0x800000;
- break;
- }
-
- /* Put FLASH back in read mode */
- flash_reset(info);
-
- return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- FPWV *addr;
- int flag, prot, sect;
- int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
- ulong start, now, last;
- int rcode = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM160B:
- case FLASH_AMLV640U:
- break;
- case FLASH_UNKNOWN:
- default:
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- last = get_timer(0);
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
-
- if (info->protect[sect] != 0) /* protected, skip it */
- continue;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr = (FPWV *)(info->start[sect]);
- if (intel) {
- *addr = (FPW)0x00500050; /* clear status register */
- *addr = (FPW)0x00200020; /* erase setup */
- *addr = (FPW)0x00D000D0; /* erase confirm */
- }
- else {
- /* must be AMD style if not Intel */
- FPWV *base; /* first address in bank */
-
- base = (FPWV *)(info->start[0]);
- base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
- base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */
- base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
- *addr = (FPW)0x00300030; /* erase sector */
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer(0);
-
- /* wait at least 50us for AMD, 80us for Intel.
- * Let's wait 1 ms.
- */
- udelay (1000);
-
- while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
-
- if (intel) {
- /* suspend erase */
- *addr = (FPW)0x00B000B0;
- }
-
- flash_reset(info); /* reset to read mode */
- rcode = 1; /* failed */
- break;
- }
-
- /* show that we're waiting */
- if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
- putc ('.');
- last = get_timer(0);
- }
- }
-
- /* show that we're waiting */
- if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */
- putc ('.');
- last = get_timer(0);
- }
-
- flash_reset(info); /* reset to read mode */
- }
-
- printf (" done\n");
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
- int bytes; /* number of bytes to program in current word */
- int left; /* number of bytes left to program */
- int i, res;
-
- for (left = cnt, res = 0;
- left > 0 && res == 0;
- addr += sizeof(data), left -= sizeof(data) - bytes) {
-
- bytes = addr & (sizeof(data) - 1);
- addr &= ~(sizeof(data) - 1);
-
- /* combine source and destination data so can program
- * an entire word of 16 or 32 bits
- */
- for (i = 0; i < sizeof(data); i++) {
- data <<= 8;
- if (i < bytes || i - bytes >= left )
- data += *((uchar *)addr + i);
- else
- data += *src++;
- }
-
- /* write one word to the flash */
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- res = write_word_amd(info, (FPWV *)addr, data);
- break;
- default:
- /* unknown flash type, error! */
- printf ("missing or unknown FLASH type\n");
- res = 1; /* not really a timeout, but gives error */
- break;
- }
- }
-
- return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash for AMD FLASH
- * A word is 16 or 32 bits, whichever the bus width of the flash bank
- * (not an individual chip) is.
- *
- * returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
-{
- ulong start;
- int flag;
- int res = 0; /* result, assume success */
- FPWV *base; /* first address in flash bank */
-
- /* Check if Flash is (sufficiently) erased */
- if ((*dest & data) != data) {
- return (2);
- }
-
-
- base = (FPWV *)(info->start[0]);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
- base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
-
- *dest = data; /* start programming the data */
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer (0);
-
- /* data polling for D7 */
- while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *dest = (FPW)0x00F000F0; /* reset bank */
- res = 1;
- }
- }
-
- return (res);
-}
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-/*****************************************************************************
- * read "factory" part of EEPROM and set some environment variables
- *****************************************************************************/
-void read_factory_r (void)
-{
- /* read 'factory' part of EEPROM */
- uchar buf[81];
- uchar *p;
- uint length;
- uint addr;
- uint len;
-
- /* get length first */
- addr = CONFIG_SYS_FACT_OFFSET;
- if (eeprom_read (CONFIG_SYS_I2C_FACT_ADDR, addr, buf, 2)) {
- bailout:
- printf ("cannot read factory configuration\n");
- printf ("be sure to set ethaddr yourself!\n");
- return;
- }
- length = buf[0] + (buf[1] << 8);
- addr += 2;
-
- /* sanity check */
- if (length < 20 || length > CONFIG_SYS_FACT_SIZE - 2)
- goto bailout;
-
- /* read lines */
- while (length > 0) {
- /* read one line */
- len = length > 80 ? 80 : length;
- if (eeprom_read (CONFIG_SYS_I2C_FACT_ADDR, addr, buf, len))
- goto bailout;
- /* mark end of buffer */
- buf[len] = 0;
- /* search end of line */
- for (p = buf; *p && *p != 0x0a; p++);
- if (!*p)
- goto bailout;
- *p++ = 0;
- /* advance to next line start */
- length -= p - buf;
- addr += p - buf;
- /*printf ("%s\n", buf); */
- /* search for our specific entry */
- if (!strncmp ((char *) buf, "[RLA/lan/Ethernet] ", 19)) {
- setenv ("ethaddr", (char *)(buf + 19));
- } else if (!strncmp ((char *) buf, "[BOARD/SERIAL] ", 15)) {
- setenv ("serial#", (char *)(buf + 15));
- } else if (!strncmp ((char *) buf, "[BOARD/TYPE] ", 13)) {
- setenv ("board_id", (char *)(buf + 13));
- }
- }
-}
+++ /dev/null
-if TARGET_TOP5200
-
-config SYS_BOARD
- default "top5200"
-
-config SYS_VENDOR
- default "emk"
-
-config SYS_CONFIG_NAME
- default "TOP5200"
-
-endif
+++ /dev/null
-TOP5200 BOARD
-M: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
-S: Maintained
-F: board/emk/top5200/
-F: include/configs/TOP5200.h
-F: configs/EVAL5200_defconfig
-F: configs/MINI5200_defconfig
-F: configs/TOP5200_defconfig
+++ /dev/null
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := top5200.o ../common/flash.o ../common/vpd.o ../common/am79c874.o
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2003
- * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-
-/*****************************************************************************
- * initialize SDRAM/DDRAM controller.
- * TBD: get data from I2C EEPROM
- *****************************************************************************/
-phys_size_t initdram (int board_type)
-{
- ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-#if 0
- ulong t;
- ulong tap_del;
-#endif
-
- #define MODE_EN 0x80000000
- #define SOFT_PRE 2
- #define SOFT_REF 4
-
- /* configure SDRAM start/end */
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | CONFIG_SYS_DRAM_RAM_SIZE;
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
-
- /* setup config registers */
- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CONFIG_SYS_DRAM_CONFIG1;
- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CONFIG_SYS_DRAM_CONFIG2;
-
- /* unlock mode register */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN;
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_PRE;
-#ifdef CONFIG_SYS_DRAM_DDR
- /* set extended mode register */
- *(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_EMODE;
-#endif
- /* set mode register */
- *(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE | 0x0400;
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_PRE;
- /* auto refresh */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_REF;
- /* set mode register */
- *(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE;
- /* normal operation */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL;
- /* write default TAP delay */
- *(vu_long *)MPC5XXX_CDM_PORCFG = CONFIG_SYS_DRAM_TAP_DEL << 24;
-
-#if 0
- for (tap_del = 0; tap_del < 32; tap_del++)
- {
- *(vu_long *)MPC5XXX_CDM_PORCFG = tap_del << 24;
-
- printf ("\nTAP Delay:%x Filling DRAM...", *(vu_long *)MPC5XXX_CDM_PORCFG);
- for (t = 0; t < 0x04000000; t+=4)
- *(vu_long *) t = t;
- printf ("Checking DRAM...\n");
- for (t = 0; t < 0x04000000; t+=4)
- {
- ulong rval = *(vu_long *) t;
- if (rval != t)
- {
- printf ("mismatch at %x: ", t);
- printf (" 1.read %x", rval);
- printf (" 2.read %x", *(vu_long *) t);
- printf (" 3.read %x", *(vu_long *) t);
- break;
- }
- }
- }
-#endif
-#endif /* CONFIG_SYS_RAMBOOT */
-
- dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
-
- /* return total ram size */
- return dramsize;
-}
-
-/*****************************************************************************
- * print board identification
- *****************************************************************************/
-int checkboard (void)
-{
-#if defined (CONFIG_EVAL5200)
- puts ("Board: EMK TOP5200 on EVAL5200\n");
-#else
-#if defined (CONFIG_LITE5200)
- puts ("Board: LITE5200\n");
-#else
-#if defined (CONFIG_MINI5200)
- puts ("Board: EMK TOP5200 on MINI5200\n");
-#else
- puts ("Board: EMK TOP5200\n");
-#endif
-#endif
-#endif
- return 0;
-}
-
-/*****************************************************************************
- * prepare for FLASH detection
- *****************************************************************************/
-void flash_preinit(void)
-{
- /*
- * Now, when we are in RAM, enable flash write
- * access for detection process.
- * Note that CS_BOOT cannot be cleared when
- * executing in flash.
- */
- *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-}
-
-/*****************************************************************************
- * finalize FLASH setup
- *****************************************************************************/
-void flash_afterinit(uint bank, ulong start, ulong size)
-{
- if (bank == 0) { /* adjust mapping */
- *(vu_long *)MPC5XXX_BOOTCS_START =
- *(vu_long *)MPC5XXX_CS0_START = START_REG(start);
- *(vu_long *)MPC5XXX_BOOTCS_STOP =
- *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(start, size);
- }
-}
-
-/*****************************************************************************
- * otherinits after RAM is there and we are relocated to RAM
- * note: though this is an int function, nobody cares for the result!
- *****************************************************************************/
-int misc_init_r (void)
-{
-#if !defined (CONFIG_LITE5200)
- /* read 'factory' part of EEPROM */
- extern void read_factory_r (void);
- read_factory_r ();
-#endif
- return (0);
-}
-
-/*****************************************************************************
- * initialize the PCI system
- *****************************************************************************/
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc5xxx_init(&hose);
-}
-#endif
-
-/*****************************************************************************
- * provide the IDE Reset Function
- *****************************************************************************/
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-
-void init_ide_reset (void)
-{
- debug ("init_ide_reset\n");
-
- /* Configure PSC1_4 as GPIO output for ATA reset */
- *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
- *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
-}
-
-void ide_set_reset (int idereset)
-{
- debug ("ide_reset(%d)\n", idereset);
-
- if (idereset) {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
- } else {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
- }
-}
-#endif
+++ /dev/null
-if TARGET_TOP860
-
-config SYS_BOARD
- default "top860"
-
-config SYS_VENDOR
- default "emk"
-
-config SYS_CONFIG_NAME
- default "TOP860"
-
-endif
+++ /dev/null
-TOP860 BOARD
-M: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
-S: Maintained
-F: board/emk/top860/
-F: include/configs/TOP860.h
-F: configs/TOP860_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = top860.o ../common/flash.o ../common/vpd.o ../common/am79c874.o
+++ /dev/null
-/*
- * (C) Copyright 2003
- * EMK Elektronik GmbH <www.emk-elektronik.de>
- * Reinhard Meyer <r.meyer@emk-elektronik.de>
- *
- * Board specific routines for the TOP860
- *
- * - initialisation
- * - interface to VPD data (mac address, clock speeds)
- * - memory controller
- * - serial io initialisation
- * - ethernet io initialisation
- *
- * -----------------------------------------------------------------
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <commproc.h>
-#include <mpc8xx.h>
-#include <asm/io.h>
-
-/*****************************************************************************
- * UPM table for 60ns EDO RAM at 25 MHz bus/external clock
- *****************************************************************************/
-static const uint edo_60ns_25MHz_tbl[] = {
-
-/* single read (offset 0x00 in upm ram) */
- 0x0ff3fc04,0x08f3fc04,0x00f3fc04,0x00f3fc00,
- 0x33f7fc07,0xfffffc05,0xfffffc05,0xfffffc05,
-/* burst read (offset 0x08 in upm ram) */
- 0x0ff3fc04,0x08f3fc04,0x00f3fc0c,0x0ff3fc40,
- 0x0cf3fc04,0x03f3fc48,0x0cf3fc04,0x03f3fc48,
- 0x0cf3fc04,0x03f3fc00,0x3ff7fc07,0xfffffc05,
- 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
-/* single write (offset 0x18 in upm ram) */
- 0x0ffffc04,0x08fffc04,0x30fffc00,0xf1fffc07,
- 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
-/* burst write (offset 0x20 in upm ram) */
- 0x0ffffc04,0x08fffc00,0x00fffc04,0x03fffc4c,
- 0x00fffc00,0x07fffc4c,0x00fffc00,0x0ffffc4c,
- 0x00fffc00,0x3ffffc07,0xfffffc05,0xfffffc05,
- 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
-/* refresh (offset 0x30 in upm ram) */
- 0xc0fffc04,0x07fffc04,0x0ffffc04,0x0ffffc04,
- 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
- 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
-/* exception (offset 0x3C in upm ram) */
- 0xfffffc07,0xfffffc03,0xfffffc05,0xfffffc05,
-};
-
-/*****************************************************************************
- * Print Board Identity
- *****************************************************************************/
-int checkboard (void)
-{
- puts ("Board:"CONFIG_IDENT_STRING"\n");
- return (0);
-}
-
-/*****************************************************************************
- * Initialize DRAM controller
- *****************************************************************************/
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- /*
- * Only initialize memory controller when running from FLASH.
- * When running from RAM, don't touch it.
- */
- if ((ulong) initdram & 0xff000000) {
- volatile uint *addr1, *addr2;
- uint i;
-
- upmconfig (UPMA, (uint *) edo_60ns_25MHz_tbl,
- sizeof (edo_60ns_25MHz_tbl) / sizeof (uint));
- memctl->memc_mptpr = 0x0200;
- memctl->memc_mamr = 0x0ca20330;
- memctl->memc_or2 = -CONFIG_SYS_DRAM_MAX | OR_CSNT_SAM;
- memctl->memc_br2 = CONFIG_SYS_DRAM_BASE | BR_MS_UPMA | BR_V;
- /*
- * Do 8 read accesses to DRAM
- */
- addr1 = (volatile uint *) 0;
- addr2 = (volatile uint *) 0x00400000;
- for (i = 0; i < 8; i++)
- in_be32(addr1);
-
- /*
- * Now check whether we got 4MB or 16MB populated
- */
- addr1[0] = 0x12345678;
- addr1[1] = 0x9abcdef0;
- addr2[0] = 0xfeedc0de;
- addr2[1] = 0x47110815;
- if (addr1[0] == 0xfeedc0de && addr1[1] == 0x47110815) {
- /* only 4MB populated */
- memctl->memc_or2 = -(CONFIG_SYS_DRAM_MAX / 4) | OR_CSNT_SAM;
- }
- }
-
- return -(memctl->memc_or2 & 0xffff0000);
-}
-
-/*****************************************************************************
- * prepare for FLASH detection
- *****************************************************************************/
-void flash_preinit(void)
-{
-}
-
-/*****************************************************************************
- * finalize FLASH setup
- *****************************************************************************/
-void flash_afterinit(uint bank, ulong start, ulong size)
-{
-}
-
-/*****************************************************************************
- * otherinits after RAM is there and we are relocated to RAM
- * note: though this is an int function, nobody cares for the result!
- *****************************************************************************/
-int misc_init_r (void)
-{
- /* read 'factory' part of EEPROM */
- extern void read_factory_r (void);
- read_factory_r ();
-
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-if TARGET_TOP9000
-
-config SYS_CPU
- default "arm926ejs"
-
-config SYS_BOARD
- default "top9000"
-
-config SYS_VENDOR
- default "emk"
-
-config SYS_SOC
- default "at91"
-
-config SYS_CONFIG_NAME
- default "top9000"
-
-endif
+++ /dev/null
-TOP9000 BOARD
-M: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
-S: Maintained
-F: board/emk/top9000/
-F: include/configs/top9000.h
-F: configs/top9000eval_xe_defconfig
-F: configs/top9000su_xe_defconfig
+++ /dev/null
-#
-# (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2010
-# Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += top9000.o
-obj-$(CONFIG_ATMEL_SPI) += spi.o
+++ /dev/null
-/*
- * Copyright (C) 2010
- * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_spi.h>
-#include <asm/arch/gpio.h>
-#include <spi.h>
-
-static const struct {
- u32 port;
- u32 bit;
-} cs_to_portbit[2][4] = {
- {{AT91_PIO_PORTA, 3}, {AT91_PIO_PORTC, 11},
- {AT91_PIO_PORTC, 16}, {AT91_PIO_PORTC, 17} },
- {{AT91_PIO_PORTB, 3}, {AT91_PIO_PORTC, 5},
- {AT91_PIO_PORTC, 4}, {AT91_PIO_PORTC, 3} }
-};
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- debug("spi_cs_is_valid: bus=%u cs=%u\n", bus, cs);
- if (bus < 2 && cs < 4)
- return 1;
- return 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- debug("spi_cs_activate: bus=%u cs=%u\n", slave->bus, slave->cs);
- at91_set_pio_output(cs_to_portbit[slave->bus][slave->cs].port,
- cs_to_portbit[slave->bus][slave->cs].bit, 0);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- debug("spi_cs_deactivate: bus=%u cs=%u\n", slave->bus, slave->cs);
- at91_set_pio_output(cs_to_portbit[slave->bus][slave->cs].port,
- cs_to_portbit[slave->bus][slave->cs].bit, 1);
-}
+++ /dev/null
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2010
- * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-#include <mmc.h>
-#include <atmel_mci.h>
-#include <i2c.h>
-#include <spi.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91sam9260_matrix.h>
-#include <asm/arch/at91sam9_smc.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
-#include <asm/arch/at91_shdwn.h>
-#include <asm/arch/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_CMD_NAND
-static void nand_hw_init(void)
-{
- struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
- struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
- unsigned long csa;
-
- /* Assign CS3 to NAND/SmartMedia Interface */
- csa = readl(&matrix->ebicsa);
- csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
- writel(csa, &matrix->ebicsa);
-
- /* Configure SMC CS3 for NAND/SmartMedia */
- writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
- AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
- &smc->cs[3].setup);
- writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
- AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
- &smc->cs[3].pulse);
- writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
- &smc->cs[3].cycle);
- writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
- AT91_SMC_MODE_EXNW_DISABLE |
- AT91_SMC_MODE_DBW_8 |
- AT91_SMC_MODE_TDF_CYCLE(2),
- &smc->cs[3].mode);
-
- /* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
-
- /* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
-}
-#endif
-
-#ifdef CONFIG_MACB
-static void macb_hw_init(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- /* Enable EMAC clock */
- writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
-
- /* Initialize EMAC=MACB hardware */
- at91_macb_hw_init();
-}
-#endif
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-/* this is a weak define that we are overriding */
-int board_mmc_init(bd_t *bd)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- /* Enable MCI clock */
- writel(1 << ATMEL_ID_MCI, &pmc->pcer);
-
- /* Initialize MCI hardware */
- at91_mci_hw_init();
-
- /* This calls the atmel_mmc_init in gen_atmel_mci.c */
- return atmel_mci_init((void *)ATMEL_BASE_MCI);
-}
-
-/* this is a weak define that we are overriding */
-int board_mmc_getcd(struct mmc *mmc)
-{
- return !at91_get_gpio_value(CONFIG_SYS_MMC_CD_PIN);
-}
-
-#endif
-
-int board_early_init_f(void)
-{
- struct at91_shdwn *shdwn = (struct at91_shdwn *)ATMEL_BASE_SHDWN;
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- /*
- * make sure the board can be powered on by
- * any transition on WKUP
- */
- writel(AT91_SHDW_MR_WKMODE0H2L | AT91_SHDW_MR_WKMODE0L2H,
- &shdwn->mr);
-
- /* Enable clocks for all PIOs */
- writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
- (1 << ATMEL_ID_PIOC),
- &pmc->pcer);
-
- /* set SCL0 and SDA0 to open drain */
- at91_set_pio_output(I2C0_PORT, SCL0_PIN, 1);
- at91_set_pio_multi_drive(I2C0_PORT, SCL0_PIN, 1);
- at91_set_pio_pullup(I2C0_PORT, SCL0_PIN, 1);
- at91_set_pio_output(I2C0_PORT, SDA0_PIN, 1);
- at91_set_pio_multi_drive(I2C0_PORT, SDA0_PIN, 1);
- at91_set_pio_pullup(I2C0_PORT, SDA0_PIN, 1);
-
- /* set SCL1 and SDA1 to open drain */
- at91_set_pio_output(I2C1_PORT, SCL1_PIN, 1);
- at91_set_pio_multi_drive(I2C1_PORT, SCL1_PIN, 1);
- at91_set_pio_pullup(I2C1_PORT, SCL1_PIN, 1);
- at91_set_pio_output(I2C1_PORT, SDA1_PIN, 1);
- at91_set_pio_multi_drive(I2C1_PORT, SDA1_PIN, 1);
- at91_set_pio_pullup(I2C1_PORT, SDA1_PIN, 1);
- return 0;
-}
-
-int board_init(void)
-{
- /* arch number of TOP9000 Board */
- gd->bd->bi_arch_number = MACH_TYPE_TOP9000;
- /* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- at91_seriald_hw_init();
-#ifdef CONFIG_CMD_NAND
- nand_hw_init();
-#endif
-#ifdef CONFIG_MACB
- macb_hw_init();
-#endif
-#ifdef CONFIG_ATMEL_SPI0
- /* (n+4) denotes to use nSPISEL(0) in GPIO mode! */
- at91_spi0_hw_init(1 << (FRAM_CS_NUM + 4));
-#endif
-#ifdef CONFIG_ATMEL_SPI1
- at91_spi1_hw_init(1 << (ENC_CS_NUM + 4));
-#endif
- return 0;
-}
-
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
-{
- /* read 'factory' part of EEPROM */
- read_factory_r();
- return 0;
-}
-#endif
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-void reset_phy(void)
-{
- /*
- * Initialize ethernet HW addresses prior to starting Linux,
- * needed for nfsroot.
- * TODO: We need to investigate if that is really necessary.
- */
- eth_init(gd->bd);
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
- int num = 0;
-#ifdef CONFIG_MACB
- rc = macb_eth_initialize(0,
- (void *)ATMEL_BASE_EMAC0,
- CONFIG_SYS_PHY_ID);
- if (!rc)
- num++;
-#endif
-#ifdef CONFIG_ENC28J60
- rc = enc28j60_initialize(ENC_SPI_BUS, ENC_CS_NUM,
- ENC_SPI_CLOCK, SPI_MODE_0);
- if (!rc)
- num++;
-# ifdef CONFIG_ENC28J60_2
- rc = enc28j60_initialize(ENC_SPI_BUS, ENC_CS_NUM+1,
- ENC_SPI_CLOCK, SPI_MODE_0);
- if (!rc)
- num++;
-# ifdef CONFIG_ENC28J60_3
- rc = enc28j60_initialize(ENC_SPI_BUS, ENC_CS_NUM+2,
- ENC_SPI_CLOCK, SPI_MODE_0);
- if (!rc)
- num++;
-# endif
-# endif
-#endif
- return num;
-}
-
-/*
- * I2C access functions
- *
- * Note:
- * We need to access Bus 0 before relocation to access the
- * environment settings.
- * However i2c_get_bus_num() cannot be called before
- * relocation.
- */
-#ifdef CONFIG_SYS_I2C_SOFT
-void iic_init(void)
-{
- /* ports are now initialized in board_early_init_f() */
-}
-
-int iic_read(void)
-{
- switch (I2C_ADAP_HWNR) {
- case 0:
- return at91_get_pio_value(I2C0_PORT, SDA0_PIN);
- case 1:
- return at91_get_pio_value(I2C1_PORT, SDA1_PIN);
- }
- return 1;
-}
-
-void iic_sda(int bit)
-{
- switch (I2C_ADAP_HWNR) {
- case 0:
- at91_set_pio_value(I2C0_PORT, SDA0_PIN, bit);
- break;
- case 1:
- at91_set_pio_value(I2C1_PORT, SDA1_PIN, bit);
- break;
- }
-}
-
-void iic_scl(int bit)
-{
- switch (I2C_ADAP_HWNR) {
- case 0:
- at91_set_pio_value(I2C0_PORT, SCL0_PIN, bit);
- break;
- case 1:
- at91_set_pio_value(I2C1_PORT, SCL1_PIN, bit);
- break;
- }
-}
-
-#endif
{
block_dev_desc_t *stor_dev = NULL;
long sz;
- int i, res, cnt, old_ctrlc;
+ int i, res, old_ctrlc;
char buffer[32];
char str[80];
int n;
clear_ctrlc ();
break;
}
- cnt++;
} while (res < 0);
}
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- * for cpci750 Reinhard Arlt
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * main board support/init for the cpci750.
- */
-
-#ifndef __64360_H__
-#define __64360_H__
-
-/* CPU Configuration bits */
-#define CPU_CONF_ADDR_MISS_EN (1 << 8)
-#define CPU_CONF_SINGLE_CPU (1 << 11)
-#define CPU_CONF_ENDIANESS (1 << 12)
-#define CPU_CONF_PIPELINE (1 << 13)
-#define CPU_CONF_STOP_RETRY (1 << 17)
-#define CPU_CONF_MULTI_DECODE (1 << 18)
-#define CPU_CONF_DP_VALID (1 << 19)
-#define CPU_CONF_PERR_PROP (1 << 22)
-#define CPU_CONF_AACK_DELAY_2 (1 << 25)
-#define CPU_CONF_AP_VALID (1 << 26)
-#define CPU_CONF_REMAP_WR_DIS (1 << 27)
-
-/* CPU Master Control bits */
-#define CPU_MAST_CTL_ARB_EN (1 << 8)
-#define CPU_MAST_CTL_MASK_BR_1 (1 << 9)
-#define CPU_MAST_CTL_M_WR_TRIG (1 << 10)
-#define CPU_MAST_CTL_M_RD_TRIG (1 << 11)
-#define CPU_MAST_CTL_CLEAN_BLK (1 << 12)
-#define CPU_MAST_CTL_FLUSH_BLK (1 << 13)
-
-#endif /* __64360_H__ */
+++ /dev/null
-if TARGET_CPCI750
-
-config SYS_BOARD
- default "cpci750"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "CPCI750"
-
-endif
+++ /dev/null
-CPCI750 BOARD
-M: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-S: Maintained
-F: board/esd/cpci750/
-F: include/configs/CPCI750.h
-F: configs/CPCI750_defconfig
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2001
-# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = misc.o
-obj-y += cpci750.o serial.o ../../Marvell/common/memory.o pci.o \
- mv_eth.o mpsc.o i2c.o \
- sdram_init.o ide.o
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
- * modifications for the cpci750 by reinhard.arlt@esd-electronics.com
- */
-
-/*
- * cpci750.c - main board support/init for the esd cpci750.
- */
-
-#include <common.h>
-#include <command.h>
-#include <74xx_7xx.h>
-#include "../../Marvell/include/memory.h"
-#include "../../Marvell/include/pci.h"
-#include "../../Marvell/include/mv_gen_reg.h"
-#include <net.h>
-
-#include "eth.h"
-#include "mpsc.h"
-#include "i2c.h"
-#include "64360.h"
-#include "mv_regs.h"
-
-#undef DEBUG
-/*#define DEBUG */
-
-#ifdef CONFIG_PCI
-#define MAP_PCI
-#endif /* of CONFIG_PCI */
-
-#ifdef DEBUG
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-static char show_config_tab[][15] = {{"PCI0DLL_2 "}, /* 31 */
- {"PCI0DLL_1 "}, /* 30 */
- {"PCI0DLL_0 "}, /* 29 */
- {"PCI1DLL_2 "}, /* 28 */
- {"PCI1DLL_1 "}, /* 27 */
- {"PCI1DLL_0 "}, /* 26 */
- {"BbEP2En "}, /* 25 */
- {"SDRAMRdDataDel"}, /* 24 */
- {"SDRAMRdDel "}, /* 23 */
- {"SDRAMSync "}, /* 22 */
- {"SDRAMPipeSel_1"}, /* 21 */
- {"SDRAMPipeSel_0"}, /* 20 */
- {"SDRAMAddDel "}, /* 19 */
- {"SDRAMClkSel "}, /* 18 */
- {"Reserved(1!) "}, /* 17 */
- {"PCIRty "}, /* 16 */
- {"BootCSWidth_1 "}, /* 15 */
- {"BootCSWidth_0 "}, /* 14 */
- {"PCI1PadsCal "}, /* 13 */
- {"PCI0PadsCal "}, /* 12 */
- {"MultiMVId_1 "}, /* 11 */
- {"MultiMVId_0 "}, /* 10 */
- {"MultiGTEn "}, /* 09 */
- {"Int60xArb "}, /* 08 */
- {"CPUBusConfig_1"}, /* 07 */
- {"CPUBusConfig_0"}, /* 06 */
- {"DefIntSpc "}, /* 05 */
- {0 }, /* 04 */
- {"SROMAdd_1 "}, /* 03 */
- {"SROMAdd_0 "}, /* 02 */
- {"DRAMPadCal "}, /* 01 */
- {"SInitEn "}, /* 00 */
- {0 }, /* 31 */
- {0 }, /* 30 */
- {0 }, /* 29 */
- {0 }, /* 28 */
- {0 }, /* 27 */
- {0 }, /* 26 */
- {0 }, /* 25 */
- {0 }, /* 24 */
- {0 }, /* 23 */
- {0 }, /* 22 */
- {"JTAGCalBy "}, /* 21 */
- {"GB2Sel "}, /* 20 */
- {"GB1Sel "}, /* 19 */
- {"DRAMPLL_MDiv_5"}, /* 18 */
- {"DRAMPLL_MDiv_4"}, /* 17 */
- {"DRAMPLL_MDiv_3"}, /* 16 */
- {"DRAMPLL_MDiv_2"}, /* 15 */
- {"DRAMPLL_MDiv_1"}, /* 14 */
- {"DRAMPLL_MDiv_0"}, /* 13 */
- {"GB0Sel "}, /* 12 */
- {"DRAMPLLPU "}, /* 11 */
- {"DRAMPLL_HIKVCO"}, /* 10 */
- {"DRAMPLLNP "}, /* 09 */
- {"DRAMPLL_NDiv_7"}, /* 08 */
- {"DRAMPLL_NDiv_6"}, /* 07 */
- {"CPUPadCal "}, /* 06 */
- {"DRAMPLL_NDiv_5"}, /* 05 */
- {"DRAMPLL_NDiv_4"}, /* 04 */
- {"DRAMPLL_NDiv_3"}, /* 03 */
- {"DRAMPLL_NDiv_2"}, /* 02 */
- {"DRAMPLL_NDiv_1"}, /* 01 */
- {"DRAMPLL_NDiv_0"}}; /* 00 */
-
-extern flash_info_t flash_info[];
-
-extern int do_bootvx (cmd_tbl_t *, int, int, char *[]);
-
-/* ------------------------------------------------------------------------- */
-
-/* this is the current GT register space location */
-/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
-
-/* Unfortunately, we cant change it while we are in flash, so we initialize it
- * to the "final" value. This means that any debug_led calls before
- * board_early_init_f wont work right (like in cpu_init_f).
- * See also my_remap_gt_regs below. (NTL)
- */
-
-void board_prebootm_init (void);
-unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
-int display_mem_map (void);
-
-/*
- * Skip video initialization on slave variant.
- * This function will overwrite the weak default in cfb_console.c
- */
-int board_video_skip(void)
-{
- return CPCI750_SLAVE_TEST;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * This is a version of the GT register space remapping function that
- * doesn't touch globals (meaning, it's ok to run from flash.)
- *
- * Unfortunately, this has the side effect that a writable
- * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
- */
-
-void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
-{
- u32 temp;
-
- /* check and see if it's already moved */
-
-/* original ppcboot 1.1.6 source
-
- temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
- if ((temp & 0xffff) == new_loc >> 20)
- return;
-
- temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
- 0xffff0000) | (new_loc >> 20);
-
- out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
-
- while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
-original ppcboot 1.1.6 source end */
-
- temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
- if ((temp & 0xffff) == new_loc >> 16)
- return;
-
- temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
- 0xffff0000) | (new_loc >> 16);
-
- out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
-
- while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
-}
-
-#ifdef CONFIG_PCI
-
-static void gt_pci_config (void)
-{
- unsigned int stat;
- unsigned int data;
- unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
-
- /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
- * config registers by writing ones to the bus and device.
- * We then update the Virtual register with the correct value for the bus and device.
- */
- if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
- GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
-
- GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
-
- GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
- GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
- (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
-
- }
- if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
- GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
- GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
-
- GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
- GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
- (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
- }
-
- /* Enable master */
- PCI_MASTER_ENABLE (0, SELF);
- PCI_MASTER_ENABLE (1, SELF);
-
- /* Enable PCI0/1 Mem0 and IO 0 disable all others */
- GT_REG_READ (BASE_ADDR_ENABLE, &stat);
- stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
- <<
- 18);
- stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
- GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
-
- /* ronen- add write to pci remap registers for 64460.
- in 64360 when writing to pci base go and overide remap automaticaly,
- in 64460 it doesn't */
- GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16);
- GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16);
- GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
-
- GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
-
- GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16);
- GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16);
- GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
-
- GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
-
- /* PCI interface settings */
- /* Timeout set to retry forever */
- GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
- GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
-
- /* ronen - enable only CS0 and Internal reg!! */
- GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
- GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
-
-/*ronen update the pci internal registers base address.*/
-#ifdef MAP_PCI
- for (stat = 0; stat <= PCI_HOST1; stat++) {
- data = pciReadConfigReg(stat,
- PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
- SELF);
- data = (data & 0x0f) | CONFIG_SYS_GT_REGS;
- pciWriteConfigReg (stat,
- PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
- SELF, data);
- }
-#endif
-
-}
-#endif
-
-/* Setup CPU interface paramaters */
-static void gt_cpu_config (void)
-{
- cpu_t cpu = get_cpu_type ();
- ulong tmp;
-
- /* cpu configuration register */
- tmp = GTREGREAD (CPU_CONFIGURATION);
-
- /* set the SINGLE_CPU bit see MV64360 P.399 */
-#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
- tmp |= CPU_CONF_SINGLE_CPU;
-#endif
-
- tmp &= ~CPU_CONF_AACK_DELAY_2;
-
- tmp |= CPU_CONF_DP_VALID;
- tmp |= CPU_CONF_AP_VALID;
-
- tmp |= CPU_CONF_PIPELINE;
-
- GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */
-
- /* CPU master control register */
- tmp = GTREGREAD (CPU_MASTER_CONTROL);
-
- tmp |= CPU_MAST_CTL_ARB_EN;
-
- if ((cpu == CPU_7400) ||
- (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
-
- tmp |= CPU_MAST_CTL_CLEAN_BLK;
- tmp |= CPU_MAST_CTL_FLUSH_BLK;
-
- } else {
- /* cleanblock must be cleared for CPUs
- * that do not support this command (603e, 750)
- * see Res#1 */
- tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
- tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
- }
- GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
-}
-
-/*
- * board_early_init_f.
- *
- * set up gal. device mappings, etc.
- */
-int board_early_init_f (void)
-{
-
- /*
- * set up the GT the way the kernel wants it
- * the call to move the GT register space will obviously
- * fail if it has already been done, but we're going to assume
- * that if it's not at the power-on location, it's where we put
- * it last time. (huber)
- */
-
- my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
-
- /* No PCI in first release of Port To_do: enable it. */
-#ifdef CONFIG_PCI
- gt_pci_config ();
-#endif
- /* mask all external interrupt sources */
- GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
- GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
- /* new in MV6436x */
- GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
- GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
- /* --------------------- */
- GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
- GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
- GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
- GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
- /* does not exist in MV6436x
- GT_REG_WRITE(CPU_INT_0_MASK, 0);
- GT_REG_WRITE(CPU_INT_1_MASK, 0);
- GT_REG_WRITE(CPU_INT_2_MASK, 0);
- GT_REG_WRITE(CPU_INT_3_MASK, 0);
- --------------------- */
-
-
- /* ----- DEVICE BUS SETTINGS ------ */
-
- /*
- * EVB
- * 0 - SRAM ????
- * 1 - RTC ????
- * 2 - UART ????
- * 3 - Flash checked 32Bit Intel Strata
- * boot - BootCS checked 8Bit 29LV040B
- *
- */
-
- /*
- * the dual 7450 module requires burst access to the boot
- * device, so the serial rom copies the boot device to the
- * on-board sram on the eval board, and updates the correct
- * registers to boot from the sram. (device0)
- */
-
- memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
- memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
- memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
- memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
-
-
- /* configure device timing */
- GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
- GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
- GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
- GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_DEV3_PAR);
-
-#ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */
- /* detect if we are booting from the 32 bit flash */
- if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
- /* 32 bit boot flash */
- GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
- GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
- CONFIG_SYS_32BIT_BOOT_PAR);
- } else {
- /* 8 bit boot flash */
- GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
- GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
- }
-#else
- /* 8 bit boot flash only */
-/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
-#endif
-
-
- gt_cpu_config ();
-
- /* MPP setup */
- GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
- GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
- GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
- GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
-
- GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
- DEBUG_LED0_ON ();
- DEBUG_LED1_ON ();
- DEBUG_LED2_ON ();
-
- return 0;
-}
-
-/* various things to do after relocation */
-
-int misc_init_r ()
-{
- icache_enable ();
-#ifdef CONFIG_SYS_L2
- l2cache_enable ();
-#endif
-#ifdef CONFIG_MPSC
-
- mpsc_sdma_init ();
- mpsc_init2 ();
-#endif
-
-#if 0
- /* disable the dcache and MMU */
- dcache_lock ();
-#endif
- if (flash_info[3].size < CONFIG_SYS_FLASH_INCREMENT) {
- unsigned int flash_offset;
- unsigned int l;
-
- flash_offset = CONFIG_SYS_FLASH_INCREMENT - flash_info[3].size;
- for (l = 0; l < CONFIG_SYS_MAX_FLASH_SECT; l++) {
- if (flash_info[3].start[l] != 0) {
- flash_info[3].start[l] += flash_offset;
- }
- }
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[3]);
- }
- return 0;
-}
-
-void after_reloc (ulong dest_addr, gd_t * gd)
-{
- memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE,
- CONFIG_SYS_BOOT_SIZE);
-
- display_mem_map ();
- GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
- GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
-
- /* now, jump to the main ppcboot board init code */
- board_init_r (gd, dest_addr);
- /* NOTREACHED */
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- *
- * right now, assume borad type. (there is just one...after all)
- */
-
-int checkboard (void)
-{
- int l_type = 0;
-
- printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
- return (l_type);
-}
-
-/* utility functions */
-void debug_led (int led, int mode)
-{
-}
-
-int display_mem_map (void)
-{
- int i, j;
- unsigned int base, size, width;
-
- /* SDRAM */
- printf ("SD (DDR) RAM\n");
- for (i = 0; i <= BANK3; i++) {
- base = memoryGetBankBaseAddress (i);
- size = memoryGetBankSize (i);
- if (size != 0) {
- printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
- i, base, size >> 20);
- }
- }
-#ifdef CONFIG_PCI
- /* CPU's PCI windows */
- for (i = 0; i <= PCI_HOST1; i++) {
- printf ("\nCPU's PCI %d windows\n", i);
- base = pciGetSpaceBase (i, PCI_IO);
- size = pciGetSpaceSize (i, PCI_IO);
- printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base,
- size >> 20);
- for (j = 0;
- j <=
- PCI_REGION0
- /*ronen currently only first PCI MEM is used 3 */ ;
- j++) {
- base = pciGetSpaceBase (i, j);
- size = pciGetSpaceSize (i, j);
- printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
- }
- }
-#endif /* of CONFIG_PCI */
- /* Devices */
- printf ("\nDEVICES\n");
- for (i = 0; i <= DEVICE3; i++) {
- base = memoryGetDeviceBaseAddress (i);
- size = memoryGetDeviceSize (i);
- width = memoryGetDeviceWidth (i) * 8;
- printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
- if (i == 0)
- printf ("\t- FLASH\n");
- else if (i == 1)
- printf ("\t- FLASH\n");
- else if (i == 2)
- printf ("\t- FLASH\n");
- else
- printf ("\t- RTC/REGS/CAN\n");
- }
-
- /* Bootrom */
- base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */
- size = memoryGetDeviceSize (BOOT_DEVICE);
- width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
- printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\t- FLASH\n",
- base, size >> 20, width);
- return (0);
-}
-
-/*
- * Command loadpci: wait for signal from host and boot image.
- */
-int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- volatile unsigned int *ptr;
- int count = 0;
- int count2 = 0;
- int status = 0;
- char addr[16];
- char str[] = "\\|/-";
- char *local_args[2];
-
- /*
- * Mark sync address
- */
- ptr = 0;
- ptr[0] = 0xffffffff;
- ptr[1] = 0xffffffff;
- puts("\nWaiting for image from pci host -");
-
- /*
- * Wait for host to write the start address
- */
- while (*ptr == 0xffffffff) {
- count++;
- if (!(count % 100)) {
- count2++;
- putc(0x08); /* backspace */
- putc(str[count2 % 4]);
- }
-
- /* Abort if ctrl-c was pressed */
- if (ctrlc()) {
- puts("\nAbort\n");
- return 0;
- }
-
- udelay(1000);
- }
-
- sprintf(addr, "%08x", *ptr);
- printf("\nBooting Image at addr 0x%s ...\n", addr);
- setenv("loadaddr", addr);
-
- switch (ptr[1] == 0) {
- case 0:
- /*
- * Boot image via bootm
- */
- local_args[0] = argv[0];
- local_args[1] = NULL;
- status = do_bootm (cmdtp, 0, 1, local_args);
- break;
- case 1:
- /*
- * Boot image via bootvx
- */
- local_args[0] = argv[0];
- local_args[1] = NULL;
- status = do_bootvx (cmdtp, 0, 1, local_args);
- break;
- }
-
- return status;
-}
-
-U_BOOT_CMD(
- loadpci, 1, 1, do_loadpci,
- "loadpci - Wait for pci-image and boot it\n",
- NULL
- );
-
-/* DRAM check routines copied from gw8260 */
-
-#if defined (CONFIG_SYS_DRAM_TEST)
-
-/*********************************************************************/
-/* NAME: move64() - moves a double word (64-bit) */
-/* */
-/* DESCRIPTION: */
-/* this function performs a double word move from the data at */
-/* the source pointer to the location at the destination pointer. */
-/* */
-/* INPUTS: */
-/* unsigned long long *src - pointer to data to move */
-/* */
-/* OUTPUTS: */
-/* unsigned long long *dest - pointer to locate to move data */
-/* */
-/* RETURNS: */
-/* None */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* May cloober fr0. */
-/* */
-/*********************************************************************/
-static void move64 (unsigned long long *src, unsigned long long *dest)
-{
- asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
- "stfd 0, 0(4)" /* *dest = fpr0 */
- : : : "fr0"); /* Clobbers fr0 */
- return;
-}
-
-
-#if defined (CONFIG_SYS_DRAM_TEST_DATA)
-
-unsigned long long pattern[] = {
- 0xaaaaaaaaaaaaaaaaLL,
- 0xccccccccccccccccLL,
- 0xf0f0f0f0f0f0f0f0LL,
- 0xff00ff00ff00ff00LL,
- 0xffff0000ffff0000LL,
- 0xffffffff00000000LL,
- 0x00000000ffffffffLL,
- 0x0000ffff0000ffffLL,
- 0x00ff00ff00ff00ffLL,
- 0x0f0f0f0f0f0f0f0fLL,
- 0x3333333333333333LL,
- 0x5555555555555555LL,
-};
-
-/*********************************************************************/
-/* NAME: mem_test_data() - test data lines for shorts and opens */
-/* */
-/* DESCRIPTION: */
-/* Tests data lines for shorts and opens by forcing adjacent data */
-/* to opposite states. Because the data lines could be routed in */
-/* an arbitrary manner the must ensure test patterns ensure that */
-/* every case is tested. By using the following series of binary */
-/* patterns every combination of adjacent bits is test regardless */
-/* of routing. */
-/* */
-/* ...101010101010101010101010 */
-/* ...110011001100110011001100 */
-/* ...111100001111000011110000 */
-/* ...111111110000000011111111 */
-/* */
-/* Carrying this out, gives us six hex patterns as follows: */
-/* */
-/* 0xaaaaaaaaaaaaaaaa */
-/* 0xcccccccccccccccc */
-/* 0xf0f0f0f0f0f0f0f0 */
-/* 0xff00ff00ff00ff00 */
-/* 0xffff0000ffff0000 */
-/* 0xffffffff00000000 */
-/* */
-/* The number test patterns will always be given by: */
-/* */
-/* log(base 2)(number data bits) = log2 (64) = 6 */
-/* */
-/* To test for short and opens to other signals on our boards. we */
-/* simply */
-/* test with the 1's complemnt of the paterns as well. */
-/* */
-/* OUTPUTS: */
-/* Displays failing test pattern */
-/* */
-/* RETURNS: */
-/* 0 - Passed test */
-/* 1 - Failed test */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* Assumes only one one SDRAM bank */
-/* */
-/*********************************************************************/
-int mem_test_data (void)
-{
- unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
- unsigned long long temp64 = 0;
- int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
- int i;
- unsigned int hi, lo;
-
- for (i = 0; i < num_patterns; i++) {
- move64 (&(pattern[i]), pmem);
- move64 (pmem, &temp64);
-
- /* hi = (temp64>>32) & 0xffffffff; */
- /* lo = temp64 & 0xffffffff; */
- /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
-
- hi = (pattern[i] >> 32) & 0xffffffff;
- lo = pattern[i] & 0xffffffff;
- /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
-
- if (temp64 != pattern[i]) {
- printf ("\n Data Test Failed, pattern 0x%08x%08x",
- hi, lo);
- return 1;
- }
- }
-
- return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_DATA */
-
-#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
-/*********************************************************************/
-/* NAME: mem_test_address() - test address lines */
-/* */
-/* DESCRIPTION: */
-/* This function performs a test to verify that each word im */
-/* memory is uniquly addressable. The test sequence is as follows: */
-/* */
-/* 1) write the address of each word to each word. */
-/* 2) verify that each location equals its address */
-/* */
-/* OUTPUTS: */
-/* Displays failing test pattern and address */
-/* */
-/* RETURNS: */
-/* 0 - Passed test */
-/* 1 - Failed test */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/* */
-/*********************************************************************/
-int mem_test_address (void)
-{
- volatile unsigned int *pmem =
- (volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
- const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
- unsigned int i;
-
- /* write address to each location */
- for (i = 0; i < size; i++) {
- pmem[i] = i;
- }
-
- /* verify each loaction */
- for (i = 0; i < size; i++) {
- if (pmem[i] != i) {
- printf ("\n Address Test Failed at 0x%x", i);
- return 1;
- }
- }
- return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
-
-#if defined (CONFIG_SYS_DRAM_TEST_WALK)
-/*********************************************************************/
-/* NAME: mem_march() - memory march */
-/* */
-/* DESCRIPTION: */
-/* Marches up through memory. At each location verifies rmask if */
-/* read = 1. At each location write wmask if write = 1. Displays */
-/* failing address and pattern. */
-/* */
-/* INPUTS: */
-/* volatile unsigned long long * base - start address of test */
-/* unsigned int size - number of dwords(64-bit) to test */
-/* unsigned long long rmask - read verify mask */
-/* unsigned long long wmask - wrtie verify mask */
-/* short read - verifies rmask if read = 1 */
-/* short write - writes wmask if write = 1 */
-/* */
-/* OUTPUTS: */
-/* Displays failing test pattern and address */
-/* */
-/* RETURNS: */
-/* 0 - Passed test */
-/* 1 - Failed test */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/* */
-/*********************************************************************/
-int mem_march (volatile unsigned long long *base,
- unsigned int size,
- unsigned long long rmask,
- unsigned long long wmask, short read, short write)
-{
- unsigned int i;
- unsigned long long temp = 0;
- unsigned int hitemp, lotemp, himask, lomask;
-
- for (i = 0; i < size; i++) {
- if (read != 0) {
- /* temp = base[i]; */
- move64 ((unsigned long long *) &(base[i]), &temp);
- if (rmask != temp) {
- hitemp = (temp >> 32) & 0xffffffff;
- lotemp = temp & 0xffffffff;
- himask = (rmask >> 32) & 0xffffffff;
- lomask = rmask & 0xffffffff;
-
- printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
- return 1;
- }
- }
- if (write != 0) {
- /* base[i] = wmask; */
- move64 (&wmask, (unsigned long long *) &(base[i]));
- }
- }
- return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_WALK */
-
-/*********************************************************************/
-/* NAME: mem_test_walk() - a simple walking ones test */
-/* */
-/* DESCRIPTION: */
-/* Performs a walking ones through entire physical memory. The */
-/* test uses as series of memory marches, mem_march(), to verify */
-/* and write the test patterns to memory. The test sequence is as */
-/* follows: */
-/* 1) march writing 0000...0001 */
-/* 2) march verifying 0000...0001 , writing 0000...0010 */
-/* 3) repeat step 2 shifting masks left 1 bit each time unitl */
-/* the write mask equals 1000...0000 */
-/* 4) march verifying 1000...0000 */
-/* The test fails if any of the memory marches return a failure. */
-/* */
-/* OUTPUTS: */
-/* Displays which pass on the memory test is executing */
-/* */
-/* RETURNS: */
-/* 0 - Passed test */
-/* 1 - Failed test */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/* */
-/*********************************************************************/
-int mem_test_walk (void)
-{
- unsigned long long mask;
- volatile unsigned long long *pmem =
- (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
- const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
-
- unsigned int i;
-
- mask = 0x01;
-
- printf ("Initial Pass");
- mem_march (pmem, size, 0x0, 0x1, 0, 1);
-
- printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
- printf (" ");
- printf (" ");
- printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
-
- for (i = 0; i < 63; i++) {
- printf ("Pass %2d", i + 2);
- if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
- /*printf("mask: 0x%x, pass: %d, ", mask, i); */
- return 1;
- }
- mask = mask << 1;
- printf ("\b\b\b\b\b\b\b");
- }
-
- printf ("Last Pass");
- if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
- /* printf("mask: 0x%x", mask); */
- return 1;
- }
- printf ("\b\b\b\b\b\b\b\b\b");
- printf (" ");
- printf ("\b\b\b\b\b\b\b\b\b");
-
- return 0;
-}
-
-/*********************************************************************/
-/* NAME: testdram() - calls any enabled memory tests */
-/* */
-/* DESCRIPTION: */
-/* Runs memory tests if the environment test variables are set to */
-/* 'y'. */
-/* */
-/* INPUTS: */
-/* testdramdata - If set to 'y', data test is run. */
-/* testdramaddress - If set to 'y', address test is run. */
-/* testdramwalk - If set to 'y', walking ones test is run */
-/* */
-/* OUTPUTS: */
-/* None */
-/* */
-/* RETURNS: */
-/* 0 - Passed test */
-/* 1 - Failed test */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/* */
-/*********************************************************************/
-int testdram (void)
-{
- int rundata = 0;
- int runaddress = 0;
- int runwalk = 0;
-
-#ifdef CONFIG_SYS_DRAM_TEST_DATA
- rundata = getenv_yesno("testdramdata") == 1;
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
- runaddress = getenv_yesno("testdramaddress") == 1;
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_WALK
- runwalk = getenv_yesno("testdramwalk") == 1;
-#endif
-
- if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
- printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
- }
-#ifdef CONFIG_SYS_DRAM_TEST_DATA
- if (rundata == 1) {
- printf ("Test DATA ... ");
- if (mem_test_data () == 1) {
- printf ("failed \n");
- return 1;
- } else
- printf ("ok \n");
- }
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
- if (runaddress == 1) {
- printf ("Test ADDRESS ... ");
- if (mem_test_address () == 1) {
- printf ("failed \n");
- return 1;
- } else
- printf ("ok \n");
- }
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_WALK
- if (runwalk == 1) {
- printf ("Test WALKING ONEs ... ");
- if (mem_test_walk () == 1) {
- printf ("failed \n");
- return 1;
- } else
- printf ("ok \n");
- }
-#endif
- if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
- printf ("passed\n");
- }
- return 0;
-
-}
-#endif /* CONFIG_SYS_DRAM_TEST */
-
-/* ronen - the below functions are used by the bootm function */
-/* - we map the base register to fbe00000 (same mapping as in the LSP) */
-/* - we turn off the RX gig dmas - to prevent the dma from overunning */
-/* the kernel data areas. */
-/* - we diable and invalidate the icache and dcache. */
-void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
-{
- u32 temp;
-
- temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
- if ((temp & 0xffff) == new_loc >> 16)
- return;
-
- temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
- 0xffff0000) | (new_loc >> 16);
-
- out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
-
- while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
- new_loc |
- (INTERNAL_SPACE_DECODE)))))
- != temp);
-
-}
-
-void board_prebootm_init ()
-{
-
-/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
- GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
-
-/* Stop GigE Rx DMA engines */
- GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
-/* GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00); */
-/* GV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); */
-
-/* Relocate MV64360 internal regs */
- my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, CONFIG_SYS_DFL_GT_REGS);
-
- icache_disable ();
- dcache_disable ();
-}
-
-int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned int reset_sample_low;
- unsigned int reset_sample_high;
- unsigned int l, l1, l2;
-
- GT_REG_READ(0x3c4, &reset_sample_low);
- GT_REG_READ(0x3d4, &reset_sample_high);
- printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high);
-
- l2 = 0;
- for (l=0; l<63; l++) {
- if (show_config_tab[l][0] != 0) {
- printf("%14s:%1x ", show_config_tab[l],
- ((reset_sample_low >> (31 - (l & 0x1f)))) & 0x01);
- l2++;
- if ((l2 % 4) == 0)
- printf("\n");
- } else {
- l1++;
- }
- if (l == 32)
- reset_sample_low = reset_sample_high;
- }
- printf("\n");
-
- return(0);
-}
-
-U_BOOT_CMD(
- show_config, 1, 1, do_show_config,
- "Show Marvell strapping register",
- "Show Marvell strapping register (ResetSampleLow ResetSampleHigh)"
-);
-
-int do_pldver(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- printf("PLD version:0x%02x\n", in_8((void *)CONFIG_SYS_PLD_VER));
-
- return 0;
-}
-
-U_BOOT_CMD(
- pldver, 1, 1, do_pldver,
- "Show PLD version",
- "Show PLD version)");
-
-int board_eth_init(bd_t *bis)
-{
- return mv6436x_eth_initialize(bis);
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * eth.h - header file for the polled mode GT ethernet driver
- */
-
-#ifndef __EVB64360_ETH_H__
-#define __EVB64360_ETH_H__
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-#include <common.h>
-
-
-int db64360_eth0_poll(void);
-int db64360_eth0_transmit(unsigned int s, volatile char *p);
-void db64360_eth0_disable(void);
-bool network_start(bd_t *bis);
-
-int mv6436x_eth_initialize(bd_t *);
-
-#endif /* __EVB64360_ETH_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
- * extra improvments by Brain Waite
- * for cpci750 by reinhard.arlt@esd-electronics.com
- */
-#include <common.h>
-#include <mpc8xx.h>
-#include <malloc.h>
-#include <i2c.h>
-#include "../../Marvell/include/mv_gen_reg.h"
-#include "../../Marvell/include/core.h"
-
-#define I2C_DELAY 100
-#undef DEBUG_I2C
-
-#ifdef DEBUG_I2C
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-/* Assuming that there is only one master on the bus (us) */
-
-void i2c_init (int speed, int slaveaddr)
-{
- unsigned int n, m, freq, margin, power;
- unsigned int actualN = 0, actualM = 0;
- unsigned int minMargin = 0xffffffff;
- unsigned int tclk = CONFIG_SYS_TCLK;
- unsigned int i2cFreq = speed; /* 100000 max. Fast mode not supported */
-
- DP (puts ("i2c_init\n"));
-/* gtI2cMasterInit */
- for (n = 0; n < 8; n++) {
- for (m = 0; m < 16; m++) {
- power = 2 << n; /* power = 2^(n+1) */
- freq = tclk / (10 * (m + 1) * power);
- if (i2cFreq > freq)
- margin = i2cFreq - freq;
- else
- margin = freq - i2cFreq;
- if (margin < minMargin) {
- minMargin = margin;
- actualN = n;
- actualM = m;
- }
- }
- }
-
- DP (puts ("setup i2c bus\n"));
-
- /* Setup bus */
- /* gtI2cReset */
- GT_REG_WRITE (I2C_SOFT_RESET, 0);
- asm(" sync");
- GT_REG_WRITE (I2C_CONTROL, 0);
- asm(" sync");
-
- DP (puts ("set baudrate\n"));
-
- GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN);
- asm(" sync");
-
- DP (puts ("udelay...\n"));
-
- udelay (I2C_DELAY);
-
- GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6));
- asm(" sync");
-}
-
-
-static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
-{
- unsigned int status, data, bits = 7;
- unsigned int control;
- int count = 0;
-
- DP (puts ("i2c_select_device\n"));
-
- /* Output slave address */
-
- if (ten_bit) {
- bits = 10;
- }
-
- GT_REG_READ (I2C_CONTROL, &control);
- control |= (0x1 << 2);
- GT_REG_WRITE (I2C_CONTROL, control);
- asm(" sync");
-
- GT_REG_READ (I2C_CONTROL, &control);
- control |= (0x1 << 5); /* generate the I2C_START_BIT */
- GT_REG_WRITE (I2C_CONTROL, control);
- asm(" sync");
- RESET_REG_BITS (I2C_CONTROL, (0x01 << 3));
- asm(" sync");
-
- GT_REG_READ (I2C_CONTROL, &status);
- while ((status & 0x08) != 0x08) {
- GT_REG_READ (I2C_CONTROL, &status);
- }
-
-
- count = 0;
-
- GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
- while (((status & 0xff) != 0x08) && ((status & 0xff) != 0x10)){
- if (count > 200) {
-#ifdef DEBUG_I2C
- printf ("Failed to set startbit: 0x%02x\n", status);
-#endif
- GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
- asm(" sync");
- return (status);
- }
- GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
- count++;
- }
-
- DP (puts ("i2c_select_device:write addr byte\n"));
-
- /* assert the address */
-
- data = (dev_addr << 1);
- /* set the read bit */
- data |= read;
- GT_REG_WRITE (I2C_DATA, data);
- asm(" sync");
- RESET_REG_BITS (I2C_CONTROL, BIT3);
- asm(" sync");
-
- GT_REG_READ (I2C_CONTROL, &status);
- while ((status & 0x08) != 0x08) {
- GT_REG_READ (I2C_CONTROL, &status);
- }
-
- GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
- count = 0;
- while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) {
- if (count > 200) {
-#ifdef DEBUG_I2C
- printf ("Failed to write address: 0x%02x\n", status);
-#endif
- GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
- return (status);
- }
- GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
- asm(" sync");
- count++;
- }
-
- if (bits == 10) {
- printf ("10 bit I2C addressing not yet implemented\n");
- return (0xff);
- }
-
- return (0);
-}
-
-static uchar i2c_get_data (uchar * return_data, int len)
-{
-
- unsigned int data, status;
- int count = 0;
-
- DP (puts ("i2c_get_data\n"));
-
- while (len) {
-
- RESET_REG_BITS (I2C_CONTROL, BIT3);
- asm(" sync");
-
- /* Get and return the data */
-
- GT_REG_READ (I2C_CONTROL, &status);
- while ((status & 0x08) != 0x08) {
- GT_REG_READ (I2C_CONTROL, &status);
- }
-
- GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
- count++;
- while ((status & 0xff) != 0x50) {
- if (count > 20) {
-#ifdef DEBUG_I2C
- printf ("Failed to get data len status: 0x%02x\n", status);
-#endif
- GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
- asm(" sync");
- return 0;
- }
- GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
- count++;
- }
- GT_REG_READ (I2C_DATA, &data);
- len--;
- *return_data = (uchar) data;
- return_data++;
-
- }
- RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3);
- asm(" sync");
- count = 0;
-
- GT_REG_READ (I2C_CONTROL, &status);
- while ((status & 0x08) != 0x08) {
- GT_REG_READ (I2C_CONTROL, &status);
- }
-
- while ((status & 0xff) != 0x58) {
- if (count > 2000) {
- GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
- return (status);
- }
- GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
- count++;
- }
- GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /* stop */
- asm(" sync");
- RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
- asm(" sync");
-
- return (0);
-}
-
-
-static uchar i2c_write_data (unsigned int *data, int len)
-{
- unsigned int status;
- int count;
- unsigned int temp;
- unsigned int *temp_ptr = data;
-
- DP (puts ("i2c_write_data\n"));
-
- while (len) {
- count = 0;
- temp = (unsigned int) (*temp_ptr);
- GT_REG_WRITE (I2C_DATA, temp);
- asm(" sync");
- RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
- asm(" sync");
-
- GT_REG_READ (I2C_CONTROL, &status);
- while ((status & 0x08) != 0x08) {
- GT_REG_READ (I2C_CONTROL, &status);
- }
-
- GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
- count++;
- while ((status & 0xff) != 0x28) {
- if (count > 200) {
- GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
- asm(" sync");
- return (status);
- }
- GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
- count++;
- }
- len--;
- temp_ptr++;
- }
- return (0);
-}
-
-
-static uchar i2c_write_byte (unsigned char *data, int len)
-{
- unsigned int status;
- int count;
- unsigned int temp;
- unsigned char *temp_ptr = data;
-
- DP (puts ("i2c_write_byte\n"));
-
- while (len) {
- count = 0;
- /* Set and assert the data */
- temp = *temp_ptr;
- GT_REG_WRITE (I2C_DATA, temp);
- asm(" sync");
- RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
- asm(" sync");
-
-
- GT_REG_READ (I2C_CONTROL, &status);
- while ((status & 0x08) != 0x08) {
- GT_REG_READ (I2C_CONTROL, &status);
- }
-
- GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
- count++;
- while ((status & 0xff) != 0x28) {
- if (count > 200) {
- GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
- asm(" sync");
- return (status);
- }
- GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
- count++;
- }
- len--;
- temp_ptr++;
- }
- return (0);
-}
-
-static uchar
-i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit,
- int alen)
-{
- uchar status;
- unsigned int table[2];
-
- table[1] = (offset ) & 0x0ff; /* low byte */
- table[0] = (offset >> 8) & 0x0ff; /* high byte */
-
- DP (puts ("i2c_set_dev_offset\n"));
-
- status = i2c_select_device (dev_addr, 0, ten_bit);
- if (status) {
-#ifdef DEBUG_I2C
-22 printf ("Failed to select device setting offset: 0x%02x\n",
- status);
-#endif
- return status;
- }
-/* check the address offset length */
- if (alen == 0)
- /* no address offset */
- return (0);
- else if (alen == 1) {
- /* 1 byte address offset */
- status = i2c_write_data (&offset, 1);
- if (status) {
-#ifdef DEBUG_I2C
- printf ("Failed to write data: 0x%02x\n", status);
-#endif
- return status;
- }
- } else if (alen == 2) {
- /* 2 bytes address offset */
- status = i2c_write_data (table, 2);
- if (status) {
-#ifdef DEBUG_I2C
- printf ("Failed to write data: 0x%02x\n", status);
-#endif
- return status;
- }
- } else {
- /* address offset unknown or not supported */
- printf ("Address length offset %d is not supported\n", alen);
- return 1;
- }
- return 0; /* sucessful completion */
-}
-
-int
-i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
- int len)
-{
- uchar status = 0;
- unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
-
- DP (puts ("i2c_read\n"));
-
- /* set the i2c frequency */
- i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
-
- status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */
- if (status) {
-#ifdef DEBUG_I2C
- printf ("Failed to set slave address & offset: 0x%02x\n",
- status);
-#endif
- return status;
- }
-
- status = i2c_select_device (dev_addr, 1, 0);
- if (status) {
-#ifdef DEBUG_I2C
- printf ("Failed to select device for data read: 0x%02x\n",
- status);
-#endif
- return status;
- }
-
- status = i2c_get_data (data, len);
- if (status) {
-#ifdef DEBUG_I2C
- printf ("Data not read: 0x%02x\n", status);
-#endif
- return status;
- }
-
- return 0;
-}
-
-
-void i2c_stop (void)
-{
- GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));
- asm(" sync");
-}
-
-
-int
-i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
- int len)
-{
- uchar status = 0;
- unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
-
- DP (puts ("i2c_write\n"));
-
- /* set the i2c frequency */
- i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
-
- status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */
- if (status) {
-#ifdef DEBUG_I2C
- printf ("Failed to set slave address & offset: 0x%02x\n",
- status);
-#endif
- return status;
- }
-
-
- status = i2c_write_byte (data, len); /* write the data */
- if (status) {
-#ifdef DEBUG_I2C
- printf ("Data not written: 0x%02x\n", status);
-#endif
- return status;
- }
- /* issue a stop bit */
- i2c_stop ();
- return 0;
-}
-
-
-int i2c_probe (uchar chip)
-{
-
-#ifdef DEBUG_I2C
- unsigned int i2c_status;
-#endif
- uchar status = 0;
- unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
-
- DP (puts ("i2c_probe\n"));
-
- /* set the i2c frequency */
- i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
-
- status = i2c_set_dev_offset (chip, 0, 0, 0); /* send the slave address + no offset */
- if (status) {
-#ifdef DEBUG_I2C
- printf ("Failed to set slave address: 0x%02x\n", status);
-#endif
- return (int) status;
- }
-#ifdef DEBUG_I2C
- GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status);
- printf ("address %#x returned %#x\n", chip, i2c_status);
-#endif
- /* issue a stop bit */
- i2c_stop ();
- return 0; /* successful completion */
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
- */
-
-#ifndef __I2C_H__
-#define __I2C_H__
-
-/* function declarations */
-uchar i2c_read(uchar, unsigned int, int, uchar*, int);
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-/* ide.c - ide support functions */
-
-
-#include <common.h>
-#if defined(CONFIG_CMD_IDE)
-#include <ata.h>
-#include <ide.h>
-#include <pci.h>
-
-int cpci_hd_type;
-
-int ata_device(int dev)
-{
- int retval;
-
- retval = (dev & 1) << 4;
- if (cpci_hd_type == 2)
- retval ^= 1 << 4;
- return retval;
-}
-
-
-int ide_preinit (void)
-{
- int status;
- pci_dev_t devbusfn;
- int l;
-
- status = 1;
- cpci_hd_type = 0;
- if (CPCI750_SLAVE_TEST != 0)
- return status;
- for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) {
- ide_bus_offset[l] = -ATA_STATUS;
- }
- devbusfn = pci_find_device (0x1103, 0x0004, 0);
- if (devbusfn != -1) {
- cpci_hd_type = 1;
- } else {
- devbusfn = pci_find_device (0x1095, 0x3114, 0);
- if (devbusfn != -1) {
- cpci_hd_type = 2;
- }
- }
- if (devbusfn != -1) {
- ulong *ide_bus_offset_ptr;
-
- status = 0;
-
- ide_bus_offset_ptr = &ide_bus_offset[0];
- pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
- (u32 *)ide_bus_offset_ptr);
- ide_bus_offset[0] &= 0xfffffffe;
- ide_bus_offset[0] += CONFIG_SYS_PCI0_IO_SPACE;
- ide_bus_offset_ptr = &ide_bus_offset[1];
- pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2,
- (u32 *)ide_bus_offset_ptr);
- ide_bus_offset[1] &= 0xfffffffe;
- ide_bus_offset[1] += CONFIG_SYS_PCI0_IO_SPACE;
- }
- return status;
-}
-
-void ide_set_reset (int flag) {
- return;
-}
-
-#endif /* of CONFIG_CMDS_IDE */
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * include/local.h - local configuration options, board specific
- */
-
-#ifndef __LOCAL_H
-#define __LOCAL_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-/* This tells PPCBoot that the config options are compiled in */
-/* #undef ENV_IS_EMBEDDED */
-/* Don't touch this! PPCBOOT figures this out based on other
- * magic. */
-
-/* Uncomment and define any of the below options */
-
-/* #define CONFIG_750CX */ /* The 750CX doesn't support as many things in L2CR */
-#define CONFIG_750FX /* The 750FX doesn't support as many things in L2CR like 750CX*/
-
-/* These want string arguments */
-/* #define CONFIG_BOOTARGS */
-/* #define CONFIG_BOOTCOMMAND */
-/* #define CONFIG_RAMBOOTCOMMAND */
-/* #define CONFIG_NFSBOOTCOMMAND */
-/* #define CONFIG_SYS_AUTOLOAD */
-/* #define CONFIG_PREBOOT */
-
-/* These don't */
-
-/* #define CONFIG_BOOTDELAY */
-/* #define CONFIG_BAUDRATE */
-/* #define CONFIG_LOADS_ECHO */
-/* #define CONFIG_ETHADDR */
-/* #define CONFIG_ETH2ADDR */
-/* #define CONFIG_ETH3ADDR */
-/* #define CONFIG_IPADDR */
-/* #define CONFIG_SERVERIP */
-/* #define CONFIG_ROOTPATH */
-/* #define CONFIG_GATEWAYIP */
-/* #define CONFIG_NETMASK */
-/* #define CONFIG_HOSTNAME */
-/* #define CONFIG_BOOTFILE */
-/* #define CONFIG_LOADADDR */
-
-/* these hardware addresses are pretty bogus, please change them to
- suit your needs */
-
-/* first ethernet */
-/* #define CONFIG_ETHADDR 86:06:2d:7e:c6:53 */
-#define CONFIG_ETHADDR 64:36:00:00:00:01
-
-/* next two ethernet hwaddrs */
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 86:06:2d:7e:c6:54
-#define CONFIG_HAS_ETH2
-#define CONFIG_ETH2ADDR 86:06:2d:7e:c6:55
-
-#define CONFIG_ENV_OVERWRITE
-#endif /* __CONFIG_H */
+++ /dev/null
-#include <config.h>
-#include <74xx_7xx.h>
-#include "version.h"
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#include "../../Marvell/include/mv_gen_reg.h"
-
-#ifdef CONFIG_ECC
- /* Galileo specific asm code for initializing ECC */
- .globl board_relocate_rom
-board_relocate_rom:
- mflr r7
- /* update the location of the GT registers */
- lis r11, CONFIG_SYS_GT_REGS@h
- /* if we're using ECC, we must use the DMA engine to copy ourselves */
- bl start_idma_transfer_0
- bl wait_for_idma_0
- bl stop_idma_engine_0
-
- mtlr r7
- blr
-
- .globl board_init_ecc
-board_init_ecc:
- mflr r7
- /* NOTE: r10 still contains the location we've been relocated to
- * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
-
- /* now that we're running from ram, init the rest of main memory
- * for ECC use */
- lis r8, CONFIG_SYS_MONITOR_LEN@h
- ori r8, r8, CONFIG_SYS_MONITOR_LEN@l
-
- divw r3, r10, r8
-
- /* set up the counter, and init the starting address */
- mtctr r3
- li r12, 0
-
- /* bytes per transfer */
- mr r5, r8
-about_to_init_ecc:
-1: mr r3, r12
- mr r4, r12
- bl start_idma_transfer_0
- bl wait_for_idma_0
- bl stop_idma_engine_0
- add r12, r12, r8
- bdnz 1b
-
- mtlr r7
- blr
-
- /* r3: dest addr
- * r4: source addr
- * r5: byte count
- * r11: gt regbase
- * trashes: r6, r5
- */
-start_idma_transfer_0:
- /* set the byte count, including the OWN bit */
- mr r6, r11
- ori r6, r6, CHANNEL0_DMA_BYTE_COUNT
- stwbrx r5, 0, (r6)
-
- /* set the source address */
- mr r6, r11
- ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
- stwbrx r4, 0, (r6)
-
- /* set the dest address */
- mr r6, r11
- ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
- stwbrx r3, 0, (r6)
-
- /* set the next record pointer */
- li r5, 0
- mr r6, r11
- ori r6, r6, CHANNEL0NEXT_RECORD_POINTER
- stwbrx r5, 0, (r6)
-
- /* set the low control register */
- /* bit 9 is NON chained mode, bit 31 is new style descriptors.
- bit 12 is channel enable */
- ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
- /* 15 shifted by 16 (oris) == bit 31 */
- oris r5, r5, (1 << 15)
- mr r6, r11
- ori r6, r6, CHANNEL0CONTROL
- stwbrx r5, 0, (r6)
-
- blr
-
- /* this waits for the bytecount to return to zero, indicating
- * that the trasfer is complete */
-wait_for_idma_0:
- mr r5, r11
- lis r6, 0xff
- ori r6, r6, 0xffff
- ori r5, r5, CHANNEL0_DMA_BYTE_COUNT
-1: lwbrx r4, 0, (r5)
- and. r4, r4, r6
- bne 1b
-
- blr
-
- /* this turns off channel 0 of the idma engine */
-stop_idma_engine_0:
- /* shut off the DMA engine */
- li r5, 0
- mr r6, r11
- ori r6, r6, CHANNEL0CONTROL
- stwbrx r5, 0, (r6)
-
- blr
-#endif
-
-#ifdef CONFIG_SYS_BOARD_ASM_INIT
- /* NOTE: trashes r3-r7 */
- .globl board_asm_init
-board_asm_init:
- /* just move the GT registers to where they belong */
- lis r3, CONFIG_SYS_DFL_GT_REGS@h
- ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l
- lis r4, CONFIG_SYS_GT_REGS@h
- ori r4, r4, CONFIG_SYS_GT_REGS@l
- li r5, INTERNAL_SPACE_DECODE
-
- /* test to see if we've already moved */
- lwbrx r6, r5, r4
- andi. r6, r6, 0xffff
- /* check loading of R7 is: 0x0F80 should: 0xf800: DONE */
-/* rlwinm r7, r4, 8, 16, 31
- rlwinm r7, r4, 12, 16, 31 */ /* original */
- rlwinm r7, r4, 16, 16, 31
- /* -----------------------------------------------------*/
- cmp cr0, r7, r6
- beqlr
-
- /* nope, have to move the registers */
- lwbrx r6, r5, r3
- andis. r6, r6, 0xffff
- or r6, r6, r7
- stwbrx r6, r5, r3
-
- /* now, poll for the change */
-1: lwbrx r7, r5, r4
- cmp cr0, r7, r6
- bne 1b
-
- lis r3, CONFIG_SYS_INT_SRAM_BASE@h
- ori r3, r3, CONFIG_SYS_INT_SRAM_BASE@l
- rlwinm r3, r3, 16, 16, 31
- lis r4, CONFIG_SYS_GT_REGS@h
- ori r4, r4, CONFIG_SYS_GT_REGS@l
- li r5, INTEGRATED_SRAM_BASE_ADDR
- stwbrx r3, r5, r4
-
-2: lwbrx r6, r5, r4
- cmp cr0, r3, r6
- bne 2b
-
- /* done! */
- blr
-#endif
-
-/* For use of the debug LEDs */
- .global led_on0_relocated
-led_on0_relocated:
- xor r21, r21, r21
- xor r18, r18, r18
- lis r18, 0xFC80
- ori r18, r18, 0x8000
-/* stw r21, 0x0(r18) */
- sync
- blr
-
- .global led_off0_relocated
-led_off0_relocated:
- xor r21, r21, r21
- xor r18, r18, r18
- lis r18, 0xFC81
- ori r18, r18, 0x4000
-/* stw r21, 0x0(r18) */
- sync
- blr
-
- .global led_on0
-led_on0:
- xor r18, r18, r18
- lis r18, 0x1c80
- ori r18, r18, 0x8000
-/* stw r18, 0x0(r18) */
- sync
- blr
-
- .global led_off0
-led_off0:
- xor r18, r18, r18
- lis r18, 0x1c81
- ori r18, r18, 0x4000
-/* stw r18, 0x0(r18) */
- sync
- blr
-
- .global led_on1
-led_on1:
- xor r18, r18, r18
- lis r18, 0x1c80
- ori r18, r18, 0xc000
-/* stw r18, 0x0(r18) */
- sync
- blr
-
- .global led_off1
-led_off1:
- xor r18, r18, r18
- lis r18, 0x1c81
- ori r18, r18, 0x8000
-/* stw r18, 0x0(r18) */
- sync
- blr
-
- .global led_on2
-led_on2:
- xor r18, r18, r18
- lis r18, 0x1c81
- ori r18, r18, 0x0000
-/* stw r18, 0x0(r18) */
- sync
- blr
-
- .global led_off2
-led_off2:
- xor r18, r18, r18
- lis r18, 0x1c81
- ori r18, r18, 0xc000
-/* stw r18, 0x0(r18) */
- sync
- blr
+++ /dev/null
-/*
- * (C) Copyright 2001
- * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*************************************************************************
- * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
- *
- ************************************************************************/
-
-/*
- * mpsc.c - driver for console over the MPSC.
- */
-
-
-#include <common.h>
-#include <config.h>
-#include <asm/cache.h>
-
-#include <malloc.h>
-#include "mpsc.h"
-
-#include "mv_regs.h"
-
-#include "../../Marvell/include/memory.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Define this if you wish to use the MPSC as a register based UART.
- * This will force the serial port to not use the SDMA engine at all.
- */
-
-#undef CONFIG_MPSC_DEBUG_PORT
-
-
-int (*mpsc_putchar) (char ch) = mpsc_putchar_early;
-char (*mpsc_getchar) (void) = mpsc_getchar_debug;
-int (*mpsc_test_char) (void) = mpsc_test_char_debug;
-
-
-static volatile unsigned int *rx_desc_base = NULL;
-static unsigned int rx_desc_index = 0;
-static volatile unsigned int *tx_desc_base = NULL;
-static unsigned int tx_desc_index = 0;
-
-/* local function declarations */
-static int galmpsc_connect (int channel, int connect);
-static int galmpsc_route_rx_clock (int channel, int brg);
-static int galmpsc_route_tx_clock (int channel, int brg);
-static int galmpsc_write_config_regs (int mpsc, int mode);
-static int galmpsc_config_channel_regs (int mpsc);
-static int galmpsc_set_char_length (int mpsc, int value);
-static int galmpsc_set_stop_bit_length (int mpsc, int value);
-static int galmpsc_set_parity (int mpsc, int value);
-static int galmpsc_enter_hunt (int mpsc);
-static int galmpsc_set_brkcnt (int mpsc, int value);
-static int galmpsc_set_tcschar (int mpsc, int value);
-static int galmpsc_set_snoop (int mpsc, int value);
-static int galmpsc_shutdown (int mpsc);
-
-static int galsdma_set_RFT (int channel);
-static int galsdma_set_SFM (int channel);
-static int galsdma_set_rxle (int channel);
-static int galsdma_set_txle (int channel);
-static int galsdma_set_burstsize (int channel, unsigned int value);
-static int galsdma_set_RC (int channel, unsigned int value);
-
-static int galbrg_set_CDV (int channel, int value);
-static int galbrg_enable (int channel);
-static int galbrg_disable (int channel);
-static int galbrg_set_clksrc (int channel, int value);
-static int galbrg_set_CUV (int channel, int value);
-
-static void galsdma_enable_rx (void);
-static int galsdma_set_mem_space (unsigned int memSpace,
- unsigned int memSpaceTarget,
- unsigned int memSpaceAttr,
- unsigned int baseAddress,
- unsigned int size);
-
-
-#define SOFTWARE_CACHE_MANAGEMENT
-
-#ifdef SOFTWARE_CACHE_MANAGEMENT
-#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
-#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
-#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
-#else
-#define FLUSH_DCACHE(a,b)
-#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
-#define INVALIDATE_DCACHE(a,b)
-#endif
-
-#ifdef CONFIG_MPSC_DEBUG_PORT
-static void mpsc_debug_init (void)
-{
-
- volatile unsigned int temp;
-
- /* Clear the CFR (CHR4) */
- /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
- temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
- temp &= 0xffffff00;
- temp |= BIT29;
- GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
- temp);
-
- /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */
- temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP));
- temp |= (BIT12 | BIT15);
- GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP),
- temp);
-
- /* Set int mask */
- temp = GTREGREAD (GALMPSC_0_INT_MASK);
- temp |= BIT6;
- GT_REG_WRITE (GALMPSC_0_INT_MASK, temp);
-}
-#endif
-
-char mpsc_getchar_debug (void)
-{
- volatile int temp;
- volatile unsigned int cause;
-
- cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
- while ((cause & BIT6) == 0) {
- cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
- }
-
- temp = GTREGREAD (GALMPSC_CHANNELREG_10 +
- (CHANNEL * GALMPSC_REG_GAP));
- /* By writing 1's to the set bits, the register is cleared */
- GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP),
- temp);
- GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6);
- return (temp >> 16) & 0xff;
-}
-
-/* special function for running out of flash. doesn't modify any
- * global variables [josh] */
-int mpsc_putchar_early (char ch)
-{
- int mpsc = CHANNEL;
- int temp =
- GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
- galmpsc_set_tcschar (mpsc, ch);
- GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP),
- temp | 0x200);
-
-#define MAGIC_FACTOR (10*1000000)
-
- udelay (MAGIC_FACTOR / gd->baudrate);
- return 0;
-}
-
-/* This is used after relocation, see serial.c and mpsc_init2 */
-static int mpsc_putchar_sdma (char ch)
-{
- volatile unsigned int *p;
- unsigned int temp;
-
-
- /* align the descriptor */
- p = tx_desc_base;
- memset ((void *) p, 0, 8 * sizeof (unsigned int));
-
- /* fill one 64 bit buffer */
- /* word swap, pad with 0 */
- p[4] = 0; /* x */
- p[5] = (unsigned int) ch; /* x */
-
- /* CHANGED completely according to GT64260A dox - NTL */
- p[0] = 0x00010001; /* 0 */
- p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* 4 */
- p[2] = 0; /* 8 */
- p[3] = (unsigned int) &p[4]; /* c */
-
-#if 0
- p[9] = DESC_FIRST | DESC_LAST;
- p[10] = (unsigned int) &p[0];
- p[11] = (unsigned int) &p[12];
-#endif
-
- FLUSH_DCACHE (&p[0], &p[8]);
-
- GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
- (unsigned int) &p[0]);
- GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
- (unsigned int) &p[0]);
-
- temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
- temp |= (TX_DEMAND | TX_STOP);
- GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
-
- INVALIDATE_DCACHE (&p[1], &p[2]);
-
- while (p[1] & DESC_OWNER_BIT) {
- udelay (100);
- INVALIDATE_DCACHE (&p[1], &p[2]);
- }
- return 0;
-}
-
-char mpsc_getchar_sdma (void)
-{
- static unsigned int done = 0;
- volatile char ch;
- unsigned int len = 0, idx = 0, temp;
-
- volatile unsigned int *p;
-
-
- do {
- p = &rx_desc_base[rx_desc_index * 8];
-
- INVALIDATE_DCACHE (&p[0], &p[1]);
- /* Wait for character */
- while (p[1] & DESC_OWNER_BIT) {
- udelay (100);
- INVALIDATE_DCACHE (&p[0], &p[1]);
- }
-
- /* Handle error case */
- if (p[1] & (1 << 15)) {
- printf ("oops, error: %08x\n", p[1]);
-
- temp = GTREGREAD (GALMPSC_CHANNELREG_2 +
- (CHANNEL * GALMPSC_REG_GAP));
- temp |= (1 << 23);
- GT_REG_WRITE (GALMPSC_CHANNELREG_2 +
- (CHANNEL * GALMPSC_REG_GAP), temp);
-
- /* Can't poll on abort bit, so we just wait. */
- udelay (100);
-
- galsdma_enable_rx ();
- }
-
- /* Number of bytes left in this descriptor */
- len = p[0] & 0xffff;
-
- if (len) {
- /* Where to look */
- idx = 5;
- if (done > 3)
- idx = 4;
- if (done > 7)
- idx = 7;
- if (done > 11)
- idx = 6;
-
- INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
- ch = p[idx] & 0xff;
- done++;
- }
-
- if (done < len) {
- /* this descriptor has more bytes still
- * shift down the char we just read, and leave the
- * buffer in place for the next time around
- */
- p[idx] = p[idx] >> 8;
- FLUSH_DCACHE (&p[idx], &p[idx + 1]);
- }
-
- if (done == len) {
- /* nothing left in this descriptor.
- * go to next one
- */
- p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
- p[0] = 0x00100000;
- FLUSH_DCACHE (&p[0], &p[1]);
- /* Next descriptor */
- rx_desc_index = (rx_desc_index + 1) % RX_DESC;
- done = 0;
- }
- } while (len == 0); /* galileo bug.. len might be zero */
-
- return ch;
-}
-
-
-int mpsc_test_char_debug (void)
-{
- if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0)
- return 0;
- else {
- return 1;
- }
-}
-
-
-int mpsc_test_char_sdma (void)
-{
- volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8];
-
- INVALIDATE_DCACHE (&p[1], &p[2]);
-
- if (p[1] & DESC_OWNER_BIT)
- return 0;
- else
- return 1;
-}
-
-int mpsc_init (int baud)
-{
- /* BRG CONFIG */
- galbrg_set_baudrate (CHANNEL, baud);
- galbrg_set_clksrc (CHANNEL, 8); /* set source=Tclk */
- galbrg_set_CUV (CHANNEL, 0); /* set up CountUpValue */
- galbrg_enable (CHANNEL); /* Enable BRG */
-
- /* Set up clock routing */
- galmpsc_connect (CHANNEL, GALMPSC_CONNECT); /* connect it */
-
- galmpsc_route_rx_clock (CHANNEL, CHANNEL); /* chosse BRG0 for Rx */
- galmpsc_route_tx_clock (CHANNEL, CHANNEL); /* chose BRG0 for Tx */
-
- /* reset MPSC state */
- galmpsc_shutdown (CHANNEL);
-
- /* SDMA CONFIG */
- galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8); /* in 64 bit words (8 bytes) */
- galsdma_set_txle (CHANNEL);
- galsdma_set_rxle (CHANNEL);
- galsdma_set_RC (CHANNEL, 0xf);
- galsdma_set_SFM (CHANNEL);
- galsdma_set_RFT (CHANNEL);
-
- /* MPSC CONFIG */
- galmpsc_write_config_regs (CHANNEL, GALMPSC_UART);
- galmpsc_config_channel_regs (CHANNEL);
- galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */
- galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE); /* N */
- galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */
-
-#ifdef CONFIG_MPSC_DEBUG_PORT
- mpsc_debug_init ();
-#endif
-
- /* COMM_MPSC CONFIG */
-#ifdef SOFTWARE_CACHE_MANAGEMENT
- galmpsc_set_snoop (CHANNEL, 0); /* disable snoop */
-#else
- galmpsc_set_snoop (CHANNEL, 1); /* enable snoop */
-#endif
-
- return 0;
-}
-
-
-void mpsc_sdma_init (void)
-{
-/* Setup SDMA channel0 SDMA_CONFIG_REG*/
- GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff);
-
-/* Enable MPSC-Window0 for DRAM Bank0 */
- if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT,
- MV64360_SDMA_DRAM_CS_0_TARGET,
- 0,
- memoryGetBankBaseAddress
- (CS_0_LOW_DECODE_ADDRESS),
- memoryGetBankSize (BANK0)) != true)
- printf ("%s: SDMA_Window0 memory setup failed !!! \n",
- __FUNCTION__);
-
-
-/* Disable MPSC-Window1 */
- if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_1_BIT,
- MV64360_SDMA_DRAM_CS_0_TARGET,
- 0,
- memoryGetBankBaseAddress
- (CS_1_LOW_DECODE_ADDRESS),
- memoryGetBankSize (BANK3)) != true)
- printf ("%s: SDMA_Window1 memory setup failed !!! \n",
- __FUNCTION__);
-
-
-/* Disable MPSC-Window2 */
- if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_2_BIT,
- MV64360_SDMA_DRAM_CS_0_TARGET,
- 0,
- memoryGetBankBaseAddress
- (CS_2_LOW_DECODE_ADDRESS),
- memoryGetBankSize (BANK3)) != true)
- printf ("%s: SDMA_Window2 memory setup failed !!! \n",
- __FUNCTION__);
-
-
-/* Disable MPSC-Window3 */
- if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_3_BIT,
- MV64360_SDMA_DRAM_CS_0_TARGET,
- 0,
- memoryGetBankBaseAddress
- (CS_3_LOW_DECODE_ADDRESS),
- memoryGetBankSize (BANK3)) != true)
- printf ("%s: SDMA_Window3 memory setup failed !!! \n",
- __FUNCTION__);
-
-/* Setup MPSC0 access mode Window0 full access */
- GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG,
- (MV64360_SDMA_WIN_ACCESS_FULL <<
- (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
-
-/* Setup MPSC1 access mode Window1 full access */
- GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG,
- (MV64360_SDMA_WIN_ACCESS_FULL <<
- (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
-
-/* Setup MPSC internal address space base address */
- GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
-
-/* no high address remap*/
- GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
- GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00);
-
-/* clear interrupt cause register for MPSC (fault register)*/
- GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00);
-}
-
-
-void mpsc_init2 (void)
-{
- int i;
-
-#ifndef CONFIG_MPSC_DEBUG_PORT
- mpsc_putchar = mpsc_putchar_sdma;
- mpsc_getchar = mpsc_getchar_sdma;
- mpsc_test_char = mpsc_test_char_sdma;
-#endif
- /* RX descriptors */
- rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) *
- sizeof (unsigned int));
-
- /* align descriptors */
- rx_desc_base = (unsigned int *)
- (((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0);
-
- rx_desc_index = 0;
-
- memset ((void *) rx_desc_base, 0,
- (RX_DESC * 8) * sizeof (unsigned int));
-
- for (i = 0; i < RX_DESC; i++) {
- rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4]; /* Buffer */
- rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8]; /* Next descriptor */
- rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* Command & control */
- rx_desc_base[i * 8] = 0x00100000;
- }
- rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0];
-
- FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]);
- GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
- (unsigned int) &rx_desc_base[0]);
-
- /* TX descriptors */
- tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) *
- sizeof (unsigned int));
-
- /* align descriptors */
- tx_desc_base = (unsigned int *)
- (((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0);
-
- tx_desc_index = -1;
-
- memset ((void *) tx_desc_base, 0,
- (TX_DESC * 8) * sizeof (unsigned int));
-
- for (i = 0; i < TX_DESC; i++) {
- tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323;
- tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323;
- tx_desc_base[i * 8 + 3] =
- (unsigned int) &tx_desc_base[i * 8 + 4];
- tx_desc_base[i * 8 + 2] =
- (unsigned int) &tx_desc_base[(i + 1) * 8];
- tx_desc_base[i * 8 + 1] =
- DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
-
- /* set sbytecnt and shadow byte cnt to 1 */
- tx_desc_base[i * 8] = 0x00010001;
- }
- tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0];
-
- FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]);
-
- udelay (100);
-
- galsdma_enable_rx ();
-
- return;
-}
-
-int galbrg_set_baudrate (int channel, int rate)
-{
- int clock;
-
- galbrg_disable (channel); /*ok */
-
-#ifdef ZUMA_NTL
- /* from tclk */
- clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
-#else
- clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
-#endif
-
- galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */
-
- galbrg_enable (channel);
-
- gd->baudrate = rate;
-
- return 0;
-}
-
-/* ------------------------------------------------------------------ */
-
-/* Below are all the private functions that no one else needs */
-
-static int galbrg_set_CDV (int channel, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
- temp &= 0xFFFF0000;
- temp |= (value & 0x0000FFFF);
- GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
- return 0;
-}
-
-static int galbrg_enable (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
- temp |= 0x00010000;
- GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
- return 0;
-}
-
-static int galbrg_disable (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
- temp &= 0xFFFEFFFF;
- GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
- return 0;
-}
-
-static int galbrg_set_clksrc (int channel, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
- temp &= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */
- temp |= (value << 18);
- GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
- return 0;
-}
-
-static int galbrg_set_CUV (int channel, int value)
-{
- /* set CountUpValue */
- GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
-
- return 0;
-}
-
-#if 0
-static int galbrg_reset (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
- temp |= 0x20000;
- GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
- return 0;
-}
-#endif
-
-static int galsdma_set_RFT (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
- temp |= 0x00000001;
- GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
- temp);
-
- return 0;
-}
-
-static int galsdma_set_SFM (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
- temp |= 0x00000002;
- GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
- temp);
-
- return 0;
-}
-
-static int galsdma_set_rxle (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
- temp |= 0x00000040;
- GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
- temp);
-
- return 0;
-}
-
-static int galsdma_set_txle (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
- temp |= 0x00000080;
- GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
- temp);
-
- return 0;
-}
-
-static int galsdma_set_RC (int channel, unsigned int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
- temp &= ~0x0000003c;
- temp |= (value << 2);
- GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
- temp);
-
- return 0;
-}
-
-static int galsdma_set_burstsize (int channel, unsigned int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
- temp &= 0xFFFFCFFF;
- switch (value) {
- case 8:
- GT_REG_WRITE (GALSDMA_0_CONF_REG +
- (channel * GALSDMA_REG_DIFF),
- (temp | (0x3 << 12)));
- break;
-
- case 4:
- GT_REG_WRITE (GALSDMA_0_CONF_REG +
- (channel * GALSDMA_REG_DIFF),
- (temp | (0x2 << 12)));
- break;
-
- case 2:
- GT_REG_WRITE (GALSDMA_0_CONF_REG +
- (channel * GALSDMA_REG_DIFF),
- (temp | (0x1 << 12)));
- break;
-
- case 1:
- GT_REG_WRITE (GALSDMA_0_CONF_REG +
- (channel * GALSDMA_REG_DIFF),
- (temp | (0x0 << 12)));
- break;
-
- default:
- return -1;
- break;
- }
-
- return 0;
-}
-
-static int galmpsc_connect (int channel, int connect)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_ROUTING_REGISTER);
-
- if ((channel == 0) && connect)
- temp &= ~0x00000007;
- else if ((channel == 1) && connect)
- temp &= ~(0x00000007 << 6);
- else if ((channel == 0) && !connect)
- temp |= 0x00000007;
- else
- temp |= (0x00000007 << 6);
-
- /* Just in case... */
- temp &= 0x3fffffff;
-
- GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp);
-
- return 0;
-}
-
-static int galmpsc_route_rx_clock (int channel, int brg)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_RxC_ROUTE);
-
- if (channel == 0) {
- temp &= ~0x0000000F;
- temp |= brg;
- } else {
- temp &= ~0x00000F00;
- temp |= (brg << 8);
- }
-
- GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp);
-
- return 0;
-}
-
-static int galmpsc_route_tx_clock (int channel, int brg)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_TxC_ROUTE);
-
- if (channel == 0) {
- temp &= ~0x0000000F;
- temp |= brg;
- } else {
- temp &= ~0x00000F00;
- temp |= (brg << 8);
- }
-
- GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp);
-
- return 0;
-}
-
-static int galmpsc_write_config_regs (int mpsc, int mode)
-{
- if (mode == GALMPSC_UART) {
- /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
- GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP),
- 0x000004c4);
-
- /* Main config reg High (32x Rx/Tx clock mode, width=8bits */
- GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP),
- 0x024003f8);
- /* 22 2222 1111 */
- /* 54 3210 9876 */
- /* 0000 0010 0000 0000 */
- /* 1 */
- /* 098 7654 3210 */
- /* 0000 0011 1111 1000 */
- } else
- return -1;
-
- return 0;
-}
-
-static int galmpsc_config_channel_regs (int mpsc)
-{
- GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1);
- GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0);
-
- galmpsc_set_brkcnt (mpsc, 0x3);
- galmpsc_set_tcschar (mpsc, 0xab);
-
- return 0;
-}
-
-static int galmpsc_set_brkcnt (int mpsc, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
- temp &= 0x0000FFFF;
- temp |= (value << 16);
- GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
-
- return 0;
-}
-
-static int galmpsc_set_tcschar (int mpsc, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
- temp &= 0xFFFF0000;
- temp |= value;
- GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
-
- return 0;
-}
-
-static int galmpsc_set_char_length (int mpsc, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
- temp &= 0xFFFFCFFF;
- temp |= (value << 12);
- GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
-
- return 0;
-}
-
-static int galmpsc_set_stop_bit_length (int mpsc, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
- temp &= 0xFFFFBFFF;
- temp |= (value << 14);
- GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
-
- return 0;
-}
-
-static int galmpsc_set_parity (int mpsc, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
- if (value != -1) {
- temp &= 0xFFF3FFF3;
- temp |= ((value << 18) | (value << 2));
- temp |= ((value << 17) | (value << 1));
- } else {
- temp &= 0xFFF1FFF1;
- }
-
- GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
-
- return 0;
-}
-
-static int galmpsc_enter_hunt (int mpsc)
-{
- int temp;
-
- temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
- temp |= 0x80000000;
- GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
-
- while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) &
- MPSC_ENTER_HUNT) {
- udelay (1);
- }
- return 0;
-}
-
-
-static int galmpsc_shutdown (int mpsc)
-{
- unsigned int temp;
-
- /* cause RX abort (clears RX) */
- temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
- temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
- temp &= ~MPSC_ENTER_HUNT;
- GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
-
- GT_REG_WRITE (GALSDMA_0_COM_REG, 0);
- GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT);
-
- /* shut down the MPSC */
- GT_REG_WRITE (GALMPSC_MCONF_LOW, 0);
- GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0);
- GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0);
-
- udelay (100);
-
- /* shut down the sdma engines. */
- /* reset config to default */
- GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc);
-
- udelay (100);
-
- /* clear the SDMA current and first TX and RX pointers */
- GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0);
- GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0);
- GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0);
-
- udelay (100);
-
- return 0;
-}
-
-static void galsdma_enable_rx (void)
-{
- int temp;
-
- /* Enable RX processing */
- temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
- temp |= RX_ENABLE;
- GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
-
- galmpsc_enter_hunt (CHANNEL);
-}
-
-static int galmpsc_set_snoop (int mpsc, int value)
-{
- int reg =
- mpsc ? MPSC_1_ADDRESS_CONTROL_LOW :
- MPSC_0_ADDRESS_CONTROL_LOW;
- int temp = GTREGREAD (reg);
-
- if (value)
- temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);
- else
- temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));
- GT_REG_WRITE (reg, temp);
- return 0;
-}
-
-/*******************************************************************************
-* galsdma_set_mem_space - Set MV64360 IDMA memory decoding map.
-*
-* DESCRIPTION:
-* the MV64360 SDMA has its own address decoding map that is de-coupled
-* from the CPU interface address decoding windows. The SDMA channels
-* share four address windows. Each region can be individually configured
-* by this function by associating it to a target interface and setting
-* base and size values.
-*
-* NOTE!!!
-* The size must be in 64Kbyte granularity.
-* The base address must be aligned to the size.
-* The size must be a series of 1s followed by a series of zeros
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* true for success, false otherwise.
-*
-*******************************************************************************/
-
-static int galsdma_set_mem_space (unsigned int memSpace,
- unsigned int memSpaceTarget,
- unsigned int memSpaceAttr,
- unsigned int baseAddress, unsigned int size)
-{
- unsigned int temp;
-
- if (size == 0) {
- GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
- 1 << memSpace);
- return true;
- }
-
- /* The base address must be aligned to the size. */
- if (baseAddress % size != 0) {
- return false;
- }
- if (size < 0x10000) {
- return false;
- }
-
- /* Align size and base to 64K */
- baseAddress &= 0xffff0000;
- size &= 0xffff0000;
- temp = size >> 16;
-
- /* Checking that the size is a sequence of '1' followed by a
- sequence of '0' starting from LSB to MSB. */
- while ((temp > 0) && (temp & 0x1)) {
- temp = temp >> 1;
- }
-
- if (temp != 0) {
- GT_REG_WRITE (MV64360_CUNIT_BASE_ADDR_REG0 + memSpace * 8,
- (baseAddress | memSpaceTarget | memSpaceAttr));
- GT_REG_WRITE ((MV64360_CUNIT_SIZE0 + memSpace * 8),
- (size - 1) & 0xffff0000);
- GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
- 1 << memSpace);
- } else {
- /* An invalid size was specified */
- return false;
- }
- return true;
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*************************************************************************
- * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
- *
- ************************************************************************/
-
-
-/*
- * mpsc.h - header file for MPSC in uart mode (console driver)
- */
-
-#ifndef __MPSC_H__
-#define __MPSC_H__
-
-/* include actual Galileo defines */
-#include "../../Marvell/include/mv_gen_reg.h"
-
-/* driver related defines */
-
-int mpsc_init(int baud);
-void mpsc_sdma_init(void);
-void mpsc_init2(void);
-int galbrg_set_baudrate(int channel, int rate);
-
-int mpsc_putchar_early(char ch);
-char mpsc_getchar_debug(void);
-int mpsc_test_char_debug(void);
-
-int mpsc_test_char_sdma(void);
-
-extern int (*mpsc_putchar)(char ch);
-extern char (*mpsc_getchar)(void);
-extern int (*mpsc_test_char)(void);
-
-#define CHANNEL CONFIG_MPSC_PORT
-
-#define TX_DESC 5
-#define RX_DESC 20
-
-#define DESC_FIRST 0x00010000
-#define DESC_LAST 0x00020000
-#define DESC_OWNER_BIT 0x80000000
-
-#define TX_DEMAND 0x00800000
-#define TX_STOP 0x00010000
-#define RX_ENABLE 0x00000080
-
-#define SDMA_RX_ABORT (1 << 15)
-#define SDMA_TX_ABORT (1 << 31)
-#define MPSC_TX_ABORT (1 << 7)
-#define MPSC_RX_ABORT (1 << 23)
-#define MPSC_ENTER_HUNT (1 << 31)
-
-/* MPSC defines */
-
-#define GALMPSC_CONNECT 0x1
-#define GALMPSC_DISCONNECT 0x0
-
-#define GALMPSC_UART 0x1
-
-#define GALMPSC_STOP_BITS_1 0x0
-#define GALMPSC_STOP_BITS_2 0x1
-#define GALMPSC_CHAR_LENGTH_8 0x3
-#define GALMPSC_CHAR_LENGTH_7 0x2
-
-#define GALMPSC_PARITY_ODD 0x0
-#define GALMPSC_PARITY_EVEN 0x2
-#define GALMPSC_PARITY_MARK 0x3
-#define GALMPSC_PARITY_SPACE 0x1
-#define GALMPSC_PARITY_NONE -1
-
-#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */
-#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */
-#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */
-#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
-#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */
-#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */
-#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */
-
-#define GALMPSC_REG_GAP 0x1000
-
-#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */
-#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */
-#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */
-#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */
-#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */
-#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */
-#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */
-#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */
-#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */
-#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */
-#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */
-#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */
-
-#define GALSDMA_COMMAND_FIRST (1 << 16)
-#define GALSDMA_COMMAND_LAST (1 << 17)
-#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
-#define GALSDMA_COMMAND_AUTO (1 << 30)
-#define GALSDMA_COMMAND_OWNER (1 << 31)
-
-#define GALSDMA_RX 0
-#define GALSDMA_TX 1
-
-/* CHANNEL2 should be CHANNEL1, according to documentation,
- * but to work with the current GTREGS file...
- */
-#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */
-#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */
-#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */
-#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */
-#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */
-#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */
-#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */
-#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */
-#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */
-#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */
-#define GALSDMA_REG_DIFF 0x2000
-
-/* WRONG in gt64260R.h */
-#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */
-#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */
-#define GALMPSC_0_INT_CAUSE 0xb804
-#define GALMPSC_0_INT_MASK 0xb884
-
-#define GALSDMA_MODE_UART 0
-#define GALSDMA_MODE_BISYNC 1
-#define GALSDMA_MODE_HDLC 2
-#define GALSDMA_MODE_TRANSPARENT 3
-
-#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */
-#define GALBRG_REG_GAP 0x0008
-#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */
-
-#endif /* __MPSC_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64360X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-/*
- * mv_eth.c - header file for the polled mode GT ethernet driver
- */
-#include <common.h>
-#include <net.h>
-#include <malloc.h>
-
-#include "mv_eth.h"
-
-/* enable Debug outputs */
-
-#undef DEBUG_MV_ETH
-
-#ifdef DEBUG_MV_ETH
-#define DEBUG
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-#undef MV64360_CHECKSUM_OFFLOAD
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-* The first part is the high level driver of the gigE ethernet ports. *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-
-/* Definition for configuring driver */
-/* #define UPDATE_STATS_BY_SOFTWARE */
-#undef MV64360_RX_QUEUE_FILL_ON_TASK
-
-
-/* Constants */
-#define MAGIC_ETH_RUNNING 8031971
-#define MV64360_INTERNAL_SRAM_SIZE _256K
-#define EXTRA_BYTES 32
-#define WRAP ETH_HLEN + 2 + 4 + 16
-#define BUFFER_MTU dev->mtu + WRAP
-#define INT_CAUSE_UNMASK_ALL 0x0007ffff
-#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
-#ifdef MV64360_RX_FILL_ON_TASK
-#define INT_CAUSE_MASK_ALL 0x00000000
-#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
-#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
-#endif
-
-/* Read/Write to/from MV64360 internal registers */
-#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
-#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
-#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
-#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
-
-/* Static function declarations */
-static int mv64360_eth_real_open (struct eth_device *eth);
-static int mv64360_eth_real_stop (struct eth_device *eth);
-static struct net_device_stats *mv64360_eth_get_stats (struct eth_device
- *dev);
-static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
-static void mv64360_eth_update_stat (struct eth_device *dev);
-bool db64360_eth_start (struct eth_device *eth);
-unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
- unsigned int mib_offset);
-int mv64360_eth_receive (struct eth_device *dev);
-
-int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length);
-
-#ifndef UPDATE_STATS_BY_SOFTWARE
-static void mv64360_eth_print_stat (struct eth_device *dev);
-#endif
-
-extern unsigned int INTERNAL_REG_BASE_ADDR;
-
-/*************************************************
- *Helper functions - used inside the driver only *
- *************************************************/
-#ifdef DEBUG_MV_ETH
-void print_globals (struct eth_device *dev)
-{
- printf ("Ethernet PRINT_Globals-Debug function\n");
- printf ("Base Address for ETH_PORT_INFO: %08x\n",
- (unsigned int) dev->priv);
- printf ("Base Address for mv64360_eth_priv: %08x\n",
- (unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
- port_private));
-
- printf ("GT Internal Base Address: %08x\n",
- INTERNAL_REG_BASE_ADDR);
- printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE);
- printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE);
- printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n",
- (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
- p_rx_buffer_base[0],
- (MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32);
- printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n",
- (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
- p_tx_buffer_base[0],
- (MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32);
-}
-#endif
-
-#define my_cpu_to_le32(x) my_le32_to_cpu((x))
-
-unsigned long my_le32_to_cpu (unsigned long x)
-{
- return (((x & 0x000000ffU) << 24) |
- ((x & 0x0000ff00U) << 8) |
- ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
-}
-
-
-/**********************************************************************
- * mv64360_eth_print_phy_status
- *
- * Prints gigabit ethenret phy status
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- **********************************************************************/
-
-static void mv64360_eth_print_phy_status (struct eth_device *dev)
-{
- struct mv64360_eth_priv *port_private;
- unsigned int port_num;
- ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
- unsigned int port_status, phy_reg_data;
-
- port_private =
- (struct mv64360_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
-
- /* Check Link status on phy */
- eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
- if (!(phy_reg_data & 0x20)) {
- printf ("Ethernet port changed link status to DOWN\n");
- } else {
- port_status =
- MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
- printf ("Ethernet status port %d: Link up", port_num);
- printf (", %s",
- (port_status & BIT2) ? "Full Duplex" : "Half Duplex");
- if (port_status & BIT4)
- printf (", Speed 1 Gbps");
- else
- printf (", %s",
- (port_status & BIT5) ? "Speed 100 Mbps" :
- "Speed 10 Mbps");
- printf ("\n");
- }
-}
-
-/**********************************************************************
- * u-boot entry functions for mv64360_eth
- *
- **********************************************************************/
-int db64360_eth_probe (struct eth_device *dev)
-{
- return ((int) db64360_eth_start (dev));
-}
-
-int db64360_eth_poll (struct eth_device *dev)
-{
- return mv64360_eth_receive (dev);
-}
-
-int db64360_eth_transmit(struct eth_device *dev, void *packet, int length)
-{
- mv64360_eth_xmit (dev, packet, length);
- return 0;
-}
-
-void db64360_eth_disable (struct eth_device *dev)
-{
- mv64360_eth_stop (dev);
-}
-
-
-void mv6436x_eth_initialize (bd_t * bis)
-{
- struct eth_device *dev;
- ETH_PORT_INFO *ethernet_private;
- struct mv64360_eth_priv *port_private;
- int devnum, x, temp;
- char *s, *e, buf[64];
-
- for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
- dev = calloc (sizeof (*dev), 1);
- if (!dev) {
- printf ("%s: mv_enet%d allocation failure, %s\n",
- __FUNCTION__, devnum, "eth_device structure");
- return;
- }
-
- /* must be less than sizeof(dev->name) */
- sprintf (dev->name, "mv_enet%d", devnum);
-
-#ifdef DEBUG
- printf ("Initializing %s\n", dev->name);
-#endif
-
- /* Extract the MAC address from the environment */
- switch (devnum) {
- case 0:
- s = "ethaddr";
- break;
-
- case 1:
- s = "eth1addr";
- break;
-
- case 2:
- s = "eth2addr";
- break;
-
- default: /* this should never happen */
- printf ("%s: Invalid device number %d\n",
- __FUNCTION__, devnum);
- return;
- }
-
- temp = getenv_f(s, buf, sizeof (buf));
- s = (temp > 0) ? buf : NULL;
-
-#ifdef DEBUG
- printf ("Setting MAC %d to %s\n", devnum, s);
-#endif
- for (x = 0; x < 6; ++x) {
- dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
- if (s)
- s = (*e) ? e + 1 : e;
- }
- /* ronen - set the MAC addr in the HW */
- eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
-
- dev->init = (void *) db64360_eth_probe;
- dev->halt = (void *) ethernet_phy_reset;
- dev->send = (void *) db64360_eth_transmit;
- dev->recv = (void *) db64360_eth_poll;
-
- ethernet_private =
- calloc (sizeof (*ethernet_private), 1);
- dev->priv = (void *) ethernet_private;
- if (!ethernet_private) {
- printf ("%s: %s allocation failure, %s\n",
- __FUNCTION__, dev->name,
- "Private Device Structure");
- free (dev);
- return;
- }
- /* start with an zeroed ETH_PORT_INFO */
- memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
- memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
-
- /* set pointer to memory for stats data structure etc... */
- port_private =
- calloc (sizeof (*ethernet_private), 1);
- ethernet_private->port_private = (void *)port_private;
- if (!port_private) {
- printf ("%s: %s allocation failure, %s\n",
- __FUNCTION__, dev->name,
- "Port Private Device Structure");
-
- free (ethernet_private);
- free (dev);
- return;
- }
-
- port_private->stats =
- calloc (sizeof (struct net_device_stats), 1);
- if (!port_private->stats) {
- printf ("%s: %s allocation failure, %s\n",
- __FUNCTION__, dev->name,
- "Net stat Structure");
-
- free (port_private);
- free (ethernet_private);
- free (dev);
- return;
- }
- memset (ethernet_private->port_private, 0,
- sizeof (struct mv64360_eth_priv));
- switch (devnum) {
- case 0:
- ethernet_private->port_num = ETH_0;
- break;
- case 1:
- ethernet_private->port_num = ETH_1;
- break;
- case 2:
- ethernet_private->port_num = ETH_2;
- break;
- default:
- printf ("Invalid device number %d\n", devnum);
- break;
- };
-
- port_private->port_num = devnum;
- /*
- * Read MIB counter on the GT in order to reset them,
- * then zero all the stats fields in memory
- */
- mv64360_eth_update_stat (dev);
- memset (port_private->stats, 0,
- sizeof (struct net_device_stats));
- /* Extract the MAC address from the environment */
- switch (devnum) {
- case 0:
- s = "ethaddr";
- break;
-
- case 1:
- s = "eth1addr";
- break;
-
- case 2:
- s = "eth2addr";
- break;
-
- default: /* this should never happen */
- printf ("%s: Invalid device number %d\n",
- __FUNCTION__, devnum);
- return;
- }
-
- temp = getenv_f(s, buf, sizeof (buf));
- s = (temp > 0) ? buf : NULL;
-
-#ifdef DEBUG
- printf ("Setting MAC %d to %s\n", devnum, s);
-#endif
- for (x = 0; x < 6; ++x) {
- dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
- if (s)
- s = (*e) ? e + 1 : e;
- }
-
- DP (printf ("Allocating descriptor and buffer rings\n"));
-
- ethernet_private->p_rx_desc_area_base[0] =
- (ETH_RX_DESC *) memalign (16,
- RX_DESC_ALIGNED_SIZE *
- MV64360_RX_QUEUE_SIZE + 1);
- ethernet_private->p_tx_desc_area_base[0] =
- (ETH_TX_DESC *) memalign (16,
- TX_DESC_ALIGNED_SIZE *
- MV64360_TX_QUEUE_SIZE + 1);
-
- ethernet_private->p_rx_buffer_base[0] =
- (char *) memalign (16,
- MV64360_RX_QUEUE_SIZE *
- MV64360_TX_BUFFER_SIZE + 1);
- ethernet_private->p_tx_buffer_base[0] =
- (char *) memalign (16,
- MV64360_RX_QUEUE_SIZE *
- MV64360_TX_BUFFER_SIZE + 1);
-
-#ifdef DEBUG_MV_ETH
- /* DEBUG OUTPUT prints adresses of globals */
- print_globals (dev);
-#endif
- eth_register (dev);
-
- }
- DP (printf ("%s: exit\n", __FUNCTION__));
-
-}
-
-/**********************************************************************
- * mv64360_eth_open
- *
- * This function is called when openning the network device. The function
- * should initialize all the hardware, initialize cyclic Rx/Tx
- * descriptors chain and buffers and allocate an IRQ to the network
- * device.
- *
- * Input : a pointer to the network device structure
- * / / ronen - changed the output to match net/eth.c needs
- * Output : nonzero of success , zero if fails.
- * under construction
- **********************************************************************/
-
-int mv64360_eth_open (struct eth_device *dev)
-{
- return (mv64360_eth_real_open (dev));
-}
-
-/* Helper function for mv64360_eth_open */
-static int mv64360_eth_real_open (struct eth_device *dev)
-{
-
- unsigned int queue;
- ETH_PORT_INFO *ethernet_private;
- struct mv64360_eth_priv *port_private;
- unsigned int port_num;
- u32 phy_reg_data;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- /* ronen - when we update the MAC env params we only update dev->enetaddr
- see ./net/eth.c eth_set_enetaddr() */
- memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
-
- port_private =
- (struct mv64360_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
-
- /* Stop RX Queues */
- MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
- 0x0000ff00);
-
- /* Clear the ethernet port interrupts */
- MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
- MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
-
- /* Unmask RX buffer and TX end interrupt */
- MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num),
- INT_CAUSE_UNMASK_ALL);
-
- /* Unmask phy and link status changes interrupts */
- MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
- INT_CAUSE_UNMASK_ALL_EXT);
-
- /* Set phy address of the port */
- ethernet_private->port_phy_addr = 0x8 + port_num;
-
- /* Activate the DMA channels etc */
- eth_port_init (ethernet_private);
-
-
- /* "Allocate" setup TX rings */
-
- for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
- unsigned int size;
-
- port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE;
- size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */
- ethernet_private->tx_desc_area_size[queue] = size;
-
- /* first clear desc area completely */
- memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
- 0, ethernet_private->tx_desc_area_size[queue]);
-
- /* initialize tx desc ring with low level driver */
- if (ether_init_tx_desc_ring
- (ethernet_private, ETH_Q0,
- port_private->tx_ring_size[queue],
- MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
- (unsigned int) ethernet_private->
- p_tx_desc_area_base[queue],
- (unsigned int) ethernet_private->
- p_tx_buffer_base[queue]) == false)
- printf ("### Error initializing TX Ring\n");
- }
-
- /* "Allocate" setup RX rings */
- for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
- unsigned int size;
-
- /* Meantime RX Ring are fixed - but must be configurable by user */
- port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE;
- size = (port_private->rx_ring_size[queue] *
- RX_DESC_ALIGNED_SIZE);
- ethernet_private->rx_desc_area_size[queue] = size;
-
- /* first clear desc area completely */
- memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
- 0, ethernet_private->rx_desc_area_size[queue]);
- if ((ether_init_rx_desc_ring
- (ethernet_private, ETH_Q0,
- port_private->rx_ring_size[queue],
- MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
- (unsigned int) ethernet_private->
- p_rx_desc_area_base[queue],
- (unsigned int) ethernet_private->
- p_rx_buffer_base[queue])) == false)
- printf ("### Error initializing RX Ring\n");
- }
-
- eth_port_start (ethernet_private);
-
- /* Set maximum receive buffer to 9700 bytes */
- MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num),
- (0x5 << 17) |
- (MV_REG_READ
- (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num))
- & 0xfff1ffff));
-
- /*
- * Set ethernet MTU for leaky bucket mechanism to 0 - this will
- * disable the leaky bucket mechanism .
- */
-
- MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
- MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
-
- /* Check Link status on phy */
- eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
- if (!(phy_reg_data & 0x20)) {
- /* Reset PHY */
- if ((ethernet_phy_reset (port_num)) != true) {
- printf ("$$ Warnning: No link on port %d \n",
- port_num);
- return 0;
- } else {
- eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
- if (!(phy_reg_data & 0x20)) {
- printf ("### Error: Phy is not active\n");
- return 0;
- }
- }
- } else {
- mv64360_eth_print_phy_status (dev);
- }
- port_private->eth_running = MAGIC_ETH_RUNNING;
- return 1;
-}
-
-
-static int mv64360_eth_free_tx_rings (struct eth_device *dev)
-{
- unsigned int queue;
- ETH_PORT_INFO *ethernet_private;
- struct mv64360_eth_priv *port_private;
- unsigned int port_num;
- volatile ETH_TX_DESC *p_tx_curr_desc;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64360_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
-
- /* Stop Tx Queues */
- MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
- 0x0000ff00);
-
- /* Free TX rings */
- DP (printf ("Clearing previously allocated TX queues... "));
- for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
- /* Free on TX rings */
- for (p_tx_curr_desc =
- ethernet_private->p_tx_desc_area_base[queue];
- ((unsigned int) p_tx_curr_desc <= (unsigned int)
- ethernet_private->p_tx_desc_area_base[queue] +
- ethernet_private->tx_desc_area_size[queue]);
- p_tx_curr_desc =
- (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
- TX_DESC_ALIGNED_SIZE)) {
- /* this is inside for loop */
- if (p_tx_curr_desc->return_info != 0) {
- p_tx_curr_desc->return_info = 0;
- DP (printf ("freed\n"));
- }
- }
- DP (printf ("Done\n"));
- }
- return 0;
-}
-
-static int mv64360_eth_free_rx_rings (struct eth_device *dev)
-{
- unsigned int queue;
- ETH_PORT_INFO *ethernet_private;
- struct mv64360_eth_priv *port_private;
- unsigned int port_num;
- volatile ETH_RX_DESC *p_rx_curr_desc;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64360_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
-
-
- /* Stop RX Queues */
- MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
- 0x0000ff00);
-
- /* Free RX rings */
- DP (printf ("Clearing previously allocated RX queues... "));
- for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
- /* Free preallocated skb's on RX rings */
- for (p_rx_curr_desc =
- ethernet_private->p_rx_desc_area_base[queue];
- (((unsigned int) p_rx_curr_desc <
- ((unsigned int) ethernet_private->
- p_rx_desc_area_base[queue] +
- ethernet_private->rx_desc_area_size[queue])));
- p_rx_curr_desc =
- (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
- RX_DESC_ALIGNED_SIZE)) {
- if (p_rx_curr_desc->return_info != 0) {
- p_rx_curr_desc->return_info = 0;
- DP (printf ("freed\n"));
- }
- }
- DP (printf ("Done\n"));
- }
- return 0;
-}
-
-/**********************************************************************
- * mv64360_eth_stop
- *
- * This function is used when closing the network device.
- * It updates the hardware,
- * release all memory that holds buffers and descriptors and release the IRQ.
- * Input : a pointer to the device structure
- * Output : zero if success , nonzero if fails
- *********************************************************************/
-
-int mv64360_eth_stop (struct eth_device *dev)
-{
- /* Disable all gigE address decoder */
- MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
- DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
- mv64360_eth_real_stop (dev);
-
- return 0;
-};
-
-/* Helper function for mv64360_eth_stop */
-
-static int mv64360_eth_real_stop (struct eth_device *dev)
-{
- ETH_PORT_INFO *ethernet_private;
- struct mv64360_eth_priv *port_private;
- unsigned int port_num;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64360_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
-
-
- mv64360_eth_free_tx_rings (dev);
- mv64360_eth_free_rx_rings (dev);
-
- eth_port_reset (ethernet_private->port_num);
- /* Disable ethernet port interrupts */
- MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
- MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
- /* Mask RX buffer and TX end interrupt */
- MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0);
- /* Mask phy and link status changes interrupts */
- MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
- MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH,
- BIT0 << port_num);
- /* Print Network statistics */
-#ifndef UPDATE_STATS_BY_SOFTWARE
- /*
- * Print statistics (only if ethernet is running),
- * then zero all the stats fields in memory
- */
- if (port_private->eth_running == MAGIC_ETH_RUNNING) {
- port_private->eth_running = 0;
- mv64360_eth_print_stat (dev);
- }
- memset (port_private->stats, 0, sizeof (struct net_device_stats));
-#endif
- DP (printf ("\nEthernet stopped ... \n"));
- return 0;
-}
-
-
-/**********************************************************************
- * mv64360_eth_start_xmit
- *
- * This function is queues a packet in the Tx descriptor for
- * required port.
- *
- * Input : skb - a pointer to socket buffer
- * dev - a pointer to the required port
- *
- * Output : zero upon success
- **********************************************************************/
-
-int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
- int dataSize)
-{
- ETH_PORT_INFO *ethernet_private;
- struct mv64360_eth_priv *port_private;
- PKT_INFO pkt_info;
- ETH_FUNC_RET_STATUS status;
- struct net_device_stats *stats;
- ETH_FUNC_RET_STATUS release_result;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64360_eth_priv *) ethernet_private->port_private;
-
- stats = port_private->stats;
-
- /* Update packet info data structure */
- pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */
- pkt_info.byte_cnt = dataSize;
- pkt_info.buf_ptr = (unsigned int) dataPtr;
- pkt_info.return_info = 0;
-
- status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
- if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
- printf ("Error on transmitting packet ..");
- if (status == ETH_QUEUE_FULL)
- printf ("ETH Queue is full. \n");
- if (status == ETH_QUEUE_LAST_RESOURCE)
- printf ("ETH Queue: using last available resource. \n");
- goto error;
- }
-
- /* Update statistics and start of transmittion time */
- stats->tx_bytes += dataSize;
- stats->tx_packets++;
-
- /* Check if packet(s) is(are) transmitted correctly (release everything) */
- do {
- release_result =
- eth_tx_return_desc (ethernet_private, ETH_Q0,
- &pkt_info);
- switch (release_result) {
- case ETH_OK:
- DP (printf ("descriptor released\n"));
- if (pkt_info.cmd_sts & BIT0) {
- printf ("Error in TX\n");
- stats->tx_errors++;
-
- }
- break;
- case ETH_RETRY:
- DP (printf ("transmission still in process\n"));
- break;
-
- case ETH_ERROR:
- printf ("routine can not access Tx desc ring\n");
- break;
-
- case ETH_END_OF_JOB:
- DP (printf ("the routine has nothing to release\n"));
- break;
- default: /* should not happen */
- break;
- }
- } while (release_result == ETH_OK);
-
-
- return 0; /* success */
- error:
- return 1; /* Failed - higher layers will free the skb */
-}
-
-/**********************************************************************
- * mv64360_eth_receive
- *
- * This function is forward packets that are received from the port's
- * queues toward kernel core or FastRoute them to another interface.
- *
- * Input : dev - a pointer to the required interface
- * max - maximum number to receive (0 means unlimted)
- *
- * Output : number of served packets
- **********************************************************************/
-
-int mv64360_eth_receive (struct eth_device *dev)
-{
- ETH_PORT_INFO *ethernet_private;
- struct mv64360_eth_priv *port_private;
- PKT_INFO pkt_info;
- struct net_device_stats *stats;
-
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64360_eth_priv *) ethernet_private->port_private;
- stats = port_private->stats;
-
- while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
- ETH_OK)) {
-
-#ifdef DEBUG_MV_ETH
- if (pkt_info.byte_cnt != 0) {
- printf ("%s: Received %d byte Packet @ 0x%x\n",
- __FUNCTION__, pkt_info.byte_cnt,
- pkt_info.buf_ptr);
- }
-#endif
- /* Update statistics. Note byte count includes 4 byte CRC count */
- stats->rx_packets++;
- stats->rx_bytes += pkt_info.byte_cnt;
-
- /*
- * In case received a packet without first / last bits on OR the error
- * summary bit is on, the packets needs to be dropeed.
- */
- if (((pkt_info.
- cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
- (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
- || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
- stats->rx_dropped++;
-
- printf ("Received packet spread on multiple descriptors\n");
-
- /* Is this caused by an error ? */
- if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
- stats->rx_errors++;
- }
-
- /* free these descriptors again without forwarding them to the higher layers */
- pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
- pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
-
- if (eth_rx_return_buff
- (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
- printf ("Error while returning the RX Desc to Ring\n");
- } else {
- DP (printf ("RX Desc returned to Ring\n"));
- }
- /* /free these descriptors again */
- } else {
-
-/* !!! call higher layer processing */
-#ifdef DEBUG_MV_ETH
- printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
-#endif
- /* let the upper layer handle the packet */
- NetReceive ((uchar *) pkt_info.buf_ptr,
- (int) pkt_info.byte_cnt);
-
-/* **************************************************************** */
-/* free descriptor */
- pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
- pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
- DP (printf
- ("RX: pkt_info.buf_ptr = %x\n",
- pkt_info.buf_ptr));
- if (eth_rx_return_buff
- (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
- printf ("Error while returning the RX Desc to Ring\n");
- } else {
- DP (printf ("RX Desc returned to Ring\n"));
- }
-
-/* **************************************************************** */
-
- }
- }
- mv64360_eth_get_stats (dev); /* update statistics */
- return 1;
-}
-
-/**********************************************************************
- * mv64360_eth_get_stats
- *
- * Returns a pointer to the interface statistics.
- *
- * Input : dev - a pointer to the required interface
- *
- * Output : a pointer to the interface's statistics
- **********************************************************************/
-
-static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev)
-{
- ETH_PORT_INFO *ethernet_private;
- struct mv64360_eth_priv *port_private;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64360_eth_priv *) ethernet_private->port_private;
-
- mv64360_eth_update_stat (dev);
-
- return port_private->stats;
-}
-
-
-/**********************************************************************
- * mv64360_eth_update_stat
- *
- * Update the statistics structure in the private data structure
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- **********************************************************************/
-
-static void mv64360_eth_update_stat (struct eth_device *dev)
-{
- ETH_PORT_INFO *ethernet_private;
- struct mv64360_eth_priv *port_private;
- struct net_device_stats *stats;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64360_eth_priv *) ethernet_private->port_private;
- stats = port_private->stats;
-
- /* These are false updates */
- stats->rx_packets += (unsigned long)
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_GOOD_FRAMES_RECEIVED);
- stats->tx_packets += (unsigned long)
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_GOOD_FRAMES_SENT);
- stats->rx_bytes += (unsigned long)
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
- /*
- * Ideally this should be as follows -
- *
- * stats->rx_bytes += stats->rx_bytes +
- * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
- * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
- *
- * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
- * is just a dummy read for proper work of the GigE port
- */
- (void)eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
- stats->tx_bytes += (unsigned long)
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_GOOD_OCTETS_SENT_LOW);
- (void)eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_GOOD_OCTETS_SENT_HIGH);
- stats->rx_errors += (unsigned long)
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_MAC_RECEIVE_ERROR);
-
- /* Rx dropped is for received packet with CRC error */
- stats->rx_dropped +=
- (unsigned long) eth_read_mib_counter (ethernet_private->
- port_num,
- ETH_MIB_BAD_CRC_EVENT);
- stats->multicast += (unsigned long)
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_MULTICAST_FRAMES_RECEIVED);
- stats->collisions +=
- (unsigned long) eth_read_mib_counter (ethernet_private->
- port_num,
- ETH_MIB_COLLISION) +
- (unsigned long) eth_read_mib_counter (ethernet_private->
- port_num,
- ETH_MIB_LATE_COLLISION);
- /* detailed rx errors */
- stats->rx_length_errors +=
- (unsigned long) eth_read_mib_counter (ethernet_private->
- port_num,
- ETH_MIB_UNDERSIZE_RECEIVED)
- +
- (unsigned long) eth_read_mib_counter (ethernet_private->
- port_num,
- ETH_MIB_OVERSIZE_RECEIVED);
- /* detailed tx errors */
-}
-
-#ifndef UPDATE_STATS_BY_SOFTWARE
-/**********************************************************************
- * mv64360_eth_print_stat
- *
- * Update the statistics structure in the private data structure
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- **********************************************************************/
-
-static void mv64360_eth_print_stat (struct eth_device *dev)
-{
- ETH_PORT_INFO *ethernet_private;
- struct mv64360_eth_priv *port_private;
- struct net_device_stats *stats;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64360_eth_priv *) ethernet_private->port_private;
- stats = port_private->stats;
-
- /* These are false updates */
- printf ("\n### Network statistics: ###\n");
- printf ("--------------------------\n");
- printf (" Packets received: %ld\n", stats->rx_packets);
- printf (" Packets send: %ld\n", stats->tx_packets);
- printf (" Received bytes: %ld\n", stats->rx_bytes);
- printf (" Send bytes: %ld\n", stats->tx_bytes);
- if (stats->rx_errors != 0)
- printf (" Rx Errors: %ld\n",
- stats->rx_errors);
- if (stats->rx_dropped != 0)
- printf (" Rx dropped (CRC Errors): %ld\n",
- stats->rx_dropped);
- if (stats->multicast != 0)
- printf (" Rx mulicast frames: %ld\n",
- stats->multicast);
- if (stats->collisions != 0)
- printf (" No. of collisions: %ld\n",
- stats->collisions);
- if (stats->rx_length_errors != 0)
- printf (" Rx length errors: %ld\n",
- stats->rx_length_errors);
-}
-#endif
-
-/**************************************************************************
- *network_start - Network Kick Off Routine UBoot
- *Inputs :
- *Outputs :
- **************************************************************************/
-
-bool db64360_eth_start (struct eth_device *dev)
-{
- return (mv64360_eth_open (dev)); /* calls real open */
-}
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-* The second part is the low level driver of the gigE ethernet ports. *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-/*
- * based on Linux code
- * arch/powerpc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- */
-
-/********************************************************************************
- * Marvell's Gigabit Ethernet controller low level driver
- *
- * DESCRIPTION:
- * This file introduce low level API to Marvell's Gigabit Ethernet
- * controller. This Gigabit Ethernet Controller driver API controls
- * 1) Operations (i.e. port init, start, reset etc').
- * 2) Data flow (i.e. port send, receive etc').
- * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
- * struct.
- * This struct includes user configuration information as well as
- * driver internal data needed for its operations.
- *
- * Supported Features:
- * - This low level driver is OS independent. Allocating memory for
- * the descriptor rings and buffers are not within the scope of
- * this driver.
- * - The user is free from Rx/Tx queue managing.
- * - This low level driver introduce functionality API that enable
- * the to operate Marvell's Gigabit Ethernet Controller in a
- * convenient way.
- * - Simple Gigabit Ethernet port operation API.
- * - Simple Gigabit Ethernet port data flow API.
- * - Data flow and operation API support per queue functionality.
- * - Support cached descriptors for better performance.
- * - Enable access to all four DRAM banks and internal SRAM memory
- * spaces.
- * - PHY access and control API.
- * - Port control register configuration API.
- * - Full control over Unicast and Multicast MAC configurations.
- *
- * Operation flow:
- *
- * Initialization phase
- * This phase complete the initialization of the ETH_PORT_INFO
- * struct.
- * User information regarding port configuration has to be set
- * prior to calling the port initialization routine. For example,
- * the user has to assign the port_phy_addr field which is board
- * depended parameter.
- * In this phase any port Tx/Rx activity is halted, MIB counters
- * are cleared, PHY address is set according to user parameter and
- * access to DRAM and internal SRAM memory spaces.
- *
- * Driver ring initialization
- * Allocating memory for the descriptor rings and buffers is not
- * within the scope of this driver. Thus, the user is required to
- * allocate memory for the descriptors ring and buffers. Those
- * memory parameters are used by the Rx and Tx ring initialization
- * routines in order to curve the descriptor linked list in a form
- * of a ring.
- * Note: Pay special attention to alignment issues when using
- * cached descriptors/buffers. In this phase the driver store
- * information in the ETH_PORT_INFO struct regarding each queue
- * ring.
- *
- * Driver start
- * This phase prepares the Ethernet port for Rx and Tx activity.
- * It uses the information stored in the ETH_PORT_INFO struct to
- * initialize the various port registers.
- *
- * Data flow:
- * All packet references to/from the driver are done using PKT_INFO
- * struct.
- * This struct is a unified struct used with Rx and Tx operations.
- * This way the user is not required to be familiar with neither
- * Tx nor Rx descriptors structures.
- * The driver's descriptors rings are management by indexes.
- * Those indexes controls the ring resources and used to indicate
- * a SW resource error:
- * 'current'
- * This index points to the current available resource for use. For
- * example in Rx process this index will point to the descriptor
- * that will be passed to the user upon calling the receive routine.
- * In Tx process, this index will point to the descriptor
- * that will be assigned with the user packet info and transmitted.
- * 'used'
- * This index points to the descriptor that need to restore its
- * resources. For example in Rx process, using the Rx buffer return
- * API will attach the buffer returned in packet info to the
- * descriptor pointed by 'used'. In Tx process, using the Tx
- * descriptor return will merely return the user packet info with
- * the command status of the transmitted buffer pointed by the
- * 'used' index. Nevertheless, it is essential to use this routine
- * to update the 'used' index.
- * 'first'
- * This index supports Tx Scatter-Gather. It points to the first
- * descriptor of a packet assembled of multiple buffers. For example
- * when in middle of Such packet we have a Tx resource error the
- * 'curr' index get the value of 'first' to indicate that the ring
- * returned to its state before trying to transmit this packet.
- *
- * Receive operation:
- * The eth_port_receive API set the packet information struct,
- * passed by the caller, with received information from the
- * 'current' SDMA descriptor.
- * It is the user responsibility to return this resource back
- * to the Rx descriptor ring to enable the reuse of this source.
- * Return Rx resource is done using the eth_rx_return_buff API.
- *
- * Transmit operation:
- * The eth_port_send API supports Scatter-Gather which enables to
- * send a packet spanned over multiple buffers. This means that
- * for each packet info structure given by the user and put into
- * the Tx descriptors ring, will be transmitted only if the 'LAST'
- * bit will be set in the packet info command status field. This
- * API also consider restriction regarding buffer alignments and
- * sizes.
- * The user must return a Tx resource after ensuring the buffer
- * has been transmitted to enable the Tx ring indexes to update.
- *
- * BOARD LAYOUT
- * This device is on-board. No jumper diagram is necessary.
- *
- * EXTERNAL INTERFACE
- *
- * Prior to calling the initialization routine eth_port_init() the user
- * must set the following fields under ETH_PORT_INFO struct:
- * port_num User Ethernet port number.
- * port_phy_addr User PHY address of Ethernet port.
- * port_mac_addr[6] User defined port MAC address.
- * port_config User port configuration value.
- * port_config_extend User port config extend value.
- * port_sdma_config User port SDMA config value.
- * port_serial_control User port serial control value.
- * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr.
- * *port_private User scratch pad for user specific data structures.
- *
- * This driver introduce a set of default values:
- * PORT_CONFIG_VALUE Default port configuration value
- * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value
- * PORT_SDMA_CONFIG_VALUE Default sdma control value
- * PORT_SERIAL_CONTROL_VALUE Default port serial control value
- *
- * This driver data flow is done using the PKT_INFO struct which is
- * a unified struct for Rx and Tx operations:
- * byte_cnt Tx/Rx descriptor buffer byte count.
- * l4i_chk CPU provided TCP Checksum. For Tx operation only.
- * cmd_sts Tx/Rx descriptor command status.
- * buf_ptr Tx/Rx descriptor buffer pointer.
- * return_info Tx/Rx user resource return information.
- *
- *
- * EXTERNAL SUPPORT REQUIREMENTS
- *
- * This driver requires the following external support:
- *
- * D_CACHE_FLUSH_LINE (address, address offset)
- *
- * This macro applies assembly code to flush and invalidate cache
- * line.
- * address - address base.
- * address offset - address offset
- *
- *
- * CPU_PIPE_FLUSH
- *
- * This macro applies assembly code to flush the CPU pipeline.
- *
- *******************************************************************************/
-/* includes */
-
-/* defines */
-/* SDMA command macros */
-#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
- MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
-
-#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
- MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
- (1 << (8 + tx_queue)))
-
-#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
-MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
-
-#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
-MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
-
-#define CURR_RFD_GET(p_curr_desc, queue) \
- ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
-
-#define CURR_RFD_SET(p_curr_desc, queue) \
- (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
-
-#define USED_RFD_GET(p_used_desc, queue) \
- ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
-
-#define USED_RFD_SET(p_used_desc, queue)\
-(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
-
-
-#define CURR_TFD_GET(p_curr_desc, queue) \
- ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
-
-#define CURR_TFD_SET(p_curr_desc, queue) \
- (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
-
-#define USED_TFD_GET(p_used_desc, queue) \
- ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
-
-#define USED_TFD_SET(p_used_desc, queue) \
- (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
-
-#define FIRST_TFD_GET(p_first_desc, queue) \
- ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
-
-#define FIRST_TFD_SET(p_first_desc, queue) \
- (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
-
-
-/* Macros that save access to desc in order to find next desc pointer */
-#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
-
-#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
-
-#define LINK_UP_TIMEOUT 100000
-#define PHY_BUSY_TIMEOUT 10000000
-
-/* locals */
-
-/* PHY routines */
-static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
-static int ethernet_phy_get (ETH_PORT eth_port_num);
-
-/* Ethernet Port routines */
-static void eth_set_access_control (ETH_PORT eth_port_num,
- ETH_WIN_PARAM * param);
-static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
- ETH_QUEUE queue, int option);
-#if 0 /* FIXME */
-static bool eth_port_smc_addr (ETH_PORT eth_port_num,
- unsigned char mc_byte,
- ETH_QUEUE queue, int option);
-static bool eth_port_omc_addr (ETH_PORT eth_port_num,
- unsigned char crc8,
- ETH_QUEUE queue, int option);
-#endif
-
-static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
- int byte_count);
-
-void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
-
-
-typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
-u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
-{
- u32 result = 0;
- u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
-
- if (enable & (1 << bank))
- return 0;
- if (bank == BANK0)
- result = MV_REG_READ (MV64360_CS_0_BASE_ADDR);
- if (bank == BANK1)
- result = MV_REG_READ (MV64360_CS_1_BASE_ADDR);
- if (bank == BANK2)
- result = MV_REG_READ (MV64360_CS_2_BASE_ADDR);
- if (bank == BANK3)
- result = MV_REG_READ (MV64360_CS_3_BASE_ADDR);
- result &= 0x0000ffff;
- result = result << 16;
- return result;
-}
-
-u32 mv_get_dram_bank_size (MEMORY_BANK bank)
-{
- u32 result = 0;
- u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
-
- if (enable & (1 << bank))
- return 0;
- if (bank == BANK0)
- result = MV_REG_READ (MV64360_CS_0_SIZE);
- if (bank == BANK1)
- result = MV_REG_READ (MV64360_CS_1_SIZE);
- if (bank == BANK2)
- result = MV_REG_READ (MV64360_CS_2_SIZE);
- if (bank == BANK3)
- result = MV_REG_READ (MV64360_CS_3_SIZE);
- result += 1;
- result &= 0x0000ffff;
- result = result << 16;
- return result;
-}
-
-u32 mv_get_internal_sram_base (void)
-{
- u32 result;
-
- result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR);
- result &= 0x0000ffff;
- result = result << 16;
- return result;
-}
-
-/*******************************************************************************
-* eth_port_init - Initialize the Ethernet port driver
-*
-* DESCRIPTION:
-* This function prepares the ethernet port to start its activity:
-* 1) Completes the ethernet port driver struct initialization toward port
-* start routine.
-* 2) Resets the device to a quiescent state in case of warm reboot.
-* 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
-* 4) Clean MAC tables. The reset status of those tables is unknown.
-* 5) Set PHY address.
-* Note: Call this routine prior to eth_port_start routine and after setting
-* user values in the user fields of Ethernet port control struct (i.e.
-* port_phy_addr).
-*
-* INPUT:
-* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
-*
-* OUTPUT:
-* See description.
-*
-* RETURN:
-* None.
-*
-*******************************************************************************/
-static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
-{
- int queue;
- ETH_WIN_PARAM win_param;
-
- p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
- p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
- p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
- p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
-
- p_eth_port_ctrl->port_rx_queue_command = 0;
- p_eth_port_ctrl->port_tx_queue_command = 0;
-
- /* Zero out SW structs */
- for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
- CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
- USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
- p_eth_port_ctrl->rx_resource_err[queue] = false;
- }
-
- for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
- CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
- USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
- FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
- p_eth_port_ctrl->tx_resource_err[queue] = false;
- }
-
- eth_port_reset (p_eth_port_ctrl->port_num);
-
- /* Set access parameters for DRAM bank 0 */
- win_param.win = ETH_WIN0; /* Use Ethernet window 0 */
- win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
- win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
- win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
- win_param.high_addr = 0;
- /* Get bank base */
- win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
- win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */
- if (win_param.size == 0)
- win_param.enable = 0;
- else
- win_param.enable = 1; /* Enable the access */
- win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
-
- /* Set the access control for address window (EPAPR) READ & WRITE */
- eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
- /* Set access parameters for DRAM bank 1 */
- win_param.win = ETH_WIN1; /* Use Ethernet window 1 */
- win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
- win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
- win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
- win_param.high_addr = 0;
- /* Get bank base */
- win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
- win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */
- if (win_param.size == 0)
- win_param.enable = 0;
- else
- win_param.enable = 1; /* Enable the access */
- win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
-
- /* Set the access control for address window (EPAPR) READ & WRITE */
- eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
- /* Set access parameters for DRAM bank 2 */
- win_param.win = ETH_WIN2; /* Use Ethernet window 2 */
- win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
- win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
- win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
- win_param.high_addr = 0;
- /* Get bank base */
- win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
- win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */
- if (win_param.size == 0)
- win_param.enable = 0;
- else
- win_param.enable = 1; /* Enable the access */
- win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
-
- /* Set the access control for address window (EPAPR) READ & WRITE */
- eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
- /* Set access parameters for DRAM bank 3 */
- win_param.win = ETH_WIN3; /* Use Ethernet window 3 */
- win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
- win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
- win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
- win_param.high_addr = 0;
- /* Get bank base */
- win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
- win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */
- if (win_param.size == 0)
- win_param.enable = 0;
- else
- win_param.enable = 1; /* Enable the access */
- win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
-
- /* Set the access control for address window (EPAPR) READ & WRITE */
- eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
- /* Set access parameters for Internal SRAM */
- win_param.win = ETH_WIN4; /* Use Ethernet window 0 */
- win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */
- win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
- win_param.high_addr = 0;
- win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */
- win_param.size = MV64360_INTERNAL_SRAM_SIZE; /* Get bank size */
- win_param.enable = 1; /* Enable the access */
- win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
-
- /* Set the access control for address window (EPAPR) READ & WRITE */
- eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
- eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
-
- ethernet_phy_set (p_eth_port_ctrl->port_num,
- p_eth_port_ctrl->port_phy_addr);
-
- return;
-
-}
-
-/*******************************************************************************
-* eth_port_start - Start the Ethernet port activity.
-*
-* DESCRIPTION:
-* This routine prepares the Ethernet port for Rx and Tx activity:
-* 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
-* has been initialized a descriptor's ring (using ether_init_tx_desc_ring
-* for Tx and ether_init_rx_desc_ring for Rx)
-* 2. Initialize and enable the Ethernet configuration port by writing to
-* the port's configuration and command registers.
-* 3. Initialize and enable the SDMA by writing to the SDMA's
-* configuration and command registers.
-* After completing these steps, the ethernet port SDMA can starts to
-* perform Rx and Tx activities.
-*
-* Note: Each Rx and Tx queue descriptor's list must be initialized prior
-* to calling this function (use ether_init_tx_desc_ring for Tx queues and
-* ether_init_rx_desc_ring for Rx queues).
-*
-* INPUT:
-* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
-*
-* OUTPUT:
-* Ethernet port is ready to receive and transmit.
-*
-* RETURN:
-* false if the port PHY is not up.
-* true otherwise.
-*
-*******************************************************************************/
-static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
-{
- int queue;
- volatile ETH_TX_DESC *p_tx_curr_desc;
- volatile ETH_RX_DESC *p_rx_curr_desc;
- unsigned int phy_reg_data;
- ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
-
-
- /* Assignment of Tx CTRP of given queue */
- for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
- CURR_TFD_GET (p_tx_curr_desc, queue);
- MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
- (eth_port_num)
- + (4 * queue)),
- ((unsigned int) p_tx_curr_desc));
-
- }
-
- /* Assignment of Rx CRDP of given queue */
- for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
- CURR_RFD_GET (p_rx_curr_desc, queue);
- MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
- (eth_port_num)
- + (4 * queue)),
- ((unsigned int) p_rx_curr_desc));
-
- if (p_rx_curr_desc != NULL)
- /* Add the assigned Ethernet address to the port's address table */
- eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
- p_eth_port_ctrl->port_mac_addr,
- queue);
- }
-
- /* Assign port configuration and command. */
- MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
- p_eth_port_ctrl->port_config);
-
- MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
- p_eth_port_ctrl->port_config_extend);
-
- MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
- p_eth_port_ctrl->port_serial_control);
-
- MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
- ETH_SERIAL_PORT_ENABLE);
-
- /* Assign port SDMA configuration */
- MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
- p_eth_port_ctrl->port_sdma_config);
-
- MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
- (eth_port_num), 0x3fffffff);
- MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
- (eth_port_num), 0x03fffcff);
- /* Turn off the port/queue bandwidth limitation */
- MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
-
- /* Enable port Rx. */
- MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
- p_eth_port_ctrl->port_rx_queue_command);
-
- /* Check if link is up */
- eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
-
- if (!(phy_reg_data & 0x20))
- return false;
-
- return true;
-}
-
-/*******************************************************************************
-* eth_port_uc_addr_set - This function Set the port Unicast address.
-*
-* DESCRIPTION:
-* This function Set the port Ethernet MAC address.
-*
-* INPUT:
-* ETH_PORT eth_port_num Port number.
-* char * p_addr Address to be set
-* ETH_QUEUE queue Rx queue number for this MAC address.
-*
-* OUTPUT:
-* Set MAC address low and high registers. also calls eth_port_uc_addr()
-* To set the unicast table with the proper information.
-*
-* RETURN:
-* N/A.
-*
-*******************************************************************************/
-static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
- unsigned char *p_addr, ETH_QUEUE queue)
-{
- unsigned int mac_h;
- unsigned int mac_l;
-
- mac_l = (p_addr[4] << 8) | (p_addr[5]);
- mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
- (p_addr[2] << 8) | (p_addr[3] << 0);
-
- MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
- MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
-
- /* Accept frames of this address */
- eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
-
- return;
-}
-
-/*******************************************************************************
-* eth_port_uc_addr - This function Set the port unicast address table
-*
-* DESCRIPTION:
-* This function locates the proper entry in the Unicast table for the
-* specified MAC nibble and sets its properties according to function
-* parameters.
-*
-* INPUT:
-* ETH_PORT eth_port_num Port number.
-* unsigned char uc_nibble Unicast MAC Address last nibble.
-* ETH_QUEUE queue Rx queue number for this MAC address.
-* int option 0 = Add, 1 = remove address.
-*
-* OUTPUT:
-* This function add/removes MAC addresses from the port unicast address
-* table.
-*
-* RETURN:
-* true is output succeeded.
-* false if option parameter is invalid.
-*
-*******************************************************************************/
-static bool eth_port_uc_addr (ETH_PORT eth_port_num,
- unsigned char uc_nibble,
- ETH_QUEUE queue, int option)
-{
- unsigned int unicast_reg;
- unsigned int tbl_offset;
- unsigned int reg_offset;
-
- /* Locate the Unicast table entry */
- uc_nibble = (0xf & uc_nibble);
- tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
- reg_offset = uc_nibble % 4; /* Entry offset within the above register */
-
- switch (option) {
- case REJECT_MAC_ADDR:
- /* Clear accepts frame bit at specified unicast DA table entry */
- unicast_reg =
- MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
- (eth_port_num)
- + tbl_offset));
-
- unicast_reg &= (0x0E << (8 * reg_offset));
-
- MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
- (eth_port_num)
- + tbl_offset), unicast_reg);
- break;
-
- case ACCEPT_MAC_ADDR:
- /* Set accepts frame bit at unicast DA filter table entry */
- unicast_reg =
- MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
- (eth_port_num)
- + tbl_offset));
-
- unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
-
- MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
- (eth_port_num)
- + tbl_offset), unicast_reg);
-
- break;
-
- default:
- return false;
- }
- return true;
-}
-
-#if 0 /* FIXME */
-/*******************************************************************************
-* eth_port_mc_addr - Multicast address settings.
-*
-* DESCRIPTION:
-* This API controls the MV device MAC multicast support.
-* The MV device supports multicast using two tables:
-* 1) Special Multicast Table for MAC addresses of the form
-* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
-* The MAC DA[7:0] bits are used as a pointer to the Special Multicast
-* Table entries in the DA-Filter table.
-* In this case, the function calls eth_port_smc_addr() routine to set the
-* Special Multicast Table.
-* 2) Other Multicast Table for multicast of another type. A CRC-8bit
-* is used as an index to the Other Multicast Table entries in the
-* DA-Filter table.
-* In this case, the function calculates the CRC-8bit value and calls
-* eth_port_omc_addr() routine to set the Other Multicast Table.
-* INPUT:
-* ETH_PORT eth_port_num Port number.
-* unsigned char *p_addr Unicast MAC Address.
-* ETH_QUEUE queue Rx queue number for this MAC address.
-* int option 0 = Add, 1 = remove address.
-*
-* OUTPUT:
-* See description.
-*
-* RETURN:
-* true is output succeeded.
-* false if add_address_table_entry( ) failed.
-*
-*******************************************************************************/
-static void eth_port_mc_addr (ETH_PORT eth_port_num,
- unsigned char *p_addr,
- ETH_QUEUE queue, int option)
-{
- unsigned int mac_h;
- unsigned int mac_l;
- unsigned char crc_result = 0;
- int mac_array[48];
- int crc[8];
- int i;
-
-
- if ((p_addr[0] == 0x01) &&
- (p_addr[1] == 0x00) &&
- (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00))
-
- eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
- else {
- /* Calculate CRC-8 out of the given address */
- mac_h = (p_addr[0] << 8) | (p_addr[1]);
- mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
- (p_addr[4] << 8) | (p_addr[5] << 0);
-
- for (i = 0; i < 32; i++)
- mac_array[i] = (mac_l >> i) & 0x1;
- for (i = 32; i < 48; i++)
- mac_array[i] = (mac_h >> (i - 32)) & 0x1;
-
-
- crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
- mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
- mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
- mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
- mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
- mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
- mac_array[6] ^ mac_array[0];
-
- crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
- mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
- mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
- mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
- mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
- mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
- mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
- mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
- mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
- mac_array[0];
-
- crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
- mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
- mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
- mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
- mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
- mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
- mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
- mac_array[2] ^ mac_array[1] ^ mac_array[0];
-
- crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
- mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
- mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
- mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
- mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
- mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
- mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
- mac_array[2] ^ mac_array[1];
-
- crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
- mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
- mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
- mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
- mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
- mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
- mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
- mac_array[2];
-
- crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
- mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
- mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
- mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
- mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
- mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
- mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
- mac_array[3];
-
- crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
- mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
- mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
- mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
- mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
- mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
- mac_array[6] ^ mac_array[5] ^ mac_array[4];
-
- crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
- mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
- mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
- mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
- mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
- mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
- mac_array[6] ^ mac_array[5];
-
- for (i = 0; i < 8; i++)
- crc_result = crc_result | (crc[i] << i);
-
- eth_port_omc_addr (eth_port_num, crc_result, queue, option);
- }
- return;
-}
-
-/*******************************************************************************
-* eth_port_smc_addr - Special Multicast address settings.
-*
-* DESCRIPTION:
-* This routine controls the MV device special MAC multicast support.
-* The Special Multicast Table for MAC addresses supports MAC of the form
-* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
-* The MAC DA[7:0] bits are used as a pointer to the Special Multicast
-* Table entries in the DA-Filter table.
-* This function set the Special Multicast Table appropriate entry
-* according to the argument given.
-*
-* INPUT:
-* ETH_PORT eth_port_num Port number.
-* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits).
-* ETH_QUEUE queue Rx queue number for this MAC address.
-* int option 0 = Add, 1 = remove address.
-*
-* OUTPUT:
-* See description.
-*
-* RETURN:
-* true is output succeeded.
-* false if option parameter is invalid.
-*
-*******************************************************************************/
-static bool eth_port_smc_addr (ETH_PORT eth_port_num,
- unsigned char mc_byte,
- ETH_QUEUE queue, int option)
-{
- unsigned int smc_table_reg;
- unsigned int tbl_offset;
- unsigned int reg_offset;
-
- /* Locate the SMC table entry */
- tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */
- reg_offset = mc_byte % 4; /* Entry offset within the above register */
- queue &= 0x7;
-
- switch (option) {
- case REJECT_MAC_ADDR:
- /* Clear accepts frame bit at specified Special DA table entry */
- smc_table_reg =
- MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
- smc_table_reg &= (0x0E << (8 * reg_offset));
-
- MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
- break;
-
- case ACCEPT_MAC_ADDR:
- /* Set accepts frame bit at specified Special DA table entry */
- smc_table_reg =
- MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
- smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
-
- MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
- break;
-
- default:
- return false;
- }
- return true;
-}
-
-/*******************************************************************************
-* eth_port_omc_addr - Multicast address settings.
-*
-* DESCRIPTION:
-* This routine controls the MV device Other MAC multicast support.
-* The Other Multicast Table is used for multicast of another type.
-* A CRC-8bit is used as an index to the Other Multicast Table entries
-* in the DA-Filter table.
-* The function gets the CRC-8bit value from the calling routine and
-* set the Other Multicast Table appropriate entry according to the
-* CRC-8 argument given.
-*
-* INPUT:
-* ETH_PORT eth_port_num Port number.
-* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
-* ETH_QUEUE queue Rx queue number for this MAC address.
-* int option 0 = Add, 1 = remove address.
-*
-* OUTPUT:
-* See description.
-*
-* RETURN:
-* true is output succeeded.
-* false if option parameter is invalid.
-*
-*******************************************************************************/
-static bool eth_port_omc_addr (ETH_PORT eth_port_num,
- unsigned char crc8,
- ETH_QUEUE queue, int option)
-{
- unsigned int omc_table_reg;
- unsigned int tbl_offset;
- unsigned int reg_offset;
-
- /* Locate the OMC table entry */
- tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
- reg_offset = crc8 % 4; /* Entry offset within the above register */
- queue &= 0x7;
-
- switch (option) {
- case REJECT_MAC_ADDR:
- /* Clear accepts frame bit at specified Other DA table entry */
- omc_table_reg =
- MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
- omc_table_reg &= (0x0E << (8 * reg_offset));
-
- MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
- break;
-
- case ACCEPT_MAC_ADDR:
- /* Set accepts frame bit at specified Other DA table entry */
- omc_table_reg =
- MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
- omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
-
- MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
- break;
-
- default:
- return false;
- }
- return true;
-}
-#endif
-
-/*******************************************************************************
-* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
-*
-* DESCRIPTION:
-* Go through all the DA filter tables (Unicast, Special Multicast & Other
-* Multicast) and set each entry to 0.
-*
-* INPUT:
-* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
-*
-* OUTPUT:
-* Multicast and Unicast packets are rejected.
-*
-* RETURN:
-* None.
-*
-*******************************************************************************/
-static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
-{
- int table_index;
-
- /* Clear DA filter unicast table (Ex_dFUT) */
- for (table_index = 0; table_index <= 0xC; table_index += 4)
- MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
- (eth_port_num) + table_index), 0);
-
- for (table_index = 0; table_index <= 0xFC; table_index += 4) {
- /* Clear DA filter special multicast table (Ex_dFSMT) */
- MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
- /* Clear DA filter other multicast table (Ex_dFOMT) */
- MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
- }
-}
-
-/*******************************************************************************
-* eth_clear_mib_counters - Clear all MIB counters
-*
-* DESCRIPTION:
-* This function clears all MIB counters of a specific ethernet port.
-* A read from the MIB counter will reset the counter.
-*
-* INPUT:
-* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
-*
-* OUTPUT:
-* After reading all MIB counters, the counters resets.
-*
-* RETURN:
-* MIB counter value.
-*
-*******************************************************************************/
-static void eth_clear_mib_counters (ETH_PORT eth_port_num)
-{
- int i;
-
- /* Perform dummy reads from MIB counters */
- for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
- i += 4) {
- (void)MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE
- (eth_port_num) + i));
- }
-
- return;
-}
-
-/*******************************************************************************
-* eth_read_mib_counter - Read a MIB counter
-*
-* DESCRIPTION:
-* This function reads a MIB counter of a specific ethernet port.
-* NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
-* following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
-* register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
-* ETH_MIB_GOOD_OCTETS_SENT_HIGH
-*
-* INPUT:
-* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
-* unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros).
-*
-* OUTPUT:
-* After reading the MIB counter, the counter resets.
-*
-* RETURN:
-* MIB counter value.
-*
-*******************************************************************************/
-unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
- unsigned int mib_offset)
-{
- return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num)
- + mib_offset));
-}
-
-/*******************************************************************************
-* ethernet_phy_set - Set the ethernet port PHY address.
-*
-* DESCRIPTION:
-* This routine set the ethernet port PHY address according to given
-* parameter.
-*
-* INPUT:
-* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
-*
-* OUTPUT:
-* Set PHY Address Register with given PHY address parameter.
-*
-* RETURN:
-* None.
-*
-*******************************************************************************/
-static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
-{
- unsigned int reg_data;
-
- reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
-
- reg_data &= ~(0x1F << (5 * eth_port_num));
- reg_data |= (phy_addr << (5 * eth_port_num));
-
- MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data);
-
- return;
-}
-
-/*******************************************************************************
- * ethernet_phy_get - Get the ethernet port PHY address.
- *
- * DESCRIPTION:
- * This routine returns the given ethernet port PHY address.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- * None.
- *
- * RETURN:
- * PHY address.
- *
- *******************************************************************************/
-static int ethernet_phy_get (ETH_PORT eth_port_num)
-{
- unsigned int reg_data;
-
- reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
-
- return ((reg_data >> (5 * eth_port_num)) & 0x1f);
-}
-
-/*******************************************************************************
- * ethernet_phy_reset - Reset Ethernet port PHY.
- *
- * DESCRIPTION:
- * This routine utilize the SMI interface to reset the ethernet port PHY.
- * The routine waits until the link is up again or link up is timeout.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- * The ethernet port PHY renew its link.
- *
- * RETURN:
- * None.
- *
-*******************************************************************************/
-static bool ethernet_phy_reset (ETH_PORT eth_port_num)
-{
- unsigned int time_out = 50;
- unsigned int phy_reg_data;
-
- /* Reset the PHY */
- eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
- phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
- eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
-
- /* Poll on the PHY LINK */
- do {
- eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
-
- if (time_out-- == 0)
- return false;
- }
- while (!(phy_reg_data & 0x20));
-
- return true;
-}
-
-/*******************************************************************************
- * eth_port_reset - Reset Ethernet port
- *
- * DESCRIPTION:
- * This routine resets the chip by aborting any SDMA engine activity and
- * clearing the MIB counters. The Receiver and the Transmit unit are in
- * idle state after this command is performed and the port is disabled.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- * Channel activity is halted.
- *
- * RETURN:
- * None.
- *
- *******************************************************************************/
-static void eth_port_reset (ETH_PORT eth_port_num)
-{
- unsigned int reg_data;
-
- /* Stop Tx port activity. Check port Tx activity. */
- reg_data =
- MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
- (eth_port_num));
-
- if (reg_data & 0xFF) {
- /* Issue stop command for active channels only */
- MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
- (eth_port_num), (reg_data << 8));
-
- /* Wait for all Tx activity to terminate. */
- do {
- /* Check port cause register that all Tx queues are stopped */
- reg_data =
- MV_REG_READ
- (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
- (eth_port_num));
- }
- while (reg_data & 0xFF);
- }
-
- /* Stop Rx port activity. Check port Rx activity. */
- reg_data =
- MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
- (eth_port_num));
-
- if (reg_data & 0xFF) {
- /* Issue stop command for active channels only */
- MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
- (eth_port_num), (reg_data << 8));
-
- /* Wait for all Rx activity to terminate. */
- do {
- /* Check port cause register that all Rx queues are stopped */
- reg_data =
- MV_REG_READ
- (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
- (eth_port_num));
- }
- while (reg_data & 0xFF);
- }
-
-
- /* Clear all MIB counters */
- eth_clear_mib_counters (eth_port_num);
-
- /* Reset the Enable bit in the Configuration Register */
- reg_data =
- MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG
- (eth_port_num));
- reg_data &= ~ETH_SERIAL_PORT_ENABLE;
- MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
- reg_data);
-
- return;
-}
-
-#if 0 /* Not needed here */
-/*******************************************************************************
- * ethernet_set_config_reg - Set specified bits in configuration register.
- *
- * DESCRIPTION:
- * This function sets specified bits in the given ethernet
- * configuration register.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- * unsigned int value 32 bit value.
- *
- * OUTPUT:
- * The set bits in the value parameter are set in the configuration
- * register.
- *
- * RETURN:
- * None.
- *
- *******************************************************************************/
-static void ethernet_set_config_reg (ETH_PORT eth_port_num,
- unsigned int value)
-{
- unsigned int eth_config_reg;
-
- eth_config_reg =
- MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num));
- eth_config_reg |= value;
- MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
- eth_config_reg);
-
- return;
-}
-#endif
-
-#if 0 /* FIXME */
-/*******************************************************************************
- * ethernet_reset_config_reg - Reset specified bits in configuration register.
- *
- * DESCRIPTION:
- * This function resets specified bits in the given Ethernet
- * configuration register.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- * unsigned int value 32 bit value.
- *
- * OUTPUT:
- * The set bits in the value parameter are reset in the configuration
- * register.
- *
- * RETURN:
- * None.
- *
- *******************************************************************************/
-static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
- unsigned int value)
-{
- unsigned int eth_config_reg;
-
- eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
- (eth_port_num));
- eth_config_reg &= ~value;
- MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
- eth_config_reg);
-
- return;
-}
-#endif
-
-#if 0 /* Not needed here */
-/*******************************************************************************
- * ethernet_get_config_reg - Get the port configuration register
- *
- * DESCRIPTION:
- * This function returns the configuration register value of the given
- * ethernet port.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- * None.
- *
- * RETURN:
- * Port configuration register value.
- *
- *******************************************************************************/
-static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
-{
- unsigned int eth_config_reg;
-
- eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
- (eth_port_num));
- return eth_config_reg;
-}
-
-#endif
-
-/*******************************************************************************
- * eth_port_read_smi_reg - Read PHY registers
- *
- * DESCRIPTION:
- * This routine utilize the SMI interface to interact with the PHY in
- * order to perform PHY register read.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- * unsigned int phy_reg PHY register address offset.
- * unsigned int *value Register value buffer.
- *
- * OUTPUT:
- * Write the value of a specified PHY register into given buffer.
- *
- * RETURN:
- * false if the PHY is busy or read data is not in valid state.
- * true otherwise.
- *
- *******************************************************************************/
-static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
- unsigned int phy_reg, unsigned int *value)
-{
- unsigned int reg_value;
- unsigned int time_out = PHY_BUSY_TIMEOUT;
- int phy_addr;
-
- phy_addr = ethernet_phy_get (eth_port_num);
-/* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/
-
- /* first check that it is not busy */
- do {
- reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
- if (time_out-- == 0) {
- return false;
- }
- }
- while (reg_value & ETH_SMI_BUSY);
-
- /* not busy */
-
- MV_REG_WRITE (MV64360_ETH_SMI_REG,
- (phy_addr << 16) | (phy_reg << 21) |
- ETH_SMI_OPCODE_READ);
-
- time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */
-
- do {
- reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
- if (time_out-- == 0) {
- return false;
- }
- }
- while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */
-
- /* Wait for the data to update in the SMI register */
-#define PHY_UPDATE_TIMEOUT 10000
- for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
-
- reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
-
- *value = reg_value & 0xffff;
-
- return true;
-}
-
-/*******************************************************************************
- * eth_port_write_smi_reg - Write to PHY registers
- *
- * DESCRIPTION:
- * This routine utilize the SMI interface to interact with the PHY in
- * order to perform writes to PHY registers.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- * unsigned int phy_reg PHY register address offset.
- * unsigned int value Register value.
- *
- * OUTPUT:
- * Write the given value to the specified PHY register.
- *
- * RETURN:
- * false if the PHY is busy.
- * true otherwise.
- *
- *******************************************************************************/
-static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
- unsigned int phy_reg, unsigned int value)
-{
- unsigned int reg_value;
- unsigned int time_out = PHY_BUSY_TIMEOUT;
- int phy_addr;
-
- phy_addr = ethernet_phy_get (eth_port_num);
-
- /* first check that it is not busy */
- do {
- reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
- if (time_out-- == 0) {
- return false;
- }
- }
- while (reg_value & ETH_SMI_BUSY);
-
- /* not busy */
- MV_REG_WRITE (MV64360_ETH_SMI_REG,
- (phy_addr << 16) | (phy_reg << 21) |
- ETH_SMI_OPCODE_WRITE | (value & 0xffff));
- return true;
-}
-
-/*******************************************************************************
- * eth_set_access_control - Config address decode parameters for Ethernet unit
- *
- * DESCRIPTION:
- * This function configures the address decode parameters for the Gigabit
- * Ethernet Controller according the given parameters struct.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- * ETH_WIN_PARAM *param Address decode parameter struct.
- *
- * OUTPUT:
- * An access window is opened using the given access parameters.
- *
- * RETURN:
- * None.
- *
- *******************************************************************************/
-static void eth_set_access_control (ETH_PORT eth_port_num,
- ETH_WIN_PARAM * param)
-{
- unsigned int access_prot_reg;
-
- /* Set access control register */
- access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG
- (eth_port_num));
- access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */
- access_prot_reg |= (param->access_ctrl << (param->win * 2));
- MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num),
- access_prot_reg);
-
- /* Set window Size reg (SR) */
- MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 +
- (ETH_SIZE_REG_GAP * param->win)),
- (((param->size / 0x10000) - 1) << 16));
-
- /* Set window Base address reg (BA) */
- MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
- (param->target | param->attributes | param->base_addr));
- /* High address remap reg (HARR) */
- if (param->win < 4)
- MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 +
- (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
- param->high_addr);
-
- /* Base address enable reg (BARER) */
- if (param->enable == 1)
- MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
- (1 << param->win));
- else
- MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
- (1 << param->win));
-}
-
-/*******************************************************************************
- * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
- *
- * DESCRIPTION:
- * This function prepares a Rx chained list of descriptors and packet
- * buffers in a form of a ring. The routine must be called after port
- * initialization routine and before port start routine.
- * The Ethernet SDMA engine uses CPU bus addresses to access the various
- * devices in the system (i.e. DRAM). This function uses the ethernet
- * struct 'virtual to physical' routine (set by the user) to set the ring
- * with physical addresses.
- *
- * INPUT:
- * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
- * ETH_QUEUE rx_queue Number of Rx queue.
- * int rx_desc_num Number of Rx descriptors
- * int rx_buff_size Size of Rx buffer
- * unsigned int rx_desc_base_addr Rx descriptors memory area base addr.
- * unsigned int rx_buff_base_addr Rx buffer memory area base addr.
- *
- * OUTPUT:
- * The routine updates the Ethernet port control struct with information
- * regarding the Rx descriptors and buffers.
- *
- * RETURN:
- * false if the given descriptors memory area is not aligned according to
- * Ethernet SDMA specifications.
- * true otherwise.
- *
- *******************************************************************************/
-static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
- ETH_QUEUE rx_queue,
- int rx_desc_num,
- int rx_buff_size,
- unsigned int rx_desc_base_addr,
- unsigned int rx_buff_base_addr)
-{
- ETH_RX_DESC *p_rx_desc;
- ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */
- unsigned int buffer_addr;
- int ix; /* a counter */
-
-
- p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
- p_rx_prev_desc = p_rx_desc;
- buffer_addr = rx_buff_base_addr;
-
- /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
- if (rx_buff_base_addr & 0xF)
- return false;
-
- /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */
- if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
- return false;
-
- /* Rx buffers must be 64-bit aligned. */
- if ((rx_buff_base_addr + rx_buff_size) & 0x7)
- return false;
-
- /* initialize the Rx descriptors ring */
- for (ix = 0; ix < rx_desc_num; ix++) {
- p_rx_desc->buf_size = rx_buff_size;
- p_rx_desc->byte_cnt = 0x0000;
- p_rx_desc->cmd_sts =
- ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
- p_rx_desc->next_desc_ptr =
- ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
- p_rx_desc->buf_ptr = buffer_addr;
- p_rx_desc->return_info = 0x00000000;
- D_CACHE_FLUSH_LINE (p_rx_desc, 0);
- buffer_addr += rx_buff_size;
- p_rx_prev_desc = p_rx_desc;
- p_rx_desc = (ETH_RX_DESC *)
- ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
- }
-
- /* Closing Rx descriptors ring */
- p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
- D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
-
- /* Save Rx desc pointer to driver struct. */
- CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
- USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
-
- p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
- (ETH_RX_DESC *) rx_desc_base_addr;
- p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
- rx_desc_num * RX_DESC_ALIGNED_SIZE;
-
- p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
-
- return true;
-}
-
-/*******************************************************************************
- * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
- *
- * DESCRIPTION:
- * This function prepares a Tx chained list of descriptors and packet
- * buffers in a form of a ring. The routine must be called after port
- * initialization routine and before port start routine.
- * The Ethernet SDMA engine uses CPU bus addresses to access the various
- * devices in the system (i.e. DRAM). This function uses the ethernet
- * struct 'virtual to physical' routine (set by the user) to set the ring
- * with physical addresses.
- *
- * INPUT:
- * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
- * ETH_QUEUE tx_queue Number of Tx queue.
- * int tx_desc_num Number of Tx descriptors
- * int tx_buff_size Size of Tx buffer
- * unsigned int tx_desc_base_addr Tx descriptors memory area base addr.
- * unsigned int tx_buff_base_addr Tx buffer memory area base addr.
- *
- * OUTPUT:
- * The routine updates the Ethernet port control struct with information
- * regarding the Tx descriptors and buffers.
- *
- * RETURN:
- * false if the given descriptors memory area is not aligned according to
- * Ethernet SDMA specifications.
- * true otherwise.
- *
- *******************************************************************************/
-static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
- ETH_QUEUE tx_queue,
- int tx_desc_num,
- int tx_buff_size,
- unsigned int tx_desc_base_addr,
- unsigned int tx_buff_base_addr)
-{
-
- ETH_TX_DESC *p_tx_desc;
- ETH_TX_DESC *p_tx_prev_desc;
- unsigned int buffer_addr;
- int ix; /* a counter */
-
-
- /* save the first desc pointer to link with the last descriptor */
- p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
- p_tx_prev_desc = p_tx_desc;
- buffer_addr = tx_buff_base_addr;
-
- /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
- if (tx_buff_base_addr & 0xF)
- return false;
-
- /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */
- if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
- || (tx_buff_size < TX_BUFFER_MIN_SIZE))
- return false;
-
- /* Initialize the Tx descriptors ring */
- for (ix = 0; ix < tx_desc_num; ix++) {
- p_tx_desc->byte_cnt = 0x0000;
- p_tx_desc->l4i_chk = 0x0000;
- p_tx_desc->cmd_sts = 0x00000000;
- p_tx_desc->next_desc_ptr =
- ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
-
- p_tx_desc->buf_ptr = buffer_addr;
- p_tx_desc->return_info = 0x00000000;
- D_CACHE_FLUSH_LINE (p_tx_desc, 0);
- buffer_addr += tx_buff_size;
- p_tx_prev_desc = p_tx_desc;
- p_tx_desc = (ETH_TX_DESC *)
- ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
-
- }
- /* Closing Tx descriptors ring */
- p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
- D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
- /* Set Tx desc pointer in driver struct. */
- CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
- USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
-
- /* Init Tx ring base and size parameters */
- p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
- (ETH_TX_DESC *) tx_desc_base_addr;
- p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
- (tx_desc_num * TX_DESC_ALIGNED_SIZE);
-
- /* Add the queue to the list of Tx queues of this port */
- p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
-
- return true;
-}
-
-/*******************************************************************************
- * eth_port_send - Send an Ethernet packet
- *
- * DESCRIPTION:
- * This routine send a given packet described by p_pktinfo parameter. It
- * supports transmitting of a packet spaned over multiple buffers. The
- * routine updates 'curr' and 'first' indexes according to the packet
- * segment passed to the routine. In case the packet segment is first,
- * the 'first' index is update. In any case, the 'curr' index is updated.
- * If the routine get into Tx resource error it assigns 'curr' index as
- * 'first'. This way the function can abort Tx process of multiple
- * descriptors per packet.
- *
- * INPUT:
- * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
- * ETH_QUEUE tx_queue Number of Tx queue.
- * PKT_INFO *p_pkt_info User packet buffer.
- *
- * OUTPUT:
- * Tx ring 'curr' and 'first' indexes are updated.
- *
- * RETURN:
- * ETH_QUEUE_FULL in case of Tx resource error.
- * ETH_ERROR in case the routine can not access Tx desc ring.
- * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
- * ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
- ETH_QUEUE tx_queue,
- PKT_INFO * p_pkt_info)
-{
- volatile ETH_TX_DESC *p_tx_desc_first;
- volatile ETH_TX_DESC *p_tx_desc_curr;
- volatile ETH_TX_DESC *p_tx_next_desc_curr;
- volatile ETH_TX_DESC *p_tx_desc_used;
- unsigned int command_status;
-
- /* Do not process Tx ring in case of Tx ring resource error */
- if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
- return ETH_QUEUE_FULL;
-
- /* Get the Tx Desc ring indexes */
- CURR_TFD_GET (p_tx_desc_curr, tx_queue);
- USED_TFD_GET (p_tx_desc_used, tx_queue);
-
- if (p_tx_desc_curr == NULL)
- return ETH_ERROR;
-
- /* The following parameters are used to save readings from memory */
- p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
- command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
-
- if (command_status & (ETH_TX_FIRST_DESC)) {
- /* Update first desc */
- FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
- p_tx_desc_first = p_tx_desc_curr;
- } else {
- FIRST_TFD_GET (p_tx_desc_first, tx_queue);
- command_status |= ETH_BUFFER_OWNED_BY_DMA;
- }
-
- /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
- /* boundary. We use the memory allocated for Tx descriptor. This memory */
- /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
- if (p_pkt_info->byte_cnt <= 8) {
- printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */
- return ETH_ERROR;
-
- p_tx_desc_curr->buf_ptr =
- (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
- eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
- p_pkt_info->byte_cnt);
- } else
- p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
-
- p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
- p_tx_desc_curr->return_info = p_pkt_info->return_info;
-
- if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
- /* Set last desc with DMA ownership and interrupt enable. */
- p_tx_desc_curr->cmd_sts = command_status |
- ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
-
- if (p_tx_desc_curr != p_tx_desc_first)
- p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
-
- /* Flush CPU pipe */
-
- D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
- D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
- CPU_PIPE_FLUSH;
-
- /* Apply send command */
- ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
-
- /* Finish Tx packet. Update first desc in case of Tx resource error */
- p_tx_desc_first = p_tx_next_desc_curr;
- FIRST_TFD_SET (p_tx_desc_first, tx_queue);
-
- } else {
- p_tx_desc_curr->cmd_sts = command_status;
- D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
- }
-
- /* Check for ring index overlap in the Tx desc ring */
- if (p_tx_next_desc_curr == p_tx_desc_used) {
- /* Update the current descriptor */
- CURR_TFD_SET (p_tx_desc_first, tx_queue);
-
- p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
- return ETH_QUEUE_LAST_RESOURCE;
- } else {
- /* Update the current descriptor */
- CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
- return ETH_OK;
- }
-}
-
-/*******************************************************************************
- * eth_tx_return_desc - Free all used Tx descriptors
- *
- * DESCRIPTION:
- * This routine returns the transmitted packet information to the caller.
- * It uses the 'first' index to support Tx desc return in case a transmit
- * of a packet spanned over multiple buffer still in process.
- * In case the Tx queue was in "resource error" condition, where there are
- * no available Tx resources, the function resets the resource error flag.
- *
- * INPUT:
- * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
- * ETH_QUEUE tx_queue Number of Tx queue.
- * PKT_INFO *p_pkt_info User packet buffer.
- *
- * OUTPUT:
- * Tx ring 'first' and 'used' indexes are updated.
- *
- * RETURN:
- * ETH_ERROR in case the routine can not access Tx desc ring.
- * ETH_RETRY in case there is transmission in process.
- * ETH_END_OF_JOB if the routine has nothing to release.
- * ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
- p_eth_port_ctrl,
- ETH_QUEUE tx_queue,
- PKT_INFO * p_pkt_info)
-{
- volatile ETH_TX_DESC *p_tx_desc_used = NULL;
- volatile ETH_TX_DESC *p_tx_desc_first = NULL;
- unsigned int command_status;
-
-
- /* Get the Tx Desc ring indexes */
- USED_TFD_GET (p_tx_desc_used, tx_queue);
- FIRST_TFD_GET (p_tx_desc_first, tx_queue);
-
-
- /* Sanity check */
- if (p_tx_desc_used == NULL)
- return ETH_ERROR;
-
- command_status = p_tx_desc_used->cmd_sts;
-
- /* Still transmitting... */
- if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
- D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
- return ETH_RETRY;
- }
-
- /* Stop release. About to overlap the current available Tx descriptor */
- if ((p_tx_desc_used == p_tx_desc_first) &&
- (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
- D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
- return ETH_END_OF_JOB;
- }
-
- /* Pass the packet information to the caller */
- p_pkt_info->cmd_sts = command_status;
- p_pkt_info->return_info = p_tx_desc_used->return_info;
- p_tx_desc_used->return_info = 0;
-
- /* Update the next descriptor to release. */
- USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
-
- /* Any Tx return cancels the Tx resource error status */
- if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
- p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
-
- D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
-
- return ETH_OK;
-
-}
-
-/*******************************************************************************
- * eth_port_receive - Get received information from Rx ring.
- *
- * DESCRIPTION:
- * This routine returns the received data to the caller. There is no
- * data copying during routine operation. All information is returned
- * using pointer to packet information struct passed from the caller.
- * If the routine exhausts Rx ring resources then the resource error flag
- * is set.
- *
- * INPUT:
- * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
- * ETH_QUEUE rx_queue Number of Rx queue.
- * PKT_INFO *p_pkt_info User packet buffer.
- *
- * OUTPUT:
- * Rx ring current and used indexes are updated.
- *
- * RETURN:
- * ETH_ERROR in case the routine can not access Rx desc ring.
- * ETH_QUEUE_FULL if Rx ring resources are exhausted.
- * ETH_END_OF_JOB if there is no received data.
- * ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
- ETH_QUEUE rx_queue,
- PKT_INFO * p_pkt_info)
-{
- volatile ETH_RX_DESC *p_rx_curr_desc;
- volatile ETH_RX_DESC *p_rx_next_curr_desc;
- volatile ETH_RX_DESC *p_rx_used_desc;
- unsigned int command_status;
-
- /* Do not process Rx ring in case of Rx ring resource error */
- if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
- printf ("\nRx Queue is full ...\n");
- return ETH_QUEUE_FULL;
- }
-
- /* Get the Rx Desc ring 'curr and 'used' indexes */
- CURR_RFD_GET (p_rx_curr_desc, rx_queue);
- USED_RFD_GET (p_rx_used_desc, rx_queue);
-
- /* Sanity check */
- if (p_rx_curr_desc == NULL)
- return ETH_ERROR;
-
- /* The following parameters are used to save readings from memory */
- p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
- command_status = p_rx_curr_desc->cmd_sts;
-
- /* Nothing to receive... */
- if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
-/* DP(printf("Rx: command_status: %08x\n", command_status)); */
- D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
-/* DP(printf("\nETH_END_OF_JOB ...\n"));*/
- return ETH_END_OF_JOB;
- }
-
- p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
- p_pkt_info->cmd_sts = command_status;
- p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
- p_pkt_info->return_info = p_rx_curr_desc->return_info;
- p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */
-
- /* Clean the return info field to indicate that the packet has been */
- /* moved to the upper layers */
- p_rx_curr_desc->return_info = 0;
-
- /* Update 'curr' in data structure */
- CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
-
- /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
- if (p_rx_next_curr_desc == p_rx_used_desc)
- p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
-
- D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
- CPU_PIPE_FLUSH;
- return ETH_OK;
-}
-
-/*******************************************************************************
- * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
- *
- * DESCRIPTION:
- * This routine returns a Rx buffer back to the Rx ring. It retrieves the
- * next 'used' descriptor and attached the returned buffer to it.
- * In case the Rx ring was in "resource error" condition, where there are
- * no available Rx resources, the function resets the resource error flag.
- *
- * INPUT:
- * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
- * ETH_QUEUE rx_queue Number of Rx queue.
- * PKT_INFO *p_pkt_info Information on the returned buffer.
- *
- * OUTPUT:
- * New available Rx resource in Rx descriptor ring.
- *
- * RETURN:
- * ETH_ERROR in case the routine can not access Rx desc ring.
- * ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
- p_eth_port_ctrl,
- ETH_QUEUE rx_queue,
- PKT_INFO * p_pkt_info)
-{
- volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */
-
- /* Get 'used' Rx descriptor */
- USED_RFD_GET (p_used_rx_desc, rx_queue);
-
- /* Sanity check */
- if (p_used_rx_desc == NULL)
- return ETH_ERROR;
-
- p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
- p_used_rx_desc->return_info = p_pkt_info->return_info;
- p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
- p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE; /* Reset Buffer size */
-
- /* Flush the write pipe */
- CPU_PIPE_FLUSH;
-
- /* Return the descriptor to DMA ownership */
- p_used_rx_desc->cmd_sts =
- ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
-
- /* Flush descriptor and CPU pipe */
- D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
- CPU_PIPE_FLUSH;
-
- /* Move the used descriptor pointer to the next descriptor */
- USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
-
- /* Any Rx return cancels the Rx resource error status */
- if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
- p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
-
- return ETH_OK;
-}
-
-/*******************************************************************************
- * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
- *
- * DESCRIPTION:
- * This routine sets the RX coalescing interrupt mechanism parameter.
- * This parameter is a timeout counter, that counts in 64 t_clk
- * chunks ; that when timeout event occurs a maskable interrupt
- * occurs.
- * The parameter is calculated using the tClk of the MV-643xx chip
- * , and the required delay of the interrupt in usec.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet port number
- * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
- * unsigned int delay Delay in usec
- *
- * OUTPUT:
- * Interrupt coalescing mechanism value is set in MV-643xx chip.
- *
- * RETURN:
- * The interrupt coalescing value set in the gigE port.
- *
- *******************************************************************************/
-#if 0 /* FIXME */
-static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
- unsigned int t_clk,
- unsigned int delay)
-{
- unsigned int coal;
-
- coal = ((t_clk / 1000000) * delay) / 64;
- /* Set RX Coalescing mechanism */
- MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
- ((coal & 0x3fff) << 8) |
- (MV_REG_READ
- (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num))
- & 0xffc000ff));
- return coal;
-}
-
-#endif
-/*******************************************************************************
- * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
- *
- * DESCRIPTION:
- * This routine sets the TX coalescing interrupt mechanism parameter.
- * This parameter is a timeout counter, that counts in 64 t_clk
- * chunks ; that when timeout event occurs a maskable interrupt
- * occurs.
- * The parameter is calculated using the t_cLK frequency of the
- * MV-643xx chip and the required delay in the interrupt in uSec
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet port number
- * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
- * unsigned int delay Delay in uSeconds
- *
- * OUTPUT:
- * Interrupt coalescing mechanism value is set in MV-643xx chip.
- *
- * RETURN:
- * The interrupt coalescing value set in the gigE port.
- *
- *******************************************************************************/
-#if 0 /* FIXME */
-static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
- unsigned int t_clk,
- unsigned int delay)
-{
- unsigned int coal;
-
- coal = ((t_clk / 1000000) * delay) / 64;
- /* Set TX Coalescing mechanism */
- MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
- coal << 4);
- return coal;
-}
-#endif
-
-/*******************************************************************************
- * eth_b_copy - Copy bytes from source to destination
- *
- * DESCRIPTION:
- * This function supports the eight bytes limitation on Tx buffer size.
- * The routine will zero eight bytes starting from the destination address
- * followed by copying bytes from the source address to the destination.
- *
- * INPUT:
- * unsigned int src_addr 32 bit source address.
- * unsigned int dst_addr 32 bit destination address.
- * int byte_count Number of bytes to copy.
- *
- * OUTPUT:
- * See description.
- *
- * RETURN:
- * None.
- *
- *******************************************************************************/
-static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
- int byte_count)
-{
- /* Zero the dst_addr area */
- *(unsigned int *) dst_addr = 0x0;
-
- while (byte_count != 0) {
- *(char *) dst_addr = *(char *) src_addr;
- dst_addr++;
- src_addr++;
- byte_count--;
- }
-}
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64360X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * mv_eth.h - header file for the polled mode GT ethernet driver
- */
-
-#ifndef __DB64360_ETH_H__
-#define __DB64360_ETH_H__
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-#include <common.h>
-#include <net.h>
-#include "mv_regs.h"
-#include <asm/errno.h>
-
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-* The first part is the high level driver of the gigE ethernet ports. *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
-#ifndef MAX_SKB_FRAGS
-#define MAX_SKB_FRAGS 0
-#endif
-
-/* Port attributes */
-/*#define MAX_RX_QUEUE_NUM 8*/
-/*#define MAX_TX_QUEUE_NUM 8*/
-#define MAX_RX_QUEUE_NUM 1
-#define MAX_TX_QUEUE_NUM 1
-
-
-/* Use one TX queue and one RX queue */
-#define MV64360_TX_QUEUE_NUM 1
-#define MV64360_RX_QUEUE_NUM 1
-
-/*
- * Number of RX / TX descriptors on RX / TX rings.
- * Note that allocating RX descriptors is done by allocating the RX
- * ring AND a preallocated RX buffers (skb's) for each descriptor.
- * The TX descriptors only allocates the TX descriptors ring,
- * with no pre allocated TX buffers (skb's are allocated by higher layers.
- */
-
-/* Default TX ring size is 10 descriptors */
-#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE
-#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE
-#else
-#define MV64360_TX_QUEUE_SIZE 4
-#endif
-
-/* Default RX ring size is 4 descriptors */
-#ifdef CONFIG_MV64360_ETH_RXQUEUE_SIZE
-#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE
-#else
-#define MV64360_RX_QUEUE_SIZE 4
-#endif
-
-#ifdef CONFIG_RX_BUFFER_SIZE
-#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
-#else
-#define MV64360_RX_BUFFER_SIZE 1600
-#endif
-
-#ifdef CONFIG_TX_BUFFER_SIZE
-#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
-#else
-#define MV64360_TX_BUFFER_SIZE 1600
-#endif
-
-
-/*
- * Network device statistics. Akin to the 2.0 ether stats but
- * with byte counters.
- */
-
-struct net_device_stats
-{
- unsigned long rx_packets; /* total packets received */
- unsigned long tx_packets; /* total packets transmitted */
- unsigned long rx_bytes; /* total bytes received */
- unsigned long tx_bytes; /* total bytes transmitted */
- unsigned long rx_errors; /* bad packets received */
- unsigned long tx_errors; /* packet transmit problems */
- unsigned long rx_dropped; /* no space in linux buffers */
- unsigned long tx_dropped; /* no space available in linux */
- unsigned long multicast; /* multicast packets received */
- unsigned long collisions;
-
- /* detailed rx_errors: */
- unsigned long rx_length_errors;
- unsigned long rx_over_errors; /* receiver ring buff overflow */
- unsigned long rx_crc_errors; /* recved pkt with crc error */
- unsigned long rx_frame_errors; /* recv'd frame alignment error */
- unsigned long rx_fifo_errors; /* recv'r fifo overrun */
- unsigned long rx_missed_errors; /* receiver missed packet */
-
- /* detailed tx_errors */
- unsigned long tx_aborted_errors;
- unsigned long tx_carrier_errors;
- unsigned long tx_fifo_errors;
- unsigned long tx_heartbeat_errors;
- unsigned long tx_window_errors;
-
- /* for cslip etc */
- unsigned long rx_compressed;
- unsigned long tx_compressed;
-};
-
-
-/* Private data structure used for ethernet device */
-struct mv64360_eth_priv {
- unsigned int port_num;
- struct net_device_stats *stats;
-
-/* to buffer area aligned */
- char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */
- char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */
-
- /* Size of Tx Ring per queue */
- unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
-
-
- /* Size of Rx Ring per queue */
- unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
-
- /* Magic Number for Ethernet running */
- unsigned int eth_running;
-
-};
-
-
-int mv64360_eth_init (struct eth_device *dev);
-int mv64360_eth_stop (struct eth_device *dev);
-int mv64360_eth_start_xmit(struct eth_device *dev, void *packet, int length);
-int mv64360_eth_open (struct eth_device *dev);
-
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-* The second part is the low level driver of the gigE ethernet ports. *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-
-
-/********************************************************************************
- * Header File for : MV-643xx network interface header
- *
- * DESCRIPTION:
- * This header file contains macros typedefs and function declaration for
- * the Marvell Gig Bit Ethernet Controller.
- *
- * DEPENDENCIES:
- * None.
- *
- *******************************************************************************/
-
-
-#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
-#ifdef CONFIG_MV64360_SRAM_CACHEABLE
-/* In case SRAM is cacheable but not cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset) \
-{ \
- __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
-}
-#else
-/* In case SRAM is cache coherent or non-cacheable */
-#define D_CACHE_FLUSH_LINE(addr, offset) ;
-#endif
-#else
-#ifdef CONFIG_NOT_COHERENT_CACHE
-/* In case of descriptors on DDR but not cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset) \
-{ \
- __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
-}
-#else
-/* In case of descriptors on DDR and cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset) ;
-#endif /* CONFIG_NOT_COHERENT_CACHE */
-#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
-
-
-#define CPU_PIPE_FLUSH \
-{ \
- __asm__ __volatile__ ("eieio"); \
-}
-
-
-/* defines */
-
-/* Default port configuration value */
-#define PORT_CONFIG_VALUE \
- ETH_UNICAST_NORMAL_MODE | \
- ETH_DEFAULT_RX_QUEUE_0 | \
- ETH_DEFAULT_RX_ARP_QUEUE_0 | \
- ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
- ETH_RECEIVE_BC_IF_IP | \
- ETH_RECEIVE_BC_IF_ARP | \
- ETH_CAPTURE_TCP_FRAMES_DIS | \
- ETH_CAPTURE_UDP_FRAMES_DIS | \
- ETH_DEFAULT_RX_TCP_QUEUE_0 | \
- ETH_DEFAULT_RX_UDP_QUEUE_0 | \
- ETH_DEFAULT_RX_BPDU_QUEUE_0
-
-/* Default port extend configuration value */
-#define PORT_CONFIG_EXTEND_VALUE \
- ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
- ETH_PARTITION_DISABLE
-
-
-/* Default sdma control value */
-#ifdef CONFIG_NOT_COHERENT_CACHE
-#define PORT_SDMA_CONFIG_VALUE \
- ETH_RX_BURST_SIZE_16_64BIT | \
- GT_ETH_IPG_INT_RX(0) | \
- ETH_TX_BURST_SIZE_16_64BIT;
-#else
-#define PORT_SDMA_CONFIG_VALUE \
- ETH_RX_BURST_SIZE_4_64BIT | \
- GT_ETH_IPG_INT_RX(0) | \
- ETH_TX_BURST_SIZE_4_64BIT;
-#endif
-
-#define GT_ETH_IPG_INT_RX(value) \
- ((value & 0x3fff) << 8)
-
-/* Default port serial control value */
-#define PORT_SERIAL_CONTROL_VALUE \
- ETH_FORCE_LINK_PASS | \
- ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
- ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
- ETH_ADV_SYMMETRIC_FLOW_CTRL | \
- ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
- ETH_FORCE_BP_MODE_NO_JAM | \
- BIT9 | \
- ETH_DO_NOT_FORCE_LINK_FAIL | \
- ETH_RETRANSMIT_16_ETTEMPTS | \
- ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
- ETH_DTE_ADV_0 | \
- ETH_DISABLE_AUTO_NEG_BYPASS | \
- ETH_AUTO_NEG_NO_CHANGE | \
- ETH_MAX_RX_PACKET_1552BYTE | \
- ETH_CLR_EXT_LOOPBACK | \
- ETH_SET_FULL_DUPLEX_MODE | \
- ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
-
-#define RX_BUFFER_MAX_SIZE 0xFFFF
-#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */
-
-#define RX_BUFFER_MIN_SIZE 0x8
-#define TX_BUFFER_MIN_SIZE 0x8
-
-/* Tx WRR confoguration macros */
-#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
-#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */
-#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */
-
-/* MAC accepet/reject macros */
-#define ACCEPT_MAC_ADDR 0
-#define REJECT_MAC_ADDR 1
-
-/* Size of a Tx/Rx descriptor used in chain list data structure */
-#define RX_DESC_ALIGNED_SIZE 0x20
-#define TX_DESC_ALIGNED_SIZE 0x20
-
-/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
-#define TX_BUF_OFFSET_IN_DESC 0x18
-/* Buffer offset from buffer pointer */
-#define RX_BUF_OFFSET 0x2
-
-/* Gap define */
-#define ETH_BAR_GAP 0x8
-#define ETH_SIZE_REG_GAP 0x8
-#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4
-#define ETH_PORT_ACCESS_CTRL_GAP 0x4
-
-/* Gigabit Ethernet Unit Global Registers */
-
-/* MIB Counters register definitions */
-#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
-#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
-#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
-#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
-#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
-#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
-#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
-#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
-#define ETH_MIB_FRAMES_64_OCTETS 0x20
-#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
-#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
-#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
-#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
-#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
-#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
-#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
-#define ETH_MIB_GOOD_FRAMES_SENT 0x40
-#define ETH_MIB_EXCESSIVE_COLLISION 0x44
-#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
-#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
-#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
-#define ETH_MIB_FC_SENT 0x54
-#define ETH_MIB_GOOD_FC_RECEIVED 0x58
-#define ETH_MIB_BAD_FC_RECEIVED 0x5c
-#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
-#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
-#define ETH_MIB_OVERSIZE_RECEIVED 0x68
-#define ETH_MIB_JABBER_RECEIVED 0x6c
-#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
-#define ETH_MIB_BAD_CRC_EVENT 0x74
-#define ETH_MIB_COLLISION 0x78
-#define ETH_MIB_LATE_COLLISION 0x7c
-
-/* Port serial status reg (PSR) */
-#define ETH_INTERFACE_GMII_MII 0
-#define ETH_INTERFACE_PCM BIT0
-#define ETH_LINK_IS_DOWN 0
-#define ETH_LINK_IS_UP BIT1
-#define ETH_PORT_AT_HALF_DUPLEX 0
-#define ETH_PORT_AT_FULL_DUPLEX BIT2
-#define ETH_RX_FLOW_CTRL_DISABLED 0
-#define ETH_RX_FLOW_CTRL_ENBALED BIT3
-#define ETH_GMII_SPEED_100_10 0
-#define ETH_GMII_SPEED_1000 BIT4
-#define ETH_MII_SPEED_10 0
-#define ETH_MII_SPEED_100 BIT5
-#define ETH_NO_TX 0
-#define ETH_TX_IN_PROGRESS BIT7
-#define ETH_BYPASS_NO_ACTIVE 0
-#define ETH_BYPASS_ACTIVE BIT8
-#define ETH_PORT_NOT_AT_PARTITION_STATE 0
-#define ETH_PORT_AT_PARTITION_STATE BIT9
-#define ETH_PORT_TX_FIFO_NOT_EMPTY 0
-#define ETH_PORT_TX_FIFO_EMPTY BIT10
-
-
-/* These macros describes the Port configuration reg (Px_cR) bits */
-#define ETH_UNICAST_NORMAL_MODE 0
-#define ETH_UNICAST_PROMISCUOUS_MODE BIT0
-#define ETH_DEFAULT_RX_QUEUE_0 0
-#define ETH_DEFAULT_RX_QUEUE_1 BIT1
-#define ETH_DEFAULT_RX_QUEUE_2 BIT2
-#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1)
-#define ETH_DEFAULT_RX_QUEUE_4 BIT3
-#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1)
-#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2)
-#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1)
-#define ETH_DEFAULT_RX_ARP_QUEUE_0 0
-#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4
-#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5
-#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4)
-#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6
-#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4)
-#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5)
-#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4)
-#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
-#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7
-#define ETH_RECEIVE_BC_IF_IP 0
-#define ETH_REJECT_BC_IF_IP BIT8
-#define ETH_RECEIVE_BC_IF_ARP 0
-#define ETH_REJECT_BC_IF_ARP BIT9
-#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12
-#define ETH_CAPTURE_TCP_FRAMES_DIS 0
-#define ETH_CAPTURE_TCP_FRAMES_EN BIT14
-#define ETH_CAPTURE_UDP_FRAMES_DIS 0
-#define ETH_CAPTURE_UDP_FRAMES_EN BIT15
-#define ETH_DEFAULT_RX_TCP_QUEUE_0 0
-#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16
-#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17
-#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16)
-#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18
-#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16)
-#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17)
-#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16)
-#define ETH_DEFAULT_RX_UDP_QUEUE_0 0
-#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19
-#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20
-#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19)
-#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21
-#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19)
-#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20)
-#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0
-#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22
-#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23
-#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
-#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
-
-
-/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
-#define ETH_CLASSIFY_EN BIT0
-#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
-#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1
-#define ETH_PARTITION_DISABLE 0
-#define ETH_PARTITION_ENABLE BIT2
-
-
-/* Tx/Rx queue command reg (RQCR/TQCR)*/
-#define ETH_QUEUE_0_ENABLE BIT0
-#define ETH_QUEUE_1_ENABLE BIT1
-#define ETH_QUEUE_2_ENABLE BIT2
-#define ETH_QUEUE_3_ENABLE BIT3
-#define ETH_QUEUE_4_ENABLE BIT4
-#define ETH_QUEUE_5_ENABLE BIT5
-#define ETH_QUEUE_6_ENABLE BIT6
-#define ETH_QUEUE_7_ENABLE BIT7
-#define ETH_QUEUE_0_DISABLE BIT8
-#define ETH_QUEUE_1_DISABLE BIT9
-#define ETH_QUEUE_2_DISABLE BIT10
-#define ETH_QUEUE_3_DISABLE BIT11
-#define ETH_QUEUE_4_DISABLE BIT12
-#define ETH_QUEUE_5_DISABLE BIT13
-#define ETH_QUEUE_6_DISABLE BIT14
-#define ETH_QUEUE_7_DISABLE BIT15
-
-
-/* These macros describes the Port Sdma configuration reg (SDCR) bits */
-#define ETH_RIFB BIT0
-#define ETH_RX_BURST_SIZE_1_64BIT 0
-#define ETH_RX_BURST_SIZE_2_64BIT BIT1
-#define ETH_RX_BURST_SIZE_4_64BIT BIT2
-#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1)
-#define ETH_RX_BURST_SIZE_16_64BIT BIT3
-#define ETH_BLM_RX_NO_SWAP BIT4
-#define ETH_BLM_RX_BYTE_SWAP 0
-#define ETH_BLM_TX_NO_SWAP BIT5
-#define ETH_BLM_TX_BYTE_SWAP 0
-#define ETH_DESCRIPTORS_BYTE_SWAP BIT6
-#define ETH_DESCRIPTORS_NO_SWAP 0
-#define ETH_TX_BURST_SIZE_1_64BIT 0
-#define ETH_TX_BURST_SIZE_2_64BIT BIT22
-#define ETH_TX_BURST_SIZE_4_64BIT BIT23
-#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22)
-#define ETH_TX_BURST_SIZE_16_64BIT BIT24
-
-
-/* These macros describes the Port serial control reg (PSCR) bits */
-#define ETH_SERIAL_PORT_DISABLE 0
-#define ETH_SERIAL_PORT_ENABLE BIT0
-#define ETH_FORCE_LINK_PASS BIT1
-#define ETH_DO_NOT_FORCE_LINK_PASS 0
-#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
-#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2
-#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
-#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3
-#define ETH_ADV_NO_FLOW_CTRL 0
-#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4
-#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
-#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5
-#define ETH_FORCE_BP_MODE_NO_JAM 0
-#define ETH_FORCE_BP_MODE_JAM_TX BIT7
-#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8
-#define ETH_FORCE_LINK_FAIL 0
-#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10
-#define ETH_RETRANSMIT_16_ETTEMPTS 0
-#define ETH_RETRANSMIT_FOREVER BIT11
-#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13
-#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
-#define ETH_DTE_ADV_0 0
-#define ETH_DTE_ADV_1 BIT14
-#define ETH_DISABLE_AUTO_NEG_BYPASS 0
-#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15
-#define ETH_AUTO_NEG_NO_CHANGE 0
-#define ETH_RESTART_AUTO_NEG BIT16
-#define ETH_MAX_RX_PACKET_1518BYTE 0
-#define ETH_MAX_RX_PACKET_1522BYTE BIT17
-#define ETH_MAX_RX_PACKET_1552BYTE BIT18
-#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17)
-#define ETH_MAX_RX_PACKET_9192BYTE BIT19
-#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17)
-#define ETH_SET_EXT_LOOPBACK BIT20
-#define ETH_CLR_EXT_LOOPBACK 0
-#define ETH_SET_FULL_DUPLEX_MODE BIT21
-#define ETH_SET_HALF_DUPLEX_MODE 0
-#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22
-#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
-#define ETH_SET_GMII_SPEED_TO_10_100 0
-#define ETH_SET_GMII_SPEED_TO_1000 BIT23
-#define ETH_SET_MII_SPEED_TO_10 0
-#define ETH_SET_MII_SPEED_TO_100 BIT24
-
-
-/* SMI reg */
-#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
-#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
-#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
-#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
-
-/* SDMA command status fields macros */
-
-/* Tx & Rx descriptors status */
-#define ETH_ERROR_SUMMARY (BIT0)
-
-/* Tx & Rx descriptors command */
-#define ETH_BUFFER_OWNED_BY_DMA (BIT31)
-
-/* Tx descriptors status */
-#define ETH_LC_ERROR (0 )
-#define ETH_UR_ERROR (BIT1 )
-#define ETH_RL_ERROR (BIT2 )
-#define ETH_LLC_SNAP_FORMAT (BIT9 )
-
-/* Rx descriptors status */
-#define ETH_CRC_ERROR (0 )
-#define ETH_OVERRUN_ERROR (BIT1 )
-#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
-#define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
-#define ETH_VLAN_TAGGED (BIT19)
-#define ETH_BPDU_FRAME (BIT20)
-#define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
-#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
-#define ETH_OTHER_FRAME_TYPE (BIT22)
-#define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
-#define ETH_FRAME_TYPE_IP_V_4 (BIT24)
-#define ETH_FRAME_HEADER_OK (BIT25)
-#define ETH_RX_LAST_DESC (BIT26)
-#define ETH_RX_FIRST_DESC (BIT27)
-#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
-#define ETH_RX_ENABLE_INTERRUPT (BIT29)
-#define ETH_LAYER_4_CHECKSUM_OK (BIT30)
-
-/* Rx descriptors byte count */
-#define ETH_FRAME_FRAGMENTED (BIT2)
-
-/* Tx descriptors command */
-#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
-#define ETH_FRAME_SET_TO_VLAN (BIT15)
-#define ETH_TCP_FRAME (0 )
-#define ETH_UDP_FRAME (BIT16)
-#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
-#define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
-#define ETH_ZERO_PADDING (BIT19)
-#define ETH_TX_LAST_DESC (BIT20)
-#define ETH_TX_FIRST_DESC (BIT21)
-#define ETH_GEN_CRC (BIT22)
-#define ETH_TX_ENABLE_INTERRUPT (BIT23)
-#define ETH_AUTO_MODE (BIT30)
-
-/* Address decode parameters */
-/* Ethernet Base Address Register bits */
-#define EBAR_TARGET_DRAM 0x00000000
-#define EBAR_TARGET_DEVICE 0x00000001
-#define EBAR_TARGET_CBS 0x00000002
-#define EBAR_TARGET_PCI0 0x00000003
-#define EBAR_TARGET_PCI1 0x00000004
-#define EBAR_TARGET_CUNIT 0x00000005
-#define EBAR_TARGET_AUNIT 0x00000006
-#define EBAR_TARGET_GUNIT 0x00000007
-
-/* Window attributes */
-#define EBAR_ATTR_DRAM_CS0 0x00000E00
-#define EBAR_ATTR_DRAM_CS1 0x00000D00
-#define EBAR_ATTR_DRAM_CS2 0x00000B00
-#define EBAR_ATTR_DRAM_CS3 0x00000700
-
-/* DRAM Target interface */
-#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000
-#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000
-#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000
-
-/* Device Bus Target interface */
-#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00
-#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00
-#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00
-#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700
-#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00
-
-/* PCI Target interface */
-#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000
-#define EBAR_ATTR_PCI_NO_SWAP 0x00000100
-#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200
-#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300
-#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
-#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400
-#define EBAR_ATTR_PCI_IO_SPACE 0x00000000
-#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800
-#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000
-#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000
-
-/* CPU 60x bus or internal SRAM interface */
-#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000
-#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100
-#define EBAR_ATTR_CBS_SRAM 0x00000000
-#define EBAR_ATTR_CBS_CPU_BUS 0x00000800
-
-/* Window access control */
-#define EWIN_ACCESS_NOT_ALLOWED 0
-#define EWIN_ACCESS_READ_ONLY BIT0
-#define EWIN_ACCESS_FULL (BIT1 | BIT0)
-#define EWIN0_ACCESS_MASK 0x0003
-#define EWIN1_ACCESS_MASK 0x000C
-#define EWIN2_ACCESS_MASK 0x0030
-#define EWIN3_ACCESS_MASK 0x00C0
-
-/* typedefs */
-
-typedef enum _eth_port
-{
- ETH_0 = 0,
- ETH_1 = 1,
- ETH_2 = 2
-}ETH_PORT;
-
-typedef enum _eth_func_ret_status
-{
- ETH_OK, /* Returned as expected. */
- ETH_ERROR, /* Fundamental error. */
- ETH_RETRY, /* Could not process request. Try later. */
- ETH_END_OF_JOB, /* Ring has nothing to process. */
- ETH_QUEUE_FULL, /* Ring resource error. */
- ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
-}ETH_FUNC_RET_STATUS;
-
-typedef enum _eth_queue
-{
- ETH_Q0 = 0,
- ETH_Q1 = 1,
- ETH_Q2 = 2,
- ETH_Q3 = 3,
- ETH_Q4 = 4,
- ETH_Q5 = 5,
- ETH_Q6 = 6,
- ETH_Q7 = 7
-} ETH_QUEUE;
-
-typedef enum _addr_win
-{
- ETH_WIN0,
- ETH_WIN1,
- ETH_WIN2,
- ETH_WIN3,
- ETH_WIN4,
- ETH_WIN5
-} ETH_ADDR_WIN;
-
-typedef enum _eth_target
-{
- ETH_TARGET_DRAM ,
- ETH_TARGET_DEVICE,
- ETH_TARGET_CBS ,
- ETH_TARGET_PCI0 ,
- ETH_TARGET_PCI1
-}ETH_TARGET;
-
-typedef struct _eth_rx_desc
-{
- unsigned short byte_cnt ; /* Descriptor buffer byte count */
- unsigned short buf_size ; /* Buffer size */
- unsigned int cmd_sts ; /* Descriptor command status */
- unsigned int next_desc_ptr; /* Next descriptor pointer */
- unsigned int buf_ptr ; /* Descriptor buffer pointer */
- unsigned int return_info ; /* User resource return information */
-} ETH_RX_DESC;
-
-
-typedef struct _eth_tx_desc
-{
- unsigned short byte_cnt ; /* Descriptor buffer byte count */
- unsigned short l4i_chk ; /* CPU provided TCP Checksum */
- unsigned int cmd_sts ; /* Descriptor command status */
- unsigned int next_desc_ptr; /* Next descriptor pointer */
- unsigned int buf_ptr ; /* Descriptor buffer pointer */
- unsigned int return_info ; /* User resource return information */
-} ETH_TX_DESC;
-
-/* Unified struct for Rx and Tx operations. The user is not required to */
-/* be familier with neither Tx nor Rx descriptors. */
-typedef struct _pkt_info
-{
- unsigned short byte_cnt ; /* Descriptor buffer byte count */
- unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */
- unsigned int cmd_sts ; /* Descriptor command status */
- unsigned int buf_ptr ; /* Descriptor buffer pointer */
- unsigned int return_info ; /* User resource return information */
-} PKT_INFO;
-
-
-typedef struct _eth_win_param
-{
- ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */
- ETH_TARGET target; /* System targets. See ETH_TARGET enum */
- unsigned short attributes; /* BAR attributes. See above macros. */
- unsigned int base_addr; /* Window base address in unsigned int form */
- unsigned int high_addr; /* Window high address in unsigned int form */
- unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
- bool enable; /* Enable/disable access to the window. */
- unsigned short access_ctrl; /* Access ctrl register. see above macros */
-} ETH_WIN_PARAM;
-
-
-/* Ethernet port specific infomation */
-
-typedef struct _eth_port_ctrl
-{
- ETH_PORT port_num; /* User Ethernet port number */
- int port_phy_addr; /* User phy address of Ethrnet port */
- unsigned char port_mac_addr[6]; /* User defined port MAC address. */
- unsigned int port_config; /* User port configuration value */
- unsigned int port_config_extend; /* User port config extend value */
- unsigned int port_sdma_config; /* User port SDMA config value */
- unsigned int port_serial_control; /* User port serial control value */
- unsigned int port_tx_queue_command; /* Port active Tx queues summary */
- unsigned int port_rx_queue_command; /* Port active Rx queues summary */
-
- /* User function to cast virtual address to CPU bus address */
- unsigned int (*port_virt_to_phys)(unsigned int addr);
- /* User scratch pad for user specific data structures */
- void *port_private;
-
- bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
- bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
-
- /* Tx/Rx rings managment indexes fields. For driver use */
-
- /* Next available Rx resource */
- volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
- /* Returning Rx resource */
- volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
-
- /* Next available Tx resource */
- volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
- /* Returning Tx resource */
- volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
- /* An extra Tx index to support transmit of multiple buffers per packet */
- volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
-
- /* Tx/Rx rings size and base variables fields. For driver use */
-
- volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
- unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM];
- char *p_rx_buffer_base[MAX_RX_QUEUE_NUM];
-
- volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
- unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM];
- char *p_tx_buffer_base[MAX_TX_QUEUE_NUM];
-
-} ETH_PORT_INFO;
-
-
-/* ethernet.h API list */
-
-/* Port operation control routines */
-static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
-static void eth_port_reset(ETH_PORT eth_port_num);
-static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
-
-
-/* Port MAC address routines */
-static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
- unsigned char *p_addr,
- ETH_QUEUE queue);
-#if 0 /* FIXME */
-static void eth_port_mc_addr (ETH_PORT eth_port_num,
- unsigned char *p_addr,
- ETH_QUEUE queue,
- int option);
-#endif
-
-/* PHY and MIB routines */
-static bool ethernet_phy_reset(ETH_PORT eth_port_num);
-
-static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
- unsigned int phy_reg,
- unsigned int value);
-
-static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
- unsigned int phy_reg,
- unsigned int* value);
-
-static void eth_clear_mib_counters(ETH_PORT eth_port_num);
-
-/* Port data flow control routines */
-static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl,
- ETH_QUEUE tx_queue,
- PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
- ETH_QUEUE tx_queue,
- PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
- ETH_QUEUE rx_queue,
- PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
- ETH_QUEUE rx_queue,
- PKT_INFO *p_pkt_info);
-
-
-static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
- ETH_QUEUE tx_queue,
- int tx_desc_num,
- int tx_buff_size,
- unsigned int tx_desc_base_addr,
- unsigned int tx_buff_base_addr);
-
-static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
- ETH_QUEUE rx_queue,
- int rx_desc_num,
- int rx_buff_size,
- unsigned int rx_desc_base_addr,
- unsigned int rx_buff_base_addr);
-
-#endif /* MV64360_ETH_ */
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64360X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/********************************************************************************
-* gt64360r.h - GT-64360 Internal registers definition file.
-*
-* DESCRIPTION:
-* None.
-*
-* DEPENDENCIES:
-* None.
-*
-*******************************************************************************/
-
-#ifndef __INCmv_regsh
-#define __INCmv_regsh
-
-#define MV64360
-
-/* Supported by the Atlantis */
-#define MV64360_INCLUDE_PCI_1
-#define MV64360_INCLUDE_PCI_0_ARBITER
-#define MV64360_INCLUDE_PCI_1_ARBITER
-#define MV64360_INCLUDE_SNOOP_SUPPORT
-#define MV64360_INCLUDE_P2P
-#define MV64360_INCLUDE_ETH_PORT_2
-#define MV64360_INCLUDE_CPU_MAPPING
-#define MV64360_INCLUDE_MPSC
-
-/* Not supported features */
-#undef INCLUDE_CNTMR_4_7
-#undef INCLUDE_DMA_4_7
-
-/****************************************/
-/* Processor Address Space */
-/****************************************/
-
-/* DDR SDRAM BAR and size registers */
-
-#define MV64360_CS_0_BASE_ADDR 0x008
-#define MV64360_CS_0_SIZE 0x010
-#define MV64360_CS_1_BASE_ADDR 0x208
-#define MV64360_CS_1_SIZE 0x210
-#define MV64360_CS_2_BASE_ADDR 0x018
-#define MV64360_CS_2_SIZE 0x020
-#define MV64360_CS_3_BASE_ADDR 0x218
-#define MV64360_CS_3_SIZE 0x220
-
-/* Devices BAR and size registers */
-
-#define MV64360_DEV_CS0_BASE_ADDR 0x028
-#define MV64360_DEV_CS0_SIZE 0x030
-#define MV64360_DEV_CS1_BASE_ADDR 0x228
-#define MV64360_DEV_CS1_SIZE 0x230
-#define MV64360_DEV_CS2_BASE_ADDR 0x248
-#define MV64360_DEV_CS2_SIZE 0x250
-#define MV64360_DEV_CS3_BASE_ADDR 0x038
-#define MV64360_DEV_CS3_SIZE 0x040
-#define MV64360_BOOTCS_BASE_ADDR 0x238
-#define MV64360_BOOTCS_SIZE 0x240
-
-/* PCI 0 BAR and size registers */
-
-#define MV64360_PCI_0_IO_BASE_ADDR 0x048
-#define MV64360_PCI_0_IO_SIZE 0x050
-#define MV64360_PCI_0_MEMORY0_BASE_ADDR 0x058
-#define MV64360_PCI_0_MEMORY0_SIZE 0x060
-#define MV64360_PCI_0_MEMORY1_BASE_ADDR 0x080
-#define MV64360_PCI_0_MEMORY1_SIZE 0x088
-#define MV64360_PCI_0_MEMORY2_BASE_ADDR 0x258
-#define MV64360_PCI_0_MEMORY2_SIZE 0x260
-#define MV64360_PCI_0_MEMORY3_BASE_ADDR 0x280
-#define MV64360_PCI_0_MEMORY3_SIZE 0x288
-
-/* PCI 1 BAR and size registers */
-#define MV64360_PCI_1_IO_BASE_ADDR 0x090
-#define MV64360_PCI_1_IO_SIZE 0x098
-#define MV64360_PCI_1_MEMORY0_BASE_ADDR 0x0a0
-#define MV64360_PCI_1_MEMORY0_SIZE 0x0a8
-#define MV64360_PCI_1_MEMORY1_BASE_ADDR 0x0b0
-#define MV64360_PCI_1_MEMORY1_SIZE 0x0b8
-#define MV64360_PCI_1_MEMORY2_BASE_ADDR 0x2a0
-#define MV64360_PCI_1_MEMORY2_SIZE 0x2a8
-#define MV64360_PCI_1_MEMORY3_BASE_ADDR 0x2b0
-#define MV64360_PCI_1_MEMORY3_SIZE 0x2b8
-
-/* SRAM base address */
-#define MV64360_INTEGRATED_SRAM_BASE_ADDR 0x268
-
-/* internal registers space base address */
-#define MV64360_INTERNAL_SPACE_BASE_ADDR 0x068
-
-/* Enables the CS , DEV_CS , PCI 0 and PCI 1
- windows above */
-#define MV64360_BASE_ADDR_ENABLE 0x278
-
-/****************************************/
-/* PCI remap registers */
-/****************************************/
- /* PCI 0 */
-#define MV64360_PCI_0_IO_ADDR_REMAP 0x0f0
-#define MV64360_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8
-#define MV64360_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320
-#define MV64360_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100
-#define MV64360_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328
-#define MV64360_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8
-#define MV64360_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330
-#define MV64360_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300
-#define MV64360_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338
- /* PCI 1 */
-#define MV64360_PCI_1_IO_ADDR_REMAP 0x108
-#define MV64360_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110
-#define MV64360_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340
-#define MV64360_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118
-#define MV64360_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348
-#define MV64360_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310
-#define MV64360_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350
-#define MV64360_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318
-#define MV64360_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358
-
-#define MV64360_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0
-#define MV64360_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8
-#define MV64360_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0
-#define MV64360_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8
-#define MV64360_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0
-#define MV64360_CPU_GE_HEADERS_RETARGET_BASE 0x3d8
-#define MV64360_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0
-#define MV64360_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8
-
-/****************************************/
-/* CPU Control Registers */
-/****************************************/
-
-#define MV64360_CPU_CONFIG 0x000
-#define MV64360_CPU_MODE 0x120
-#define MV64360_CPU_MASTER_CONTROL 0x160
-#define MV64360_CPU_CROSS_BAR_CONTROL_LOW 0x150
-#define MV64360_CPU_CROSS_BAR_CONTROL_HIGH 0x158
-#define MV64360_CPU_CROSS_BAR_TIMEOUT 0x168
-
-/****************************************/
-/* SMP RegisterS */
-/****************************************/
-
-#define MV64360_SMP_WHO_AM_I 0x200
-#define MV64360_SMP_CPU0_DOORBELL 0x214
-#define MV64360_SMP_CPU0_DOORBELL_CLEAR 0x21C
-#define MV64360_SMP_CPU1_DOORBELL 0x224
-#define MV64360_SMP_CPU1_DOORBELL_CLEAR 0x22C
-#define MV64360_SMP_CPU0_DOORBELL_MASK 0x234
-#define MV64360_SMP_CPU1_DOORBELL_MASK 0x23C
-#define MV64360_SMP_SEMAPHOR0 0x244
-#define MV64360_SMP_SEMAPHOR1 0x24c
-#define MV64360_SMP_SEMAPHOR2 0x254
-#define MV64360_SMP_SEMAPHOR3 0x25c
-#define MV64360_SMP_SEMAPHOR4 0x264
-#define MV64360_SMP_SEMAPHOR5 0x26c
-#define MV64360_SMP_SEMAPHOR6 0x274
-#define MV64360_SMP_SEMAPHOR7 0x27c
-
-/****************************************/
-/* CPU Sync Barrier Register */
-/****************************************/
-
-#define MV64360_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0
-#define MV64360_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8
-#define MV64360_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0
-#define MV64360_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8
-
-/****************************************/
-/* CPU Access Protect */
-/****************************************/
-
-#define MV64360_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180
-#define MV64360_CPU_PROTECT_WINDOW_0_SIZE 0x188
-#define MV64360_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190
-#define MV64360_CPU_PROTECT_WINDOW_1_SIZE 0x198
-#define MV64360_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0
-#define MV64360_CPU_PROTECT_WINDOW_2_SIZE 0x1a8
-#define MV64360_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0
-#define MV64360_CPU_PROTECT_WINDOW_3_SIZE 0x1b8
-
-
-/****************************************/
-/* CPU Error Report */
-/****************************************/
-
-#define MV64360_CPU_ERROR_ADDR_LOW 0x070
-#define MV64360_CPU_ERROR_ADDR_HIGH 0x078
-#define MV64360_CPU_ERROR_DATA_LOW 0x128
-#define MV64360_CPU_ERROR_DATA_HIGH 0x130
-#define MV64360_CPU_ERROR_PARITY 0x138
-#define MV64360_CPU_ERROR_CAUSE 0x140
-#define MV64360_CPU_ERROR_MASK 0x148
-
-/****************************************/
-/* CPU Interface Debug Registers */
-/****************************************/
-
-#define MV64360_PUNIT_SLAVE_DEBUG_LOW 0x360
-#define MV64360_PUNIT_SLAVE_DEBUG_HIGH 0x368
-#define MV64360_PUNIT_MASTER_DEBUG_LOW 0x370
-#define MV64360_PUNIT_MASTER_DEBUG_HIGH 0x378
-#define MV64360_PUNIT_MMASK 0x3e4
-
-/****************************************/
-/* Integrated SRAM Registers */
-/****************************************/
-
-#define MV64360_SRAM_CONFIG 0x380
-#define MV64360_SRAM_TEST_MODE 0X3F4
-#define MV64360_SRAM_ERROR_CAUSE 0x388
-#define MV64360_SRAM_ERROR_ADDR 0x390
-#define MV64360_SRAM_ERROR_ADDR_HIGH 0X3F8
-#define MV64360_SRAM_ERROR_DATA_LOW 0x398
-#define MV64360_SRAM_ERROR_DATA_HIGH 0x3a0
-#define MV64360_SRAM_ERROR_DATA_PARITY 0x3a8
-
-/****************************************/
-/* SDRAM Configuration */
-/****************************************/
-
-#define MV64360_SDRAM_CONFIG 0x1400
-#define MV64360_D_UNIT_CONTROL_LOW 0x1404
-#define MV64360_D_UNIT_CONTROL_HIGH 0x1424
-#define MV64360_SDRAM_TIMING_CONTROL_LOW 0x1408
-#define MV64360_SDRAM_TIMING_CONTROL_HIGH 0x140c
-#define MV64360_SDRAM_ADDR_CONTROL 0x1410
-#define MV64360_SDRAM_OPEN_PAGES_CONTROL 0x1414
-#define MV64360_SDRAM_OPERATION 0x1418
-#define MV64360_SDRAM_MODE 0x141c
-#define MV64360_EXTENDED_DRAM_MODE 0x1420
-#define MV64360_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430
-#define MV64360_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434
-#define MV64360_SDRAM_CROSS_BAR_TIMEOUT 0x1438
-#define MV64360_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0
-#define MV64360_SDRAM_DATA_PADS_CALIBRATION 0x14c4
-
-/****************************************/
-/* SDRAM Error Report */
-/****************************************/
-
-#define MV64360_SDRAM_ERROR_DATA_LOW 0x1444
-#define MV64360_SDRAM_ERROR_DATA_HIGH 0x1440
-#define MV64360_SDRAM_ERROR_ADDR 0x1450
-#define MV64360_SDRAM_RECEIVED_ECC 0x1448
-#define MV64360_SDRAM_CALCULATED_ECC 0x144c
-#define MV64360_SDRAM_ECC_CONTROL 0x1454
-#define MV64360_SDRAM_ECC_ERROR_COUNTER 0x1458
-
-/******************************************/
-/* Controlled Delay Line (CDL) Registers */
-/******************************************/
-
-#define MV64360_DFCDL_CONFIG0 0x1480
-#define MV64360_DFCDL_CONFIG1 0x1484
-#define MV64360_DLL_WRITE 0x1488
-#define MV64360_DLL_READ 0x148c
-#define MV64360_SRAM_ADDR 0x1490
-#define MV64360_SRAM_DATA0 0x1494
-#define MV64360_SRAM_DATA1 0x1498
-#define MV64360_SRAM_DATA2 0x149c
-#define MV64360_DFCL_PROBE 0x14a0
-
-/******************************************/
-/* Debug Registers */
-/******************************************/
-
-#define MV64360_DUNIT_DEBUG_LOW 0x1460
-#define MV64360_DUNIT_DEBUG_HIGH 0x1464
-#define MV64360_DUNIT_MMASK 0X1b40
-
-/****************************************/
-/* Device Parameters */
-/****************************************/
-
-#define MV64360_DEVICE_BANK0_PARAMETERS 0x45c
-#define MV64360_DEVICE_BANK1_PARAMETERS 0x460
-#define MV64360_DEVICE_BANK2_PARAMETERS 0x464
-#define MV64360_DEVICE_BANK3_PARAMETERS 0x468
-#define MV64360_DEVICE_BOOT_BANK_PARAMETERS 0x46c
-#define MV64360_DEVICE_INTERFACE_CONTROL 0x4c0
-#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8
-#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc
-#define MV64360_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4
-
-/****************************************/
-/* Device interrupt registers */
-/****************************************/
-
-#define MV64360_DEVICE_INTERRUPT_CAUSE 0x4d0
-#define MV64360_DEVICE_INTERRUPT_MASK 0x4d4
-#define MV64360_DEVICE_ERROR_ADDR 0x4d8
-#define MV64360_DEVICE_ERROR_DATA 0x4dc
-#define MV64360_DEVICE_ERROR_PARITY 0x4e0
-
-/****************************************/
-/* Device debug registers */
-/****************************************/
-
-#define MV64360_DEVICE_DEBUG_LOW 0x4e4
-#define MV64360_DEVICE_DEBUG_HIGH 0x4e8
-#define MV64360_RUNIT_MMASK 0x4f0
-
-/****************************************/
-/* PCI Slave Address Decoding registers */
-/****************************************/
-
-#define MV64360_PCI_0_CS_0_BANK_SIZE 0xc08
-#define MV64360_PCI_1_CS_0_BANK_SIZE 0xc88
-#define MV64360_PCI_0_CS_1_BANK_SIZE 0xd08
-#define MV64360_PCI_1_CS_1_BANK_SIZE 0xd88
-#define MV64360_PCI_0_CS_2_BANK_SIZE 0xc0c
-#define MV64360_PCI_1_CS_2_BANK_SIZE 0xc8c
-#define MV64360_PCI_0_CS_3_BANK_SIZE 0xd0c
-#define MV64360_PCI_1_CS_3_BANK_SIZE 0xd8c
-#define MV64360_PCI_0_DEVCS_0_BANK_SIZE 0xc10
-#define MV64360_PCI_1_DEVCS_0_BANK_SIZE 0xc90
-#define MV64360_PCI_0_DEVCS_1_BANK_SIZE 0xd10
-#define MV64360_PCI_1_DEVCS_1_BANK_SIZE 0xd90
-#define MV64360_PCI_0_DEVCS_2_BANK_SIZE 0xd18
-#define MV64360_PCI_1_DEVCS_2_BANK_SIZE 0xd98
-#define MV64360_PCI_0_DEVCS_3_BANK_SIZE 0xc14
-#define MV64360_PCI_1_DEVCS_3_BANK_SIZE 0xc94
-#define MV64360_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14
-#define MV64360_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94
-#define MV64360_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c
-#define MV64360_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c
-#define MV64360_PCI_0_P2P_MEM1_BAR_SIZE 0xd20
-#define MV64360_PCI_1_P2P_MEM1_BAR_SIZE 0xda0
-#define MV64360_PCI_0_P2P_I_O_BAR_SIZE 0xd24
-#define MV64360_PCI_1_P2P_I_O_BAR_SIZE 0xda4
-#define MV64360_PCI_0_CPU_BAR_SIZE 0xd28
-#define MV64360_PCI_1_CPU_BAR_SIZE 0xda8
-#define MV64360_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00
-#define MV64360_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80
-#define MV64360_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c
-#define MV64360_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c
-#define MV64360_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c
-#define MV64360_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc
-#define MV64360_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48
-#define MV64360_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8
-#define MV64360_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48
-#define MV64360_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8
-#define MV64360_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c
-#define MV64360_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc
-#define MV64360_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c
-#define MV64360_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc
-#define MV64360_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04
-#define MV64360_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84
-#define MV64360_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08
-#define MV64360_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88
-#define MV64360_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C
-#define MV64360_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C
-#define MV64360_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10
-#define MV64360_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90
-#define MV64360_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50
-#define MV64360_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0
-#define MV64360_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50
-#define MV64360_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0
-#define MV64360_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58
-#define MV64360_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8
-#define MV64360_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54
-#define MV64360_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4
-#define MV64360_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54
-#define MV64360_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4
-#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c
-#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc
-#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60
-#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0
-#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64
-#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4
-#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68
-#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8
-#define MV64360_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c
-#define MV64360_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec
-#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70
-#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0
-#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74
-#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4
-#define MV64360_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00
-#define MV64360_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80
-#define MV64360_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38
-#define MV64360_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8
-#define MV64360_PCI_0_ADDR_DECODE_CONTROL 0xd3c
-#define MV64360_PCI_1_ADDR_DECODE_CONTROL 0xdbc
-#define MV64360_PCI_0_HEADERS_RETARGET_CONTROL 0xF40
-#define MV64360_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0
-#define MV64360_PCI_0_HEADERS_RETARGET_BASE 0xF44
-#define MV64360_PCI_1_HEADERS_RETARGET_BASE 0xFc4
-#define MV64360_PCI_0_HEADERS_RETARGET_HIGH 0xF48
-#define MV64360_PCI_1_HEADERS_RETARGET_HIGH 0xFc8
-
-/***********************************/
-/* PCI Control Register Map */
-/***********************************/
-
-#define MV64360_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20
-#define MV64360_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0
-#define MV64360_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C
-#define MV64360_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C
-#define MV64360_PCI_0_COMMAND 0xc00
-#define MV64360_PCI_1_COMMAND 0xc80
-#define MV64360_PCI_0_MODE 0xd00
-#define MV64360_PCI_1_MODE 0xd80
-#define MV64360_PCI_0_RETRY 0xc04
-#define MV64360_PCI_1_RETRY 0xc84
-#define MV64360_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04
-#define MV64360_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84
-#define MV64360_PCI_0_MSI_TRIGGER_TIMER 0xc38
-#define MV64360_PCI_1_MSI_TRIGGER_TIMER 0xcb8
-#define MV64360_PCI_0_ARBITER_CONTROL 0x1d00
-#define MV64360_PCI_1_ARBITER_CONTROL 0x1d80
-#define MV64360_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08
-#define MV64360_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88
-#define MV64360_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c
-#define MV64360_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c
-#define MV64360_PCI_0_CROSS_BAR_TIMEOUT 0x1d04
-#define MV64360_PCI_1_CROSS_BAR_TIMEOUT 0x1d84
-#define MV64360_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18
-#define MV64360_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98
-#define MV64360_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10
-#define MV64360_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90
-#define MV64360_PCI_0_P2P_CONFIG 0x1d14
-#define MV64360_PCI_1_P2P_CONFIG 0x1d94
-
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04
-#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14
-#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24
-#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34
-#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44
-#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50
-#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54
-#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58
-
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84
-#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94
-#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
-#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
-#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
-#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0
-#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
-#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8
-
-/****************************************/
-/* PCI Configuration Access Registers */
-/****************************************/
-
-#define MV64360_PCI_0_CONFIG_ADDR 0xcf8
-#define MV64360_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc
-#define MV64360_PCI_1_CONFIG_ADDR 0xc78
-#define MV64360_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c
-#define MV64360_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34
-#define MV64360_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4
-
-/****************************************/
-/* PCI Error Report Registers */
-/****************************************/
-
-#define MV64360_PCI_0_SERR_MASK 0xc28
-#define MV64360_PCI_1_SERR_MASK 0xca8
-#define MV64360_PCI_0_ERROR_ADDR_LOW 0x1d40
-#define MV64360_PCI_1_ERROR_ADDR_LOW 0x1dc0
-#define MV64360_PCI_0_ERROR_ADDR_HIGH 0x1d44
-#define MV64360_PCI_1_ERROR_ADDR_HIGH 0x1dc4
-#define MV64360_PCI_0_ERROR_ATTRIBUTE 0x1d48
-#define MV64360_PCI_1_ERROR_ATTRIBUTE 0x1dc8
-#define MV64360_PCI_0_ERROR_COMMAND 0x1d50
-#define MV64360_PCI_1_ERROR_COMMAND 0x1dd0
-#define MV64360_PCI_0_ERROR_CAUSE 0x1d58
-#define MV64360_PCI_1_ERROR_CAUSE 0x1dd8
-#define MV64360_PCI_0_ERROR_MASK 0x1d5c
-#define MV64360_PCI_1_ERROR_MASK 0x1ddc
-
-/****************************************/
-/* PCI Debug Registers */
-/****************************************/
-
-#define MV64360_PCI_0_MMASK 0X1D24
-#define MV64360_PCI_1_MMASK 0X1DA4
-
-/*********************************************/
-/* PCI Configuration, Function 0, Registers */
-/*********************************************/
-
-#define MV64360_PCI_DEVICE_AND_VENDOR_ID 0x000
-#define MV64360_PCI_STATUS_AND_COMMAND 0x004
-#define MV64360_PCI_CLASS_CODE_AND_REVISION_ID 0x008
-#define MV64360_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
-
-#define MV64360_PCI_SCS_0_BASE_ADDR_LOW 0x010
-#define MV64360_PCI_SCS_0_BASE_ADDR_HIGH 0x014
-#define MV64360_PCI_SCS_1_BASE_ADDR_LOW 0x018
-#define MV64360_PCI_SCS_1_BASE_ADDR_HIGH 0x01C
-#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020
-#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024
-#define MV64360_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c
-#define MV64360_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030
-#define MV64360_PCI_CAPABILTY_LIST_POINTER 0x034
-#define MV64360_PCI_INTERRUPT_PIN_AND_LINE 0x03C
- /* capability list */
-#define MV64360_PCI_POWER_MANAGEMENT_CAPABILITY 0x040
-#define MV64360_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
-#define MV64360_PCI_VPD_ADDR 0x048
-#define MV64360_PCI_VPD_DATA 0x04c
-#define MV64360_PCI_MSI_MESSAGE_CONTROL 0x050
-#define MV64360_PCI_MSI_MESSAGE_ADDR 0x054
-#define MV64360_PCI_MSI_MESSAGE_UPPER_ADDR 0x058
-#define MV64360_PCI_MSI_MESSAGE_DATA 0x05c
-#define MV64360_PCI_X_COMMAND 0x060
-#define MV64360_PCI_X_STATUS 0x064
-#define MV64360_PCI_COMPACT_PCI_HOT_SWAP 0x068
-
-/***********************************************/
-/* PCI Configuration, Function 1, Registers */
-/***********************************************/
-
-#define MV64360_PCI_SCS_2_BASE_ADDR_LOW 0x110
-#define MV64360_PCI_SCS_2_BASE_ADDR_HIGH 0x114
-#define MV64360_PCI_SCS_3_BASE_ADDR_LOW 0x118
-#define MV64360_PCI_SCS_3_BASE_ADDR_HIGH 0x11c
-#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120
-#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124
-
-/***********************************************/
-/* PCI Configuration, Function 2, Registers */
-/***********************************************/
-
-#define MV64360_PCI_DEVCS_0_BASE_ADDR_LOW 0x210
-#define MV64360_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214
-#define MV64360_PCI_DEVCS_1_BASE_ADDR_LOW 0x218
-#define MV64360_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c
-#define MV64360_PCI_DEVCS_2_BASE_ADDR_LOW 0x220
-#define MV64360_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224
-
-/***********************************************/
-/* PCI Configuration, Function 3, Registers */
-/***********************************************/
-
-#define MV64360_PCI_DEVCS_3_BASE_ADDR_LOW 0x310
-#define MV64360_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314
-#define MV64360_PCI_BOOT_CS_BASE_ADDR_LOW 0x318
-#define MV64360_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c
-#define MV64360_PCI_CPU_BASE_ADDR_LOW 0x220
-#define MV64360_PCI_CPU_BASE_ADDR_HIGH 0x224
-
-/***********************************************/
-/* PCI Configuration, Function 4, Registers */
-/***********************************************/
-
-#define MV64360_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410
-#define MV64360_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414
-#define MV64360_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418
-#define MV64360_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c
-#define MV64360_PCI_P2P_I_O_BASE_ADDR 0x420
-#define MV64360_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424
-
-/****************************************/
-/* Messaging Unit Registers (I20) */
-/****************************************/
-
-#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010
-#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C
-#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020
-#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024
-#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028
-#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C
-#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030
-#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034
-#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040
-#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044
-#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050
-#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054
-#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060
-#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064
-#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068
-#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C
-#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070
-#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074
-#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8
-#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC
-
-#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090
-#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C
-#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0
-#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4
-#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8
-#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC
-#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0
-#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4
-#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0
-#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4
-#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0
-#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4
-#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0
-#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4
-#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8
-#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC
-#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0
-#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4
-#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078
-#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C
-
-#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10
-#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C
-#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20
-#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24
-#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28
-#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C
-#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30
-#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34
-#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40
-#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44
-#define MV64360_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50
-#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54
-#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60
-#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64
-#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68
-#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C
-#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70
-#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74
-#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8
-#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC
-#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90
-#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98
-#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C
-#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0
-#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4
-#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8
-#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC
-#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0
-#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4
-#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0
-#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4
-#define MV64360_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0
-#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4
-#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0
-#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4
-#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8
-#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC
-#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0
-#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4
-#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78
-#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C
-
-/****************************************/
-/* Ethernet Unit Registers */
-/****************************************/
-
-#define MV64360_ETH_PHY_ADDR_REG 0x2000
-#define MV64360_ETH_SMI_REG 0x2004
-#define MV64360_ETH_UNIT_DEFAULT_ADDR_REG 0x2008
-#define MV64360_ETH_UNIT_DEFAULTID_REG 0x200c
-#define MV64360_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080
-#define MV64360_ETH_UNIT_INTERRUPT_MASK_REG 0x2084
-#define MV64360_ETH_UNIT_INTERNAL_USE_REG 0x24fc
-#define MV64360_ETH_UNIT_ERROR_ADDR_REG 0x2094
-#define MV64360_ETH_BAR_0 0x2200
-#define MV64360_ETH_BAR_1 0x2208
-#define MV64360_ETH_BAR_2 0x2210
-#define MV64360_ETH_BAR_3 0x2218
-#define MV64360_ETH_BAR_4 0x2220
-#define MV64360_ETH_BAR_5 0x2228
-#define MV64360_ETH_SIZE_REG_0 0x2204
-#define MV64360_ETH_SIZE_REG_1 0x220c
-#define MV64360_ETH_SIZE_REG_2 0x2214
-#define MV64360_ETH_SIZE_REG_3 0x221c
-#define MV64360_ETH_SIZE_REG_4 0x2224
-#define MV64360_ETH_SIZE_REG_5 0x222c
-#define MV64360_ETH_HEADERS_RETARGET_BASE_REG 0x2230
-#define MV64360_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234
-#define MV64360_ETH_HIGH_ADDR_REMAP_REG_0 0x2280
-#define MV64360_ETH_HIGH_ADDR_REMAP_REG_1 0x2284
-#define MV64360_ETH_HIGH_ADDR_REMAP_REG_2 0x2288
-#define MV64360_ETH_HIGH_ADDR_REMAP_REG_3 0x228c
-#define MV64360_ETH_BASE_ADDR_ENABLE_REG 0x2290
-#define MV64360_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2))
-#define MV64360_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7))
-#define MV64360_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10))
-#define MV64360_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10))
-#define MV64360_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10))
-#define MV64360_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10))
-#define MV64360_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10))
-#define MV64360_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10))
-#define MV64360_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10))
-#define MV64360_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10))
-#define MV64360_ETH_DSCP_0(port) (0x2420 + (port<<10))
-#define MV64360_ETH_DSCP_1(port) (0x2424 + (port<<10))
-#define MV64360_ETH_DSCP_2(port) (0x2428 + (port<<10))
-#define MV64360_ETH_DSCP_3(port) (0x242c + (port<<10))
-#define MV64360_ETH_DSCP_4(port) (0x2430 + (port<<10))
-#define MV64360_ETH_DSCP_5(port) (0x2434 + (port<<10))
-#define MV64360_ETH_DSCP_6(port) (0x2438 + (port<<10))
-#define MV64360_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10))
-#define MV64360_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10))
-#define MV64360_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10))
-#define MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10))
-#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10))
-#define MV64360_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10))
-#define MV64360_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10))
-#define MV64360_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10))
-#define MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10))
-#define MV64360_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10))
-#define MV64360_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10))
-#define MV64360_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
-#define MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
-#define MV64360_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
-#define MV64360_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10)
-#define MV64360_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
-#define MV64360_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
-#define MV64360_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
-#define MV64360_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10))
-#define MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10))
-#define MV64360_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10))
-#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10))
-#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10))
-#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10))
-#define MV64360_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10))
-#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10))
-#define MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10))
-#define MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
-#define MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
-
-/*******************************************/
-/* CUNIT Registers */
-/*******************************************/
-
- /* Address Decoding Register Map */
-
-#define MV64360_CUNIT_BASE_ADDR_REG0 0xf200
-#define MV64360_CUNIT_BASE_ADDR_REG1 0xf208
-#define MV64360_CUNIT_BASE_ADDR_REG2 0xf210
-#define MV64360_CUNIT_BASE_ADDR_REG3 0xf218
-#define MV64360_CUNIT_SIZE0 0xf204
-#define MV64360_CUNIT_SIZE1 0xf20c
-#define MV64360_CUNIT_SIZE2 0xf214
-#define MV64360_CUNIT_SIZE3 0xf21c
-#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240
-#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244
-#define MV64360_CUNIT_BASE_ADDR_ENABLE_REG 0xf250
-#define MV64360_MPSC0_ACCESS_PROTECTION_REG 0xf254
-#define MV64360_MPSC1_ACCESS_PROTECTION_REG 0xf258
-#define MV64360_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C
-
- /* Error Report Registers */
-
-#define MV64360_CUNIT_INTERRUPT_CAUSE_REG 0xf310
-#define MV64360_CUNIT_INTERRUPT_MASK_REG 0xf314
-#define MV64360_CUNIT_ERROR_ADDR 0xf318
-
- /* Cunit Control Registers */
-
-#define MV64360_CUNIT_ARBITER_CONTROL_REG 0xf300
-#define MV64360_CUNIT_CONFIG_REG 0xb40c
-#define MV64360_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304
-
- /* Cunit Debug Registers */
-
-#define MV64360_CUNIT_DEBUG_LOW 0xf340
-#define MV64360_CUNIT_DEBUG_HIGH 0xf344
-#define MV64360_CUNIT_MMASK 0xf380
-
- /* Cunit Base Address Enable Window Bits*/
-#define MV64360_CUNIT_BASE_ADDR_WIN_0_BIT 0x0
-#define MV64360_CUNIT_BASE_ADDR_WIN_1_BIT 0x1
-#define MV64360_CUNIT_BASE_ADDR_WIN_2_BIT 0x2
-#define MV64360_CUNIT_BASE_ADDR_WIN_3_BIT 0x3
-
- /* MPSCs Clocks Routing Registers */
-
-#define MV64360_MPSC_ROUTING_REG 0xb400
-#define MV64360_MPSC_RX_CLOCK_ROUTING_REG 0xb404
-#define MV64360_MPSC_TX_CLOCK_ROUTING_REG 0xb408
-
- /* MPSCs Interrupts Registers */
-
-#define MV64360_MPSC_CAUSE_REG(port) (0xb804 + (port<<3))
-#define MV64360_MPSC_MASK_REG(port) (0xb884 + (port<<3))
-
-#define MV64360_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12))
-#define MV64360_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12))
-#define MV64360_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12))
-#define MV64360_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12))
-
- /* MPSC0 Registers */
-
-
-/***************************************/
-/* SDMA Registers */
-/***************************************/
-
-#define MV64360_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13))
-#define MV64360_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13))
-#define MV64360_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13))
-#define MV64360_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13))
-#define MV64360_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13))
-
-#define MV64360_SDMA_CAUSE_REG 0xb800
-#define MV64360_SDMA_MASK_REG 0xb880
-
-
-/****************************************/
-/* SDMA Address Space Targets */
-/****************************************/
-
-#define MV64360_SDMA_DRAM_CS_0_TARGET 0x0e00
-#define MV64360_SDMA_DRAM_CS_1_TARGET 0x0d00
-#define MV64360_SDMA_DRAM_CS_2_TARGET 0x0b00
-#define MV64360_SDMA_DRAM_CS_3_TARGET 0x0700
-
-#define MV64360_SDMA_DEV_CS_0_TARGET 0x1e01
-#define MV64360_SDMA_DEV_CS_1_TARGET 0x1d01
-#define MV64360_SDMA_DEV_CS_2_TARGET 0x1b01
-#define MV64360_SDMA_DEV_CS_3_TARGET 0x1701
-
-#define MV64360_SDMA_BOOT_CS_TARGET 0x0f00
-
-#define MV64360_SDMA_SRAM_TARGET 0x0003
-#define MV64360_SDMA_60X_BUS_TARGET 0x4003
-
-#define MV64360_PCI_0_TARGET 0x0003
-#define MV64360_PCI_1_TARGET 0x0004
-
-
-/* Devices BAR and size registers */
-
-#define MV64360_DEV_CS0_BASE_ADDR 0x028
-#define MV64360_DEV_CS0_SIZE 0x030
-#define MV64360_DEV_CS1_BASE_ADDR 0x228
-#define MV64360_DEV_CS1_SIZE 0x230
-#define MV64360_DEV_CS2_BASE_ADDR 0x248
-#define MV64360_DEV_CS2_SIZE 0x250
-#define MV64360_DEV_CS3_BASE_ADDR 0x038
-#define MV64360_DEV_CS3_SIZE 0x040
-#define MV64360_BOOTCS_BASE_ADDR 0x238
-#define MV64360_BOOTCS_SIZE 0x240
-
-/* SDMA Window access protection */
-#define MV64360_SDMA_WIN_ACCESS_NOT_ALLOWED 0
-#define MV64360_SDMA_WIN_ACCESS_READ_ONLY 1
-#define MV64360_SDMA_WIN_ACCESS_FULL 2
-
-/* BRG Interrupts */
-
-#define MV64360_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3))
-#define MV64360_BRG_BAUDE_TUNING_REG(brg) (0xb204 + (brg<<3))
-#define MV64360_BRG_CAUSE_REG 0xb834
-#define MV64360_BRG_MASK_REG 0xb8b4
-
-/****************************************/
-/* DMA Channel Control */
-/****************************************/
-
-#define MV64360_DMA_CHANNEL0_CONTROL 0x840
-#define MV64360_DMA_CHANNEL0_CONTROL_HIGH 0x880
-#define MV64360_DMA_CHANNEL1_CONTROL 0x844
-#define MV64360_DMA_CHANNEL1_CONTROL_HIGH 0x884
-#define MV64360_DMA_CHANNEL2_CONTROL 0x848
-#define MV64360_DMA_CHANNEL2_CONTROL_HIGH 0x888
-#define MV64360_DMA_CHANNEL3_CONTROL 0x84C
-#define MV64360_DMA_CHANNEL3_CONTROL_HIGH 0x88C
-
-
-/****************************************/
-/* IDMA Registers */
-/****************************************/
-
-#define MV64360_DMA_CHANNEL0_BYTE_COUNT 0x800
-#define MV64360_DMA_CHANNEL1_BYTE_COUNT 0x804
-#define MV64360_DMA_CHANNEL2_BYTE_COUNT 0x808
-#define MV64360_DMA_CHANNEL3_BYTE_COUNT 0x80C
-#define MV64360_DMA_CHANNEL0_SOURCE_ADDR 0x810
-#define MV64360_DMA_CHANNEL1_SOURCE_ADDR 0x814
-#define MV64360_DMA_CHANNEL2_SOURCE_ADDR 0x818
-#define MV64360_DMA_CHANNEL3_SOURCE_ADDR 0x81c
-#define MV64360_DMA_CHANNEL0_DESTINATION_ADDR 0x820
-#define MV64360_DMA_CHANNEL1_DESTINATION_ADDR 0x824
-#define MV64360_DMA_CHANNEL2_DESTINATION_ADDR 0x828
-#define MV64360_DMA_CHANNEL3_DESTINATION_ADDR 0x82C
-#define MV64360_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830
-#define MV64360_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834
-#define MV64360_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838
-#define MV64360_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C
-#define MV64360_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870
-#define MV64360_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874
-#define MV64360_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878
-#define MV64360_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C
-
- /* IDMA Address Decoding Base Address Registers */
-
-#define MV64360_DMA_BASE_ADDR_REG0 0xa00
-#define MV64360_DMA_BASE_ADDR_REG1 0xa08
-#define MV64360_DMA_BASE_ADDR_REG2 0xa10
-#define MV64360_DMA_BASE_ADDR_REG3 0xa18
-#define MV64360_DMA_BASE_ADDR_REG4 0xa20
-#define MV64360_DMA_BASE_ADDR_REG5 0xa28
-#define MV64360_DMA_BASE_ADDR_REG6 0xa30
-#define MV64360_DMA_BASE_ADDR_REG7 0xa38
-
- /* IDMA Address Decoding Size Address Register */
-
-#define MV64360_DMA_SIZE_REG0 0xa04
-#define MV64360_DMA_SIZE_REG1 0xa0c
-#define MV64360_DMA_SIZE_REG2 0xa14
-#define MV64360_DMA_SIZE_REG3 0xa1c
-#define MV64360_DMA_SIZE_REG4 0xa24
-#define MV64360_DMA_SIZE_REG5 0xa2c
-#define MV64360_DMA_SIZE_REG6 0xa34
-#define MV64360_DMA_SIZE_REG7 0xa3C
-
- /* IDMA Address Decoding High Address Remap and Access
- Protection Registers */
-
-#define MV64360_DMA_HIGH_ADDR_REMAP_REG0 0xa60
-#define MV64360_DMA_HIGH_ADDR_REMAP_REG1 0xa64
-#define MV64360_DMA_HIGH_ADDR_REMAP_REG2 0xa68
-#define MV64360_DMA_HIGH_ADDR_REMAP_REG3 0xa6C
-#define MV64360_DMA_BASE_ADDR_ENABLE_REG 0xa80
-#define MV64360_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70
-#define MV64360_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74
-#define MV64360_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78
-#define MV64360_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c
-#define MV64360_DMA_ARBITER_CONTROL 0x860
-#define MV64360_DMA_CROSS_BAR_TIMEOUT 0x8d0
-
- /* IDMA Headers Retarget Registers */
-
-#define MV64360_DMA_HEADERS_RETARGET_CONTROL 0xa84
-#define MV64360_DMA_HEADERS_RETARGET_BASE 0xa88
-
- /* IDMA Interrupt Register */
-
-#define MV64360_DMA_INTERRUPT_CAUSE_REG 0x8c0
-#define MV64360_DMA_INTERRUPT_CAUSE_MASK 0x8c4
-#define MV64360_DMA_ERROR_ADDR 0x8c8
-#define MV64360_DMA_ERROR_SELECT 0x8cc
-
- /* IDMA Debug Register ( for internal use ) */
-
-#define MV64360_DMA_DEBUG_LOW 0x8e0
-#define MV64360_DMA_DEBUG_HIGH 0x8e4
-#define MV64360_DMA_SPARE 0xA8C
-
-/****************************************/
-/* Timer_Counter */
-/****************************************/
-
-#define MV64360_TIMER_COUNTER0 0x850
-#define MV64360_TIMER_COUNTER1 0x854
-#define MV64360_TIMER_COUNTER2 0x858
-#define MV64360_TIMER_COUNTER3 0x85C
-#define MV64360_TIMER_COUNTER_0_3_CONTROL 0x864
-#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868
-#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c
-
-/****************************************/
-/* Watchdog registers */
-/****************************************/
-
-#define MV64360_WATCHDOG_CONFIG_REG 0xb410
-#define MV64360_WATCHDOG_VALUE_REG 0xb414
-
-/****************************************/
-/* I2C Registers */
-/****************************************/
-
-#define MV64360_I2C_SLAVE_ADDR 0xc000
-#define MV64360_I2C_EXTENDED_SLAVE_ADDR 0xc010
-#define MV64360_I2C_DATA 0xc004
-#define MV64360_I2C_CONTROL 0xc008
-#define MV64360_I2C_STATUS_BAUDE_RATE 0xc00C
-#define MV64360_I2C_SOFT_RESET 0xc01c
-
-/****************************************/
-/* GPP Interface Registers */
-/****************************************/
-
-#define MV64360_GPP_IO_CONTROL 0xf100
-#define MV64360_GPP_LEVEL_CONTROL 0xf110
-#define MV64360_GPP_VALUE 0xf104
-#define MV64360_GPP_INTERRUPT_CAUSE 0xf108
-#define MV64360_GPP_INTERRUPT_MASK0 0xf10c
-#define MV64360_GPP_INTERRUPT_MASK1 0xf114
-#define MV64360_GPP_VALUE_SET 0xf118
-#define MV64360_GPP_VALUE_CLEAR 0xf11c
-
-/****************************************/
-/* Interrupt Controller Registers */
-/****************************************/
-
-/****************************************/
-/* Interrupts */
-/****************************************/
-
-#define MV64360_MAIN_INTERRUPT_CAUSE_LOW 0x004
-#define MV64360_MAIN_INTERRUPT_CAUSE_HIGH 0x00c
-#define MV64360_CPU_INTERRUPT0_MASK_LOW 0x014
-#define MV64360_CPU_INTERRUPT0_MASK_HIGH 0x01c
-#define MV64360_CPU_INTERRUPT0_SELECT_CAUSE 0x024
-#define MV64360_CPU_INTERRUPT1_MASK_LOW 0x034
-#define MV64360_CPU_INTERRUPT1_MASK_HIGH 0x03c
-#define MV64360_CPU_INTERRUPT1_SELECT_CAUSE 0x044
-#define MV64360_INTERRUPT0_MASK_0_LOW 0x054
-#define MV64360_INTERRUPT0_MASK_0_HIGH 0x05c
-#define MV64360_INTERRUPT0_SELECT_CAUSE 0x064
-#define MV64360_INTERRUPT1_MASK_0_LOW 0x074
-#define MV64360_INTERRUPT1_MASK_0_HIGH 0x07c
-#define MV64360_INTERRUPT1_SELECT_CAUSE 0x084
-
-/****************************************/
-/* MPP Interface Registers */
-/****************************************/
-
-#define MV64360_MPP_CONTROL0 0xf000
-#define MV64360_MPP_CONTROL1 0xf004
-#define MV64360_MPP_CONTROL2 0xf008
-#define MV64360_MPP_CONTROL3 0xf00c
-
-/****************************************/
-/* Serial Initialization registers */
-/****************************************/
-
-#define MV64360_SERIAL_INIT_LAST_DATA 0xf324
-#define MV64360_SERIAL_INIT_CONTROL 0xf328
-#define MV64360_SERIAL_INIT_STATUS 0xf32c
-
-
-#endif /* __INCgt64360rh */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-/* PCI.c - PCI functions */
-
-
-#include <common.h>
-#ifdef CONFIG_PCI
-#include <pci.h>
-
-#include "../../Marvell/include/pci.h"
-
-#undef DEBUG
-#undef IDE_SET_NATIVE_MODE
-static unsigned int local_buses[] = { 0, 0 };
-
-static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
- {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
- {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
-};
-
-#ifdef CONFIG_USE_CPCIDVI
-typedef struct {
- unsigned int base;
- unsigned int init;
-} GT_CPCIDVI_ROM_T;
-
-static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0};
-#endif
-
-#ifdef DEBUG
-static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
-static void gt_pci_bus_mode_display (PCI_HOST host)
-{
- unsigned int mode;
-
-
- mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
- switch (mode) {
- case 0:
- printf ("PCI %d bus mode: Conventional PCI\n", host);
- break;
- case 1:
- printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
- break;
- case 2:
- printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
- break;
- case 3:
- printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
- break;
- default:
- printf ("Unknown BUS %d\n", mode);
- }
-}
-#endif
-
-static const unsigned int pci_p2p_configuration_reg[] = {
- PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
-};
-
-static const unsigned int pci_configuration_address[] = {
- PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
-};
-
-static const unsigned int pci_configuration_data[] = {
- PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
- PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
-};
-
-static const unsigned int pci_error_cause_reg[] = {
- PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
-};
-
-static const unsigned int pci_arbiter_control[] = {
- PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
-};
-
-static const unsigned int pci_address_space_en[] = {
- PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
-};
-
-static const unsigned int pci_snoop_control_base_0_low[] = {
- PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
-};
-static const unsigned int pci_snoop_control_top_0[] = {
- PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
-};
-
-static const unsigned int pci_access_control_base_0_low[] = {
- PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
-};
-static const unsigned int pci_access_control_top_0[] = {
- PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
-};
-
-static const unsigned int pci_scs_bank_size[2][4] = {
- {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
- PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
- {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
- PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
-};
-
-static const unsigned int pci_p2p_configuration[] = {
- PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
-};
-
-
-/********************************************************************
-* pciWriteConfigReg - Write to a PCI configuration register
-* - Make sure the GT is configured as a master before writing
-* to another device on the PCI.
-* - The function takes care of Big/Little endian conversion.
-*
-*
-* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec
-* (or any other PCI device spec)
-* pciDevNum: The device number needs to be addressed.
-*
-* Configuration Address 0xCF8:
-*
-* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
-* |congif|Reserved| Bus |Device|Function|Register|00|
-* |Enable| |Number|Number| Number | Number | | <=field Name
-*
-*********************************************************************/
-void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
- unsigned int pciDevNum, unsigned int data)
-{
- volatile unsigned int DataForAddrReg;
- unsigned int functionNum;
- unsigned int busNum = 0;
- unsigned int addr;
-
- if (pciDevNum > 32) /* illegal device Number */
- return;
- if (pciDevNum == SELF) { /* configure our configuration space. */
- pciDevNum =
- (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
- 0x1f;
- busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
- 0xff0000;
- }
- functionNum = regOffset & 0x00000700;
- pciDevNum = pciDevNum << 11;
- regOffset = regOffset & 0xfc;
- DataForAddrReg =
- (regOffset | pciDevNum | functionNum | busNum) | BIT31;
- GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
- GT_REG_READ (pci_configuration_address[host], &addr);
- if (addr != DataForAddrReg)
- return;
- GT_REG_WRITE (pci_configuration_data[host], data);
-}
-
-/********************************************************************
-* pciReadConfigReg - Read from a PCI0 configuration register
-* - Make sure the GT is configured as a master before reading
-* from another device on the PCI.
-* - The function takes care of Big/Little endian conversion.
-* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
-* spec)
-* pciDevNum: The device number needs to be addressed.
-* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
-* cause register to make sure the data is valid
-*
-* Configuration Address 0xCF8:
-*
-* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
-* |congif|Reserved| Bus |Device|Function|Register|00|
-* |Enable| |Number|Number| Number | Number | | <=field Name
-*
-*********************************************************************/
-unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
- unsigned int pciDevNum)
-{
- volatile unsigned int DataForAddrReg;
- unsigned int data;
- unsigned int functionNum;
- unsigned int busNum = 0;
-
- if (pciDevNum > 32) /* illegal device Number */
- return 0xffffffff;
- if (pciDevNum == SELF) { /* configure our configuration space. */
- pciDevNum =
- (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
- 0x1f;
- busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
- 0xff0000;
- }
- functionNum = regOffset & 0x00000700;
- pciDevNum = pciDevNum << 11;
- regOffset = regOffset & 0xfc;
- DataForAddrReg =
- (regOffset | pciDevNum | functionNum | busNum) | BIT31;
- GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
- GT_REG_READ (pci_configuration_address[host], &data);
- if (data != DataForAddrReg)
- return 0xffffffff;
- GT_REG_READ (pci_configuration_data[host], &data);
- return data;
-}
-
-/********************************************************************
-* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
-* the agent is placed on another Bus. For more
-* information read P2P in the PCI spec.
-*
-* Inputs: unsigned int regOffset - The register offset as it apears in the
-* GT spec (or any other PCI device spec).
-* unsigned int pciDevNum - The device number needs to be addressed.
-* unsigned int busNum - On which bus does the Target agent connect
-* to.
-* unsigned int data - data to be written.
-*
-* Configuration Address 0xCF8:
-*
-* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
-* |congif|Reserved| Bus |Device|Function|Register|01|
-* |Enable| |Number|Number| Number | Number | | <=field Name
-*
-* The configuration Address is configure as type-I (bits[1:0] = '01') due to
-* PCI spec referring to P2P.
-*
-*********************************************************************/
-void pciOverBridgeWriteConfigReg (PCI_HOST host,
- unsigned int regOffset,
- unsigned int pciDevNum,
- unsigned int busNum, unsigned int data)
-{
- unsigned int DataForReg;
- unsigned int functionNum;
-
- functionNum = regOffset & 0x00000700;
- pciDevNum = pciDevNum << 11;
- regOffset = regOffset & 0xff;
- busNum = busNum << 16;
- if (pciDevNum == SELF) { /* This board */
- DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
- } else {
- DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
- BIT31 | BIT0;
- }
- GT_REG_WRITE (pci_configuration_address[host], DataForReg);
- GT_REG_WRITE (pci_configuration_data[host], data);
-}
-
-
-/********************************************************************
-* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where
-* the agent target locate on another PCI bus.
-* - Make sure the GT is configured as a master
-* before reading from another device on the PCI.
-* - The function takes care of Big/Little endian
-* conversion.
-* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
-* spec). (configuration register offset.)
-* pciDevNum: The device number needs to be addressed.
-* busNum: the Bus number where the agent is place.
-* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
-* cause register to make sure the data is valid
-*
-* Configuration Address 0xCF8:
-*
-* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
-* |congif|Reserved| Bus |Device|Function|Register|01|
-* |Enable| |Number|Number| Number | Number | | <=field Name
-*
-*********************************************************************/
-unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
- unsigned int regOffset,
- unsigned int pciDevNum,
- unsigned int busNum)
-{
- unsigned int DataForReg;
- unsigned int data;
- unsigned int functionNum;
-
- functionNum = regOffset & 0x00000700;
- pciDevNum = pciDevNum << 11;
- regOffset = regOffset & 0xff;
- busNum = busNum << 16;
- if (pciDevNum == SELF) { /* This board */
- DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
- } else { /* agent on another bus */
-
- DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
- BIT0 | BIT31;
- }
- GT_REG_WRITE (pci_configuration_address[host], DataForReg);
- GT_REG_READ (pci_configuration_data[host], &data);
- return data;
-}
-
-
-/********************************************************************
-* pciGetRegOffset - Gets the register offset for this region config.
-*
-* INPUT: Bus, Region - The bus and region we ask for its base address.
-* OUTPUT: N/A
-* RETURNS: PCI register base address
-*********************************************************************/
-static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
-{
- switch (host) {
- case PCI_HOST0:
- switch (region) {
- case PCI_IO:
- return PCI_0I_O_LOW_DECODE_ADDRESS;
- case PCI_REGION0:
- return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
- case PCI_REGION1:
- return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
- case PCI_REGION2:
- return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
- case PCI_REGION3:
- return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
- }
- case PCI_HOST1:
- switch (region) {
- case PCI_IO:
- return PCI_1I_O_LOW_DECODE_ADDRESS;
- case PCI_REGION0:
- return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
- case PCI_REGION1:
- return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
- case PCI_REGION2:
- return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
- case PCI_REGION3:
- return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
- }
- }
- return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
-}
-
-static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
-{
- switch (host) {
- case PCI_HOST0:
- switch (region) {
- case PCI_IO:
- return PCI_0I_O_ADDRESS_REMAP;
- case PCI_REGION0:
- return PCI_0MEMORY0_ADDRESS_REMAP;
- case PCI_REGION1:
- return PCI_0MEMORY1_ADDRESS_REMAP;
- case PCI_REGION2:
- return PCI_0MEMORY2_ADDRESS_REMAP;
- case PCI_REGION3:
- return PCI_0MEMORY3_ADDRESS_REMAP;
- }
- case PCI_HOST1:
- switch (region) {
- case PCI_IO:
- return PCI_1I_O_ADDRESS_REMAP;
- case PCI_REGION0:
- return PCI_1MEMORY0_ADDRESS_REMAP;
- case PCI_REGION1:
- return PCI_1MEMORY1_ADDRESS_REMAP;
- case PCI_REGION2:
- return PCI_1MEMORY2_ADDRESS_REMAP;
- case PCI_REGION3:
- return PCI_1MEMORY3_ADDRESS_REMAP;
- }
- }
- return PCI_0MEMORY0_ADDRESS_REMAP;
-}
-
-/********************************************************************
-* pciGetBaseAddress - Gets the base address of a PCI.
-* - If the PCI size is 0 then this base address has no meaning!!!
-*
-*
-* INPUT: Bus, Region - The bus and region we ask for its base address.
-* OUTPUT: N/A
-* RETURNS: PCI base address.
-*********************************************************************/
-unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
-{
- unsigned int regBase;
- unsigned int regEnd;
- unsigned int regOffset = pciGetRegOffset (host, region);
-
- GT_REG_READ (regOffset, ®Base);
- GT_REG_READ (regOffset + 8, ®End);
-
- if (regEnd <= regBase)
- return 0xffffffff; /* ERROR !!! */
-
- regBase = regBase << 16;
- return regBase;
-}
-
-bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
- unsigned int bankBase, unsigned int bankLength)
-{
- unsigned int low = 0xfff;
- unsigned int high = 0x0;
- unsigned int regOffset = pciGetRegOffset (host, region);
- unsigned int remapOffset = pciGetRemapOffset (host, region);
-
- if (bankLength != 0) {
- low = (bankBase >> 16) & 0xffff;
- high = ((bankBase + bankLength) >> 16) - 1;
- }
-
- GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */
- GT_REG_WRITE (regOffset + 8, high);
-
- if (bankLength != 0) { /* must do AFTER writing maps */
- GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only.
- dont support upper 32
- in this driver */
- }
- return true;
-}
-
-unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
-{
- unsigned int low;
- unsigned int regOffset = pciGetRegOffset (host, region);
-
- GT_REG_READ (regOffset, &low);
- return (low & 0xffff) << 16;
-}
-
-unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
-{
- unsigned int low, high;
- unsigned int regOffset = pciGetRegOffset (host, region);
-
- GT_REG_READ (regOffset, &low);
- GT_REG_READ (regOffset + 8, &high);
- return ((high & 0xffff) + 1) << 16;
-}
-
-
-/* ronen - 7/Dec/03*/
-/********************************************************************
-* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
-* Inputs: one of the PCI BAR
-*********************************************************************/
-void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
-{
- RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
-}
-
-void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
-{
- SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
-}
-
-/********************************************************************
-* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
-*
-* Inputs: base and size of PCI SCS
-*********************************************************************/
-void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
- unsigned int pciDramBase, unsigned int pciDramSize)
-{
- /*ronen different function for 3rd bank. */
- unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
-
- pciDramBase = pciDramBase & 0xfffff000;
- pciDramBase = pciDramBase | (pciReadConfigReg (host,
- PCI_SCS_0_BASE_ADDRESS
- + offset,
- SELF) & 0x00000fff);
- pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
- pciDramBase);
- if (pciDramSize == 0)
- pciDramSize++;
- GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
- gtPciEnableInternalBAR (host, bank);
-}
-
-/********************************************************************
-* pciSetRegionFeatures - This function modifys one of the 8 regions with
-* feature bits given as an input.
-* - Be advised to check the spec before modifying them.
-* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
-* unsigned int features - See file: pci.h there are defintion for those
-* region features.
-* unsigned int baseAddress - The region base Address.
-* unsigned int topAddress - The region top Address.
-* Returns: false if one of the parameters is erroneous true otherwise.
-*********************************************************************/
-bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
- unsigned int features, unsigned int baseAddress,
- unsigned int regionLength)
-{
- unsigned int accessLow;
- unsigned int accessHigh;
- unsigned int accessTop = baseAddress + regionLength;
-
- if (regionLength == 0) { /* close the region. */
- pciDisableAccessRegion (host, region);
- return true;
- }
- /* base Address is store is bits [11:0] */
- accessLow = (baseAddress & 0xfff00000) >> 20;
- /* All the features are update according to the defines in pci.h (to be on
- the safe side we disable bits: [11:0] */
- accessLow = accessLow | (features & 0xfffff000);
- /* write to the Low Access Region register */
- GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
- accessLow);
-
- accessHigh = (accessTop & 0xfff00000) >> 20;
-
- /* write to the High Access Region register */
- GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
- accessHigh - 1);
- return true;
-}
-
-/********************************************************************
-* pciDisableAccessRegion - Disable The given Region by writing MAX size
-* to its low Address and MIN size to its high Address.
-*
-* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled.
-* Returns: N/A.
-*********************************************************************/
-void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
-{
- /* writing back the registers default values. */
- GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
- 0x01001fff);
- GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
-}
-
-/********************************************************************
-* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
-*
-* Inputs: N/A
-* Returns: true.
-*********************************************************************/
-bool pciArbiterEnable (PCI_HOST host)
-{
- unsigned int regData;
-
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
- return true;
-}
-
-/********************************************************************
-* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
-*
-* Inputs: N/A
-* Returns: true
-*********************************************************************/
-bool pciArbiterDisable (PCI_HOST host)
-{
- unsigned int regData;
-
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
- return true;
-}
-
-/********************************************************************
-* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
-*
-* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent.
-* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
-* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
-* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
-* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
-* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
-* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
-* Returns: true
-*********************************************************************/
-bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
- PCI_AGENT_PRIO externalAgent0,
- PCI_AGENT_PRIO externalAgent1,
- PCI_AGENT_PRIO externalAgent2,
- PCI_AGENT_PRIO externalAgent3,
- PCI_AGENT_PRIO externalAgent4,
- PCI_AGENT_PRIO externalAgent5)
-{
- unsigned int regData;
- unsigned int writeData;
-
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- writeData = (internalAgent << 7) + (externalAgent0 << 8) +
- (externalAgent1 << 9) + (externalAgent2 << 10) +
- (externalAgent3 << 11) + (externalAgent4 << 12) +
- (externalAgent5 << 13);
- regData = (regData & 0xffffc07f) | writeData;
- GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
- return true;
-}
-
-/********************************************************************
-* pciParkingDisable - Park on last option disable, with this function you can
-* disable the park on last mechanism for each agent.
-* disabling this option for all agents results parking
-* on the internal master.
-*
-* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent.
-* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
-* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
-* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
-* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
-* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
-* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
-* Returns: true
-*********************************************************************/
-bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
- PCI_AGENT_PARK externalAgent0,
- PCI_AGENT_PARK externalAgent1,
- PCI_AGENT_PARK externalAgent2,
- PCI_AGENT_PARK externalAgent3,
- PCI_AGENT_PARK externalAgent4,
- PCI_AGENT_PARK externalAgent5)
-{
- unsigned int regData;
- unsigned int writeData;
-
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- writeData = (internalAgent << 14) + (externalAgent0 << 15) +
- (externalAgent1 << 16) + (externalAgent2 << 17) +
- (externalAgent3 << 18) + (externalAgent4 << 19) +
- (externalAgent5 << 20);
- regData = (regData & ~(0x7f << 14)) | writeData;
- GT_REG_WRITE (pci_arbiter_control[host], regData);
- return true;
-}
-
-/********************************************************************
-* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
-* respond to grant assertion within a window specified in
-* the input value: 'brokenValue'.
-*
-* Inputs: unsigned char brokenValue - A value which limits the Master to hold the
-* grant without asserting frame.
-* Returns: Error for illegal broken value otherwise true.
-*********************************************************************/
-bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
-{
- unsigned int data;
- unsigned int regData;
-
- if (brokenValue > 0xf)
- return false; /* brokenValue must be 4 bit */
- data = brokenValue << 3;
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- regData = (regData & 0xffffff87) | data;
- GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
- return true;
-}
-
-/********************************************************************
-* pciDisableBrokenAgentDetection - This function disable the Broken agent
-* Detection mechanism.
-* NOTE: This operation may cause a dead lock on the
-* pci0 arbitration.
-*
-* Inputs: N/A
-* Returns: true.
-*********************************************************************/
-bool pciDisableBrokenAgentDetection (PCI_HOST host)
-{
- unsigned int regData;
-
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- regData = regData & 0xfffffffd;
- GT_REG_WRITE (pci_arbiter_control[host], regData);
- return true;
-}
-
-/********************************************************************
-* pciP2PConfig - This function set the PCI_n P2P configurate.
-* For more information on the P2P read PCI spec.
-*
-* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
-* Boundry.
-* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
-* Boundry.
-* unsigned int busNum - The CPI bus number to which the PCI interface
-* is connected.
-* unsigned int devNum - The PCI interface's device number.
-*
-* Returns: true.
-*********************************************************************/
-bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
- unsigned int SecondBusHigh,
- unsigned int busNum, unsigned int devNum)
-{
- unsigned int regData;
-
- regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
- ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
- GT_REG_WRITE (pci_p2p_configuration[host], regData);
- return true;
-}
-
-/********************************************************************
-* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
-* supports Cache Coherency in the PCI_n interface.
-* Inputs: region - One of the four regions.
-* snoopType - There is four optional Types:
-* 1. No Snoop.
-* 2. Snoop to WT region.
-* 3. Snoop to WB region.
-* 4. Snoop & Invalidate to WB region.
-* baseAddress - Base Address of this region.
-* regionLength - Region length.
-* Returns: false if one of the parameters is wrong otherwise return true.
-*********************************************************************/
-bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
- PCI_SNOOP_TYPE snoopType,
- unsigned int baseAddress,
- unsigned int regionLength)
-{
- unsigned int snoopXbaseAddress;
- unsigned int snoopXtopAddress;
- unsigned int data;
- unsigned int snoopHigh = baseAddress + regionLength;
-
- if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
- return false;
- snoopXbaseAddress =
- pci_snoop_control_base_0_low[host] + 0x10 * region;
- snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
- if (regionLength == 0) { /* closing the region */
- GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
- GT_REG_WRITE (snoopXtopAddress, 0);
- return true;
- }
- baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
- data = (baseAddress >> 20) | snoopType << 12;
- GT_REG_WRITE (snoopXbaseAddress, data);
- snoopHigh = (snoopHigh & 0xfff00000) >> 20;
- GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
- return true;
-}
-
-static int gt_read_config_dword (struct pci_controller *hose,
- pci_dev_t dev, int offset, u32 * value)
-{
- int bus = PCI_BUS (dev);
-
- if ((bus == local_buses[0]) || (bus == local_buses[1])) {
- *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr,
- offset | (PCI_FUNC(dev) << 8),
- PCI_DEV (dev));
- } else {
- *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->cfg_addr,
- offset | (PCI_FUNC(dev) << 8),
- PCI_DEV (dev), bus);
- }
-
- return 0;
-}
-
-static int gt_write_config_dword (struct pci_controller *hose,
- pci_dev_t dev, int offset, u32 value)
-{
- int bus = PCI_BUS (dev);
-
- if ((bus == local_buses[0]) || (bus == local_buses[1])) {
- pciWriteConfigReg ((PCI_HOST) hose->cfg_addr,
- offset | (PCI_FUNC(dev) << 8),
- PCI_DEV (dev), value);
- } else {
- pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
- offset | (PCI_FUNC(dev) << 8),
- PCI_DEV (dev), bus,
- value);
- }
- return 0;
-}
-
-
-static void gt_setup_ide (struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *entry)
-{
- static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
- u32 bar_response, bar_value;
- int bar;
-
- if (CPCI750_SLAVE_TEST != 0)
- return;
-
- for (bar = 0; bar < 6; bar++) {
- /*ronen different function for 3rd bank. */
- unsigned int offset =
- (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
-
- pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
- 0x0);
- pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
- &bar_response);
-
- pciauto_region_allocate (bar_response &
- PCI_BASE_ADDRESS_SPACE_IO ? hose->
- pci_io : hose->pci_mem, ide_bar[bar],
- &bar_value);
-
- pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4,
- bar_value);
- }
-}
-
-#ifdef CONFIG_USE_CPCIDVI
-static void gt_setup_cpcidvi (struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *entry)
-{
- u32 bar_value, pci_response;
-
- if (CPCI750_SLAVE_TEST != 0)
- return;
-
- pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response);
- pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
- pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response);
- pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value);
- pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00));
- pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0);
- pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value);
- pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01);
- gt_cpcidvi_rom.base = bar_value & 0xffffff00;
- gt_cpcidvi_rom.init = 1;
-}
-
-unsigned char gt_cpcidvi_in8(unsigned int offset)
-{
- unsigned char data;
-
- if (gt_cpcidvi_rom.init == 0) {
- return(0);
- }
- data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base);
- return(data);
-}
-
-void gt_cpcidvi_out8(unsigned int offset, unsigned char data)
-{
- unsigned int off;
-
- if (gt_cpcidvi_rom.init == 0) {
- return;
- }
- off = data;
- off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base;
- in8(off);
- return;
-}
-#endif
-
-/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */
-/* and is curently not called *. */
-#if 0
-static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
-{
- unsigned char pin, irq;
-
- pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
-
- if (pin == 1) { /* only allow INT A */
- irq = pci_irq_swizzle[(PCI_HOST) hose->
- cfg_addr][PCI_DEV (dev)];
- if (irq)
- pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
- }
-}
-#endif
-
-struct pci_config_table gt_config_table[] = {
-#ifdef CONFIG_USE_CPCIDVI
- {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi},
-#endif
- {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
- {}
-};
-
-struct pci_controller pci0_hose = {
-/* fixup_irq: gt_fixup_irq, */
- config_table:gt_config_table,
-};
-
-struct pci_controller pci1_hose = {
-/* fixup_irq: gt_fixup_irq, */
- config_table:gt_config_table,
-};
-
-void pci_init_board (void)
-{
- unsigned int command;
- unsigned int slave;
-#ifdef CONFIG_PCI_PNP
- unsigned int bar;
-#endif
-#ifdef DEBUG
- gt_pci_bus_mode_display (PCI_HOST0);
-#endif
-#ifdef CONFIG_USE_CPCIDVI
- gt_cpcidvi_rom.init = 0;
- gt_cpcidvi_rom.base = 0;
-#endif
-
- slave = CPCI750_SLAVE_TEST;
-
- pci0_hose.config_table = gt_config_table;
- pci1_hose.config_table = gt_config_table;
-
-#ifdef CONFIG_USE_CPCIDVI
- gt_config_table[0].config_device = gt_setup_cpcidvi;
-#endif
- gt_config_table[1].config_device = gt_setup_ide;
-
- pci0_hose.first_busno = 0;
- pci0_hose.last_busno = 0xff;
- local_buses[0] = pci0_hose.first_busno;
-
- /* PCI memory space */
- pci_set_region (pci0_hose.regions + 0,
- CONFIG_SYS_PCI0_0_MEM_SPACE,
- CONFIG_SYS_PCI0_0_MEM_SPACE,
- CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region (pci0_hose.regions + 1,
- CONFIG_SYS_PCI0_IO_SPACE_PCI,
- CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
-
- pci_set_ops (&pci0_hose,
- pci_hose_read_config_byte_via_dword,
- pci_hose_read_config_word_via_dword,
- gt_read_config_dword,
- pci_hose_write_config_byte_via_dword,
- pci_hose_write_config_word_via_dword,
- gt_write_config_dword);
- pci0_hose.region_count = 2;
-
- pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
-
- pci_register_hose (&pci0_hose);
- if (slave == 0) {
- pciArbiterEnable (PCI_HOST0);
- pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
- command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MASTER;
- pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
- command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MEMORY;
- pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
-
-#ifdef CONFIG_PCI_PNP
- pciauto_config_init(&pci0_hose);
- pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar);
-#endif
-#ifdef CONFIG_PCI_SCAN_SHOW
- printf("PCI: Bus Dev VenId DevId Class Int\n");
-#endif
- pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose,
- pci0_hose.first_busno);
-
-#ifdef DEBUG
- gt_pci_bus_mode_display (PCI_HOST1);
-#endif
- } else {
- pciArbiterDisable (PCI_HOST0);
- pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
- command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MASTER;
- pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
- command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MEMORY;
- pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
- pci0_hose.last_busno = pci0_hose.first_busno;
- }
- pci1_hose.first_busno = pci0_hose.last_busno + 1;
- pci1_hose.last_busno = 0xff;
- pci1_hose.current_busno = pci1_hose.first_busno;
- local_buses[1] = pci1_hose.first_busno;
-
- /* PCI memory space */
- pci_set_region (pci1_hose.regions + 0,
- CONFIG_SYS_PCI1_0_MEM_SPACE,
- CONFIG_SYS_PCI1_0_MEM_SPACE,
- CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region (pci1_hose.regions + 1,
- CONFIG_SYS_PCI1_IO_SPACE_PCI,
- CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
-
- pci_set_ops (&pci1_hose,
- pci_hose_read_config_byte_via_dword,
- pci_hose_read_config_word_via_dword,
- gt_read_config_dword,
- pci_hose_write_config_byte_via_dword,
- pci_hose_write_config_word_via_dword,
- gt_write_config_dword);
-
- pci1_hose.region_count = 2;
-
- pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
-
- pci_register_hose (&pci1_hose);
-
- pciArbiterEnable (PCI_HOST1);
- pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
-
- command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MASTER;
- pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
-
-#ifdef CONFIG_PCI_PNP
- pciauto_config_init(&pci1_hose);
- pciauto_region_allocate(pci1_hose.pci_io, 0x400, &bar);
-#endif
- pci1_hose.last_busno = pci_hose_scan_bus (&pci1_hose, pci1_hose.first_busno);
-
- command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MEMORY;
- pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
-
-}
-#endif /* of CONFIG_PCI */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*************************************************************************
- * adaption for the Marvell DB64360 Board
- * Ingo Assmus (ingo.assmus@keymile.com)
- *
- * adaption for the cpci750 Board
- * Reinhard Arlt (reinhard.arlt@esd-electronics.com)
- *************************************************************************/
-
-
-/* sdram_init.c - automatic memory sizing */
-
-#include <common.h>
-#include <74xx_7xx.h>
-#include "../../Marvell/include/memory.h"
-#include "../../Marvell/include/pci.h"
-#include "../../Marvell/include/mv_gen_reg.h"
-#include <net.h>
-
-#include "eth.h"
-#include "mpsc.h"
-#include "../../Marvell/common/i2c.h"
-#include "64360.h"
-#include "mv_regs.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int set_dfcdlInit(void); /* setup delay line of Mv64360 */
-
-/* ------------------------------------------------------------------------- */
-
-int
-memory_map_bank(unsigned int bankNo,
- unsigned int bankBase,
- unsigned int bankLength)
-{
-#ifdef MAP_PCI
- PCI_HOST host;
-#endif
-
-
-#ifdef DEBUG
- if (bankLength > 0) {
- printf("mapping bank %d at %08x - %08x\n",
- bankNo, bankBase, bankBase + bankLength - 1);
- } else {
- printf("unmapping bank %d\n", bankNo);
- }
-#endif
-
- memoryMapBank(bankNo, bankBase, bankLength);
-
-#ifdef MAP_PCI
- for (host=PCI_HOST0;host<=PCI_HOST1;host++) {
- const int features=
- PREFETCH_ENABLE |
- DELAYED_READ_ENABLE |
- AGGRESSIVE_PREFETCH |
- READ_LINE_AGGRESSIVE_PREFETCH |
- READ_MULTI_AGGRESSIVE_PREFETCH |
- MAX_BURST_4 |
- PCI_NO_SWAP;
-
- pciMapMemoryBank(host, bankNo, bankBase, bankLength);
-
- pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase,
- bankLength);
-
- pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength);
- }
-#endif
- return 0;
-}
-
-#define GB (1 << 30)
-
-/* much of this code is based on (or is) the code in the pip405 port */
-/* thanks go to the authors of said port - Josh */
-
-/* structure to store the relevant information about an sdram bank */
-typedef struct sdram_info {
- uchar drb_size;
- uchar registered, ecc;
- uchar tpar;
- uchar tras_clocks;
- uchar burst_len;
- uchar banks, slot;
-} sdram_info_t;
-
-/* Typedefs for 'gtAuxilGetDIMMinfo' function */
-
-typedef enum _memoryType {SDRAM, DDR} MEMORY_TYPE;
-
-typedef enum _voltageInterface {TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
- SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
- } VOLTAGE_INTERFACE;
-
-typedef enum _max_CL_supported_DDR {DDR_CL_1=1, DDR_CL_1_5=2, DDR_CL_2=4, DDR_CL_2_5=8, DDR_CL_3=16, DDR_CL_3_5=32, DDR_CL_FAULT} MAX_CL_SUPPORTED_DDR;
-typedef enum _max_CL_supported_SD {SD_CL_1=1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, SD_FAULT} MAX_CL_SUPPORTED_SD;
-
-
-/* SDRAM/DDR information struct */
-typedef struct _gtMemoryDimmInfo {
- MEMORY_TYPE memoryType;
- unsigned int numOfRowAddresses;
- unsigned int numOfColAddresses;
- unsigned int numOfModuleBanks;
- unsigned int dataWidth;
- VOLTAGE_INTERFACE voltageInterface;
- unsigned int errorCheckType; /* ECC , PARITY.. */
- unsigned int sdramWidth; /* 4,8,16 or 32 */ ;
- unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */
- unsigned int minClkDelay;
- unsigned int burstLengthSupported;
- unsigned int numOfBanksOnEachDevice;
- unsigned int suportedCasLatencies;
- unsigned int RefreshInterval;
- unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */
- unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns) */
- MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
- MAX_CL_SUPPORTED_SD maxClSupported_SD;
- unsigned int moduleBankDensity;
- /* module attributes (true for yes) */
- bool bufferedAddrAndControlInputs;
- bool registeredAddrAndControlInputs;
- bool onCardPLL;
- bool bufferedDQMBinputs;
- bool registeredDQMBinputs;
- bool differentialClockInput;
- bool redundantRowAddressing;
-
- /* module general attributes */
- bool suportedAutoPreCharge;
- bool suportedPreChargeAll;
- bool suportedEarlyRasPreCharge;
- bool suportedWrite1ReadBurst;
- bool suported5PercentLowVCC;
- bool suported5PercentUpperVCC;
- /* module timing parameters */
- unsigned int minRasToCasDelay;
- unsigned int minRowActiveRowActiveDelay;
- unsigned int minRasPulseWidth;
- unsigned int minRowPrechargeTime; /* measured in ns */
-
- int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */
- int addrAndCommandSetupTime; /* (measured in ns/100) */
- int dataInputSetupTime; /* LoP left of point (measured in ns) */
- int dataInputHoldTime; /* LoP left of point (measured in ns) */
-/* tAC times for highest 2nd and 3rd highest CAS Latency values */
- unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */
- unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns) */
- unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */
- unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns) */
- unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */
- unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns) */
-
- unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */
- unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns) */
-
- unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */
- unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */
-
- unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */
- unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */
-
- /* Parameters calculated from
- the extracted DIMM information */
- unsigned int size;
- unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */
- unsigned int numberOfDevices;
- uchar drb_size; /* DRAM size in n*64Mbit */
- uchar slot; /* Slot Number this module is inserted in */
- uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */
-#ifdef DEBUG
- uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */
- uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */
- uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */
- unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */
- unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */
- unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */
- uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */
-
-#endif
-} AUX_MEM_DIMM_INFO;
-
-
-/*
- * translate ns.ns/10 coding of SPD timing values
- * into 10 ps unit values
- */
-static inline unsigned short
-NS10to10PS(unsigned char spd_byte)
-{
- unsigned short ns, ns10;
-
- /* isolate upper nibble */
- ns = (spd_byte >> 4) & 0x0F;
- /* isolate lower nibble */
- ns10 = (spd_byte & 0x0F);
-
- return(ns*100 + ns10*10);
-}
-
-/*
- * translate ns coding of SPD timing values
- * into 10 ps unit values
- */
-static inline unsigned short
-NSto10PS(unsigned char spd_byte)
-{
- return(spd_byte*100);
-}
-
-/* This code reads the SPD chip on the sdram and populates
- * the array which is passed in with the relevant information */
-/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
-static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
-{
- uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
- int ret;
- unsigned int i, j, density = 1, devicesForErrCheck = 0;
-
-#ifdef DEBUG
- unsigned int k;
-#endif
- unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
- int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
- uchar supp_cal, cal_val;
- ulong memclk, tmemclk;
- ulong tmp;
- uchar trp_clocks = 0, tras_clocks;
- uchar data[128];
-
- memclk = gd->bus_clk;
- tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
-
- memset (data, 0, sizeof (data));
-
-
- ret = 0;
-
- debug("before i2c read\n");
-
- ret = i2c_read (addr, 0, 2, data, 128);
-
- debug("after i2c read\n");
-
- if ((data[64] != 'e') || (data[65] != 's') || (data[66] != 'd')
- || (data[67] != '-') || (data[68] != 'g') || (data[69] != 'm')
- || (data[70] != 'b') || (data[71] != 'h')) {
- ret = -1;
- }
-
- if ((ret != 0) && (slot == 0)) {
- memset (data, 0, sizeof (data));
- data[0] = 0x80;
- data[1] = 0x08;
- data[2] = 0x07;
- data[3] = 0x0c;
- data[4] = 0x09;
- data[5] = 0x01;
- data[6] = 0x48;
- data[7] = 0x00;
- data[8] = 0x04;
- data[9] = 0x75;
- data[10] = 0x80;
- data[11] = 0x02;
- data[12] = 0x80;
- data[13] = 0x10;
- data[14] = 0x08;
- data[15] = 0x01;
- data[16] = 0x0e;
- data[17] = 0x04;
- data[18] = 0x0c;
- data[19] = 0x01;
- data[20] = 0x02;
- data[21] = 0x20;
- data[22] = 0x00;
- data[23] = 0xa0;
- data[24] = 0x80;
- data[25] = 0x00;
- data[26] = 0x00;
- data[27] = 0x50;
- data[28] = 0x3c;
- data[29] = 0x50;
- data[30] = 0x32;
- data[31] = 0x10;
- data[32] = 0xb0;
- data[33] = 0xb0;
- data[34] = 0x60;
- data[35] = 0x60;
- data[64] = 'e';
- data[65] = 's';
- data[66] = 'd';
- data[67] = '-';
- data[68] = 'g';
- data[69] = 'm';
- data[70] = 'b';
- data[71] = 'h';
- ret = 0;
- }
-
- /* zero all the values */
- memset (dimmInfo, 0, sizeof (*dimmInfo));
-
- /* copy the SPD content 1:1 into the dimmInfo structure */
- for (i = 0; i <= 127; i++) {
- dimmInfo->spd_raw_data[i] = data[i];
- }
-
- if (ret) {
- debug("No DIMM in slot %d [err = %x]\n", slot, ret);
- return 0;
- } else
- dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */
-
-#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
-
- for (i = 0; i <= 127; i++) {
- printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
- data[i]);
- }
-
-#endif
-#ifdef DEBUG
- /* find Manufacturer of Dimm Module */
- for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
- dimmInfo->manufactura[i] = data[64 + i];
- }
- printf ("\nThis RAM-Module is produced by: %s\n",
- dimmInfo->manufactura);
-
- /* find Manul-ID of Dimm Module */
- for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
- dimmInfo->modul_id[i] = data[73 + i];
- }
- printf ("The Module-ID of this RAM-Module is: %s\n",
- dimmInfo->modul_id);
-
- /* find Vendor-Data of Dimm Module */
- for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
- dimmInfo->vendor_data[i] = data[99 + i];
- }
- printf ("Vendor Data of this RAM-Module is: %s\n",
- dimmInfo->vendor_data);
-
- /* find modul_serial_no of Dimm Module */
- dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
- printf ("Serial No. of this RAM-Module is: %ld (%lx)\n",
- dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
-
- /* find Manufac-Data of Dimm Module */
- dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
- printf ("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data[94]); /*dimmInfo->manufac_date */
-
- /* find modul_revision of Dimm Module */
- dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
- printf ("Module Revision of this RAM-Module is: %d.%d\n", data[91], data[92]); /* dimmInfo->modul_revision */
-
- /* find manufac_place of Dimm Module */
- dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
- printf ("manufac_place of this RAM-Module is: %d\n",
- dimmInfo->manufac_place);
-
-#endif
-/*------------------------------------------------------------------------------------------------------------------------------*/
-/* calculate SPD checksum */
-/*------------------------------------------------------------------------------------------------------------------------------*/
-#if 0 /* test-only */
- spd_checksum = 0;
-
- for (i = 0; i <= 62; i++) {
- spd_checksum += data[i];
- }
-
- if ((spd_checksum & 0xff) != data[63]) {
- printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
- hang ();
- }
-
- else
- printf ("SPD Checksum ok!\n");
-#endif /* test-only */
-
-/*------------------------------------------------------------------------------------------------------------------------------*/
- for (i = 2; i <= 35; i++) {
- switch (i) {
- case 2: /* Memory type (DDR / SDRAM) */
- dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
-#ifdef DEBUG
- if (dimmInfo->memoryType == 0)
- debug("Dram_type in slot %d is: SDRAM\n",
- dimmInfo->slot);
- if (dimmInfo->memoryType == 1)
- debug("Dram_type in slot %d is: DDRAM\n",
- dimmInfo->slot);
-#endif
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 3: /* Number Of Row Addresses */
- dimmInfo->numOfRowAddresses = data[i];
- debug("Module Number of row addresses: %d\n",
- dimmInfo->numOfRowAddresses);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 4: /* Number Of Column Addresses */
- dimmInfo->numOfColAddresses = data[i];
- debug("Module Number of col addresses: %d\n",
- dimmInfo->numOfColAddresses);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 5: /* Number Of Module Banks */
- dimmInfo->numOfModuleBanks = data[i];
- debug("Number of Banks on Mod. : %d\n",
- dimmInfo->numOfModuleBanks);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 6: /* Data Width */
- dimmInfo->dataWidth = data[i];
- debug("Module Data Width: %d\n",
- dimmInfo->dataWidth);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 8: /* Voltage Interface */
- switch (data[i]) {
- case 0x0:
- dimmInfo->voltageInterface = TTL_5V_TOLERANT;
- debug("Module is TTL_5V_TOLERANT\n");
- break;
- case 0x1:
- dimmInfo->voltageInterface = LVTTL;
- debug("Module is LVTTL\n");
- break;
- case 0x2:
- dimmInfo->voltageInterface = HSTL_1_5V;
- debug("Module is TTL_5V_TOLERANT\n");
- break;
- case 0x3:
- dimmInfo->voltageInterface = SSTL_3_3V;
- debug("Module is HSTL_1_5V\n");
- break;
- case 0x4:
- dimmInfo->voltageInterface = SSTL_2_5V;
- debug("Module is SSTL_2_5V\n");
- break;
- default:
- dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
- debug("Module is VOLTAGE_UNKNOWN\n");
- break;
- }
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 9: /* Minimum Cycle Time At Max CasLatancy */
- shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
- mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
- maskLeftOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
- maskRightOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
- leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
- rightOfPoint = (data[i] & maskRightOfPoint) * mult;
- dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
- leftOfPoint;
- dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
- rightOfPoint;
- debug("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n",
- leftOfPoint, rightOfPoint);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 10: /* Clock To Data Out */
- div = (dimmInfo->memoryType == DDR) ? 100 : 10;
- time_tmp =
- (((data[i] & 0xf0) >> 4) * 10) +
- ((data[i] & 0x0f));
- leftOfPoint = time_tmp / div;
- rightOfPoint = time_tmp % div;
- dimmInfo->clockToDataOut_LoP = leftOfPoint;
- dimmInfo->clockToDataOut_RoP = rightOfPoint;
- debug("Clock To Data Out: %d.%2d [ns]\n",
- leftOfPoint, rightOfPoint);
- /*dimmInfo->clockToDataOut */
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
-#ifdef CONFIG_MV64360_ECC
- case 11: /* Error Check Type */
- dimmInfo->errorCheckType = data[i];
- debug("Error Check Type (0=NONE): %d\n",
- dimmInfo->errorCheckType);
- break;
-#endif /* of ifdef CONFIG_MV64360_ECC */
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 12: /* Refresh Interval */
- dimmInfo->RefreshInterval = data[i];
- debug("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
- dimmInfo->RefreshInterval);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 13: /* Sdram Width */
- dimmInfo->sdramWidth = data[i];
- debug("Sdram Width: %d\n",
- dimmInfo->sdramWidth);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 14: /* Error Check Data Width */
- dimmInfo->errorCheckDataWidth = data[i];
- debug("Error Check Data Width: %d\n",
- dimmInfo->errorCheckDataWidth);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 15: /* Minimum Clock Delay */
- dimmInfo->minClkDelay = data[i];
- debug("Minimum Clock Delay: %d\n",
- dimmInfo->minClkDelay);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 16: /* Burst Length Supported */
- /******-******-******-*******
- * bit3 | bit2 | bit1 | bit0 *
- *******-******-******-*******
- burst length = * 8 | 4 | 2 | 1 *
- *****************************
-
- If for example bit0 and bit2 are set, the burst
- length supported are 1 and 4. */
-
- dimmInfo->burstLengthSupported = data[i];
-#ifdef DEBUG
- debug("Burst Length Supported: ");
- if (dimmInfo->burstLengthSupported & 0x01)
- debug("1, ");
- if (dimmInfo->burstLengthSupported & 0x02)
- debug("2, ");
- if (dimmInfo->burstLengthSupported & 0x04)
- debug("4, ");
- if (dimmInfo->burstLengthSupported & 0x08)
- debug("8, ");
- debug(" Bit \n");
-#endif
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 17: /* Number Of Banks On Each Device */
- dimmInfo->numOfBanksOnEachDevice = data[i];
- debug("Number Of Banks On Each Chip: %d\n",
- dimmInfo->numOfBanksOnEachDevice);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 18: /* Suported Cas Latencies */
-
- /* DDR:
- *******-******-******-******-******-******-******-*******
- * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
- *******-******-******-******-******-******-******-*******
- CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 *
- *********************************************************
- SDRAM:
- *******-******-******-******-******-******-******-*******
- * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
- *******-******-******-******-******-******-******-*******
- CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 *
- ********************************************************/
- dimmInfo->suportedCasLatencies = data[i];
-#ifdef DEBUG
- debug("Suported Cas Latencies: (CL) ");
- if (dimmInfo->memoryType == 0) { /* SDRAM */
- for (k = 0; k <= 7; k++) {
- if (dimmInfo->
- suportedCasLatencies & (1 << k))
- debug("%d, ",
- k + 1);
- }
-
- } else { /* DDR-RAM */
-
- if (dimmInfo->suportedCasLatencies & 1)
- debug("1, ");
- if (dimmInfo->suportedCasLatencies & 2)
- debug("1.5, ");
- if (dimmInfo->suportedCasLatencies & 4)
- debug("2, ");
- if (dimmInfo->suportedCasLatencies & 8)
- debug("2.5, ");
- if (dimmInfo->suportedCasLatencies & 16)
- debug("3, ");
- if (dimmInfo->suportedCasLatencies & 32)
- debug("3.5, ");
-
- }
- debug("\n");
-#endif
- /* Calculating MAX CAS latency */
- for (j = 7; j > 0; j--) {
- if (((dimmInfo->
- suportedCasLatencies >> j) & 0x1) ==
- 1) {
- switch (dimmInfo->memoryType) {
- case DDR:
- /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
- switch (j) {
- case 7:
- debug("Max. Cas Latencies (DDR): ERROR !!!\n");
- dimmInfo->
- maxClSupported_DDR
- =
- DDR_CL_FAULT;
- hang ();
- break;
- case 6:
- debug("Max. Cas Latencies (DDR): ERROR !!!\n");
- dimmInfo->
- maxClSupported_DDR
- =
- DDR_CL_FAULT;
- hang ();
- break;
- case 5:
- debug("Max. Cas Latencies (DDR): 3.5 clk's\n");
- dimmInfo->
- maxClSupported_DDR
- = DDR_CL_3_5;
- break;
- case 4:
- debug("Max. Cas Latencies (DDR): 3 clk's \n");
- dimmInfo->
- maxClSupported_DDR
- = DDR_CL_3;
- break;
- case 3:
- debug("Max. Cas Latencies (DDR): 2.5 clk's \n");
- dimmInfo->
- maxClSupported_DDR
- = DDR_CL_2_5;
- break;
- case 2:
- debug("Max. Cas Latencies (DDR): 2 clk's \n");
- dimmInfo->
- maxClSupported_DDR
- = DDR_CL_2;
- break;
- case 1:
- debug("Max. Cas Latencies (DDR): 1.5 clk's \n");
- dimmInfo->
- maxClSupported_DDR
- = DDR_CL_1_5;
- break;
- }
- dimmInfo->
- maxCASlatencySupported_LoP
- =
- 1 +
- (int) (5 * j / 10);
- if (((5 * j) % 10) != 0)
- dimmInfo->
- maxCASlatencySupported_RoP
- = 5;
- else
- dimmInfo->
- maxCASlatencySupported_RoP
- = 0;
- debug("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
- dimmInfo->
- maxCASlatencySupported_LoP,
- dimmInfo->
- maxCASlatencySupported_RoP);
- break;
- case SDRAM:
- /* CAS latency 1, 2, 3, 4, 5, 6, 7 */
- dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */
- debug("Max. Cas Latencies (SD): %d\n",
- dimmInfo->
- maxClSupported_SD);
- dimmInfo->
- maxCASlatencySupported_LoP
- = j;
- dimmInfo->
- maxCASlatencySupported_RoP
- = 0;
- debug("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
- dimmInfo->
- maxCASlatencySupported_LoP,
- dimmInfo->
- maxCASlatencySupported_RoP);
- break;
- }
- break;
- }
- }
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 21: /* Buffered Address And Control Inputs */
- debug("\nModul Attributes (SPD Byte 21): \n");
- dimmInfo->bufferedAddrAndControlInputs =
- data[i] & BIT0;
- dimmInfo->registeredAddrAndControlInputs =
- (data[i] & BIT1) >> 1;
- dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
- dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
- dimmInfo->registeredDQMBinputs =
- (data[i] & BIT4) >> 4;
- dimmInfo->differentialClockInput =
- (data[i] & BIT5) >> 5;
- dimmInfo->redundantRowAddressing =
- (data[i] & BIT6) >> 6;
-
- if (dimmInfo->bufferedAddrAndControlInputs == 1)
- debug(" - Buffered Address/Control Input: Yes \n");
- else
- debug(" - Buffered Address/Control Input: No \n");
-
- if (dimmInfo->registeredAddrAndControlInputs == 1)
- debug(" - Registered Address/Control Input: Yes \n");
- else
- debug(" - Registered Address/Control Input: No \n");
-
- if (dimmInfo->onCardPLL == 1)
- debug(" - On-Card PLL (clock): Yes \n");
- else
- debug(" - On-Card PLL (clock): No \n");
-
- if (dimmInfo->bufferedDQMBinputs == 1)
- debug(" - Bufferd DQMB Inputs: Yes \n");
- else
- debug(" - Bufferd DQMB Inputs: No \n");
-
- if (dimmInfo->registeredDQMBinputs == 1)
- debug(" - Registered DQMB Inputs: Yes \n");
- else
- debug(" - Registered DQMB Inputs: No \n");
-
- if (dimmInfo->differentialClockInput == 1)
- debug(" - Differential Clock Input: Yes \n");
- else
- debug(" - Differential Clock Input: No \n");
-
- if (dimmInfo->redundantRowAddressing == 1)
- debug(" - redundant Row Addressing: Yes \n");
- else
- debug(" - redundant Row Addressing: No \n");
-
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 22: /* Suported AutoPreCharge */
- debug("\nModul Attributes (SPD Byte 22): \n");
- dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
- dimmInfo->suportedAutoPreCharge =
- (data[i] & BIT1) >> 1;
- dimmInfo->suportedPreChargeAll =
- (data[i] & BIT2) >> 2;
- dimmInfo->suportedWrite1ReadBurst =
- (data[i] & BIT3) >> 3;
- dimmInfo->suported5PercentLowVCC =
- (data[i] & BIT4) >> 4;
- dimmInfo->suported5PercentUpperVCC =
- (data[i] & BIT5) >> 5;
-
- if (dimmInfo->suportedEarlyRasPreCharge == 1)
- debug(" - Early Ras Precharge: Yes \n");
- else
- debug(" - Early Ras Precharge: No \n");
-
- if (dimmInfo->suportedAutoPreCharge == 1)
- debug(" - AutoPreCharge: Yes \n");
- else
- debug(" - AutoPreCharge: No \n");
-
- if (dimmInfo->suportedPreChargeAll == 1)
- debug(" - Precharge All: Yes \n");
- else
- debug(" - Precharge All: No \n");
-
- if (dimmInfo->suportedWrite1ReadBurst == 1)
- debug(" - Write 1/ReadBurst: Yes \n");
- else
- debug(" - Write 1/ReadBurst: No \n");
-
- if (dimmInfo->suported5PercentLowVCC == 1)
- debug(" - lower VCC tolerance: 5 Percent \n");
- else
- debug(" - lower VCC tolerance: 10 Percent \n");
-
- if (dimmInfo->suported5PercentUpperVCC == 1)
- debug(" - upper VCC tolerance: 5 Percent \n");
- else
- debug(" - upper VCC tolerance: 10 Percent \n");
-
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
- shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
- mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
- maskLeftOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
- maskRightOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
- leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
- rightOfPoint = (data[i] & maskRightOfPoint) * mult;
- dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
- leftOfPoint;
- dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
- rightOfPoint;
- debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
- leftOfPoint, rightOfPoint);
- /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 24: /* Clock To Data Out 2nd highest Cas Latency Value */
- div = (dimmInfo->memoryType == DDR) ? 100 : 10;
- time_tmp =
- (((data[i] & 0xf0) >> 4) * 10) +
- ((data[i] & 0x0f));
- leftOfPoint = time_tmp / div;
- rightOfPoint = time_tmp % div;
- dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
- dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
- debug("Clock To Data Out (2nd CL value): %d.%2d [ns]\n",
- leftOfPoint, rightOfPoint);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
- shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
- mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
- maskLeftOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
- maskRightOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
- leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
- rightOfPoint = (data[i] & maskRightOfPoint) * mult;
- dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
- leftOfPoint;
- dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
- rightOfPoint;
- debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
- leftOfPoint, rightOfPoint);
- /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 26: /* Clock To Data Out 3rd highest Cas Latency Value */
- div = (dimmInfo->memoryType == DDR) ? 100 : 10;
- time_tmp =
- (((data[i] & 0xf0) >> 4) * 10) +
- ((data[i] & 0x0f));
- leftOfPoint = time_tmp / div;
- rightOfPoint = time_tmp % div;
- dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
- dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
- debug("Clock To Data Out (3rd CL value): %d.%2d [ns]\n",
- leftOfPoint, rightOfPoint);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 27: /* Minimum Row Precharge Time */
- shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
- maskLeftOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
- maskRightOfPoint =
- (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
- leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
- rightOfPoint = (data[i] & maskRightOfPoint) * 25;
-
- dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint); /* measured in n times 10ps Intervals */
- trp_clocks =
- (dimmInfo->minRowPrechargeTime +
- (tmemclk - 1)) / tmemclk;
- debug("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n",
- tmemclk, tmemclk / 100, tmemclk % 100);
- debug("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n",
- leftOfPoint, rightOfPoint, trp_clocks);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 28: /* Minimum Row Active to Row Active Time */
- shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
- maskLeftOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
- maskRightOfPoint =
- (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
- leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
- rightOfPoint = (data[i] & maskRightOfPoint) * 25;
-
- dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
- debug("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n",
- leftOfPoint, rightOfPoint, trp_clocks);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 29: /* Minimum Ras-To-Cas Delay */
- shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
- maskLeftOfPoint =
- (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
- maskRightOfPoint =
- (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
- leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
- rightOfPoint = (data[i] & maskRightOfPoint) * 25;
-
- dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
- debug("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n",
- leftOfPoint, rightOfPoint, trp_clocks);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 30: /* Minimum Ras Pulse Width */
- dimmInfo->minRasPulseWidth = data[i];
- tras_clocks =
- (NSto10PS (data[i]) +
- (tmemclk - 1)) / tmemclk;
- debug("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n",
- dimmInfo->minRasPulseWidth, tras_clocks);
-
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 31: /* Module Bank Density */
- dimmInfo->moduleBankDensity = data[i];
- debug("Module Bank Density: %d\n",
- dimmInfo->moduleBankDensity);
-#ifdef DEBUG
- debug("*** Offered Densities (more than 1 = Multisize-Module): ");
- {
- if (dimmInfo->moduleBankDensity & 1)
- debug("4MB, ");
- if (dimmInfo->moduleBankDensity & 2)
- debug("8MB, ");
- if (dimmInfo->moduleBankDensity & 4)
- debug("16MB, ");
- if (dimmInfo->moduleBankDensity & 8)
- debug("32MB, ");
- if (dimmInfo->moduleBankDensity & 16)
- debug("64MB, ");
- if (dimmInfo->moduleBankDensity & 32)
- debug("128MB, ");
- if ((dimmInfo->moduleBankDensity & 64)
- || (dimmInfo->moduleBankDensity & 128)) {
- debug("ERROR, ");
- hang ();
- }
- }
- debug("\n");
-#endif
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 32: /* Address And Command Setup Time (measured in ns/1000) */
- sign = 1;
- switch (dimmInfo->memoryType) {
- case DDR:
- time_tmp =
- (((data[i] & 0xf0) >> 4) * 10) +
- ((data[i] & 0x0f));
- leftOfPoint = time_tmp / 100;
- rightOfPoint = time_tmp % 100;
- break;
- case SDRAM:
- leftOfPoint = (data[i] & 0xf0) >> 4;
- if (leftOfPoint > 7) {
- leftOfPoint = data[i] & 0x70 >> 4;
- sign = -1;
- }
- rightOfPoint = (data[i] & 0x0f);
- break;
- }
- dimmInfo->addrAndCommandSetupTime =
- (leftOfPoint * 100 + rightOfPoint) * sign;
- debug("Address And Command Setup Time [ns]: %d.%d\n",
- sign * leftOfPoint, rightOfPoint);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 33: /* Address And Command Hold Time */
- sign = 1;
- switch (dimmInfo->memoryType) {
- case DDR:
- time_tmp =
- (((data[i] & 0xf0) >> 4) * 10) +
- ((data[i] & 0x0f));
- leftOfPoint = time_tmp / 100;
- rightOfPoint = time_tmp % 100;
- break;
- case SDRAM:
- leftOfPoint = (data[i] & 0xf0) >> 4;
- if (leftOfPoint > 7) {
- leftOfPoint = data[i] & 0x70 >> 4;
- sign = -1;
- }
- rightOfPoint = (data[i] & 0x0f);
- break;
- }
- dimmInfo->addrAndCommandHoldTime =
- (leftOfPoint * 100 + rightOfPoint) * sign;
- debug("Address And Command Hold Time [ns]: %d.%d\n",
- sign * leftOfPoint, rightOfPoint);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 34: /* Data Input Setup Time */
- sign = 1;
- switch (dimmInfo->memoryType) {
- case DDR:
- time_tmp =
- (((data[i] & 0xf0) >> 4) * 10) +
- ((data[i] & 0x0f));
- leftOfPoint = time_tmp / 100;
- rightOfPoint = time_tmp % 100;
- break;
- case SDRAM:
- leftOfPoint = (data[i] & 0xf0) >> 4;
- if (leftOfPoint > 7) {
- leftOfPoint = data[i] & 0x70 >> 4;
- sign = -1;
- }
- rightOfPoint = (data[i] & 0x0f);
- break;
- }
- dimmInfo->dataInputSetupTime =
- (leftOfPoint * 100 + rightOfPoint) * sign;
- debug("Data Input Setup Time [ns]: %d.%d\n",
- sign * leftOfPoint, rightOfPoint);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
-
- case 35: /* Data Input Hold Time */
- sign = 1;
- switch (dimmInfo->memoryType) {
- case DDR:
- time_tmp =
- (((data[i] & 0xf0) >> 4) * 10) +
- ((data[i] & 0x0f));
- leftOfPoint = time_tmp / 100;
- rightOfPoint = time_tmp % 100;
- break;
- case SDRAM:
- leftOfPoint = (data[i] & 0xf0) >> 4;
- if (leftOfPoint > 7) {
- leftOfPoint = data[i] & 0x70 >> 4;
- sign = -1;
- }
- rightOfPoint = (data[i] & 0x0f);
- break;
- }
- dimmInfo->dataInputHoldTime =
- (leftOfPoint * 100 + rightOfPoint) * sign;
- debug("Data Input Hold Time [ns]: %d.%d\n\n",
- sign * leftOfPoint, rightOfPoint);
- break;
-/*------------------------------------------------------------------------------------------------------------------------------*/
- }
- }
- /* calculating the sdram density */
- for (i = 0;
- i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
- i++) {
- density = density * 2;
- }
- dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
- dimmInfo->sdramWidth;
- dimmInfo->numberOfDevices =
- (dimmInfo->dataWidth / dimmInfo->sdramWidth) *
- dimmInfo->numOfModuleBanks;
- devicesForErrCheck =
- (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth;
- if ((dimmInfo->errorCheckType == 0x1)
- || (dimmInfo->errorCheckType == 0x2)
- || (dimmInfo->errorCheckType == 0x3)) {
- dimmInfo->size =
- (dimmInfo->deviceDensity / 8) *
- (dimmInfo->numberOfDevices - devicesForErrCheck);
- } else {
- dimmInfo->size =
- (dimmInfo->deviceDensity / 8) *
- dimmInfo->numberOfDevices;
- }
-
- /* compute the module DRB size */
- tmp = (1 <<
- (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
- tmp *= dimmInfo->numOfModuleBanks;
- tmp *= dimmInfo->sdramWidth;
- tmp = tmp >> 24; /* div by 0x4000000 (64M) */
- dimmInfo->drb_size = (uchar) tmp;
- debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size);
-
- /* try a CAS latency of 3 first... */
-
- /* bit 1 is CL2, bit 2 is CL3 */
- supp_cal = (dimmInfo->suportedCasLatencies & 0x1c) >> 1;
-
- cal_val = 0;
- if (supp_cal & 8) {
- if (NS10to10PS (data[9]) <= tmemclk)
- cal_val = 6;
- }
- if (supp_cal & 4) {
- if (NS10to10PS (data[9]) <= tmemclk)
- cal_val = 5;
- }
-
- /* then 2... */
- if (supp_cal & 2) {
- if (NS10to10PS (data[23]) <= tmemclk)
- cal_val = 4;
- }
-
- debug("cal_val = %d\n", cal_val * 5);
-
- /* bummer, did't work... */
- if (cal_val == 0) {
- debug("Couldn't find a good CAS latency\n");
- hang ();
- return 0;
- }
-
- return true;
-}
-
-/* sets up the GT properly with information passed in */
-int setup_sdram (AUX_MEM_DIMM_INFO * info)
-{
- ulong tmp;
- ulong tmp_sdram_mode = 0; /* 0x141c */
- ulong tmp_dunit_control_low = 0; /* 0x1404 */
- uint sdram_config_reg = CONFIG_SYS_SDRAM_CONFIG;
- int i;
-
- /* sanity checking */
- if (!info->numOfModuleBanks) {
- printf ("setup_sdram called with 0 banks\n");
- return 1;
- }
-
- /* delay line */
-
- /* Program the GT with the discovered data */
- if (info->registeredAddrAndControlInputs == true)
- debug("Module is registered, but we do not support registered Modules !!!\n");
-
- /* delay line */
- set_dfcdlInit (); /* may be its not needed */
- debug("Delay line set done\n");
-
- /* set SDRAM mode NOP */ /* To_do check it */
- GT_REG_WRITE (SDRAM_OPERATION, 0x5);
- while (GTREGREAD (SDRAM_OPERATION) != 0) {
- debug("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n");
- }
-
-#ifdef CONFIG_MV64360_ECC
- if ((info->errorCheckType == 0x2) && (CPCI750_ECC_TEST)) {
- /* DRAM has ECC, so turn it on */
- sdram_config_reg |= BIT18;
- debug("Enabling ECC\n");
- }
-#endif /* of ifdef CONFIG_MV64360_ECC */
-
- /* SDRAM configuration */
- GT_REG_WRITE(SDRAM_CONFIG, sdram_config_reg);
- debug("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG));
-
- /* SDRAM open pages controll keep open as much as I can */
- GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
- debug("sdram_open_pages_controll 0x1414: %08x\n",
- GTREGREAD (SDRAM_OPEN_PAGES_CONTROL));
-
-
- /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
- tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */
- if (tmp == 0)
- debug("Core Signals are sync (by HW-Setting)!!!\n");
- else
- debug("Core Signals syncs. are bypassed (by HW-Setting)!!!\n");
-
- /* SDRAM set CAS Lentency according to SPD information */
- switch (info->memoryType) {
- case SDRAM:
- debug("### SD-RAM not supported yet !!!\n");
- hang ();
- /* ToDo fill SD-RAM if needed !!!!! */
- break;
-
- case DDR:
- debug("### SET-CL for DDR-RAM\n");
-
- switch (info->maxClSupported_DDR) {
- case DDR_CL_3:
- tmp_dunit_control_low = 0x3c000000; /* Read-Data sampled on falling edge of Clk */
- tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */
- debug("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low);
- break;
-
- case DDR_CL_2_5:
- if (tmp == 1) { /* clocks sync */
- tmp_dunit_control_low = 0x24000000; /* Read-Data sampled on falling edge of Clk */
- tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */
- debug("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low);
- } else { /* clk sync. bypassed */
-
- tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */
- tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */
- debug("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low);
- }
- break;
-
- case DDR_CL_2:
- if (tmp == 1) { /* Sync */
- tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */
- tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */
- debug("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low);
- } else { /* Not sync. */
-
- tmp_dunit_control_low = 0x3b000000; /* Read-Data sampled on rising edge of Clk */
- tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */
- debug("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low);
- }
- break;
-
- case DDR_CL_1_5:
- if (tmp == 1) { /* Sync */
- tmp_dunit_control_low = 0x23000000; /* Read-Data sampled on falling edge of Clk */
- tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */
- debug("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low);
- } else { /* not sync */
-
- tmp_dunit_control_low = 0x1a000000; /* Read-Data sampled on rising edge of Clk */
- tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */
- debug("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low);
- }
- break;
-
- default:
- printf ("Max. CL is out of range %d\n",
- info->maxClSupported_DDR);
- hang ();
- break;
- }
- break;
- }
-
- /* Write results of CL detection procedure */
- GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
- /* set SDRAM mode SetCommand 0x1418 */
- GT_REG_WRITE (SDRAM_OPERATION, 0x3);
- while (GTREGREAD (SDRAM_OPERATION) != 0) {
- debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
- }
-
-
- /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
- tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */
- if (tmp != 1) { /*clocks are not sync */
- /* asyncmode */
- GT_REG_WRITE (D_UNIT_CONTROL_LOW,
- (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
- 0x18110780 | tmp_dunit_control_low);
- } else {
- /* syncmode */
- GT_REG_WRITE (D_UNIT_CONTROL_LOW,
- (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
- 0x00110000 | tmp_dunit_control_low);
- }
-
- /* set SDRAM mode SetCommand 0x1418 */
- GT_REG_WRITE (SDRAM_OPERATION, 0x3);
- while (GTREGREAD (SDRAM_OPERATION) != 0) {
- debug("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n");
- }
-
-/*------------------------------------------------------------------------------ */
-
-
- /* bank parameters */
- /* SDRAM address decode register */
- /* program this with the default value */
- tmp = 0x02;
-
-
- debug("drb_size (n*64Mbit): %d\n", info->drb_size);
- switch (info->drb_size) {
- case 1: /* 64 Mbit */
- case 2: /* 128 Mbit */
- debug("RAM-Device_size 64Mbit or 128Mbit)\n");
- tmp |= (0x00 << 4);
- break;
- case 4: /* 256 Mbit */
- case 8: /* 512 Mbit */
- debug("RAM-Device_size 256Mbit or 512Mbit)\n");
- tmp |= (0x01 << 4);
- break;
- case 16: /* 1 Gbit */
- case 32: /* 2 Gbit */
- debug("RAM-Device_size 1Gbit or 2Gbit)\n");
- tmp |= (0x02 << 4);
- break;
- default:
- printf ("Error in dram size calculation\n");
- debug("Assume: RAM-Device_size 1Gbit or 2Gbit)\n");
- tmp |= (0x02 << 4);
- return 1;
- }
-
- /* SDRAM bank parameters */
- /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
- debug("setting up slot %d config with: %08lx \n", info->slot, tmp);
- GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
-
-/* ------------------------------------------------------------------------------ */
-
- debug("setting up sdram_timing_control_low with: %08x \n",
- 0x11511220);
- GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220);
-
-
-/* ------------------------------------------------------------------------------ */
-
- /* SDRAM configuration */
- tmp = GTREGREAD (SDRAM_CONFIG);
-
- if (info->registeredAddrAndControlInputs
- || info->registeredDQMBinputs) {
- tmp |= (1 << 17);
- debug("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
- info->registeredAddrAndControlInputs,
- info->registeredDQMBinputs);
- }
-
- /* Use buffer 1 to return read data to the CPU
- * Page 426 MV64360 */
- tmp |= (1 << 26);
- debug("Before Buffer assignment - sdram_conf: %08x\n",
- GTREGREAD (SDRAM_CONFIG));
- debug("After Buffer assignment - sdram_conf: %08x\n",
- GTREGREAD (SDRAM_CONFIG));
-
- /* SDRAM timing To_do: */
-
-
- tmp = GTREGREAD (SDRAM_TIMING_CONTROL_HIGH);
- debug("# sdram_timing_control_high is : %08lx \n", tmp);
-
- /* SDRAM address decode register */
- /* program this with the default value */
- tmp = GTREGREAD (SDRAM_ADDR_CONTROL);
- debug("SDRAM address control (before: decode): %08x ",
- GTREGREAD (SDRAM_ADDR_CONTROL));
- GT_REG_WRITE (SDRAM_ADDR_CONTROL, (tmp | 0x2));
- debug("SDRAM address control (after: decode): %08x\n",
- GTREGREAD (SDRAM_ADDR_CONTROL));
-
- /* set the SDRAM configuration for each bank */
-
-/* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
- {
- int l, l1;
-
- i = info->slot;
- debug("\n*** Running a MRS cycle for bank %d ***\n", i);
-
- /* map the bank */
- memory_map_bank (i, 0, GB / 4);
-#if 1 /* test only */
-
- tmp = GTREGREAD (SDRAM_MODE);
- GT_REG_WRITE (EXTENDED_DRAM_MODE, 0x0);
- GT_REG_WRITE (SDRAM_OPERATION, 0x4);
- while (GTREGREAD (SDRAM_OPERATION) != 0) {
- debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
- }
-
- GT_REG_WRITE (SDRAM_MODE, tmp | 0x80);
- GT_REG_WRITE (SDRAM_OPERATION, 0x3);
- while (GTREGREAD (SDRAM_OPERATION) != 0) {
- debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
- }
- l1 = 0;
- for (l=0;l<200;l++)
- l1 += GTREGREAD (SDRAM_OPERATION);
-
- GT_REG_WRITE (SDRAM_MODE, tmp);
- GT_REG_WRITE (SDRAM_OPERATION, 0x3);
- while (GTREGREAD (SDRAM_OPERATION) != 0) {
- debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
- }
-
- /* switch back to normal operation mode */
- GT_REG_WRITE (SDRAM_OPERATION, 0x5);
- while (GTREGREAD (SDRAM_OPERATION) != 0) {
- debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
- }
-
-#endif /* test only */
- /* unmap the bank */
- memory_map_bank (i, 0, 0);
- }
-
- return 0;
-}
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-long int
-dram_size(long int *base, long int maxsize)
-{
- volatile long int *addr, *b=base;
- long int cnt, val, save1, save2;
-
-#define STARTVAL (1<<20) /* start test at 1M */
- for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save1 = *addr; /* save contents of addr */
- save2 = *b; /* save contents of base */
-
- *addr=cnt; /* write cnt to addr */
- *b=0; /* put null at base */
-
- /* check at base address */
- if ((*b) != 0) {
- *addr=save1; /* restore *addr */
- *b=save2; /* restore *b */
- return (0);
- }
- val = *addr; /* read *addr */
- val = *addr; /* read *addr */
-
- *addr=save1;
- *b=save2;
-
- if (val != cnt) {
- debug("Found %08x at Address %08x (failure)\n", (unsigned int)val, (unsigned int) addr);
- /* fix boundary condition.. STARTVAL means zero */
- if(cnt==STARTVAL/sizeof(long)) cnt=0;
- return (cnt * sizeof(long));
- }
- }
- return maxsize;
-}
-
-#ifdef CONFIG_MV64360_ECC
-/*
- * mv_dma_is_channel_active:
- * Checks if a engine is busy.
- */
-int mv_dma_is_channel_active(int engine)
-{
- ulong data;
-
- data = GTREGREAD(MV64360_DMA_CHANNEL0_CONTROL + 4 * engine);
- if (data & BIT14) /* activity status */
- return 1;
-
- return 0;
-}
-
-/*
- * mv_dma_set_memory_space:
- * Set a DMA memory window for the DMA's address decoding map.
- */
-int mv_dma_set_memory_space(ulong mem_space, ulong mem_space_target,
- ulong mem_space_attr, ulong base_address,
- ulong size)
-{
- ulong temp;
-
- /* The base address must be aligned to the size. */
- if (base_address % size != 0)
- return 0;
-
- if (size >= 0x10000) {
- size &= 0xffff0000;
- base_address = (base_address & 0xffff0000);
- /* Set the new attributes */
- GT_REG_WRITE(MV64360_DMA_BASE_ADDR_REG0 + mem_space * 8,
- (base_address | mem_space_target |
- mem_space_attr));
- GT_REG_WRITE((MV64360_DMA_SIZE_REG0 + mem_space * 8),
- (size - 1) & 0xffff0000);
- temp = GTREGREAD(MV64360_DMA_BASE_ADDR_ENABLE_REG);
- GT_REG_WRITE(DMA_BASE_ADDR_ENABLE_REG,
- (temp & ~(BIT0 << mem_space)));
- return 1;
- }
-
- return 0;
-}
-
-
-/*
- * mv_dma_transfer:
- * Transfer data from source_addr to dest_addr on one of the 4 DMA channels.
- */
-int mv_dma_transfer(int engine, ulong source_addr,
- ulong dest_addr, ulong bytes, ulong command)
-{
- ulong eng_off_reg; /* Engine Offset Register */
-
- if (bytes > 0xffff)
- command = command | BIT31; /* DMA_16M_DESCRIPTOR_MODE */
-
- command = command | ((command >> 6) & 0x7);
- eng_off_reg = engine * 4;
- GT_REG_WRITE(MV64360_DMA_CHANNEL0_BYTE_COUNT + eng_off_reg,
- bytes);
- GT_REG_WRITE(MV64360_DMA_CHANNEL0_SOURCE_ADDR + eng_off_reg,
- source_addr);
- GT_REG_WRITE(MV64360_DMA_CHANNEL0_DESTINATION_ADDR + eng_off_reg,
- dest_addr);
- command |= BIT12 /* DMA_CHANNEL_ENABLE */
- | BIT9; /* DMA_NON_CHAIN_MODE */
-
- /* Activate DMA engine By writting to mv_dma_control_register */
- GT_REG_WRITE(MV64360_DMA_CHANNEL0_CONTROL + eng_off_reg, command);
-
- return 1;
-}
-#endif /* of ifdef CONFIG_MV64360_ECC */
-
-/* ppcboot interface function to SDRAM init - this is where all the
- * controlling logic happens */
-phys_size_t
-initdram(int board_type)
-{
- int checkbank[4] = { [0 ... 3] = 0 };
- ulong realsize, total, check;
- AUX_MEM_DIMM_INFO dimmInfo1;
- AUX_MEM_DIMM_INFO dimmInfo2;
- int bank_no, nhr;
-#ifdef CONFIG_MV64360_ECC
- ulong dest, mem_space_attr;
-#endif /* of ifdef CONFIG_MV64360_ECC */
-
- /* first, use the SPD to get info about the SDRAM/ DDRRAM */
-
- /* check the NHR bit and skip mem init if it's already done */
- nhr = get_hid0() & (1 << 16);
-
- if (nhr) {
- printf("Skipping SD- DDRRAM setup due to NHR bit being set\n");
- } else {
- /* DIMM0 */
- (void)check_dimm(0, &dimmInfo1);
-
- /* DIMM1 */
- (void)check_dimm(1, &dimmInfo2);
-
- memory_map_bank(0, 0, 0);
- memory_map_bank(1, 0, 0);
- memory_map_bank(2, 0, 0);
- memory_map_bank(3, 0, 0);
-
- if (dimmInfo1.numOfModuleBanks && setup_sdram(&dimmInfo1)) {
- printf("Setup for DIMM1 failed.\n");
- }
-
- if (dimmInfo2.numOfModuleBanks && setup_sdram(&dimmInfo2)) {
- printf("Setup for DIMM2 failed.\n");
- }
-
- /* set the NHR bit */
- set_hid0(get_hid0() | (1 << 16));
- }
- /* next, size the SDRAM banks */
-
- realsize = total = 0;
- check = GB/4;
- if (dimmInfo1.numOfModuleBanks > 0) {checkbank[0] = 1; printf("-- DIMM1 has 1 bank\n");}
- if (dimmInfo1.numOfModuleBanks > 1) {checkbank[1] = 1; printf("-- DIMM1 has 2 banks\n");}
- if (dimmInfo1.numOfModuleBanks > 2)
- printf("Error, SPD claims DIMM1 has >2 banks\n");
-
- if (dimmInfo2.numOfModuleBanks > 0) {checkbank[2] = 1; printf("-- DIMM2 has 1 bank\n");}
- if (dimmInfo2.numOfModuleBanks > 1) {checkbank[3] = 1; printf("-- DIMM2 has 2 banks\n");}
- if (dimmInfo2.numOfModuleBanks > 2)
- printf("Error, SPD claims DIMM2 has >2 banks\n");
-
- for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
- /* skip over banks that are not populated */
- if (! checkbank[bank_no])
- continue;
-
- if ((total + check) > CONFIG_SYS_GT_REGS)
- check = CONFIG_SYS_GT_REGS - total;
-
- memory_map_bank(bank_no, total, check);
- realsize = dram_size((long int *)total, check);
- memory_map_bank(bank_no, total, realsize);
-
-#ifdef CONFIG_MV64360_ECC
- if (((dimmInfo1.errorCheckType != 0) &&
- ((dimmInfo2.errorCheckType != 0) ||
- (dimmInfo2.numOfModuleBanks == 0))) &&
- (CPCI750_ECC_TEST)) {
- printf("ECC Initialization of Bank %d:", bank_no);
- mem_space_attr = ((~(BIT0 << bank_no)) & 0xf) << 8;
- mv_dma_set_memory_space(0, 0, mem_space_attr, total,
- realsize);
- for (dest = total; dest < total + realsize;
- dest += _8M) {
- mv_dma_transfer(0, total, dest, _8M,
- BIT8 | /* DMA_DTL_128BYTES */
- BIT3 | /* DMA_HOLD_SOURCE_ADDR */
- BIT11); /* DMA_BLOCK_TRANSFER_MODE */
- while (mv_dma_is_channel_active(0))
- ;
- }
- printf(" PASS\n");
- }
-#endif /* of ifdef CONFIG_MV64360_ECC */
-
- total += realsize;
- }
-
-/* Setup Ethernet DMA Adress window to DRAM Area */
- return(total);
-}
-
-/* ***************************************************************************************
-! * SDRAM INIT *
-! * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb *
-! * This procedure fits only the Atlantis *
-! * *
-! *************************************************************************************** */
-
-
-/* ***************************************************************************************
-! * DFCDL initialize MV643xx Design Considerations *
-! * *
-! *************************************************************************************** */
-int set_dfcdlInit (void)
-{
- int i;
- unsigned int dfcdl_word = 0x0000014f;
-
- for (i = 0; i < 64; i++) {
- GT_REG_WRITE (SRAM_DATA0, dfcdl_word);
- }
- GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000); /* enable dynamic delay line updating */
-
-
- return (0);
-}
-
-int do_show_ecc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned int ecc_counter;
- unsigned int ecc_addr;
-
- GT_REG_READ(0x1458, &ecc_counter);
- GT_REG_READ(0x1450, &ecc_addr);
- GT_REG_WRITE(0x1450, 0);
-
- printf("Error Counter since Reset: %8d\n", ecc_counter);
- printf("Last error address :0x%08x (" , ecc_addr & 0xfffffff8);
- if (ecc_addr & 0x01)
- printf("double");
- else
- printf("single");
- printf(" bit) at DDR-RAM CS#%d\n", ((ecc_addr & 0x6) >> 1));
-
- return 0;
-}
-
-
-U_BOOT_CMD(
- show_ecc, 1, 1, do_show_ecc,
- "Show Marvell MV64360 ECC Info",
- "Show Marvell MV64360 ECC Counter and last error."
-);
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * modified for marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * modified for cpci750 board by
- * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * serial.c - serial support for esd cpci750 board
- */
-
-/* supports the MPSC */
-
-#include <common.h>
-#include <command.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-#include "../../Marvell/include/memory.h"
-
-#include "mpsc.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int cpci750_serial_init(void)
-{
- mpsc_init (gd->baudrate);
-
- return (0);
-}
-
-static void cpci750_serial_putc(const char c)
-{
- if (c == '\n')
- mpsc_putchar ('\r');
-
- mpsc_putchar (c);
-}
-
-static int cpci750_serial_getc(void)
-{
- return mpsc_getchar ();
-}
-
-static int cpci750_serial_tstc(void)
-{
- return mpsc_test_char ();
-}
-
-static void cpci750_serial_setbrg(void)
-{
- galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
-}
-
-static struct serial_device cpci750_serial_drv = {
- .name = "cpci750_serial",
- .start = cpci750_serial_init,
- .stop = NULL,
- .setbrg = cpci750_serial_setbrg,
- .putc = cpci750_serial_putc,
- .puts = default_serial_puts,
- .getc = cpci750_serial_getc,
- .tstc = cpci750_serial_tstc,
-};
-
-void cpci750_serial_initialize(void)
-{
- serial_register(&cpci750_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &cpci750_serial_drv;
-}
-
-#if defined(CONFIG_CMD_KGDB)
-void kgdb_serial_init (void)
-{
-}
-
-void putDebugChar (int c)
-{
- serial_putc (c);
-}
-
-void putDebugStr (const char *str)
-{
- serial_puts (str);
-}
-
-int getDebugChar (void)
-{
- return serial_getc ();
-}
-
-void kgdb_interruptible (int yes)
-{
- return;
-}
-#endif
if TARGET_MEESC
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "meesc"
if TARGET_OTC570
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "otc570"
*/
int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- unsigned int *ptr = 0;
+ unsigned int *ptr;
int count = 0;
int count2 = 0;
int i;
* Mark sync address
*/
ptr = 0;
+ /* cppcheck-suppress nullPointer */
*ptr = 0xffffffff;
puts("\nWaiting for image from pci host -");
/*
* Wait for host to write the start address
*/
+ /* cppcheck-suppress nullPointer */
while (*ptr == 0xffffffff) {
count++;
if (!(count % 100)) {
return 1;
}
- base = gd->bd->bi_memsize;
+ base = (u32)gd->ram_size;
#if defined(CONFIG_LOGBUFFER)
base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
#endif
/*
- * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MEM_TOP_HIDE
+ * gd->ram_size == physical ram size - CONFIG_SYS_MEM_TOP_HIDE
*/
param = base - (pram << 10);
printf("PARAM: @%08x\n", param);
- debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->bd->bi_memsize, base);
+ debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->ram_size, base);
/* clear entire PA ram */
memset((void*)param, 0, (pram << 10));
if TARGET_IMA3_MX53
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "ima3-mx53"
if TARGET_CPU9260
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "cpu9260"
if TARGET_CPUAT91
-config SYS_CPU
- default "arm920t"
-
config SYS_BOARD
default "cpuat91"
+++ /dev/null
-if TARGET_HWW1U1A
-
-config SYS_BOARD
- default "hww1u1a"
-
-config SYS_VENDOR
- default "exmeritus"
-
-config SYS_CONFIG_NAME
- default "HWW1U1A"
-
-endif
+++ /dev/null
-HWW1U1A BOARD
-#M: Kyle Moffett <Kyle.D.Moffett@boeing.com>
-S: Orphan (since 2014-06)
-F: board/exmeritus/hww1u1a/
-F: include/configs/HWW1U1A.h
-F: configs/HWW1U1A_defconfig
+++ /dev/null
-#
-# Copyright 2007-2009 Freescale Semiconductor, Inc.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += hww1u1a.o
-obj-y += law.o
-obj-y += tlb.o
-obj-$(CONFIG_DDR_SPD) += ddr.o
+++ /dev/null
-/*
- * Copyright 2009-2010 eXMeritus, A Boeing Company
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- /*
- * We only support one DIMM, so according to the P2020 docs we should
- * set the options as follows:
- */
- popts->cs_local_opts[0].odt_rd_cfg = 0;
- popts->cs_local_opts[0].odt_wr_cfg = 4;
- popts->cs_local_opts[1].odt_rd_cfg = 0;
- popts->cs_local_opts[1].odt_wr_cfg = 0;
- popts->half_strength_driver_enable = 0;
-
- /* Manually configured for our static clock rate */
- popts->clk_adjust = 4;
- popts->cpo_override = 4;
- popts->write_data_delay = 2;
- popts->twot_en = 0;
-}
+++ /dev/null
-/*
- * Copyright 2010 eXMeritus, A Boeing Company
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/mpc85xx_gpio.h>
-
-/* Common CPU A/B GPIOs (GPIO8-GPIO15 and IRQ4-IRQ6) */
-#define GPIO_CPU_ID (1UL << (31 - 8))
-#define GPIO_BLUE_LED (1UL << (31 - 9))
-#define GPIO_DIMM_RESET (1UL << (31 - 10))
-#define GPIO_USB_RESET (1UL << (31 - 11))
-#define GPIO_UNUSED_12 (1UL << (31 - 12))
-#define GPIO_GETH0_RESET (1UL << (31 - 13))
-#define GPIO_RS422_RE (1UL << (31 - 14))
-#define GPIO_RS422_DE (1UL << (31 - 15))
-#define IRQ_I2CINT (1UL << (31 - 20))
-#define IRQ_FANINT (1UL << (31 - 21))
-#define IRQ_DIMM_EVENT (1UL << (31 - 22))
-
-#define GPIO_RESETS (GPIO_DIMM_RESET|GPIO_USB_RESET|GPIO_GETH0_RESET)
-
-/* CPU A GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */
-#define GPIO_CPUA_UNUSED_0 (1UL << (31 - 0))
-#define GPIO_CPUA_CPU_READY (1UL << (31 - 1))
-#define GPIO_CPUA_DEBUG_LED2 (1UL << (31 - 2))
-#define GPIO_CPUA_DEBUG_LED1 (1UL << (31 - 3))
-#define GPIO_CPUA_TDIS2B (1UL << (31 - 4)) /* MAC 2 TX B */
-#define GPIO_CPUA_TDIS2A (1UL << (31 - 5)) /* MAC 2 TX A */
-#define GPIO_CPUA_TDIS1B (1UL << (31 - 6)) /* MAC 1 TX B */
-#define GPIO_CPUA_TDIS1A (1UL << (31 - 7)) /* MAC 1 TX A */
-#define IRQ_CPUA_UNUSED_0 (1UL << (31 - 16))
-#define IRQ_CPUA_UNUSED_1 (1UL << (31 - 17))
-#define IRQ_CPUA_UNUSED_2 (1UL << (31 - 18))
-#define IRQ_CPUA_UNUSED_3 (1UL << (31 - 19))
-
-/* CPU B GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */
-#define GPIO_CPUB_RMUX_SEL1B (1UL << (31 - 0))
-#define GPIO_CPUB_RMUX_SEL0B (1UL << (31 - 1))
-#define GPIO_CPUB_RMUX_SEL1A (1UL << (31 - 2))
-#define GPIO_CPUB_RMUX_SEL0A (1UL << (31 - 3))
-#define GPIO_CPUB_UNUSED_4 (1UL << (31 - 4))
-#define GPIO_CPUB_CPU_READY (1UL << (31 - 5))
-#define GPIO_CPUB_DEBUG_LED2 (1UL << (31 - 6))
-#define GPIO_CPUB_DEBUG_LED1 (1UL << (31 - 7))
-#define IRQ_CPUB_SD_1A (1UL << (31 - 16))
-#define IRQ_CPUB_SD_2B (1UL << (31 - 17))
-#define IRQ_CPUB_SD_2A (1UL << (31 - 18))
-#define IRQ_CPUB_SD_1B (1UL << (31 - 19))
-
-/* If it isn't CPU A then it's CPU B */
-static inline unsigned int hww1u1a_is_cpu_a(void)
-{
- return !mpc85xx_gpio_get(GPIO_CPU_ID);
-}
+++ /dev/null
-/*
- * Copyright 2009-2011 eXMeritus, A Boeing Company
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#include <libfdt.h>
-#include <linux/ctype.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <asm/fsl_law.h>
-#include <netdev.h>
-#include <malloc.h>
-#include <i2c.h>
-#include <pca953x.h>
-
-#include "gpios.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- unsigned int gpio_high = 0;
- unsigned int gpio_low = 0;
- unsigned int gpio_in = 0;
- unsigned int i;
- struct ccsr_ddr __iomem *ddr;
-
- puts("Board: HWW-1U-1A ");
-
- /*
- * First just figure out which CPU we're on, then use that to
- * configure the lists of other GPIOs to be programmed.
- */
- mpc85xx_gpio_set_in(GPIO_CPU_ID);
- if (hww1u1a_is_cpu_a()) {
- puts("CPU A\n");
-
- /* We want to turn on some LEDs */
- gpio_high |= GPIO_CPUA_CPU_READY;
- gpio_low |= GPIO_CPUA_DEBUG_LED1;
- gpio_low |= GPIO_CPUA_DEBUG_LED2;
-
- /* Disable the unused transmitters */
- gpio_low |= GPIO_CPUA_TDIS1A;
- gpio_high |= GPIO_CPUA_TDIS1B;
- gpio_low |= GPIO_CPUA_TDIS2A;
- gpio_high |= GPIO_CPUA_TDIS2B;
- } else {
- puts("CPU B\n");
-
- /* We want to turn on some LEDs */
- gpio_high |= GPIO_CPUB_CPU_READY;
- gpio_low |= GPIO_CPUB_DEBUG_LED1;
- gpio_low |= GPIO_CPUB_DEBUG_LED2;
-
- /* Enable the appropriate receivers */
- gpio_high |= GPIO_CPUB_RMUX_SEL0A;
- gpio_high |= GPIO_CPUB_RMUX_SEL0B;
- gpio_low |= GPIO_CPUB_RMUX_SEL1A;
- gpio_low |= GPIO_CPUB_RMUX_SEL1B;
- }
-
- /* These GPIOs are common */
- gpio_in |= IRQ_I2CINT | IRQ_FANINT | IRQ_DIMM_EVENT;
- gpio_low |= GPIO_RS422_RE;
- gpio_high |= GPIO_RS422_DE;
-
- /* Ok, now go ahead and program all of those in one go */
- mpc85xx_gpio_set(gpio_high|gpio_low|gpio_in,
- gpio_high|gpio_low,
- gpio_high);
-
- /*
- * If things have been taken out of reset early (for example, by one
- * of the BDI3000 debuggers), then we need to put them back in reset
- * and delay a while before we continue.
- */
- if (mpc85xx_gpio_get(GPIO_RESETS)) {
- ddr = (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
-
- puts("Debugger detected... extra device reset enabled!\n");
-
- /* Put stuff into reset and disable the DDR controller */
- mpc85xx_gpio_set_low(GPIO_RESETS);
- out_be32(&ddr->sdram_cfg, 0x00000000);
-
- puts(" Waiting 1 sec for reset...");
- for (i = 0; i < 10; i++) {
- udelay(100000);
- puts(".");
- }
- puts("\n");
- }
-
- /* Now bring everything back out of reset again */
- mpc85xx_gpio_set_high(GPIO_RESETS);
- return 0;
-}
-
-/*
- * This little shell function just returns whether or not it's CPU A.
- * It can be used to select the right device-tree when booting, etc.
- */
-int do_hww1u1a_test_cpu_a(cmd_tbl_t *cmdtp, int flag,
- int argc, char * const argv[])
-{
- if (argc > 1)
- cmd_usage(cmdtp);
-
- if (hww1u1a_is_cpu_a())
- return 0;
- else
- return 1;
-}
-U_BOOT_CMD(
- test_cpu_a, 1, 0, do_hww1u1a_test_cpu_a,
- "Test if this is CPU A (versus B) on the eXMeritus HWW-1U-1A board",
- ""
-);
-
-/* Create a prompt-like string: "uboot@HOSTNAME% " */
-#define PROMPT_PREFIX "uboot@exm"
-#define PROMPT_SUFFIX "% "
-
-/* This function returns a PS1 prompt based on the serial number */
-static char *hww1u1a_prompt;
-const char *hww1u1a_get_ps1(void)
-{
- unsigned long len, i, j;
- const char *serialnr;
-
- /* If our prompt was already set, just use that */
- if (hww1u1a_prompt)
- return hww1u1a_prompt;
-
- /* Use our serial number if present, otherwise a default */
- serialnr = getenv("serial#");
- if (!serialnr || !serialnr[0])
- serialnr = "999999-X";
-
- /*
- * We will turn the serial number into a hostname by:
- * (A) Delete all non-alphanumerics.
- * (B) Lowercase all letters.
- * (C) Prefix "exm".
- * (D) Suffix "a" for CPU A and "b" for CPU B.
- */
- for (i = 0, len = 0; serialnr[i]; i++) {
- if (isalnum(serialnr[i]))
- len++;
- }
-
- len += sizeof(PROMPT_PREFIX PROMPT_SUFFIX) + 1; /* Includes NUL */
- hww1u1a_prompt = malloc(len);
- if (!hww1u1a_prompt)
- return PROMPT_PREFIX "UNKNOWN(ENOMEM)" PROMPT_SUFFIX;
-
- /* Now actually fill it in */
- i = 0;
-
- /* Handle the prefix */
- for (j = 0; j < sizeof(PROMPT_PREFIX) - 1; j++)
- hww1u1a_prompt[i++] = PROMPT_PREFIX[j];
-
- /* Now the serial# part of the hostname */
- for (j = 0; serialnr[j]; j++)
- if (isalnum(serialnr[j]))
- hww1u1a_prompt[i++] = tolower(serialnr[j]);
-
- /* Now the CPU id ("a" or "b") */
- hww1u1a_prompt[i++] = hww1u1a_is_cpu_a() ? 'a' : 'b';
-
- /* Finally the suffix */
- for (j = 0; j < sizeof(PROMPT_SUFFIX); j++)
- hww1u1a_prompt[i++] = PROMPT_SUFFIX[j];
-
- /* This should all have added up, but just in case */
- hww1u1a_prompt[len - 1] = '\0';
-
- /* Now we're done */
- return hww1u1a_prompt;
-}
-
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap bootflash region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for FLASH */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- struct tsec_info_struct tsec_info[4];
- struct fsl_pq_mdio_info mdio_info;
-
- SET_STD_TSEC_INFO(tsec_info[0], 1);
- SET_STD_TSEC_INFO(tsec_info[1], 2);
- SET_STD_TSEC_INFO(tsec_info[2], 3);
-
- if (hww1u1a_is_cpu_a())
- tsec_info[2].phyaddr = TSEC3_PHY_ADDR_CPUA;
- else
- tsec_info[2].phyaddr = TSEC3_PHY_ADDR_CPUB;
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, 3);
- return pci_eth_init(bis);
-}
-
-void ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = getenv_bootm_low();
- size = getenv_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
- FT_FSL_PCI_SETUP;
-}
+++ /dev/null
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
+++ /dev/null
-/*
- * Copyright 2009-2010 eXMeritus, A Boeing Company
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 0 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 0 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Boot page */
- SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR,
- CONFIG_BPTR_VIRT_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR,
- CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
- /*
- * W**G* - FLASH (Will be *I*G* after relocation to RAM)
- *
- * This maps both SPI FLASH chips (128MByte per chip)
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
- /*
- * *I*G* - PCI memory
- *
- * We have 1.5GB total PCI-E memory space to map and we want to use
- * the minimum possible number of TLB entries. Since Book-E TLB
- * entries are sized in powers of 4, we use 1GB + 256MB + 256MB.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT,
- CONFIG_SYS_PCIE3_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
- CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
- CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
-
- /*
- * *I*G* - PCI I/O
- *
- * This one entry covers all 3 64k PCI-E I/O windows
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT,
- CONFIG_SYS_PCIE3_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256K, 1),
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
if TARGET_A320EVB
-config SYS_CPU
- default "arm920t"
-
config SYS_BOARD
default "a320evb"
if TARGET_LS1021AQDS
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "ls1021aqds"
if TARGET_LS1021ATWR
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "ls1021atwr"
To configure for the current (Rev 3.x) ADS5121
- make ads5121_config
+ make mpc5121ads_config
This will automatically include PCI, the Real Time CLock, add backup flash
ability and set the correct frequency and memory configuration.
To configure for the older Rev 2 ADS5121 type (this will not have PCI)
- make ads5121_rev2_config
+ make mpc5121ads_rev2_config
if TARGET_MX23EVK
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "mx23evk"
if TARGET_MX25PDK
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "mx25pdk"
if TARGET_MX28EVK
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "mx28evk"
if TARGET_MX31ADS
-config SYS_CPU
- default "arm1136"
-
config SYS_BOARD
default "mx31ads"
if TARGET_MX31PDK
-config SYS_CPU
- default "arm1136"
-
config SYS_BOARD
default "mx31pdk"
if TARGET_MX35PDK
-config SYS_CPU
- default "arm1136"
-
config SYS_BOARD
default "mx35pdk"
if TARGET_MX51EVK
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "mx51evk"
if TARGET_MX53ARD
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "mx53ard"
if TARGET_MX53EVK
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "mx53evk"
if TARGET_MX53LOCO
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "mx53loco"
if TARGET_MX53SMD
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "mx53smd"
if TARGET_MX6QARM2
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "mx6qarm2"
if TARGET_MX6QSABREAUTO
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "mx6qsabreauto"
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/spi.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/sys_proto.h>
#include <i2c.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/imx-common/video.h>
+#include <asm/arch/crm_regs.h>
+#include <pca953x.h>
DECLARE_GLOBAL_DATA_PTR;
MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
+/*Define for building port exp gpio, pin starts from 0*/
+#define PORTEXP_IO_NR(chip, pin) \
+ ((chip << 5) + pin)
+
+/*Get the chip addr from a ioexp gpio*/
+#define PORTEXP_IO_TO_CHIP(gpio_nr) \
+ (gpio_nr >> 5)
+
+/*Get the pin number from a ioexp gpio*/
+#define PORTEXP_IO_TO_PIN(gpio_nr) \
+ (gpio_nr & 0x1f)
+
+static int port_exp_direction_output(unsigned gpio, int value)
+{
+ int ret;
+
+ i2c_set_bus_num(2);
+ ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
+ if (ret)
+ return ret;
+
+ ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
+ (1 << PORTEXP_IO_TO_PIN(gpio)),
+ (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
+
+ if (ret)
+ return ret;
+
+ ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
+ (1 << PORTEXP_IO_TO_PIN(gpio)),
+ (value << PORTEXP_IO_TO_PIN(gpio)));
+
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
static void setup_iomux_enet(void)
{
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
return (get_cpu_rev() & ~(0xF << 8)) | rev;
}
+#if defined(CONFIG_VIDEO_IPUV3)
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+ imx_enable_hdmi_phy();
+}
+
+struct display_info_t const displays[] = {{
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = do_enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED,
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ int reg;
+
+ enable_ipu_clock();
+ imx_setup_hdmi();
+
+ reg = readl(&mxc_ccm->chsccdr);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->chsccdr);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
int board_early_init_f(void)
{
setup_iomux_uart();
-
+#ifdef CONFIG_VIDEO_IPUV3
+ setup_display();
+#endif
return 0;
}
return 0;
}
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7)
+#define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1)
+
+iomux_v3_cfg_t const usb_otg_pads[] = {
+ MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_ehci_hcd_init(int port)
+{
+ switch (port) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ ARRAY_SIZE(usb_otg_pads));
+
+ /*
+ * Set daisy chain for otg_pin_id on 6q.
+ * For 6dl, this bit is reserved.
+ */
+ imx_iomux_set_gpr_register(1, 13, 1, 0);
+ break;
+ case 1:
+ break;
+ default:
+ printf("MXC USB port %d not yet supported\n", port);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+ switch (port) {
+ case 0:
+ if (on)
+ port_exp_direction_output(USB_OTG_PWR, 1);
+ else
+ port_exp_direction_output(USB_OTG_PWR, 0);
+ break;
+ case 1:
+ if (on)
+ port_exp_direction_output(USB_HOST1_PWR, 1);
+ else
+ port_exp_direction_output(USB_HOST1_PWR, 0);
+ break;
+ default:
+ printf("MXC USB port %d not yet supported\n", port);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+#endif
if TARGET_MX6SABRESD
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "mx6sabresd"
#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
+#define DISP0_PWR_EN IMX_GPIO_NR(1, 21)
+
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
+static iomux_v3_cfg_t const rgb_pads[] = {
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void enable_rgb(struct display_info_t const *dev)
+{
+ imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads));
+ gpio_direction_output(DISP0_PWR_EN, 1);
+}
+
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = 0,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = NULL,
+ .enable = enable_rgb,
+ .mode = {
+ .name = "SEIKO-WVGA",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 29850,
+ .left_margin = 89,
+ .right_margin = 164,
+ .upper_margin = 23,
+ .lower_margin = 10,
+ .hsync_len = 10,
+ .vsync_len = 10,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
} } };
size_t display_count = ARRAY_SIZE(displays);
if TARGET_MX6SLEVK
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "mx6slevk"
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/spi.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
};
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ /* 8 bit SD */
+ MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /*CD pin*/
+ MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
static iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /*CD pin*/
+ MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /*CD pin*/
+ MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const fec_pads[] = {
gpio_set_value(ETH_PHY_RESET, 1);
}
-static struct fsl_esdhc_cfg usdhc_cfg[1] = {
- {USDHC2_BASE_ADDR},
+#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7)
+#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0)
+#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22)
+
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+ {USDHC1_BASE_ADDR},
+ {USDHC2_BASE_ADDR, 0, 4},
+ {USDHC3_BASE_ADDR, 0, 4},
};
int board_mmc_getcd(struct mmc *mmc)
{
- return 1; /* Assume boot SD always present */
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ ret = !gpio_get_value(USDHC1_CD_GPIO);
+ break;
+ case USDHC2_BASE_ADDR:
+ ret = !gpio_get_value(USDHC2_CD_GPIO);
+ break;
+ case USDHC3_BASE_ADDR:
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ break;
+ }
+
+ return ret;
}
int board_mmc_init(bd_t *bis)
{
- imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ int i, ret;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC1
+ * mmc1 USDHC2
+ * mmc2 USDHC3
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ gpio_direction_input(USDHC1_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ gpio_direction_input(USDHC2_CD_GPIO);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ break;
+ case 2:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ gpio_direction_input(USDHC3_CD_GPIO);
+ usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) than supported by the board\n", i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret) {
+ printf("Warning: failed to initialize "
+ "mmc dev %d\n", i);
+ return ret;
+ }
+ }
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+ return 0;
}
#ifdef CONFIG_FEC_MXC
if TARGET_MX6SXSABRESD
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "mx6sxsabresd"
if TARGET_VF610TWR
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "vf610twr"
if TARGET_GR_CPCI_AX2000
-config SYS_CPU
- default "leon3"
-
config SYS_BOARD
default "gr_cpci_ax2000"
-config SYS_VENDOR
- default "gaisler"
-
config SYS_CONFIG_NAME
default "gr_cpci_ax2000"
+++ /dev/null
-#
-# (C) Copyright 2008
-# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#
-# GR-CPCI-AX2000 board
-#
-
-# U-BOOT IN FLASH
-CONFIG_SYS_TEXT_BASE = 0x00000000
-
-# U-BOOT IN RAM or SDRAM with -nosram flag set when starting GRMON
-#CONFIG_SYS_TEXT_BASE = 0x40000000
-
-# U-BOOT IN SDRAM
-#CONFIG_SYS_TEXT_BASE = 0x60000000
if TARGET_GR_EP2S60
-config SYS_CPU
- default "leon3"
-
config SYS_BOARD
default "gr_ep2s60"
-config SYS_VENDOR
- default "gaisler"
-
config SYS_CONFIG_NAME
default "gr_ep2s60"
+++ /dev/null
-#
-# (C) Copyright 2008
-# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#
-# Altera NIOS delopment board Stratix II edition, FPGA device EP2S60,
-# with GRLIB Template design (GPL Open Source SPARC/LEON3)
-#
-
-# U-BOOT IN FLASH
-CONFIG_SYS_TEXT_BASE = 0x00000000
-
-# U-BOOT IN SDRAM
-#CONFIG_SYS_TEXT_BASE = 0x40000000
if TARGET_GR_XC3S_1500
-config SYS_CPU
- default "leon3"
-
config SYS_BOARD
default "gr_xc3s_1500"
-config SYS_VENDOR
- default "gaisler"
-
config SYS_CONFIG_NAME
default "gr_xc3s_1500"
+++ /dev/null
-#
-# (C) Copyright 2007
-# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#
-# GR-XC3S-1500 board
-#
-
-# U-BOOT IN FLASH
-CONFIG_SYS_TEXT_BASE = 0x00000000
-
-# U-BOOT IN RAM
-#CONFIG_SYS_TEXT_BASE = 0x40000000
if TARGET_GRSIM
-config SYS_CPU
- default "leon3"
-
config SYS_BOARD
default "grsim"
-config SYS_VENDOR
- default "gaisler"
-
config SYS_CONFIG_NAME
default "grsim"
+++ /dev/null
-#
-# (C) Copyright 2007
-# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#
-# GRSIM simulating a LEON3 GR-XC3S-1500 board
-#
-
-# U-BOOT IN FLASH
-CONFIG_SYS_TEXT_BASE = 0x00000000
-
-# U-BOOT IN RAM
-#CONFIG_SYS_TEXT_BASE = 0x40000000
if TARGET_GRSIM_LEON2
-config SYS_CPU
- default "leon2"
-
config SYS_BOARD
default "grsim_leon2"
-config SYS_VENDOR
- default "gaisler"
-
config SYS_CONFIG_NAME
default "grsim_leon2"
+++ /dev/null
-#
-# (C) Copyright 2007
-# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#
-# GRSIM simulating a LEON2 board
-#
-
-# RUN U-BOOT FROM PROM
-CONFIG_SYS_TEXT_BASE = 0x00000000
-
-# RUN U-BOOT FROM RAM
-#CONFIG_SYS_TEXT_BASE = 0x40000000
if TARGET_GW_VENTANA
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "gw_ventana"
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/sata.h>
+#include <asm/imx-common/spi.h>
#include <asm/imx-common/video.h>
#include <jffs2/load_kernel.h>
#include <hwconfig.h>
if TARGET_MX51_EFIKAMX
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "mx51_efikamx"
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
+#include <asm/imx-common/spi.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
if TARGET_PEPPER
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "pepper"
if TARGET_H2200
-config SYS_CPU
- default "pxa"
-
config SYS_BOARD
default "h2200"
if TARGET_TT01
-config SYS_CPU
- default "arm1136"
-
config SYS_BOARD
default "tt01"
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))\
MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4))\
/* JTAG */\
- MUX_VAL(CP(JTAG_nTRST), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(JTAG_TCK), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M4)) \
+++ /dev/null
-if TARGET_HYMOD
-
-config SYS_BOARD
- default "hymod"
-
-config SYS_CONFIG_NAME
- default "hymod"
-
-endif
+++ /dev/null
-HYMOD BOARD
-M: Murray Jensen <Murray.Jensen@csiro.au>
-S: Maintained
-F: board/hymod/
-F: include/configs/hymod.h
-F: configs/hymod_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = hymod.o flash.o bsp.o eeprom.o fetch.o input.o env.o
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * hacked for Hymod FPGA support by Murray.Jensen@csiro.au, 29-Jan-01
- */
-
-#include <common.h>
-#include <command.h>
-#include <net.h>
-#include <asm/iopin_8260.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*-----------------------------------------------------------------------
- * Board Special Commands: FPGA load/store, EEPROM erase
- */
-
-#if defined(CONFIG_CMD_BSP)
-
-#define LOAD_SUCCESS 0
-#define LOAD_FAIL_NOCONF 1
-#define LOAD_FAIL_NOINIT 2
-#define LOAD_FAIL_NODONE 3
-
-#define STORE_SUCCESS 0
-
-/*
- * Programming the Hymod FPGAs
- *
- * The 8260 io port config table is set up so that the INIT pin is
- * held Low (Open Drain output 0) - this will delay the automatic
- * Power-On config until INIT is released (by making it an input).
- *
- * If the FPGA has been programmed before, then the assertion of PROGRAM
- * will initiate configuration (i.e. it begins clearing the RAM).
- *
- * When the FPGA is ready to receive configuration data (either after
- * releasing INIT after Power-On, or after asserting PROGRAM), it will
- * pull INIT high.
- *
- * Notes from Paul Dunn:
- *
- * 1. program pin should be forced low for >= 300ns
- * (about 20 bus clock cycles minimum).
- *
- * 2. then wait for init to go high, which signals
- * that the FPGA has cleared its internal memory
- * and is ready to load
- *
- * 3. perform load writes of entire config file
- *
- * 4. wait for done to go high, which should be
- * within a few bus clock cycles. If done has not
- * gone high after reasonable period, then load
- * has not worked (wait several ms?)
- */
-
-int
-fpga_load(int mezz, const uchar *addr, ulong size)
-{
- hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
- xlx_info_t *fp;
- xlx_iopins_t *fpgaio;
- volatile uchar *fpgabase;
- volatile uint cnt;
- const uchar *eaddr = addr + size;
- int result;
-
- if (mezz)
- fp = &cp->mezz.xlx[0];
- else
- fp = &cp->main.xlx[0];
-
- if (!fp->mmap.prog.exists)
- return (LOAD_FAIL_NOCONF);
-
- fpgabase = (uchar *)fp->mmap.prog.base;
- fpgaio = &fp->iopins;
-
- /* set enable HIGH if required */
- if (fpgaio->enable_pin.flag)
- iopin_set_high (&fpgaio->enable_pin);
-
- /* ensure INIT is released (set it to be an input) */
- iopin_set_in (&fpgaio->init_pin);
-
- /* toggle PROG Low then High (will already be Low after Power-On) */
- iopin_set_low (&fpgaio->prog_pin);
- udelay (1); /* minimum 300ns - 1usec should do it */
- iopin_set_high (&fpgaio->prog_pin);
-
- /* wait for INIT High */
- cnt = 0;
- while (!iopin_is_high (&fpgaio->init_pin))
- if (++cnt == 10000000) {
- result = LOAD_FAIL_NOINIT;
- goto done;
- }
-
- /* write configuration data */
- while (addr < eaddr)
- *fpgabase = *addr++;
-
- /* wait for DONE High */
- cnt = 0;
- while (!iopin_is_high (&fpgaio->done_pin))
- if (++cnt == 100000000) {
- result = LOAD_FAIL_NODONE;
- goto done;
- }
-
- /* success */
- result = LOAD_SUCCESS;
-
- done:
-
- if (fpgaio->enable_pin.flag)
- iopin_set_low (&fpgaio->enable_pin);
-
- return (result);
-}
-
-/* ------------------------------------------------------------------------- */
-int
-do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- uchar *addr, *save_addr;
- ulong size;
- int mezz, arg, result;
-
- switch (argc) {
-
- case 0:
- case 1:
- break;
-
- case 2:
- if (strcmp (argv[1], "info") == 0) {
- printf ("\nHymod FPGA Info...\n");
- printf ("\t\t\t\tAddress\t\tSize\n");
- printf ("\tMain Configuration:\t0x%08x\t%d\n",
- FPGA_MAIN_CFG_BASE, FPGA_MAIN_CFG_SIZE);
- printf ("\tMain Register:\t\t0x%08x\t%d\n",
- FPGA_MAIN_REG_BASE, FPGA_MAIN_REG_SIZE);
- printf ("\tMain Port:\t\t0x%08x\t%d\n",
- FPGA_MAIN_PORT_BASE, FPGA_MAIN_PORT_SIZE);
- printf ("\tMezz Configuration:\t0x%08x\t%d\n",
- FPGA_MEZZ_CFG_BASE, FPGA_MEZZ_CFG_SIZE);
- return 0;
- }
- break;
-
- case 3:
- if (strcmp (argv[1], "store") == 0) {
- addr = (uchar *) simple_strtoul (argv[2], NULL, 16);
-
- save_addr = addr;
-#if 0
- /* fpga readback unimplemented */
- while (more readback data)
- *addr++ = *fpga;
- result = error ? STORE_FAIL_XXX : STORE_SUCCESS;
-#else
- result = STORE_SUCCESS;
-#endif
-
- if (result == STORE_SUCCESS) {
- printf ("SUCCEEDED (%d bytes)\n",
- addr - save_addr);
- return 0;
- } else
- printf ("FAILED (%d bytes)\n",
- addr - save_addr);
- return 1;
- }
- break;
-
- case 4:
- if (strcmp (argv[1], "tftp") == 0) {
- copy_filename (BootFile, argv[2], sizeof (BootFile));
- load_addr = simple_strtoul (argv[3], NULL, 16);
- NetBootFileXferSize = 0;
-
- if (NetLoop(TFTPGET) <= 0) {
- printf ("tftp transfer failed - aborting "
- "fgpa load\n");
- return 1;
- }
-
- if (NetBootFileXferSize == 0) {
- printf ("can't determine file size - "
- "aborting fpga load\n");
- return 1;
- }
-
- printf ("File transfer succeeded - "
- "beginning fpga load...");
-
- result = fpga_load (0, (uchar *) load_addr,
- NetBootFileXferSize);
-
- if (result == LOAD_SUCCESS) {
- printf ("SUCCEEDED\n");
- return 0;
- } else if (result == LOAD_FAIL_NOCONF)
- printf ("FAILED (no CONF)\n");
- else if (result == LOAD_FAIL_NOINIT)
- printf ("FAILED (no INIT)\n");
- else
- printf ("FAILED (no DONE)\n");
- return 1;
-
- }
- /* fall through ... */
-
- case 5:
- if (strcmp (argv[1], "load") == 0) {
- if (argc == 5) {
- if (strcmp (argv[2], "main") == 0)
- mezz = 0;
- else if (strcmp (argv[2], "mezz") == 0)
- mezz = 1;
- else {
- printf ("FPGA type must be either "
- "`main' or `mezz'\n");
- return 1;
- }
- arg = 3;
- } else {
- mezz = 0;
- arg = 2;
- }
-
- addr = (uchar *) simple_strtoul (argv[arg++], NULL, 16);
- size = (ulong) simple_strtoul (argv[arg], NULL, 16);
-
- result = fpga_load (mezz, addr, size);
-
- if (result == LOAD_SUCCESS) {
- printf ("SUCCEEDED\n");
- return 0;
- } else if (result == LOAD_FAIL_NOCONF)
- printf ("FAILED (no CONF)\n");
- else if (result == LOAD_FAIL_NOINIT)
- printf ("FAILED (no INIT)\n");
- else
- printf ("FAILED (no DONE)\n");
- return 1;
- }
- break;
-
- default:
- break;
- }
-
- return cmd_usage(cmdtp);
-}
-U_BOOT_CMD(
- fpga, 6, 1, do_fpga,
- "FPGA sub-system",
- "load [type] addr size\n"
- " - write the configuration data at memory address `addr',\n"
- " size `size' bytes, into the FPGA of type `type' (either\n"
- " `main' or `mezz', default `main'). e.g.\n"
- " `fpga load 100000 7d8f'\n"
- " loads the main FPGA with config data at address 100000\n"
- " HEX, size 7d8f HEX (32143 DEC) bytes\n"
- "fpga tftp file addr\n"
- " - transfers `file' from the tftp server into memory at\n"
- " address `addr', then writes the entire file contents\n"
- " into the main FPGA\n"
- "fpga store addr\n"
- " - read configuration data from the main FPGA (the mezz\n"
- " FPGA is write-only), into address `addr'. There must be\n"
- " enough memory available at `addr' to hold all the config\n"
- " data - the size of which is determined by VC:???\n"
- "fpga info\n"
- " - print information about the Hymod FPGA, namely the\n"
- " memory addresses at which the four FPGA local bus\n"
- " address spaces appear in the physical address space"
-);
-/* ------------------------------------------------------------------------- */
-int
-do_eecl (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- uchar data[HYMOD_EEPROM_SIZE];
- uint addr = CONFIG_SYS_I2C_EEPROM_ADDR;
-
- switch (argc) {
-
- case 1:
- addr |= HYMOD_EEOFF_MAIN;
- break;
-
- case 2:
- if (strcmp (argv[1], "main") == 0) {
- addr |= HYMOD_EEOFF_MAIN;
- break;
- }
- if (strcmp (argv[1], "mezz") == 0) {
- addr |= HYMOD_EEOFF_MEZZ;
- break;
- }
- /* fall through ... */
-
- default:
- return cmd_usage(cmdtp);
- }
-
- memset (data, 0, HYMOD_EEPROM_SIZE);
-
- eeprom_write (addr, 0, data, HYMOD_EEPROM_SIZE);
-
- return 0;
-}
-U_BOOT_CMD(
- eeclear, 1, 0, do_eecl,
- "Clear the eeprom on a Hymod board",
- "[type]\n"
- " - write zeroes into the EEPROM on the board of type `type'\n"
- " (`type' is either `main' or `mezz' - default `main')\n"
- " Note: the EEPROM write enable jumper must be installed"
-);
-
-/* ------------------------------------------------------------------------- */
-
-int
-do_htest (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-#if 0
- int rc;
-#endif
-#ifdef CONFIG_ETHER_LOOPBACK_TEST
- extern void eth_loopback_test (void);
-#endif /* CONFIG_ETHER_LOOPBACK_TEST */
-
- printf ("HYMOD tests - ensure loopbacks etc. are connected\n\n");
-
-#if 0
- /* Load FPGA with test program */
-
- printf ("Loading test FPGA program ...");
-
- rc = fpga_load (0, test_bitfile, sizeof (test_bitfile));
-
- switch (rc) {
-
- case LOAD_SUCCESS:
- printf (" SUCCEEDED\n");
- break;
-
- case LOAD_FAIL_NOCONF:
- printf (" FAILED (no configuration space defined)\n");
- return 1;
-
- case LOAD_FAIL_NOINIT:
- printf (" FAILED (timeout - no INIT signal seen)\n");
- return 1;
-
- case LOAD_FAIL_NODONE:
- printf (" FAILED (timeout - no DONE signal seen)\n");
- return 1;
-
- default:
- printf (" FAILED (unknown return code from fpga_load\n");
- return 1;
- }
-
- /* run Local Bus <=> Xilinx tests */
-
- /* tell Xilinx to run ZBT Ram, High Speed serial and Mezzanine tests */
-
- /* run SDRAM test */
-#endif
-
-#ifdef CONFIG_ETHER_LOOPBACK_TEST
- /* run Ethernet test */
- eth_loopback_test ();
-#endif /* CONFIG_ETHER_LOOPBACK_TEST */
-
- return 0;
-}
-
-#endif
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#
-# HYMOD boards
-#
-
-PLATFORM_CPPFLAGS += -I$(srctree)
-
-OBJCOPYFLAGS = --remove-section=.ppcenv
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8260.h>
-
-/* imports from fetch.c */
-extern int fetch_and_parse (char *, ulong, int (*)(uchar *, uchar *));
-
-/* imports from input.c */
-extern int hymod_get_serno (const char *);
-
-/* this is relative to the root of the server's tftp directory */
-static char *def_bddb_cfgdir = "/hymod/bddb";
-
-static int
-hymod_eeprom_load (int which, hymod_eeprom_t *ep)
-{
- unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \
- (which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN);
- unsigned offset = 0;
- uchar data[HYMOD_EEPROM_MAXLEN], *dp, *edp;
- hymod_eehdr_t hdr;
- ulong len, crc;
-
- memset (ep, 0, sizeof *ep);
-
- eeprom_read (dev_addr, offset, (uchar *)&hdr, sizeof (hdr));
- offset += sizeof (hdr);
-
- if (hdr.id != HYMOD_EEPROM_ID || hdr.ver > HYMOD_EEPROM_VER ||
- (len = hdr.len) > HYMOD_EEPROM_MAXLEN)
- return (0);
-
- eeprom_read (dev_addr, offset, data, len);
- offset += len;
-
- eeprom_read (dev_addr, offset, (uchar *)&crc, sizeof (ulong));
- offset += sizeof (ulong);
-
- if (crc32 (crc32 (0, (uchar *)&hdr, sizeof hdr), data, len) != crc)
- return (0);
-
- ep->ver = hdr.ver;
- dp = data; edp = dp + len;
-
- for (;;) {
- ulong rtyp;
- uchar rlen, *rdat;
-
- rtyp = *dp++;
- if ((rtyp & 0x80) == 0)
- rlen = *dp++;
- else {
- uchar islarge = rtyp & 0x40;
-
- rtyp = ((rtyp & 0x3f) << 8) | *dp++;
- if (islarge) {
- rtyp = (rtyp << 8) | *dp++;
- rtyp = (rtyp << 8) | *dp++;
- }
-
- rlen = *dp++;
- rlen = (rlen << 8) | *dp++;
- if (islarge) {
- rlen = (rlen << 8) | *dp++;
- rlen = (rlen << 8) | *dp++;
- }
- }
-
- if (rtyp == 0)
- break;
-
- rdat = dp;
- dp += rlen;
-
- if (dp > edp) /* error? */
- break;
-
- switch (rtyp) {
-
- case HYMOD_EEREC_SERNO: /* serial number */
- if (rlen == sizeof (ulong))
- ep->serno = \
- ((ulong)rdat[0] << 24) | \
- ((ulong)rdat[1] << 16) | \
- ((ulong)rdat[2] << 8) | \
- (ulong)rdat[3];
- break;
-
- case HYMOD_EEREC_DATE: /* date */
- if (rlen == sizeof (hymod_date_t)) {
- ep->date.year = ((ushort)rdat[0] << 8) | \
- (ushort)rdat[1];
- ep->date.month = rdat[2];
- ep->date.day = rdat[3];
- }
- break;
-
- case HYMOD_EEREC_BATCH: /* batch */
- if (rlen <= HYMOD_MAX_BATCH)
- memcpy (ep->batch, rdat, ep->batchlen = rlen);
- break;
-
- case HYMOD_EEREC_TYPE: /* board type */
- if (rlen == 1)
- ep->bdtype = *rdat;
- break;
-
- case HYMOD_EEREC_REV: /* board revision */
- if (rlen == 1)
- ep->bdrev = *rdat;
- break;
-
- case HYMOD_EEREC_SDRAM: /* sdram size(s) */
- if (rlen > 0 && rlen <= HYMOD_MAX_SDRAM) {
- int i;
-
- for (i = 0; i < rlen; i++)
- ep->sdramsz[i] = rdat[i];
- ep->nsdram = rlen;
- }
- break;
-
- case HYMOD_EEREC_FLASH: /* flash size(s) */
- if (rlen > 0 && rlen <= HYMOD_MAX_FLASH) {
- int i;
-
- for (i = 0; i < rlen; i++)
- ep->flashsz[i] = rdat[i];
- ep->nflash = rlen;
- }
- break;
-
- case HYMOD_EEREC_ZBT: /* zbt ram size(s) */
- if (rlen > 0 && rlen <= HYMOD_MAX_ZBT) {
- int i;
-
- for (i = 0; i < rlen; i++)
- ep->zbtsz[i] = rdat[i];
- ep->nzbt = rlen;
- }
- break;
-
- case HYMOD_EEREC_XLXTYP: /* xilinx fpga type(s) */
- if (rlen > 0 && rlen <= HYMOD_MAX_XLX) {
- int i;
-
- for (i = 0; i < rlen; i++)
- ep->xlx[i].type = rdat[i];
- ep->nxlx = rlen;
- }
- break;
-
- case HYMOD_EEREC_XLXSPD: /* xilinx fpga speed(s) */
- if (rlen > 0 && rlen <= HYMOD_MAX_XLX) {
- int i;
-
- for (i = 0; i < rlen; i++)
- ep->xlx[i].speed = rdat[i];
- }
- break;
-
- case HYMOD_EEREC_XLXTMP: /* xilinx fpga temperature(s) */
- if (rlen > 0 && rlen <= HYMOD_MAX_XLX) {
- int i;
-
- for (i = 0; i < rlen; i++)
- ep->xlx[i].temp = rdat[i];
- }
- break;
-
- case HYMOD_EEREC_XLXGRD: /* xilinx fpga grade(s) */
- if (rlen > 0 && rlen <= HYMOD_MAX_XLX) {
- int i;
-
- for (i = 0; i < rlen; i++)
- ep->xlx[i].grade = rdat[i];
- }
- break;
-
- case HYMOD_EEREC_CPUTYP: /* CPU type */
- if (rlen == 1)
- ep->mpc.type = *rdat;
- break;
-
- case HYMOD_EEREC_CPUSPD: /* CPU speed */
- if (rlen == 1)
- ep->mpc.cpuspd = *rdat;
- break;
-
- case HYMOD_EEREC_CPMSPD: /* CPM speed */
- if (rlen == 1)
- ep->mpc.cpmspd = *rdat;
- break;
-
- case HYMOD_EEREC_BUSSPD: /* bus speed */
- if (rlen == 1)
- ep->mpc.busspd = *rdat;
- break;
-
- case HYMOD_EEREC_HSTYPE: /* hs-serial chip type */
- if (rlen == 1)
- ep->hss.type = *rdat;
- break;
-
- case HYMOD_EEREC_HSCHIN: /* num hs-serial input chans */
- if (rlen == 1)
- ep->hss.nchin = *rdat;
- break;
-
- case HYMOD_EEREC_HSCHOUT: /* num hs-serial output chans */
- if (rlen == 1)
- ep->hss.nchout = *rdat;
- break;
-
- default: /* ignore */
- break;
- }
- }
-
- return (1);
-}
-
-/* maps an ascii "name=value" into a binary eeprom data record */
-typedef
- struct _eerec_map {
- char *name;
- uint type;
- uchar *(*handler) \
- (struct _eerec_map *, uchar *, uchar *, uchar *);
- uint length;
- uint maxlen;
- }
-eerec_map_t;
-
-static uchar *
-uint_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp)
-{
- char *eval;
- ulong lval;
-
- lval = simple_strtol ((char *)val, &eval, 10);
-
- if ((uchar *)eval == val || *eval != '\0') {
- printf ("%s rec (%s) is not a valid uint\n", rp->name, val);
- return (NULL);
- }
-
- if (dp + 2 + rp->length > edp) {
- printf ("can't fit %s rec into eeprom\n", rp->name);
- return (NULL);
- }
-
- *dp++ = rp->type;
- *dp++ = rp->length;
-
- switch (rp->length) {
-
- case 1:
- if (lval >= 256) {
- printf ("%s rec value (%lu) out of range (0-255)\n",
- rp->name, lval);
- return (NULL);
- }
- *dp++ = lval;
- break;
-
- case 2:
- if (lval >= 65536) {
- printf ("%s rec value (%lu) out of range (0-65535)\n",
- rp->name, lval);
- return (NULL);
- }
- *dp++ = lval >> 8;
- *dp++ = lval;
- break;
-
- case 4:
- *dp++ = lval >> 24;
- *dp++ = lval >> 16;
- *dp++ = lval >> 8;
- *dp++ = lval;
- break;
-
- default:
- printf ("huh? rp->length not 1, 2 or 4! (%d)\n", rp->length);
- return (NULL);
- }
-
- return (dp);
-}
-
-static uchar *
-date_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp)
-{
- hymod_date_t date;
- char *p = (char *)val;
- char *ep;
- ulong lval;
-
- lval = simple_strtol (p, &ep, 10);
- if (ep == p || *ep++ != '-') {
-bad_date:
- printf ("%s rec (%s) is not a valid date\n", rp->name, val);
- return (NULL);
- }
- if (lval >= 65536)
- goto bad_date;
- date.year = lval;
-
- lval = simple_strtol (p = ep, &ep, 10);
- if (ep == p || *ep++ != '-' || lval == 0 || lval > 12)
- goto bad_date;
- date.month = lval;
-
- lval = simple_strtol (p = ep, &ep, 10);
- if (ep == p || *ep != '\0' || lval == 0 || lval > 31)
- goto bad_date;
- date.day = lval;
-
- if (dp + 2 + rp->length > edp) {
- printf ("can't fit %s rec into eeprom\n", rp->name);
- return (NULL);
- }
-
- *dp++ = rp->type;
- *dp++ = rp->length;
- *dp++ = date.year >> 8;
- *dp++ = date.year;
- *dp++ = date.month;
- *dp++ = date.day;
-
- return (dp);
-}
-
-static uchar *
-string_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp)
-{
- uint len;
-
- if ((len = strlen ((char *)val)) > rp->maxlen) {
- printf ("%s rec (%s) string is too long (%d>%d)\n",
- rp->name, val, len, rp->maxlen);
- return (NULL);
- }
-
- if (dp + 2 + len > edp) {
- printf ("can't fit %s rec into eeprom\n", rp->name);
- return (NULL);
- }
-
- *dp++ = rp->type;
- *dp++ = len;
- memcpy (dp, val, len);
- dp += len;
-
- return (dp);
-}
-
-static uchar *
-bytes_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp)
-{
- uchar bytes[HYMOD_MAX_BYTES], nbytes, *p;
- char *ep;
-
- for (nbytes = 0, p = val; *p != '\0'; p = (uchar *)ep) {
- ulong lval;
-
- lval = simple_strtol ((char *)p, &ep, 10);
- if ((uchar *)ep == p || (*ep != '\0' && *ep != ',') || \
- lval >= 256) {
- printf ("%s rec (%s) byte array has invalid uint\n",
- rp->name, val);
- return (NULL);
- }
- if (nbytes >= HYMOD_MAX_BYTES) {
- printf ("%s rec (%s) byte array too long\n",
- rp->name, val);
- return (NULL);
- }
- bytes[nbytes++] = lval;
-
- if (*ep != '\0')
- ep++;
- }
-
- if (dp + 2 + nbytes > edp) {
- printf ("can't fit %s rec into eeprom\n", rp->name);
- return (NULL);
- }
-
- *dp++ = rp->type;
- *dp++ = nbytes;
- memcpy (dp, bytes, nbytes);
- dp += nbytes;
-
- return (dp);
-}
-
-static eerec_map_t eerec_map[] = {
- /* name type handler len max */
- { "serno", HYMOD_EEREC_SERNO, uint_handler, 4, 0 },
- { "date", HYMOD_EEREC_DATE, date_handler, 4, 0 },
- { "batch", HYMOD_EEREC_BATCH, string_handler, 0, HYMOD_MAX_BATCH },
- { "type", HYMOD_EEREC_TYPE, uint_handler, 1, 0 },
- { "rev", HYMOD_EEREC_REV, uint_handler, 1, 0 },
- { "sdram", HYMOD_EEREC_SDRAM, bytes_handler, 0, HYMOD_MAX_SDRAM },
- { "flash", HYMOD_EEREC_FLASH, bytes_handler, 0, HYMOD_MAX_FLASH },
- { "zbt", HYMOD_EEREC_ZBT, bytes_handler, 0, HYMOD_MAX_ZBT },
- { "xlxtyp", HYMOD_EEREC_XLXTYP, bytes_handler, 0, HYMOD_MAX_XLX },
- { "xlxspd", HYMOD_EEREC_XLXSPD, bytes_handler, 0, HYMOD_MAX_XLX },
- { "xlxtmp", HYMOD_EEREC_XLXTMP, bytes_handler, 0, HYMOD_MAX_XLX },
- { "xlxgrd", HYMOD_EEREC_XLXGRD, bytes_handler, 0, HYMOD_MAX_XLX },
- { "cputyp", HYMOD_EEREC_CPUTYP, uint_handler, 1, 0 },
- { "cpuspd", HYMOD_EEREC_CPUSPD, uint_handler, 1, 0 },
- { "cpmspd", HYMOD_EEREC_CPMSPD, uint_handler, 1, 0 },
- { "busspd", HYMOD_EEREC_BUSSPD, uint_handler, 1, 0 },
- { "hstype", HYMOD_EEREC_HSTYPE, uint_handler, 1, 0 },
- { "hschin", HYMOD_EEREC_HSCHIN, uint_handler, 1, 0 },
- { "hschout", HYMOD_EEREC_HSCHOUT, uint_handler, 1, 0 },
-};
-
-static int neerecs = sizeof eerec_map / sizeof eerec_map[0];
-
-static uchar data[HYMOD_EEPROM_SIZE], *sdp, *dp, *edp;
-
-static int
-eerec_callback (uchar *name, uchar *val)
-{
- eerec_map_t *rp;
-
- for (rp = eerec_map; rp < &eerec_map[neerecs]; rp++)
- if (strcmp ((char *)name, rp->name) == 0)
- break;
-
- if (rp >= &eerec_map[neerecs])
- return (0);
-
- if ((dp = (*rp->handler) (rp, val, dp, edp)) == NULL)
- return (0);
-
- return (1);
-}
-
-static int
-hymod_eeprom_fetch(int which, char *filename, ulong addr)
-{
- unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \
- (which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN);
- hymod_eehdr_t *hp = (hymod_eehdr_t *)&data[0];
- ulong crc;
-
- memset (hp, 0, sizeof *hp);
- hp->id = HYMOD_EEPROM_ID;
- hp->ver = HYMOD_EEPROM_VER;
-
- dp = sdp = (uchar *)(hp + 1);
- edp = dp + HYMOD_EEPROM_MAXLEN;
-
- if (fetch_and_parse (filename, addr, eerec_callback) == 0)
- return (0);
-
- hp->len = dp - sdp;
-
- crc = crc32 (0, data, dp - data);
- memcpy (dp, &crc, sizeof (ulong));
- dp += sizeof (ulong);
-
- eeprom_write (dev_addr, 0, data, dp - data);
-
- return (1);
-}
-
-static char *type_vals[] = {
- "NONE", "IO", "CLP", "DSP", "INPUT", "ALT-INPUT", "DISPLAY"
-};
-
-static char *xlxtyp_vals[] = {
- "NONE", "XCV300E", "XCV400E", "XCV600E"
-};
-
-static char *xlxspd_vals[] = {
- "NONE", "6", "7", "8"
-};
-
-static char *xlxtmp_vals[] = {
- "NONE", "COM", "IND"
-};
-
-static char *xlxgrd_vals[] = {
- "NONE", "NORMAL", "ENGSAMP"
-};
-
-static char *cputyp_vals[] = {
- "NONE", "MPC8260"
-};
-
-static char *clk_vals[] = {
- "NONE", "33", "66", "100", "133", "166", "200"
-};
-
-static char *hstype_vals[] = {
- "NONE", "AMCC-S2064A"
-};
-
-static void
-print_mem (char *l, char *s, uchar n, uchar a[])
-{
- if (n > 0) {
- if (n == 1)
- printf ("%s%dMB %s", s, 1 << (a[0] - 20), l);
- else {
- ulong t = 0;
- int i;
-
- for (i = 0; i < n; i++)
- t += 1 << (a[i] - 20);
-
- printf ("%s%luMB %s (%d banks:", s, t, l, n);
-
- for (i = 0; i < n; i++)
- printf ("%dMB%s",
- 1 << (a[i] - 20),
- (i == n - 1) ? ")" : ",");
- }
- }
- else
- printf ("%sNO %s", s, l);
-}
-
-void
-hymod_eeprom_print (hymod_eeprom_t *ep)
-{
- int i;
-
- printf (" Hymod %s board, rev %03d\n",
- type_vals[ep->bdtype], ep->bdrev);
-
- printf (" serial #: %010lu, date %04d-%02d-%02d",
- ep->serno, ep->date.year, ep->date.month, ep->date.day);
- if (ep->batchlen > 0)
- printf (", batch \"%.*s\"", ep->batchlen, ep->batch);
- puts ("\n");
-
- switch (ep->bdtype) {
-
- case HYMOD_BDTYPE_IO:
- case HYMOD_BDTYPE_CLP:
- case HYMOD_BDTYPE_DSP:
- printf (" Motorola %s CPU, speeds: %s/%s/%s",
- cputyp_vals[ep->mpc.type], clk_vals[ep->mpc.cpuspd],
- clk_vals[ep->mpc.cpmspd], clk_vals[ep->mpc.busspd]);
-
- print_mem ("SDRAM", ", ", ep->nsdram, ep->sdramsz);
-
- print_mem ("FLASH", ", ", ep->nflash, ep->flashsz);
-
- puts ("\n");
-
- print_mem ("ZBT", " ", ep->nzbt, ep->zbtsz);
-
- if (ep->nxlx > 0) {
- hymod_xlx_t *xp;
-
- if (ep->nxlx == 1) {
- xp = &ep->xlx[0];
- printf (", Xilinx %s FPGA (%s/%s/%s)",
- xlxtyp_vals[xp->type],
- xlxspd_vals[xp->speed],
- xlxtmp_vals[xp->temp],
- xlxgrd_vals[xp->grade]);
- }
- else {
- printf (", %d Xilinx FPGAs (", ep->nxlx);
- for (i = 0; i < ep->nxlx; i++) {
- xp = &ep->xlx[i];
- printf ("%s[%s/%s/%s]%s",
- xlxtyp_vals[xp->type],
- xlxspd_vals[xp->speed],
- xlxtmp_vals[xp->temp],
- xlxgrd_vals[xp->grade],
- (i == ep->nxlx - 1) ? ")" : ", ");
- }
- }
- }
- else
- puts(", NO FPGAs");
-
- puts ("\n");
-
- if (ep->hss.type > 0)
- printf (" High Speed Serial: "
- "%s, %d input%s, %d output%s\n",
- hstype_vals[ep->hss.type],
- ep->hss.nchin,
- (ep->hss.nchin == 1 ? "" : "s"),
- ep->hss.nchout,
- (ep->hss.nchout == 1 ? "" : "s"));
- break;
-
- case HYMOD_BDTYPE_INPUT:
- case HYMOD_BDTYPE_ALTINPUT:
- case HYMOD_BDTYPE_DISPLAY:
- break;
-
- default:
- /* crap! */
- printf (" UNKNOWN BOARD TYPE: %d\n", ep->bdtype);
- break;
- }
-}
-
-int
-hymod_eeprom_read (int which, hymod_eeprom_t *ep)
-{
- char *label = which ? "mezzanine" : "main";
- unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \
- (which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN);
- char filename[50], prompt[50], *dir;
- int serno, count = 0, rc;
-
- rc = eeprom_probe (dev_addr, 0);
-
- if (rc > 0) {
- printf ("*** probe for eeprom failed with code %d\n", rc);
- return (0);
- }
-
- if (rc < 0)
- return (rc);
-
- sprintf (prompt, "Enter %s board serial number: ", label);
-
- if ((dir = getenv ("bddb_cfgdir")) == NULL)
- dir = def_bddb_cfgdir;
-
- for (;;) {
- int rc;
-
- if (hymod_eeprom_load (which, ep))
- return (1);
-
- printf ("*** %s board EEPROM contents are %sinvalid\n",
- label, count == 0 ? "" : "STILL ");
-
- puts ("*** will fetch from server (Ctrl-C to abort)\n");
-
- serno = hymod_get_serno (prompt);
-
- if (serno < 0) {
- if (serno == -1)
- puts ("\n*** interrupted!");
- else
- puts ("\n*** timeout!");
- puts (" - ignoring eeprom contents\n");
- return (0);
- }
-
- sprintf (filename, "%s/%010d.cfg", dir, serno);
-
- printf ("*** fetching %s board EEPROM contents from server\n",
- label);
-
- rc = hymod_eeprom_fetch (which, filename, CONFIG_SYS_LOAD_ADDR);
-
- if (rc == 0) {
- puts ("*** fetch failed - ignoring eeprom contents\n");
- return (0);
- }
-
- count++;
- }
-}
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/ctype.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* imports from fetch.c */
-extern int fetch_and_parse (char *, ulong, int (*)(uchar *, uchar *));
-
-/* this is relative to the root of the server's tftp directory */
-static char *def_global_env_path = "/hymod/global_env";
-
-static int
-env_callback (uchar *name, uchar *value)
-{
- hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
- char ov[CONFIG_SYS_CBSIZE], nv[CONFIG_SYS_CBSIZE], *p, *q, *nn, c, *curver, *newver;
- int override = 1, append = 0, remove = 0, nnl, ovl, nvl;
-
- nn = (char *)name;
-
- if (*nn == '-') {
- override = 0;
- nn++;
- }
-
- while (isblank(*nn))
- nn++;
-
- if ((nnl = strlen (nn)) == 0) {
- printf ("Empty name in global env file\n");
- return (0);
- }
-
- if ((c = nn[nnl - 1]) == '+' || c == '-') {
- if (c == '+')
- append = 1;
- else
- remove = 1;
- nn[--nnl] = '\0';
- }
-
- while (nnl > 0 && isblank(nn[nnl - 1]))
- nn[--nnl] = '\0';
- if (nnl == 0) {
- printf ("Empty name in global env file\n");
- return (0);
- }
-
- p = (char *)value;
- q = nv;
-
- while (isblank(*p))
- p++;
-
- nvl = strlen (p);
- while (nvl > 0 && isblank(p[nvl - 1]))
- p[--nvl] = '\0';
-
- while ((*q = *p++) != '\0') {
- if (*q == '%') {
- switch (*p++) {
-
- case '\0': /* whoops - back up */
- p--;
- break;
-
- case '%': /* a single percent character */
- q++;
- break;
-
- case 's': /* main board serial number as string */
- q += sprintf (q, "%010lu",
- cp->main.eeprom.serno);
- break;
-
- case 'S': /* main board serial number as number */
- q += sprintf (q, "%lu", cp->main.eeprom.serno);
- break;
-
- default: /* ignore any others */
- break;
- }
- }
- else
- q++;
- }
-
- if ((nvl = q - nv) == 0) {
- setenv (nn, NULL);
- return (1);
- }
-
- if ((curver = getenv ("global_env_version")) == NULL)
- curver = "unknown";
-
- if ((newver = getenv ("new_genv_version")) == NULL || \
- strcmp (curver, newver) == 0) {
- if (strcmp (nn, "version") == 0)
- setenv ("new_genv_version", nv);
- return (1);
- }
-
- if ((p = getenv (nn)) != NULL) {
-
- strcpy (ov, p);
- ovl = strlen (ov);
-
- if (append) {
-
- if (strstr (ov, nv) == NULL) {
-
- printf ("Appending '%s' to env var '%s'\n",
- nv, nn);
-
- while (nvl >= 0) {
- nv[ovl + 1 + nvl] = nv[nvl];
- nvl--;
- }
-
- nv[ovl] = ' ';
-
- while (--ovl >= 0)
- nv[ovl] = ov[ovl];
-
- setenv (nn, nv);
- }
-
- return (1);
- }
-
- if (remove) {
-
- if (strstr (ov, nv) != NULL) {
-
- printf ("Removing '%s' from env var '%s'\n",
- nv, nn);
-
- while ((p = strstr (ov, nv)) != NULL) {
- q = p + nvl;
- if (*q == ' ')
- q++;
- strcpy(p, q);
- }
-
- setenv (nn, ov);
- }
-
- return (1);
- }
-
- if (!override || strcmp (ov, nv) == 0)
- return (1);
-
- printf ("Re-setting env cmd '%s' from '%s' to '%s'\n",
- nn, ov, nv);
- }
- else
- printf ("Setting env cmd '%s' to '%s'\n", nn, nv);
-
- setenv (nn, nv);
- return (1);
-}
-
-void
-hymod_check_env (void)
-{
- char *p, *path, *curver, *newver;
- int firsttime = 0, needsave = 0;
-
- if (getenv ("global_env_loaded") == NULL) {
- puts ("*** global environment has never been loaded\n");
- puts ("*** fetching from server");
- firsttime = 1;
- }
- else if ((p = getenv ("always_check_env")) != NULL &&
- strcmp (p, "yes") == 0)
- puts ("*** checking for updated global environment");
- else
- return;
-
- puts (" (Control-C to Abort)\n");
-
- if ((path = getenv ("global_env_path")) == NULL || *path == '\0')
- path = def_global_env_path;
-
- if (fetch_and_parse (path, CONFIG_SYS_LOAD_ADDR, env_callback) == 0) {
- puts ("*** Fetch of global environment failed!\n");
- return;
- }
-
- if ((newver = getenv ("new_genv_version")) == NULL) {
- puts ("*** Version number not set - contents ignored!\n");
- return;
- }
-
- if ((curver = getenv ("global_env_version")) == NULL || \
- strcmp (curver, newver) != 0) {
- setenv ("global_env_version", newver);
- needsave = 1;
- }
- else
- printf ("*** Global environment up-to-date (ver %s)\n", curver);
-
- setenv ("new_genv_version", NULL);
-
- if (firsttime) {
- setenv ("global_env_loaded", "yes");
- needsave = 1;
- }
-
- if (needsave)
- puts ("\n*** Remember to run the 'saveenv' "
- "command to save the changes\n\n");
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <net.h>
-
-/* imports from input.c */
-extern int hymod_get_ethaddr (void);
-
-int
-fetch_and_parse (char *fn, ulong addr, int (*cback)(uchar *, uchar *))
-{
- char *ethaddr;
- uchar *fp, *efp;
- int rc, count = 0;
-
- while ((ethaddr = getenv ("ethaddr")) == NULL || *ethaddr == '\0') {
-
- printf ("*** Ethernet address is%s not set\n",
- count == 0 ? "" : " STILL");
-
- if ((rc = hymod_get_ethaddr ()) < 0) {
- if (rc == -1)
- puts ("\n*** interrupted!");
- else
- puts ("\n*** timeout!");
- printf (" - fetch of '%s' aborted\n", fn);
- return (0);
- }
-
- count++;
- }
-
- copy_filename (BootFile, fn, sizeof (BootFile));
- load_addr = addr;
- NetBootFileXferSize = 0;
-
- if (NetLoop(TFTPGET) == 0) {
- printf ("tftp transfer of file '%s' failed\n", fn);
- return (0);
- }
-
- if (NetBootFileXferSize == 0) {
- printf ("can't determine size of file '%s'\n", fn);
- return (0);
- }
-
- fp = (uchar *)load_addr;
- efp = fp + NetBootFileXferSize;
-
- do {
- uchar *name, *value;
-
- if (*fp == '#' || *fp == '\n') {
- /* skip this line */
- while (fp < efp && *fp++ != '\n')
- ;
- continue;
- }
-
- name = fp;
-
- while (fp < efp && *fp != '=' && *fp != '\n')
- fp++;
- if (fp >= efp)
- break;
- if (*fp == '\n') {
- fp++;
- continue;
- }
- *fp++ = '\0';
-
- value = fp;
-
- while (fp < efp && *fp != '\n')
- fp++;
- if (fp[-1] == '\r')
- fp[-1] = '\0';
- *fp++ = '\0'; /* ok if we go off the end here */
-
- if ((*cback)(name, value) == 0)
- return (0);
-
- } while (fp < efp);
-
- return (1);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Hacked for the Hymod board by Murray.Jensen@csiro.au, 20-Oct-00
- */
-
-#include <common.h>
-#include <mpc8260.h>
-#include <board/hymod/flash.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Protection Flags:
- */
-#define FLAG_PROTECT_SET 0x01
-#define FLAG_PROTECT_CLEAR 0x02
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * probe for flash bank at address "base" and store info about it
- * in the flash_info entry "fip". Fatal error if nothing there.
- */
-static void
-bank_probe (flash_info_t *fip, volatile bank_addr_t base)
-{
- volatile bank_addr_t addr;
- bank_word_t word;
- int i;
-
- /* reset the flash */
- *base = BANK_CMD_RST;
-
- /* put flash into read id mode */
- *base = BANK_CMD_RD_ID;
-
- /* check the manufacturer id - must be intel */
- word = *BANK_REG_MAN_CODE (base);
- if (word != BANK_FILL_WORD (INTEL_MANUFACT&0xff))
- panic ("\nbad manufacturer's code (0x%08lx) at addr 0x%08lx",
- (unsigned long)word, (unsigned long)base);
-
- /* check the device id */
- word = *BANK_REG_DEV_CODE (base);
- switch (word) {
-
- case BANK_FILL_WORD (INTEL_ID_28F320J5&0xff):
- fip->flash_id = FLASH_MAN_INTEL | FLASH_28F320J5;
- fip->sector_count = 32;
- break;
-
- case BANK_FILL_WORD (INTEL_ID_28F640J5&0xff):
- fip->flash_id = FLASH_MAN_INTEL | FLASH_28F640J5;
- fip->sector_count = 64;
- break;
-
- case BANK_FILL_WORD (INTEL_ID_28F320J3A&0xff):
- fip->flash_id = FLASH_MAN_INTEL | FLASH_28F320J3A;
- fip->sector_count = 32;
- break;
-
- case BANK_FILL_WORD (INTEL_ID_28F640J3A&0xff):
- fip->flash_id = FLASH_MAN_INTEL | FLASH_28F640J3A;
- fip->sector_count = 64;
- break;
-
- case BANK_FILL_WORD (INTEL_ID_28F128J3A&0xff):
- fip->flash_id = FLASH_MAN_INTEL | FLASH_28F128J3A;
- fip->sector_count = 128;
- break;
-
- default:
- panic ("\nbad device code (0x%08lx) at addr 0x%08lx",
- (unsigned long)word, (unsigned long)base);
- }
-
- if (fip->sector_count >= CONFIG_SYS_MAX_FLASH_SECT)
- panic ("\ntoo many sectors (%d) in flash at address 0x%08lx",
- fip->sector_count, (unsigned long)base);
-
- addr = base;
- for (i = 0; i < fip->sector_count; i++) {
- fip->start[i] = (unsigned long)addr;
- fip->protect[i] = 0;
- addr = BANK_ADDR_NEXT_BLK (addr);
- }
-
- fip->size = (bank_size_t)addr - (bank_size_t)base;
-
- /* reset the flash */
- *base = BANK_CMD_RST;
-}
-
-static void
-bank_reset (flash_info_t *info, int sect)
-{
- volatile bank_addr_t addr = (bank_addr_t)info->start[sect];
-
-#ifdef FLASH_DEBUG
- printf ("writing reset cmd to addr 0x%08lx\n", (unsigned long)addr);
-#endif
-
- *addr = BANK_CMD_RST;
-}
-
-static void
-bank_erase_init (flash_info_t *info, int sect)
-{
- volatile bank_addr_t addr = (bank_addr_t)info->start[sect];
- int flag;
-
-#ifdef FLASH_DEBUG
- printf ("erasing sector %d, addr = 0x%08lx\n",
- sect, (unsigned long)addr);
-#endif
-
- /* Disable intrs which might cause a timeout here */
- flag = disable_interrupts ();
-
-#ifdef FLASH_DEBUG
- printf ("writing erase cmd to addr 0x%08lx\n", (unsigned long)addr);
-#endif
- *addr = BANK_CMD_ERASE1;
- *addr = BANK_CMD_ERASE2;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-}
-
-static int
-bank_erase_poll (flash_info_t *info, int sect)
-{
- volatile bank_addr_t addr = (bank_addr_t)info->start[sect];
- bank_word_t stat = *addr;
-
-#ifdef FLASH_DEBUG
- printf ("checking status at addr 0x%08lx [0x%08lx]\n",
- (unsigned long)addr, (unsigned long)stat);
-#endif
-
- if ((stat & BANK_STAT_RDY) == BANK_STAT_RDY) {
- if ((stat & BANK_STAT_ERR) != 0) {
- printf ("failed on sector %d [0x%08lx] at "
- "address 0x%08lx\n", sect,
- (unsigned long)stat, (unsigned long)addr);
- *addr = BANK_CMD_CLR_STAT;
- return (-1);
- }
- else
- return (1);
- }
- else
- return (0);
-}
-
-static int
-bank_write_word (volatile bank_addr_t addr, bank_word_t value)
-{
- bank_word_t stat;
- ulong start;
- int flag, retval;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- *addr = BANK_CMD_PROG;
-
- *addr = value;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- retval = 0;
-
- /* data polling for D7 */
- start = get_timer (0);
- do {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- retval = 1;
- goto done;
- }
- stat = *addr;
- } while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY);
-
- if ((stat & BANK_STAT_ERR) != 0) {
- printf ("flash program failed [0x%08lx] at address 0x%08lx\n",
- (unsigned long)stat, (unsigned long)addr);
- *addr = BANK_CMD_CLR_STAT;
- retval = 3;
- }
-
-done:
- /* reset to read mode */
- *addr = BANK_CMD_RST;
-
- return (retval);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long
-flash_init (void)
-{
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- bank_probe (&flash_info[0], (bank_addr_t)CONFIG_SYS_FLASH_BASE);
-
- /*
- * protect monitor and environment sectors
- */
-
-#if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
- (void)flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#if defined(CONFIG_SYS_FLASH_ENV_ADDR)
- (void)flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_ENV_ADDR,
-#if defined(CONFIG_SYS_FLASH_ENV_BUF)
- CONFIG_SYS_FLASH_ENV_ADDR + CONFIG_SYS_FLASH_ENV_BUF - 1,
-#else
- CONFIG_SYS_FLASH_ENV_ADDR + CONFIG_SYS_FLASH_ENV_SIZE - 1,
-#endif
- &flash_info[0]);
-#endif
-
- return flash_info[0].size;
-}
-
-/*-----------------------------------------------------------------------
- */
-void
-flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL: printf ("INTEL "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F320J5: printf ("28F320J5 (32 Mbit, 2 x 16bit)\n");
- break;
- case FLASH_28F640J5: printf ("28F640J5 (64 Mbit, 2 x 16bit)\n");
- break;
- case FLASH_28F320J3A: printf ("28F320J3A (32 Mbit, 2 x 16bit)\n");
- break;
- case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 2 x 16bit)\n");
- break;
- case FLASH_28F128J3A: printf ("28F320J3A (128 Mbit, 2 x 16bit)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-/*-----------------------------------------------------------------------
- */
-
-int
-flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int prot, sect, haderr;
- ulong start, now, last;
- int rcode = 0;
-
-#ifdef FLASH_DEBUG
- printf ("\nflash_erase: erase %d sectors (%d to %d incl.) from\n"
- " Bank # %d: ", s_last - s_first + 1, s_first, s_last,
- (info - flash_info) + 1);
- flash_print_info (info);
-#endif
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sector%s will not be erased\n",
- prot, (prot > 1 ? "s" : ""));
- }
-
- start = get_timer (0);
- last = 0;
- haderr = 0;
-
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- ulong estart;
- int sectdone;
-
- bank_erase_init (info, sect);
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- estart = get_timer (start);
-
- do {
- now = get_timer (start);
-
- if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout (sect %d)\n", sect);
- haderr = 1;
- rcode = 1;
- break;
- }
-
-#ifndef FLASH_DEBUG
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
-#endif
-
- sectdone = bank_erase_poll (info, sect);
-
- if (sectdone < 0) {
- haderr = 1;
- rcode = 1;
- break;
- }
-
- } while (!sectdone);
-
- if (haderr)
- break;
- }
- }
-
- if (haderr > 0)
- printf (" failed\n");
- else
- printf (" done\n");
-
- /* reset to read mode */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- bank_reset (info, sect);
- }
- }
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 3 - Program failed
- */
-static int
-write_word (flash_info_t *info, ulong dest, ulong data)
-{
- /* Check if Flash is (sufficiently) erased */
- if ((*(ulong *)dest & data) != data)
- return (2);
-
- return (bank_write_word ((bank_addr_t)dest, (bank_word_t)data));
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 3 - Program failed
- */
-
-int
-write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word (info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*************** DEFINES for Intel StrataFlash FLASH chip ********************/
-
-/* Commands */
-#define ISF_CMD_RST 0xFF /* reset flash */
-#define ISF_CMD_RD_ID 0x90 /* read the id and lock bits */
-#define ISF_CMD_RD_QUERY 0x98 /* read device capabilities */
-#define ISF_CMD_RD_STAT 0x70 /* read the status register */
-#define ISF_CMD_CLR_STAT 0x50 /* clear the staus register */
-#define ISF_CMD_WR_BUF 0xE8 /* clear the staus register */
-#define ISF_CMD_PROG 0x40 /* program word command */
-#define ISF_CMD_ERASE1 0x20 /* 1st word for block erase */
-#define ISF_CMD_ERASE2 0xD0 /* 2nd word for block erase */
-#define ISF_CMD_ERASE_SUSP 0xB0 /* suspend block erase */
-#define ISF_CMD_LOCK 0x60 /* 1st word for all lock cmds */
-#define ISF_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */
-#define ISF_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */
-#define ISF_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */
-
-/* status register bits */
-#define ISF_STAT_DPS 0x02 /* Device Protect Status */
-#define ISF_STAT_VPPS 0x08 /* VPP Status */
-#define ISF_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */
-#define ISF_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */
-#define ISF_STAT_ESS 0x40 /* Erase Suspend Status */
-#define ISF_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */
-
-#define ISF_STAT_ERR (ISF_STAT_VPPS | ISF_STAT_DPS | \
- ISF_STAT_ECLBS | ISF_STAT_PSLBS)
-
-/* register addresses, valid only following an ISF_CMD_RD_ID command */
-#define ISF_REG_MAN_CODE 0x00 /* manufacturer code */
-#define ISF_REG_DEV_CODE 0x01 /* device code */
-#define ISF_REG_BLK_LCK 0x02 /* block lock configuration */
-#define ISF_REG_MST_LCK 0x03 /* master lock configuration */
-
-/********************** DEFINES for Hymod Flash ******************************/
-
-/*
- * this code requires that the flash on any Hymod board appear as a bank
- * of two (identical) 16bit Intel StrataFlash chips with 64Kword erase
- * sectors (or blocks), running in x16 bit mode and connected side-by-side
- * to make a 32-bit wide bus.
- */
-
-typedef unsigned long bank_word_t;
-typedef bank_word_t bank_blk_t[64 * 1024];
-
-#define BANK_FILL_WORD(b) (((bank_word_t)(b) << 16) | (bank_word_t)(b))
-
-#ifdef EXAMPLE
-
-/* theoretically the following examples should also work */
-
-/* one flash chip in x8 mode with 128Kword sectors and 8bit bus */
-typedef unsigned char bank_word_t;
-typedef bank_word_t bank_blk_t[128 * 1024];
-#define BANK_FILL_WORD(b) ((bank_word_t)(b))
-
-/* four flash chips in x16 mode with 32Kword sectors and 64bit bus */
-typedef unsigned long long bank_word_t;
-typedef bank_word_t bank_blk_t[32 * 1024];
-#define BANK_FILL_WORD(b) ( \
- ((bank_word_t)(b) << 48) \
- ((bank_word_t)(b) << 32) \
- ((bank_word_t)(b) << 16) \
- ((bank_word_t)(b) << 0) \
- )
-
-#endif /* EXAMPLE */
-
-/* the sizes of these two types should probably be the same */
-typedef bank_word_t *bank_addr_t;
-typedef unsigned long bank_size_t;
-
-/* align bank addresses and sizes to bank word boundaries */
-#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
- & ~(sizeof (bank_word_t) - 1)))
-#define BANK_SIZE_WORD_ALIGN(s) (((bank_size_t)(s) + sizeof (bank_word_t) - 1) \
- & ~(sizeof (bank_word_t) - 1))
-
-/* align bank addresses and sizes to bank block boundaries */
-#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
- & ~(sizeof (bank_blk_t) - 1)))
-#define BANK_SIZE_BLK_ALIGN(s) (((bank_size_t)(s) + sizeof (bank_blk_t) - 1) \
- & ~(sizeof (bank_blk_t) - 1))
-
-/* add an offset to a bank address */
-#define BANK_ADDR_OFFSET(a, o) ((bank_addr_t)((bank_size_t)(a) + \
- (bank_size_t)(o)))
-
-/* adjust a bank address to start of next word, block or bank */
-#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
- sizeof (bank_word_t))
-#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
- sizeof (bank_blk_t))
-
-/* get bank address of register r given a bank base address a and block num b */
-#define BANK_ADDR_REG(a, b, r) BANK_ADDR_OFFSET(BANK_ADDR_OFFSET((a), \
- (bank_size_t)(b) * sizeof (bank_blk_t)), \
- (bank_size_t)(r) * sizeof (bank_word_t))
-
-/* make a bank word value for each StrataFlash value */
-
-/* Commands */
-#define BANK_CMD_RST BANK_FILL_WORD(ISF_CMD_RST)
-#define BANK_CMD_RD_ID BANK_FILL_WORD(ISF_CMD_RD_ID)
-#define BANK_CMD_RD_STAT BANK_FILL_WORD(ISF_CMD_RD_STAT)
-#define BANK_CMD_CLR_STAT BANK_FILL_WORD(ISF_CMD_CLR_STAT)
-#define BANK_CMD_ERASE1 BANK_FILL_WORD(ISF_CMD_ERASE1)
-#define BANK_CMD_ERASE2 BANK_FILL_WORD(ISF_CMD_ERASE2)
-#define BANK_CMD_PROG BANK_FILL_WORD(ISF_CMD_PROG)
-#define BANK_CMD_LOCK BANK_FILL_WORD(ISF_CMD_LOCK)
-#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(ISF_CMD_SET_LOCK_BLK)
-#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(ISF_CMD_SET_LOCK_MSTR)
-#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(ISF_CMD_CLR_LOCK_BLK)
-
-/* status register bits */
-#define BANK_STAT_DPS BANK_FILL_WORD(ISF_STAT_DPS)
-#define BANK_STAT_PSS BANK_FILL_WORD(ISF_STAT_PSS)
-#define BANK_STAT_VPPS BANK_FILL_WORD(ISF_STAT_VPPS)
-#define BANK_STAT_PSLBS BANK_FILL_WORD(ISF_STAT_PSLBS)
-#define BANK_STAT_ECLBS BANK_FILL_WORD(ISF_STAT_ECLBS)
-#define BANK_STAT_ESS BANK_FILL_WORD(ISF_STAT_ESS)
-#define BANK_STAT_RDY BANK_FILL_WORD(ISF_STAT_RDY)
-
-#define BANK_STAT_ERR BANK_FILL_WORD(ISF_STAT_ERR)
-
-/* make a bank register address for each StrataFlash register address */
-
-#define BANK_REG_MAN_CODE(a) BANK_ADDR_REG((a), 0, ISF_REG_MAN_CODE)
-#define BANK_REG_DEV_CODE(a) BANK_ADDR_REG((a), 0, ISF_REG_DEV_CODE)
-#define BANK_REG_BLK_LCK(a, b) BANK_ADDR_REG((a), (b), ISF_REG_BLK_LCK)
-#define BANK_REG_MST_LCK(a) BANK_ADDR_REG((a), 0, ISF_REG_MST_LCK)
+++ /dev/null
-# DONT FORGET TO CHANGE THE "version" VAR BELOW IF YOU MAKE CHANGES TO THIS FILE
-
-# (C) Copyright 2001
-# Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
-#
-# SPDX-License-Identifier: GPL-2.0+
-
-#
-# global_env
-#
-# file used by Hymod boards to initialise the u-boot non-volatile
-# environment when u-boot is first run (it determines this by the
-# absence of the environment variable "global_env_loaded")
-#
-# format of this file is:
-#
-# 1. blank lines and lines beginning with '#' are ignored
-# 2. all other lines must have the form <name>=<value>
-# 3. if a percent appears anywhere, it is replaced like so:
-#
-# %s serial number of the main board (10 digit zero filled)
-# %S serial number of the main board (plain number)
-# %% a percentage character
-# ... otherwise the %x is discarded
-#
-# if first character in <name> is a dash ('-'), then an existing env var
-# will not be overwritten (the dash is removed). i.e. it is only set if
-# it does not exist
-#
-# if last character in <name> is a plus ('+'), then <value> will be appended
-# to any existing env var (the plus is ignored). Duplicates of <value> are
-# removed.
-#
-# similarly, if the last character in <name> is a minus ('-'), then any
-# occurences of <value> in the current value of <name> will removed (the
-# minus is ignored).
-#
-# leading and trailing whitespace is removed in both <name> and <value>
-# (after processing any initial or final plus/minus in <name>).
-#
-
-# MISCELLANEOUS PARAMETERS
-
-# version must always come first
-version=4
-
-# set the ip address based on the main board serial number
-ipaddr=192.168.1.%S
-serverip=192.168.1.254
-
-# stop auto execute after tftp (not a very good name really)
-autostart=no
-
-# setting this to "yes" forces the global_env file to be loaded and processed
-# if the current version is different to the version in the file
-always_check_env=no
-
-# BOOTING COMMANDS AND PARAMETERS
-
-# command to run when "auto-booting"
-bootcmd=bootm 40080000
-
-# how long the "countdown" to automatically running "bootcmd" is
-bootdelay=2
-
-# how long before it "times out" console input and attempts to run "bootcmd"
-bootretry=5
-
-# arguments passed to the boot program (i.e. linux kernel) via register 6
-# the linux kernel (v2.4) uses the following registers:
-# r3 - address of board information structure
-# r4 - address of initial ramdisk image (0 means no initrd)
-# r5 - size of initial ramdisk image
-# r6 - address of command line string
--bootargs=root=/dev/mtdblock5 rootfstype=squashfs ro
-
-# these four are for hymod linux integrated into our Sun network
-bootargs+=serialno=%S
-bootargs+=nisclient nisdomain=mlb.dmt.csiro.au nissrvadr=138.194.112.4
-bootargs+=nfsclient
-bootargs+=automount
-
-# start a web server by default
-bootargs+=webserver
-
-# give negotiation time to finish
-bootargs+=netsleep=5
-
-# then our ciscos don't pass packets for 25-30 secs after that, so
-# pinging the server until it responds prevents network connections
-# from failing...
-bootargs+=netping
-
-# these are old bootargs - we don't need them anymore
-bootargs-=preload=unix,i2c-cpm,i2c-dev
-bootargs-=ramdisk_size=32768
-bootargs-=ramdisk_size=24576
-
-# FLASH MANIPULATION COMMANDS
-
-#
-# 16M flash, 64 x 256K sectors, mapped at address 0x40000000
-#
-# Sector(s) Address Size Description
-#
-# 0 - 0 0x40000000 256K boot code
-# 1 - 1 0x40040000 256K non volatile environment
-# 2 - 4 0x40080000 768K linux kernel image
-# 5 - 7 0x40140000 768K alternate linux kernel image
-# 8 - 47 0x40200000 10M linux initial ramdisk image
-# 48 - 63 0x40c00000 4M ramdisk image for applications
-#
-
-fetchboot=tftp 100000 /hymod/u-boot.bin
-eraseboot=protect off 1:0 ; erase 1:0 ; protect on 1:0
-copyboot=protect off 1:0 ; cp.b 100000 40000000 40000 ; protect on 1:0
-cmpboot=cmp.b 100000 40000000 40000
-newboot=run fetchboot eraseboot copyboot cmpboot
-
-fetchlinux=tftp 100000 /hymod/linux.bin
-eraselinux=erase 1:2-4
-copylinux=cp.b 100000 40080000 ${filesize}
-cmplinux=cmp.b 100000 40080000 ${filesize}
-newlinux=run fetchlinux eraselinux copylinux cmplinux
-
-fetchaltlinux=tftp 100000 /hymod/altlinux.bin
-erasealtlinux=erase 1:5-7
-copyaltlinux=cp.b 100000 40140000 ${filesize}
-cmpaltlinux=cmp.b 100000 40140000 ${filesize}
-newaltlinux=run fetchaltlinux erasealtlinux copyaltlinux cmpaltlinux
-
-fetchroot=tftp 100000 /hymod/root.bin
-eraseroot=erase 1:8-47
-copyroot=cp.b 100000 40200000 ${filesize}
-cmproot=cmp.b 100000 40200000 ${filesize}
-newroot=run fetchroot eraseroot copyroot cmproot
-
-fetchard=tftp 100000 /hymod/apprd.bin
-eraseard=erase 1:48-63
-copyard=cp.b 100000 40c00000 ${filesize}
-cmpard=cmp.b 100000 40c00000 ${filesize}
-newapprd=run fetchard eraseard copyard cmpard
-
-# pass above map to linux mtd driver
-bootargs+=mtdparts=phys:256k(u-boot),256k(u-boot-env),768k(linux),768k(altlinux),10m(root),4m(hymod)
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Hacked for the Hymod board by Murray.Jensen@csiro.au, 20-Oct-00
- */
-
-#include <common.h>
-#include <bootretry.h>
-#include <cli.h>
-#include <mpc8260.h>
-#include <mpc8260_irq.h>
-#include <ioports.h>
-#include <i2c.h>
-#include <asm/iopin_8260.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-/* imports from eeprom.c */
-extern int hymod_eeprom_read (int, hymod_eeprom_t *);
-extern void hymod_eeprom_print (hymod_eeprom_t *);
-
-/* imports from env.c */
-extern void hymod_check_env (void);
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- {
- /* cnf par sor dir odr dat */
- { 1, 1, 1, 0, 0, 0 }, /* PA31: FCC1 MII COL */
- { 1, 1, 1, 0, 0, 0 }, /* PA30: FCC1 MII CRS */
- { 1, 1, 1, 1, 0, 0 }, /* PA29: FCC1 MII TX_ER */
- { 1, 1, 1, 1, 0, 0 }, /* PA28: FCC1 MII TX_EN */
- { 1, 1, 1, 0, 0, 0 }, /* PA27: FCC1 MII RX_DV */
- { 1, 1, 1, 0, 0, 0 }, /* PA26: FCC1 MII RX_ER */
- { 1, 0, 0, 1, 0, 0 }, /* PA25: FCC2 MII MDIO */
- { 1, 0, 0, 1, 0, 0 }, /* PA24: FCC2 MII MDC */
- { 1, 0, 0, 1, 0, 0 }, /* PA23: FCC3 MII MDIO */
- { 1, 0, 0, 1, 0, 0 }, /* PA22: FCC3 MII MDC */
- { 1, 1, 0, 1, 0, 0 }, /* PA21: FCC1 MII TxD[3] */
- { 1, 1, 0, 1, 0, 0 }, /* PA20: FCC1 MII TxD[2] */
- { 1, 1, 0, 1, 0, 0 }, /* PA19: FCC1 MII TxD[1] */
- { 1, 1, 0, 1, 0, 0 }, /* PA18: FCC1 MII TxD[0] */
- { 1, 1, 0, 0, 0, 0 }, /* PA17: FCC1 MII RxD[3] */
- { 1, 1, 0, 0, 0, 0 }, /* PA16: FCC1 MII RxD[2] */
- { 1, 1, 0, 0, 0, 0 }, /* PA15: FCC1 MII RxD[1] */
- { 1, 1, 0, 0, 0, 0 }, /* PA14: FCC1 MII RxD[0] */
- { 1, 0, 0, 1, 0, 0 }, /* PA13: FCC1 MII MDIO */
- { 1, 0, 0, 1, 0, 0 }, /* PA12: FCC1 MII MDC */
- { 1, 0, 0, 1, 0, 0 }, /* PA11: SEL_CD */
- { 1, 0, 0, 0, 0, 0 }, /* PA10: FLASH STS1 */
- { 1, 0, 0, 0, 0, 0 }, /* PA09: FLASH STS0 */
- { 1, 0, 0, 0, 0, 0 }, /* PA08: FLASH ~PE */
- { 1, 0, 0, 0, 0, 0 }, /* PA07: WATCH ~HRESET */
- { 1, 0, 0, 0, 1, 0 }, /* PA06: VC DONE */
- { 1, 0, 0, 1, 1, 0 }, /* PA05: VC INIT */
- { 1, 0, 0, 1, 0, 0 }, /* PA04: VC ~PROG */
- { 1, 0, 0, 1, 0, 0 }, /* PA03: VM ENABLE */
- { 1, 0, 0, 0, 1, 0 }, /* PA02: VM DONE */
- { 1, 0, 0, 1, 1, 0 }, /* PA01: VM INIT */
- { 1, 0, 0, 1, 0, 0 } /* PA00: VM ~PROG */
- },
-
- /* Port B configuration */
- {
- /* cnf par sor dir odr dat */
- { 1, 1, 0, 1, 0, 0 }, /* PB31: FCC2 MII TX_ER */
- { 1, 1, 0, 0, 0, 0 }, /* PB30: FCC2 MII RX_DV */
- { 1, 1, 1, 1, 0, 0 }, /* PB29: FCC2 MII TX_EN */
- { 1, 1, 0, 0, 0, 0 }, /* PB28: FCC2 MII RX_ER */
- { 1, 1, 0, 0, 0, 0 }, /* PB27: FCC2 MII COL */
- { 1, 1, 0, 0, 0, 0 }, /* PB26: FCC2 MII CRS */
- { 1, 1, 0, 1, 0, 0 }, /* PB25: FCC2 MII TxD[3] */
- { 1, 1, 0, 1, 0, 0 }, /* PB24: FCC2 MII TxD[2] */
- { 1, 1, 0, 1, 0, 0 }, /* PB23: FCC2 MII TxD[1] */
- { 1, 1, 0, 1, 0, 0 }, /* PB22: FCC2 MII TxD[0] */
- { 1, 1, 0, 0, 0, 0 }, /* PB21: FCC2 MII RxD[0] */
- { 1, 1, 0, 0, 0, 0 }, /* PB20: FCC2 MII RxD[1] */
- { 1, 1, 0, 0, 0, 0 }, /* PB19: FCC2 MII RxD[2] */
- { 1, 1, 0, 0, 0, 0 }, /* PB18: FCC2 MII RxD[3] */
- { 1, 1, 0, 0, 0, 0 }, /* PB17: FCC3 MII RX_DV */
- { 1, 1, 0, 0, 0, 0 }, /* PB16: FCC3 MII RX_ER */
- { 1, 1, 0, 1, 0, 0 }, /* PB15: FCC3 MII TX_ER */
- { 1, 1, 0, 1, 0, 0 }, /* PB14: FCC3 MII TX_EN */
- { 1, 1, 0, 0, 0, 0 }, /* PB13: FCC3 MII COL */
- { 1, 1, 0, 0, 0, 0 }, /* PB12: FCC3 MII CRS */
- { 1, 1, 0, 0, 0, 0 }, /* PB11: FCC3 MII RxD[3] */
- { 1, 1, 0, 0, 0, 0 }, /* PB10: FCC3 MII RxD[2] */
- { 1, 1, 0, 0, 0, 0 }, /* PB09: FCC3 MII RxD[1] */
- { 1, 1, 0, 0, 0, 0 }, /* PB08: FCC3 MII RxD[0] */
- { 1, 1, 0, 1, 0, 0 }, /* PB07: FCC3 MII TxD[3] */
- { 1, 1, 0, 1, 0, 0 }, /* PB06: FCC3 MII TxD[2] */
- { 1, 1, 0, 1, 0, 0 }, /* PB05: FCC3 MII TxD[1] */
- { 1, 1, 0, 1, 0, 0 }, /* PB04: FCC3 MII TxD[0] */
- { 0, 0, 0, 0, 0, 0 }, /* PB03: pin doesn't exist */
- { 0, 0, 0, 0, 0, 0 }, /* PB02: pin doesn't exist */
- { 0, 0, 0, 0, 0, 0 }, /* PB01: pin doesn't exist */
- { 0, 0, 0, 0, 0, 0 } /* PB00: pin doesn't exist */
- },
-
- /* Port C configuration */
- {
- /* cnf par sor dir odr dat */
- { 1, 0, 0, 0, 0, 0 }, /* PC31: MEZ ~IACK */
- { 0, 0, 0, 0, 0, 0 }, /* PC30: ? */
- { 1, 1, 0, 0, 0, 0 }, /* PC29: CLK SCCx */
- { 1, 1, 0, 0, 0, 0 }, /* PC28: CLK4 */
- { 1, 1, 0, 0, 0, 0 }, /* PC27: CLK SCCF */
- { 1, 1, 0, 0, 0, 0 }, /* PC26: CLK 32K */
- { 1, 1, 0, 0, 0, 0 }, /* PC25: BRG4/CLK7 */
- { 0, 0, 0, 0, 0, 0 }, /* PC24: ? */
- { 1, 1, 0, 0, 0, 0 }, /* PC23: CLK SCCx */
- { 1, 1, 0, 0, 0, 0 }, /* PC22: FCC1 MII RX_CLK */
- { 1, 1, 0, 0, 0, 0 }, /* PC21: FCC1 MII TX_CLK */
- { 1, 1, 0, 0, 0, 0 }, /* PC20: CLK SCCF */
- { 1, 1, 0, 0, 0, 0 }, /* PC19: FCC2 MII RX_CLK */
- { 1, 1, 0, 0, 0, 0 }, /* PC18: FCC2 MII TX_CLK */
- { 1, 1, 0, 0, 0, 0 }, /* PC17: FCC3 MII RX_CLK */
- { 1, 1, 0, 0, 0, 0 }, /* PC16: FCC3 MII TX_CLK */
- { 1, 0, 0, 0, 0, 0 }, /* PC15: SCC1 UART ~CTS */
- { 1, 0, 0, 0, 0, 0 }, /* PC14: SCC1 UART ~CD */
- { 1, 0, 0, 0, 0, 0 }, /* PC13: SCC2 UART ~CTS */
- { 1, 0, 0, 0, 0, 0 }, /* PC12: SCC2 UART ~CD */
- { 1, 0, 0, 1, 0, 0 }, /* PC11: SCC1 UART ~DTR */
- { 1, 0, 0, 1, 0, 0 }, /* PC10: SCC1 UART ~DSR */
- { 1, 0, 0, 1, 0, 0 }, /* PC09: SCC2 UART ~DTR */
- { 1, 0, 0, 1, 0, 0 }, /* PC08: SCC2 UART ~DSR */
- { 1, 0, 0, 0, 0, 0 }, /* PC07: TEMP ~ALERT */
- { 1, 0, 0, 0, 0, 0 }, /* PC06: FCC3 INT */
- { 1, 0, 0, 0, 0, 0 }, /* PC05: FCC2 INT */
- { 1, 0, 0, 0, 0, 0 }, /* PC04: FCC1 INT */
- { 0, 1, 1, 1, 0, 0 }, /* PC03: SDMA IDMA2 ~DACK */
- { 0, 1, 1, 0, 0, 0 }, /* PC02: SDMA IDMA2 ~DONE */
- { 0, 1, 0, 0, 0, 0 }, /* PC01: SDMA IDMA2 ~DREQ */
- { 1, 1, 0, 1, 0, 0 } /* PC00: BRG7 */
- },
-
- /* Port D configuration */
- {
- /* cnf par sor dir odr dat */
- { 1, 1, 0, 0, 0, 0 }, /* PD31: SCC1 UART RxD */
- { 1, 1, 1, 1, 0, 0 }, /* PD30: SCC1 UART TxD */
- { 1, 0, 0, 1, 0, 0 }, /* PD29: SCC1 UART ~RTS */
- { 1, 1, 0, 0, 0, 0 }, /* PD28: SCC2 UART RxD */
- { 1, 1, 0, 1, 0, 0 }, /* PD27: SCC2 UART TxD */
- { 1, 0, 0, 1, 0, 0 }, /* PD26: SCC2 UART ~RTS */
- { 1, 0, 0, 0, 0, 0 }, /* PD25: SCC1 UART ~RI */
- { 1, 0, 0, 0, 0, 0 }, /* PD24: SCC2 UART ~RI */
- { 1, 0, 0, 1, 0, 0 }, /* PD23: CLKGEN PD */
- { 1, 0, 0, 0, 0, 0 }, /* PD22: USER3 */
- { 1, 0, 0, 0, 0, 0 }, /* PD21: USER2 */
- { 1, 0, 0, 0, 0, 0 }, /* PD20: USER1 */
- { 1, 1, 1, 0, 0, 0 }, /* PD19: SPI ~SEL */
- { 1, 1, 1, 0, 0, 0 }, /* PD18: SPI CLK */
- { 1, 1, 1, 0, 0, 0 }, /* PD17: SPI MOSI */
- { 1, 1, 1, 0, 0, 0 }, /* PD16: SPI MISO */
- { 1, 1, 1, 0, 1, 0 }, /* PD15: I2C SDA */
- { 1, 1, 1, 0, 1, 0 }, /* PD14: I2C SCL */
- { 1, 0, 0, 1, 0, 1 }, /* PD13: TEMP ~STDBY */
- { 1, 0, 0, 1, 0, 1 }, /* PD12: FCC3 ~RESET */
- { 1, 0, 0, 1, 0, 1 }, /* PD11: FCC2 ~RESET */
- { 1, 0, 0, 1, 0, 1 }, /* PD10: FCC1 ~RESET */
- { 1, 0, 0, 0, 0, 0 }, /* PD09: PD9 */
- { 1, 0, 0, 0, 0, 0 }, /* PD08: PD8 */
- { 1, 0, 0, 1, 0, 1 }, /* PD07: PD7 */
- { 1, 0, 0, 1, 0, 1 }, /* PD06: PD6 */
- { 1, 0, 0, 1, 0, 1 }, /* PD05: PD5 */
- { 1, 0, 0, 1, 0, 1 }, /* PD04: PD4 */
- { 0, 0, 0, 0, 0, 0 }, /* PD03: pin doesn't exist */
- { 0, 0, 0, 0, 0, 0 }, /* PD02: pin doesn't exist */
- { 0, 0, 0, 0, 0, 0 }, /* PD01: pin doesn't exist */
- { 0, 0, 0, 0, 0, 0 } /* PD00: pin doesn't exist */
- }
-};
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * AMI FS6377 Clock Generator configuration table
- *
- * the "fs6377_regs[]" table entries correspond to FS6377 registers
- * 0 - 15 (total of 16 bytes).
- *
- * the data is written to the FS6377 via the i2c bus using address in
- * "fs6377_addr" (address is 7 bits - R/W bit not included).
- *
- * The fs6377 has four clock outputs: A, B, C and D.
- *
- * Outputs C and D can each provide two different clock outputs C1/D1 or
- * C2/D2 depending on the state of the SEL_CD input which is connected to
- * the MPC8260 I/O port pin PA11. PA11 output (SEL_CD input) low (or 0)
- * selects C1/D1 and PA11 output (SEL_CD input) high (or 1) selects C2/D2.
- *
- * PA11 defaults to output low (or 0) in the i/o port config table above.
- *
- * Output A provides a 100MHz for the High Speed Serial chips. Output B
- * provides a 3.6864MHz clock for more accurate asynchronous serial bit
- * rates. Output C is routed to the mezzanine connector but is currently
- * unused - both C1 and C2 are set to 16MHz. Output D is used by both the
- * alt-input and display mezzanine boards for their video chips. The
- * alt-input board requires a clock of 24.576MHz and this is available on
- * D1 (PA11=SEL_CD=0). The display board requires a clock of 27MHz and this
- * is available on D2 (PA11=SEL_CD=1).
- *
- * So the default is a clock suitable for the alt-input board. PA11 is toggled
- * later in misc_init_r(), if a display board is detected.
- */
-
-uchar fs6377_addr = 0x5c;
-
-uchar fs6377_regs[16] = {
- 12, 75, 64, 25, 144, 128, 25, 192,
- 0, 16, 135, 192, 224, 64, 64, 192
-};
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * special board initialisation, after clocks and timebase have been
- * set up but before environment and serial are initialised.
- *
- * added so that very early initialisations can be done using the i2c
- * driver (which requires the clocks, to calculate the dividers, and
- * the timebase, for udelay())
- */
-
-int
-board_postclk_init (void)
-{
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
- /*
- * Initialise the FS6377 clock chip
- *
- * the secondary address is the register number from where to
- * start the write - I want to write all the registers
- *
- * don't bother checking return status - we have no console yet
- * to print it on, nor any RAM to store it in - it will be obvious
- * if this doesn't work
- */
- (void) i2c_write (fs6377_addr, 0, 1, fs6377_regs,
- sizeof (fs6377_regs));
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity: Hardwired to HYMOD
- */
-
-int
-checkboard (void)
-{
- puts ("Board: HYMOD\n");
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * miscellaneous (early - while running in flash) initialisations.
- */
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-uint upmb_table[] = {
- /* Read Single Beat (RSS) - offset 0x00 */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /* Read Burst (RBS) - offset 0x08 */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /* Write Single Beat (WSS) - offset 0x18 */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /* Write Burst (WSS) - offset 0x20 */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /* Refresh Timer (PTS) - offset 0x30 */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /* Exception Condition (EXS) - offset 0x3c */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
-};
-
-uint upmc_table[] = {
- /* Read Single Beat (RSS) - offset 0x00 */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /* Read Burst (RBS) - offset 0x08 */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /* Write Single Beat (WSS) - offset 0x18 */
- 0xF0E00000, 0xF0A00000, 0x00A00000, 0x30A00000,
- 0xF0F40007, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /* Write Burst (WSS) - offset 0x20 */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /* Refresh Timer (PTS) - offset 0x30 */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /* Exception Condition (EXS) - offset 0x3c */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
-};
-
-int
-misc_init_f (void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
-
- printf ("UPMs: ");
-
- upmconfig (UPMB, upmb_table, sizeof upmb_table / sizeof upmb_table[0]);
- memctl->memc_mbmr = CONFIG_SYS_MBMR;
-
- upmconfig (UPMC, upmc_table, sizeof upmc_table / sizeof upmc_table[0]);
- memctl->memc_mcmr = CONFIG_SYS_MCMR;
-
- printf ("configured\n");
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t
-initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
- volatile uchar c = 0, *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8);
- ulong psdmr = CONFIG_SYS_PSDMR;
- int i;
-
- /*
- * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
- *
- * "At system reset, initialization software must set up the
- * programmable parameters in the memory controller banks registers
- * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
- * system software should execute the following initialization sequence
- * for each SDRAM device.
- *
- * 1. Issue a PRECHARGE-ALL-BANKS command
- * 2. Issue eight CBR REFRESH commands
- * 3. Issue a MODE-SET command to initialize the mode register
- *
- * The initial commands are executed by setting P/LSDMR[OP] and
- * accessing the SDRAM with a single-byte transaction."
- *
- * The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
- */
-
- memctl->memc_psrt = CONFIG_SYS_PSRT;
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
- *ramaddr = c;
-
- return (CONFIG_SYS_SDRAM_SIZE << 20);
-}
-
-/* ------------------------------------------------------------------------- */
-/* miscellaneous initialisations after relocation into ram (misc_init_r) */
-/* */
-/* loads the data in the main board and mezzanine board eeproms into */
-/* the hymod configuration struct stored in the board information area. */
-/* */
-/* if the contents of either eeprom is invalid, prompts for a serial */
-/* number (and an ethernet address if required) then fetches a file */
-/* containing information to be stored in the eeprom from the tftp server */
-/* (the file name is based on the serial number and a built-in path) */
-
-int
-last_stage_init (void)
-{
- hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
- int rc;
-
- /*
- * we use the cli_readline() function, but we also want
- * command timeout enabled
- */
- bootretry_init_cmd_timeout();
-
- memset ((void *) cp, 0, sizeof (*cp));
-
- /* set up main board config info */
-
- rc = hymod_eeprom_read (0, &cp->main.eeprom);
-
- puts ("EEPROM:main...");
- if (rc < 0)
- puts ("NOT PRESENT\n");
- else if (rc == 0)
- puts ("INVALID\n");
- else {
- cp->main.eeprom.valid = 1;
-
- printf ("OK (ver %u)\n", cp->main.eeprom.ver);
- hymod_eeprom_print (&cp->main.eeprom);
-
- /*
- * hard-wired assumption here: all hymod main boards will have
- * one xilinx fpga, with the interrupt line connected to IRQ2
- *
- * One day, this might be based on the board type
- */
-
- cp->main.xlx[0].mmap.prog.exists = 1;
- cp->main.xlx[0].mmap.prog.size = FPGA_MAIN_CFG_SIZE;
- cp->main.xlx[0].mmap.prog.base = FPGA_MAIN_CFG_BASE;
-
- cp->main.xlx[0].mmap.reg.exists = 1;
- cp->main.xlx[0].mmap.reg.size = FPGA_MAIN_REG_SIZE;
- cp->main.xlx[0].mmap.reg.base = FPGA_MAIN_REG_BASE;
-
- cp->main.xlx[0].mmap.port.exists = 1;
- cp->main.xlx[0].mmap.port.size = FPGA_MAIN_PORT_SIZE;
- cp->main.xlx[0].mmap.port.base = FPGA_MAIN_PORT_BASE;
-
- cp->main.xlx[0].iopins.prog_pin.port = FPGA_MAIN_PROG_PORT;
- cp->main.xlx[0].iopins.prog_pin.pin = FPGA_MAIN_PROG_PIN;
- cp->main.xlx[0].iopins.prog_pin.flag = 1;
- cp->main.xlx[0].iopins.init_pin.port = FPGA_MAIN_INIT_PORT;
- cp->main.xlx[0].iopins.init_pin.pin = FPGA_MAIN_INIT_PIN;
- cp->main.xlx[0].iopins.init_pin.flag = 1;
- cp->main.xlx[0].iopins.done_pin.port = FPGA_MAIN_DONE_PORT;
- cp->main.xlx[0].iopins.done_pin.pin = FPGA_MAIN_DONE_PIN;
- cp->main.xlx[0].iopins.done_pin.flag = 1;
-#ifdef FPGA_MAIN_ENABLE_PORT
- cp->main.xlx[0].iopins.enable_pin.port = FPGA_MAIN_ENABLE_PORT;
- cp->main.xlx[0].iopins.enable_pin.pin = FPGA_MAIN_ENABLE_PIN;
- cp->main.xlx[0].iopins.enable_pin.flag = 1;
-#endif
-
- cp->main.xlx[0].irq = FPGA_MAIN_IRQ;
- }
-
- /* set up mezzanine board config info */
-
- rc = hymod_eeprom_read (1, &cp->mezz.eeprom);
-
- puts ("EEPROM:mezz...");
- if (rc < 0)
- puts ("NOT PRESENT\n");
- else if (rc == 0)
- puts ("INVALID\n");
- else {
- cp->main.eeprom.valid = 1;
-
- printf ("OK (ver %u)\n", cp->mezz.eeprom.ver);
- hymod_eeprom_print (&cp->mezz.eeprom);
- }
-
- cp->crc = crc32 (0, (unsigned char *)cp, offsetof (hymod_conf_t, crc));
-
- hymod_check_env ();
-
- return (0);
-}
-
-#ifdef CONFIG_SHOW_ACTIVITY
-void board_show_activity (ulong timebase)
-{
-#ifdef CONFIG_SYS_HYMOD_DBLEDS
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile iop8260_t *iop = &immr->im_ioport;
- static int shift = 0;
-
- if ((timestamp % CONFIG_SYS_HZ) == 0) {
- if (++shift > 3)
- shift = 0;
- iop->iop_pdatd =
- (iop->iop_pdatd & ~0x0f000000) | (1 << (24 + shift));
- }
-#endif /* CONFIG_SYS_HYMOD_DBLEDS */
-}
-
-void show_activity(int arg)
-{
-}
-#endif /* CONFIG_SHOW_ACTIVITY */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _HYMOD_H_
-#define _HYMOD_H_
-
-#ifdef CONFIG_MPC8260
-#include <asm/iopin_8260.h>
-#endif
-
-/*
- * hymod configuration data - passed by boot code via the board information
- * structure (only U-Boot has support for this at the moment)
- *
- * there are three types of data passed up from the boot monitor. the first
- * (type hymod_eeprom_t) is the eeprom data that was read off both the main
- * (or mother) board and the mezzanine board (if any). this data defines how
- * many Xilinx fpgas are on each board, and their types (among other things).
- * the second type of data (type xlx_mmap_t, one per Xilinx fpga) defines where
- * in the physical address space the various Xilinx fpga access regions have
- * been mapped by the boot rom. the third type of data (type xlx_iopins_t,
- * one per Xilinx fpga) defines which io port pins are connected to the various
- * signals required to program a Xilinx fpga.
- *
- * A ram/flash "bank" refers to memory controlled by the same chip select.
- *
- * the eeprom contents are defined as in technical note #2 - basically,
- * a header, zero or more records in no particular order, and a 32 bit crc
- * a record is 1 or more type bytes, a length byte and "length" bytes.
- */
-
-#define HYMOD_EEPROM_ID 0xAA /* eeprom id byte */
-#define HYMOD_EEPROM_VER 1 /* eeprom contents version (0-127) */
-#define HYMOD_EEPROM_SIZE 256 /* number of bytes in the eeprom */
-
-/* eeprom header */
-typedef
- struct {
- unsigned char id; /* eeprom id byte */
- unsigned char :1;
- unsigned char ver:7; /* eeprom contents version number */
- unsigned long len; /* total # of bytes btw hdr and crc */
- }
-hymod_eehdr_t;
-
-/* maximum number of bytes available for eeprom data records */
-#define HYMOD_EEPROM_MAXLEN (HYMOD_EEPROM_SIZE \
- - sizeof (hymod_eehdr_t) \
- - sizeof (unsigned long))
-
-/* eeprom data record */
-typedef
- union {
- struct {
- unsigned char topbit:1;
- unsigned char type:7;
- unsigned char len;
- unsigned char data[1]; /* variable length */
- } small;
- struct {
- unsigned short topbit:1;
- unsigned short nxtbit:1;
- unsigned short type:14;
- unsigned short len;
- unsigned char data[1]; /* variable length */
- } medium;
- struct {
- unsigned long topbit:1;
- unsigned long nxtbit:1;
- unsigned long type:30;
- unsigned long len;
- unsigned char data[1]; /* variable length */
- } large;
- }
-hymod_eerec_t;
-
-#define HYMOD_EEOFF_MAIN 0x00 /* i2c addr offset for main eeprom */
-#define HYMOD_EEOFF_MEZZ 0x04 /* i2c addr offset for mezz eepomr */
-
-/* eeprom record types */
-#define HYMOD_EEREC_SERNO 1 /* serial number */
-#define HYMOD_EEREC_DATE 2 /* date */
-#define HYMOD_EEREC_BATCH 3 /* batch id */
-#define HYMOD_EEREC_TYPE 4 /* board type */
-#define HYMOD_EEREC_REV 5 /* revision number */
-#define HYMOD_EEREC_SDRAM 6 /* sdram sizes */
-#define HYMOD_EEREC_FLASH 7 /* flash sizes */
-#define HYMOD_EEREC_ZBT 8 /* zbt ram sizes */
-#define HYMOD_EEREC_XLXTYP 9 /* Xilinx fpga types */
-#define HYMOD_EEREC_XLXSPD 10 /* Xilinx fpga speeds */
-#define HYMOD_EEREC_XLXTMP 11 /* Xilinx fpga temperatures */
-#define HYMOD_EEREC_XLXGRD 12 /* Xilinx fpga grades */
-#define HYMOD_EEREC_CPUTYP 13 /* Motorola CPU type */
-#define HYMOD_EEREC_CPUSPD 14 /* CPU speed */
-#define HYMOD_EEREC_BUSSPD 15 /* bus speed */
-#define HYMOD_EEREC_CPMSPD 16 /* CPM speed */
-#define HYMOD_EEREC_HSTYPE 17 /* high-speed serial chip type */
-#define HYMOD_EEREC_HSCHIN 18 /* high-speed serial input channels */
-#define HYMOD_EEREC_HSCHOUT 19 /* high-speed serial output channels */
-
-/* some dimensions */
-#define HYMOD_MAX_BATCH 32 /* max no. of bytes in batch id */
-#define HYMOD_MAX_SDRAM 4 /* max sdram "banks" on any board */
-#define HYMOD_MAX_FLASH 4 /* max flash "banks" on any board */
-#define HYMOD_MAX_ZBT 16 /* max ZBT rams on any board */
-#define HYMOD_MAX_XLX 4 /* max Xilinx fpgas on any board */
-
-#define HYMOD_MAX_BYTES 16 /* enough to store any bytes array */
-
-/* board types */
-#define HYMOD_BDTYPE_NONE 0 /* information not present */
-#define HYMOD_BDTYPE_IO 1 /* I/O main board */
-#define HYMOD_BDTYPE_CLP 2 /* CLP main board */
-#define HYMOD_BDTYPE_DSP 3 /* DSP main board */
-#define HYMOD_BDTYPE_INPUT 4 /* video input mezzanine board */
-#define HYMOD_BDTYPE_ALTINPUT 5 /* video input mezzanine board */
-#define HYMOD_BDTYPE_DISPLAY 6 /* video display mezzanine board */
-#define HYMOD_BDTYPE_MAX 7 /* first invalid value */
-
-/* Xilinx fpga types */
-#define HYMOD_XTYP_NONE 0 /* information not present */
-#define HYMOD_XTYP_XCV300E 1 /* Xilinx Virtex 300 */
-#define HYMOD_XTYP_XCV400E 2 /* Xilinx Virtex 400 */
-#define HYMOD_XTYP_XCV600E 3 /* Xilinx Virtex 600 */
-#define HYMOD_XTYP_MAX 4 /* first invalid value */
-
-/* Xilinx fpga speeds */
-#define HYMOD_XSPD_NONE 0 /* information not present */
-#define HYMOD_XSPD_SIX 1
-#define HYMOD_XSPD_SEVEN 2
-#define HYMOD_XSPD_EIGHT 3
-#define HYMOD_XSPD_MAX 4 /* first invalid value */
-
-/* Xilinx fpga temperatures */
-#define HYMOD_XTMP_NONE 0 /* information not present */
-#define HYMOD_XTMP_COM 1
-#define HYMOD_XTMP_IND 2
-#define HYMOD_XTMP_MAX 3 /* first invalid value */
-
-/* Xilinx fpga grades */
-#define HYMOD_XTMP_NONE 0 /* information not present */
-#define HYMOD_XTMP_NORMAL 1
-#define HYMOD_XTMP_ENGSAMP 2
-#define HYMOD_XTMP_MAX 3 /* first invalid value */
-
-/* CPU types */
-#define HYMOD_CPUTYPE_NONE 0 /* information not present */
-#define HYMOD_CPUTYPE_MPC8260 1 /* Motorola MPC8260 embedded powerpc */
-#define HYMOD_CPUTYPE_MAX 2 /* first invalid value */
-
-/* CPU/BUS/CPM clock speeds */
-#define HYMOD_CLKSPD_NONE 0 /* information not present */
-#define HYMOD_CLKSPD_33MHZ 1
-#define HYMOD_CLKSPD_66MHZ 2
-#define HYMOD_CLKSPD_100MHZ 3
-#define HYMOD_CLKSPD_133MHZ 4
-#define HYMOD_CLKSPD_166MHZ 5
-#define HYMOD_CLKSPD_200MHZ 6
-#define HYMOD_CLKSPD_MAX 7 /* first invalid value */
-
-/* high speed serial chip types */
-#define HYMOD_HSSTYPE_NONE 0 /* information not present */
-#define HYMOD_HSSTYPE_AMCC52064 1
-#define HYMOD_HSSTYPE_MAX 2 /* first invalid value */
-
-/* a date (yyyy-mm-dd) */
-typedef
- struct {
- unsigned short year;
- unsigned char month;
- unsigned char day;
- }
-hymod_date_t;
-
-/* describes a Xilinx fpga */
-typedef
- struct {
- unsigned char type; /* chip type */
- unsigned char speed; /* chip speed rating */
- unsigned char temp; /* chip temperature rating */
- unsigned char grade; /* chip grade */
- }
-hymod_xlx_t;
-
-/* describes a Motorola embedded processor */
-typedef
- struct {
- unsigned char type; /* CPU type */
- unsigned char cpuspd; /* speed of the PowerPC core */
- unsigned char busspd; /* speed of the system and 60x bus */
- unsigned char cpmspd; /* speed of the CPM co-processor */
- }
-hymod_mpc_t;
-
-/* info about high-speed (1Gbit) serial interface */
-typedef
- struct {
- unsigned char type; /* high-speed serial chip type */
- unsigned char nchin; /* number of input channels mounted */
- unsigned char nchout; /* number of output channels mounted */
- }
-hymod_hss_t;
-
-/*
- * this defines the contents of the serial eeprom that exists on every
- * hymod board, including mezzanine boards (the serial eeprom will be
- * faked for early development boards that don't have one)
- */
-
-typedef
- struct {
- unsigned char valid:1; /* contents of this struct is valid */
- unsigned char ver:7; /* eeprom contents version */
- unsigned char bdtype; /* board type */
- unsigned char bdrev; /* board revision */
- unsigned char batchlen; /* length of batch string below */
- unsigned long serno; /* serial number */
- hymod_date_t date; /* manufacture date */
- unsigned char batch[32]; /* manufacturer specific batch id */
- unsigned char nsdram; /* # of ram "banks" */
- unsigned char nflash; /* # of flash "banks" */
- unsigned char nzbt; /* # of ZBT rams */
- unsigned char nxlx; /* # of Xilinx fpgas */
- unsigned char sdramsz[HYMOD_MAX_SDRAM]; /* log2 of sdram size */
- unsigned char flashsz[HYMOD_MAX_FLASH]; /* log2 of flash size */
- unsigned char zbtsz[HYMOD_MAX_ZBT]; /* log2 of ZBT ram size */
- hymod_xlx_t xlx[HYMOD_MAX_XLX]; /* Xilinx fpga info */
- hymod_mpc_t mpc; /* Motorola MPC CPU info */
- hymod_hss_t hss; /* high-speed serial info */
- }
-hymod_eeprom_t;
-
-/*
- * this defines a region in the processor's physical address space
- */
-typedef
- struct {
- unsigned long exists:1; /* 1 if the region exists, 0 if not */
- unsigned long size:31; /* size in bytes */
- unsigned long base; /* base address */
- }
-xlx_prgn_t;
-
-/*
- * this defines where the various Xilinx fpga access regions are mapped
- * into the physical address space of the processor
- */
-typedef
- struct {
- xlx_prgn_t prog; /* program access region */
- xlx_prgn_t reg; /* register access region */
- xlx_prgn_t port; /* port access region */
- }
-xlx_mmap_t;
-
-/*
- * this defines which 8260 i/o port pins are connected to the various
- * signals required for programming a Xilinx fpga
- */
-typedef
- struct {
- iopin_t prog_pin; /* assert for >= 300ns to program */
- iopin_t init_pin; /* goes high when fpga is cleared */
- iopin_t done_pin; /* goes high when program is done */
- iopin_t enable_pin; /* some fpgas need enabling */
- }
-xlx_iopins_t;
-
-/* all info about one Xilinx chip */
-typedef
- struct {
- xlx_mmap_t mmap;
- xlx_iopins_t iopins;
- unsigned long irq:8; /* h/w intr req number for this fpga */
- }
-xlx_info_t;
-
-/* all info about one hymod board */
-typedef
- struct {
- hymod_eeprom_t eeprom;
- xlx_info_t xlx[HYMOD_MAX_XLX];
- }
-hymod_board_t;
-
-/*
- * this defines the configuration information of a hymod board-set
- * (main board + possible mezzanine board). In future, there may be
- * more than one mezzanine board (stackable?) - if so, add a "mezz2"
- * field, and so on... or make mezz an array?
- */
-typedef
- struct {
- unsigned long ver:8; /* version control */
- hymod_board_t main; /* main board info */
- hymod_board_t mezz; /* mezzanine board info */
- unsigned long crc; /* ensures kernel and boot prom agree */
- }
-hymod_conf_t;
-
-#endif /* _HYMOD_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <bootretry.h>
-#include <cli.h>
-
-int
-hymod_get_serno (const char *prompt)
-{
- for (;;) {
- int n, serno;
- char *p;
-
- bootretry_reset_cmd_timeout();
-
- n = cli_readline(prompt);
-
- if (n < 0)
- return (n);
-
- if (n == 0)
- continue;
-
- serno = (int) simple_strtol (console_buffer, &p, 10);
-
- if (p > console_buffer && *p == '\0' && serno > 0)
- return (serno);
-
- printf ("Invalid number (%s) - please re-enter\n",
- console_buffer);
- }
-}
-
-int
-hymod_get_ethaddr (void)
-{
- for (;;) {
- int n;
-
- bootretry_reset_cmd_timeout();
-
- n = cli_readline("Enter board ethernet address: ");
-
- if (n < 0)
- return (n);
-
- if (n == 0)
- continue;
-
- if (n == 17) {
- int i;
- char *p, *q;
-
- /* see if it looks like an ethernet address */
-
- p = console_buffer;
-
- for (i = 0; i < 6; i++) {
- char term = (i == 5 ? '\0' : ':');
-
- (void)simple_strtol (p, &q, 16);
-
- if ((q - p) != 2 || *q++ != term)
- break;
-
- p = q;
- }
-
- if (i == 6) {
- /* it looks ok - set it */
- printf ("Setting ethernet addr to %s\n",
- console_buffer);
-
- setenv ("ethaddr", console_buffer);
-
- puts ("Remember to do a 'saveenv' to "
- "make it permanent\n");
-
- return (0);
- }
- }
-
- printf ("Invalid ethernet addr (%s) - please re-enter\n",
- console_buffer);
- }
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8260/start.o (.text)
-/*
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
-
- . = env_offset;
-*/
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- . = ALIGN(256 * 1024);
- .ppcenv :
- {
- common/env_embedded.o (.ppcenv)
- }
- . = ALIGN(4);
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
if TARGET_LP8X4X
-config SYS_CPU
- default "pxa"
-
config SYS_BOARD
default "lp8x4x"
+++ /dev/null
-if TARGET_ICU862
-
-config SYS_BOARD
- default "icu862"
-
-config SYS_CONFIG_NAME
- default "ICU862"
-
-endif
+++ /dev/null
-ICU862 BOARD
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-F: board/icu862/
-F: include/configs/ICU862.h
-F: configs/ICU862_defconfig
-F: configs/ICU862_100MHz_defconfig
+++ /dev/null
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = icu862.o flash.o pcmcia.o
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size_b0;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
- flash_info[i].flash_id = FLASH_UNKNOWN;
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0,
- size_b0 >> 20);
- }
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
-
- /* Re-do sizing to get full correct info */
- size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
- &flash_info[0]);
-#endif
-
- /* ICU862 Board has only one Flash Bank */
- flash_info[0].size = size_b0;
-
- return size_b0;
-
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM033C)) {
- /* set sector offsets for uniform sector type */
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00040000);
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- puts ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: puts ("AMD "); break;
- case FLASH_MAN_FUJ: puts ("FUJITSU "); break;
- case FLASH_MAN_BM: puts ("BRIGHT MICRO "); break;
- default: puts ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040: puts ("29F040/29LV040 (4 Mbit, uniform sectors)\n");
- break;
- case FLASH_AM400B: puts ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: puts ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: puts ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: puts ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: puts ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: puts ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: puts ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: puts ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_AM033C: puts ("AM29LV033C (32 Mbit)\n");
- break;
- default: puts ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- puts (" Sector Start Addresses:");
-
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0) {
- puts ("\n ");
- }
-
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
-
- puts ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
-#if 0
- ulong base = (ulong)addr;
-#endif
- uchar value;
-
- /* Write auto select command: read Manufacturer ID */
-#if 0
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00900090;
-#else
- addr[0x0555] = 0xAAAAAAAA;
- addr[0x02AA] = 0x55555555;
- addr[0x0555] = 0x90909090;
-#endif
-
- value = addr[0];
-
- switch (value + (value << 16)) {
- case AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
-
- case FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- break;
- }
-
- value = addr[1]; /* device ID */
-
- switch ((unsigned long)value) {
- case AMD_ID_F040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#if 0 /* enable when device IDs are available */
- case AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-#endif
- case AMD_ID_LV033C:
- info->flash_id += FLASH_AM033C;
- info->sector_count = 64;
- info->size = 0x01000000;
- break; /* => 16Mb */
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
-#if 0
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
-#else
- flash_get_offsets ((ulong)addr, &flash_info[0]);
-#endif
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile unsigned long *)(info->start[i]);
-#if 1
- /* We don't know why it happens, but on ICU Board *
- * for AMD29033C flash we need to resend the command of *
- * reading flash protection for upper 8 Mb of flash */
- if ( i == 32 ) {
- addr[0x0555] = 0xAAAAAAAA;
- addr[0x02AA] = 0x55555555;
- addr[0x0555] = 0x90909090;
- }
-#endif
- info->protect[i] = addr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (volatile unsigned long *)info->start[0];
-#if 0
- *addr = 0x00F000F0; /* reset bank */
-#else
- *addr = 0xF0F0F0F0; /* reset bank */
-#endif
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- puts ("- missing\n");
- } else {
- puts ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- puts ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- puts ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
-#if 0
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00800080;
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
-#else
- addr[0x0555] = 0xAAAAAAAA;
- addr[0x02AA] = 0x55555555;
- addr[0x0555] = 0x80808080;
- addr[0x0555] = 0xAAAAAAAA;
- addr[0x02AA] = 0x55555555;
-#endif
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_long*)(info->start[sect]);
-#if 0
- addr[0] = 0x00300030;
-#else
- addr[0] = 0x30303030;
-#endif
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_long*)(info->start[l_sect]);
-#if 0
- while ((addr[0] & 0x00800080) != 0x00800080)
-#else
- while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF)
-#endif
- {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- puts ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (volatile unsigned long *)info->start[0];
-#if 0
- addr[0] = 0x00F000F0; /* reset bank */
-#else
- addr[0] = 0xF0F0F0F0; /* reset bank */
-#endif
-
- puts (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
-#if 0
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00A000A0;
-#else
- addr[0x0555] = 0xAAAAAAAA;
- addr[0x02AA] = 0x55555555;
- addr[0x0555] = 0xA0A0A0A0;
-#endif
-
- *((vu_long *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
-#if 0
- while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080))
-#else
- while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080))
-#endif
- {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <mpc8xx.h>
-
-/*
- * Memory Controller Using
- *
- * CS0 - Flash memory (0x40000000)
- * CS1 - SDRAM (0x00000000}
- * CS2 - S/UNI Ultra ATM155
- * CS3 - IDT 77106 ATM25
- * CS4 - DSP HPI
- * CS5 - E1/T1 Interface device
- * CS6 - PCMCIA device
- * CS7 - PCMCIA device
- */
-
-/* ------------------------------------------------------------------------- */
-
-#define _not_used_ 0xffffffff
-
-const uint sdram_table[] = {
- /* single read. (offset 0 in upm RAM) */
- 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
- 0x1ff77c47,
-
- /* MRS initialization (offset 5) */
-
- 0x1ff77c34, 0xefeabc34, 0x1fb57c35,
-
- /* burst read. (offset 8 in upm RAM) */
- 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
- 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
- _not_used_, _not_used_, _not_used_, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
-
- /* single write. (offset 18 in upm RAM) */
- 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
- _not_used_, _not_used_, _not_used_, _not_used_,
-
- /* burst write. (offset 20 in upm RAM) */
- 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
- 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
-
- /* refresh. (offset 30 in upm RAM) */
- 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- 0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
-
- /* exception. (offset 3c in upm RAM) */
- 0x7ffffc07, _not_used_, _not_used_, _not_used_
-};
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- puts ("Board: ICU862 Board\n");
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size8, size9;
- long int size_b0 = 0;
- unsigned long reg;
-
- upmconfig (UPMA, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- /*
- * Preliminary prescaler for refresh (depends on number of
- * banks): This value is selected for four cycles every 62.4 us
- * with two SDRAM banks or four cycles every 31.2 us with one
- * bank. It will be adjusted after memory sizing.
- */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
-
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller bank 1 to the SDRAM bank at
- * preliminary address - these have to be modified after the
- * SDRAM size has been determined.
- */
- memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
- memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
-
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
-
- udelay (200);
-
- /* perform SDRAM initializsation sequence */
-
- memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
- udelay (200);
- memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */
- udelay (200);
-
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
-
- udelay (1000);
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- *
- * try 8 column mode
- */
- size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE1_PRELIM,
- SDRAM_MAX_SIZE);
-
- udelay (1000);
-
- /*
- * try 9 column mode
- */
- size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE1_PRELIM,
- SDRAM_MAX_SIZE);
-
- if (size8 < size9) { /* leave configuration at 9 columns */
- size_b0 = size9;
-/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
- } else { /* back to 8 columns */
- size_b0 = size8;
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
- udelay (500);
-/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
- }
-
- udelay (1000);
-
- /*
- * Adjust refresh rate depending on SDRAM type, both banks
- * For types > 128 MBit leave it at the current (fast) rate
- */
- if ((size_b0 < 0x02000000)) {
- /* reduce to 15.6 us (62.4 us / quad) */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
- udelay (1000);
- }
-
- /*
- * Final mapping
- */
-
- memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
- memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
- /* adjust refresh rate depending on SDRAM type, one bank */
- reg = memctl->memc_mptpr;
- reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
- memctl->memc_mptpr = reg;
-
- udelay (10000);
-
- return (size_b0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
- long int maxsize)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_mamr = mamr_value;
-
- return (get_ram_size(base, maxsize));
-}
+++ /dev/null
-#include <common.h>
-#include <mpc8xx.h>
-#include <pcmcia.h>
-
-#undef CONFIG_PCMCIA
-
-#if defined(CONFIG_CMD_PCMCIA)
-#define CONFIG_PCMCIA
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
-#define CONFIG_PCMCIA
-#endif
-
-#ifdef CONFIG_PCMCIA
-
-#define PCMCIA_BOARD_MSG "ICU862"
-
-static void cfg_port_B (void)
-{
- volatile cpm8xx_t *cp;
- uint reg;
-
- cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
-
- /*
- * Configure Port B for TPS2205 PC-Card Power-Interface Switch
- *
- * Switch off all voltages, assert shutdown
- */
- reg = cp->cp_pbdat;
- reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */
- TPS2205_VCC3 | TPS2205_VCC5 | /* VAVCC => Hi-Z */
- TPS2205_SHDN); /* enable switch */
- cp->cp_pbdat = reg;
-
- cp->cp_pbpar &= ~(TPS2205_INPUTS | TPS2205_OUTPUTS);
-
- reg = cp->cp_pbdir & ~(TPS2205_INPUTS);
- cp->cp_pbdir = reg | TPS2205_OUTPUTS;
-
- debug ("Set Port B: PAR: %08x DIR: %08x DAT: %08x\n",
- cp->cp_pbpar, cp->cp_pbdir, cp->cp_pbdat);
-}
-
-int pcmcia_hardware_enable(int slot)
-{
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- volatile sysconf8xx_t *sysp;
- uint reg, pipr, mask;
- int i;
-
- debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- udelay(10000);
-
- sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
- cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
-
- /* Configure Port B for TPS2205 PC-Card Power-Interface Switch */
- cfg_port_B ();
-
- /*
- * Configure SIUMCR to enable PCMCIA port B
- * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
- */
- sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
-
- /* clear interrupt state, and disable interrupts */
- pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
- pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
-
- /*
- * Disable interrupts, DMA, and PCMCIA buffers
- * (isolate the interface) and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- /*
- * Make sure there is a card in the slot, then configure the interface.
- */
- udelay(10000);
- debug ("[%d] %s: PIPR(%p)=0x%x\n",
- __LINE__,__FUNCTION__,
- &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
- if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
- printf (" No Card found\n");
- return (1);
- }
-
- /*
- * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
- */
- mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
- pipr = pcmp->pcmc_pipr;
- debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
- pipr,
- (reg&PCMCIA_VS1(slot))?"n":"ff",
- (reg&PCMCIA_VS2(slot))?"n":"ff");
-
- reg = cp->cp_pbdat;
- if ((pipr & mask) == mask) {
- reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */
- TPS2205_VCC3); /* 3V off */
- reg &= ~(TPS2205_VCC5); /* 5V on */
- puts (" 5.0V card found: ");
- } else {
- reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */
- TPS2205_VCC5); /* 5V off */
- reg &= ~(TPS2205_VCC3); /* 3V on */
- puts (" 3.3V card found: ");
- }
-
- debug ("\nPB DAT: %08x -> 3.3V %s 5.0V %s VPP_PGM %s VPP_VCC %s\n",
- reg,
- (reg & TPS2205_VCC3) ? "off" : "on",
- (reg & TPS2205_VCC5) ? "off" : "on",
- (reg & TPS2205_VPP_PGM) ? "off" : "on",
- (reg & TPS2205_VPP_VCC) ? "off" : "on" );
-
- cp->cp_pbdat = reg;
-
- /* Wait 500 ms; use this to check for over-current */
- for (i=0; i<5000; ++i) {
- if ((cp->cp_pbdat & TPS2205_OC) == 0) {
- printf (" *** Overcurrent - Safety shutdown ***\n");
- cp->cp_pbdat &= ~(TPS2205_SHDN);
- return (1);
- }
- udelay (100);
- }
-
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
-
- udelay(250000); /* some cards need >150 ms to come up :-( */
-
- debug ("# hardware_enable done\n");
-
- return (0);
-}
-
-
-#if defined(CONFIG_CMD_PCMCIA)
-int pcmcia_hardware_disable(int slot)
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
-
- debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- immap = (immap_t *)CONFIG_SYS_IMMR;
- cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
-
- /* Shut down */
- cp->cp_pbdat &= ~(TPS2205_SHDN);
-
- /* Configure PCMCIA General Control Register */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
-
- udelay(10000);
-
- return (0);
-}
-#endif
-
-
-int pcmcia_voltage_set(int slot, int vcc, int vpp)
-{
- volatile cpm8xx_t *cp;
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
-
- debug ("voltage_set: "
- PCMCIA_BOARD_MSG
- " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
- 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
-
- cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
- /*
- * Disable PCMCIA buffers (isolate the interface)
- * and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- /*
- * Configure Port C pins for
- * 5 Volts Enable and 3 Volts enable,
- * Turn all power pins to Hi-Z
- */
- debug ("PCMCIA power OFF\n");
- cfg_port_B (); /* Enables switch, but all in Hi-Z */
-
- reg = cp->cp_pbdat;
-
- switch(vcc) {
- case 0: break; /* Switch off */
- case 33: reg &= ~TPS2205_VCC3; break; /* Switch on 3.3V */
- case 50: reg &= ~TPS2205_VCC5; break; /* Switch on 5.0V */
- default: goto done;
- }
-
- /* Checking supported voltages */
-
- debug ("PIPR: 0x%x --> %s\n",
- pcmp->pcmc_pipr,
- (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
-
- cp->cp_pbdat = reg;
-
-#ifdef DEBUG
-{
- char *s;
-
- if ((reg & TPS2205_VCC3) == 0) {
- s = "at 3.3V";
- } else if ((reg & TPS2205_VCC5) == 0) {
- s = "at 5.0V";
- } else {
- s = "down";
- }
- printf ("PCMCIA powered %s\n", s);
-}
-#endif
-
-done:
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
- slot+'A');
- return (0);
-}
-
-#endif /* CONFIG_PCMCIA */
+++ /dev/null
-/*
- * (C) Copyright 2001-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-if TARGET_IDS8247
-
-config SYS_BOARD
- default "ids8247"
-
-config SYS_VENDOR
- default "ids"
-
-config SYS_CONFIG_NAME
- default "IDS8247"
-
-endif
+++ /dev/null
-IDS8247 BOARD
-M: Heiko Schocher <hs@denx.de>
-S: Maintained
-F: board/ids/ids8247/
-F: include/configs/IDS8247.h
-F: configs/IDS8247_defconfig
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2005
-# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = ids8247.o
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#include <libfdt_env.h>
-#include <fdt_support.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */
- /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */
- /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
- /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
- /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
- /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
- /* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */
-#if defined(CONFIG_SYS_I2C_SOFT)
- /* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */
- /* PA23 */ { 1, 0, 0, 1, 1, 1 }, /* I2C_SCL2 */
-#else /* normal I/O port pins */
- /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */
- /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */
-#endif
- /* PA22 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DCD */
- /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
- /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
- /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
- /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
- /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
- /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */
- /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
- /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
- /* PA13 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_RTS */
- /* PA12 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_CTS */
- /* PA11 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_DTR */
- /* PA10 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DSR */
- /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
- /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
- /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
- /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
- /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
- /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
- /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
- /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
- /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
- /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
- /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
- /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
- /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
- /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
- /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CLSN */
- /* PC28 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_OUT */
- /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
- /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_IN */
- /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
- /* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
- /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
- /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
- /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
- /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
- /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
- /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
- /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */
- /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */
- /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
- /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
- /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
- /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
- /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
- /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 1, 0, 0, 0, 0 }, /* SCC3_RX */
- /* PD24 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_TX */
- /* PD23 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_RTS */
- /* PD22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC4_RXD */
- /* PD21 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_TXD */
- /* PD20 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_RTS */
- /* PD19 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_SEL */
- /* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_CLK */
- /* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MOSI */
- /* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MISO */
-#if defined(CONFIG_HARD_I2C)
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA1 */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL1 */
-#else /* normal I/O port pins */
- /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* PD15 */
- /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* PD14 */
-#endif
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
- /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
- /* PD7 */ { 1, 0, 0, 1, 0, 1 }, /* MII_MDIO */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-/* ------------------------------------------------------------------------- */
-
-/* Check Board Identity:
- */
-int checkboard (void)
-{
- puts ("Board: IDS 8247\n");
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
- *
- * This routine performs standard 8260 initialization sequence
- * and calculates the available memory size. It may be called
- * several times to try different SDRAM configurations on both
- * 60x and local buses.
- */
-static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
- ulong orx, volatile uchar * base)
-{
- volatile uchar c = 0xff;
- volatile uint *sdmr_ptr;
- volatile uint *orx_ptr;
- ulong maxsize, size;
- int i;
-
- /* We must be able to test a location outsize the maximum legal size
- * to find out THAT we are outside; but this address still has to be
- * mapped by the controller. That means, that the initial mapping has
- * to be (at least) twice as large as the maximum expected size.
- */
- maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
-
- sdmr_ptr = &memctl->memc_psdmr;
- orx_ptr = &memctl->memc_or2;
-
- *orx_ptr = orx;
-
- /*
- * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
- *
- * "At system reset, initialization software must set up the
- * programmable parameters in the memory controller banks registers
- * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
- * system software should execute the following initialization sequence
- * for each SDRAM device.
- *
- * 1. Issue a PRECHARGE-ALL-BANKS command
- * 2. Issue eight CBR REFRESH commands
- * 3. Issue a MODE-SET command to initialize the mode register
- *
- * The initial commands are executed by setting P/LSDMR[OP] and
- * accessing the SDRAM with a single-byte transaction."
- *
- * The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
- */
-
- *sdmr_ptr = sdmr | PSDMR_OP_PREA;
- *base = c;
-
- *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
- *base = c;
-
- *sdmr_ptr = sdmr | PSDMR_OP_MRW;
- *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
-
- *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
- *base = c;
-
- size = get_ram_size((long *)base, maxsize);
- *orx_ptr = orx | ~(size - 1);
-
- return (size);
-}
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
-
- long psize;
-
- psize = 16 * 1024 * 1024;
-
- memctl->memc_psrt = CONFIG_SYS_PSRT;
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-#ifndef CONFIG_SYS_RAMBOOT
- /* 60x SDRAM setup:
- */
- psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR2,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
-#endif /* CONFIG_SYS_RAMBOOT */
-
- icache_enable ();
-
- return (psize);
-}
-
-int misc_init_r (void)
-{
- gd->bd->bi_flashstart = 0xff800000;
- return 0;
-}
-
-#if defined(CONFIG_CMD_NAND)
-#include <nand.h>
-#include <linux/mtd/mtd.h>
-#include <asm/io.h>
-
-static u8 hwctl;
-
-static void ids_nand_hwctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- if ( ctrl & NAND_CLE ) {
- hwctl |= 0x1;
- writeb(0x00, (this->IO_ADDR_W + 0x0a));
- } else {
- hwctl &= ~0x1;
- writeb(0x00, (this->IO_ADDR_W + 0x08));
- }
- if ( ctrl & NAND_ALE ) {
- hwctl |= 0x2;
- writeb(0x00, (this->IO_ADDR_W + 0x09));
- } else {
- hwctl &= ~0x2;
- writeb(0x00, (this->IO_ADDR_W + 0x08));
- }
- if ( (ctrl & NAND_NCE) != NAND_NCE)
- writeb(0x00, (this->IO_ADDR_W + 0x0c));
- else
- writeb(0x00, (this->IO_ADDR_W + 0x08));
- }
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-
-}
-
-static u_char ids_nand_read_byte(struct mtd_info *mtd)
-{
- struct nand_chip *this = mtd->priv;
-
- return readb(this->IO_ADDR_R);
-}
-
-static void ids_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
- struct nand_chip *nand = mtd->priv;
- int i;
-
- for (i = 0; i < len; i++) {
- if (hwctl & 0x1)
- writeb(buf[i], (nand->IO_ADDR_W + 0x02));
- else if (hwctl & 0x2)
- writeb(buf[i], (nand->IO_ADDR_W + 0x01));
- else
- writeb(buf[i], nand->IO_ADDR_W);
- }
-}
-
-static void ids_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
-{
- struct nand_chip *this = mtd->priv;
- int i;
-
- for (i = 0; i < len; i++) {
- buf[i] = readb(this->IO_ADDR_R);
- }
-}
-
-static int ids_nand_dev_ready(struct mtd_info *mtd)
-{
- /* constant delay (see also tR in the datasheet) */
- udelay(12);
- return 1;
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
- nand->ecc.mode = NAND_ECC_SOFT;
-
- /* Reference hardware control function */
- nand->cmd_ctrl = ids_nand_hwctrl;
- nand->read_byte = ids_nand_read_byte;
- nand->write_buf = ids_nand_write_buf;
- nand->read_buf = ids_nand_read_buf;
- nand->dev_ready = ids_nand_dev_ready;
- nand->chip_delay = 12;
-
- return 0;
-}
-
-#endif /* CONFIG_CMD_NAND */
-
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-void ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup( blob, bd);
-}
-#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
if TARGET_MALTA
-config SYS_CPU
- default "mips32"
-
config SYS_BOARD
default "malta"
if TARGET_IMX31_PHYCORE
-config SYS_CPU
- default "arm1136"
-
config SYS_BOARD
default "imx31_phycore"
if TARGET_AM335X_IGEP0033
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "igep0033"
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
#include <twl4030.h>
#include <netdev.h>
#include <asm/gpio.h>
};
#endif
+static const struct ns16550_platdata igep_serial = {
+ OMAP34XX_UART3,
+ 2,
+ V_NS16550_CLK
+};
+
+U_BOOT_DEVICE(igep_uart) = {
+ "serial_omap",
+ &igep_serial
+};
+
/*
* Routine: board_init
* Description: Early hardware init.
if TARGET_JORNADA
-config SYS_CPU
- default "sa1100"
-
config SYS_BOARD
default "jornada"
if TARGET_TX25
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "tx25"
testboot = (testpin != 0) && (s);
if (verbose) {
printf("testpin = %d\n", testpin);
+ /* cppcheck-suppress nullPointer */
printf("test_bank = %s\n", s ? s : "not set");
printf("boot test app : %s\n", (testboot) ? "yes" : "no");
}
--- /dev/null
+if TARGET_KOSAGI_NOVENA
+
+config SYS_CPU
+ default "armv7"
+
+config SYS_BOARD
+ default "novena"
+
+config SYS_VENDOR
+ default "kosagi"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "novena"
+
+endif
--- /dev/null
+NOVENA BOARD
+M: Marek Vasut <marex@denx.de>
+S: Maintained
+F: board/kosagi/novena/
+F: include/configs/novena.h
+F: configs/novena_defconfig
--- /dev/null
+#
+# Copyright (C) 2014 Marek Vasut <marex@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y := novena_spl.o
+else
+obj-y := novena.o
+endif
--- /dev/null
+/*
+ * Novena board support
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/sata.h>
+#include <asm/imx-common/video.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <input.h>
+#include <ipu_pixfmt.h>
+#include <linux/fb.h>
+#include <linux/input.h>
+#include <malloc.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <stdio_dev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define NOVENA_BUTTON_GPIO IMX_GPIO_NR(4, 14)
+#define NOVENA_SD_WP IMX_GPIO_NR(1, 2)
+#define NOVENA_SD_CD IMX_GPIO_NR(1, 4)
+
+/*
+ * GPIO button
+ */
+#ifdef CONFIG_KEYBOARD
+static struct input_config button_input;
+
+static int novena_gpio_button_read_keys(struct input_config *input)
+{
+ int key = KEY_ENTER;
+ if (gpio_get_value(NOVENA_BUTTON_GPIO))
+ return 0;
+ input_send_keycodes(&button_input, &key, 1);
+ return 1;
+}
+
+static int novena_gpio_button_getc(struct stdio_dev *dev)
+{
+ return input_getc(&button_input);
+}
+
+static int novena_gpio_button_tstc(struct stdio_dev *dev)
+{
+ return input_tstc(&button_input);
+}
+
+static int novena_gpio_button_init(struct stdio_dev *dev)
+{
+ gpio_direction_input(NOVENA_BUTTON_GPIO);
+ input_set_delays(&button_input, 250, 250);
+ return 0;
+}
+
+int drv_keyboard_init(void)
+{
+ int error;
+ struct stdio_dev dev = {
+ .name = "button",
+ .flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM,
+ .start = novena_gpio_button_init,
+ .getc = novena_gpio_button_getc,
+ .tstc = novena_gpio_button_tstc,
+ };
+
+ error = input_init(&button_input, 0);
+ if (error) {
+ debug("%s: Cannot set up input\n", __func__);
+ return -1;
+ }
+ button_input.read_keys = novena_gpio_button_read_keys;
+
+ error = input_stdio_register(&dev);
+ if (error)
+ return error;
+
+ return 0;
+}
+#endif
+
+/*
+ * SDHC
+ */
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg[] = {
+ { USDHC3_BASE_ADDR, 0, 4 }, /* Micro SD */
+ { USDHC2_BASE_ADDR, 0, 4 }, /* Big SD */
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+ /* There is no CD for a microSD card, assume always present. */
+ if (cfg->esdhc_base == USDHC3_BASE_ADDR)
+ return 1;
+ else
+ return !gpio_get_value(NOVENA_SD_CD);
+}
+
+int board_mmc_getwp(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+ /* There is no WP for a microSD card, assume always read-write. */
+ if (cfg->esdhc_base == USDHC3_BASE_ADDR)
+ return 0;
+ else
+ return gpio_get_value(NOVENA_SD_WP);
+}
+
+
+int board_mmc_init(bd_t *bis)
+{
+ s32 status = 0;
+ int index;
+
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+ /* Big SD write-protect and card-detect */
+ gpio_direction_input(NOVENA_SD_WP);
+ gpio_direction_input(NOVENA_SD_CD);
+
+ for (index = 0; index < ARRAY_SIZE(usdhc_cfg); index++) {
+ status = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ if (status)
+ return status;
+ }
+
+ return status;
+}
+#endif
+
+/*
+ * Video over HDMI
+ */
+#if defined(CONFIG_VIDEO_IPUV3)
+static void enable_hdmi(struct display_info_t const *dev)
+{
+ imx_enable_hdmi_phy();
+}
+
+struct display_info_t const displays[] = {
+ {
+ /* HDMI Output */
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+ }
+ }
+};
+
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ enable_ipu_clock();
+ imx_setup_hdmi();
+
+ /* Turn on LDB0,IPU,IPU DI0 clocks */
+ setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
+
+ /* set LDB0, LDB1 clk select to 011/011 */
+ clrsetbits_le32(&mxc_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
+ MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK,
+ (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
+ (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET));
+
+ setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+
+ setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 <<
+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+
+ writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
+ IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
+ IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
+ IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
+ IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
+ IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+ IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
+ IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
+ IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
+ &iomux->gpr[2]);
+
+ clrsetbits_le32(&iomux->gpr[3], IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
+ IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+ IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+}
+#endif
+
+int board_early_init_f(void)
+{
+#if defined(CONFIG_VIDEO_IPUV3)
+ setup_display();
+#endif
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_CMD_SATA
+ setup_sata();
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: Novena 4x\n");
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+ return 0;
+}
+
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+ struct pmic *p;
+ u32 reg;
+ int ret;
+
+ power_pfuze100_init(1);
+ p = pmic_get("PFUZE100");
+ if (!p)
+ return -EINVAL;
+
+ ret = pmic_probe(p);
+ if (ret)
+ return ret;
+
+ pmic_reg_read(p, PFUZE100_DEVICEID, ®);
+ printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
+
+ /* Set SWBST to 5.0V and enable (for USB) */
+ pmic_reg_read(p, PFUZE100_SWBSTCON1, ®);
+ reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
+ reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
+ pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
+
+ return 0;
+}
+
+/* EEPROM configuration data */
+struct novena_eeprom_data {
+ uint8_t signature[6];
+ uint8_t version;
+ uint8_t reserved;
+ uint32_t serial;
+ uint8_t mac[6];
+ uint16_t features;
+};
+
+int misc_init_r(void)
+{
+ struct novena_eeprom_data data;
+ uchar *datap = (uchar *)&data;
+ const char *signature = "Novena";
+ int ret;
+
+ /* If 'ethaddr' is already set, do nothing. */
+ if (getenv("ethaddr"))
+ return 0;
+
+ /* EEPROM is at bus 2. */
+ ret = i2c_set_bus_num(2);
+ if (ret) {
+ puts("Cannot select EEPROM I2C bus.\n");
+ return 0;
+ }
+
+ /* EEPROM is at address 0x56. */
+ ret = eeprom_read(0x56, 0, datap, sizeof(data));
+ if (ret) {
+ puts("Cannot read I2C EEPROM.\n");
+ return 0;
+ }
+
+ /* Check EEPROM signature. */
+ if (memcmp(data.signature, signature, 6)) {
+ puts("Invalid I2C EEPROM signature.\n");
+ return 0;
+ }
+
+ /* Set ethernet address from EEPROM. */
+ eth_setenv_enetaddr("ethaddr", data.mac);
+
+ return ret;
+}
--- /dev/null
+/*
+ * Novena SPL
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <spl.h>
+
+#include <asm/arch/mx6-ddr.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL \
+ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL \
+ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL \
+ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ENET_PHY_CFG_PAD_CTRL \
+ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_HYS)
+
+#define RGMII_PAD_CTRL \
+ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL \
+ (PAD_CTL_HYS | \
+ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL \
+ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_240ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE)
+
+#define BUTTON_PAD_CTRL \
+ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+#define NOVENA_AUDIO_PWRON IMX_GPIO_NR(5, 17)
+#define NOVENA_FPGA_RESET_N_GPIO IMX_GPIO_NR(5, 7)
+#define NOVENA_HDMI_GHOST_HPD IMX_GPIO_NR(5, 4)
+#define NOVENA_PCIE_RESET_GPIO IMX_GPIO_NR(3, 29)
+#define NOVENA_PCIE_POWER_ON_GPIO IMX_GPIO_NR(7, 12)
+#define NOVENA_PCIE_WAKE_UP_GPIO IMX_GPIO_NR(3, 22)
+#define NOVENA_PCIE_DISABLE_GPIO IMX_GPIO_NR(2, 16)
+
+/*
+ * Audio
+ */
+static iomux_v3_cfg_t audio_pads[] = {
+ /* AUD_PWRON */
+ MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_audio(void)
+{
+ imx_iomux_v3_setup_multiple_pads(audio_pads, ARRAY_SIZE(audio_pads));
+ gpio_direction_output(NOVENA_AUDIO_PWRON, 1);
+}
+
+/*
+ * ENET
+ */
+static iomux_v3_cfg_t enet_pads1[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+ /* pin 35, PHY_AD2 */
+ MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+ /* pin 32, MODE0 */
+ MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+ /* pin 31, MODE1 */
+ MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+ /* pin 28, MODE2 */
+ MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+ /* pin 27, MODE3 */
+ MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+ /* pin 33, CLK125_EN */
+ MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+
+ /* pin 42 PHY nRST */
+ MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t enet_pads2[] = {
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
+
+ /* Assert Ethernet PHY nRST */
+ gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
+
+ /*
+ * Use imx6 internal pull-ups to drive PHY mode pins during PHY reset
+ * de-assertion. The intention is to use weak signal drivers (pull-ups)
+ * to prevent the conflict between PHY pins becoming outputs after
+ * reset and imx6 still driving the pins. The issue is described in PHY
+ * datasheet, p.14
+ */
+ gpio_direction_input(IMX_GPIO_NR(6, 30)); /* PHY_AD2 = 1 */
+ gpio_direction_input(IMX_GPIO_NR(6, 25)); /* MODE0 = 1 */
+ gpio_direction_input(IMX_GPIO_NR(6, 27)); /* MODE1 = 1 */
+ gpio_direction_input(IMX_GPIO_NR(6, 28)); /* MODE2 = 1 */
+ gpio_direction_input(IMX_GPIO_NR(6, 29)); /* MODE3 = 1 */
+ gpio_direction_input(IMX_GPIO_NR(6, 24)); /* CLK125_EN = 1 */
+
+ /* Following reset timing (p.53, fig.8 from the PHY datasheet) */
+ mdelay(10);
+
+ /* De-assert Ethernet PHY nRST */
+ gpio_set_value(IMX_GPIO_NR(3, 23), 1);
+
+ /* PHY is now configured, connect FEC to the pads */
+ imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+
+ /*
+ * PHY datasheet recommends on p.53 to wait at least 100us after reset
+ * before using MII, so we enforce the delay here
+ */
+ udelay(100);
+}
+
+/*
+ * FPGA
+ */
+static iomux_v3_cfg_t fpga_pads[] = {
+ /* FPGA_RESET_N */
+ MX6_PAD_DISP0_DAT13__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_fpga(void)
+{
+ imx_iomux_v3_setup_multiple_pads(fpga_pads, ARRAY_SIZE(fpga_pads));
+ gpio_direction_output(NOVENA_FPGA_RESET_N_GPIO, 0);
+}
+
+/*
+ * GPIO Button
+ */
+static iomux_v3_cfg_t button_pads[] = {
+ /* Debug */
+ MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_buttons(void)
+{
+ imx_iomux_v3_setup_multiple_pads(button_pads, ARRAY_SIZE(button_pads));
+}
+
+/*
+ * I2C
+ */
+/*
+ * I2C1:
+ * 0x1d ... MMA7455L
+ * 0x30 ... SO-DIMM temp sensor
+ * 0x44 ... STMPE610
+ * 0x50 ... SO-DIMM ID
+ */
+struct i2c_pads_info i2c_pad_info0 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
+ .gp = IMX_GPIO_NR(3, 21)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
+ .gp = IMX_GPIO_NR(3, 28)
+ }
+};
+
+/*
+ * I2C2:
+ * 0x08 ... PMIC
+ * 0x3a ... HDMI DCC
+ * 0x50 ... HDMI DCC
+ */
+static struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
+ .gp = IMX_GPIO_NR(2, 30)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
+ .gp = IMX_GPIO_NR(3, 16)
+ }
+};
+
+/*
+ * I2C3:
+ * 0x11 ... ES8283
+ * 0x50 ... LCD EDID
+ * 0x56 ... EEPROM
+ */
+static struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
+ .gp = IMX_GPIO_NR(3, 17)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
+ .gp = IMX_GPIO_NR(3, 18)
+ }
+};
+
+static void novena_spl_setup_iomux_i2c(void)
+{
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+}
+
+/*
+ * PCI express
+ */
+#ifdef CONFIG_CMD_PCI
+static iomux_v3_cfg_t pcie_pads[] = {
+ /* "Reset" pin */
+ MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* "Power on" pin */
+ MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* "Wake up" pin (input) */
+ MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* "Disable endpoint" (rfkill) pin */
+ MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_pcie(void)
+{
+ imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
+
+ /* Ensure PCIe is powered down */
+ gpio_direction_output(NOVENA_PCIE_POWER_ON_GPIO, 0);
+
+ /* Put the card into reset */
+ gpio_direction_output(NOVENA_PCIE_RESET_GPIO, 0);
+
+ /* Input signal to wake system from mPCIe card */
+ gpio_direction_input(NOVENA_PCIE_WAKE_UP_GPIO);
+
+ /* Drive RFKILL high, to ensure the radio is turned on */
+ gpio_direction_output(NOVENA_PCIE_DISABLE_GPIO, 1);
+}
+#else
+static inline void novena_spl_setup_iomux_pcie(void) {}
+#endif
+
+/*
+ * SDHC
+ */
+static iomux_v3_cfg_t usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
+ MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+static iomux_v3_cfg_t usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_sdhc(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+
+ /* Big SD write-protect and card-detect */
+ gpio_direction_input(IMX_GPIO_NR(1, 2));
+ gpio_direction_input(IMX_GPIO_NR(1, 4));
+}
+
+/*
+ * SPI
+ */
+#ifdef CONFIG_MXC_SPI
+static iomux_v3_cfg_t ecspi3_pads[] = {
+ /* SS1 */
+ MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT4__GPIO4_IO25 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT5__GPIO4_IO26 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(SPI_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_spi(void)
+{
+ imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
+ /* De-assert the nCS */
+ gpio_direction_output(MX6_PAD_DISP0_DAT3__GPIO4_IO24, 1);
+ gpio_direction_output(MX6_PAD_DISP0_DAT4__GPIO4_IO25, 1);
+ gpio_direction_output(MX6_PAD_DISP0_DAT5__GPIO4_IO26, 1);
+}
+#else
+static void novena_spl_setup_iomux_spi(void) {}
+#endif
+
+/*
+ * UART
+ */
+static iomux_v3_cfg_t const uart2_pads[] = {
+ MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart3_pads[] = {
+ MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+ MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+
+};
+
+static void novena_spl_setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+ imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
+ imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+}
+
+/*
+ * Video
+ */
+#ifdef CONFIG_VIDEO
+static iomux_v3_cfg_t hdmi_pads[] = {
+ /* "Ghost HPD" pin */
+ MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_video(void)
+{
+ imx_iomux_v3_setup_multiple_pads(hdmi_pads, ARRAY_SIZE(hdmi_pads));
+ gpio_direction_input(NOVENA_HDMI_GHOST_HPD);
+}
+#else
+static inline void novena_spl_setup_iomux_video(void) {}
+#endif
+
+/*
+ * SPL boots from uSDHC card
+ */
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg = {
+ USDHC3_BASE_ADDR, 0, 4
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ /* There is no CD for a microSD card, assume always present. */
+ return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ return fsl_esdhc_initialize(bis, &usdhc_cfg);
+}
+#endif
+
+/* Configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs novena_ddr_ioregs = {
+ /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
+ .dram_sdclk_0 = 0x00020038,
+ .dram_sdclk_1 = 0x00020038,
+ .dram_cas = 0x00000038,
+ .dram_ras = 0x00000038,
+ .dram_reset = 0x00000038,
+ /* SDCKE[0:1]: 100k pull-up */
+ .dram_sdcke0 = 0x00003000,
+ .dram_sdcke1 = 0x00003000,
+ /* SDBA2: pull-up disabled */
+ .dram_sdba2 = 0x00000000,
+ /* SDODT[0:1]: 100k pull-up, 40 ohm */
+ .dram_sdodt0 = 0x00000038,
+ .dram_sdodt1 = 0x00000038,
+ /* SDQS[0:7]: Differential input, 40 ohm */
+ .dram_sdqs0 = 0x00000038,
+ .dram_sdqs1 = 0x00000038,
+ .dram_sdqs2 = 0x00000038,
+ .dram_sdqs3 = 0x00000038,
+ .dram_sdqs4 = 0x00000038,
+ .dram_sdqs5 = 0x00000038,
+ .dram_sdqs6 = 0x00000038,
+ .dram_sdqs7 = 0x00000038,
+
+ /* DQM[0:7]: Differential input, 40 ohm */
+ .dram_dqm0 = 0x00000038,
+ .dram_dqm1 = 0x00000038,
+ .dram_dqm2 = 0x00000038,
+ .dram_dqm3 = 0x00000038,
+ .dram_dqm4 = 0x00000038,
+ .dram_dqm5 = 0x00000038,
+ .dram_dqm6 = 0x00000038,
+ .dram_dqm7 = 0x00000038,
+};
+
+/* Configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs novena_grp_ioregs = {
+ /* DDR3 */
+ .grp_ddr_type = 0x000c0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ /* Disable DDR pullups */
+ .grp_ddrpke = 0x00000000,
+ /* ADDR[00:16], SDBA[0:1]: 40 ohm */
+ .grp_addds = 0x00000038,
+ /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
+ .grp_ctlds = 0x00000038,
+ /* DATA[00:63]: Differential input, 40 ohm */
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = 0x00000038,
+ .grp_b1ds = 0x00000038,
+ .grp_b2ds = 0x00000038,
+ .grp_b3ds = 0x00000038,
+ .grp_b4ds = 0x00000038,
+ .grp_b5ds = 0x00000038,
+ .grp_b6ds = 0x00000038,
+ .grp_b7ds = 0x00000038,
+};
+
+static struct mx6_mmdc_calibration novena_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x00420048,
+ .p0_mpwldectrl1 = 0x006f0059,
+ .p1_mpwldectrl0 = 0x005a0104,
+ .p1_mpwldectrl1 = 0x01070113,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x437c040b,
+ .p0_mpdgctrl1 = 0x0413040e,
+ .p1_mpdgctrl0 = 0x444f0446,
+ .p1_mpdgctrl1 = 0x044d0422,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x4c424249,
+ .p1_mprddlctl = 0x4e48414f,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x42414641,
+ .p1_mpwrdlctl = 0x46374b43,
+};
+
+static struct mx6_ddr_sysinfo novena_ddr_info = {
+ /* Width of data bus: 0=16, 1=32, 2=64 */
+ .dsize = 2,
+ /* Config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32, /* 32Gb per CS */
+ /* Single chip select */
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 1, /* RTT_Wr = RZQ/4 */
+ .rtt_nom = 2, /* RTT_Nom = RZQ/2 */
+ .walat = 3, /* Write additional latency */
+ .ralat = 7, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+};
+
+static struct mx6_ddr3_cfg elpida_4gib_1600 = {
+ .mem_speed = 1600,
+ .density = 4,
+ .width = 64,
+ .banks = 8,
+ .rowaddr = 16,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1300,
+ .trcmin = 4900,
+ .trasmin = 3590,
+};
+
+/*
+ * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
+ * - we have a stack and a place to store GD, both in SRAM
+ * - no variable global data is available
+ */
+void board_init_f(ulong dummy)
+{
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ /* setup GP timer */
+ timer_init();
+
+#ifdef CONFIG_BOARD_POSTCLK_INIT
+ board_postclk_init();
+#endif
+#ifdef CONFIG_FSL_ESDHC
+ get_clocks();
+#endif
+
+ /* Setup IOMUX and configure basics. */
+ novena_spl_setup_iomux_audio();
+ novena_spl_setup_iomux_buttons();
+ novena_spl_setup_iomux_enet();
+ novena_spl_setup_iomux_fpga();
+ novena_spl_setup_iomux_i2c();
+ novena_spl_setup_iomux_pcie();
+ novena_spl_setup_iomux_sdhc();
+ novena_spl_setup_iomux_spi();
+ novena_spl_setup_iomux_uart();
+ novena_spl_setup_iomux_video();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* Start the DDR DRAM */
+ mx6dq_dram_iocfg(64, &novena_ddr_ioregs, &novena_grp_ioregs);
+ mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &elpida_4gib_1600);
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+
+void reset_cpu(ulong addr)
+{
+}
--- /dev/null
+/*
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/* Boot Device : sd */
+BOOT_FROM sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en = 1 --> CKO1 enabled
+ * cko1_div = 111 --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4, CCM_CCOSR, 0x000000fb
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
/* JTAG */\
- MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
if TARGET_IMX27LITE
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "imx27lite"
if TARGET_MAGNESIUM
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "imx27lite"
if TARGET_IMX31_LITEKIT
-config SYS_CPU
- default "arm1136"
-
config SYS_BOARD
default "imx31_litekit"
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0));
- MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
}
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
#include <netdev.h>
#include <twl4030.h>
#include <asm/io.h>
/*CONF7- computed as params */
};
+static const struct ns16550_platdata zoom1_serial = {
+ OMAP34XX_UART3,
+ 2,
+ V_NS16550_CLK
+};
+
+U_BOOT_DEVICE(zoom1_uart) = {
+ "serial_omap",
+ &zoom1_serial
+};
+
/*
* Routine: board_init
* Description: Early hardware init.
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = mv_common.o
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <environment.h>
-#include <fpga.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_ENV_IS_NOWHERE
-static char* entries_to_keep[] = {
- "serial#", "ethaddr", "eth1addr", "model_info", "sensor_cnt",
- "fpgadatasize", "ddr_size", "use_dhcp", "use_static_ipaddr",
- "static_ipaddr", "static_netmask", "static_gateway",
- "syslog", "watchdog", "netboot", "evo8serialnumber" };
-
-#define MV_MAX_ENV_ENTRY_LENGTH 64
-#define MV_KEEP_ENTRIES ARRAY_SIZE(entries_to_keep)
-
-void mv_reset_environment(void)
-{
- int i;
- char *s[MV_KEEP_ENTRIES];
- char entries[MV_KEEP_ENTRIES][MV_MAX_ENV_ENTRY_LENGTH];
-
- printf("\n*** RESET ENVIRONMENT ***\n");
-
- memset(entries, 0, MV_KEEP_ENTRIES * MV_MAX_ENV_ENTRY_LENGTH);
- for (i = 0; i < MV_KEEP_ENTRIES; i++) {
- s[i] = getenv(entries_to_keep[i]);
- if (s[i]) {
- printf("save '%s' : %s\n", entries_to_keep[i], s[i]);
- strncpy(entries[i], s[i], MV_MAX_ENV_ENTRY_LENGTH);
- }
- }
-
- gd->env_valid = 0;
- env_relocate();
-
- for (i = 0; i < MV_KEEP_ENTRIES; i++) {
- if (s[i]) {
- printf("restore '%s' : %s\n", entries_to_keep[i], s[i]);
- setenv(entries_to_keep[i], s[i]);
- }
- }
-
- saveenv();
-}
-#endif
-
-int mv_load_fpga(void)
-{
- int result;
- size_t data_size = 0;
- void *fpga_data = NULL;
- char *datastr = getenv("fpgadata");
- char *sizestr = getenv("fpgadatasize");
-
- if (getenv("skip_fpga")) {
- printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
- return -1;
- }
- printf("loading FPGA\n");
-
- if (datastr)
- fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
- if (sizestr)
- data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
- if (!data_size) {
- printf("fpgadatasize invalid -> FPGA _not_ loaded !\n");
- return -1;
- }
-
- result = fpga_load(0, fpga_data, data_size, BIT_FULL);
- if (!result)
- bootstage_mark(BOOTSTAGE_ID_START);
-
- return result;
-}
-
-u8 *dhcp_vendorex_prep(u8 *e)
-{
- char *ptr;
-
- /* DHCP vendor-class-identifier = 60 */
- if ((ptr = getenv("dhcp_vendor-class-identifier"))) {
- *e++ = 60;
- *e++ = strlen(ptr);
- while (*ptr)
- *e++ = *ptr++;
- }
- /* DHCP_CLIENT_IDENTIFIER = 61 */
- if ((ptr = getenv("dhcp_client_id"))) {
- *e++ = 61;
- *e++ = strlen(ptr);
- while (*ptr)
- *e++ = *ptr++;
- }
-
- return e;
-}
-
-u8 *dhcp_vendorex_proc(u8 *popt)
-{
- return NULL;
-}
+++ /dev/null
-/*
- * Copyright 2008 Matrix Vision GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-extern int mv_load_fpga(void);
-extern void mv_reset_environment(void);
if (memcmp(&e.mac, "\0\0\0\0\0\0", 6) &&
memcmp(&e.mac, "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
- char ethaddr[9];
+ char ethaddr[18];
sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
e.mac[0],
--- /dev/null
+--------
+WARNING:
+--------
+This file should contain the bin_hdr generated by the original Marvell
+U-Boot implementation. As this is currently not included in this
+U-Boot version, we have added this placeholder, so that the U-Boot
+image can be generated without errors.
+
+If you have a known to be working bin_hdr for your board, then you
+just need to replace this text file here with the binary header
+and recompile U-Boot.
+
+In a few weeks, mainline U-Boot will get support to generate the
+bin_hdr with the DDR training code itself. By implementing this code
+as SPL U-Boot. Then this file will not be needed any more and will
+get removed.
+
if TARGET_VCT
-config SYS_CPU
- default "mips32"
-
config SYS_BOARD
default "vct"
config SYS_CONFIG_NAME
default "vct"
+menu "vct board options"
+
+choice
+ prompt "Board variant"
+
+config VCT_PLATINUM
+ bool "Enable VCT_PLATINUM"
+
+config VCT_PLATINUMAVC
+ bool "Enable VCT_PLATINUMAVC"
+
+config VCT_PREMIUM
+ bool "Enable VCT_PLATINUMAVC"
+
+endchoice
+
+config VCT_ONENAND
+ bool "Enable VCT_ONENAND"
+
+config VCT_SMALL_IMAGE
+ bool "Enable VCT_SMALL_IMAGE"
+
+endmenu
+
endif
if TARGET_VCMA9
-config SYS_CPU
- default "arm920t"
-
config SYS_BOARD
default "vcma9"
CONFIG_TEGRA_BOARD_STRING
};
-void __pinmux_init(void)
-{
-}
-
-void pinmux_init(void) __attribute__((weak, alias("__pinmux_init")));
-
-void __pin_mux_usb(void)
-{
-}
-
-void pin_mux_usb(void) __attribute__((weak, alias("__pin_mux_usb")));
-
-void __pin_mux_spi(void)
-{
-}
-
-void pin_mux_spi(void) __attribute__((weak, alias("__pin_mux_spi")));
-
-void __gpio_early_init_uart(void)
-{
-}
-
-void gpio_early_init_uart(void)
-__attribute__((weak, alias("__gpio_early_init_uart")));
+__weak void pinmux_init(void) {}
+__weak void pin_mux_usb(void) {}
+__weak void pin_mux_spi(void) {}
+__weak void gpio_early_init_uart(void) {}
+__weak void pin_mux_display(void) {}
#if defined(CONFIG_TEGRA_NAND)
-void __pin_mux_nand(void)
+__weak void pin_mux_nand(void)
{
funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
}
-
-void pin_mux_nand(void) __attribute__((weak, alias("__pin_mux_nand")));
#endif
-void __pin_mux_display(void)
-{
-}
-
-void pin_mux_display(void) __attribute__((weak, alias("__pin_mux_display")));
-
/*
* Routine: power_det_init
* Description: turn off power detects
}
#if defined(CONFIG_TEGRA_MMC)
-void __pin_mux_mmc(void)
+__weak void pin_mux_mmc(void)
{
}
-void pin_mux_mmc(void) __attribute__((weak, alias("__pin_mux_mmc")));
-
/* this is a weak define that we are overriding */
int board_mmc_init(bd_t *bd)
{
*/
#include <common.h>
+#include "emc.h"
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/emc.h>
#include <common.h>
#include <asm/io.h>
#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/board.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/gpio.h>
if TARGET_MX23_OLINUXINO
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "mx23_olinuxino"
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
#include <netdev.h>
#include <twl4030.h>
#include <linux/mtd/nand.h>
#include <asm/mach-types.h>
#include "overo.h"
+#ifdef CONFIG_USB_EHCI
+#include <usb.h>
+#include <asm/ehci-omap.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
#define TWL4030_I2C_BUS 0
#define EXPANSION_EEPROM_I2C_BUS 2
#define EXPANSION_EEPROM_I2C_ADDRESS 0x51
+#define GUMSTIX_EMPTY_EEPROM 0x0
+
#define GUMSTIX_SUMMIT 0x01000200
#define GUMSTIX_TOBI 0x02000200
#define GUMSTIX_TOBI_DUO 0x03000200
char fab_revision[8];
char env_var[16];
char env_setting[64];
-} expansion_config;
+} expansion_config = {0x0};
-#if defined(CONFIG_CMD_NET)
-static void setup_net_chip(void);
-#endif
+static const struct ns16550_platdata overo_serial = {
+ OMAP34XX_UART3,
+ 2,
+ V_NS16550_CLK
+};
-/* GPMC definitions for LAN9221 chips on Tobi expansion boards */
-static const u32 gpmc_lan_config[] = {
- NET_LAN9221_GPMC_CONFIG1,
- NET_LAN9221_GPMC_CONFIG2,
- NET_LAN9221_GPMC_CONFIG3,
- NET_LAN9221_GPMC_CONFIG4,
- NET_LAN9221_GPMC_CONFIG5,
- NET_LAN9221_GPMC_CONFIG6,
- /*CONFIG7- computed as params */
+U_BOOT_DEVICE(overo_uart) = {
+ "serial_omap",
+ &overo_serial
};
/*
*/
unsigned int get_expansion_id(void)
{
+ if (expansion_config.device_vendor != 0x0)
+ return expansion_config.device_vendor;
+
i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
/* return GUMSTIX_NO_EEPROM if eeprom doesn't respond */
twl4030_power_init();
twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
-#if defined(CONFIG_CMD_NET)
- setup_net_chip();
-#endif
-
printf("Board revision: %d\n", get_board_revision());
switch (get_sdio2_config()) {
printf("Recognized Summit expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
+ MUX_GUMSTIX();
setenv("defaultdisplay", "dvi");
setenv("expansionname", "summit");
break;
printf("Recognized Tobi expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
+ MUX_GUMSTIX();
setenv("defaultdisplay", "dvi");
setenv("expansionname", "tobi");
break;
printf("Recognized Tobi Duo expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
- /* second lan chip */
- enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4],
- 0x2B000000, GPMC_SIZE_16M);
+ MUX_GUMSTIX();
break;
case GUMSTIX_PALO35:
printf("Recognized Palo35 expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
+ MUX_GUMSTIX();
setenv("defaultdisplay", "lcd35");
break;
case GUMSTIX_PALO43:
printf("Recognized Palo43 expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
+ MUX_GUMSTIX();
setenv("defaultdisplay", "lcd43");
setenv("expansionname", "palo43");
break;
printf("Recognized Chestnut43 expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
+ MUX_GUMSTIX();
setenv("defaultdisplay", "lcd43");
setenv("expansionname", "chestnut43");
break;
printf("Recognized Pinto expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
+ MUX_GUMSTIX();
break;
case GUMSTIX_GALLOP43:
printf("Recognized Gallop43 expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
+ MUX_GUMSTIX();
setenv("defaultdisplay", "lcd43");
setenv("expansionname", "gallop43");
break;
printf("Recognized Alto35 expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
+ MUX_GUMSTIX();
MUX_ALTO35();
setenv("defaultdisplay", "lcd35");
setenv("expansionname", "alto35");
printf("Recognized Stagecoach expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
+ MUX_GUMSTIX();
break;
case GUMSTIX_THUMBO:
printf("Recognized Thumbo expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
+ MUX_GUMSTIX();
break;
case GUMSTIX_TURTLECORE:
printf("Recognized Turtlecore expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
+ MUX_GUMSTIX();
break;
case GUMSTIX_ARBOR43C:
printf("Recognized Arbor43C expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
+ MUX_GUMSTIX();
MUX_ARBOR43C();
setenv("defaultdisplay", "lcd43");
break;
printf("Recognized Ettus Research USRP-E (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
+ MUX_GUMSTIX();
MUX_USRP_E();
setenv("defaultdisplay", "dvi");
break;
case GUMSTIX_NO_EEPROM:
- puts("No EEPROM on expansion board\n");
+ case GUMSTIX_EMPTY_EEPROM:
+ puts("No or empty EEPROM on expansion board\n");
+ MUX_GUMSTIX();
setenv("expansionname", "tobi");
break;
default:
- if (expansion_id == 0x0)
- setenv("expansionname", "tobi");
printf("Unrecognized expansion board 0x%08x\n", expansion_id);
break;
}
MUX_OVERO();
}
-#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SPL_BUILD)
+/* GPMC definitions for LAN9221 chips on Tobi expansion boards */
+static const u32 gpmc_lan_config[] = {
+ NET_LAN9221_GPMC_CONFIG1,
+ NET_LAN9221_GPMC_CONFIG2,
+ NET_LAN9221_GPMC_CONFIG3,
+ NET_LAN9221_GPMC_CONFIG4,
+ NET_LAN9221_GPMC_CONFIG5,
+ NET_LAN9221_GPMC_CONFIG6,
+ /*CONFIG7- computed as params */
+};
+
/*
* Routine: setup_net_chip
* Description: Setting up the configuration GPMC registers specific to the
{
struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
- /* first lan chip */
- enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
- GPMC_SIZE_16M);
-
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
&ctrl_base->gpmc_nadv_ale);
+}
+/*
+ * Routine: reset_net_chip
+ * Description: Reset the Ethernet hardware.
+ */
+static void reset_net_chip(void)
+{
/* Make GPIO 64 as output pin and send a magic pulse through it */
if (!gpio_request(64, "")) {
gpio_direction_output(64, 0);
gpio_set_value(64, 1);
}
}
-#endif
int board_eth_init(bd_t *bis)
{
+ unsigned int expansion_id;
int rc = 0;
+
#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+ expansion_id = get_expansion_id();
+ switch (expansion_id) {
+ case GUMSTIX_TOBI_DUO:
+ /* second lan chip */
+ enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4],
+ 0x2B000000, GPMC_SIZE_16M);
+ /* no break */
+ case GUMSTIX_TOBI:
+ case GUMSTIX_CHESTNUT43:
+ case GUMSTIX_STAGECOACH:
+ case GUMSTIX_NO_EEPROM:
+ case GUMSTIX_EMPTY_EEPROM:
+ /* first lan chip */
+ enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
+ 0x2C000000, GPMC_SIZE_16M);
+
+ setup_net_chip();
+ reset_net_chip();
+
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+ break;
+ default:
+ break;
+ }
#endif
+
return rc;
}
+#endif
#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
+
+#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
+static struct omap_usbhs_board_data usbhs_bdata = {
+ .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
+ .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
+};
+
+#define GUMSTIX_GPIO_USBH_CPEN 168
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ /* Enable USB power */
+ if (!gpio_request(GUMSTIX_GPIO_USBH_CPEN, "usbh_cpen"))
+ gpio_direction_output(GUMSTIX_GPIO_USBH_CPEN, 1);
+
+ return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
+}
+
+int ehci_hcd_stop(void)
+{
+ /* Disable USB power */
+ gpio_set_value(GUMSTIX_GPIO_USBH_CPEN, 0);
+ gpio_free(GUMSTIX_GPIO_USBH_CPEN);
+
+ return omap_ehci_hcd_stop();
+}
+
+#endif /* CONFIG_USB_EHCI */
MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO_54*/\
/* - MMC1_WP*/\
- MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/\
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nCS3*/\
MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M0)) /*GPMC_CLK*/\
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
- /* - SMSC911X_NRES*/\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | DIS | M4)) /*GPIO_65*/\
- /*DSS*/\
- MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
- MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
- MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
- MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
- MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
- MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
- MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
- MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
- MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
- MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
- MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
- MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
- MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
- MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
- MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
- MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
- MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
- MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
- MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
- MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
/*CAMERA*/\
MUX_VAL(CP(CAM_HS), (IEN | PTU | DIS | M0)) /*CAM_HS */\
MUX_VAL(CP(CAM_VS), (IEN | PTU | DIS | M0)) /*CAM_VS */\
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
MUX_VAL(CP(CAM_PCLK), (IEN | PTU | DIS | M0)) /*CAM_PCLK*/\
- MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*CAM_FLD*/\
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
- MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M0)) /*CAM_WEN*/\
- MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) /*GPIO_112*/\
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) /*GPIO_113*/\
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\
- /* - PEN_DOWN*/\
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) /*GPIO_115*/\
/*Audio Interface */\
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
- MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\
- MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
- MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
- MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
MUX_VAL(CP(UART1_RTS), (IEN | PTU | DIS | M4)) /*GPIO_149*/ \
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M0)) /*McBSP4_CLKX*/\
MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M0)) /*McBSP4_DR*/\
MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M0)) /*McBSP4_DX*/\
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) /*McBSP1_FSX*/\
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) /*McBSP1_CLKX*/\
/*Serial Interface*/\
- MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
MUX_VAL(CP(UART3_RTS_SD), (IEN | PTU | EN | M4)) /*GPIO_164 W2W_*/\
/* BT_NRESET*/\
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTU | EN | M0)) /*UART3_RX_IRRX*/\
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
- MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\
- MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\
- MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\
- MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
- MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
- MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176 */\
- /* - LAN_INTR */\
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA2*/\
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA7*/\
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA4*/\
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10*/\
- MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
- MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M2)) /*MMC3_CLK*/\
- MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\
- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M4)) /*GPIO_14*/\
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M4)) /*GPIO_15 - X_GATE*/\
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M4)) /*GPIO_16*/\
/* - W2W_NRESET*/\
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M4)) /*GPIO_21*/\
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M4)) /*GPIO_22*/\
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M4)) /*GPIO_23*/\
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DIR*/\
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
+#define MUX_GUMSTIX() \
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) /*GPIO_63*/\
+ /* - CAM_IRQ*/\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
+ /* - SMSC911X_NRES*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | DIS | M4)) /*GPIO_65*/\
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+ /*CAMERA*/\
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*CAM_FLD*/\
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M0)) /*CAM_WEN*/\
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\
+ /* - PEN_DOWN*/\
+ /*Bluetooth*/\
+ MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\
+ MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
+ MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
+ /*Serial Interface*/\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
+ MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
+ MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176 */\
+ /* - LAN_INTR */\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
+ MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M2)) /*MMC3_CLK*/\
+ MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M4)) /*GPIO_14*/\
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M4)) /*GPIO_21*/\
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M4)) /*GPIO_22*/\
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M4)) /*GPIO_23*/\
+
#define MUX_OVERO_SDIO2_DIRECT() \
MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
if TARGET_PALMLD
-config SYS_CPU
- default "pxa"
-
config SYS_BOARD
default "palmld"
if TARGET_PALMTC
-config SYS_CPU
- default "pxa"
-
config SYS_BOARD
default "palmtc"
if TARGET_PALMTREO680
-config SYS_CPU
- default "pxa"
-
config SYS_BOARD
default "palmtreo680"
MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8*/\
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
/*JTAG*/\
- MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /*JTAG_NTRST*/\
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
if TARGET_PB1X00
-config SYS_CPU
- default "mips32"
-
config SYS_BOARD
default "pb1x00"
if TARGET_PCM051
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "pcm051"
if TARGET_BG0900
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "bg0900"
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * main board support/init for the Galileo Eval board DB64460.
- */
-
-#ifndef __64460_H__
-#define __64460_H__
-
-/* CPU Configuration bits */
-#define CPU_CONF_ADDR_MISS_EN (1 << 8)
-#define CPU_CONF_SINGLE_CPU (1 << 11)
-#define CPU_CONF_ENDIANESS (1 << 12)
-#define CPU_CONF_PIPELINE (1 << 13)
-#define CPU_CONF_STOP_RETRY (1 << 17)
-#define CPU_CONF_MULTI_DECODE (1 << 18)
-#define CPU_CONF_DP_VALID (1 << 19)
-#define CPU_CONF_PERR_PROP (1 << 22)
-#define CPU_CONF_AACK_DELAY_2 (1 << 25)
-#define CPU_CONF_AP_VALID (1 << 26)
-#define CPU_CONF_REMAP_WR_DIS (1 << 27)
-
-/* CPU Master Control bits */
-#define CPU_MAST_CTL_ARB_EN (1 << 8)
-#define CPU_MAST_CTL_MASK_BR_1 (1 << 9)
-#define CPU_MAST_CTL_M_WR_TRIG (1 << 10)
-#define CPU_MAST_CTL_M_RD_TRIG (1 << 11)
-#define CPU_MAST_CTL_CLEAN_BLK (1 << 12)
-#define CPU_MAST_CTL_FLUSH_BLK (1 << 13)
-
-#endif /* __64460_H__ */
+++ /dev/null
-if TARGET_P3MX
-
-config SYS_BOARD
- default "p3mx"
-
-config SYS_VENDOR
- default "prodrive"
-
-config SYS_CONFIG_NAME
- default "p3mx"
-
-endif
+++ /dev/null
-P3MX BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/prodrive/p3mx/
-F: include/configs/p3mx.h
-F: configs/p3m7448_defconfig
-F: configs/p3m750_defconfig
+++ /dev/null
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = misc.o
-obj-y += p3mx.o mpsc.o mv_eth.o pci.o sdram_init.o serial.o \
- ../../Marvell/common/i2c.o ../../Marvell/common/memory.o
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * eth.h - header file for the polled mode GT ethernet driver
- */
-
-#ifndef __EVB64360_ETH_H__
-#define __EVB64360_ETH_H__
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-#include <common.h>
-
-
-int db64360_eth0_poll(void);
-int db64360_eth0_transmit(unsigned int s, volatile char *p);
-void db64360_eth0_disable(void);
-bool network_start(bd_t *bis);
-
-int mv6446x_eth_initialize(bd_t *);
-
-#endif /* __EVB64360_ETH_H__ */
+++ /dev/null
-#include <config.h>
-#include <74xx_7xx.h>
-#include "version.h"
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#include "../../Marvell/include/mv_gen_reg.h"
-
-#ifdef CONFIG_ECC
- /* Galileo specific asm code for initializing ECC */
- .globl board_relocate_rom
-board_relocate_rom:
- mflr r7
- /* update the location of the GT registers */
- lis r11, CONFIG_SYS_GT_REGS@h
- /* if we're using ECC, we must use the DMA engine to copy ourselves */
- bl start_idma_transfer_0
- bl wait_for_idma_0
- bl stop_idma_engine_0
-
- mtlr r7
- blr
-
- .globl board_init_ecc
-board_init_ecc:
- mflr r7
- /* NOTE: r10 still contains the location we've been relocated to
- * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
-
- /* now that we're running from ram, init the rest of main memory
- * for ECC use */
- lis r8, CONFIG_SYS_MONITOR_LEN@h
- ori r8, r8, CONFIG_SYS_MONITOR_LEN@l
-
- divw r3, r10, r8
-
- /* set up the counter, and init the starting address */
- mtctr r3
- li r12, 0
-
- /* bytes per transfer */
- mr r5, r8
-about_to_init_ecc:
-1: mr r3, r12
- mr r4, r12
- bl start_idma_transfer_0
- bl wait_for_idma_0
- bl stop_idma_engine_0
- add r12, r12, r8
- bdnz 1b
-
- mtlr r7
- blr
-
- /* r3: dest addr
- * r4: source addr
- * r5: byte count
- * r11: gt regbase
- * trashes: r6, r5
- */
-start_idma_transfer_0:
- /* set the byte count, including the OWN bit */
- mr r6, r11
- ori r6, r6, CHANNEL0_DMA_BYTE_COUNT
- stwbrx r5, 0, (r6)
-
- /* set the source address */
- mr r6, r11
- ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
- stwbrx r4, 0, (r6)
-
- /* set the dest address */
- mr r6, r11
- ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
- stwbrx r3, 0, (r6)
-
- /* set the next record pointer */
- li r5, 0
- mr r6, r11
- ori r6, r6, CHANNEL0NEXT_RECORD_POINTER
- stwbrx r5, 0, (r6)
-
- /* set the low control register */
- /* bit 9 is NON chained mode, bit 31 is new style descriptors.
- bit 12 is channel enable */
- ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
- /* 15 shifted by 16 (oris) == bit 31 */
- oris r5, r5, (1 << 15)
- mr r6, r11
- ori r6, r6, CHANNEL0CONTROL
- stwbrx r5, 0, (r6)
-
- blr
-
- /* this waits for the bytecount to return to zero, indicating
- * that the trasfer is complete */
-wait_for_idma_0:
- mr r5, r11
- lis r6, 0xff
- ori r6, r6, 0xffff
- ori r5, r5, CHANNEL0_DMA_BYTE_COUNT
-1: lwbrx r4, 0, (r5)
- and. r4, r4, r6
- bne 1b
-
- blr
-
- /* this turns off channel 0 of the idma engine */
-stop_idma_engine_0:
- /* shut off the DMA engine */
- li r5, 0
- mr r6, r11
- ori r6, r6, CHANNEL0CONTROL
- stwbrx r5, 0, (r6)
-
- blr
-#endif
-
-#ifdef CONFIG_SYS_BOARD_ASM_INIT
- /* NOTE: trashes r3-r7 */
- .globl board_asm_init
-board_asm_init:
- /* just move the GT registers to where they belong */
- lis r3, CONFIG_SYS_DFL_GT_REGS@h
- ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l
- lis r4, CONFIG_SYS_GT_REGS@h
- ori r4, r4, CONFIG_SYS_GT_REGS@l
- li r5, INTERNAL_SPACE_DECODE
-
- /* test to see if we've already moved */
- lwbrx r6, r5, r4
- andi. r6, r6, 0xffff
- /* check loading of R7 is: 0x0F80 should: 0xf800: DONE */
-/* rlwinm r7, r4, 8, 16, 31
- rlwinm r7, r4, 12, 16, 31 */ /* original */
- rlwinm r7, r4, 16, 16, 31
- /* -----------------------------------------------------*/
- cmp cr0, r7, r6
- beqlr
-
- /* nope, have to move the registers */
- lwbrx r6, r5, r3
- andis. r6, r6, 0xffff
- or r6, r6, r7
- stwbrx r6, r5, r3
-
- /* now, poll for the change */
-1: lwbrx r7, r5, r4
- cmp cr0, r7, r6
- bne 1b
-
- lis r3, CONFIG_SYS_INT_SRAM_BASE@h
- ori r3, r3, CONFIG_SYS_INT_SRAM_BASE@l
- rlwinm r3, r3, 16, 16, 31
- lis r4, CONFIG_SYS_GT_REGS@h
- ori r4, r4, CONFIG_SYS_GT_REGS@l
- li r5, INTEGRATED_SRAM_BASE_ADDR
- stwbrx r3, r5, r4
-
-2: lwbrx r6, r5, r4
- cmp cr0, r3, r6
- bne 2b
-
- /* done! */
- blr
-#endif
-
-/* For use of the debug LEDs */
- .global led_on0_relocated
-led_on0_relocated:
- xor r21, r21, r21
- xor r18, r18, r18
- lis r18, 0xFC80
- ori r18, r18, 0x8000
-/* stw r21, 0x0(r18) */
- sync
- blr
-
- .global led_off0_relocated
-led_off0_relocated:
- xor r21, r21, r21
- xor r18, r18, r18
- lis r18, 0xFC81
- ori r18, r18, 0x4000
-/* stw r21, 0x0(r18) */
- sync
- blr
-
- .global led_on0
-led_on0:
- xor r18, r18, r18
- lis r18, 0x1c80
- ori r18, r18, 0x8000
-/* stw r18, 0x0(r18) */
- sync
- blr
-
- .global led_off0
-led_off0:
- xor r18, r18, r18
- lis r18, 0x1c81
- ori r18, r18, 0x4000
-/* stw r18, 0x0(r18) */
- sync
- blr
-
- .global led_on1
-led_on1:
- xor r18, r18, r18
- lis r18, 0x1c80
- ori r18, r18, 0xc000
-/* stw r18, 0x0(r18) */
- sync
- blr
-
- .global led_off1
-led_off1:
- xor r18, r18, r18
- lis r18, 0x1c81
- ori r18, r18, 0x8000
-/* stw r18, 0x0(r18) */
- sync
- blr
-
- .global led_on2
-led_on2:
- xor r18, r18, r18
- lis r18, 0x1c81
- ori r18, r18, 0x0000
-/* stw r18, 0x0(r18) */
- sync
- blr
-
- .global led_off2
-led_off2:
- xor r18, r18, r18
- lis r18, 0x1c81
- ori r18, r18, 0xc000
-/* stw r18, 0x0(r18) */
- sync
- blr
+++ /dev/null
-/*
- * (C) Copyright 2001
- * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*************************************************************************
- * changes for Marvell DB64460 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
- *
- ************************************************************************/
-
-/*
- * mpsc.c - driver for console over the MPSC.
- */
-
-
-#include <common.h>
-#include <config.h>
-#include <asm/cache.h>
-
-#include <malloc.h>
-#include "mpsc.h"
-
-#include "mv_regs.h"
-
-#include "../../Marvell/include/memory.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Define this if you wish to use the MPSC as a register based UART.
- * This will force the serial port to not use the SDMA engine at all.
- */
-#undef CONFIG_MPSC_DEBUG_PORT
-
-
-int (*mpsc_putchar) (char ch) = mpsc_putchar_early;
-char (*mpsc_getchar) (void) = mpsc_getchar_debug;
-int (*mpsc_test_char) (void) = mpsc_test_char_debug;
-
-
-static volatile unsigned int *rx_desc_base = NULL;
-static unsigned int rx_desc_index = 0;
-static volatile unsigned int *tx_desc_base = NULL;
-static unsigned int tx_desc_index = 0;
-
-/* local function declarations */
-static int galmpsc_connect (int channel, int connect);
-static int galmpsc_route_rx_clock (int channel, int brg);
-static int galmpsc_route_tx_clock (int channel, int brg);
-static int galmpsc_write_config_regs (int mpsc, int mode);
-static int galmpsc_config_channel_regs (int mpsc);
-static int galmpsc_set_char_length (int mpsc, int value);
-static int galmpsc_set_stop_bit_length (int mpsc, int value);
-static int galmpsc_set_parity (int mpsc, int value);
-static int galmpsc_enter_hunt (int mpsc);
-static int galmpsc_set_brkcnt (int mpsc, int value);
-static int galmpsc_set_tcschar (int mpsc, int value);
-static int galmpsc_set_snoop (int mpsc, int value);
-static int galmpsc_shutdown (int mpsc);
-
-static int galsdma_set_RFT (int channel);
-static int galsdma_set_SFM (int channel);
-static int galsdma_set_rxle (int channel);
-static int galsdma_set_txle (int channel);
-static int galsdma_set_burstsize (int channel, unsigned int value);
-static int galsdma_set_RC (int channel, unsigned int value);
-
-static int galbrg_set_CDV (int channel, int value);
-static int galbrg_enable (int channel);
-static int galbrg_disable (int channel);
-static int galbrg_set_clksrc (int channel, int value);
-static int galbrg_set_CUV (int channel, int value);
-
-static void galsdma_enable_rx (void);
-static int galsdma_set_mem_space (unsigned int memSpace,
- unsigned int memSpaceTarget,
- unsigned int memSpaceAttr,
- unsigned int baseAddress,
- unsigned int size);
-
-
-#define SOFTWARE_CACHE_MANAGEMENT
-
-#ifdef SOFTWARE_CACHE_MANAGEMENT
-#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
-#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
-#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
-#else
-#define FLUSH_DCACHE(a,b)
-#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
-#define INVALIDATE_DCACHE(a,b)
-#endif
-
-#ifdef CONFIG_MPSC_DEBUG_PORT
-static void mpsc_debug_init (void)
-{
-
- volatile unsigned int temp;
-
- /* Clear the CFR (CHR4) */
- /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
- temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
- temp &= 0xffffff00;
- temp |= BIT29;
- GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
- temp);
-
- /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */
- temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP));
- temp |= (BIT12 | BIT15);
- GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP),
- temp);
-
- /* Set int mask */
- temp = GTREGREAD (GALMPSC_0_INT_MASK);
- temp |= BIT6;
- GT_REG_WRITE (GALMPSC_0_INT_MASK, temp);
-}
-#endif
-
-char mpsc_getchar_debug (void)
-{
- volatile int temp;
- volatile unsigned int cause;
-
- cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
- while ((cause & BIT6) == 0) {
- cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
- }
-
- temp = GTREGREAD (GALMPSC_CHANNELREG_10 +
- (CHANNEL * GALMPSC_REG_GAP));
- /* By writing 1's to the set bits, the register is cleared */
- GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP),
- temp);
- GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6);
- return (temp >> 16) & 0xff;
-}
-
-/* special function for running out of flash. doesn't modify any
- * global variables [josh] */
-int mpsc_putchar_early (char ch)
-{
- int mpsc = CHANNEL;
- int temp =
- GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
- galmpsc_set_tcschar (mpsc, ch);
- GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP),
- temp | 0x200);
-
-#define MAGIC_FACTOR (10*1000000)
-
- udelay (MAGIC_FACTOR / gd->baudrate);
- return 0;
-}
-
-/* This is used after relocation, see serial.c and mpsc_init2 */
-static int mpsc_putchar_sdma (char ch)
-{
- volatile unsigned int *p;
- unsigned int temp;
-
-
- /* align the descriptor */
- p = tx_desc_base;
- memset ((void *) p, 0, 8 * sizeof (unsigned int));
-
- /* fill one 64 bit buffer */
- /* word swap, pad with 0 */
- p[4] = 0; /* x */
- p[5] = (unsigned int) ch; /* x */
-
- /* CHANGED completely according to GT64260A dox - NTL */
- p[0] = 0x00010001; /* 0 */
- p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* 4 */
- p[2] = 0; /* 8 */
- p[3] = (unsigned int) &p[4]; /* c */
-
-#if 0
- p[9] = DESC_FIRST | DESC_LAST;
- p[10] = (unsigned int) &p[0];
- p[11] = (unsigned int) &p[12];
-#endif
-
- FLUSH_DCACHE (&p[0], &p[8]);
-
- GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
- (unsigned int) &p[0]);
- GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
- (unsigned int) &p[0]);
-
- temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
- temp |= (TX_DEMAND | TX_STOP);
- GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
-
- INVALIDATE_DCACHE (&p[1], &p[2]);
-
- while (p[1] & DESC_OWNER_BIT) {
- udelay (100);
- INVALIDATE_DCACHE (&p[1], &p[2]);
- }
- return 0;
-}
-
-char mpsc_getchar_sdma (void)
-{
- static unsigned int done = 0;
- volatile char ch;
- unsigned int len = 0, idx = 0, temp;
-
- volatile unsigned int *p;
-
-
- do {
- p = &rx_desc_base[rx_desc_index * 8];
-
- INVALIDATE_DCACHE (&p[0], &p[1]);
- /* Wait for character */
- while (p[1] & DESC_OWNER_BIT) {
- udelay (100);
- INVALIDATE_DCACHE (&p[0], &p[1]);
- }
-
- /* Handle error case */
- if (p[1] & (1 << 15)) {
- printf ("oops, error: %08x\n", p[1]);
-
- temp = GTREGREAD (GALMPSC_CHANNELREG_2 +
- (CHANNEL * GALMPSC_REG_GAP));
- temp |= (1 << 23);
- GT_REG_WRITE (GALMPSC_CHANNELREG_2 +
- (CHANNEL * GALMPSC_REG_GAP), temp);
-
- /* Can't poll on abort bit, so we just wait. */
- udelay (100);
-
- galsdma_enable_rx ();
- }
-
- /* Number of bytes left in this descriptor */
- len = p[0] & 0xffff;
-
- if (len) {
- /* Where to look */
- idx = 5;
- if (done > 3)
- idx = 4;
- if (done > 7)
- idx = 7;
- if (done > 11)
- idx = 6;
-
- INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
- ch = p[idx] & 0xff;
- done++;
- }
-
- if (done < len) {
- /* this descriptor has more bytes still
- * shift down the char we just read, and leave the
- * buffer in place for the next time around
- */
- p[idx] = p[idx] >> 8;
- FLUSH_DCACHE (&p[idx], &p[idx + 1]);
- }
-
- if (done == len) {
- /* nothing left in this descriptor.
- * go to next one
- */
- p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
- p[0] = 0x00100000;
- FLUSH_DCACHE (&p[0], &p[1]);
- /* Next descriptor */
- rx_desc_index = (rx_desc_index + 1) % RX_DESC;
- done = 0;
- }
- } while (len == 0); /* galileo bug.. len might be zero */
-
- return ch;
-}
-
-
-int mpsc_test_char_debug (void)
-{
- if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0)
- return 0;
- else {
- return 1;
- }
-}
-
-
-int mpsc_test_char_sdma (void)
-{
- volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8];
-
- INVALIDATE_DCACHE (&p[1], &p[2]);
-
- if (p[1] & DESC_OWNER_BIT)
- return 0;
- else
- return 1;
-}
-
-int mpsc_init (int baud)
-{
- /* BRG CONFIG */
- galbrg_set_baudrate (CHANNEL, baud);
- galbrg_set_clksrc (CHANNEL, 8); /* set source=Tclk */
- galbrg_set_CUV (CHANNEL, 0); /* set up CountUpValue */
- galbrg_enable (CHANNEL); /* Enable BRG */
-
- /* Set up clock routing */
- galmpsc_connect (CHANNEL, GALMPSC_CONNECT); /* connect it */
-
- galmpsc_route_rx_clock (CHANNEL, CHANNEL); /* chosse BRG0 for Rx */
- galmpsc_route_tx_clock (CHANNEL, CHANNEL); /* chose BRG0 for Tx */
-
- /* reset MPSC state */
- galmpsc_shutdown (CHANNEL);
-
- /* SDMA CONFIG */
- galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8); /* in 64 bit words (8 bytes) */
- galsdma_set_txle (CHANNEL);
- galsdma_set_rxle (CHANNEL);
- galsdma_set_RC (CHANNEL, 0xf);
- galsdma_set_SFM (CHANNEL);
- galsdma_set_RFT (CHANNEL);
-
- /* MPSC CONFIG */
- galmpsc_write_config_regs (CHANNEL, GALMPSC_UART);
- galmpsc_config_channel_regs (CHANNEL);
- galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */
- galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE); /* N */
- galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */
-
-#ifdef CONFIG_MPSC_DEBUG_PORT
- mpsc_debug_init ();
-#endif
-
- /* COMM_MPSC CONFIG */
-#ifdef SOFTWARE_CACHE_MANAGEMENT
- galmpsc_set_snoop (CHANNEL, 0); /* disable snoop */
-#else
- galmpsc_set_snoop (CHANNEL, 1); /* enable snoop */
-#endif
-
- return 0;
-}
-
-
-void mpsc_sdma_init (void)
-{
- /* Setup SDMA channel0 SDMA_CONFIG_REG*/
- GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff);
-
- /* Enable MPSC-Window0 for DRAM Bank 0 */
- if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT,
- MV64460_SDMA_DRAM_CS_0_TARGET,
- 0,
- memoryGetBankBaseAddress(0),
- memoryGetBankSize(0)) != true)
- printf ("%s: SDMA_Window0 memory setup failed !!! \n",
- __FUNCTION__);
-
-
- /* Enable MPSC-Window1 for DRAM Bank 1 */
- if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_1_BIT,
- MV64460_SDMA_DRAM_CS_1_TARGET,
- 0,
- memoryGetBankBaseAddress(1),
- memoryGetBankSize(1)) != true)
- printf ("%s: SDMA_Window1 memory setup failed !!! \n",
- __FUNCTION__);
-
-
- /* Disable MPSC-Window2 */
- if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_2_BIT,
- MV64460_SDMA_DRAM_CS_2_TARGET,
- 0,
- memoryGetBankBaseAddress(2),
- memoryGetBankSize(2)) != true)
- printf ("%s: SDMA_Window2 memory setup failed !!! \n",
- __FUNCTION__);
-
-
- /* Disable MPSC-Window3 */
- if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_3_BIT,
- MV64460_SDMA_DRAM_CS_3_TARGET,
- 0,
- memoryGetBankBaseAddress(3),
- memoryGetBankSize(3)) != true)
- printf ("%s: SDMA_Window3 memory setup failed !!! \n",
- __FUNCTION__);
-
- /* Setup MPSC0 access mode Window0 full access */
- GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG,
- (MV64460_SDMA_WIN_ACCESS_FULL <<
- (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
-
- /* Setup MPSC1 access mode Window1 full access */
- GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG,
- (MV64460_SDMA_WIN_ACCESS_FULL <<
- (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
-
- /* Setup MPSC internal address space base address */
- GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
-
- /* no high address remap*/
- GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
- GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00);
-
- /* clear interrupt cause register for MPSC (fault register)*/
- GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00);
-}
-
-
-void mpsc_init2 (void)
-{
- int i;
-
-#ifndef CONFIG_MPSC_DEBUG_PORT
- mpsc_putchar = mpsc_putchar_sdma;
- mpsc_getchar = mpsc_getchar_sdma;
- mpsc_test_char = mpsc_test_char_sdma;
-#endif
- /* RX descriptors */
- rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) *
- sizeof (unsigned int));
-
- /* align descriptors */
- rx_desc_base = (unsigned int *)
- (((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0);
-
- rx_desc_index = 0;
-
- memset ((void *) rx_desc_base, 0,
- (RX_DESC * 8) * sizeof (unsigned int));
-
- for (i = 0; i < RX_DESC; i++) {
- rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4]; /* Buffer */
- rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8]; /* Next descriptor */
- rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* Command & control */
- rx_desc_base[i * 8] = 0x00100000;
- }
- rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0];
-
- FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]);
- GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
- (unsigned int) &rx_desc_base[0]);
-
- /* TX descriptors */
- tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) *
- sizeof (unsigned int));
-
- /* align descriptors */
- tx_desc_base = (unsigned int *)
- (((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0);
-
- tx_desc_index = -1;
-
- memset ((void *) tx_desc_base, 0,
- (TX_DESC * 8) * sizeof (unsigned int));
-
- for (i = 0; i < TX_DESC; i++) {
- tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323;
- tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323;
- tx_desc_base[i * 8 + 3] =
- (unsigned int) &tx_desc_base[i * 8 + 4];
- tx_desc_base[i * 8 + 2] =
- (unsigned int) &tx_desc_base[(i + 1) * 8];
- tx_desc_base[i * 8 + 1] =
- DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
-
- /* set sbytecnt and shadow byte cnt to 1 */
- tx_desc_base[i * 8] = 0x00010001;
- }
- tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0];
-
- FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]);
-
- udelay (100);
-
- galsdma_enable_rx ();
-
- return;
-}
-
-int galbrg_set_baudrate (int channel, int rate)
-{
- int clock;
-
- galbrg_disable (channel); /*ok */
-
-#ifdef ZUMA_NTL
- /* from tclk */
- clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
-#else
- clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
-#endif
-
- galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */
-
- galbrg_enable (channel);
-
- gd->baudrate = rate;
-
- return 0;
-}
-
-/* ------------------------------------------------------------------ */
-
-/* Below are all the private functions that no one else needs */
-
-static int galbrg_set_CDV (int channel, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
- temp &= 0xFFFF0000;
- temp |= (value & 0x0000FFFF);
- GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
- return 0;
-}
-
-static int galbrg_enable (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
- temp |= 0x00010000;
- GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
- return 0;
-}
-
-static int galbrg_disable (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
- temp &= 0xFFFEFFFF;
- GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
- return 0;
-}
-
-static int galbrg_set_clksrc (int channel, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
- temp &= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */
- temp |= (value << 18);
- GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
- return 0;
-}
-
-static int galbrg_set_CUV (int channel, int value)
-{
- /* set CountUpValue */
- GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
-
- return 0;
-}
-
-#if 0
-static int galbrg_reset (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
- temp |= 0x20000;
- GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
- return 0;
-}
-#endif
-
-static int galsdma_set_RFT (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
- temp |= 0x00000001;
- GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
- temp);
-
- return 0;
-}
-
-static int galsdma_set_SFM (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
- temp |= 0x00000002;
- GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
- temp);
-
- return 0;
-}
-
-static int galsdma_set_rxle (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
- temp |= 0x00000040;
- GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
- temp);
-
- return 0;
-}
-
-static int galsdma_set_txle (int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
- temp |= 0x00000080;
- GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
- temp);
-
- return 0;
-}
-
-static int galsdma_set_RC (int channel, unsigned int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
- temp &= ~0x0000003c;
- temp |= (value << 2);
- GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
- temp);
-
- return 0;
-}
-
-static int galsdma_set_burstsize (int channel, unsigned int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
- temp &= 0xFFFFCFFF;
- switch (value) {
- case 8:
- GT_REG_WRITE (GALSDMA_0_CONF_REG +
- (channel * GALSDMA_REG_DIFF),
- (temp | (0x3 << 12)));
- break;
-
- case 4:
- GT_REG_WRITE (GALSDMA_0_CONF_REG +
- (channel * GALSDMA_REG_DIFF),
- (temp | (0x2 << 12)));
- break;
-
- case 2:
- GT_REG_WRITE (GALSDMA_0_CONF_REG +
- (channel * GALSDMA_REG_DIFF),
- (temp | (0x1 << 12)));
- break;
-
- case 1:
- GT_REG_WRITE (GALSDMA_0_CONF_REG +
- (channel * GALSDMA_REG_DIFF),
- (temp | (0x0 << 12)));
- break;
-
- default:
- return -1;
- break;
- }
-
- return 0;
-}
-
-static int galmpsc_connect (int channel, int connect)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_ROUTING_REGISTER);
-
- if ((channel == 0) && connect)
- temp &= ~0x00000007;
- else if ((channel == 1) && connect)
- temp &= ~(0x00000007 << 6);
- else if ((channel == 0) && !connect)
- temp |= 0x00000007;
- else
- temp |= (0x00000007 << 6);
-
- /* Just in case... */
- temp &= 0x3fffffff;
-
- GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp);
-
- return 0;
-}
-
-static int galmpsc_route_rx_clock (int channel, int brg)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_RxC_ROUTE);
-
- if (channel == 0) {
- temp &= ~0x0000000F;
- temp |= brg;
- } else {
- temp &= ~0x00000F00;
- temp |= (brg << 8);
- }
-
- GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp);
-
- return 0;
-}
-
-static int galmpsc_route_tx_clock (int channel, int brg)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_TxC_ROUTE);
-
- if (channel == 0) {
- temp &= ~0x0000000F;
- temp |= brg;
- } else {
- temp &= ~0x00000F00;
- temp |= (brg << 8);
- }
-
- GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp);
-
- return 0;
-}
-
-static int galmpsc_write_config_regs (int mpsc, int mode)
-{
- if (mode == GALMPSC_UART) {
- /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
- GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP),
- 0x000004c4);
-
- /* Main config reg High (32x Rx/Tx clock mode, width=8bits */
- GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP),
- 0x024003f8);
- /* 22 2222 1111 */
- /* 54 3210 9876 */
- /* 0000 0010 0000 0000 */
- /* 1 */
- /* 098 7654 3210 */
- /* 0000 0011 1111 1000 */
- } else
- return -1;
-
- return 0;
-}
-
-static int galmpsc_config_channel_regs (int mpsc)
-{
- GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1);
- GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0);
- GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0);
-
- galmpsc_set_brkcnt (mpsc, 0x3);
- galmpsc_set_tcschar (mpsc, 0xab);
-
- return 0;
-}
-
-static int galmpsc_set_brkcnt (int mpsc, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
- temp &= 0x0000FFFF;
- temp |= (value << 16);
- GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
-
- return 0;
-}
-
-static int galmpsc_set_tcschar (int mpsc, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
- temp &= 0xFFFF0000;
- temp |= value;
- GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
-
- return 0;
-}
-
-static int galmpsc_set_char_length (int mpsc, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
- temp &= 0xFFFFCFFF;
- temp |= (value << 12);
- GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
-
- return 0;
-}
-
-static int galmpsc_set_stop_bit_length (int mpsc, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
- temp &= 0xFFFFBFFF;
- temp |= (value << 14);
- GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
-
- return 0;
-}
-
-static int galmpsc_set_parity (int mpsc, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
- if (value != -1) {
- temp &= 0xFFF3FFF3;
- temp |= ((value << 18) | (value << 2));
- temp |= ((value << 17) | (value << 1));
- } else {
- temp &= 0xFFF1FFF1;
- }
-
- GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
-
- return 0;
-}
-
-static int galmpsc_enter_hunt (int mpsc)
-{
- int temp;
-
- temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
- temp |= 0x80000000;
- GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
-
- while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) &
- MPSC_ENTER_HUNT) {
- udelay (1);
- }
- return 0;
-}
-
-
-static int galmpsc_shutdown (int mpsc)
-{
- unsigned int temp;
-
- /* cause RX abort (clears RX) */
- temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
- temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
- temp &= ~MPSC_ENTER_HUNT;
- GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
-
- GT_REG_WRITE (GALSDMA_0_COM_REG, 0);
- GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT);
-
- /* shut down the MPSC */
- GT_REG_WRITE (GALMPSC_MCONF_LOW, 0);
- GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0);
- GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0);
-
- udelay (100);
-
- /* shut down the sdma engines. */
- /* reset config to default */
- GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc);
-
- udelay (100);
-
- /* clear the SDMA current and first TX and RX pointers */
- GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0);
- GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0);
- GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0);
-
- udelay (100);
-
- return 0;
-}
-
-static void galsdma_enable_rx (void)
-{
- int temp;
-
- /* Enable RX processing */
- temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
- temp |= RX_ENABLE;
- GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
-
- galmpsc_enter_hunt (CHANNEL);
-}
-
-static int galmpsc_set_snoop (int mpsc, int value)
-{
- int reg =
- mpsc ? MPSC_1_ADDRESS_CONTROL_LOW :
- MPSC_0_ADDRESS_CONTROL_LOW;
- int temp = GTREGREAD (reg);
-
- if (value)
- temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);
- else
- temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));
- GT_REG_WRITE (reg, temp);
- return 0;
-}
-
-/*******************************************************************************
-* galsdma_set_mem_space - Set MV64460 IDMA memory decoding map.
-*
-* DESCRIPTION:
-* the MV64460 SDMA has its own address decoding map that is de-coupled
-* from the CPU interface address decoding windows. The SDMA channels
-* share four address windows. Each region can be individually configured
-* by this function by associating it to a target interface and setting
-* base and size values.
-*
-* NOTE!!!
-* The size must be in 64Kbyte granularity.
-* The base address must be aligned to the size.
-* The size must be a series of 1s followed by a series of zeros
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* true for success, false otherwise.
-*
-*******************************************************************************/
-
-static int galsdma_set_mem_space (unsigned int memSpace,
- unsigned int memSpaceTarget,
- unsigned int memSpaceAttr,
- unsigned int baseAddress, unsigned int size)
-{
- unsigned int temp;
-
- if (size == 0) {
- GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG,
- 1 << memSpace);
- return true;
- }
-
- /* The base address must be aligned to the size. */
- if (baseAddress % size != 0) {
- return false;
- }
- if (size < 0x10000) {
- return false;
- }
-
- /* Align size and base to 64K */
- baseAddress &= 0xffff0000;
- size &= 0xffff0000;
- temp = size >> 16;
-
- /* Checking that the size is a sequence of '1' followed by a
- sequence of '0' starting from LSB to MSB. */
- while ((temp > 0) && (temp & 0x1)) {
- temp = temp >> 1;
- }
-
- if (temp != 0) {
- GT_REG_WRITE (MV64460_CUNIT_BASE_ADDR_REG0 + memSpace * 8,
- (baseAddress | memSpaceTarget | memSpaceAttr));
- GT_REG_WRITE ((MV64460_CUNIT_SIZE0 + memSpace * 8),
- (size - 1) & 0xffff0000);
- GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG,
- 1 << memSpace);
- } else {
- /* An invalid size was specified */
- return false;
- }
- return true;
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*************************************************************************
- * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
- *
- ************************************************************************/
-
-
-/*
- * mpsc.h - header file for MPSC in uart mode (console driver)
- */
-
-#ifndef __MPSC_H__
-#define __MPSC_H__
-
-/* include actual Galileo defines */
-#include "../../Marvell/include/mv_gen_reg.h"
-
-/* driver related defines */
-
-int mpsc_init(int baud);
-void mpsc_sdma_init(void);
-void mpsc_init2(void);
-int galbrg_set_baudrate(int channel, int rate);
-
-int mpsc_putchar_early(char ch);
-char mpsc_getchar_debug(void);
-int mpsc_test_char_debug(void);
-
-int mpsc_test_char_sdma(void);
-
-extern int (*mpsc_putchar)(char ch);
-extern char (*mpsc_getchar)(void);
-extern int (*mpsc_test_char)(void);
-
-#define CHANNEL CONFIG_MPSC_PORT
-
-#define TX_DESC 5
-#define RX_DESC 20
-
-#define DESC_FIRST 0x00010000
-#define DESC_LAST 0x00020000
-#define DESC_OWNER_BIT 0x80000000
-
-#define TX_DEMAND 0x00800000
-#define TX_STOP 0x00010000
-#define RX_ENABLE 0x00000080
-
-#define SDMA_RX_ABORT (1 << 15)
-#define SDMA_TX_ABORT (1 << 31)
-#define MPSC_TX_ABORT (1 << 7)
-#define MPSC_RX_ABORT (1 << 23)
-#define MPSC_ENTER_HUNT (1 << 31)
-
-/* MPSC defines */
-
-#define GALMPSC_CONNECT 0x1
-#define GALMPSC_DISCONNECT 0x0
-
-#define GALMPSC_UART 0x1
-
-#define GALMPSC_STOP_BITS_1 0x0
-#define GALMPSC_STOP_BITS_2 0x1
-#define GALMPSC_CHAR_LENGTH_8 0x3
-#define GALMPSC_CHAR_LENGTH_7 0x2
-
-#define GALMPSC_PARITY_ODD 0x0
-#define GALMPSC_PARITY_EVEN 0x2
-#define GALMPSC_PARITY_MARK 0x3
-#define GALMPSC_PARITY_SPACE 0x1
-#define GALMPSC_PARITY_NONE -1
-
-#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */
-#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */
-#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */
-#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
-#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */
-#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */
-#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */
-
-#define GALMPSC_REG_GAP 0x1000
-
-#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */
-#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */
-#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */
-#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */
-#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */
-#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */
-#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */
-#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */
-#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */
-#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */
-#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */
-#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */
-
-#define GALSDMA_COMMAND_FIRST (1 << 16)
-#define GALSDMA_COMMAND_LAST (1 << 17)
-#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
-#define GALSDMA_COMMAND_AUTO (1 << 30)
-#define GALSDMA_COMMAND_OWNER (1 << 31)
-
-#define GALSDMA_RX 0
-#define GALSDMA_TX 1
-
-/* CHANNEL2 should be CHANNEL1, according to documentation,
- * but to work with the current GTREGS file...
- */
-#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */
-#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */
-#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */
-#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */
-#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */
-#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */
-#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */
-#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */
-#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */
-#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */
-#define GALSDMA_REG_DIFF 0x2000
-
-/* WRONG in gt64260R.h */
-#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */
-#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */
-#define GALMPSC_0_INT_CAUSE 0xb804
-#define GALMPSC_0_INT_MASK 0xb884
-
-#define GALSDMA_MODE_UART 0
-#define GALSDMA_MODE_BISYNC 1
-#define GALSDMA_MODE_HDLC 2
-#define GALSDMA_MODE_TRANSPARENT 3
-
-#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */
-#define GALBRG_REG_GAP 0x0008
-#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */
-
-#endif /* __MPSC_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64460X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * mv_eth.c - header file for the polled mode GT ethernet driver
- */
-#include <common.h>
-#include <net.h>
-#include <malloc.h>
-#include <miiphy.h>
-
-#include "mv_eth.h"
-
-/* enable Debug outputs */
-
-#undef DEBUG_MV_ETH
-
-#ifdef DEBUG_MV_ETH
-#define DEBUG
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-/* PHY DFCDL Registers */
-#define ETH_PHY_DFCDL_CONFIG0_REG 0x2100
-#define ETH_PHY_DFCDL_CONFIG1_REG 0x2104
-#define ETH_PHY_DFCDL_ADDR_REG 0x2110
-#define ETH_PHY_DFCDL_DATA0_REG 0x2114
-
-#define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
-#define PHY_UPDATE_TIMEOUT 10000
-
-#undef MV64460_CHECKSUM_OFFLOAD
-/*************************************************************************
-* The first part is the high level driver of the gigE ethernet ports. *
-*************************************************************************/
-
-/* Definition for configuring driver */
-/* #define UPDATE_STATS_BY_SOFTWARE */
-#undef MV64460_RX_QUEUE_FILL_ON_TASK
-
-/* Constants */
-#define MAGIC_ETH_RUNNING 8031971
-#define MV64460_INTERNAL_SRAM_SIZE _256K
-#define EXTRA_BYTES 32
-#define WRAP ETH_HLEN + 2 + 4 + 16
-#define BUFFER_MTU dev->mtu + WRAP
-#define INT_CAUSE_UNMASK_ALL 0x0007ffff
-#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
-#ifdef MV64460_RX_FILL_ON_TASK
-#define INT_CAUSE_MASK_ALL 0x00000000
-#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
-#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
-#endif
-
-/* Read/Write to/from MV64460 internal registers */
-#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
-#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
-#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
-#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
-
-#define my_cpu_to_le32(x) my_le32_to_cpu((x))
-
-/* Static function declarations */
-static int mv64460_eth_real_open (struct eth_device *eth);
-static int mv64460_eth_real_stop (struct eth_device *eth);
-static struct net_device_stats *mv64460_eth_get_stats (struct eth_device
- *dev);
-static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
-static void mv64460_eth_update_stat (struct eth_device *dev);
-bool db64460_eth_start (struct eth_device *eth);
-unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
- unsigned int mib_offset);
-int mv64460_eth_receive (struct eth_device *dev);
-
-int mv64460_eth_xmit (struct eth_device *, volatile void *packet, int length);
-
-int mv_miiphy_read(const char *devname, unsigned char phy_addr,
- unsigned char phy_reg, unsigned short *value);
-int mv_miiphy_write(const char *devname, unsigned char phy_addr,
- unsigned char phy_reg, unsigned short value);
-
-int phy_setup_aneg (char *devname, unsigned char addr);
-
-#ifndef UPDATE_STATS_BY_SOFTWARE
-static void mv64460_eth_print_stat (struct eth_device *dev);
-#endif
-
-extern unsigned int INTERNAL_REG_BASE_ADDR;
-
-unsigned long my_le32_to_cpu (unsigned long x)
-{
- return (((x & 0x000000ffU) << 24) |
- ((x & 0x0000ff00U) << 8) |
- ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
-}
-
-/*************************************************
- *Helper functions - used inside the driver only *
- *************************************************/
-#ifdef DEBUG_MV_ETH
-void print_globals (struct eth_device *dev)
-{
- printf ("Ethernet PRINT_Globals-Debug function\n");
- printf ("Base Address for ETH_PORT_INFO: %08x\n",
- (unsigned int) dev->priv);
- printf ("Base Address for mv64460_eth_priv: %08x\n",
- (unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
- port_private));
-
- printf ("GT Internal Base Address: %08x\n",
- INTERNAL_REG_BASE_ADDR);
- printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n",
- (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64460_TX_QUEUE_SIZE);
- printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n",
- (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64460_RX_QUEUE_SIZE);
- printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n",
- (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
- p_rx_buffer_base[0],
- (MV64460_RX_QUEUE_SIZE * MV64460_RX_BUFFER_SIZE) + 32);
- printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n",
- (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
- p_tx_buffer_base[0],
- (MV64460_TX_QUEUE_SIZE * MV64460_TX_BUFFER_SIZE) + 32);
-}
-#endif
-
-/**********************************************************************
- * mv64460_eth_print_phy_status
- *
- * Prints gigabit ethenret phy status
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- **********************************************************************/
-void mv64460_eth_print_phy_status (struct eth_device *dev)
-{
- struct mv64460_eth_priv *port_private;
- unsigned int port_num;
- ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
- unsigned int port_status, phy_reg_data;
-
- port_private =
- (struct mv64460_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
-
- /* Check Link status on phy */
- eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
- if (!(phy_reg_data & 0x20)) {
- printf ("Ethernet port changed link status to DOWN\n");
- } else {
- port_status =
- MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
- printf ("Ethernet status port %d: Link up", port_num);
- printf (", %s",
- (port_status & BIT2) ? "Full Duplex" : "Half Duplex");
- if (port_status & BIT4)
- printf (", Speed 1 Gbps");
- else
- printf (", %s",
- (port_status & BIT5) ? "Speed 100 Mbps" :
- "Speed 10 Mbps");
- printf ("\n");
- }
-}
-
-/**********************************************************************
- * u-boot entry functions for mv64460_eth
- *
- **********************************************************************/
-int db64460_eth_probe (struct eth_device *dev)
-{
- return ((int) db64460_eth_start (dev));
-}
-
-int db64460_eth_poll (struct eth_device *dev)
-{
- return mv64460_eth_receive (dev);
-}
-
-int db64460_eth_transmit(struct eth_device *dev, void *packet, int length)
-{
- mv64460_eth_xmit (dev, packet, length);
- return 0;
-}
-
-void db64460_eth_disable (struct eth_device *dev)
-{
- mv64460_eth_stop (dev);
-}
-
-#define DFCDL(write,read) ((write << 6) | read)
-unsigned int ethDfcdls[] = {
- DFCDL(0,0), DFCDL(1,1), DFCDL(2,2), DFCDL(3,3),
- DFCDL(4,4), DFCDL(5,5), DFCDL(6,6), DFCDL(7,7),
- DFCDL(8,8), DFCDL(9,9), DFCDL(10,10), DFCDL(11,11),
- DFCDL(12,12), DFCDL(13,13), DFCDL(14,14), DFCDL(15,15),
- DFCDL(16,16), DFCDL(17,17), DFCDL(18,18), DFCDL(19,19),
- DFCDL(20,20), DFCDL(21,21), DFCDL(22,22), DFCDL(23,23),
- DFCDL(24,24), DFCDL(25,25), DFCDL(26,26), DFCDL(27,27),
- DFCDL(28,28), DFCDL(29,29), DFCDL(30,30), DFCDL(31,31),
- DFCDL(32,32), DFCDL(33,33), DFCDL(34,34), DFCDL(35,35),
- DFCDL(36,36), DFCDL(37,37), DFCDL(38,38), DFCDL(39,39),
- DFCDL(40,40), DFCDL(41,41), DFCDL(42,42), DFCDL(43,43),
- DFCDL(44,44), DFCDL(45,45), DFCDL(46,46), DFCDL(47,47),
- DFCDL(48,48), DFCDL(49,49), DFCDL(50,50), DFCDL(51,51),
- DFCDL(52,52), DFCDL(53,53), DFCDL(54,54), DFCDL(55,55),
- DFCDL(56,56), DFCDL(57,57), DFCDL(58,58), DFCDL(59,59),
- DFCDL(60,60), DFCDL(61,61), DFCDL(62,62), DFCDL(63,63),
-};
-
-void mv_eth_phy_init (void)
-{
- int i;
-
- MV_REG_WRITE (ETH_PHY_DFCDL_ADDR_REG, 0);
-
- for (i = 0; i < 64; i++) {
- MV_REG_WRITE (ETH_PHY_DFCDL_DATA0_REG, ethDfcdls[i]);
- }
-
- MV_REG_WRITE (ETH_PHY_DFCDL_CONFIG0_REG, 0x300000);
-}
-
-void mv6446x_eth_initialize (bd_t * bis)
-{
- struct eth_device *dev;
- ETH_PORT_INFO *ethernet_private;
- struct mv64460_eth_priv *port_private;
- int devnum, x, temp;
- char *s, *e, buf[64];
-
- /* P3M750 only
- * Set RGMII clock drives strength
- */
- temp = MV_REG_READ(0x20A0);
- temp |= 0x04000080;
- MV_REG_WRITE(0x20A0, temp);
-
- mv_eth_phy_init();
-
- for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
- dev = calloc (sizeof (*dev), 1);
- if (!dev) {
- printf ("%s: mv_enet%d allocation failure, %s\n",
- __FUNCTION__, devnum, "eth_device structure");
- return;
- }
-
- /* must be less than sizeof(dev->name) */
- sprintf (dev->name, "mv_enet%d", devnum);
-
-#ifdef DEBUG
- printf ("Initializing %s\n", dev->name);
-#endif
-
- /* Extract the MAC address from the environment */
- switch (devnum) {
- case 0:
- s = "ethaddr";
- break;
- case 1:
- s = "eth1addr";
- break;
- case 2:
- s = "eth2addr";
- break;
- default: /* this should never happen */
- printf ("%s: Invalid device number %d\n",
- __FUNCTION__, devnum);
- return;
- }
-
- temp = getenv_f(s, buf, sizeof (buf));
- s = (temp > 0) ? buf : NULL;
-
-#ifdef DEBUG
- printf ("Setting MAC %d to %s\n", devnum, s);
-#endif
- for (x = 0; x < 6; ++x) {
- dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
- if (s)
- s = (*e) ? e + 1 : e;
- }
- /* ronen - set the MAC addr in the HW */
- eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
-
- dev->init = (void *) db64460_eth_probe;
- dev->halt = (void *) ethernet_phy_reset;
- dev->send = (void *) db64460_eth_transmit;
- dev->recv = (void *) db64460_eth_poll;
-
- ethernet_private = calloc (sizeof (*ethernet_private), 1);
- dev->priv = (void *)ethernet_private;
- if (!ethernet_private) {
- printf ("%s: %s allocation failure, %s\n",
- __FUNCTION__, dev->name,
- "Private Device Structure");
- free (dev);
- return;
- }
- /* start with an zeroed ETH_PORT_INFO */
- memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
- memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
-
- /* set pointer to memory for stats data structure etc... */
- port_private = calloc (sizeof (*ethernet_private), 1);
- ethernet_private->port_private = (void *)port_private;
- if (!port_private) {
- printf ("%s: %s allocation failure, %s\n",
- __FUNCTION__, dev->name,
- "Port Private Device Structure");
-
- free (ethernet_private);
- free (dev);
- return;
- }
-
- port_private->stats =
- calloc (sizeof (struct net_device_stats), 1);
- if (!port_private->stats) {
- printf ("%s: %s allocation failure, %s\n",
- __FUNCTION__, dev->name,
- "Net stat Structure");
-
- free (port_private);
- free (ethernet_private);
- free (dev);
- return;
- }
- memset (ethernet_private->port_private, 0,
- sizeof (struct mv64460_eth_priv));
- switch (devnum) {
- case 0:
- ethernet_private->port_num = ETH_0;
- break;
- case 1:
- ethernet_private->port_num = ETH_1;
- break;
- case 2:
- ethernet_private->port_num = ETH_2;
- break;
- default:
- printf ("Invalid device number %d\n", devnum);
- break;
- };
-
- port_private->port_num = devnum;
- /*
- * Read MIB counter on the GT in order to reset them,
- * then zero all the stats fields in memory
- */
- mv64460_eth_update_stat (dev);
- memset (port_private->stats, 0,
- sizeof (struct net_device_stats));
- /* Extract the MAC address from the environment */
- switch (devnum) {
- case 0:
- s = "ethaddr";
- break;
- case 1:
- s = "eth1addr";
- break;
- case 2:
- s = "eth2addr";
- break;
- default: /* this should never happen */
- printf ("%s: Invalid device number %d\n",
- __FUNCTION__, devnum);
- return;
- }
-
- temp = getenv_f(s, buf, sizeof (buf));
- s = (temp > 0) ? buf : NULL;
-
-#ifdef DEBUG
- printf ("Setting MAC %d to %s\n", devnum, s);
-#endif
- for (x = 0; x < 6; ++x) {
- dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
- if (s)
- s = (*e) ? e + 1 : e;
- }
-
- DP (printf ("Allocating descriptor and buffer rings\n"));
-
- ethernet_private->p_rx_desc_area_base[0] =
- (ETH_RX_DESC *) memalign (16,
- RX_DESC_ALIGNED_SIZE *
- MV64460_RX_QUEUE_SIZE + 1);
- ethernet_private->p_tx_desc_area_base[0] =
- (ETH_TX_DESC *) memalign (16,
- TX_DESC_ALIGNED_SIZE *
- MV64460_TX_QUEUE_SIZE + 1);
-
- ethernet_private->p_rx_buffer_base[0] =
- (char *) memalign (16,
- MV64460_RX_QUEUE_SIZE *
- MV64460_TX_BUFFER_SIZE + 1);
- ethernet_private->p_tx_buffer_base[0] =
- (char *) memalign (16,
- MV64460_RX_QUEUE_SIZE *
- MV64460_TX_BUFFER_SIZE + 1);
-
-#ifdef DEBUG_MV_ETH
- /* DEBUG OUTPUT prints adresses of globals */
- print_globals (dev);
-#endif
- eth_register (dev);
-
- miiphy_register(dev->name, mv_miiphy_read, mv_miiphy_write);
- }
- DP (printf ("%s: exit\n", __FUNCTION__));
-
-}
-
-/**********************************************************************
- * mv64460_eth_open
- *
- * This function is called when openning the network device. The function
- * should initialize all the hardware, initialize cyclic Rx/Tx
- * descriptors chain and buffers and allocate an IRQ to the network
- * device.
- *
- * Input : a pointer to the network device structure
- * / / ronen - changed the output to match net/eth.c needs
- * Output : nonzero of success , zero if fails.
- * under construction
- **********************************************************************/
-
-int mv64460_eth_open (struct eth_device *dev)
-{
- return (mv64460_eth_real_open (dev));
-}
-
-/* Helper function for mv64460_eth_open */
-static int mv64460_eth_real_open (struct eth_device *dev)
-{
-
- unsigned int queue;
- ETH_PORT_INFO *ethernet_private;
- struct mv64460_eth_priv *port_private;
- unsigned int port_num;
- ushort reg_short;
- int speed;
- int duplex;
- int i;
- int reg;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- /* ronen - when we update the MAC env params we only update dev->enetaddr
- see ./net/eth.c eth_set_enetaddr() */
- memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
-
- port_private = (struct mv64460_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
-
- /* Stop RX Queues */
- MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), 0x0000ff00);
-
- /* Clear the ethernet port interrupts */
- MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
- MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
-
- /* Unmask RX buffer and TX end interrupt */
- MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num),
- INT_CAUSE_UNMASK_ALL);
-
- /* Unmask phy and link status changes interrupts */
- MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
- INT_CAUSE_UNMASK_ALL_EXT);
-
- /* Set phy address of the port */
- ethernet_private->port_phy_addr = 0x1 + (port_num << 1);
- reg = ethernet_private->port_phy_addr;
-
- /* Activate the DMA channels etc */
- eth_port_init (ethernet_private);
-
- /* "Allocate" setup TX rings */
-
- for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {
- unsigned int size;
-
- port_private->tx_ring_size[queue] = MV64460_TX_QUEUE_SIZE;
- size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */
- ethernet_private->tx_desc_area_size[queue] = size;
-
- /* first clear desc area completely */
- memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
- 0, ethernet_private->tx_desc_area_size[queue]);
-
- /* initialize tx desc ring with low level driver */
- if (ether_init_tx_desc_ring
- (ethernet_private, ETH_Q0,
- port_private->tx_ring_size[queue],
- MV64460_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
- (unsigned int) ethernet_private->
- p_tx_desc_area_base[queue],
- (unsigned int) ethernet_private->
- p_tx_buffer_base[queue]) == false)
- printf ("### Error initializing TX Ring\n");
- }
-
- /* "Allocate" setup RX rings */
- for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {
- unsigned int size;
-
- /* Meantime RX Ring are fixed - but must be configurable by user */
- port_private->rx_ring_size[queue] = MV64460_RX_QUEUE_SIZE;
- size = (port_private->rx_ring_size[queue] *
- RX_DESC_ALIGNED_SIZE);
- ethernet_private->rx_desc_area_size[queue] = size;
-
- /* first clear desc area completely */
- memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
- 0, ethernet_private->rx_desc_area_size[queue]);
- if ((ether_init_rx_desc_ring
- (ethernet_private, ETH_Q0,
- port_private->rx_ring_size[queue],
- MV64460_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
- (unsigned int) ethernet_private->
- p_rx_desc_area_base[queue],
- (unsigned int) ethernet_private->
- p_rx_buffer_base[queue])) == false)
- printf ("### Error initializing RX Ring\n");
- }
-
- eth_port_start (ethernet_private);
-
- /* Set maximum receive buffer to 9700 bytes */
- MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num),
- (0x5 << 17) |
- (MV_REG_READ
- (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num))
- & 0xfff1ffff));
-
- /*
- * Set ethernet MTU for leaky bucket mechanism to 0 - this will
- * disable the leaky bucket mechanism .
- */
-
- MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
- MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
-
-#if defined(CONFIG_PHY_RESET)
- /*
- * Reset the phy, only if its the first time through
- * otherwise, just check the speeds & feeds
- */
- if (port_private->first_init == 0) {
- port_private->first_init = 1;
- ethernet_phy_reset (port_num);
-
- /* Start/Restart autonegotiation */
- phy_setup_aneg (dev->name, reg);
- udelay (1000);
- }
-#endif /* defined(CONFIG_PHY_RESET) */
-
- miiphy_read (dev->name, reg, MII_BMSR, ®_short);
-
- /*
- * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
- */
- if ((reg_short & BMSR_ANEGCAPABLE)
- && !(reg_short & BMSR_ANEGCOMPLETE)) {
- puts ("Waiting for PHY auto negotiation to complete");
- i = 0;
- while (!(reg_short & BMSR_ANEGCOMPLETE)) {
- /*
- * Timeout reached ?
- */
- if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
- puts (" TIMEOUT !\n");
- break;
- }
-
- if ((i++ % 1000) == 0) {
- putc ('.');
- }
- udelay (1000); /* 1 ms */
- miiphy_read (dev->name, reg, MII_BMSR, ®_short);
-
- }
- puts (" done\n");
- udelay (500000); /* another 500 ms (results in faster booting) */
- }
-
- speed = miiphy_speed (dev->name, reg);
- duplex = miiphy_duplex (dev->name, reg);
-
- printf ("ENET Speed is %d Mbps - %s duplex connection\n",
- (int) speed, (duplex == HALF) ? "HALF" : "FULL");
-
- port_private->eth_running = MAGIC_ETH_RUNNING;
- return 1;
-}
-
-static int mv64460_eth_free_tx_rings (struct eth_device *dev)
-{
- unsigned int queue;
- ETH_PORT_INFO *ethernet_private;
- struct mv64460_eth_priv *port_private;
- unsigned int port_num;
- volatile ETH_TX_DESC *p_tx_curr_desc;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64460_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
-
- /* Stop Tx Queues */
- MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
- 0x0000ff00);
-
- /* Free TX rings */
- DP (printf ("Clearing previously allocated TX queues... "));
- for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {
- /* Free on TX rings */
- for (p_tx_curr_desc =
- ethernet_private->p_tx_desc_area_base[queue];
- ((unsigned int) p_tx_curr_desc <= (unsigned int)
- ethernet_private->p_tx_desc_area_base[queue] +
- ethernet_private->tx_desc_area_size[queue]);
- p_tx_curr_desc =
- (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
- TX_DESC_ALIGNED_SIZE)) {
- /* this is inside for loop */
- if (p_tx_curr_desc->return_info != 0) {
- p_tx_curr_desc->return_info = 0;
- DP (printf ("freed\n"));
- }
- }
- DP (printf ("Done\n"));
- }
- return 0;
-}
-
-static int mv64460_eth_free_rx_rings (struct eth_device *dev)
-{
- unsigned int queue;
- ETH_PORT_INFO *ethernet_private;
- struct mv64460_eth_priv *port_private;
- unsigned int port_num;
- volatile ETH_RX_DESC *p_rx_curr_desc;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64460_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
-
- /* Stop RX Queues */
- MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
- 0x0000ff00);
-
- /* Free RX rings */
- DP (printf ("Clearing previously allocated RX queues... "));
- for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {
- /* Free preallocated skb's on RX rings */
- for (p_rx_curr_desc =
- ethernet_private->p_rx_desc_area_base[queue];
- (((unsigned int) p_rx_curr_desc <
- ((unsigned int) ethernet_private->
- p_rx_desc_area_base[queue] +
- ethernet_private->rx_desc_area_size[queue])));
- p_rx_curr_desc =
- (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
- RX_DESC_ALIGNED_SIZE)) {
- if (p_rx_curr_desc->return_info != 0) {
- p_rx_curr_desc->return_info = 0;
- DP (printf ("freed\n"));
- }
- }
- DP (printf ("Done\n"));
- }
- return 0;
-}
-
-/**********************************************************************
- * mv64460_eth_stop
- *
- * This function is used when closing the network device.
- * It updates the hardware,
- * release all memory that holds buffers and descriptors and release the IRQ.
- * Input : a pointer to the device structure
- * Output : zero if success , nonzero if fails
- *********************************************************************/
-
-int mv64460_eth_stop (struct eth_device *dev)
-{
- /* Disable all gigE address decoder */
- MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
- DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
- mv64460_eth_real_stop (dev);
-
- return 0;
-};
-
-/* Helper function for mv64460_eth_stop */
-
-static int mv64460_eth_real_stop (struct eth_device *dev)
-{
- ETH_PORT_INFO *ethernet_private;
- struct mv64460_eth_priv *port_private;
- unsigned int port_num;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64460_eth_priv *) ethernet_private->port_private;
- port_num = port_private->port_num;
-
- mv64460_eth_free_tx_rings (dev);
- mv64460_eth_free_rx_rings (dev);
-
- eth_port_reset (ethernet_private->port_num);
- /* Disable ethernet port interrupts */
- MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
- MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
- /* Mask RX buffer and TX end interrupt */
- MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), 0);
- /* Mask phy and link status changes interrupts */
- MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
- MV_RESET_REG_BITS (MV64460_CPU_INTERRUPT0_MASK_HIGH,
- BIT0 << port_num);
- /* Print Network statistics */
-#ifndef UPDATE_STATS_BY_SOFTWARE
- /*
- * Print statistics (only if ethernet is running),
- * then zero all the stats fields in memory
- */
- if (port_private->eth_running == MAGIC_ETH_RUNNING) {
- port_private->eth_running = 0;
- mv64460_eth_print_stat (dev);
- }
- memset (port_private->stats, 0, sizeof (struct net_device_stats));
-#endif
- DP (printf ("\nEthernet stopped ... \n"));
- return 0;
-}
-
-/**********************************************************************
- * mv64460_eth_start_xmit
- *
- * This function is queues a packet in the Tx descriptor for
- * required port.
- *
- * Input : skb - a pointer to socket buffer
- * dev - a pointer to the required port
- *
- * Output : zero upon success
- **********************************************************************/
-
-int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
- int dataSize)
-{
- ETH_PORT_INFO *ethernet_private;
- struct mv64460_eth_priv *port_private;
- PKT_INFO pkt_info;
- ETH_FUNC_RET_STATUS status;
- struct net_device_stats *stats;
- ETH_FUNC_RET_STATUS release_result;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64460_eth_priv *) ethernet_private->port_private;
-
- stats = port_private->stats;
-
- /* Update packet info data structure */
- pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */
- pkt_info.byte_cnt = dataSize;
- pkt_info.buf_ptr = (unsigned int) dataPtr;
- pkt_info.return_info = 0;
-
- status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
- if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
- printf ("Error on transmitting packet ..");
- if (status == ETH_QUEUE_FULL)
- printf ("ETH Queue is full. \n");
- if (status == ETH_QUEUE_LAST_RESOURCE)
- printf ("ETH Queue: using last available resource. \n");
- return 1;
- }
-
- /* Update statistics and start of transmittion time */
- stats->tx_bytes += dataSize;
- stats->tx_packets++;
-
- /* Check if packet(s) is(are) transmitted correctly (release everything) */
- do {
- release_result =
- eth_tx_return_desc (ethernet_private, ETH_Q0,
- &pkt_info);
- switch (release_result) {
- case ETH_OK:
- DP (printf ("descriptor released\n"));
- if (pkt_info.cmd_sts & BIT0) {
- printf ("Error in TX\n");
- stats->tx_errors++;
- }
- break;
- case ETH_RETRY:
- DP (printf ("transmission still in process\n"));
- break;
-
- case ETH_ERROR:
- printf ("routine can not access Tx desc ring\n");
- break;
-
- case ETH_END_OF_JOB:
- DP (printf ("the routine has nothing to release\n"));
- break;
- default: /* should not happen */
- break;
- }
- } while (release_result == ETH_OK);
-
- return 0; /* success */
-}
-
-/**********************************************************************
- * mv64460_eth_receive
- *
- * This function is forward packets that are received from the port's
- * queues toward kernel core or FastRoute them to another interface.
- *
- * Input : dev - a pointer to the required interface
- * max - maximum number to receive (0 means unlimted)
- *
- * Output : number of served packets
- **********************************************************************/
-
-int mv64460_eth_receive (struct eth_device *dev)
-{
- ETH_PORT_INFO *ethernet_private;
- struct mv64460_eth_priv *port_private;
- PKT_INFO pkt_info;
- struct net_device_stats *stats;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private = (struct mv64460_eth_priv *) ethernet_private->port_private;
- stats = port_private->stats;
-
- while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == ETH_OK)) {
-#ifdef DEBUG_MV_ETH
- if (pkt_info.byte_cnt != 0) {
- printf ("%s: Received %d byte Packet @ 0x%x\n",
- __FUNCTION__, pkt_info.byte_cnt,
- pkt_info.buf_ptr);
- if(pkt_info.buf_ptr != 0){
- for(i=0; i < pkt_info.byte_cnt; i++){
- if((i % 4) == 0){
- printf("\n0x");
- }
- printf("%02x", ((char*)pkt_info.buf_ptr)[i]);
- }
- printf("\n");
- }
- }
-#endif
- /* Update statistics. Note byte count includes 4 byte CRC count */
- stats->rx_packets++;
- stats->rx_bytes += pkt_info.byte_cnt;
-
- /*
- * In case received a packet without first / last bits on OR the error
- * summary bit is on, the packets needs to be dropeed.
- */
- if (((pkt_info.
- cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
- (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
- || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
- stats->rx_dropped++;
-
- printf ("Received packet spread on multiple descriptors\n");
-
- /* Is this caused by an error ? */
- if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
- stats->rx_errors++;
- }
-
- /* free these descriptors again without forwarding them to the higher layers */
- pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
- pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
-
- if (eth_rx_return_buff
- (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
- printf ("Error while returning the RX Desc to Ring\n");
- } else {
- DP (printf ("RX Desc returned to Ring\n"));
- }
- /* /free these descriptors again */
- } else {
-
-/* !!! call higher layer processing */
-#ifdef DEBUG_MV_ETH
- printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
-#endif
- /* let the upper layer handle the packet */
- NetReceive ((uchar *) pkt_info.buf_ptr,
- (int) pkt_info.byte_cnt);
-
-/* **************************************************************** */
-/* free descriptor */
- pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
- pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
- DP (printf ("RX: pkt_info.buf_ptr = %x\n", pkt_info.buf_ptr));
- if (eth_rx_return_buff
- (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
- printf ("Error while returning the RX Desc to Ring\n");
- } else {
- DP (printf ("RX: Desc returned to Ring\n"));
- }
-
-/* **************************************************************** */
-
- }
- }
- mv64460_eth_get_stats (dev); /* update statistics */
- return 1;
-}
-
-/**********************************************************************
- * mv64460_eth_get_stats
- *
- * Returns a pointer to the interface statistics.
- *
- * Input : dev - a pointer to the required interface
- *
- * Output : a pointer to the interface's statistics
- **********************************************************************/
-
-static struct net_device_stats *mv64460_eth_get_stats (struct eth_device *dev)
-{
- ETH_PORT_INFO *ethernet_private;
- struct mv64460_eth_priv *port_private;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64460_eth_priv *) ethernet_private->port_private;
-
- mv64460_eth_update_stat (dev);
-
- return port_private->stats;
-}
-
-/**********************************************************************
- * mv64460_eth_update_stat
- *
- * Update the statistics structure in the private data structure
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- **********************************************************************/
-
-static void mv64460_eth_update_stat (struct eth_device *dev)
-{
- ETH_PORT_INFO *ethernet_private;
- struct mv64460_eth_priv *port_private;
- struct net_device_stats *stats;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64460_eth_priv *) ethernet_private->port_private;
- stats = port_private->stats;
-
- /* These are false updates */
- stats->rx_packets += (unsigned long)
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_GOOD_FRAMES_RECEIVED);
- stats->tx_packets += (unsigned long)
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_GOOD_FRAMES_SENT);
- stats->rx_bytes += (unsigned long)
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
- /*
- * Ideally this should be as follows -
- *
- * stats->rx_bytes += stats->rx_bytes +
- * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
- * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
- *
- * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
- * is just a dummy read for proper work of the GigE port
- */
- (void)eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
- stats->tx_bytes += (unsigned long)
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_GOOD_OCTETS_SENT_LOW);
- (void)eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_GOOD_OCTETS_SENT_HIGH);
- stats->rx_errors += (unsigned long)
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_MAC_RECEIVE_ERROR);
-
- /* Rx dropped is for received packet with CRC error */
- stats->rx_dropped +=
- (unsigned long) eth_read_mib_counter (ethernet_private->
- port_num,
- ETH_MIB_BAD_CRC_EVENT);
- stats->multicast += (unsigned long)
- eth_read_mib_counter (ethernet_private->port_num,
- ETH_MIB_MULTICAST_FRAMES_RECEIVED);
- stats->collisions +=
- (unsigned long) eth_read_mib_counter (ethernet_private->
- port_num,
- ETH_MIB_COLLISION) +
- (unsigned long) eth_read_mib_counter (ethernet_private->
- port_num,
- ETH_MIB_LATE_COLLISION);
- /* detailed rx errors */
- stats->rx_length_errors +=
- (unsigned long) eth_read_mib_counter (ethernet_private->
- port_num,
- ETH_MIB_UNDERSIZE_RECEIVED)
- +
- (unsigned long) eth_read_mib_counter (ethernet_private->
- port_num,
- ETH_MIB_OVERSIZE_RECEIVED);
- /* detailed tx errors */
-}
-
-#ifndef UPDATE_STATS_BY_SOFTWARE
-/**********************************************************************
- * mv64460_eth_print_stat
- *
- * Update the statistics structure in the private data structure
- *
- * Input : pointer to ethernet interface network device structure
- * Output : N/A
- **********************************************************************/
-
-static void mv64460_eth_print_stat (struct eth_device *dev)
-{
- ETH_PORT_INFO *ethernet_private;
- struct mv64460_eth_priv *port_private;
- struct net_device_stats *stats;
-
- ethernet_private = (ETH_PORT_INFO *) dev->priv;
- port_private =
- (struct mv64460_eth_priv *) ethernet_private->port_private;
- stats = port_private->stats;
-
- /* These are false updates */
- printf ("\n### Network statistics: ###\n");
- printf ("--------------------------\n");
- printf (" Packets received: %ld\n", stats->rx_packets);
- printf (" Packets send: %ld\n", stats->tx_packets);
- printf (" Received bytes: %ld\n", stats->rx_bytes);
- printf (" Send bytes: %ld\n", stats->tx_bytes);
- if (stats->rx_errors != 0)
- printf (" Rx Errors: %ld\n",
- stats->rx_errors);
- if (stats->rx_dropped != 0)
- printf (" Rx dropped (CRC Errors): %ld\n",
- stats->rx_dropped);
- if (stats->multicast != 0)
- printf (" Rx mulicast frames: %ld\n",
- stats->multicast);
- if (stats->collisions != 0)
- printf (" No. of collisions: %ld\n",
- stats->collisions);
- if (stats->rx_length_errors != 0)
- printf (" Rx length errors: %ld\n",
- stats->rx_length_errors);
-}
-#endif
-
-/**************************************************************************
- *network_start - Network Kick Off Routine UBoot
- *Inputs :
- *Outputs :
- **************************************************************************/
-
-bool db64460_eth_start (struct eth_device *dev)
-{
- return (mv64460_eth_open (dev)); /* calls real open */
-}
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-* The second part is the low level driver of the gigE ethernet ports. *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-/*
- * based on Linux code
- * arch/powerpc/galileo/EVB64460/mv64460_eth.c - Driver for MV64460X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
-
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/********************************************************************************
- * Marvell's Gigabit Ethernet controller low level driver
- *
- * DESCRIPTION:
- * This file introduce low level API to Marvell's Gigabit Ethernet
- * controller. This Gigabit Ethernet Controller driver API controls
- * 1) Operations (i.e. port init, start, reset etc').
- * 2) Data flow (i.e. port send, receive etc').
- * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
- * struct.
- * This struct includes user configuration information as well as
- * driver internal data needed for its operations.
- *
- * Supported Features:
- * - This low level driver is OS independent. Allocating memory for
- * the descriptor rings and buffers are not within the scope of
- * this driver.
- * - The user is free from Rx/Tx queue managing.
- * - This low level driver introduce functionality API that enable
- * the to operate Marvell's Gigabit Ethernet Controller in a
- * convenient way.
- * - Simple Gigabit Ethernet port operation API.
- * - Simple Gigabit Ethernet port data flow API.
- * - Data flow and operation API support per queue functionality.
- * - Support cached descriptors for better performance.
- * - Enable access to all four DRAM banks and internal SRAM memory
- * spaces.
- * - PHY access and control API.
- * - Port control register configuration API.
- * - Full control over Unicast and Multicast MAC configurations.
- *
- * Operation flow:
- *
- * Initialization phase
- * This phase complete the initialization of the ETH_PORT_INFO
- * struct.
- * User information regarding port configuration has to be set
- * prior to calling the port initialization routine. For example,
- * the user has to assign the port_phy_addr field which is board
- * depended parameter.
- * In this phase any port Tx/Rx activity is halted, MIB counters
- * are cleared, PHY address is set according to user parameter and
- * access to DRAM and internal SRAM memory spaces.
- *
- * Driver ring initialization
- * Allocating memory for the descriptor rings and buffers is not
- * within the scope of this driver. Thus, the user is required to
- * allocate memory for the descriptors ring and buffers. Those
- * memory parameters are used by the Rx and Tx ring initialization
- * routines in order to curve the descriptor linked list in a form
- * of a ring.
- * Note: Pay special attention to alignment issues when using
- * cached descriptors/buffers. In this phase the driver store
- * information in the ETH_PORT_INFO struct regarding each queue
- * ring.
- *
- * Driver start
- * This phase prepares the Ethernet port for Rx and Tx activity.
- * It uses the information stored in the ETH_PORT_INFO struct to
- * initialize the various port registers.
- *
- * Data flow:
- * All packet references to/from the driver are done using PKT_INFO
- * struct.
- * This struct is a unified struct used with Rx and Tx operations.
- * This way the user is not required to be familiar with neither
- * Tx nor Rx descriptors structures.
- * The driver's descriptors rings are management by indexes.
- * Those indexes controls the ring resources and used to indicate
- * a SW resource error:
- * 'current'
- * This index points to the current available resource for use. For
- * example in Rx process this index will point to the descriptor
- * that will be passed to the user upon calling the receive routine.
- * In Tx process, this index will point to the descriptor
- * that will be assigned with the user packet info and transmitted.
- * 'used'
- * This index points to the descriptor that need to restore its
- * resources. For example in Rx process, using the Rx buffer return
- * API will attach the buffer returned in packet info to the
- * descriptor pointed by 'used'. In Tx process, using the Tx
- * descriptor return will merely return the user packet info with
- * the command status of the transmitted buffer pointed by the
- * 'used' index. Nevertheless, it is essential to use this routine
- * to update the 'used' index.
- * 'first'
- * This index supports Tx Scatter-Gather. It points to the first
- * descriptor of a packet assembled of multiple buffers. For example
- * when in middle of Such packet we have a Tx resource error the
- * 'curr' index get the value of 'first' to indicate that the ring
- * returned to its state before trying to transmit this packet.
- *
- * Receive operation:
- * The eth_port_receive API set the packet information struct,
- * passed by the caller, with received information from the
- * 'current' SDMA descriptor.
- * It is the user responsibility to return this resource back
- * to the Rx descriptor ring to enable the reuse of this source.
- * Return Rx resource is done using the eth_rx_return_buff API.
- *
- * Transmit operation:
- * The eth_port_send API supports Scatter-Gather which enables to
- * send a packet spanned over multiple buffers. This means that
- * for each packet info structure given by the user and put into
- * the Tx descriptors ring, will be transmitted only if the 'LAST'
- * bit will be set in the packet info command status field. This
- * API also consider restriction regarding buffer alignments and
- * sizes.
- * The user must return a Tx resource after ensuring the buffer
- * has been transmitted to enable the Tx ring indexes to update.
- *
- * BOARD LAYOUT
- * This device is on-board. No jumper diagram is necessary.
- *
- * EXTERNAL INTERFACE
- *
- * Prior to calling the initialization routine eth_port_init() the user
- * must set the following fields under ETH_PORT_INFO struct:
- * port_num User Ethernet port number.
- * port_phy_addr User PHY address of Ethernet port.
- * port_mac_addr[6] User defined port MAC address.
- * port_config User port configuration value.
- * port_config_extend User port config extend value.
- * port_sdma_config User port SDMA config value.
- * port_serial_control User port serial control value.
- * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr.
- * *port_private User scratch pad for user specific data structures.
- *
- * This driver introduce a set of default values:
- * PORT_CONFIG_VALUE Default port configuration value
- * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value
- * PORT_SDMA_CONFIG_VALUE Default sdma control value
- * PORT_SERIAL_CONTROL_VALUE Default port serial control value
- *
- * This driver data flow is done using the PKT_INFO struct which is
- * a unified struct for Rx and Tx operations:
- * byte_cnt Tx/Rx descriptor buffer byte count.
- * l4i_chk CPU provided TCP Checksum. For Tx operation only.
- * cmd_sts Tx/Rx descriptor command status.
- * buf_ptr Tx/Rx descriptor buffer pointer.
- * return_info Tx/Rx user resource return information.
- *
- *
- * EXTERNAL SUPPORT REQUIREMENTS
- *
- * This driver requires the following external support:
- *
- * D_CACHE_FLUSH_LINE (address, address offset)
- *
- * This macro applies assembly code to flush and invalidate cache
- * line.
- * address - address base.
- * address offset - address offset
- *
- *
- * CPU_PIPE_FLUSH
- *
- * This macro applies assembly code to flush the CPU pipeline.
- *
- *******************************************************************************/
-/* includes */
-
-/* defines */
-/* SDMA command macros */
-#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
- MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
-
-#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
- MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
- (1 << (8 + tx_queue)))
-
-#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
-MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
-
-#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
-MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
-
-#define CURR_RFD_GET(p_curr_desc, queue) \
- ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
-
-#define CURR_RFD_SET(p_curr_desc, queue) \
- (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
-
-#define USED_RFD_GET(p_used_desc, queue) \
- ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
-
-#define USED_RFD_SET(p_used_desc, queue)\
-(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
-
-
-#define CURR_TFD_GET(p_curr_desc, queue) \
- ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
-
-#define CURR_TFD_SET(p_curr_desc, queue) \
- (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
-
-#define USED_TFD_GET(p_used_desc, queue) \
- ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
-
-#define USED_TFD_SET(p_used_desc, queue) \
- (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
-
-#define FIRST_TFD_GET(p_first_desc, queue) \
- ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
-
-#define FIRST_TFD_SET(p_first_desc, queue) \
- (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
-
-
-/* Macros that save access to desc in order to find next desc pointer */
-#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
-
-#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
-
-#define LINK_UP_TIMEOUT 100000
-#define PHY_BUSY_TIMEOUT 10000000
-
-/* locals */
-
-/* PHY routines */
-static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
-static int ethernet_phy_get (ETH_PORT eth_port_num);
-
-/* Ethernet Port routines */
-static void eth_set_access_control (ETH_PORT eth_port_num,
- ETH_WIN_PARAM * param);
-static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
- ETH_QUEUE queue, int option);
-#if 0 /* FIXME */
-static bool eth_port_smc_addr (ETH_PORT eth_port_num,
- unsigned char mc_byte,
- ETH_QUEUE queue, int option);
-static bool eth_port_omc_addr (ETH_PORT eth_port_num,
- unsigned char crc8,
- ETH_QUEUE queue, int option);
-#endif
-
-static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
- int byte_count);
-
-void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
-
-
-typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
-u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
-{
- u32 result = 0;
- u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);
-
- if (enable & (1 << bank))
- return 0;
- if (bank == BANK0)
- result = MV_REG_READ (MV64460_CS_0_BASE_ADDR);
- if (bank == BANK1)
- result = MV_REG_READ (MV64460_CS_1_BASE_ADDR);
- if (bank == BANK2)
- result = MV_REG_READ (MV64460_CS_2_BASE_ADDR);
- if (bank == BANK3)
- result = MV_REG_READ (MV64460_CS_3_BASE_ADDR);
- result &= 0x0000ffff;
- result = result << 16;
- return result;
-}
-
-u32 mv_get_dram_bank_size (MEMORY_BANK bank)
-{
- u32 result = 0;
- u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);
-
- if (enable & (1 << bank))
- return 0;
- if (bank == BANK0)
- result = MV_REG_READ (MV64460_CS_0_SIZE);
- if (bank == BANK1)
- result = MV_REG_READ (MV64460_CS_1_SIZE);
- if (bank == BANK2)
- result = MV_REG_READ (MV64460_CS_2_SIZE);
- if (bank == BANK3)
- result = MV_REG_READ (MV64460_CS_3_SIZE);
- result += 1;
- result &= 0x0000ffff;
- result = result << 16;
- return result;
-}
-
-u32 mv_get_internal_sram_base (void)
-{
- u32 result;
-
- result = MV_REG_READ (MV64460_INTEGRATED_SRAM_BASE_ADDR);
- result &= 0x0000ffff;
- result = result << 16;
- return result;
-}
-
-/*******************************************************************************
-* eth_port_init - Initialize the Ethernet port driver
-*
-* DESCRIPTION:
-* This function prepares the ethernet port to start its activity:
-* 1) Completes the ethernet port driver struct initialization toward port
-* start routine.
-* 2) Resets the device to a quiescent state in case of warm reboot.
-* 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
-* 4) Clean MAC tables. The reset status of those tables is unknown.
-* 5) Set PHY address.
-* Note: Call this routine prior to eth_port_start routine and after setting
-* user values in the user fields of Ethernet port control struct (i.e.
-* port_phy_addr).
-*
-* INPUT:
-* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
-*
-* OUTPUT:
-* See description.
-*
-* RETURN:
-* None.
-*
-*******************************************************************************/
-static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
-{
- int queue;
- ETH_WIN_PARAM win_param;
-
- p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
- p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
- p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
- p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
-
- p_eth_port_ctrl->port_rx_queue_command = 0;
- p_eth_port_ctrl->port_tx_queue_command = 0;
-
- /* Zero out SW structs */
- for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
- CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
- USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
- p_eth_port_ctrl->rx_resource_err[queue] = false;
- }
-
- for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
- CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
- USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
- FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
- p_eth_port_ctrl->tx_resource_err[queue] = false;
- }
-
- eth_port_reset (p_eth_port_ctrl->port_num);
-
- /* Set access parameters for DRAM bank 0 */
- win_param.win = ETH_WIN0; /* Use Ethernet window 0 */
- win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
- win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
- win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
- win_param.high_addr = 0;
- /* Get bank base */
- win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
- win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */
- if (win_param.size == 0)
- win_param.enable = 0;
- else
- win_param.enable = 1; /* Enable the access */
- win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
-
- /* Set the access control for address window (EPAPR) READ & WRITE */
- eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
- /* Set access parameters for DRAM bank 1 */
- win_param.win = ETH_WIN1; /* Use Ethernet window 1 */
- win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
- win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
- win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
- win_param.high_addr = 0;
- /* Get bank base */
- win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
- win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */
- if (win_param.size == 0)
- win_param.enable = 0;
- else
- win_param.enable = 1; /* Enable the access */
- win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
-
- /* Set the access control for address window (EPAPR) READ & WRITE */
- eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
- /* Set access parameters for DRAM bank 2 */
- win_param.win = ETH_WIN2; /* Use Ethernet window 2 */
- win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
- win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
- win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
- win_param.high_addr = 0;
- /* Get bank base */
- win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
- win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */
- if (win_param.size == 0)
- win_param.enable = 0;
- else
- win_param.enable = 1; /* Enable the access */
- win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
-
- /* Set the access control for address window (EPAPR) READ & WRITE */
- eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
- /* Set access parameters for DRAM bank 3 */
- win_param.win = ETH_WIN3; /* Use Ethernet window 3 */
- win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
- win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */
-#ifndef CONFIG_NOT_COHERENT_CACHE
- win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
-#endif
- win_param.high_addr = 0;
- /* Get bank base */
- win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
- win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */
- if (win_param.size == 0)
- win_param.enable = 0;
- else
- win_param.enable = 1; /* Enable the access */
- win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
-
- /* Set the access control for address window (EPAPR) READ & WRITE */
- eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
- /* Set access parameters for Internal SRAM */
- win_param.win = ETH_WIN4; /* Use Ethernet window 0 */
- win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */
- win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
- win_param.high_addr = 0;
- win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */
- win_param.size = MV64460_INTERNAL_SRAM_SIZE; /* Get bank size */
- win_param.enable = 1; /* Enable the access */
- win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
-
- /* Set the access control for address window (EPAPR) READ & WRITE */
- eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
-
- eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
-
- ethernet_phy_set (p_eth_port_ctrl->port_num,
- p_eth_port_ctrl->port_phy_addr);
-
- return;
-
-}
-
-/*******************************************************************************
-* eth_port_start - Start the Ethernet port activity.
-*
-* DESCRIPTION:
-* This routine prepares the Ethernet port for Rx and Tx activity:
-* 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
-* has been initialized a descriptor's ring (using ether_init_tx_desc_ring
-* for Tx and ether_init_rx_desc_ring for Rx)
-* 2. Initialize and enable the Ethernet configuration port by writing to
-* the port's configuration and command registers.
-* 3. Initialize and enable the SDMA by writing to the SDMA's
-* configuration and command registers.
-* After completing these steps, the ethernet port SDMA can starts to
-* perform Rx and Tx activities.
-*
-* Note: Each Rx and Tx queue descriptor's list must be initialized prior
-* to calling this function (use ether_init_tx_desc_ring for Tx queues and
-* ether_init_rx_desc_ring for Rx queues).
-*
-* INPUT:
-* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
-*
-* OUTPUT:
-* Ethernet port is ready to receive and transmit.
-*
-* RETURN:
-* false if the port PHY is not up.
-* true otherwise.
-*
-*******************************************************************************/
-static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
-{
- int queue;
- volatile ETH_TX_DESC *p_tx_curr_desc;
- volatile ETH_RX_DESC *p_rx_curr_desc;
- unsigned int phy_reg_data;
- ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
-
- /* Assignment of Tx CTRP of given queue */
- for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
- CURR_TFD_GET (p_tx_curr_desc, queue);
- MV_REG_WRITE ((MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
- (eth_port_num)
- + (4 * queue)),
- ((unsigned int) p_tx_curr_desc));
-
- }
-
- /* Assignment of Rx CRDP of given queue */
- for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
- CURR_RFD_GET (p_rx_curr_desc, queue);
- MV_REG_WRITE ((MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
- (eth_port_num)
- + (4 * queue)),
- ((unsigned int) p_rx_curr_desc));
-
- if (p_rx_curr_desc != NULL)
- /* Add the assigned Ethernet address to the port's address table */
- eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
- p_eth_port_ctrl->port_mac_addr,
- queue);
- }
-
- /* Assign port configuration and command. */
- MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),
- p_eth_port_ctrl->port_config);
-
- MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
- p_eth_port_ctrl->port_config_extend);
-
- MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
- p_eth_port_ctrl->port_serial_control);
-
- MV_SET_REG_BITS (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
- ETH_SERIAL_PORT_ENABLE);
-
- /* Assign port SDMA configuration */
- MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),
- p_eth_port_ctrl->port_sdma_config);
-
- MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
- (eth_port_num), 0x3fffffff);
- MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
- (eth_port_num), 0x03fffcff);
- /* Turn off the port/queue bandwidth limitation */
- MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
-
- /* Enable port Rx. */
- MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
- p_eth_port_ctrl->port_rx_queue_command);
-
- /* Check if link is up */
- eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
-
- if (!(phy_reg_data & 0x20))
- return false;
-
- return true;
-}
-
-/*******************************************************************************
-* eth_port_uc_addr_set - This function Set the port Unicast address.
-*
-* DESCRIPTION:
-* This function Set the port Ethernet MAC address.
-*
-* INPUT:
-* ETH_PORT eth_port_num Port number.
-* char * p_addr Address to be set
-* ETH_QUEUE queue Rx queue number for this MAC address.
-*
-* OUTPUT:
-* Set MAC address low and high registers. also calls eth_port_uc_addr()
-* To set the unicast table with the proper information.
-*
-* RETURN:
-* N/A.
-*
-*******************************************************************************/
-static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
- unsigned char *p_addr, ETH_QUEUE queue)
-{
- unsigned int mac_h;
- unsigned int mac_l;
-
- mac_l = (p_addr[4] << 8) | (p_addr[5]);
- mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
- (p_addr[2] << 8) | (p_addr[3] << 0);
-
- MV_REG_WRITE (MV64460_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
- MV_REG_WRITE (MV64460_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
-
- /* Accept frames of this address */
- eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
-
- return;
-}
-
-/*******************************************************************************
-* eth_port_uc_addr - This function Set the port unicast address table
-*
-* DESCRIPTION:
-* This function locates the proper entry in the Unicast table for the
-* specified MAC nibble and sets its properties according to function
-* parameters.
-*
-* INPUT:
-* ETH_PORT eth_port_num Port number.
-* unsigned char uc_nibble Unicast MAC Address last nibble.
-* ETH_QUEUE queue Rx queue number for this MAC address.
-* int option 0 = Add, 1 = remove address.
-*
-* OUTPUT:
-* This function add/removes MAC addresses from the port unicast address
-* table.
-*
-* RETURN:
-* true is output succeeded.
-* false if option parameter is invalid.
-*
-*******************************************************************************/
-static bool eth_port_uc_addr (ETH_PORT eth_port_num,
- unsigned char uc_nibble,
- ETH_QUEUE queue, int option)
-{
- unsigned int unicast_reg;
- unsigned int tbl_offset;
- unsigned int reg_offset;
-
- /* Locate the Unicast table entry */
- uc_nibble = (0xf & uc_nibble);
- tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
- reg_offset = uc_nibble % 4; /* Entry offset within the above register */
-
- switch (option) {
- case REJECT_MAC_ADDR:
- /* Clear accepts frame bit at specified unicast DA table entry */
- unicast_reg =
- MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
- (eth_port_num)
- + tbl_offset));
-
- unicast_reg &= (0x0E << (8 * reg_offset));
-
- MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
- (eth_port_num)
- + tbl_offset), unicast_reg);
- break;
-
- case ACCEPT_MAC_ADDR:
- /* Set accepts frame bit at unicast DA filter table entry */
- unicast_reg =
- MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
- (eth_port_num)
- + tbl_offset));
-
- unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
-
- MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
- (eth_port_num)
- + tbl_offset), unicast_reg);
-
- break;
-
- default:
- return false;
- }
- return true;
-}
-
-#if 0 /* FIXME */
-/*******************************************************************************
-* eth_port_mc_addr - Multicast address settings.
-*
-* DESCRIPTION:
-* This API controls the MV device MAC multicast support.
-* The MV device supports multicast using two tables:
-* 1) Special Multicast Table for MAC addresses of the form
-* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
-* The MAC DA[7:0] bits are used as a pointer to the Special Multicast
-* Table entries in the DA-Filter table.
-* In this case, the function calls eth_port_smc_addr() routine to set the
-* Special Multicast Table.
-* 2) Other Multicast Table for multicast of another type. A CRC-8bit
-* is used as an index to the Other Multicast Table entries in the
-* DA-Filter table.
-* In this case, the function calculates the CRC-8bit value and calls
-* eth_port_omc_addr() routine to set the Other Multicast Table.
-* INPUT:
-* ETH_PORT eth_port_num Port number.
-* unsigned char *p_addr Unicast MAC Address.
-* ETH_QUEUE queue Rx queue number for this MAC address.
-* int option 0 = Add, 1 = remove address.
-*
-* OUTPUT:
-* See description.
-*
-* RETURN:
-* true is output succeeded.
-* false if add_address_table_entry( ) failed.
-*
-*******************************************************************************/
-static void eth_port_mc_addr (ETH_PORT eth_port_num,
- unsigned char *p_addr,
- ETH_QUEUE queue, int option)
-{
- unsigned int mac_h;
- unsigned int mac_l;
- unsigned char crc_result = 0;
- int mac_array[48];
- int crc[8];
- int i;
-
- if ((p_addr[0] == 0x01) &&
- (p_addr[1] == 0x00) &&
- (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
-
- eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
- } else {
- /* Calculate CRC-8 out of the given address */
- mac_h = (p_addr[0] << 8) | (p_addr[1]);
- mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
- (p_addr[4] << 8) | (p_addr[5] << 0);
-
- for (i = 0; i < 32; i++)
- mac_array[i] = (mac_l >> i) & 0x1;
- for (i = 32; i < 48; i++)
- mac_array[i] = (mac_h >> (i - 32)) & 0x1;
-
- crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
- mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
- mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
- mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
- mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
- mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
- mac_array[6] ^ mac_array[0];
-
- crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
- mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
- mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
- mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
- mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
- mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
- mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
- mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
- mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
- mac_array[0];
-
- crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
- mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
- mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
- mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
- mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
- mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
- mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
- mac_array[2] ^ mac_array[1] ^ mac_array[0];
-
- crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
- mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
- mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
- mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
- mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
- mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
- mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
- mac_array[2] ^ mac_array[1];
-
- crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
- mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
- mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
- mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
- mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
- mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
- mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
- mac_array[2];
-
- crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
- mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
- mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
- mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
- mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
- mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
- mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
- mac_array[3];
-
- crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
- mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
- mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
- mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
- mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
- mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
- mac_array[6] ^ mac_array[5] ^ mac_array[4];
-
- crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
- mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
- mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
- mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
- mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
- mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
- mac_array[6] ^ mac_array[5];
-
- for (i = 0; i < 8; i++)
- crc_result = crc_result | (crc[i] << i);
-
- eth_port_omc_addr (eth_port_num, crc_result, queue, option);
- }
- return;
-}
-
-/*******************************************************************************
-* eth_port_smc_addr - Special Multicast address settings.
-*
-* DESCRIPTION:
-* This routine controls the MV device special MAC multicast support.
-* The Special Multicast Table for MAC addresses supports MAC of the form
-* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
-* The MAC DA[7:0] bits are used as a pointer to the Special Multicast
-* Table entries in the DA-Filter table.
-* This function set the Special Multicast Table appropriate entry
-* according to the argument given.
-*
-* INPUT:
-* ETH_PORT eth_port_num Port number.
-* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits).
-* ETH_QUEUE queue Rx queue number for this MAC address.
-* int option 0 = Add, 1 = remove address.
-*
-* OUTPUT:
-* See description.
-*
-* RETURN:
-* true is output succeeded.
-* false if option parameter is invalid.
-*
-*******************************************************************************/
-static bool eth_port_smc_addr (ETH_PORT eth_port_num,
- unsigned char mc_byte,
- ETH_QUEUE queue, int option)
-{
- unsigned int smc_table_reg;
- unsigned int tbl_offset;
- unsigned int reg_offset;
-
- /* Locate the SMC table entry */
- tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */
- reg_offset = mc_byte % 4; /* Entry offset within the above register */
- queue &= 0x7;
-
- switch (option) {
- case REJECT_MAC_ADDR:
- /* Clear accepts frame bit at specified Special DA table entry */
- smc_table_reg =
- MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
- smc_table_reg &= (0x0E << (8 * reg_offset));
-
- MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
- break;
-
- case ACCEPT_MAC_ADDR:
- /* Set accepts frame bit at specified Special DA table entry */
- smc_table_reg =
- MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
- smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
-
- MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
- break;
-
- default:
- return false;
- }
- return true;
-}
-
-/*******************************************************************************
-* eth_port_omc_addr - Multicast address settings.
-*
-* DESCRIPTION:
-* This routine controls the MV device Other MAC multicast support.
-* The Other Multicast Table is used for multicast of another type.
-* A CRC-8bit is used as an index to the Other Multicast Table entries
-* in the DA-Filter table.
-* The function gets the CRC-8bit value from the calling routine and
-* set the Other Multicast Table appropriate entry according to the
-* CRC-8 argument given.
-*
-* INPUT:
-* ETH_PORT eth_port_num Port number.
-* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
-* ETH_QUEUE queue Rx queue number for this MAC address.
-* int option 0 = Add, 1 = remove address.
-*
-* OUTPUT:
-* See description.
-*
-* RETURN:
-* true is output succeeded.
-* false if option parameter is invalid.
-*
-*******************************************************************************/
-static bool eth_port_omc_addr (ETH_PORT eth_port_num,
- unsigned char crc8,
- ETH_QUEUE queue, int option)
-{
- unsigned int omc_table_reg;
- unsigned int tbl_offset;
- unsigned int reg_offset;
-
- /* Locate the OMC table entry */
- tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
- reg_offset = crc8 % 4; /* Entry offset within the above register */
- queue &= 0x7;
-
- switch (option) {
- case REJECT_MAC_ADDR:
- /* Clear accepts frame bit at specified Other DA table entry */
- omc_table_reg =
- MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
- omc_table_reg &= (0x0E << (8 * reg_offset));
-
- MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
- break;
-
- case ACCEPT_MAC_ADDR:
- /* Set accepts frame bit at specified Other DA table entry */
- omc_table_reg =
- MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
- omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
-
- MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
- break;
-
- default:
- return false;
- }
- return true;
-}
-#endif
-
-/*******************************************************************************
-* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
-*
-* DESCRIPTION:
-* Go through all the DA filter tables (Unicast, Special Multicast & Other
-* Multicast) and set each entry to 0.
-*
-* INPUT:
-* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
-*
-* OUTPUT:
-* Multicast and Unicast packets are rejected.
-*
-* RETURN:
-* None.
-*
-*******************************************************************************/
-static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
-{
- int table_index;
-
- /* Clear DA filter unicast table (Ex_dFUT) */
- for (table_index = 0; table_index <= 0xC; table_index += 4)
- MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
- (eth_port_num) + table_index), 0);
-
- for (table_index = 0; table_index <= 0xFC; table_index += 4) {
- /* Clear DA filter special multicast table (Ex_dFSMT) */
- MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
- /* Clear DA filter other multicast table (Ex_dFOMT) */
- MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
- }
-}
-
-/*******************************************************************************
-* eth_clear_mib_counters - Clear all MIB counters
-*
-* DESCRIPTION:
-* This function clears all MIB counters of a specific ethernet port.
-* A read from the MIB counter will reset the counter.
-*
-* INPUT:
-* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
-*
-* OUTPUT:
-* After reading all MIB counters, the counters resets.
-*
-* RETURN:
-* MIB counter value.
-*
-*******************************************************************************/
-static void eth_clear_mib_counters (ETH_PORT eth_port_num)
-{
- int i;
-
- /* Perform dummy reads from MIB counters */
- for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
- i += 4) {
- (void)MV_REG_READ ((MV64460_ETH_MIB_COUNTERS_BASE
- (eth_port_num) + i));
- }
-
- return;
-}
-
-/*******************************************************************************
-* eth_read_mib_counter - Read a MIB counter
-*
-* DESCRIPTION:
-* This function reads a MIB counter of a specific ethernet port.
-* NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
-* following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
-* register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
-* ETH_MIB_GOOD_OCTETS_SENT_HIGH
-*
-* INPUT:
-* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
-* unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros).
-*
-* OUTPUT:
-* After reading the MIB counter, the counter resets.
-*
-* RETURN:
-* MIB counter value.
-*
-*******************************************************************************/
-unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
- unsigned int mib_offset)
-{
- return (MV_REG_READ (MV64460_ETH_MIB_COUNTERS_BASE (eth_port_num)
- + mib_offset));
-}
-
-/*******************************************************************************
-* ethernet_phy_set - Set the ethernet port PHY address.
-*
-* DESCRIPTION:
-* This routine set the ethernet port PHY address according to given
-* parameter.
-*
-* INPUT:
-* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
-*
-* OUTPUT:
-* Set PHY Address Register with given PHY address parameter.
-*
-* RETURN:
-* None.
-*
-*******************************************************************************/
-static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
-{
- unsigned int reg_data;
-
- reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);
-
- reg_data &= ~(0x1F << (5 * eth_port_num));
- reg_data |= (phy_addr << (5 * eth_port_num));
-
- MV_REG_WRITE (MV64460_ETH_PHY_ADDR_REG, reg_data);
-
- return;
-}
-
-/*******************************************************************************
- * ethernet_phy_get - Get the ethernet port PHY address.
- *
- * DESCRIPTION:
- * This routine returns the given ethernet port PHY address.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- * None.
- *
- * RETURN:
- * PHY address.
- *
- *******************************************************************************/
-static int ethernet_phy_get (ETH_PORT eth_port_num)
-{
- unsigned int reg_data;
-
- reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);
-
- return ((reg_data >> (5 * eth_port_num)) & 0x1f);
-}
-
-/***********************************************************/
-/* (Re)start autonegotiation */
-/***********************************************************/
-int phy_setup_aneg (char *devname, unsigned char addr)
-{
- unsigned short ctl, adv;
-
- /* Setup standard advertise */
- miiphy_read (devname, addr, MII_ADVERTISE, &adv);
- adv |= (LPA_LPACK | LPA_RFAULT | LPA_100BASE4 |
- LPA_100FULL | LPA_100HALF | LPA_10FULL |
- LPA_10HALF);
- miiphy_write (devname, addr, MII_ADVERTISE, adv);
-
- miiphy_read (devname, addr, MII_CTRL1000, &adv);
- adv |= (0x0300);
- miiphy_write (devname, addr, MII_CTRL1000, adv);
-
- /* Start/Restart aneg */
- miiphy_read (devname, addr, MII_BMCR, &ctl);
- ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
- miiphy_write (devname, addr, MII_BMCR, ctl);
-
- return 0;
-}
-
-/*******************************************************************************
- * ethernet_phy_reset - Reset Ethernet port PHY.
- *
- * DESCRIPTION:
- * This routine utilize the SMI interface to reset the ethernet port PHY.
- * The routine waits until the link is up again or link up is timeout.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- * The ethernet port PHY renew its link.
- *
- * RETURN:
- * None.
- *
- *******************************************************************************/
-static bool ethernet_phy_reset (ETH_PORT eth_port_num)
-{
- unsigned int time_out = 50;
- unsigned int phy_reg_data;
-
- eth_port_read_smi_reg (eth_port_num, 20, &phy_reg_data);
- phy_reg_data |= 0x0083; /* Set bit 7 to 1 for different RGMII timing */
- eth_port_write_smi_reg (eth_port_num, 20, phy_reg_data);
-
- /* Reset the PHY */
- eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
- phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
- eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
-
- /* Poll on the PHY LINK */
- do {
- eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
-
- if (time_out-- == 0)
- return false;
- }
- while (!(phy_reg_data & 0x20));
-
- return true;
-}
-
-/*******************************************************************************
- * eth_port_reset - Reset Ethernet port
- *
- * DESCRIPTION:
- * This routine resets the chip by aborting any SDMA engine activity and
- * clearing the MIB counters. The Receiver and the Transmit unit are in
- * idle state after this command is performed and the port is disabled.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- * Channel activity is halted.
- *
- * RETURN:
- * None.
- *
- *******************************************************************************/
-static void eth_port_reset (ETH_PORT eth_port_num)
-{
- unsigned int reg_data;
-
- /* Stop Tx port activity. Check port Tx activity. */
- reg_data =
- MV_REG_READ (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
- (eth_port_num));
-
- if (reg_data & 0xFF) {
- /* Issue stop command for active channels only */
- MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
- (eth_port_num), (reg_data << 8));
-
- /* Wait for all Tx activity to terminate. */
- do {
- /* Check port cause register that all Tx queues are stopped */
- reg_data =
- MV_REG_READ
- (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
- (eth_port_num));
- }
- while (reg_data & 0xFF);
- }
-
- /* Stop Rx port activity. Check port Rx activity. */
- reg_data =
- MV_REG_READ (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
- (eth_port_num));
-
- if (reg_data & 0xFF) {
- /* Issue stop command for active channels only */
- MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
- (eth_port_num), (reg_data << 8));
-
- /* Wait for all Rx activity to terminate. */
- do {
- /* Check port cause register that all Rx queues are stopped */
- reg_data =
- MV_REG_READ
- (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
- (eth_port_num));
- }
- while (reg_data & 0xFF);
- }
-
- /* Clear all MIB counters */
- eth_clear_mib_counters (eth_port_num);
-
- /* Reset the Enable bit in the Configuration Register */
- reg_data =
- MV_REG_READ (MV64460_ETH_PORT_SERIAL_CONTROL_REG
- (eth_port_num));
- reg_data &= ~ETH_SERIAL_PORT_ENABLE;
- MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
- reg_data);
-
- return;
-}
-
-#if 0 /* Not needed here */
-/*******************************************************************************
- * ethernet_set_config_reg - Set specified bits in configuration register.
- *
- * DESCRIPTION:
- * This function sets specified bits in the given ethernet
- * configuration register.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- * unsigned int value 32 bit value.
- *
- * OUTPUT:
- * The set bits in the value parameter are set in the configuration
- * register.
- *
- * RETURN:
- * None.
- *
- *******************************************************************************/
-static void ethernet_set_config_reg (ETH_PORT eth_port_num,
- unsigned int value)
-{
- unsigned int eth_config_reg;
-
- eth_config_reg =
- MV_REG_READ (MV64460_ETH_PORT_CONFIG_REG (eth_port_num));
- eth_config_reg |= value;
- MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),
- eth_config_reg);
-
- return;
-}
-#endif
-
-#if 0 /* FIXME */
-/*******************************************************************************
- * ethernet_reset_config_reg - Reset specified bits in configuration register.
- *
- * DESCRIPTION:
- * This function resets specified bits in the given Ethernet
- * configuration register.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- * unsigned int value 32 bit value.
- *
- * OUTPUT:
- * The set bits in the value parameter are reset in the configuration
- * register.
- *
- * RETURN:
- * None.
- *
- *******************************************************************************/
-static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
- unsigned int value)
-{
- unsigned int eth_config_reg;
-
- eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG
- (eth_port_num));
- eth_config_reg &= ~value;
- MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
- eth_config_reg);
-
- return;
-}
-#endif
-
-#if 0 /* Not needed here */
-/*******************************************************************************
- * ethernet_get_config_reg - Get the port configuration register
- *
- * DESCRIPTION:
- * This function returns the configuration register value of the given
- * ethernet port.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- *
- * OUTPUT:
- * None.
- *
- * RETURN:
- * Port configuration register value.
- *
- *******************************************************************************/
-static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
-{
- unsigned int eth_config_reg;
-
- eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG
- (eth_port_num));
- return eth_config_reg;
-}
-
-#endif
-
-/*******************************************************************************
- * eth_port_read_smi_reg - Read PHY registers
- *
- * DESCRIPTION:
- * This routine utilize the SMI interface to interact with the PHY in
- * order to perform PHY register read.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- * unsigned int phy_reg PHY register address offset.
- * unsigned int *value Register value buffer.
- *
- * OUTPUT:
- * Write the value of a specified PHY register into given buffer.
- *
- * RETURN:
- * false if the PHY is busy or read data is not in valid state.
- * true otherwise.
- *
- *******************************************************************************/
-static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
- unsigned int phy_reg, unsigned int *value)
-{
- unsigned int reg_value;
- unsigned int time_out = PHY_BUSY_TIMEOUT;
- int phy_addr;
-
- phy_addr = ethernet_phy_get (eth_port_num);
-
- /* first check that it is not busy */
- do {
- reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
- if (time_out-- == 0) {
- return false;
- }
- }
- while (reg_value & ETH_SMI_BUSY);
-
- /* not busy */
-
- MV_REG_WRITE (MV64460_ETH_SMI_REG,
- (phy_addr << 16) | (phy_reg << 21) |
- ETH_SMI_OPCODE_READ);
-
- time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */
-
- do {
- reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
- if (time_out-- == 0) {
- return false;
- }
- }
- while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */
-
- /* Wait for the data to update in the SMI register */
-#define PHY_UPDATE_TIMEOUT 10000
- for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
-
- reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
-
- *value = reg_value & 0xffff;
-
- return true;
-}
-
-int mv_miiphy_read(const char *devname, unsigned char phy_addr,
- unsigned char phy_reg, unsigned short *value)
-{
- unsigned int reg_value;
- unsigned int time_out = PHY_BUSY_TIMEOUT;
-
- /* first check that it is not busy */
- do {
- reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
- if (time_out-- == 0) {
- return false;
- }
- }
- while (reg_value & ETH_SMI_BUSY);
-
- /* not busy */
- MV_REG_WRITE (MV64460_ETH_SMI_REG,
- (phy_addr << 16) | (phy_reg << 21) |
- ETH_SMI_OPCODE_READ);
-
- time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */
-
- do {
- reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
- if (time_out-- == 0) {
- return false;
- }
- }
- while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */
-
- /* Wait for the data to update in the SMI register */
- for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
-
- reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
-
- *value = reg_value & 0xffff;
-
- return 0;
-}
-
-/*******************************************************************************
- * eth_port_write_smi_reg - Write to PHY registers
- *
- * DESCRIPTION:
- * This routine utilize the SMI interface to interact with the PHY in
- * order to perform writes to PHY registers.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- * unsigned int phy_reg PHY register address offset.
- * unsigned int value Register value.
- *
- * OUTPUT:
- * Write the given value to the specified PHY register.
- *
- * RETURN:
- * false if the PHY is busy.
- * true otherwise.
- *
- *******************************************************************************/
-static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
- unsigned int phy_reg, unsigned int value)
-{
- unsigned int reg_value;
- unsigned int time_out = PHY_BUSY_TIMEOUT;
- int phy_addr;
-
- phy_addr = ethernet_phy_get (eth_port_num);
-
- /* first check that it is not busy */
- do {
- reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
- if (time_out-- == 0) {
- return false;
- }
- }
- while (reg_value & ETH_SMI_BUSY);
-
- /* not busy */
- MV_REG_WRITE (MV64460_ETH_SMI_REG,
- (phy_addr << 16) | (phy_reg << 21) |
- ETH_SMI_OPCODE_WRITE | (value & 0xffff));
- return true;
-}
-
-int mv_miiphy_write(const char *devname, unsigned char phy_addr,
- unsigned char phy_reg, unsigned short value)
-{
- unsigned int reg_value;
- unsigned int time_out = PHY_BUSY_TIMEOUT;
-
- /* first check that it is not busy */
- do {
- reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
- if (time_out-- == 0) {
- return false;
- }
- }
- while (reg_value & ETH_SMI_BUSY);
-
- /* not busy */
- MV_REG_WRITE (MV64460_ETH_SMI_REG,
- (phy_addr << 16) | (phy_reg << 21) |
- ETH_SMI_OPCODE_WRITE | (value & 0xffff));
- return 0;
-}
-
-/*******************************************************************************
- * eth_set_access_control - Config address decode parameters for Ethernet unit
- *
- * DESCRIPTION:
- * This function configures the address decode parameters for the Gigabit
- * Ethernet Controller according the given parameters struct.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
- * ETH_WIN_PARAM *param Address decode parameter struct.
- *
- * OUTPUT:
- * An access window is opened using the given access parameters.
- *
- * RETURN:
- * None.
- *
- *******************************************************************************/
-static void eth_set_access_control (ETH_PORT eth_port_num,
- ETH_WIN_PARAM * param)
-{
- unsigned int access_prot_reg;
-
- /* Set access control register */
- access_prot_reg = MV_REG_READ (MV64460_ETH_ACCESS_PROTECTION_REG
- (eth_port_num));
- access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */
- access_prot_reg |= (param->access_ctrl << (param->win * 2));
- MV_REG_WRITE (MV64460_ETH_ACCESS_PROTECTION_REG (eth_port_num),
- access_prot_reg);
-
- /* Set window Size reg (SR) */
- MV_REG_WRITE ((MV64460_ETH_SIZE_REG_0 +
- (ETH_SIZE_REG_GAP * param->win)),
- (((param->size / 0x10000) - 1) << 16));
-
- /* Set window Base address reg (BA) */
- MV_REG_WRITE ((MV64460_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
- (param->target | param->attributes | param->base_addr));
- /* High address remap reg (HARR) */
- if (param->win < 4)
- MV_REG_WRITE ((MV64460_ETH_HIGH_ADDR_REMAP_REG_0 +
- (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
- param->high_addr);
-
- /* Base address enable reg (BARER) */
- if (param->enable == 1)
- MV_RESET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,
- (1 << param->win));
- else
- MV_SET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,
- (1 << param->win));
-}
-
-/*******************************************************************************
- * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
- *
- * DESCRIPTION:
- * This function prepares a Rx chained list of descriptors and packet
- * buffers in a form of a ring. The routine must be called after port
- * initialization routine and before port start routine.
- * The Ethernet SDMA engine uses CPU bus addresses to access the various
- * devices in the system (i.e. DRAM). This function uses the ethernet
- * struct 'virtual to physical' routine (set by the user) to set the ring
- * with physical addresses.
- *
- * INPUT:
- * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
- * ETH_QUEUE rx_queue Number of Rx queue.
- * int rx_desc_num Number of Rx descriptors
- * int rx_buff_size Size of Rx buffer
- * unsigned int rx_desc_base_addr Rx descriptors memory area base addr.
- * unsigned int rx_buff_base_addr Rx buffer memory area base addr.
- *
- * OUTPUT:
- * The routine updates the Ethernet port control struct with information
- * regarding the Rx descriptors and buffers.
- *
- * RETURN:
- * false if the given descriptors memory area is not aligned according to
- * Ethernet SDMA specifications.
- * true otherwise.
- *
- *******************************************************************************/
-static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
- ETH_QUEUE rx_queue,
- int rx_desc_num,
- int rx_buff_size,
- unsigned int rx_desc_base_addr,
- unsigned int rx_buff_base_addr)
-{
- ETH_RX_DESC *p_rx_desc;
- ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */
- unsigned int buffer_addr;
- int ix; /* a counter */
-
- p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
- p_rx_prev_desc = p_rx_desc;
- buffer_addr = rx_buff_base_addr;
-
- /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
- if (rx_buff_base_addr & 0xF)
- return false;
-
- /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */
- if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
- return false;
-
- /* Rx buffers must be 64-bit aligned. */
- if ((rx_buff_base_addr + rx_buff_size) & 0x7)
- return false;
-
- /* initialize the Rx descriptors ring */
- for (ix = 0; ix < rx_desc_num; ix++) {
- p_rx_desc->buf_size = rx_buff_size;
- p_rx_desc->byte_cnt = 0x0000;
- p_rx_desc->cmd_sts =
- ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
- p_rx_desc->next_desc_ptr =
- ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
- p_rx_desc->buf_ptr = buffer_addr;
- p_rx_desc->return_info = 0x00000000;
- D_CACHE_FLUSH_LINE (p_rx_desc, 0);
- buffer_addr += rx_buff_size;
- p_rx_prev_desc = p_rx_desc;
- p_rx_desc = (ETH_RX_DESC *)
- ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
- }
-
- /* Closing Rx descriptors ring */
- p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
- D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
-
- /* Save Rx desc pointer to driver struct. */
- CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
- USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
-
- p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
- (ETH_RX_DESC *) rx_desc_base_addr;
- p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
- rx_desc_num * RX_DESC_ALIGNED_SIZE;
-
- p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
-
- return true;
-}
-
-/*******************************************************************************
- * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
- *
- * DESCRIPTION:
- * This function prepares a Tx chained list of descriptors and packet
- * buffers in a form of a ring. The routine must be called after port
- * initialization routine and before port start routine.
- * The Ethernet SDMA engine uses CPU bus addresses to access the various
- * devices in the system (i.e. DRAM). This function uses the ethernet
- * struct 'virtual to physical' routine (set by the user) to set the ring
- * with physical addresses.
- *
- * INPUT:
- * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
- * ETH_QUEUE tx_queue Number of Tx queue.
- * int tx_desc_num Number of Tx descriptors
- * int tx_buff_size Size of Tx buffer
- * unsigned int tx_desc_base_addr Tx descriptors memory area base addr.
- * unsigned int tx_buff_base_addr Tx buffer memory area base addr.
- *
- * OUTPUT:
- * The routine updates the Ethernet port control struct with information
- * regarding the Tx descriptors and buffers.
- *
- * RETURN:
- * false if the given descriptors memory area is not aligned according to
- * Ethernet SDMA specifications.
- * true otherwise.
- *
- *******************************************************************************/
-static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
- ETH_QUEUE tx_queue,
- int tx_desc_num,
- int tx_buff_size,
- unsigned int tx_desc_base_addr,
- unsigned int tx_buff_base_addr)
-{
-
- ETH_TX_DESC *p_tx_desc;
- ETH_TX_DESC *p_tx_prev_desc;
- unsigned int buffer_addr;
- int ix; /* a counter */
-
- /* save the first desc pointer to link with the last descriptor */
- p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
- p_tx_prev_desc = p_tx_desc;
- buffer_addr = tx_buff_base_addr;
-
- /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
- if (tx_buff_base_addr & 0xF)
- return false;
-
- /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */
- if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
- || (tx_buff_size < TX_BUFFER_MIN_SIZE))
- return false;
-
- /* Initialize the Tx descriptors ring */
- for (ix = 0; ix < tx_desc_num; ix++) {
- p_tx_desc->byte_cnt = 0x0000;
- p_tx_desc->l4i_chk = 0x0000;
- p_tx_desc->cmd_sts = 0x00000000;
- p_tx_desc->next_desc_ptr =
- ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
-
- p_tx_desc->buf_ptr = buffer_addr;
- p_tx_desc->return_info = 0x00000000;
- D_CACHE_FLUSH_LINE (p_tx_desc, 0);
- buffer_addr += tx_buff_size;
- p_tx_prev_desc = p_tx_desc;
- p_tx_desc = (ETH_TX_DESC *)
- ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
-
- }
- /* Closing Tx descriptors ring */
- p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
- D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
- /* Set Tx desc pointer in driver struct. */
- CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
- USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
-
- /* Init Tx ring base and size parameters */
- p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
- (ETH_TX_DESC *) tx_desc_base_addr;
- p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
- (tx_desc_num * TX_DESC_ALIGNED_SIZE);
-
- /* Add the queue to the list of Tx queues of this port */
- p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
-
- return true;
-}
-
-/*******************************************************************************
- * eth_port_send - Send an Ethernet packet
- *
- * DESCRIPTION:
- * This routine send a given packet described by p_pktinfo parameter. It
- * supports transmitting of a packet spaned over multiple buffers. The
- * routine updates 'curr' and 'first' indexes according to the packet
- * segment passed to the routine. In case the packet segment is first,
- * the 'first' index is update. In any case, the 'curr' index is updated.
- * If the routine get into Tx resource error it assigns 'curr' index as
- * 'first'. This way the function can abort Tx process of multiple
- * descriptors per packet.
- *
- * INPUT:
- * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
- * ETH_QUEUE tx_queue Number of Tx queue.
- * PKT_INFO *p_pkt_info User packet buffer.
- *
- * OUTPUT:
- * Tx ring 'curr' and 'first' indexes are updated.
- *
- * RETURN:
- * ETH_QUEUE_FULL in case of Tx resource error.
- * ETH_ERROR in case the routine can not access Tx desc ring.
- * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
- * ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
- ETH_QUEUE tx_queue,
- PKT_INFO * p_pkt_info)
-{
- volatile ETH_TX_DESC *p_tx_desc_first;
- volatile ETH_TX_DESC *p_tx_desc_curr;
- volatile ETH_TX_DESC *p_tx_next_desc_curr;
- volatile ETH_TX_DESC *p_tx_desc_used;
- unsigned int command_status;
-
- /* Do not process Tx ring in case of Tx ring resource error */
- if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
- return ETH_QUEUE_FULL;
-
- /* Get the Tx Desc ring indexes */
- CURR_TFD_GET (p_tx_desc_curr, tx_queue);
- USED_TFD_GET (p_tx_desc_used, tx_queue);
-
- if (p_tx_desc_curr == NULL)
- return ETH_ERROR;
-
- /* The following parameters are used to save readings from memory */
- p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
- command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
-
- if (command_status & (ETH_TX_FIRST_DESC)) {
- /* Update first desc */
- FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
- p_tx_desc_first = p_tx_desc_curr;
- } else {
- FIRST_TFD_GET (p_tx_desc_first, tx_queue);
- command_status |= ETH_BUFFER_OWNED_BY_DMA;
- }
-
- /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
- /* boundary. We use the memory allocated for Tx descriptor. This memory */
- /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
- if (p_pkt_info->byte_cnt <= 8) {
- printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */
- return ETH_ERROR;
-
- p_tx_desc_curr->buf_ptr =
- (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
- eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
- p_pkt_info->byte_cnt);
- } else
- p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
-
- p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
- p_tx_desc_curr->return_info = p_pkt_info->return_info;
-
- if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
- /* Set last desc with DMA ownership and interrupt enable. */
- p_tx_desc_curr->cmd_sts = command_status |
- ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
-
- if (p_tx_desc_curr != p_tx_desc_first)
- p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
-
- /* Flush CPU pipe */
-
- D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
- D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
- CPU_PIPE_FLUSH;
-
- /* Apply send command */
- ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
-
- /* Finish Tx packet. Update first desc in case of Tx resource error */
- p_tx_desc_first = p_tx_next_desc_curr;
- FIRST_TFD_SET (p_tx_desc_first, tx_queue);
-
- } else {
- p_tx_desc_curr->cmd_sts = command_status;
- D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
- }
-
- /* Check for ring index overlap in the Tx desc ring */
- if (p_tx_next_desc_curr == p_tx_desc_used) {
- /* Update the current descriptor */
- CURR_TFD_SET (p_tx_desc_first, tx_queue);
-
- p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
- return ETH_QUEUE_LAST_RESOURCE;
- } else {
- /* Update the current descriptor */
- CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
- return ETH_OK;
- }
-}
-
-/*******************************************************************************
- * eth_tx_return_desc - Free all used Tx descriptors
- *
- * DESCRIPTION:
- * This routine returns the transmitted packet information to the caller.
- * It uses the 'first' index to support Tx desc return in case a transmit
- * of a packet spanned over multiple buffer still in process.
- * In case the Tx queue was in "resource error" condition, where there are
- * no available Tx resources, the function resets the resource error flag.
- *
- * INPUT:
- * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
- * ETH_QUEUE tx_queue Number of Tx queue.
- * PKT_INFO *p_pkt_info User packet buffer.
- *
- * OUTPUT:
- * Tx ring 'first' and 'used' indexes are updated.
- *
- * RETURN:
- * ETH_ERROR in case the routine can not access Tx desc ring.
- * ETH_RETRY in case there is transmission in process.
- * ETH_END_OF_JOB if the routine has nothing to release.
- * ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
- p_eth_port_ctrl,
- ETH_QUEUE tx_queue,
- PKT_INFO * p_pkt_info)
-{
- volatile ETH_TX_DESC *p_tx_desc_used = NULL;
- volatile ETH_TX_DESC *p_tx_desc_first = NULL;
- unsigned int command_status;
-
- /* Get the Tx Desc ring indexes */
- USED_TFD_GET (p_tx_desc_used, tx_queue);
- FIRST_TFD_GET (p_tx_desc_first, tx_queue);
-
- /* Sanity check */
- if (p_tx_desc_used == NULL)
- return ETH_ERROR;
-
- command_status = p_tx_desc_used->cmd_sts;
-
- /* Still transmitting... */
- if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
- D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
- return ETH_RETRY;
- }
-
- /* Stop release. About to overlap the current available Tx descriptor */
- if ((p_tx_desc_used == p_tx_desc_first) &&
- (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
- D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
- return ETH_END_OF_JOB;
- }
-
- /* Pass the packet information to the caller */
- p_pkt_info->cmd_sts = command_status;
- p_pkt_info->return_info = p_tx_desc_used->return_info;
- p_tx_desc_used->return_info = 0;
-
- /* Update the next descriptor to release. */
- USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
-
- /* Any Tx return cancels the Tx resource error status */
- if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
- p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
-
- D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
-
- return ETH_OK;
-
-}
-
-/*******************************************************************************
- * eth_port_receive - Get received information from Rx ring.
- *
- * DESCRIPTION:
- * This routine returns the received data to the caller. There is no
- * data copying during routine operation. All information is returned
- * using pointer to packet information struct passed from the caller.
- * If the routine exhausts Rx ring resources then the resource error flag
- * is set.
- *
- * INPUT:
- * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
- * ETH_QUEUE rx_queue Number of Rx queue.
- * PKT_INFO *p_pkt_info User packet buffer.
- *
- * OUTPUT:
- * Rx ring current and used indexes are updated.
- *
- * RETURN:
- * ETH_ERROR in case the routine can not access Rx desc ring.
- * ETH_QUEUE_FULL if Rx ring resources are exhausted.
- * ETH_END_OF_JOB if there is no received data.
- * ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
- ETH_QUEUE rx_queue,
- PKT_INFO * p_pkt_info)
-{
- volatile ETH_RX_DESC *p_rx_curr_desc;
- volatile ETH_RX_DESC *p_rx_next_curr_desc;
- volatile ETH_RX_DESC *p_rx_used_desc;
- unsigned int command_status;
-
- /* Do not process Rx ring in case of Rx ring resource error */
- if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
- printf ("\nRx Queue is full ...\n");
- return ETH_QUEUE_FULL;
- }
-
- /* Get the Rx Desc ring 'curr and 'used' indexes */
- CURR_RFD_GET (p_rx_curr_desc, rx_queue);
- USED_RFD_GET (p_rx_used_desc, rx_queue);
-
- /* Sanity check */
- if (p_rx_curr_desc == NULL)
- return ETH_ERROR;
-
- /* The following parameters are used to save readings from memory */
- p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
- command_status = p_rx_curr_desc->cmd_sts;
-
- /* Nothing to receive... */
- if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
-/* DP(printf("Rx: command_status: %08x\n", command_status)); */
- D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
-/* DP(printf("\nETH_END_OF_JOB ...\n"));*/
- return ETH_END_OF_JOB;
- }
-
- p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
- p_pkt_info->cmd_sts = command_status;
- p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
- p_pkt_info->return_info = p_rx_curr_desc->return_info;
- p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */
-
- /* Clean the return info field to indicate that the packet has been */
- /* moved to the upper layers */
- p_rx_curr_desc->return_info = 0;
-
- /* Update 'curr' in data structure */
- CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
-
- /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
- if (p_rx_next_curr_desc == p_rx_used_desc)
- p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
-
- D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
- CPU_PIPE_FLUSH;
-
- return ETH_OK;
-}
-
-/*******************************************************************************
- * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
- *
- * DESCRIPTION:
- * This routine returns a Rx buffer back to the Rx ring. It retrieves the
- * next 'used' descriptor and attached the returned buffer to it.
- * In case the Rx ring was in "resource error" condition, where there are
- * no available Rx resources, the function resets the resource error flag.
- *
- * INPUT:
- * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
- * ETH_QUEUE rx_queue Number of Rx queue.
- * PKT_INFO *p_pkt_info Information on the returned buffer.
- *
- * OUTPUT:
- * New available Rx resource in Rx descriptor ring.
- *
- * RETURN:
- * ETH_ERROR in case the routine can not access Rx desc ring.
- * ETH_OK otherwise.
- *
- *******************************************************************************/
-static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
- p_eth_port_ctrl,
- ETH_QUEUE rx_queue,
- PKT_INFO * p_pkt_info)
-{
- volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */
-
- /* Get 'used' Rx descriptor */
- USED_RFD_GET (p_used_rx_desc, rx_queue);
-
- /* Sanity check */
- if (p_used_rx_desc == NULL)
- return ETH_ERROR;
-
- p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
- p_used_rx_desc->return_info = p_pkt_info->return_info;
- p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
- p_used_rx_desc->buf_size = MV64460_RX_BUFFER_SIZE; /* Reset Buffer size */
-
- /* Flush the write pipe */
- CPU_PIPE_FLUSH;
-
- /* Return the descriptor to DMA ownership */
- p_used_rx_desc->cmd_sts =
- ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
-
- /* Flush descriptor and CPU pipe */
- D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
- CPU_PIPE_FLUSH;
-
- /* Move the used descriptor pointer to the next descriptor */
- USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
-
- /* Any Rx return cancels the Rx resource error status */
- if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
- p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
-
- return ETH_OK;
-}
-
-/*******************************************************************************
- * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
- *
- * DESCRIPTION:
- * This routine sets the RX coalescing interrupt mechanism parameter.
- * This parameter is a timeout counter, that counts in 64 t_clk
- * chunks ; that when timeout event occurs a maskable interrupt
- * occurs.
- * The parameter is calculated using the tClk of the MV-643xx chip
- * , and the required delay of the interrupt in usec.
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet port number
- * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
- * unsigned int delay Delay in usec
- *
- * OUTPUT:
- * Interrupt coalescing mechanism value is set in MV-643xx chip.
- *
- * RETURN:
- * The interrupt coalescing value set in the gigE port.
- *
- *******************************************************************************/
-#if 0 /* FIXME */
-static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
- unsigned int t_clk,
- unsigned int delay)
-{
- unsigned int coal;
-
- coal = ((t_clk / 1000000) * delay) / 64;
- /* Set RX Coalescing mechanism */
- MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),
- ((coal & 0x3fff) << 8) |
- (MV_REG_READ
- (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num))
- & 0xffc000ff));
- return coal;
-}
-
-#endif
-/*******************************************************************************
- * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
- *
- * DESCRIPTION:
- * This routine sets the TX coalescing interrupt mechanism parameter.
- * This parameter is a timeout counter, that counts in 64 t_clk
- * chunks ; that when timeout event occurs a maskable interrupt
- * occurs.
- * The parameter is calculated using the t_cLK frequency of the
- * MV-643xx chip and the required delay in the interrupt in uSec
- *
- * INPUT:
- * ETH_PORT eth_port_num Ethernet port number
- * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
- * unsigned int delay Delay in uSeconds
- *
- * OUTPUT:
- * Interrupt coalescing mechanism value is set in MV-643xx chip.
- *
- * RETURN:
- * The interrupt coalescing value set in the gigE port.
- *
- *******************************************************************************/
-#if 0 /* FIXME */
-static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
- unsigned int t_clk,
- unsigned int delay)
-{
- unsigned int coal;
-
- coal = ((t_clk / 1000000) * delay) / 64;
- /* Set TX Coalescing mechanism */
- MV_REG_WRITE (MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
- coal << 4);
- return coal;
-}
-#endif
-
-/*******************************************************************************
- * eth_b_copy - Copy bytes from source to destination
- *
- * DESCRIPTION:
- * This function supports the eight bytes limitation on Tx buffer size.
- * The routine will zero eight bytes starting from the destination address
- * followed by copying bytes from the source address to the destination.
- *
- * INPUT:
- * unsigned int src_addr 32 bit source address.
- * unsigned int dst_addr 32 bit destination address.
- * int byte_count Number of bytes to copy.
- *
- * OUTPUT:
- * See description.
- *
- * RETURN:
- * None.
- *
- *******************************************************************************/
-static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
- int byte_count)
-{
- /* Zero the dst_addr area */
- *(unsigned int *) dst_addr = 0x0;
-
- while (byte_count != 0) {
- *(char *) dst_addr = *(char *) src_addr;
- dst_addr++;
- src_addr++;
- byte_count--;
- }
-}
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64460X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * mv_eth.h - header file for the polled mode GT ethernet driver
- */
-
-#ifndef __DB64460_ETH_H__
-#define __DB64460_ETH_H__
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-#include <common.h>
-#include <net.h>
-#include "mv_regs.h"
-#include <asm/errno.h>
-#include "../../Marvell/include/core.h"
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-* The first part is the high level driver of the gigE ethernet ports. *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
-#ifndef MAX_SKB_FRAGS
-#define MAX_SKB_FRAGS 0
-#endif
-
-/* Port attributes */
-/*#define MAX_RX_QUEUE_NUM 8*/
-/*#define MAX_TX_QUEUE_NUM 8*/
-#define MAX_RX_QUEUE_NUM 1
-#define MAX_TX_QUEUE_NUM 1
-
-
-/* Use one TX queue and one RX queue */
-#define MV64460_TX_QUEUE_NUM 1
-#define MV64460_RX_QUEUE_NUM 1
-
-/*
- * Number of RX / TX descriptors on RX / TX rings.
- * Note that allocating RX descriptors is done by allocating the RX
- * ring AND a preallocated RX buffers (skb's) for each descriptor.
- * The TX descriptors only allocates the TX descriptors ring,
- * with no pre allocated TX buffers (skb's are allocated by higher layers.
- */
-
-/* Default TX ring size is 10 descriptors */
-#ifdef CONFIG_MV64460_ETH_TXQUEUE_SIZE
-#define MV64460_TX_QUEUE_SIZE CONFIG_MV64460_ETH_TXQUEUE_SIZE
-#else
-#define MV64460_TX_QUEUE_SIZE 4
-#endif
-
-/* Default RX ring size is 4 descriptors */
-#ifdef CONFIG_MV64460_ETH_RXQUEUE_SIZE
-#define MV64460_RX_QUEUE_SIZE CONFIG_MV64460_ETH_RXQUEUE_SIZE
-#else
-#define MV64460_RX_QUEUE_SIZE 4
-#endif
-
-#ifdef CONFIG_RX_BUFFER_SIZE
-#define MV64460_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
-#else
-#define MV64460_RX_BUFFER_SIZE 1600
-#endif
-
-#ifdef CONFIG_TX_BUFFER_SIZE
-#define MV64460_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
-#else
-#define MV64460_TX_BUFFER_SIZE 1600
-#endif
-
-/*
- * Network device statistics. Akin to the 2.0 ether stats but
- * with byte counters.
- */
-
-struct net_device_stats
-{
- unsigned long rx_packets; /* total packets received */
- unsigned long tx_packets; /* total packets transmitted */
- unsigned long rx_bytes; /* total bytes received */
- unsigned long tx_bytes; /* total bytes transmitted */
- unsigned long rx_errors; /* bad packets received */
- unsigned long tx_errors; /* packet transmit problems */
- unsigned long rx_dropped; /* no space in linux buffers */
- unsigned long tx_dropped; /* no space available in linux */
- unsigned long multicast; /* multicast packets received */
- unsigned long collisions;
-
- /* detailed rx_errors: */
- unsigned long rx_length_errors;
- unsigned long rx_over_errors; /* receiver ring buff overflow */
- unsigned long rx_crc_errors; /* recved pkt with crc error */
- unsigned long rx_frame_errors; /* recv'd frame alignment error */
- unsigned long rx_fifo_errors; /* recv'r fifo overrun */
- unsigned long rx_missed_errors; /* receiver missed packet */
-
- /* detailed tx_errors */
- unsigned long tx_aborted_errors;
- unsigned long tx_carrier_errors;
- unsigned long tx_fifo_errors;
- unsigned long tx_heartbeat_errors;
- unsigned long tx_window_errors;
-
- /* for cslip etc */
- unsigned long rx_compressed;
- unsigned long tx_compressed;
-};
-
-
-/* Private data structure used for ethernet device */
-struct mv64460_eth_priv {
- unsigned int port_num;
- struct net_device_stats *stats;
-
- /* to buffer area aligned */
- char * p_eth_tx_buffer[MV64460_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */
- char * p_eth_rx_buffer[MV64460_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */
-
- /* Size of Tx Ring per queue */
- unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
-
- /* Size of Rx Ring per queue */
- unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
-
- /* Magic Number for Ethernet running */
- unsigned int eth_running;
-
- int first_init;
-};
-
-int mv64460_eth_init (struct eth_device *dev);
-int mv64460_eth_stop (struct eth_device *dev);
-int mv64460_eth_start_xmit(struct eth_device *dev, void *packet, int length);
-int mv64460_eth_open (struct eth_device *dev);
-
-
-/*************************************************************************
-**************************************************************************
-**************************************************************************
-* The second part is the low level driver of the gigE ethernet ports. *
-**************************************************************************
-**************************************************************************
-*************************************************************************/
-
-
-/********************************************************************************
- * Header File for : MV-643xx network interface header
- *
- * DESCRIPTION:
- * This header file contains macros typedefs and function declaration for
- * the Marvell Gig Bit Ethernet Controller.
- *
- * DEPENDENCIES:
- * None.
- *
- *******************************************************************************/
-
-
-#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
-#ifdef CONFIG_MV64460_SRAM_CACHEABLE
-/* In case SRAM is cacheable but not cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset) \
-{ \
- __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
-}
-#else
-/* In case SRAM is cache coherent or non-cacheable */
-#define D_CACHE_FLUSH_LINE(addr, offset) ;
-#endif
-#else
-#ifdef CONFIG_NOT_COHERENT_CACHE
-/* In case of descriptors on DDR but not cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset) \
-{ \
- __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
-}
-#else
-/* In case of descriptors on DDR and cache coherent */
-#define D_CACHE_FLUSH_LINE(addr, offset) ;
-#endif /* CONFIG_NOT_COHERENT_CACHE */
-#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
-
-
-#define CPU_PIPE_FLUSH \
-{ \
- __asm__ __volatile__ ("eieio"); \
-}
-
-
-/* defines */
-
-/* Default port configuration value */
-#define PORT_CONFIG_VALUE \
- ETH_UNICAST_NORMAL_MODE | \
- ETH_DEFAULT_RX_QUEUE_0 | \
- ETH_DEFAULT_RX_ARP_QUEUE_0 | \
- ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
- ETH_RECEIVE_BC_IF_IP | \
- ETH_RECEIVE_BC_IF_ARP | \
- ETH_CAPTURE_TCP_FRAMES_DIS | \
- ETH_CAPTURE_UDP_FRAMES_DIS | \
- ETH_DEFAULT_RX_TCP_QUEUE_0 | \
- ETH_DEFAULT_RX_UDP_QUEUE_0 | \
- ETH_DEFAULT_RX_BPDU_QUEUE_0
-
-/* Default port extend configuration value */
-#define PORT_CONFIG_EXTEND_VALUE \
- ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
- ETH_PARTITION_DISABLE
-
-
-/* Default sdma control value */
-#ifdef CONFIG_NOT_COHERENT_CACHE
-#define PORT_SDMA_CONFIG_VALUE \
- ETH_RX_BURST_SIZE_16_64BIT | \
- GT_ETH_IPG_INT_RX(0) | \
- ETH_TX_BURST_SIZE_16_64BIT;
-#else
-#define PORT_SDMA_CONFIG_VALUE \
- ETH_RX_BURST_SIZE_4_64BIT | \
- GT_ETH_IPG_INT_RX(0) | \
- ETH_TX_BURST_SIZE_4_64BIT;
-#endif
-
-#define GT_ETH_IPG_INT_RX(value) \
- ((value & 0x3fff) << 8)
-
-/* Default port serial control value */
-#define PORT_SERIAL_CONTROL_VALUE \
- ETH_FORCE_LINK_PASS | \
- ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
- ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
- ETH_ADV_SYMMETRIC_FLOW_CTRL | \
- ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
- ETH_FORCE_BP_MODE_NO_JAM | \
- BIT9 | \
- ETH_DO_NOT_FORCE_LINK_FAIL | \
- ETH_RETRANSMIT_16_ETTEMPTS | \
- ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
- ETH_DTE_ADV_0 | \
- ETH_DISABLE_AUTO_NEG_BYPASS | \
- ETH_AUTO_NEG_NO_CHANGE | \
- ETH_MAX_RX_PACKET_1552BYTE | \
- ETH_CLR_EXT_LOOPBACK | \
- ETH_SET_FULL_DUPLEX_MODE | \
- ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
-
-#define RX_BUFFER_MAX_SIZE 0xFFFF
-#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */
-
-#define RX_BUFFER_MIN_SIZE 0x8
-#define TX_BUFFER_MIN_SIZE 0x8
-
-/* Tx WRR confoguration macros */
-#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
-#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */
-#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */
-
-/* MAC accepet/reject macros */
-#define ACCEPT_MAC_ADDR 0
-#define REJECT_MAC_ADDR 1
-
-/* Size of a Tx/Rx descriptor used in chain list data structure */
-#define RX_DESC_ALIGNED_SIZE 0x20
-#define TX_DESC_ALIGNED_SIZE 0x20
-
-/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
-#define TX_BUF_OFFSET_IN_DESC 0x18
-/* Buffer offset from buffer pointer */
-#define RX_BUF_OFFSET 0x2
-
-/* Gap define */
-#define ETH_BAR_GAP 0x8
-#define ETH_SIZE_REG_GAP 0x8
-#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4
-#define ETH_PORT_ACCESS_CTRL_GAP 0x4
-
-/* Gigabit Ethernet Unit Global Registers */
-
-/* MIB Counters register definitions */
-#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
-#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
-#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
-#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
-#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
-#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
-#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
-#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
-#define ETH_MIB_FRAMES_64_OCTETS 0x20
-#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
-#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
-#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
-#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
-#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
-#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
-#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
-#define ETH_MIB_GOOD_FRAMES_SENT 0x40
-#define ETH_MIB_EXCESSIVE_COLLISION 0x44
-#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
-#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
-#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
-#define ETH_MIB_FC_SENT 0x54
-#define ETH_MIB_GOOD_FC_RECEIVED 0x58
-#define ETH_MIB_BAD_FC_RECEIVED 0x5c
-#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
-#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
-#define ETH_MIB_OVERSIZE_RECEIVED 0x68
-#define ETH_MIB_JABBER_RECEIVED 0x6c
-#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
-#define ETH_MIB_BAD_CRC_EVENT 0x74
-#define ETH_MIB_COLLISION 0x78
-#define ETH_MIB_LATE_COLLISION 0x7c
-
-/* Port serial status reg (PSR) */
-#define ETH_INTERFACE_GMII_MII 0
-#define ETH_INTERFACE_PCM BIT0
-#define ETH_LINK_IS_DOWN 0
-#define ETH_LINK_IS_UP BIT1
-#define ETH_PORT_AT_HALF_DUPLEX 0
-#define ETH_PORT_AT_FULL_DUPLEX BIT2
-#define ETH_RX_FLOW_CTRL_DISABLED 0
-#define ETH_RX_FLOW_CTRL_ENBALED BIT3
-#define ETH_GMII_SPEED_100_10 0
-#define ETH_GMII_SPEED_1000 BIT4
-#define ETH_MII_SPEED_10 0
-#define ETH_MII_SPEED_100 BIT5
-#define ETH_NO_TX 0
-#define ETH_TX_IN_PROGRESS BIT7
-#define ETH_BYPASS_NO_ACTIVE 0
-#define ETH_BYPASS_ACTIVE BIT8
-#define ETH_PORT_NOT_AT_PARTITION_STATE 0
-#define ETH_PORT_AT_PARTITION_STATE BIT9
-#define ETH_PORT_TX_FIFO_NOT_EMPTY 0
-#define ETH_PORT_TX_FIFO_EMPTY BIT10
-
-
-/* These macros describes the Port configuration reg (Px_cR) bits */
-#define ETH_UNICAST_NORMAL_MODE 0
-#define ETH_UNICAST_PROMISCUOUS_MODE BIT0
-#define ETH_DEFAULT_RX_QUEUE_0 0
-#define ETH_DEFAULT_RX_QUEUE_1 BIT1
-#define ETH_DEFAULT_RX_QUEUE_2 BIT2
-#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1)
-#define ETH_DEFAULT_RX_QUEUE_4 BIT3
-#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1)
-#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2)
-#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1)
-#define ETH_DEFAULT_RX_ARP_QUEUE_0 0
-#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4
-#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5
-#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4)
-#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6
-#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4)
-#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5)
-#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4)
-#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
-#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7
-#define ETH_RECEIVE_BC_IF_IP 0
-#define ETH_REJECT_BC_IF_IP BIT8
-#define ETH_RECEIVE_BC_IF_ARP 0
-#define ETH_REJECT_BC_IF_ARP BIT9
-#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12
-#define ETH_CAPTURE_TCP_FRAMES_DIS 0
-#define ETH_CAPTURE_TCP_FRAMES_EN BIT14
-#define ETH_CAPTURE_UDP_FRAMES_DIS 0
-#define ETH_CAPTURE_UDP_FRAMES_EN BIT15
-#define ETH_DEFAULT_RX_TCP_QUEUE_0 0
-#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16
-#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17
-#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16)
-#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18
-#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16)
-#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17)
-#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16)
-#define ETH_DEFAULT_RX_UDP_QUEUE_0 0
-#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19
-#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20
-#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19)
-#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21
-#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19)
-#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20)
-#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0
-#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22
-#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23
-#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
-#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
-#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
-
-
-/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
-#define ETH_CLASSIFY_EN BIT0
-#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
-#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1
-#define ETH_PARTITION_DISABLE 0
-#define ETH_PARTITION_ENABLE BIT2
-
-
-/* Tx/Rx queue command reg (RQCR/TQCR)*/
-#define ETH_QUEUE_0_ENABLE BIT0
-#define ETH_QUEUE_1_ENABLE BIT1
-#define ETH_QUEUE_2_ENABLE BIT2
-#define ETH_QUEUE_3_ENABLE BIT3
-#define ETH_QUEUE_4_ENABLE BIT4
-#define ETH_QUEUE_5_ENABLE BIT5
-#define ETH_QUEUE_6_ENABLE BIT6
-#define ETH_QUEUE_7_ENABLE BIT7
-#define ETH_QUEUE_0_DISABLE BIT8
-#define ETH_QUEUE_1_DISABLE BIT9
-#define ETH_QUEUE_2_DISABLE BIT10
-#define ETH_QUEUE_3_DISABLE BIT11
-#define ETH_QUEUE_4_DISABLE BIT12
-#define ETH_QUEUE_5_DISABLE BIT13
-#define ETH_QUEUE_6_DISABLE BIT14
-#define ETH_QUEUE_7_DISABLE BIT15
-
-/* These macros describes the Port Sdma configuration reg (SDCR) bits */
-#define ETH_RIFB BIT0
-#define ETH_RX_BURST_SIZE_1_64BIT 0
-#define ETH_RX_BURST_SIZE_2_64BIT BIT1
-#define ETH_RX_BURST_SIZE_4_64BIT BIT2
-#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1)
-#define ETH_RX_BURST_SIZE_16_64BIT BIT3
-#define ETH_BLM_RX_NO_SWAP BIT4
-#define ETH_BLM_RX_BYTE_SWAP 0
-#define ETH_BLM_TX_NO_SWAP BIT5
-#define ETH_BLM_TX_BYTE_SWAP 0
-#define ETH_DESCRIPTORS_BYTE_SWAP BIT6
-#define ETH_DESCRIPTORS_NO_SWAP 0
-#define ETH_TX_BURST_SIZE_1_64BIT 0
-#define ETH_TX_BURST_SIZE_2_64BIT BIT22
-#define ETH_TX_BURST_SIZE_4_64BIT BIT23
-#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22)
-#define ETH_TX_BURST_SIZE_16_64BIT BIT24
-
-/* These macros describes the Port serial control reg (PSCR) bits */
-#define ETH_SERIAL_PORT_DISABLE 0
-#define ETH_SERIAL_PORT_ENABLE BIT0
-#define ETH_FORCE_LINK_PASS BIT1
-#define ETH_DO_NOT_FORCE_LINK_PASS 0
-#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
-#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2
-#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
-#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3
-#define ETH_ADV_NO_FLOW_CTRL 0
-#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4
-#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
-#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5
-#define ETH_FORCE_BP_MODE_NO_JAM 0
-#define ETH_FORCE_BP_MODE_JAM_TX BIT7
-#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8
-#define ETH_FORCE_LINK_FAIL 0
-#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10
-#define ETH_RETRANSMIT_16_ETTEMPTS 0
-#define ETH_RETRANSMIT_FOREVER BIT11
-#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13
-#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
-#define ETH_DTE_ADV_0 0
-#define ETH_DTE_ADV_1 BIT14
-#define ETH_DISABLE_AUTO_NEG_BYPASS 0
-#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15
-#define ETH_AUTO_NEG_NO_CHANGE 0
-#define ETH_RESTART_AUTO_NEG BIT16
-#define ETH_MAX_RX_PACKET_1518BYTE 0
-#define ETH_MAX_RX_PACKET_1522BYTE BIT17
-#define ETH_MAX_RX_PACKET_1552BYTE BIT18
-#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17)
-#define ETH_MAX_RX_PACKET_9192BYTE BIT19
-#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17)
-#define ETH_SET_EXT_LOOPBACK BIT20
-#define ETH_CLR_EXT_LOOPBACK 0
-#define ETH_SET_FULL_DUPLEX_MODE BIT21
-#define ETH_SET_HALF_DUPLEX_MODE 0
-#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22
-#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
-#define ETH_SET_GMII_SPEED_TO_10_100 0
-#define ETH_SET_GMII_SPEED_TO_1000 BIT23
-#define ETH_SET_MII_SPEED_TO_10 0
-#define ETH_SET_MII_SPEED_TO_100 BIT24
-
-
-/* SMI reg */
-#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
-#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
-#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
-#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
-
-/* SDMA command status fields macros */
-
-/* Tx & Rx descriptors status */
-#define ETH_ERROR_SUMMARY (BIT0)
-
-/* Tx & Rx descriptors command */
-#define ETH_BUFFER_OWNED_BY_DMA (BIT31)
-
-/* Tx descriptors status */
-#define ETH_LC_ERROR (0 )
-#define ETH_UR_ERROR (BIT1 )
-#define ETH_RL_ERROR (BIT2 )
-#define ETH_LLC_SNAP_FORMAT (BIT9 )
-
-/* Rx descriptors status */
-#define ETH_CRC_ERROR (0 )
-#define ETH_OVERRUN_ERROR (BIT1 )
-#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
-#define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
-#define ETH_VLAN_TAGGED (BIT19)
-#define ETH_BPDU_FRAME (BIT20)
-#define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
-#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
-#define ETH_OTHER_FRAME_TYPE (BIT22)
-#define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
-#define ETH_FRAME_TYPE_IP_V_4 (BIT24)
-#define ETH_FRAME_HEADER_OK (BIT25)
-#define ETH_RX_LAST_DESC (BIT26)
-#define ETH_RX_FIRST_DESC (BIT27)
-#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
-#define ETH_RX_ENABLE_INTERRUPT (BIT29)
-#define ETH_LAYER_4_CHECKSUM_OK (BIT30)
-
-/* Rx descriptors byte count */
-#define ETH_FRAME_FRAGMENTED (BIT2)
-
-/* Tx descriptors command */
-#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
-#define ETH_FRAME_SET_TO_VLAN (BIT15)
-#define ETH_TCP_FRAME (0 )
-#define ETH_UDP_FRAME (BIT16)
-#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
-#define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
-#define ETH_ZERO_PADDING (BIT19)
-#define ETH_TX_LAST_DESC (BIT20)
-#define ETH_TX_FIRST_DESC (BIT21)
-#define ETH_GEN_CRC (BIT22)
-#define ETH_TX_ENABLE_INTERRUPT (BIT23)
-#define ETH_AUTO_MODE (BIT30)
-
-/* Address decode parameters */
-/* Ethernet Base Address Register bits */
-#define EBAR_TARGET_DRAM 0x00000000
-#define EBAR_TARGET_DEVICE 0x00000001
-#define EBAR_TARGET_CBS 0x00000002
-#define EBAR_TARGET_PCI0 0x00000003
-#define EBAR_TARGET_PCI1 0x00000004
-#define EBAR_TARGET_CUNIT 0x00000005
-#define EBAR_TARGET_AUNIT 0x00000006
-#define EBAR_TARGET_GUNIT 0x00000007
-
-/* Window attributes */
-#define EBAR_ATTR_DRAM_CS0 0x00000E00
-#define EBAR_ATTR_DRAM_CS1 0x00000D00
-#define EBAR_ATTR_DRAM_CS2 0x00000B00
-#define EBAR_ATTR_DRAM_CS3 0x00000700
-
-/* DRAM Target interface */
-#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000
-#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000
-#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000
-
-/* Device Bus Target interface */
-#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00
-#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00
-#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00
-#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700
-#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00
-
-/* PCI Target interface */
-#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000
-#define EBAR_ATTR_PCI_NO_SWAP 0x00000100
-#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200
-#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300
-#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
-#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400
-#define EBAR_ATTR_PCI_IO_SPACE 0x00000000
-#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800
-#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000
-#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000
-
-/* CPU 60x bus or internal SRAM interface */
-#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000
-#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100
-#define EBAR_ATTR_CBS_SRAM 0x00000000
-#define EBAR_ATTR_CBS_CPU_BUS 0x00000800
-
-/* Window access control */
-#define EWIN_ACCESS_NOT_ALLOWED 0
-#define EWIN_ACCESS_READ_ONLY BIT0
-#define EWIN_ACCESS_FULL (BIT1 | BIT0)
-#define EWIN0_ACCESS_MASK 0x0003
-#define EWIN1_ACCESS_MASK 0x000C
-#define EWIN2_ACCESS_MASK 0x0030
-#define EWIN3_ACCESS_MASK 0x00C0
-
-/* typedefs */
-
-typedef enum _eth_port
-{
- ETH_0 = 0,
- ETH_1 = 1,
- ETH_2 = 2
-}ETH_PORT;
-
-typedef enum _eth_func_ret_status
-{
- ETH_OK, /* Returned as expected. */
- ETH_ERROR, /* Fundamental error. */
- ETH_RETRY, /* Could not process request. Try later. */
- ETH_END_OF_JOB, /* Ring has nothing to process. */
- ETH_QUEUE_FULL, /* Ring resource error. */
- ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
-}ETH_FUNC_RET_STATUS;
-
-typedef enum _eth_queue
-{
- ETH_Q0 = 0,
- ETH_Q1 = 1,
- ETH_Q2 = 2,
- ETH_Q3 = 3,
- ETH_Q4 = 4,
- ETH_Q5 = 5,
- ETH_Q6 = 6,
- ETH_Q7 = 7
-} ETH_QUEUE;
-
-typedef enum _addr_win
-{
- ETH_WIN0,
- ETH_WIN1,
- ETH_WIN2,
- ETH_WIN3,
- ETH_WIN4,
- ETH_WIN5
-} ETH_ADDR_WIN;
-
-typedef enum _eth_target
-{
- ETH_TARGET_DRAM ,
- ETH_TARGET_DEVICE,
- ETH_TARGET_CBS ,
- ETH_TARGET_PCI0 ,
- ETH_TARGET_PCI1
-}ETH_TARGET;
-
-typedef struct _eth_rx_desc
-{
- unsigned short byte_cnt ; /* Descriptor buffer byte count */
- unsigned short buf_size ; /* Buffer size */
- unsigned int cmd_sts ; /* Descriptor command status */
- unsigned int next_desc_ptr; /* Next descriptor pointer */
- unsigned int buf_ptr ; /* Descriptor buffer pointer */
- unsigned int return_info ; /* User resource return information */
-} ETH_RX_DESC;
-
-
-typedef struct _eth_tx_desc
-{
- unsigned short byte_cnt ; /* Descriptor buffer byte count */
- unsigned short l4i_chk ; /* CPU provided TCP Checksum */
- unsigned int cmd_sts ; /* Descriptor command status */
- unsigned int next_desc_ptr; /* Next descriptor pointer */
- unsigned int buf_ptr ; /* Descriptor buffer pointer */
- unsigned int return_info ; /* User resource return information */
-} ETH_TX_DESC;
-
-/* Unified struct for Rx and Tx operations. The user is not required to */
-/* be familier with neither Tx nor Rx descriptors. */
-typedef struct _pkt_info
-{
- unsigned short byte_cnt ; /* Descriptor buffer byte count */
- unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */
- unsigned int cmd_sts ; /* Descriptor command status */
- unsigned int buf_ptr ; /* Descriptor buffer pointer */
- unsigned int return_info ; /* User resource return information */
-} PKT_INFO;
-
-
-typedef struct _eth_win_param
-{
- ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */
- ETH_TARGET target; /* System targets. See ETH_TARGET enum */
- unsigned short attributes; /* BAR attributes. See above macros. */
- unsigned int base_addr; /* Window base address in unsigned int form */
- unsigned int high_addr; /* Window high address in unsigned int form */
- unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
- bool enable; /* Enable/disable access to the window. */
- unsigned short access_ctrl; /* Access ctrl register. see above macros */
-} ETH_WIN_PARAM;
-
-
-/* Ethernet port specific infomation */
-
-typedef struct _eth_port_ctrl
-{
- ETH_PORT port_num; /* User Ethernet port number */
- int port_phy_addr; /* User phy address of Ethrnet port */
- unsigned char port_mac_addr[6]; /* User defined port MAC address. */
- unsigned int port_config; /* User port configuration value */
- unsigned int port_config_extend; /* User port config extend value */
- unsigned int port_sdma_config; /* User port SDMA config value */
- unsigned int port_serial_control; /* User port serial control value */
- unsigned int port_tx_queue_command; /* Port active Tx queues summary */
- unsigned int port_rx_queue_command; /* Port active Rx queues summary */
-
- /* User function to cast virtual address to CPU bus address */
- unsigned int (*port_virt_to_phys)(unsigned int addr);
- /* User scratch pad for user specific data structures */
- void *port_private;
-
- bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
- bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
-
- /* Tx/Rx rings managment indexes fields. For driver use */
-
- /* Next available Rx resource */
- volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
- /* Returning Rx resource */
- volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
-
- /* Next available Tx resource */
- volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
- /* Returning Tx resource */
- volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
- /* An extra Tx index to support transmit of multiple buffers per packet */
- volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
-
- /* Tx/Rx rings size and base variables fields. For driver use */
-
- volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
- unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM];
- char *p_rx_buffer_base[MAX_RX_QUEUE_NUM];
-
- volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
- unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM];
- char *p_tx_buffer_base[MAX_TX_QUEUE_NUM];
-
-} ETH_PORT_INFO;
-
-
-/* ethernet.h API list */
-
-/* Port operation control routines */
-static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
-static void eth_port_reset(ETH_PORT eth_port_num);
-static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
-
-
-/* Port MAC address routines */
-static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
- unsigned char *p_addr,
- ETH_QUEUE queue);
-#if 0 /* FIXME */
-static void eth_port_mc_addr (ETH_PORT eth_port_num,
- unsigned char *p_addr,
- ETH_QUEUE queue,
- int option);
-#endif
-
-/* PHY and MIB routines */
-static bool ethernet_phy_reset(ETH_PORT eth_port_num);
-
-static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
- unsigned int phy_reg,
- unsigned int value);
-
-static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
- unsigned int phy_reg,
- unsigned int* value);
-
-static void eth_clear_mib_counters(ETH_PORT eth_port_num);
-
-/* Port data flow control routines */
-static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl,
- ETH_QUEUE tx_queue,
- PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
- ETH_QUEUE tx_queue,
- PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
- ETH_QUEUE rx_queue,
- PKT_INFO *p_pkt_info);
-static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
- ETH_QUEUE rx_queue,
- PKT_INFO *p_pkt_info);
-
-
-static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
- ETH_QUEUE tx_queue,
- int tx_desc_num,
- int tx_buff_size,
- unsigned int tx_desc_base_addr,
- unsigned int tx_buff_base_addr);
-
-static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
- ETH_QUEUE rx_queue,
- int rx_desc_num,
- int rx_buff_size,
- unsigned int rx_desc_base_addr,
- unsigned int rx_buff_base_addr);
-
-#endif /* MV64460_ETH_ */
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64460X ethernet ports
- * Copyright (C) 2002 rabeeh@galileo.co.il
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/********************************************************************************
-* gt64460r.h - GT-64460 Internal registers definition file.
-*
-* DESCRIPTION:
-* None.
-*
-* DEPENDENCIES:
-* None.
-*
-*******************************************************************************/
-
-#ifndef __INCmv_regsh
-#define __INCmv_regsh
-
-#define MV64460
-
-/* Supported by the Atlantis */
-#define MV64460_INCLUDE_PCI_1
-#define MV64460_INCLUDE_PCI_0_ARBITER
-#define MV64460_INCLUDE_PCI_1_ARBITER
-#define MV64460_INCLUDE_SNOOP_SUPPORT
-#define MV64460_INCLUDE_P2P
-#define MV64460_INCLUDE_ETH_PORT_2
-#define MV64460_INCLUDE_CPU_MAPPING
-#define MV64460_INCLUDE_MPSC
-
-/* Not supported features */
-#undef INCLUDE_CNTMR_4_7
-#undef INCLUDE_DMA_4_7
-
-/****************************************/
-/* Processor Address Space */
-/****************************************/
-
-/* DDR SDRAM BAR and size registers */
-
-#define MV64460_CS_0_BASE_ADDR 0x008
-#define MV64460_CS_0_SIZE 0x010
-#define MV64460_CS_1_BASE_ADDR 0x208
-#define MV64460_CS_1_SIZE 0x210
-#define MV64460_CS_2_BASE_ADDR 0x018
-#define MV64460_CS_2_SIZE 0x020
-#define MV64460_CS_3_BASE_ADDR 0x218
-#define MV64460_CS_3_SIZE 0x220
-
-/* Devices BAR and size registers */
-
-#define MV64460_DEV_CS0_BASE_ADDR 0x028
-#define MV64460_DEV_CS0_SIZE 0x030
-#define MV64460_DEV_CS1_BASE_ADDR 0x228
-#define MV64460_DEV_CS1_SIZE 0x230
-#define MV64460_DEV_CS2_BASE_ADDR 0x248
-#define MV64460_DEV_CS2_SIZE 0x250
-#define MV64460_DEV_CS3_BASE_ADDR 0x038
-#define MV64460_DEV_CS3_SIZE 0x040
-#define MV64460_BOOTCS_BASE_ADDR 0x238
-#define MV64460_BOOTCS_SIZE 0x240
-
-/* PCI 0 BAR and size registers */
-
-#define MV64460_PCI_0_IO_BASE_ADDR 0x048
-#define MV64460_PCI_0_IO_SIZE 0x050
-#define MV64460_PCI_0_MEMORY0_BASE_ADDR 0x058
-#define MV64460_PCI_0_MEMORY0_SIZE 0x060
-#define MV64460_PCI_0_MEMORY1_BASE_ADDR 0x080
-#define MV64460_PCI_0_MEMORY1_SIZE 0x088
-#define MV64460_PCI_0_MEMORY2_BASE_ADDR 0x258
-#define MV64460_PCI_0_MEMORY2_SIZE 0x260
-#define MV64460_PCI_0_MEMORY3_BASE_ADDR 0x280
-#define MV64460_PCI_0_MEMORY3_SIZE 0x288
-
-/* PCI 1 BAR and size registers */
-#define MV64460_PCI_1_IO_BASE_ADDR 0x090
-#define MV64460_PCI_1_IO_SIZE 0x098
-#define MV64460_PCI_1_MEMORY0_BASE_ADDR 0x0a0
-#define MV64460_PCI_1_MEMORY0_SIZE 0x0a8
-#define MV64460_PCI_1_MEMORY1_BASE_ADDR 0x0b0
-#define MV64460_PCI_1_MEMORY1_SIZE 0x0b8
-#define MV64460_PCI_1_MEMORY2_BASE_ADDR 0x2a0
-#define MV64460_PCI_1_MEMORY2_SIZE 0x2a8
-#define MV64460_PCI_1_MEMORY3_BASE_ADDR 0x2b0
-#define MV64460_PCI_1_MEMORY3_SIZE 0x2b8
-
-/* SRAM base address */
-#define MV64460_INTEGRATED_SRAM_BASE_ADDR 0x268
-
-/* internal registers space base address */
-#define MV64460_INTERNAL_SPACE_BASE_ADDR 0x068
-
-/* Enables the CS , DEV_CS , PCI 0 and PCI 1
- windows above */
-#define MV64460_BASE_ADDR_ENABLE 0x278
-
-/****************************************/
-/* PCI remap registers */
-/****************************************/
- /* PCI 0 */
-#define MV64460_PCI_0_IO_ADDR_REMAP 0x0f0
-#define MV64460_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8
-#define MV64460_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320
-#define MV64460_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100
-#define MV64460_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328
-#define MV64460_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8
-#define MV64460_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330
-#define MV64460_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300
-#define MV64460_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338
- /* PCI 1 */
-#define MV64460_PCI_1_IO_ADDR_REMAP 0x108
-#define MV64460_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110
-#define MV64460_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340
-#define MV64460_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118
-#define MV64460_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348
-#define MV64460_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310
-#define MV64460_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350
-#define MV64460_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318
-#define MV64460_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358
-
-#define MV64460_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0
-#define MV64460_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8
-#define MV64460_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0
-#define MV64460_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8
-#define MV64460_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0
-#define MV64460_CPU_GE_HEADERS_RETARGET_BASE 0x3d8
-#define MV64460_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0
-#define MV64460_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8
-
-/****************************************/
-/* CPU Control Registers */
-/****************************************/
-
-#define MV64460_CPU_CONFIG 0x000
-#define MV64460_CPU_MODE 0x120
-#define MV64460_CPU_MASTER_CONTROL 0x160
-#define MV64460_CPU_CROSS_BAR_CONTROL_LOW 0x150
-#define MV64460_CPU_CROSS_BAR_CONTROL_HIGH 0x158
-#define MV64460_CPU_CROSS_BAR_TIMEOUT 0x168
-
-/****************************************/
-/* SMP RegisterS */
-/****************************************/
-
-#define MV64460_SMP_WHO_AM_I 0x200
-#define MV64460_SMP_CPU0_DOORBELL 0x214
-#define MV64460_SMP_CPU0_DOORBELL_CLEAR 0x21C
-#define MV64460_SMP_CPU1_DOORBELL 0x224
-#define MV64460_SMP_CPU1_DOORBELL_CLEAR 0x22C
-#define MV64460_SMP_CPU0_DOORBELL_MASK 0x234
-#define MV64460_SMP_CPU1_DOORBELL_MASK 0x23C
-#define MV64460_SMP_SEMAPHOR0 0x244
-#define MV64460_SMP_SEMAPHOR1 0x24c
-#define MV64460_SMP_SEMAPHOR2 0x254
-#define MV64460_SMP_SEMAPHOR3 0x25c
-#define MV64460_SMP_SEMAPHOR4 0x264
-#define MV64460_SMP_SEMAPHOR5 0x26c
-#define MV64460_SMP_SEMAPHOR6 0x274
-#define MV64460_SMP_SEMAPHOR7 0x27c
-
-/****************************************/
-/* CPU Sync Barrier Register */
-/****************************************/
-
-#define MV64460_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0
-#define MV64460_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8
-#define MV64460_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0
-#define MV64460_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8
-
-/****************************************/
-/* CPU Access Protect */
-/****************************************/
-
-#define MV64460_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180
-#define MV64460_CPU_PROTECT_WINDOW_0_SIZE 0x188
-#define MV64460_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190
-#define MV64460_CPU_PROTECT_WINDOW_1_SIZE 0x198
-#define MV64460_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0
-#define MV64460_CPU_PROTECT_WINDOW_2_SIZE 0x1a8
-#define MV64460_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0
-#define MV64460_CPU_PROTECT_WINDOW_3_SIZE 0x1b8
-
-
-/****************************************/
-/* CPU Error Report */
-/****************************************/
-
-#define MV64460_CPU_ERROR_ADDR_LOW 0x070
-#define MV64460_CPU_ERROR_ADDR_HIGH 0x078
-#define MV64460_CPU_ERROR_DATA_LOW 0x128
-#define MV64460_CPU_ERROR_DATA_HIGH 0x130
-#define MV64460_CPU_ERROR_PARITY 0x138
-#define MV64460_CPU_ERROR_CAUSE 0x140
-#define MV64460_CPU_ERROR_MASK 0x148
-
-/****************************************/
-/* CPU Interface Debug Registers */
-/****************************************/
-
-#define MV64460_PUNIT_SLAVE_DEBUG_LOW 0x360
-#define MV64460_PUNIT_SLAVE_DEBUG_HIGH 0x368
-#define MV64460_PUNIT_MASTER_DEBUG_LOW 0x370
-#define MV64460_PUNIT_MASTER_DEBUG_HIGH 0x378
-#define MV64460_PUNIT_MMASK 0x3e4
-
-/****************************************/
-/* Integrated SRAM Registers */
-/****************************************/
-
-#define MV64460_SRAM_CONFIG 0x380
-#define MV64460_SRAM_TEST_MODE 0X3F4
-#define MV64460_SRAM_ERROR_CAUSE 0x388
-#define MV64460_SRAM_ERROR_ADDR 0x390
-#define MV64460_SRAM_ERROR_ADDR_HIGH 0X3F8
-#define MV64460_SRAM_ERROR_DATA_LOW 0x398
-#define MV64460_SRAM_ERROR_DATA_HIGH 0x3a0
-#define MV64460_SRAM_ERROR_DATA_PARITY 0x3a8
-
-/****************************************/
-/* SDRAM Configuration */
-/****************************************/
-
-#define MV64460_SDRAM_CONFIG 0x1400
-#define MV64460_D_UNIT_CONTROL_LOW 0x1404
-#define MV64460_D_UNIT_CONTROL_HIGH 0x1424
-#define MV64460_D_UNIT_MMASK 0x14B0
-#define MV64460_SDRAM_TIMING_CONTROL_LOW 0x1408
-#define MV64460_SDRAM_TIMING_CONTROL_HIGH 0x140c
-#define MV64460_SDRAM_ADDR_CONTROL 0x1410
-#define MV64460_SDRAM_OPEN_PAGES_CONTROL 0x1414
-#define MV64460_SDRAM_OPERATION 0x1418
-#define MV64460_SDRAM_MODE 0x141c
-#define MV64460_EXTENDED_DRAM_MODE 0x1420
-#define MV64460_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430
-#define MV64460_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434
-#define MV64460_SDRAM_CROSS_BAR_TIMEOUT 0x1438
-#define MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0
-#define MV64460_SDRAM_DATA_PADS_CALIBRATION 0x14c4
-
-/****************************************/
-/* SDRAM Error Report */
-/****************************************/
-
-#define MV64460_SDRAM_ERROR_DATA_LOW 0x1444
-#define MV64460_SDRAM_ERROR_DATA_HIGH 0x1440
-#define MV64460_SDRAM_ERROR_ADDR 0x1450
-#define MV64460_SDRAM_RECEIVED_ECC 0x1448
-#define MV64460_SDRAM_CALCULATED_ECC 0x144c
-#define MV64460_SDRAM_ECC_CONTROL 0x1454
-#define MV64460_SDRAM_ECC_ERROR_COUNTER 0x1458
-
-/******************************************/
-/* Controlled Delay Line (CDL) Registers */
-/******************************************/
-
-#define MV64460_DFCDL_CONFIG0 0x1480
-#define MV64460_DFCDL_CONFIG1 0x1484
-#define MV64460_DLL_WRITE 0x1488
-#define MV64460_DLL_READ 0x148c
-#define MV64460_SRAM_ADDR 0x1490
-#define MV64460_SRAM_DATA0 0x1494
-#define MV64460_SRAM_DATA1 0x1498
-#define MV64460_SRAM_DATA2 0x149c
-#define MV64460_DFCL_PROBE 0x14a0
-
-/******************************************/
-/* Debug Registers */
-/******************************************/
-
-#define MV64460_DUNIT_DEBUG_LOW 0x1460
-#define MV64460_DUNIT_DEBUG_HIGH 0x1464
-#define MV64460_DUNIT_MMASK 0X1b40
-
-/****************************************/
-/* Device Parameters */
-/****************************************/
-
-#define MV64460_DEVICE_BANK0_PARAMETERS 0x45c
-#define MV64460_DEVICE_BANK1_PARAMETERS 0x460
-#define MV64460_DEVICE_BANK2_PARAMETERS 0x464
-#define MV64460_DEVICE_BANK3_PARAMETERS 0x468
-#define MV64460_DEVICE_BOOT_BANK_PARAMETERS 0x46c
-#define MV64460_DEVICE_INTERFACE_CONTROL 0x4c0
-#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8
-#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc
-#define MV64460_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4
-
-/****************************************/
-/* Device interrupt registers */
-/****************************************/
-
-#define MV64460_DEVICE_INTERRUPT_CAUSE 0x4d0
-#define MV64460_DEVICE_INTERRUPT_MASK 0x4d4
-#define MV64460_DEVICE_ERROR_ADDR 0x4d8
-#define MV64460_DEVICE_ERROR_DATA 0x4dc
-#define MV64460_DEVICE_ERROR_PARITY 0x4e0
-
-/****************************************/
-/* Device debug registers */
-/****************************************/
-
-#define MV64460_DEVICE_DEBUG_LOW 0x4e4
-#define MV64460_DEVICE_DEBUG_HIGH 0x4e8
-#define MV64460_RUNIT_MMASK 0x4f0
-
-/****************************************/
-/* PCI Slave Address Decoding registers */
-/****************************************/
-
-#define MV64460_PCI_0_CS_0_BANK_SIZE 0xc08
-#define MV64460_PCI_1_CS_0_BANK_SIZE 0xc88
-#define MV64460_PCI_0_CS_1_BANK_SIZE 0xd08
-#define MV64460_PCI_1_CS_1_BANK_SIZE 0xd88
-#define MV64460_PCI_0_CS_2_BANK_SIZE 0xc0c
-#define MV64460_PCI_1_CS_2_BANK_SIZE 0xc8c
-#define MV64460_PCI_0_CS_3_BANK_SIZE 0xd0c
-#define MV64460_PCI_1_CS_3_BANK_SIZE 0xd8c
-#define MV64460_PCI_0_DEVCS_0_BANK_SIZE 0xc10
-#define MV64460_PCI_1_DEVCS_0_BANK_SIZE 0xc90
-#define MV64460_PCI_0_DEVCS_1_BANK_SIZE 0xd10
-#define MV64460_PCI_1_DEVCS_1_BANK_SIZE 0xd90
-#define MV64460_PCI_0_DEVCS_2_BANK_SIZE 0xd18
-#define MV64460_PCI_1_DEVCS_2_BANK_SIZE 0xd98
-#define MV64460_PCI_0_DEVCS_3_BANK_SIZE 0xc14
-#define MV64460_PCI_1_DEVCS_3_BANK_SIZE 0xc94
-#define MV64460_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14
-#define MV64460_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94
-#define MV64460_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c
-#define MV64460_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c
-#define MV64460_PCI_0_P2P_MEM1_BAR_SIZE 0xd20
-#define MV64460_PCI_1_P2P_MEM1_BAR_SIZE 0xda0
-#define MV64460_PCI_0_P2P_I_O_BAR_SIZE 0xd24
-#define MV64460_PCI_1_P2P_I_O_BAR_SIZE 0xda4
-#define MV64460_PCI_0_CPU_BAR_SIZE 0xd28
-#define MV64460_PCI_1_CPU_BAR_SIZE 0xda8
-#define MV64460_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00
-#define MV64460_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80
-#define MV64460_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c
-#define MV64460_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c
-#define MV64460_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c
-#define MV64460_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc
-#define MV64460_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48
-#define MV64460_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8
-#define MV64460_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48
-#define MV64460_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8
-#define MV64460_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c
-#define MV64460_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc
-#define MV64460_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c
-#define MV64460_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc
-#define MV64460_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04
-#define MV64460_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84
-#define MV64460_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08
-#define MV64460_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88
-#define MV64460_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C
-#define MV64460_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C
-#define MV64460_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10
-#define MV64460_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90
-#define MV64460_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50
-#define MV64460_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0
-#define MV64460_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50
-#define MV64460_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0
-#define MV64460_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58
-#define MV64460_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8
-#define MV64460_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54
-#define MV64460_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4
-#define MV64460_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54
-#define MV64460_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4
-#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c
-#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc
-#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60
-#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0
-#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64
-#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4
-#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68
-#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8
-#define MV64460_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c
-#define MV64460_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec
-#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70
-#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0
-#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74
-#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4
-#define MV64460_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00
-#define MV64460_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80
-#define MV64460_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38
-#define MV64460_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8
-#define MV64460_PCI_0_ADDR_DECODE_CONTROL 0xd3c
-#define MV64460_PCI_1_ADDR_DECODE_CONTROL 0xdbc
-#define MV64460_PCI_0_HEADERS_RETARGET_CONTROL 0xF40
-#define MV64460_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0
-#define MV64460_PCI_0_HEADERS_RETARGET_BASE 0xF44
-#define MV64460_PCI_1_HEADERS_RETARGET_BASE 0xFc4
-#define MV64460_PCI_0_HEADERS_RETARGET_HIGH 0xF48
-#define MV64460_PCI_1_HEADERS_RETARGET_HIGH 0xFc8
-
-/***********************************/
-/* PCI Control Register Map */
-/***********************************/
-
-#define MV64460_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20
-#define MV64460_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0
-#define MV64460_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C
-#define MV64460_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C
-#define MV64460_PCI_0_COMMAND 0xc00
-#define MV64460_PCI_1_COMMAND 0xc80
-#define MV64460_PCI_0_MODE 0xd00
-#define MV64460_PCI_1_MODE 0xd80
-#define MV64460_PCI_0_RETRY 0xc04
-#define MV64460_PCI_1_RETRY 0xc84
-#define MV64460_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04
-#define MV64460_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84
-#define MV64460_PCI_0_MSI_TRIGGER_TIMER 0xc38
-#define MV64460_PCI_1_MSI_TRIGGER_TIMER 0xcb8
-#define MV64460_PCI_0_ARBITER_CONTROL 0x1d00
-#define MV64460_PCI_1_ARBITER_CONTROL 0x1d80
-#define MV64460_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08
-#define MV64460_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88
-#define MV64460_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c
-#define MV64460_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c
-#define MV64460_PCI_0_CROSS_BAR_TIMEOUT 0x1d04
-#define MV64460_PCI_1_CROSS_BAR_TIMEOUT 0x1d84
-#define MV64460_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18
-#define MV64460_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98
-#define MV64460_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10
-#define MV64460_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90
-#define MV64460_PCI_0_P2P_CONFIG 0x1d14
-#define MV64460_PCI_1_P2P_CONFIG 0x1d94
-
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04
-#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14
-#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24
-#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34
-#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44
-#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50
-#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54
-#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58
-
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84
-#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94
-#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
-#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
-#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
-#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0
-#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
-#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8
-
-/****************************************/
-/* PCI Configuration Access Registers */
-/****************************************/
-
-#define MV64460_PCI_0_CONFIG_ADDR 0xcf8
-#define MV64460_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc
-#define MV64460_PCI_1_CONFIG_ADDR 0xc78
-#define MV64460_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c
-#define MV64460_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34
-#define MV64460_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4
-
-/****************************************/
-/* PCI Error Report Registers */
-/****************************************/
-
-#define MV64460_PCI_0_SERR_MASK 0xc28
-#define MV64460_PCI_1_SERR_MASK 0xca8
-#define MV64460_PCI_0_ERROR_ADDR_LOW 0x1d40
-#define MV64460_PCI_1_ERROR_ADDR_LOW 0x1dc0
-#define MV64460_PCI_0_ERROR_ADDR_HIGH 0x1d44
-#define MV64460_PCI_1_ERROR_ADDR_HIGH 0x1dc4
-#define MV64460_PCI_0_ERROR_ATTRIBUTE 0x1d48
-#define MV64460_PCI_1_ERROR_ATTRIBUTE 0x1dc8
-#define MV64460_PCI_0_ERROR_COMMAND 0x1d50
-#define MV64460_PCI_1_ERROR_COMMAND 0x1dd0
-#define MV64460_PCI_0_ERROR_CAUSE 0x1d58
-#define MV64460_PCI_1_ERROR_CAUSE 0x1dd8
-#define MV64460_PCI_0_ERROR_MASK 0x1d5c
-#define MV64460_PCI_1_ERROR_MASK 0x1ddc
-
-/****************************************/
-/* PCI Debug Registers */
-/****************************************/
-
-#define MV64460_PCI_0_MMASK 0X1D24
-#define MV64460_PCI_1_MMASK 0X1DA4
-
-/*********************************************/
-/* PCI Configuration, Function 0, Registers */
-/*********************************************/
-
-#define MV64460_PCI_DEVICE_AND_VENDOR_ID 0x000
-#define MV64460_PCI_STATUS_AND_COMMAND 0x004
-#define MV64460_PCI_CLASS_CODE_AND_REVISION_ID 0x008
-#define MV64460_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
-
-#define MV64460_PCI_SCS_0_BASE_ADDR_LOW 0x010
-#define MV64460_PCI_SCS_0_BASE_ADDR_HIGH 0x014
-#define MV64460_PCI_SCS_1_BASE_ADDR_LOW 0x018
-#define MV64460_PCI_SCS_1_BASE_ADDR_HIGH 0x01C
-#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020
-#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024
-#define MV64460_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c
-#define MV64460_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030
-#define MV64460_PCI_CAPABILTY_LIST_POINTER 0x034
-#define MV64460_PCI_INTERRUPT_PIN_AND_LINE 0x03C
- /* capability list */
-#define MV64460_PCI_POWER_MANAGEMENT_CAPABILITY 0x040
-#define MV64460_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
-#define MV64460_PCI_VPD_ADDR 0x048
-#define MV64460_PCI_VPD_DATA 0x04c
-#define MV64460_PCI_MSI_MESSAGE_CONTROL 0x050
-#define MV64460_PCI_MSI_MESSAGE_ADDR 0x054
-#define MV64460_PCI_MSI_MESSAGE_UPPER_ADDR 0x058
-#define MV64460_PCI_MSI_MESSAGE_DATA 0x05c
-#define MV64460_PCI_X_COMMAND 0x060
-#define MV64460_PCI_X_STATUS 0x064
-#define MV64460_PCI_COMPACT_PCI_HOT_SWAP 0x068
-
-/***********************************************/
-/* PCI Configuration, Function 1, Registers */
-/***********************************************/
-
-#define MV64460_PCI_SCS_2_BASE_ADDR_LOW 0x110
-#define MV64460_PCI_SCS_2_BASE_ADDR_HIGH 0x114
-#define MV64460_PCI_SCS_3_BASE_ADDR_LOW 0x118
-#define MV64460_PCI_SCS_3_BASE_ADDR_HIGH 0x11c
-#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120
-#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124
-
-/***********************************************/
-/* PCI Configuration, Function 2, Registers */
-/***********************************************/
-
-#define MV64460_PCI_DEVCS_0_BASE_ADDR_LOW 0x210
-#define MV64460_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214
-#define MV64460_PCI_DEVCS_1_BASE_ADDR_LOW 0x218
-#define MV64460_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c
-#define MV64460_PCI_DEVCS_2_BASE_ADDR_LOW 0x220
-#define MV64460_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224
-
-/***********************************************/
-/* PCI Configuration, Function 3, Registers */
-/***********************************************/
-
-#define MV64460_PCI_DEVCS_3_BASE_ADDR_LOW 0x310
-#define MV64460_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314
-#define MV64460_PCI_BOOT_CS_BASE_ADDR_LOW 0x318
-#define MV64460_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c
-#define MV64460_PCI_CPU_BASE_ADDR_LOW 0x220
-#define MV64460_PCI_CPU_BASE_ADDR_HIGH 0x224
-
-/***********************************************/
-/* PCI Configuration, Function 4, Registers */
-/***********************************************/
-
-#define MV64460_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410
-#define MV64460_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414
-#define MV64460_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418
-#define MV64460_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c
-#define MV64460_PCI_P2P_I_O_BASE_ADDR 0x420
-#define MV64460_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424
-
-/****************************************/
-/* Messaging Unit Registers (I20) */
-/****************************************/
-
-#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010
-#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C
-#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020
-#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024
-#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028
-#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C
-#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030
-#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034
-#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040
-#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044
-#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050
-#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054
-#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060
-#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064
-#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068
-#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C
-#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070
-#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074
-#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8
-#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC
-
-#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090
-#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C
-#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0
-#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4
-#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8
-#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC
-#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0
-#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4
-#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0
-#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4
-#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0
-#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4
-#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0
-#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4
-#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8
-#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC
-#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0
-#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4
-#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078
-#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C
-
-#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10
-#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C
-#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20
-#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24
-#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28
-#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C
-#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30
-#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34
-#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40
-#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44
-#define MV64460_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50
-#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54
-#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60
-#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64
-#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68
-#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C
-#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70
-#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74
-#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8
-#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC
-#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90
-#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98
-#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C
-#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0
-#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4
-#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8
-#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC
-#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0
-#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4
-#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0
-#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4
-#define MV64460_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0
-#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4
-#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0
-#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4
-#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8
-#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC
-#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0
-#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4
-#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78
-#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C
-
-/****************************************/
-/* Ethernet Unit Registers */
-/****************************************/
-
-#define MV64460_ETH_PHY_ADDR_REG 0x2000
-#define MV64460_ETH_SMI_REG 0x2004
-#define MV64460_ETH_UNIT_DEFAULT_ADDR_REG 0x2008
-#define MV64460_ETH_UNIT_DEFAULTID_REG 0x200c
-#define MV64460_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080
-#define MV64460_ETH_UNIT_INTERRUPT_MASK_REG 0x2084
-#define MV64460_ETH_UNIT_INTERNAL_USE_REG 0x24fc
-#define MV64460_ETH_UNIT_ERROR_ADDR_REG 0x2094
-#define MV64460_ETH_BAR_0 0x2200
-#define MV64460_ETH_BAR_1 0x2208
-#define MV64460_ETH_BAR_2 0x2210
-#define MV64460_ETH_BAR_3 0x2218
-#define MV64460_ETH_BAR_4 0x2220
-#define MV64460_ETH_BAR_5 0x2228
-#define MV64460_ETH_SIZE_REG_0 0x2204
-#define MV64460_ETH_SIZE_REG_1 0x220c
-#define MV64460_ETH_SIZE_REG_2 0x2214
-#define MV64460_ETH_SIZE_REG_3 0x221c
-#define MV64460_ETH_SIZE_REG_4 0x2224
-#define MV64460_ETH_SIZE_REG_5 0x222c
-#define MV64460_ETH_HEADERS_RETARGET_BASE_REG 0x2230
-#define MV64460_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234
-#define MV64460_ETH_HIGH_ADDR_REMAP_REG_0 0x2280
-#define MV64460_ETH_HIGH_ADDR_REMAP_REG_1 0x2284
-#define MV64460_ETH_HIGH_ADDR_REMAP_REG_2 0x2288
-#define MV64460_ETH_HIGH_ADDR_REMAP_REG_3 0x228c
-#define MV64460_ETH_BASE_ADDR_ENABLE_REG 0x2290
-#define MV64460_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2))
-#define MV64460_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7))
-#define MV64460_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10))
-#define MV64460_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10))
-#define MV64460_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10))
-#define MV64460_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10))
-#define MV64460_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10))
-#define MV64460_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10))
-#define MV64460_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10))
-#define MV64460_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10))
-#define MV64460_ETH_DSCP_0(port) (0x2420 + (port<<10))
-#define MV64460_ETH_DSCP_1(port) (0x2424 + (port<<10))
-#define MV64460_ETH_DSCP_2(port) (0x2428 + (port<<10))
-#define MV64460_ETH_DSCP_3(port) (0x242c + (port<<10))
-#define MV64460_ETH_DSCP_4(port) (0x2430 + (port<<10))
-#define MV64460_ETH_DSCP_5(port) (0x2434 + (port<<10))
-#define MV64460_ETH_DSCP_6(port) (0x2438 + (port<<10))
-#define MV64460_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10))
-#define MV64460_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10))
-#define MV64460_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10))
-#define MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10))
-#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10))
-#define MV64460_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10))
-#define MV64460_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10))
-#define MV64460_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10))
-#define MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10))
-#define MV64460_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10))
-#define MV64460_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10))
-#define MV64460_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
-#define MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
-#define MV64460_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
-#define MV64460_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10)
-#define MV64460_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
-#define MV64460_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
-#define MV64460_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
-#define MV64460_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10))
-#define MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10))
-#define MV64460_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10))
-#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10))
-#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10))
-#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10))
-#define MV64460_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10))
-#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10))
-#define MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10))
-#define MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
-#define MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
-
-/*******************************************/
-/* CUNIT Registers */
-/*******************************************/
-
- /* Address Decoding Register Map */
-
-#define MV64460_CUNIT_BASE_ADDR_REG0 0xf200
-#define MV64460_CUNIT_BASE_ADDR_REG1 0xf208
-#define MV64460_CUNIT_BASE_ADDR_REG2 0xf210
-#define MV64460_CUNIT_BASE_ADDR_REG3 0xf218
-#define MV64460_CUNIT_SIZE0 0xf204
-#define MV64460_CUNIT_SIZE1 0xf20c
-#define MV64460_CUNIT_SIZE2 0xf214
-#define MV64460_CUNIT_SIZE3 0xf21c
-#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240
-#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244
-#define MV64460_CUNIT_BASE_ADDR_ENABLE_REG 0xf250
-#define MV64460_MPSC0_ACCESS_PROTECTION_REG 0xf254
-#define MV64460_MPSC1_ACCESS_PROTECTION_REG 0xf258
-#define MV64460_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C
-
- /* Error Report Registers */
-
-#define MV64460_CUNIT_INTERRUPT_CAUSE_REG 0xf310
-#define MV64460_CUNIT_INTERRUPT_MASK_REG 0xf314
-#define MV64460_CUNIT_ERROR_ADDR 0xf318
-
- /* Cunit Control Registers */
-
-#define MV64460_CUNIT_ARBITER_CONTROL_REG 0xf300
-#define MV64460_CUNIT_CONFIG_REG 0xb40c
-#define MV64460_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304
-
- /* Cunit Debug Registers */
-
-#define MV64460_CUNIT_DEBUG_LOW 0xf340
-#define MV64460_CUNIT_DEBUG_HIGH 0xf344
-#define MV64460_CUNIT_MMASK 0xf380
-
- /* Cunit Base Address Enable Window Bits*/
-#define MV64460_CUNIT_BASE_ADDR_WIN_0_BIT 0x0
-#define MV64460_CUNIT_BASE_ADDR_WIN_1_BIT 0x1
-#define MV64460_CUNIT_BASE_ADDR_WIN_2_BIT 0x2
-#define MV64460_CUNIT_BASE_ADDR_WIN_3_BIT 0x3
-
- /* MPSCs Clocks Routing Registers */
-
-#define MV64460_MPSC_ROUTING_REG 0xb400
-#define MV64460_MPSC_RX_CLOCK_ROUTING_REG 0xb404
-#define MV64460_MPSC_TX_CLOCK_ROUTING_REG 0xb408
-
- /* MPSCs Interrupts Registers */
-
-#define MV64460_MPSC_CAUSE_REG(port) (0xb804 + (port<<3))
-#define MV64460_MPSC_MASK_REG(port) (0xb884 + (port<<3))
-
-#define MV64460_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12))
-#define MV64460_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12))
-#define MV64460_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12))
-#define MV64460_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12))
-
- /* MPSC0 Registers */
-
-
-/***************************************/
-/* SDMA Registers */
-/***************************************/
-
-#define MV64460_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13))
-#define MV64460_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13))
-#define MV64460_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13))
-#define MV64460_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13))
-#define MV64460_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13))
-
-#define MV64460_SDMA_CAUSE_REG 0xb800
-#define MV64460_SDMA_MASK_REG 0xb880
-
-
-/****************************************/
-/* SDMA Address Space Targets */
-/****************************************/
-
-#define MV64460_SDMA_DRAM_CS_0_TARGET 0x0e00
-#define MV64460_SDMA_DRAM_CS_1_TARGET 0x0d00
-#define MV64460_SDMA_DRAM_CS_2_TARGET 0x0b00
-#define MV64460_SDMA_DRAM_CS_3_TARGET 0x0700
-
-#define MV64460_SDMA_DEV_CS_0_TARGET 0x1e01
-#define MV64460_SDMA_DEV_CS_1_TARGET 0x1d01
-#define MV64460_SDMA_DEV_CS_2_TARGET 0x1b01
-#define MV64460_SDMA_DEV_CS_3_TARGET 0x1701
-
-#define MV64460_SDMA_BOOT_CS_TARGET 0x0f00
-
-#define MV64460_SDMA_SRAM_TARGET 0x0003
-#define MV64460_SDMA_60X_BUS_TARGET 0x4003
-
-#define MV64460_PCI_0_TARGET 0x0003
-#define MV64460_PCI_1_TARGET 0x0004
-
-
-/* Devices BAR and size registers */
-
-#define MV64460_DEV_CS0_BASE_ADDR 0x028
-#define MV64460_DEV_CS0_SIZE 0x030
-#define MV64460_DEV_CS1_BASE_ADDR 0x228
-#define MV64460_DEV_CS1_SIZE 0x230
-#define MV64460_DEV_CS2_BASE_ADDR 0x248
-#define MV64460_DEV_CS2_SIZE 0x250
-#define MV64460_DEV_CS3_BASE_ADDR 0x038
-#define MV64460_DEV_CS3_SIZE 0x040
-#define MV64460_BOOTCS_BASE_ADDR 0x238
-#define MV64460_BOOTCS_SIZE 0x240
-
-/* SDMA Window access protection */
-#define MV64460_SDMA_WIN_ACCESS_NOT_ALLOWED 0
-#define MV64460_SDMA_WIN_ACCESS_READ_ONLY 1
-#define MV64460_SDMA_WIN_ACCESS_FULL 2
-
-/* BRG Interrupts */
-
-#define MV64460_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3))
-#define MV64460_BRG_BAUDE_TUNING_REG(brg) (0xb204 + (brg<<3))
-#define MV64460_BRG_CAUSE_REG 0xb834
-#define MV64460_BRG_MASK_REG 0xb8b4
-
-/****************************************/
-/* DMA Channel Control */
-/****************************************/
-
-#define MV64460_DMA_CHANNEL0_CONTROL 0x840
-#define MV64460_DMA_CHANNEL0_CONTROL_HIGH 0x880
-#define MV64460_DMA_CHANNEL1_CONTROL 0x844
-#define MV64460_DMA_CHANNEL1_CONTROL_HIGH 0x884
-#define MV64460_DMA_CHANNEL2_CONTROL 0x848
-#define MV64460_DMA_CHANNEL2_CONTROL_HIGH 0x888
-#define MV64460_DMA_CHANNEL3_CONTROL 0x84C
-#define MV64460_DMA_CHANNEL3_CONTROL_HIGH 0x88C
-
-
-/****************************************/
-/* IDMA Registers */
-/****************************************/
-
-#define MV64460_DMA_CHANNEL0_BYTE_COUNT 0x800
-#define MV64460_DMA_CHANNEL1_BYTE_COUNT 0x804
-#define MV64460_DMA_CHANNEL2_BYTE_COUNT 0x808
-#define MV64460_DMA_CHANNEL3_BYTE_COUNT 0x80C
-#define MV64460_DMA_CHANNEL0_SOURCE_ADDR 0x810
-#define MV64460_DMA_CHANNEL1_SOURCE_ADDR 0x814
-#define MV64460_DMA_CHANNEL2_SOURCE_ADDR 0x818
-#define MV64460_DMA_CHANNEL3_SOURCE_ADDR 0x81c
-#define MV64460_DMA_CHANNEL0_DESTINATION_ADDR 0x820
-#define MV64460_DMA_CHANNEL1_DESTINATION_ADDR 0x824
-#define MV64460_DMA_CHANNEL2_DESTINATION_ADDR 0x828
-#define MV64460_DMA_CHANNEL3_DESTINATION_ADDR 0x82C
-#define MV64460_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830
-#define MV64460_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834
-#define MV64460_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838
-#define MV64460_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C
-#define MV64460_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870
-#define MV64460_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874
-#define MV64460_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878
-#define MV64460_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C
-
- /* IDMA Address Decoding Base Address Registers */
-
-#define MV64460_DMA_BASE_ADDR_REG0 0xa00
-#define MV64460_DMA_BASE_ADDR_REG1 0xa08
-#define MV64460_DMA_BASE_ADDR_REG2 0xa10
-#define MV64460_DMA_BASE_ADDR_REG3 0xa18
-#define MV64460_DMA_BASE_ADDR_REG4 0xa20
-#define MV64460_DMA_BASE_ADDR_REG5 0xa28
-#define MV64460_DMA_BASE_ADDR_REG6 0xa30
-#define MV64460_DMA_BASE_ADDR_REG7 0xa38
-
- /* IDMA Address Decoding Size Address Register */
-
-#define MV64460_DMA_SIZE_REG0 0xa04
-#define MV64460_DMA_SIZE_REG1 0xa0c
-#define MV64460_DMA_SIZE_REG2 0xa14
-#define MV64460_DMA_SIZE_REG3 0xa1c
-#define MV64460_DMA_SIZE_REG4 0xa24
-#define MV64460_DMA_SIZE_REG5 0xa2c
-#define MV64460_DMA_SIZE_REG6 0xa34
-#define MV64460_DMA_SIZE_REG7 0xa3C
-
- /* IDMA Address Decoding High Address Remap and Access
- Protection Registers */
-
-#define MV64460_DMA_HIGH_ADDR_REMAP_REG0 0xa60
-#define MV64460_DMA_HIGH_ADDR_REMAP_REG1 0xa64
-#define MV64460_DMA_HIGH_ADDR_REMAP_REG2 0xa68
-#define MV64460_DMA_HIGH_ADDR_REMAP_REG3 0xa6C
-#define MV64460_DMA_BASE_ADDR_ENABLE_REG 0xa80
-#define MV64460_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70
-#define MV64460_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74
-#define MV64460_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78
-#define MV64460_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c
-#define MV64460_DMA_ARBITER_CONTROL 0x860
-#define MV64460_DMA_CROSS_BAR_TIMEOUT 0x8d0
-
- /* IDMA Headers Retarget Registers */
-
-#define MV64460_DMA_HEADERS_RETARGET_CONTROL 0xa84
-#define MV64460_DMA_HEADERS_RETARGET_BASE 0xa88
-
- /* IDMA Interrupt Register */
-
-#define MV64460_DMA_INTERRUPT_CAUSE_REG 0x8c0
-#define MV64460_DMA_INTERRUPT_CAUSE_MASK 0x8c4
-#define MV64460_DMA_ERROR_ADDR 0x8c8
-#define MV64460_DMA_ERROR_SELECT 0x8cc
-
- /* IDMA Debug Register ( for internal use ) */
-
-#define MV64460_DMA_DEBUG_LOW 0x8e0
-#define MV64460_DMA_DEBUG_HIGH 0x8e4
-#define MV64460_DMA_SPARE 0xA8C
-
-/****************************************/
-/* Timer_Counter */
-/****************************************/
-
-#define MV64460_TIMER_COUNTER0 0x850
-#define MV64460_TIMER_COUNTER1 0x854
-#define MV64460_TIMER_COUNTER2 0x858
-#define MV64460_TIMER_COUNTER3 0x85C
-#define MV64460_TIMER_COUNTER_0_3_CONTROL 0x864
-#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868
-#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c
-
-/****************************************/
-/* Watchdog registers */
-/****************************************/
-
-#define MV64460_WATCHDOG_CONFIG_REG 0xb410
-#define MV64460_WATCHDOG_VALUE_REG 0xb414
-
-/****************************************/
-/* I2C Registers */
-/****************************************/
-
-#define MV64460_I2C_SLAVE_ADDR 0xc000
-#define MV64460_I2C_EXTENDED_SLAVE_ADDR 0xc010
-#define MV64460_I2C_DATA 0xc004
-#define MV64460_I2C_CONTROL 0xc008
-#define MV64460_I2C_STATUS_BAUDE_RATE 0xc00C
-#define MV64460_I2C_SOFT_RESET 0xc01c
-
-/****************************************/
-/* GPP Interface Registers */
-/****************************************/
-
-#define MV64460_GPP_IO_CONTROL 0xf100
-#define MV64460_GPP_LEVEL_CONTROL 0xf110
-#define MV64460_GPP_VALUE 0xf104
-#define MV64460_GPP_INTERRUPT_CAUSE 0xf108
-#define MV64460_GPP_INTERRUPT_MASK0 0xf10c
-#define MV64460_GPP_INTERRUPT_MASK1 0xf114
-#define MV64460_GPP_VALUE_SET 0xf118
-#define MV64460_GPP_VALUE_CLEAR 0xf11c
-
-/****************************************/
-/* Interrupt Controller Registers */
-/****************************************/
-
-/****************************************/
-/* Interrupts */
-/****************************************/
-
-#define MV64460_MAIN_INTERRUPT_CAUSE_LOW 0x004
-#define MV64460_MAIN_INTERRUPT_CAUSE_HIGH 0x00c
-#define MV64460_CPU_INTERRUPT0_MASK_LOW 0x014
-#define MV64460_CPU_INTERRUPT0_MASK_HIGH 0x01c
-#define MV64460_CPU_INTERRUPT0_SELECT_CAUSE 0x024
-#define MV64460_CPU_INTERRUPT1_MASK_LOW 0x034
-#define MV64460_CPU_INTERRUPT1_MASK_HIGH 0x03c
-#define MV64460_CPU_INTERRUPT1_SELECT_CAUSE 0x044
-#define MV64460_INTERRUPT0_MASK_0_LOW 0x054
-#define MV64460_INTERRUPT0_MASK_0_HIGH 0x05c
-#define MV64460_INTERRUPT0_SELECT_CAUSE 0x064
-#define MV64460_INTERRUPT1_MASK_0_LOW 0x074
-#define MV64460_INTERRUPT1_MASK_0_HIGH 0x07c
-#define MV64460_INTERRUPT1_SELECT_CAUSE 0x084
-
-/****************************************/
-/* MPP Interface Registers */
-/****************************************/
-
-#define MV64460_MPP_CONTROL0 0xf000
-#define MV64460_MPP_CONTROL1 0xf004
-#define MV64460_MPP_CONTROL2 0xf008
-#define MV64460_MPP_CONTROL3 0xf00c
-
-/****************************************/
-/* Serial Initialization registers */
-/****************************************/
-
-#define MV64460_SERIAL_INIT_LAST_DATA 0xf324
-#define MV64460_SERIAL_INIT_CONTROL 0xf328
-#define MV64460_SERIAL_INIT_STATUS 0xf32c
-
-
-#endif /* __INCgt64460rh */
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Based on original work by
- * Roel Loeffen, (C) Copyright 2006 Prodrive B.V.
- * Josh Huber, (C) Copyright 2001 Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
- * modifications for the cpci750 by reinhard.arlt@esd-electronics.com
- * modifications for the P3M750 by roel.loeffen@prodrive.nl
- */
-
-/*
- * p3m750.c - main board support/init for the Prodrive p3m750/p3m7448.
- */
-
-#include <common.h>
-#include <74xx_7xx.h>
-#include "../../Marvell/include/memory.h"
-#include "../../Marvell/include/pci.h"
-#include "../../Marvell/include/mv_gen_reg.h"
-#include <net.h>
-#include <i2c.h>
-
-#include "eth.h"
-#include "mpsc.h"
-#include "64460.h"
-#include "mv_regs.h"
-#include "p3mx.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#undef DEBUG
-/*#define DEBUG */
-
-#ifdef CONFIG_PCI
-#define MAP_PCI
-#endif /* of CONFIG_PCI */
-
-#ifdef DEBUG
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-extern flash_info_t flash_info[];
-
-/* ------------------------------------------------------------------------- */
-
-/* this is the current GT register space location */
-/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
-
-/* Unfortunately, we cant change it while we are in flash, so we initialize it
- * to the "final" value. This means that any debug_led calls before
- * board_early_init_f wont work right (like in cpu_init_f).
- * See also my_remap_gt_regs below. (NTL)
- */
-
-void board_prebootm_init (void);
-unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
-int display_mem_map (void);
-void set_led(int);
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * This is a version of the GT register space remapping function that
- * doesn't touch globals (meaning, it's ok to run from flash.)
- *
- * Unfortunately, this has the side effect that a writable
- * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
- */
-
-void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
-{
- u32 temp;
-
- /* check and see if it's already moved */
- temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
- if ((temp & 0xffff) == new_loc >> 16)
- return;
-
- temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
- 0xffff0000) | (new_loc >> 16);
-
- out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
-
- while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
-}
-
-#ifdef CONFIG_PCI
-
-static void gt_pci_config (void)
-{
- unsigned int stat;
- unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, */
- /* FuncNum 10:8, RegNum 7:2 */
-
- /*
- * In PCIX mode devices provide their own bus and device numbers.
- * We query the Discovery II's
- * config registers by writing ones to the bus and device.
- * We then update the Virtual register with the correct value for the
- * bus and device.
- */
- if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /* if PCI-X */
- GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
-
- GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
-
- GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
- GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
- (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
-
- }
- if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /* if PCI-X */
- GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
- GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
-
- GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
- GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
- (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
- }
-
- /* Enable master */
- PCI_MASTER_ENABLE (0, SELF);
- PCI_MASTER_ENABLE (1, SELF);
-
- /* Enable PCI0/1 Mem0 and IO 0 disable all others */
- GT_REG_READ (BASE_ADDR_ENABLE, &stat);
- stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) |
- (1 << 18);
- stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
- GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
-
- /* ronen:
- * add write to pci remap registers for 64460.
- * in 64360 when writing to pci base go and overide remap automaticaly,
- * in 64460 it doesn't
- */
- GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16);
- GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16);
- GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
-
- GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
-
- GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16);
- GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16);
- GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
-
- GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
-
- /* PCI interface settings */
- /* Timeout set to retry forever */
- GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
- GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
-
- /* ronen - enable only CS0 and Internal reg!! */
- GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
- GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
-
- /* ronen:
- * update the pci internal registers base address.
- */
-#ifdef MAP_PCI
- for (stat = 0; stat <= PCI_HOST1; stat++)
- pciWriteConfigReg (stat,
- PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
- SELF, CONFIG_SYS_GT_REGS);
-#endif
-
-}
-#endif
-
-/* Setup CPU interface paramaters */
-static void gt_cpu_config (void)
-{
- cpu_t cpu = get_cpu_type ();
- ulong tmp;
-
- /* cpu configuration register */
- tmp = GTREGREAD (CPU_CONFIGURATION);
- /* set the SINGLE_CPU bit see MV64460 */
-#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
- tmp |= CPU_CONF_SINGLE_CPU;
-#endif
- tmp &= ~CPU_CONF_AACK_DELAY_2;
- tmp |= CPU_CONF_DP_VALID;
- tmp |= CPU_CONF_AP_VALID;
- tmp |= CPU_CONF_PIPELINE;
- GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */
-
- /* CPU master control register */
- tmp = GTREGREAD (CPU_MASTER_CONTROL);
- tmp |= CPU_MAST_CTL_ARB_EN;
-
- if ((cpu == CPU_7400) ||
- (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
-
- tmp |= CPU_MAST_CTL_CLEAN_BLK;
- tmp |= CPU_MAST_CTL_FLUSH_BLK;
-
- } else {
- /* cleanblock must be cleared for CPUs
- * that do not support this command (603e, 750)
- * see Res#1 */
- tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
- tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
- }
- GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
-}
-
-/*
- * board_early_init_f.
- *
- * set up gal. device mappings, etc.
- */
-int board_early_init_f (void)
-{
- /* set up the GT the way the kernel wants it
- * the call to move the GT register space will obviously
- * fail if it has already been done, but we're going to assume
- * that if it's not at the power-on location, it's where we put
- * it last time. (huber)
- */
- my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
-
-#ifdef CONFIG_PCI
- gt_pci_config ();
-#endif
- /* mask all external interrupt sources */
- GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
- GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
- /* new in >MV6436x */
- GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
- GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
- /* --------------------- */
- GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
- GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
- GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
- GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
-
- /* Device and Boot bus settings
- */
- memoryMapDeviceSpace(DEVICE0, 0, 0);
- GT_REG_WRITE(DEVICE_BANK0PARAMETERS, 0);
- memoryMapDeviceSpace(DEVICE1, 0, 0);
- GT_REG_WRITE(DEVICE_BANK1PARAMETERS, 0);
- memoryMapDeviceSpace(DEVICE2, 0, 0);
- GT_REG_WRITE(DEVICE_BANK2PARAMETERS, 0);
- memoryMapDeviceSpace(DEVICE3, 0, 0);
- GT_REG_WRITE(DEVICE_BANK3PARAMETERS, 0);
-
- GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_BOOT_PAR);
-
- gt_cpu_config();
-
- /* MPP setup */
- GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
- GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
- GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
- GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
-
- GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
-
- set_led(LED_RED);
-
- return 0;
-}
-
-/* various things to do after relocation */
-
-int misc_init_r ()
-{
- u8 val;
-
- icache_enable ();
-#ifdef CONFIG_SYS_L2
- l2cache_enable ();
-#endif
-#ifdef CONFIG_MPSC
- mpsc_sdma_init ();
- mpsc_init2 ();
-#endif
-
- /*
- * Enable trickle changing in RTC upon powerup
- * No diode, 250 ohm series resistor
- */
- val = 0xa5;
- i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 8, 1, &val, 1);
-
- return 0;
-}
-
-void after_reloc (ulong dest_addr, gd_t * gd)
-{
- memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE, CONFIG_SYS_BOOT_SIZE);
-
-/* display_mem_map(); */
-
- /* now, jump to the main U-Boot board init code */
- set_led(LED_GREEN);
- board_init_r (gd, dest_addr);
- /* NOTREACHED */
-}
-
-/*
- * Check Board Identity:
- * right now, assume borad type. (there is just one...after all)
- */
-
-int checkboard (void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- printf("Board: %s", CONFIG_SYS_BOARD_NAME);
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return (0);
-}
-
-void set_led(int col)
-{
- int tmp;
- int on_pin;
- int off_pin;
-
- /* Program Mpp[22] as Gpp[22]
- * Program Mpp[23] as Gpp[23]
- */
- tmp = GTREGREAD(MPP_CONTROL2);
- tmp &= 0x00ffffff;
- GT_REG_WRITE(MPP_CONTROL2,tmp);
-
- /* Program Gpp[22] and Gpp[23] as output
- */
- tmp = GTREGREAD(GPP_IO_CONTROL);
- tmp |= 0x00C00000;
- GT_REG_WRITE(GPP_IO_CONTROL, tmp);
-
- /* Program Gpp[22] and Gpp[23] as active high
- */
- tmp = GTREGREAD(GPP_LEVEL_CONTROL);
- tmp &= 0xff3fffff;
- GT_REG_WRITE(GPP_LEVEL_CONTROL, tmp);
-
- switch(col) {
- default:
- case LED_OFF :
- on_pin = 0;
- off_pin = ((1 << 23) | (1 << 22));
- break;
- case LED_RED :
- on_pin = (1 << 23);
- off_pin = (1 << 22);
- break;
- case LED_GREEN :
- on_pin = (1 << 22);
- off_pin = (1 << 23);
- break;
- case LED_ORANGE :
- on_pin = ((1 << 23) | (1 << 22));
- off_pin = 0;
- break;
- }
-
- /* Set output Gpp[22] and Gpp[23]
- */
- tmp = GTREGREAD(GPP_VALUE);
- tmp |= on_pin;
- tmp &= ~off_pin;
- GT_REG_WRITE(GPP_VALUE, tmp);
-}
-
-int display_mem_map (void)
-{
- int i;
- unsigned int base, size, width;
-#ifdef CONFIG_PCI
- int j;
-#endif
-
- /* SDRAM */
- printf ("SD (DDR) RAM\n");
- for (i = 0; i <= BANK3; i++) {
- base = memoryGetBankBaseAddress (i);
- size = memoryGetBankSize (i);
- if (size != 0)
- printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
- i, base, size >> 20);
- }
-#ifdef CONFIG_PCI
- /* CPU's PCI windows */
- for (i = 0; i <= PCI_HOST1; i++) {
- printf ("\nCPU's PCI %d windows\n", i);
- base = pciGetSpaceBase (i, PCI_IO);
- size = pciGetSpaceSize (i, PCI_IO);
- printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base,
- size >> 20);
- /* ronen currently only first PCI MEM is used 3 */
- for (j = 0; j <= PCI_REGION0; j++) {
- base = pciGetSpaceBase (i, j);
- size = pciGetSpaceSize (i, j);
- printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n",
- j, base, size >> 20);
- }
- }
-#endif /* of CONFIG_PCI */
-
- /* Bootrom */
- base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */
- size = memoryGetDeviceSize (BOOT_DEVICE);
- width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
- printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\t- FLASH\n",
- base, size >> 20, width);
-
- return (0);
-}
-
-/* DRAM check routines copied from gw8260 */
-
-#if defined (CONFIG_SYS_DRAM_TEST)
-
-/*********************************************************************/
-/* NAME: move64() - moves a double word (64-bit) */
-/* */
-/* DESCRIPTION: */
-/* this function performs a double word move from the data at */
-/* the source pointer to the location at the destination pointer. */
-/* */
-/* INPUTS: */
-/* unsigned long long *src - pointer to data to move */
-/* */
-/* OUTPUTS: */
-/* unsigned long long *dest - pointer to locate to move data */
-/* */
-/* RETURNS: */
-/* None */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* May cloober fr0. */
-/* */
-/*********************************************************************/
-static void move64 (unsigned long long *src, unsigned long long *dest)
-{
- asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
- "stfd 0, 0(4)" /* *dest = fpr0 */
- : : : "fr0"); /* Clobbers fr0 */
- return;
-}
-
-
-#if defined (CONFIG_SYS_DRAM_TEST_DATA)
-
-unsigned long long pattern[] = {
- 0xaaaaaaaaaaaaaaaaULL,
- 0xccccccccccccccccULL,
- 0xf0f0f0f0f0f0f0f0ULL,
- 0xff00ff00ff00ff00ULL,
- 0xffff0000ffff0000ULL,
- 0xffffffff00000000ULL,
- 0x00000000ffffffffULL,
- 0x0000ffff0000ffffULL,
- 0x00ff00ff00ff00ffULL,
- 0x0f0f0f0f0f0f0f0fULL,
- 0x3333333333333333ULL,
- 0x5555555555555555ULL
-};
-
-/*********************************************************************/
-/* NAME: mem_test_data() - test data lines for shorts and opens */
-/* */
-/* DESCRIPTION: */
-/* Tests data lines for shorts and opens by forcing adjacent data */
-/* to opposite states. Because the data lines could be routed in */
-/* an arbitrary manner the must ensure test patterns ensure that */
-/* every case is tested. By using the following series of binary */
-/* patterns every combination of adjacent bits is test regardless */
-/* of routing. */
-/* */
-/* ...101010101010101010101010 */
-/* ...110011001100110011001100 */
-/* ...111100001111000011110000 */
-/* ...111111110000000011111111 */
-/* */
-/* Carrying this out, gives us six hex patterns as follows: */
-/* */
-/* 0xaaaaaaaaaaaaaaaa */
-/* 0xcccccccccccccccc */
-/* 0xf0f0f0f0f0f0f0f0 */
-/* 0xff00ff00ff00ff00 */
-/* 0xffff0000ffff0000 */
-/* 0xffffffff00000000 */
-/* */
-/* The number test patterns will always be given by: */
-/* */
-/* log(base 2)(number data bits) = log2 (64) = 6 */
-/* */
-/* To test for short and opens to other signals on our boards. we */
-/* simply */
-/* test with the 1's complemnt of the paterns as well. */
-/* */
-/* OUTPUTS: */
-/* Displays failing test pattern */
-/* */
-/* RETURNS: */
-/* 0 - Passed test */
-/* 1 - Failed test */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* Assumes only one one SDRAM bank */
-/* */
-/*********************************************************************/
-int mem_test_data (void)
-{
- unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
- unsigned long long temp64 = 0;
- int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
- int i;
- unsigned int hi, lo;
-
- for (i = 0; i < num_patterns; i++) {
- move64 (&(pattern[i]), pmem);
- move64 (pmem, &temp64);
-
- /* hi = (temp64>>32) & 0xffffffff; */
- /* lo = temp64 & 0xffffffff; */
- /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
-
- hi = (pattern[i] >> 32) & 0xffffffff;
- lo = pattern[i] & 0xffffffff;
- /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
-
- if (temp64 != pattern[i]) {
- printf ("\n Data Test Failed, pattern 0x%08x%08x",
- hi, lo);
- return 1;
- }
- }
-
- return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_DATA */
-
-#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
-/*********************************************************************/
-/* NAME: mem_test_address() - test address lines */
-/* */
-/* DESCRIPTION: */
-/* This function performs a test to verify that each word im */
-/* memory is uniquly addressable. The test sequence is as follows: */
-/* */
-/* 1) write the address of each word to each word. */
-/* 2) verify that each location equals its address */
-/* */
-/* OUTPUTS: */
-/* Displays failing test pattern and address */
-/* */
-/* RETURNS: */
-/* 0 - Passed test */
-/* 1 - Failed test */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/* */
-/*********************************************************************/
-int mem_test_address (void)
-{
- volatile unsigned int *pmem =
- (volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
- const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
- unsigned int i;
-
- /* write address to each location */
- for (i = 0; i < size; i++)
- pmem[i] = i;
-
- /* verify each loaction */
- for (i = 0; i < size; i++) {
- if (pmem[i] != i) {
- printf ("\n Address Test Failed at 0x%x", i);
- return 1;
- }
- }
- return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
-
-#if defined (CONFIG_SYS_DRAM_TEST_WALK)
-/*********************************************************************/
-/* NAME: mem_march() - memory march */
-/* */
-/* DESCRIPTION: */
-/* Marches up through memory. At each location verifies rmask if */
-/* read = 1. At each location write wmask if write = 1. Displays */
-/* failing address and pattern. */
-/* */
-/* INPUTS: */
-/* volatile unsigned long long * base - start address of test */
-/* unsigned int size - number of dwords(64-bit) to test */
-/* unsigned long long rmask - read verify mask */
-/* unsigned long long wmask - wrtie verify mask */
-/* short read - verifies rmask if read = 1 */
-/* short write - writes wmask if write = 1 */
-/* */
-/* OUTPUTS: */
-/* Displays failing test pattern and address */
-/* */
-/* RETURNS: */
-/* 0 - Passed test */
-/* 1 - Failed test */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/* */
-/*********************************************************************/
-int mem_march (volatile unsigned long long *base,
- unsigned int size,
- unsigned long long rmask,
- unsigned long long wmask, short read, short write)
-{
- unsigned int i;
- unsigned long long temp = 0;
- unsigned int hitemp, lotemp, himask, lomask;
-
- for (i = 0; i < size; i++) {
- if (read != 0) {
- /* temp = base[i]; */
- move64 ((unsigned long long *) &(base[i]), &temp);
- if (rmask != temp) {
- hitemp = (temp >> 32) & 0xffffffff;
- lotemp = temp & 0xffffffff;
- himask = (rmask >> 32) & 0xffffffff;
- lomask = rmask & 0xffffffff;
-
- printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
- return 1;
- }
- }
- if (write != 0) {
- /* base[i] = wmask; */
- move64 (&wmask, (unsigned long long *) &(base[i]));
- }
- }
- return 0;
-}
-#endif /* CONFIG_SYS_DRAM_TEST_WALK */
-
-/*********************************************************************/
-/* NAME: mem_test_walk() - a simple walking ones test */
-/* */
-/* DESCRIPTION: */
-/* Performs a walking ones through entire physical memory. The */
-/* test uses as series of memory marches, mem_march(), to verify */
-/* and write the test patterns to memory. The test sequence is as */
-/* follows: */
-/* 1) march writing 0000...0001 */
-/* 2) march verifying 0000...0001 , writing 0000...0010 */
-/* 3) repeat step 2 shifting masks left 1 bit each time unitl */
-/* the write mask equals 1000...0000 */
-/* 4) march verifying 1000...0000 */
-/* The test fails if any of the memory marches return a failure. */
-/* */
-/* OUTPUTS: */
-/* Displays which pass on the memory test is executing */
-/* */
-/* RETURNS: */
-/* 0 - Passed test */
-/* 1 - Failed test */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/* */
-/*********************************************************************/
-int mem_test_walk (void)
-{
- unsigned long long mask;
- volatile unsigned long long *pmem =
- (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
- const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
-
- unsigned int i;
-
- mask = 0x01;
-
- printf ("Initial Pass");
- mem_march (pmem, size, 0x0, 0x1, 0, 1);
-
- printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
- printf (" ");
- printf (" ");
- printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
-
- for (i = 0; i < 63; i++) {
- printf ("Pass %2d", i + 2);
- if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
- /*printf("mask: 0x%x, pass: %d, ", mask, i); */
- return 1;
- }
- mask = mask << 1;
- printf ("\b\b\b\b\b\b\b");
- }
-
- printf ("Last Pass");
- if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
- /* printf("mask: 0x%x", mask); */
- return 1;
- }
- printf ("\b\b\b\b\b\b\b\b\b");
- printf (" ");
- printf ("\b\b\b\b\b\b\b\b\b");
-
- return 0;
-}
-
-/*********************************************************************/
-/* NAME: testdram() - calls any enabled memory tests */
-/* */
-/* DESCRIPTION: */
-/* Runs memory tests if the environment test variables are set to */
-/* 'y'. */
-/* */
-/* INPUTS: */
-/* testdramdata - If set to 'y', data test is run. */
-/* testdramaddress - If set to 'y', address test is run. */
-/* testdramwalk - If set to 'y', walking ones test is run */
-/* */
-/* OUTPUTS: */
-/* None */
-/* */
-/* RETURNS: */
-/* 0 - Passed test */
-/* 1 - Failed test */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/* */
-/*********************************************************************/
-int testdram (void)
-{
- int rundata = 0;
- int runaddress = 0;
- int runwalk = 0;
-
-#ifdef CONFIG_SYS_DRAM_TEST_DATA
- rundata = getenv_yesno("testdramdata") == 1;
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
- runaddress = getenv_yesno("testdramaddress") == 1;
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_WALK
- runwalk = getenv_yesno("testdramwalk") == 1;
-#endif
-
- if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
- printf ("Testing RAM from 0x%08x to 0x%08x ... "
- "(don't panic... that will take a moment !!!!)\n",
- CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
-#ifdef CONFIG_SYS_DRAM_TEST_DATA
- if (rundata == 1) {
- printf ("Test DATA ... ");
- if (mem_test_data () == 1) {
- printf ("failed \n");
- return 1;
- } else
- printf ("ok \n");
- }
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
- if (runaddress == 1) {
- printf ("Test ADDRESS ... ");
- if (mem_test_address () == 1) {
- printf ("failed \n");
- return 1;
- } else
- printf ("ok \n");
- }
-#endif
-#ifdef CONFIG_SYS_DRAM_TEST_WALK
- if (runwalk == 1) {
- printf ("Test WALKING ONEs ... ");
- if (mem_test_walk () == 1) {
- printf ("failed \n");
- return 1;
- } else
- printf ("ok \n");
- }
-#endif
- if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
- printf ("passed\n");
- return 0;
-
-}
-#endif /* CONFIG_SYS_DRAM_TEST */
-
-/* ronen - the below functions are used by the bootm function */
-/* - we map the base register to fbe00000 (same mapping as in the LSP) */
-/* - we turn off the RX gig dmas - to prevent the dma from overunning */
-/* the kernel data areas. */
-/* - we diable and invalidate the icache and dcache. */
-void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
-{
- u32 temp;
-
- temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
- if ((temp & 0xffff) == new_loc >> 16)
- return;
-
- temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
- 0xffff0000) | (new_loc >> 16);
-
- out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
-
- while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
- new_loc |
- (INTERNAL_SPACE_DECODE)))))
- != temp);
-
-}
-
-int board_eth_init(bd_t *bis)
-{
- return mv6446x_eth_initialize(bis);
-}
+++ /dev/null
-/*
- * (C) Copyright 2005
- *
- * Roel Loeffen, (C) Copyright 2006 Prodrive B.V. roel.loeffen@prodrive.nl
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __P3MX_H__
-#define __P3MX_H__
-
-#define LED_OFF 1
-#define LED_GREEN 2
-#define LED_RED 3
-#define LED_ORANGE 4
-
-#endif /* __P3MX_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-/* PCI.c - PCI functions */
-
-
-#include <common.h>
-#ifdef CONFIG_PCI
-#include <pci.h>
-
-#include "../../Marvell/include/pci.h"
-
-#undef DEBUG
-#undef IDE_SET_NATIVE_MODE
-static unsigned int local_buses[] = { 0, 0 };
-
-static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
- {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
- {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
-};
-
-#ifdef CONFIG_USE_CPCIDVI
-typedef struct {
- unsigned int base;
- unsigned int init;
-} GT_CPCIDVI_ROM_T;
-
-static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0};
-#endif
-
-#ifdef DEBUG
-static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
-static void gt_pci_bus_mode_display (PCI_HOST host)
-{
- unsigned int mode;
-
-
- mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
- switch (mode) {
- case 0:
- printf ("PCI %d bus mode: Conventional PCI\n", host);
- break;
- case 1:
- printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
- break;
- case 2:
- printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
- break;
- case 3:
- printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
- break;
- default:
- printf ("Unknown BUS %d\n", mode);
- }
-}
-#endif
-
-static const unsigned int pci_p2p_configuration_reg[] = {
- PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
-};
-
-static const unsigned int pci_configuration_address[] = {
- PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
-};
-
-static const unsigned int pci_configuration_data[] = {
- PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
- PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
-};
-
-static const unsigned int pci_error_cause_reg[] = {
- PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
-};
-
-static const unsigned int pci_arbiter_control[] = {
- PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
-};
-
-static const unsigned int pci_address_space_en[] = {
- PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
-};
-
-static const unsigned int pci_snoop_control_base_0_low[] = {
- PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
-};
-static const unsigned int pci_snoop_control_top_0[] = {
- PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
-};
-
-static const unsigned int pci_access_control_base_0_low[] = {
- PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
-};
-static const unsigned int pci_access_control_top_0[] = {
- PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
-};
-
-static const unsigned int pci_scs_bank_size[2][4] = {
- {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
- PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
- {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
- PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
-};
-
-static const unsigned int pci_p2p_configuration[] = {
- PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
-};
-
-
-/********************************************************************
-* pciWriteConfigReg - Write to a PCI configuration register
-* - Make sure the GT is configured as a master before writing
-* to another device on the PCI.
-* - The function takes care of Big/Little endian conversion.
-*
-*
-* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec
-* (or any other PCI device spec)
-* pciDevNum: The device number needs to be addressed.
-*
-* Configuration Address 0xCF8:
-*
-* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
-* |congif|Reserved| Bus |Device|Function|Register|00|
-* |Enable| |Number|Number| Number | Number | | <=field Name
-*
-*********************************************************************/
-void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
- unsigned int pciDevNum, unsigned int data)
-{
- volatile unsigned int DataForAddrReg;
- unsigned int functionNum;
- unsigned int busNum = 0;
- unsigned int addr;
-
- if (pciDevNum > 32) /* illegal device Number */
- return;
- if (pciDevNum == SELF) { /* configure our configuration space. */
- pciDevNum =
- (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
- 0x1f;
- busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
- 0xff0000;
- }
- functionNum = regOffset & 0x00000700;
- pciDevNum = pciDevNum << 11;
- regOffset = regOffset & 0xfc;
- DataForAddrReg =
- (regOffset | pciDevNum | functionNum | busNum) | BIT31;
- GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
- GT_REG_READ (pci_configuration_address[host], &addr);
- if (addr != DataForAddrReg)
- return;
- GT_REG_WRITE (pci_configuration_data[host], data);
-}
-
-/********************************************************************
-* pciReadConfigReg - Read from a PCI0 configuration register
-* - Make sure the GT is configured as a master before reading
-* from another device on the PCI.
-* - The function takes care of Big/Little endian conversion.
-* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
-* spec)
-* pciDevNum: The device number needs to be addressed.
-* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
-* cause register to make sure the data is valid
-*
-* Configuration Address 0xCF8:
-*
-* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
-* |congif|Reserved| Bus |Device|Function|Register|00|
-* |Enable| |Number|Number| Number | Number | | <=field Name
-*
-*********************************************************************/
-unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
- unsigned int pciDevNum)
-{
- volatile unsigned int DataForAddrReg;
- unsigned int data;
- unsigned int functionNum;
- unsigned int busNum = 0;
-
- if (pciDevNum > 32) /* illegal device Number */
- return 0xffffffff;
- if (pciDevNum == SELF) { /* configure our configuration space. */
- pciDevNum =
- (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
- 0x1f;
- busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
- 0xff0000;
- }
- functionNum = regOffset & 0x00000700;
- pciDevNum = pciDevNum << 11;
- regOffset = regOffset & 0xfc;
- DataForAddrReg =
- (regOffset | pciDevNum | functionNum | busNum) | BIT31;
- GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
- GT_REG_READ (pci_configuration_address[host], &data);
- if (data != DataForAddrReg)
- return 0xffffffff;
- GT_REG_READ (pci_configuration_data[host], &data);
- return data;
-}
-
-/********************************************************************
-* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
-* the agent is placed on another Bus. For more
-* information read P2P in the PCI spec.
-*
-* Inputs: unsigned int regOffset - The register offset as it apears in the
-* GT spec (or any other PCI device spec).
-* unsigned int pciDevNum - The device number needs to be addressed.
-* unsigned int busNum - On which bus does the Target agent connect
-* to.
-* unsigned int data - data to be written.
-*
-* Configuration Address 0xCF8:
-*
-* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
-* |congif|Reserved| Bus |Device|Function|Register|01|
-* |Enable| |Number|Number| Number | Number | | <=field Name
-*
-* The configuration Address is configure as type-I (bits[1:0] = '01') due to
-* PCI spec referring to P2P.
-*
-*********************************************************************/
-void pciOverBridgeWriteConfigReg (PCI_HOST host,
- unsigned int regOffset,
- unsigned int pciDevNum,
- unsigned int busNum, unsigned int data)
-{
- unsigned int DataForReg;
- unsigned int functionNum;
-
- functionNum = regOffset & 0x00000700;
- pciDevNum = pciDevNum << 11;
- regOffset = regOffset & 0xff;
- busNum = busNum << 16;
- if (pciDevNum == SELF) { /* This board */
- DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
- } else {
- DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
- BIT31 | BIT0;
- }
- GT_REG_WRITE (pci_configuration_address[host], DataForReg);
- GT_REG_WRITE (pci_configuration_data[host], data);
-}
-
-
-/********************************************************************
-* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where
-* the agent target locate on another PCI bus.
-* - Make sure the GT is configured as a master
-* before reading from another device on the PCI.
-* - The function takes care of Big/Little endian
-* conversion.
-* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
-* spec). (configuration register offset.)
-* pciDevNum: The device number needs to be addressed.
-* busNum: the Bus number where the agent is place.
-* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
-* cause register to make sure the data is valid
-*
-* Configuration Address 0xCF8:
-*
-* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
-* |congif|Reserved| Bus |Device|Function|Register|01|
-* |Enable| |Number|Number| Number | Number | | <=field Name
-*
-*********************************************************************/
-unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
- unsigned int regOffset,
- unsigned int pciDevNum,
- unsigned int busNum)
-{
- unsigned int DataForReg;
- unsigned int data;
- unsigned int functionNum;
-
- functionNum = regOffset & 0x00000700;
- pciDevNum = pciDevNum << 11;
- regOffset = regOffset & 0xff;
- busNum = busNum << 16;
- if (pciDevNum == SELF) { /* This board */
- DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
- } else { /* agent on another bus */
-
- DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
- BIT0 | BIT31;
- }
- GT_REG_WRITE (pci_configuration_address[host], DataForReg);
- GT_REG_READ (pci_configuration_data[host], &data);
- return data;
-}
-
-
-/********************************************************************
-* pciGetRegOffset - Gets the register offset for this region config.
-*
-* INPUT: Bus, Region - The bus and region we ask for its base address.
-* OUTPUT: N/A
-* RETURNS: PCI register base address
-*********************************************************************/
-static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
-{
- switch (host) {
- case PCI_HOST0:
- switch (region) {
- case PCI_IO:
- return PCI_0I_O_LOW_DECODE_ADDRESS;
- case PCI_REGION0:
- return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
- case PCI_REGION1:
- return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
- case PCI_REGION2:
- return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
- case PCI_REGION3:
- return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
- }
- case PCI_HOST1:
- switch (region) {
- case PCI_IO:
- return PCI_1I_O_LOW_DECODE_ADDRESS;
- case PCI_REGION0:
- return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
- case PCI_REGION1:
- return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
- case PCI_REGION2:
- return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
- case PCI_REGION3:
- return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
- }
- }
- return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
-}
-
-static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
-{
- switch (host) {
- case PCI_HOST0:
- switch (region) {
- case PCI_IO:
- return PCI_0I_O_ADDRESS_REMAP;
- case PCI_REGION0:
- return PCI_0MEMORY0_ADDRESS_REMAP;
- case PCI_REGION1:
- return PCI_0MEMORY1_ADDRESS_REMAP;
- case PCI_REGION2:
- return PCI_0MEMORY2_ADDRESS_REMAP;
- case PCI_REGION3:
- return PCI_0MEMORY3_ADDRESS_REMAP;
- }
- case PCI_HOST1:
- switch (region) {
- case PCI_IO:
- return PCI_1I_O_ADDRESS_REMAP;
- case PCI_REGION0:
- return PCI_1MEMORY0_ADDRESS_REMAP;
- case PCI_REGION1:
- return PCI_1MEMORY1_ADDRESS_REMAP;
- case PCI_REGION2:
- return PCI_1MEMORY2_ADDRESS_REMAP;
- case PCI_REGION3:
- return PCI_1MEMORY3_ADDRESS_REMAP;
- }
- }
- return PCI_0MEMORY0_ADDRESS_REMAP;
-}
-
-/********************************************************************
-* pciGetBaseAddress - Gets the base address of a PCI.
-* - If the PCI size is 0 then this base address has no meaning!!!
-*
-*
-* INPUT: Bus, Region - The bus and region we ask for its base address.
-* OUTPUT: N/A
-* RETURNS: PCI base address.
-*********************************************************************/
-unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
-{
- unsigned int regBase;
- unsigned int regEnd;
- unsigned int regOffset = pciGetRegOffset (host, region);
-
- GT_REG_READ (regOffset, ®Base);
- GT_REG_READ (regOffset + 8, ®End);
-
- if (regEnd <= regBase)
- return 0xffffffff; /* ERROR !!! */
-
- regBase = regBase << 16;
- return regBase;
-}
-
-bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
- unsigned int bankBase, unsigned int bankLength)
-{
- unsigned int low = 0xfff;
- unsigned int high = 0x0;
- unsigned int regOffset = pciGetRegOffset (host, region);
- unsigned int remapOffset = pciGetRemapOffset (host, region);
-
- if (bankLength != 0) {
- low = (bankBase >> 16) & 0xffff;
- high = ((bankBase + bankLength) >> 16) - 1;
- }
-
- GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */
- GT_REG_WRITE (regOffset + 8, high);
-
- if (bankLength != 0) { /* must do AFTER writing maps */
- GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only.
- dont support upper 32
- in this driver */
- }
- return true;
-}
-
-unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
-{
- unsigned int low;
- unsigned int regOffset = pciGetRegOffset (host, region);
-
- GT_REG_READ (regOffset, &low);
- return (low & 0xffff) << 16;
-}
-
-unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
-{
- unsigned int low, high;
- unsigned int regOffset = pciGetRegOffset (host, region);
-
- GT_REG_READ (regOffset, &low);
- GT_REG_READ (regOffset + 8, &high);
- return ((high & 0xffff) + 1) << 16;
-}
-
-
-/* ronen - 7/Dec/03*/
-/********************************************************************
-* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
-* Inputs: one of the PCI BAR
-*********************************************************************/
-void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
-{
- RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
-}
-
-void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
-{
- SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
-}
-
-/********************************************************************
-* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
-*
-* Inputs: base and size of PCI SCS
-*********************************************************************/
-void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
- unsigned int pciDramBase, unsigned int pciDramSize)
-{
- /*ronen different function for 3rd bank. */
- unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
-
- pciDramBase = pciDramBase & 0xfffff000;
- pciDramBase = pciDramBase | (pciReadConfigReg (host,
- PCI_SCS_0_BASE_ADDRESS
- + offset,
- SELF) & 0x00000fff);
- pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
- pciDramBase);
- if (pciDramSize == 0)
- pciDramSize++;
- GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
- gtPciEnableInternalBAR (host, bank);
-}
-
-/********************************************************************
-* pciSetRegionFeatures - This function modifys one of the 8 regions with
-* feature bits given as an input.
-* - Be advised to check the spec before modifying them.
-* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
-* unsigned int features - See file: pci.h there are defintion for those
-* region features.
-* unsigned int baseAddress - The region base Address.
-* unsigned int topAddress - The region top Address.
-* Returns: false if one of the parameters is erroneous true otherwise.
-*********************************************************************/
-bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
- unsigned int features, unsigned int baseAddress,
- unsigned int regionLength)
-{
- unsigned int accessLow;
- unsigned int accessHigh;
- unsigned int accessTop = baseAddress + regionLength;
-
- if (regionLength == 0) { /* close the region. */
- pciDisableAccessRegion (host, region);
- return true;
- }
- /* base Address is store is bits [11:0] */
- accessLow = (baseAddress & 0xfff00000) >> 20;
- /* All the features are update according to the defines in pci.h (to be on
- the safe side we disable bits: [11:0] */
- accessLow = accessLow | (features & 0xfffff000);
- /* write to the Low Access Region register */
- GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
- accessLow);
-
- accessHigh = (accessTop & 0xfff00000) >> 20;
-
- /* write to the High Access Region register */
- GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
- accessHigh - 1);
- return true;
-}
-
-/********************************************************************
-* pciDisableAccessRegion - Disable The given Region by writing MAX size
-* to its low Address and MIN size to its high Address.
-*
-* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled.
-* Returns: N/A.
-*********************************************************************/
-void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
-{
- /* writing back the registers default values. */
- GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
- 0x01001fff);
- GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
-}
-
-/********************************************************************
-* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
-*
-* Inputs: N/A
-* Returns: true.
-*********************************************************************/
-bool pciArbiterEnable (PCI_HOST host)
-{
- unsigned int regData;
-
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
- return true;
-}
-
-/********************************************************************
-* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
-*
-* Inputs: N/A
-* Returns: true
-*********************************************************************/
-bool pciArbiterDisable (PCI_HOST host)
-{
- unsigned int regData;
-
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
- return true;
-}
-
-/********************************************************************
-* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
-*
-* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent.
-* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
-* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
-* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
-* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
-* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
-* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
-* Returns: true
-*********************************************************************/
-bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
- PCI_AGENT_PRIO externalAgent0,
- PCI_AGENT_PRIO externalAgent1,
- PCI_AGENT_PRIO externalAgent2,
- PCI_AGENT_PRIO externalAgent3,
- PCI_AGENT_PRIO externalAgent4,
- PCI_AGENT_PRIO externalAgent5)
-{
- unsigned int regData;
- unsigned int writeData;
-
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- writeData = (internalAgent << 7) + (externalAgent0 << 8) +
- (externalAgent1 << 9) + (externalAgent2 << 10) +
- (externalAgent3 << 11) + (externalAgent4 << 12) +
- (externalAgent5 << 13);
- regData = (regData & 0xffffc07f) | writeData;
- GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
- return true;
-}
-
-/********************************************************************
-* pciParkingDisable - Park on last option disable, with this function you can
-* disable the park on last mechanism for each agent.
-* disabling this option for all agents results parking
-* on the internal master.
-*
-* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent.
-* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
-* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
-* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
-* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
-* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
-* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
-* Returns: true
-*********************************************************************/
-bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
- PCI_AGENT_PARK externalAgent0,
- PCI_AGENT_PARK externalAgent1,
- PCI_AGENT_PARK externalAgent2,
- PCI_AGENT_PARK externalAgent3,
- PCI_AGENT_PARK externalAgent4,
- PCI_AGENT_PARK externalAgent5)
-{
- unsigned int regData;
- unsigned int writeData;
-
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- writeData = (internalAgent << 14) + (externalAgent0 << 15) +
- (externalAgent1 << 16) + (externalAgent2 << 17) +
- (externalAgent3 << 18) + (externalAgent4 << 19) +
- (externalAgent5 << 20);
- regData = (regData & ~(0x7f << 14)) | writeData;
- GT_REG_WRITE (pci_arbiter_control[host], regData);
- return true;
-}
-
-/********************************************************************
-* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
-* respond to grant assertion within a window specified in
-* the input value: 'brokenValue'.
-*
-* Inputs: unsigned char brokenValue - A value which limits the Master to hold the
-* grant without asserting frame.
-* Returns: Error for illegal broken value otherwise true.
-*********************************************************************/
-bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
-{
- unsigned int data;
- unsigned int regData;
-
- if (brokenValue > 0xf)
- return false; /* brokenValue must be 4 bit */
- data = brokenValue << 3;
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- regData = (regData & 0xffffff87) | data;
- GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
- return true;
-}
-
-/********************************************************************
-* pciDisableBrokenAgentDetection - This function disable the Broken agent
-* Detection mechanism.
-* NOTE: This operation may cause a dead lock on the
-* pci0 arbitration.
-*
-* Inputs: N/A
-* Returns: true.
-*********************************************************************/
-bool pciDisableBrokenAgentDetection (PCI_HOST host)
-{
- unsigned int regData;
-
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- regData = regData & 0xfffffffd;
- GT_REG_WRITE (pci_arbiter_control[host], regData);
- return true;
-}
-
-/********************************************************************
-* pciP2PConfig - This function set the PCI_n P2P configurate.
-* For more information on the P2P read PCI spec.
-*
-* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
-* Boundry.
-* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
-* Boundry.
-* unsigned int busNum - The CPI bus number to which the PCI interface
-* is connected.
-* unsigned int devNum - The PCI interface's device number.
-*
-* Returns: true.
-*********************************************************************/
-bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
- unsigned int SecondBusHigh,
- unsigned int busNum, unsigned int devNum)
-{
- unsigned int regData;
-
- regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
- ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
- GT_REG_WRITE (pci_p2p_configuration[host], regData);
- return true;
-}
-
-/********************************************************************
-* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
-* supports Cache Coherency in the PCI_n interface.
-* Inputs: region - One of the four regions.
-* snoopType - There is four optional Types:
-* 1. No Snoop.
-* 2. Snoop to WT region.
-* 3. Snoop to WB region.
-* 4. Snoop & Invalidate to WB region.
-* baseAddress - Base Address of this region.
-* regionLength - Region length.
-* Returns: false if one of the parameters is wrong otherwise return true.
-*********************************************************************/
-bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
- PCI_SNOOP_TYPE snoopType,
- unsigned int baseAddress,
- unsigned int regionLength)
-{
- unsigned int snoopXbaseAddress;
- unsigned int snoopXtopAddress;
- unsigned int data;
- unsigned int snoopHigh = baseAddress + regionLength;
-
- if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
- return false;
- snoopXbaseAddress =
- pci_snoop_control_base_0_low[host] + 0x10 * region;
- snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
- if (regionLength == 0) { /* closing the region */
- GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
- GT_REG_WRITE (snoopXtopAddress, 0);
- return true;
- }
- baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
- data = (baseAddress >> 20) | snoopType << 12;
- GT_REG_WRITE (snoopXbaseAddress, data);
- snoopHigh = (snoopHigh & 0xfff00000) >> 20;
- GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
- return true;
-}
-
-static int gt_read_config_dword (struct pci_controller *hose,
- pci_dev_t dev, int offset, u32 * value)
-{
- int bus = PCI_BUS (dev);
-
- if ((bus == local_buses[0]) || (bus == local_buses[1])) {
- *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
- PCI_DEV (dev));
- } else {
- *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
- cfg_addr, offset,
- PCI_DEV (dev), bus);
- }
-
- return 0;
-}
-
-static int gt_write_config_dword (struct pci_controller *hose,
- pci_dev_t dev, int offset, u32 value)
-{
- int bus = PCI_BUS (dev);
-
- if ((bus == local_buses[0]) || (bus == local_buses[1])) {
- pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
- PCI_DEV (dev), value);
- } else {
- pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
- offset, PCI_DEV (dev), bus,
- value);
- }
- return 0;
-}
-
-
-static void gt_setup_ide (struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *entry)
-{
- static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
- u32 bar_response, bar_value;
- int bar;
-
- for (bar = 0; bar < 6; bar++) {
- /*ronen different function for 3rd bank. */
- unsigned int offset =
- (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
-
- pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
- 0x0);
- pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
- &bar_response);
-
- pciauto_region_allocate (bar_response &
- PCI_BASE_ADDRESS_SPACE_IO ? hose->
- pci_io : hose->pci_mem, ide_bar[bar],
- &bar_value);
-
- pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4,
- bar_value);
- }
-}
-
-#ifdef CONFIG_USE_CPCIDVI
-static void gt_setup_cpcidvi (struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *entry)
-{
- u32 bar_value, pci_response;
-
- pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response);
- pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
- pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response);
- pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value);
- pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00));
- pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0);
- pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value);
- pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01);
- gt_cpcidvi_rom.base = bar_value & 0xffffff00;
- gt_cpcidvi_rom.init = 1;
-}
-
-unsigned char gt_cpcidvi_in8(unsigned int offset)
-{
- unsigned char data;
-
- if (gt_cpcidvi_rom.init == 0) {
- return(0);
- }
- data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base);
- return(data);
-}
-
-void gt_cpcidvi_out8(unsigned int offset, unsigned char data)
-{
- unsigned int off;
-
- if (gt_cpcidvi_rom.init == 0) {
- return;
- }
- off = data;
- off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base;
- in8(off);
- return;
-}
-#endif
-
-/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */
-/* and is curently not called *. */
-#if 0
-static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
-{
- unsigned char pin, irq;
-
- pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
-
- if (pin == 1) { /* only allow INT A */
- irq = pci_irq_swizzle[(PCI_HOST) hose->
- cfg_addr][PCI_DEV (dev)];
- if (irq)
- pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
- }
-}
-#endif
-
-struct pci_config_table gt_config_table[] = {
-#ifdef CONFIG_USE_CPCIDVI
- {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi},
-#endif
- {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
- {}
-};
-
-struct pci_controller pci0_hose = {
-/* fixup_irq: gt_fixup_irq, */
- config_table:gt_config_table,
-};
-
-struct pci_controller pci1_hose = {
-/* fixup_irq: gt_fixup_irq, */
- config_table:gt_config_table,
-};
-
-void pci_init_board (void)
-{
- unsigned int command;
-#ifdef CONFIG_PCI_PNP
- unsigned int bar;
-#endif
-#ifdef DEBUG
- gt_pci_bus_mode_display (PCI_HOST0);
-#endif
-#ifdef CONFIG_USE_CPCIDVI
- gt_cpcidvi_rom.init = 0;
- gt_cpcidvi_rom.base = 0;
-#endif
-
- pci0_hose.config_table = gt_config_table;
- pci1_hose.config_table = gt_config_table;
-
-#ifdef CONFIG_USE_CPCIDVI
- gt_config_table[0].config_device = gt_setup_cpcidvi;
-#endif
- gt_config_table[1].config_device = gt_setup_ide;
-
- pci0_hose.first_busno = 0;
- pci0_hose.last_busno = 0xff;
- local_buses[0] = pci0_hose.first_busno;
-
- /* PCI memory space */
- pci_set_region (pci0_hose.regions + 0,
- CONFIG_SYS_PCI0_0_MEM_SPACE,
- CONFIG_SYS_PCI0_0_MEM_SPACE,
- CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region (pci0_hose.regions + 1,
- CONFIG_SYS_PCI0_IO_SPACE_PCI,
- CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
-
- pci_set_ops (&pci0_hose,
- pci_hose_read_config_byte_via_dword,
- pci_hose_read_config_word_via_dword,
- gt_read_config_dword,
- pci_hose_write_config_byte_via_dword,
- pci_hose_write_config_word_via_dword,
- gt_write_config_dword);
- pci0_hose.region_count = 2;
-
- pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
-
- pci_register_hose (&pci0_hose);
- pciArbiterDisable(PCI_HOST0); /* on PMC modules no arbiter is used */
- pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
- command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MASTER;
- pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
- command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MEMORY;
- pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
-
-#ifdef CONFIG_PCI_PNP
- pciauto_config_init(&pci0_hose);
- pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar);
-#endif
-#ifdef CONFIG_PCI_SCAN_SHOW
- printf("PCI: Bus Dev VenId DevId Class Int\n");
-#endif
- pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose, pci0_hose.first_busno);
-
-#ifdef DEBUG
- gt_pci_bus_mode_display (PCI_HOST1);
-#endif
- pci1_hose.first_busno = pci0_hose.last_busno + 1;
- pci1_hose.last_busno = 0xff;
- pci1_hose.current_busno = pci1_hose.first_busno;
- local_buses[1] = pci1_hose.first_busno;
-
- /* PCI memory space */
- pci_set_region (pci1_hose.regions + 0,
- CONFIG_SYS_PCI1_0_MEM_SPACE,
- CONFIG_SYS_PCI1_0_MEM_SPACE,
- CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region (pci1_hose.regions + 1,
- CONFIG_SYS_PCI1_IO_SPACE_PCI,
- CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
-
- pci_set_ops (&pci1_hose,
- pci_hose_read_config_byte_via_dword,
- pci_hose_read_config_word_via_dword,
- gt_read_config_dword,
- pci_hose_write_config_byte_via_dword,
- pci_hose_write_config_word_via_dword,
- gt_write_config_dword);
-
- pci1_hose.region_count = 2;
-
- pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
-
- pci_register_hose (&pci1_hose);
-
- pciArbiterEnable (PCI_HOST1);
- pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
-
- command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MASTER;
- pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
-
-#ifdef CONFIG_PCI_PNP
- pciauto_config_init(&pci1_hose);
- pciauto_region_allocate(pci1_hose.pci_io, 0x400, &bar);
-#endif
- pci1_hose.last_busno = pci_hose_scan_bus (&pci1_hose, pci1_hose.first_busno);
-
- command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MEMORY;
- pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
-
-}
-#endif /* of CONFIG_PCI */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*************************************************************************
- * adaption for the Marvell DB64460 Board
- * Ingo Assmus (ingo.assmus@keymile.com)
- *************************************************************************/
-
-/* sdram_init.c - automatic memory sizing */
-
-#include <common.h>
-#include <74xx_7xx.h>
-#include "../../Marvell/include/memory.h"
-#include "../../Marvell/include/pci.h"
-#include "../../Marvell/include/mv_gen_reg.h"
-#include <net.h>
-
-#include "eth.h"
-#include "mpsc.h"
-#include "../../Marvell/common/i2c.h"
-#include "64460.h"
-#include "mv_regs.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#undef DEBUG
-#define MAP_PCI
-
-#ifdef DEBUG
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-int set_dfcdlInit (void); /* setup delay line of Mv64460 */
-int mvDmaIsChannelActive (int);
-int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong);
-int mvDmaTransfer (int, ulong, ulong, ulong, ulong);
-
-#define D_CACHE_FLUSH_LINE(addr, offset) \
- { \
- __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
- }
-
-int memory_map_bank (unsigned int bankNo,
- unsigned int bankBase, unsigned int bankLength)
-{
-#if defined (MAP_PCI) && defined (CONFIG_PCI)
- PCI_HOST host;
-#endif
-
-#ifdef DEBUG
- if (bankLength > 0) {
- printf ("mapping bank %d at %08x - %08x\n",
- bankNo, bankBase, bankBase + bankLength - 1);
- } else {
- printf ("unmapping bank %d\n", bankNo);
- }
-#endif
-
- memoryMapBank (bankNo, bankBase, bankLength);
-
-#if defined (MAP_PCI) && defined (CONFIG_PCI)
- for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
- const int features =
- PREFETCH_ENABLE |
- DELAYED_READ_ENABLE |
- AGGRESSIVE_PREFETCH |
- READ_LINE_AGGRESSIVE_PREFETCH |
- READ_MULTI_AGGRESSIVE_PREFETCH |
- MAX_BURST_4 | PCI_NO_SWAP;
-
- pciMapMemoryBank (host, bankNo, bankBase, bankLength);
-
- pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
- bankLength);
-
- pciSetRegionFeatures (host, bankNo, features, bankBase,
- bankLength);
- }
-#endif
-
- return 0;
-}
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-long int dram_size (long int *base, long int maxsize)
-{
- volatile long int *addr, *b = base;
- long int cnt, val, save1, save2;
-
-#define STARTVAL (1<<20) /* start test at 1M */
- for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
- cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save1 = *addr; /* save contents of addr */
- save2 = *b; /* save contents of base */
-
- *addr = cnt; /* write cnt to addr */
- *b = 0; /* put null at base */
-
- /* check at base address */
- if ((*b) != 0) {
- *addr = save1; /* restore *addr */
- *b = save2; /* restore *b */
- return (0);
- }
- val = *addr; /* read *addr */
- val = *addr; /* read *addr */
-
- *addr = save1;
- *b = save2;
-
- if (val != cnt) {
- DP (printf
- ("Found %08x at Address %08x (failure)\n",
- (unsigned int) val, (unsigned int) addr));
- /* fix boundary condition.. STARTVAL means zero */
- if (cnt == STARTVAL / sizeof (long))
- cnt = 0;
- return (cnt * sizeof (long));
- }
- }
-
- return maxsize;
-}
-
-#define SDRAM_NORMAL 0x0
-#define SDRAM_PRECHARGE_ALL 0x1
-#define SDRAM_REFRESH_ALL 0x2
-#define SDRAM_MODE_REG_SETUP 0x3
-#define SDRAM_XTEN_MODE_REG_SETUP 0x4
-#define SDRAM_NOP 0x5
-#define SDRAM_SELF_REFRESH 0x7
-
-phys_size_t initdram (int board_type)
-{
- int tmp;
- int start;
- ulong size;
- ulong memSpaceAttr;
- ulong dest;
-
- /* first disable all banks */
- memory_map_bank(0, 0, 0);
- memory_map_bank(1, 0, 0);
- memory_map_bank(2, 0, 0);
- memory_map_bank(3, 0, 0);
-
- /* calibrate delay lines */
- set_dfcdlInit();
-
- GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_NOP); /* 0x1418 */
- do {
- tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
- } while(tmp != 0x0);
-
- /* SDRAM controller configuration */
-#ifdef CONFIG_MV64460_ECC
- GT_REG_WRITE(MV64460_SDRAM_CONFIG, 0x58201400); /* 0x1400 */
-#else
- GT_REG_WRITE(MV64460_SDRAM_CONFIG, 0x58200400); /* 0x1400 */
-#endif
- GT_REG_WRITE(MV64460_D_UNIT_CONTROL_LOW, 0xC3000540); /* 0x1404 */
- GT_REG_WRITE(MV64460_D_UNIT_CONTROL_HIGH, 0x0300F777); /* 0x1424 */
- GT_REG_WRITE(MV64460_SDRAM_TIMING_CONTROL_LOW, 0x01712220); /* 0x1408 */
- GT_REG_WRITE(MV64460_SDRAM_TIMING_CONTROL_HIGH, 0x0000005D); /* 0x140C */
- GT_REG_WRITE(MV64460_SDRAM_ADDR_CONTROL, 0x00000012); /* 0x1410 */
- GT_REG_WRITE(MV64460_SDRAM_OPEN_PAGES_CONTROL, 0x00000001); /* 0x1414 */
-
- /* SDRAM drive strength */
- GT_REG_WRITE(MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x80000000); /* 0x14C0 */
- GT_REG_WRITE(MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x80000008); /* 0x14C0 */
- GT_REG_WRITE(MV64460_SDRAM_DATA_PADS_CALIBRATION, 0x80000000); /* 0x14C4 */
- GT_REG_WRITE(MV64460_SDRAM_DATA_PADS_CALIBRATION, 0x80000008); /* 0x14C4 */
-
- /* setup SDRAM device registers */
-
- /* precharge all */
- GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_PRECHARGE_ALL); /* 0x1418 */
- do {
- tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
- } while(tmp != 0x0);
-
- /* enable DLL */
- GT_REG_WRITE(MV64460_EXTENDED_DRAM_MODE, 0x00000000); /* 0x1420 */
- GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_XTEN_MODE_REG_SETUP); /* 0x1418 */
- do {
- tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
- } while(tmp != 0x0);
-
- /* reset DLL */
- GT_REG_WRITE(MV64460_SDRAM_MODE, 0x00000132); /* 0x141C */
- GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_MODE_REG_SETUP); /* 0x1418 */
- do {
- tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
- } while(tmp != 0x0);
-
- /* precharge all */
- GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_PRECHARGE_ALL); /* 0x1418 */
- do {
- tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
- } while(tmp != 0x0);
-
- /* wait for 2 auto refresh commands */
- udelay(20);
-
- /* un-reset DLL */
- GT_REG_WRITE(MV64460_SDRAM_MODE, 0x00000032); /* 0x141C */
- GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_MODE_REG_SETUP); /* 0x1418 */
- do {
- tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
- } while(tmp != 0x0);
-
- /* wait 200 cycles */
- udelay(2); /* FIXME make this dynamic for the system clock */
-
- /* SDRAM init done */
- memory_map_bank(0, CONFIG_SYS_SDRAM_BASE, (256 << 20));
-#ifdef CONFIG_SYS_SDRAM1_BASE
- memory_map_bank(1, CONFIG_SYS_SDRAM1_BASE, (256 << 20));
-#endif
-
- /* DUNIT_MMASK: enable SnoopHitEn bit to avoid errata CPU-#4
- */
- tmp = GTREGREAD(MV64460_D_UNIT_MMASK); /* 0x14B0 */
- GT_REG_WRITE(MV64460_D_UNIT_MMASK, tmp | 0x2);
-
- start = (0 << 20);
-#ifdef CONFIG_P3M750
- size = (512 << 20);
-#elif defined (CONFIG_P3M7448)
- size = (128 << 20);
-#endif
-
-#ifdef CONFIG_MV64460_ECC
- memSpaceAttr = ((~(BIT0 << 0)) & 0xf) << 8;
- mvDmaSetMemorySpace (0, 0, memSpaceAttr, start, size);
- for (dest = start; dest < start + size; dest += _8M) {
- mvDmaTransfer (0, start, dest, _8M,
- BIT8 /*DMA_DTL_128BYTES */ |
- BIT3 /*DMA_HOLD_SOURCE_ADDR */ |
- BIT11 /*DMA_BLOCK_TRANSFER_MODE */ );
- while (mvDmaIsChannelActive (0));
- }
-#endif
-
- return (size);
-}
-
-void board_add_ram_info(int use_default)
-{
- u32 val;
-
- puts(" (CL=");
- switch ((GTREGREAD(MV64460_SDRAM_MODE) >> 4) & 0x7) {
- case 0x2:
- puts("2");
- break;
- case 0x3:
- puts("3");
- break;
- case 0x5:
- puts("1.5");
- break;
- case 0x6:
- puts("2.5");
- break;
- }
-
- val = GTREGREAD(MV64460_SDRAM_CONFIG);
-
- puts(", ECC ");
- if (val & 0x00001000)
- puts("enabled)");
- else
- puts("not enabled)");
-}
-
-/*
- * mvDmaIsChannelActive - Check if IDMA channel is active
- *
- * channel = IDMA channel number from 0 to 7
- */
-int mvDmaIsChannelActive (int channel)
-{
- ulong data;
-
- data = GTREGREAD (MV64460_DMA_CHANNEL0_CONTROL + 4 * channel);
- if (data & BIT14) /* activity status */
- return 1;
-
- return 0;
-}
-
-/*
- * mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding
- * map.
- *
- * memSpace = IDMA memory window number from 0 to 7
- * trg_if = Target interface:
- * 0x0 DRAM
- * 0x1 Device Bus
- * 0x2 Integrated SDRAM (or CPU bus 60x only)
- * 0x3 PCI0
- * 0x4 PCI1
- * attr = IDMA attributes (see MV datasheet)
- * base_addr = Sets up memory window for transfers
- *
- */
-int mvDmaSetMemorySpace (ulong memSpace,
- ulong trg_if,
- ulong attr, ulong base_addr, ulong size)
-{
- ulong temp;
-
- /* The base address must be aligned to the size. */
- if (base_addr % size != 0)
- return 0;
-
- if (size >= 0x10000) { /* 64K */
- size &= 0xffff0000;
- base_addr = (base_addr & 0xffff0000);
- /* Set the new attributes */
- GT_REG_WRITE (MV64460_DMA_BASE_ADDR_REG0 + memSpace * 8,
- (base_addr | trg_if | attr));
- GT_REG_WRITE ((MV64460_DMA_SIZE_REG0 + memSpace * 8),
- (size - 1) & 0xffff0000);
- temp = GTREGREAD (MV64460_DMA_BASE_ADDR_ENABLE_REG);
- GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG,
- (temp & ~(BIT0 << memSpace)));
- return 1;
- }
-
- return 0;
-}
-
-/*
- * mvDmaTransfer - Transfer data from src_addr to dst_addr on one of the 4
- * DMA channels.
- *
- * channel = IDMA channel number from 0 to 3
- * destAddr = Destination address
- * sourceAddr = Source address
- * size = Size in bytes
- * command = See MV datasheet
- *
- */
-int mvDmaTransfer (int channel, ulong sourceAddr,
- ulong destAddr, ulong size, ulong command)
-{
- ulong engOffReg = 0; /* Engine Offset Register */
-
- if (size > 0xffff)
- command = command | BIT31; /* DMA_16M_DESCRIPTOR_MODE */
- command = command | ((command >> 6) & 0x7);
- engOffReg = channel * 4;
- GT_REG_WRITE (MV64460_DMA_CHANNEL0_BYTE_COUNT + engOffReg, size);
- GT_REG_WRITE (MV64460_DMA_CHANNEL0_SOURCE_ADDR + engOffReg, sourceAddr);
- GT_REG_WRITE (MV64460_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg, destAddr);
- command = command |
- BIT12 | /* DMA_CHANNEL_ENABLE */
- BIT9; /* DMA_NON_CHAIN_MODE */
- /* Activate DMA channel By writting to mvDmaControlRegister */
- GT_REG_WRITE (MV64460_DMA_CHANNEL0_CONTROL + engOffReg, command);
- return 1;
-}
-
-/****************************************************************************************
- * SDRAM INIT *
- * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb *
- * This procedure fits only the Atlantis *
- * *
- ***************************************************************************************/
-
-/****************************************************************************************
- * DFCDL initialize MV643xx Design Considerations *
- * *
- ***************************************************************************************/
-int set_dfcdlInit (void)
-{
- int i;
-
- /* Values from MV64460 User Manual */
- unsigned int dfcdl_tbl[] = { 0x00000000, 0x00000001, 0x00000042, 0x00000083,
- 0x000000c4, 0x00000105, 0x00000146, 0x00000187,
- 0x000001c8, 0x00000209, 0x0000024a, 0x0000028b,
- 0x000002cc, 0x0000030d, 0x0000034e, 0x0000038f,
- 0x000003d0, 0x00000411, 0x00000452, 0x00000493,
- 0x000004d4, 0x00000515, 0x00000556, 0x00000597,
- 0x000005d8, 0x00000619, 0x0000065a, 0x0000069b,
- 0x000006dc, 0x0000071d, 0x0000075e, 0x0000079f,
- 0x000007e0, 0x00000821, 0x00000862, 0x000008a3,
- 0x000008e4, 0x00000925, 0x00000966, 0x000009a7,
- 0x000009e8, 0x00000a29, 0x00000a6a, 0x00000aab,
- 0x00000aec, 0x00000b2d, 0x00000b6e, 0x00000baf,
- 0x00000bf0, 0x00000c31, 0x00000c72, 0x00000cb3,
- 0x00000cf4, 0x00000d35, 0x00000d76, 0x00000db7,
- 0x00000df8, 0x00000e39, 0x00000e7a, 0x00000ebb,
- 0x00000efc, 0x00000f3d, 0x00000f7e, 0x00000fbf };
-
- for (i = 0; i < 64; i++)
- GT_REG_WRITE (SRAM_DATA0, dfcdl_tbl[i]);
- GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000); /* enable dynamic delay line updating */
-
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * modified for marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * modified for cpci750 board by
- * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * serial.c - serial support for esd cpci750 board
- */
-
-/* supports the MPSC */
-
-#include <common.h>
-#include <command.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-#include "../../Marvell/include/memory.h"
-
-#include "mpsc.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int p3mx_serial_init(void)
-{
- mpsc_init (gd->baudrate);
-
- return (0);
-}
-
-static void p3mx_serial_putc(const char c)
-{
- if (c == '\n')
- mpsc_putchar ('\r');
-
- mpsc_putchar (c);
-}
-
-static int p3mx_serial_getc(void)
-{
- return mpsc_getchar ();
-}
-
-static int p3mx_serial_tstc(void)
-{
- return mpsc_test_char ();
-}
-
-static void p3mx_serial_setbrg(void)
-{
- galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
-}
-
-static struct serial_device p3mx_serial_drv = {
- .name = "p3mx_serial",
- .start = p3mx_serial_init,
- .stop = NULL,
- .setbrg = p3mx_serial_setbrg,
- .putc = p3mx_serial_putc,
- .puts = default_serial_puts,
- .getc = p3mx_serial_getc,
- .tstc = p3mx_serial_tstc,
-};
-
-void p3mx_serial_initialize(void)
-{
- serial_register(&p3mx_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &p3mx_serial_drv;
-}
-
-#if defined(CONFIG_CMD_KGDB)
-void kgdb_serial_init (void)
-{
-}
-
-void putDebugChar (int c)
-{
- serial_putc (c);
-}
-
-void putDebugStr (const char *str)
-{
- serial_puts (str);
-}
-
-int getDebugChar (void)
-{
- return serial_getc ();
-}
-
-void kgdb_interruptible (int yes)
-{
- return;
-}
-#endif
if TARGET_PXA255_IDP
-config SYS_CPU
- default "pxa"
-
config SYS_BOARD
default "pxa255_idp"
if TARGET_QEMU_MIPS
-config SYS_CPU
- default "mips32"
-
-config SYS_BOARD
- default "qemu-mips"
-
-config SYS_CONFIG_NAME
- default "qemu-mips"
-
-endif
-
-if TARGET_QEMU_MIPS64
-
-config SYS_CPU
- default "mips64"
-
config SYS_BOARD
default "qemu-mips"
config SYS_CONFIG_NAME
- default "qemu-mips64"
+ default "qemu-mips" if 32BIT
+ default "qemu-mips64" if 64BIT
endif
if TARGET_RPI_B
-config SYS_CPU
- default "arm1176"
-
config SYS_BOARD
default "rpi_b"
u32 end_tag;
};
+struct msg_get_mac_address {
+ struct bcm2835_mbox_hdr hdr;
+ struct bcm2835_mbox_tag_get_mac_address get_mac_address;
+ u32 end_tag;
+};
+
struct msg_set_power_state {
struct bcm2835_mbox_hdr hdr;
struct bcm2835_mbox_tag_set_power_state set_power_state;
return 0;
}
+int misc_init_r(void)
+{
+ ALLOC_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1, 16);
+ int ret;
+
+ if (getenv("usbethaddr"))
+ return 0;
+
+ BCM2835_MBOX_INIT_HDR(msg);
+ BCM2835_MBOX_INIT_TAG(&msg->get_mac_address, GET_MAC_ADDRESS);
+
+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+ if (ret) {
+ printf("bcm2835: Could not query MAC address\n");
+ /* Ignore error; not critical */
+ return 0;
+ }
+
+ eth_setenv_enetaddr("usbethaddr", msg->get_mac_address.body.resp.mac);
+
+ return 0;
+}
+
static int power_on_module(u32 module)
{
ALLOC_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1, 16);
#define MSTPSR7 0xE61501C4
#define SMSTPCR7 0xE615014C
-#define SCIF0_MSTP719 (1 << 19)
+#define SCIF2_MSTP719 (1 << 19)
#define MSTPSR8 0xE61509A0
#define SMSTPCR8 0xE6150990
/* TMU */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
- /* SCIF0 */
- mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP719);
+ /* SCIF2 */
+ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
/* ETHER */
mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
int dram_init(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
#include <asm/io.h>
#include <asm/arch/rmobile.h>
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
/* QoS version 0.11 */
enum {
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
}
+#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
int dram_init(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
#include <asm/arch/rmobile.h>
/* QoS version 0.240 for ES1 and version 0.334 for ES2 */
-
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
enum {
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
}
+#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
/* CPU frequency setting. Set to 1.4GHz */
if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
+ u32 stat = 0;
u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
<< PLL0_STC_BIT;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+
+ do {
+ stat = readl(PLLECR) & PLL0ST;
+ } while (stat == 0x0);
}
/* QoS(Quality-of-Service) Init */
int dram_init(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
#include <asm/arch/rmobile.h>
/* QoS version 0.955 for ES1 and version 0.963 for ES2 */
-
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
enum {
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
else
qos_init_es1();
}
+#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
if TARGET_PM9261
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "pm9261"
if TARGET_PM9263
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "pm9263"
if TARGET_PM9G45
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "pm9g45"
DECLARE_GLOBAL_DATA_PTR;
-int __exynos_early_init_f(void)
+__weak int exynos_early_init_f(void)
{
return 0;
}
-int exynos_early_init_f(void)
- __attribute__((weak, alias("__exynos_early_init_f")));
-int __exynos_power_init(void)
+__weak int exynos_power_init(void)
{
return 0;
}
-int exynos_power_init(void)
- __attribute__((weak, alias("__exynos_power_init")));
#if defined CONFIG_EXYNOS_TMU
/* Boot Time Thermal Analysis for SoC temperature threshold breach */
if TARGET_S5P_GONI
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "goni"
static void board_gpio_init(void)
{
/* eMMC Reset Pin */
+ gpio_request(EXYNOS4X12_GPIO_K12, "eMMC Reset");
+
gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1));
gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE);
gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X);
/* Enable FAN (Odroid U3) */
+ gpio_request(EXYNOS4X12_GPIO_D00, "FAN Control");
+
gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP);
gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X);
gpio_direction_output(EXYNOS4X12_GPIO_D00, 1);
/* OTG Vbus output (Odroid U3+) */
+ gpio_request(EXYNOS4X12_GPIO_L20, "OTG Vbus");
+
gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE);
gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X);
gpio_direction_output(EXYNOS4X12_GPIO_L20, 0);
/* OTG INT (Odroid U3+) */
+ gpio_request(EXYNOS4X12_GPIO_X31, "OTG INT");
+
gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP);
gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X);
gpio_direction_input(EXYNOS4X12_GPIO_X31);
int exynos_early_init_f(void)
{
board_clock_init();
- board_gpio_init();
return 0;
}
gd->ram_size -= SZ_1M;
gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= SZ_1M;
+ board_gpio_init();
+
return 0;
}
if TARGET_SMDK2410
-config SYS_CPU
- default "arm920t"
-
config SYS_BOARD
default "smdk2410"
if TARGET_SMDKC100
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "smdkc100"
int exynos_init(void)
{
+ char buf[16];
+
gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
switch (get_hwrev()) {
break;
}
+ /* Request soft I2C gpios */
+ sprintf(buf, "soft_i2c_scl");
+ gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, buf);
+
+ sprintf(buf, "soft_i2c_sda");
+ gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, buf);
+
check_hw_revision();
printf("HW Revision:\t0x%x\n", board_rev);
if TARGET_SANSA_FUZE_PLUS
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "sansa_fuze_plus"
if TARGET_SCB9328
-config SYS_CPU
- default "arm920t"
-
config SYS_BOARD
default "scb9328"
FLASH_BUS *addr = (FLASH_BUS *) 0;
+ /* cppcheck-suppress nullPointer */
*addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER);
+ /* cppcheck-suppress nullPointer */
return *addr;
}
if TARGET_SC_SPS_1
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "sc_sps_1"
if TARGET_CORVUS
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "corvus"
if TARGET_DRACO
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "draco"
if TARGET_DXR2
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "draco"
if TARGET_PXM2
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "pxm2"
#endif /* #ifdef CONFIG_FACTORYSET */
/* Set rgmii mode and enable rmii clock to be sourced from chip */
- writel(RGMII_MODE_ENABLE , &cdev->miisel);
+ writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
rv = cpsw_register(&cpsw_data);
if (rv < 0)
if TARGET_RUT
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "rut"
if TARGET_TAURUS
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "taurus"
if TARGET_PENGWYN
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "pengwyn"
if TARGET_HUMMINGBOARD
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "hummingboard"
if TARGET_SPEAR300
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "spear300"
if TARGET_SPEAR310
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "spear310"
if TARGET_SPEAR320
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "spear320"
if TARGET_SPEAR600
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "spear600"
if TARGET_X600
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "x600"
if TARGET_SNOWBALL
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "snowball"
if TARGET_U8500_HREF
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "u8500"
-if TARGET_SUN4I
+if ARCH_SUNXI
-config SYS_CONFIG_NAME
- default "sun4i"
+choice
+ prompt "Sunxi SoC Variant"
-endif
+config MACH_SUN4I
+ bool "sun4i (Allwinner A10)"
+ select CPU_V7
+ select SUPPORT_SPL
-if TARGET_SUN5I
+config MACH_SUN5I
+ bool "sun5i (Allwinner A13)"
+ select CPU_V7
+ select SUPPORT_SPL
-config SYS_CONFIG_NAME
- default "sun5i"
+config MACH_SUN6I
+ bool "sun6i (Allwinner A31)"
+ select CPU_V7
-endif
+config MACH_SUN7I
+ bool "sun7i (Allwinner A20)"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config MACH_SUN8I
+ bool "sun8i (Allwinner A23)"
+ select CPU_V7
-if TARGET_SUN7I
+endchoice
config SYS_CONFIG_NAME
- default "sun7i"
+ string
+ default "sun4i" if MACH_SUN4I
+ default "sun5i" if MACH_SUN5I
+ default "sun6i" if MACH_SUN6I
+ default "sun7i" if MACH_SUN7I
+ default "sun8i" if MACH_SUN8I
-endif
+choice
+ prompt "Board"
+
+config TARGET_A10_OLINUXINO_L
+ bool "A10_OLINUXINO_L"
+ depends on MACH_SUN4I
+
+config TARGET_A10S_OLINUXINO_M
+ bool "A10S_OLINUXINO_M"
+ depends on MACH_SUN5I
+
+config TARGET_A13_OLINUXINOM
+ bool "A13_OLINUXINOM"
+ depends on MACH_SUN5I
+
+config TARGET_A13_OLINUXINO
+ bool "A13_OLINUXINO"
+ depends on MACH_SUN5I
+
+config TARGET_A20_OLINUXINO_L2
+ bool "A20_OLINUXINO_L2"
+ depends on MACH_SUN7I
+
+config TARGET_A20_OLINUXINO_L
+ bool "A20_OLINUXINO_L"
+ depends on MACH_SUN7I
+
+config TARGET_A20_OLINUXINO_M
+ bool "A20_OLINUXINO_M"
+ depends on MACH_SUN7I
+
+config TARGET_AUXTEK_T004
+ bool "AUXTEK_T004"
+ depends on MACH_SUN5I
+
+config TARGET_BANANAPI
+ bool "BANANAPI"
+ depends on MACH_SUN7I
+
+config TARGET_COLOMBUS
+ bool "COLOMBUS"
+ depends on MACH_SUN6I
+
+config TARGET_CUBIEBOARD2
+ bool "CUBIEBOARD2"
+ depends on MACH_SUN7I
+
+config TARGET_CUBIEBOARD
+ bool "CUBIEBOARD"
+ depends on MACH_SUN4I
-if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN7I
+config TARGET_CUBIETRUCK
+ bool "CUBIETRUCK"
+ depends on MACH_SUN7I
-config SYS_CPU
- default "armv7"
+config TARGET_IPPO_Q8H_V5
+ bool "IPPO_Q8H_V5"
+ depends on MACH_SUN8I
+
+config TARGET_PCDUINO3
+ bool "PCDUINO3"
+ depends on MACH_SUN7I
+
+config TARGET_MELE_A1000G
+ bool "MELE_A1000G"
+ depends on MACH_SUN4I
+
+config TARGET_MELE_A1000
+ bool "MELE_A1000"
+ depends on MACH_SUN4I
+
+config TARGET_MELE_M3
+ bool "MELE_M3"
+ depends on MACH_SUN7I
+
+config TARGET_MINI_X_1GB
+ bool "MINI_X_1GB"
+ depends on MACH_SUN4I
+
+config TARGET_MINI_X
+ bool "MINI_X"
+ depends on MACH_SUN4I
+
+config TARGET_BA10_TV_BOX
+ bool "BA10_TV_BOX"
+ depends on MACH_SUN4I
+
+config TARGET_I12_TVBOX
+ bool "I12_TVBOX"
+ depends on MACH_SUN7I
+
+config TARGET_QT840A
+ bool "QT840A"
+ depends on MACH_SUN7I
+
+config TARGET_R7DONGLE
+ bool "R7DONGLE"
+ depends on MACH_SUN5I
+
+endchoice
config SYS_BOARD
default "sunxi"
config SYS_SOC
default "sunxi"
+config SPL_FEL
+ bool "SPL/FEL mode support"
+ depends on SPL
+ default n
+
config FDTFILE
string "Default fdtfile env setting for this board"
+config OLD_SUNXI_KERNEL_COMPAT
+ boolean "Enable workarounds for booting old kernels"
+ default n
+ ---help---
+ Set this to enable various workarounds for old kernels, this results in
+ sub-optimal settings for newer kernels, only enable if needed.
+
+config MMC0_CD_PIN
+ string "Card detect pin for mmc0"
+ default ""
+ ---help---
+ Set the card detect pin for mmc0, leave empty to not use cd. This
+ takes a string in the format understood by sunxi_name_to_gpio, e.g.
+ PH1 for pin 1 of port H.
+
+config MMC1_CD_PIN
+ string "Card detect pin for mmc1"
+ default ""
+ ---help---
+ See MMC0_CD_PIN help text.
+
+config MMC2_CD_PIN
+ string "Card detect pin for mmc2"
+ default ""
+ ---help---
+ See MMC0_CD_PIN help text.
+
+config MMC3_CD_PIN
+ string "Card detect pin for mmc3"
+ default ""
+ ---help---
+ See MMC0_CD_PIN help text.
+
+config MMC_SUNXI_SLOT_EXTRA
+ int "mmc extra slot number"
+ default -1
+ ---help---
+ sunxi builds always enable mmc0, some boards also have a second sdcard
+ slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
+ support for this.
+
endif
F: configs/Cubieboard_defconfig
F: configs/Mele_A1000_defconfig
F: configs/Mele_A1000G_defconfig
+F: configs/Mele_M3_defconfig
F: configs/Mini-X_defconfig
F: configs/Mini-X-1Gb_defconfig
F: include/configs/sun5i.h
F: configs/Bananapi_defconfig
F: configs/i12-tvbox_defconfig
F: configs/Linksprite_pcDuino3_defconfig
+F: configs/Linksprite_pcDuino3_fdt_defconfig
F: configs/qt840a_defconfig
CUBIEBOARD2 BOARD
S: Maintained
F: board/sunxi/dram_a20_olinuxino_l.c
F: configs/A20-OLinuXino-Lime_defconfig
+
+A20-OLINUXINO-LIME2 BOARD
+M: Iain Paton <ipaton0@gmail.com>
+S: Maintained
+F: board/sunxi/dram_a20_olinuxino_l2.c
+F: configs/A20-OLinuXino-Lime2_defconfig
+
+COLOMBUS BOARD
+M: Maxime Ripard <maxime.ripard@free-electrons.com>
+S: Maintained
+F: configs/Colombus_defconfig
+
+IPPO-Q8H-V5 BOARD
+M: Chen-Yu Tsai <wens@csie.org>
+S: Maintained
+F: configs/Ippo_q8h_v5_defconfig
obj-y += board.o
obj-$(CONFIG_SUNXI_GMAC) += gmac.o
obj-$(CONFIG_SUNXI_AHCI) += ahci.o
-obj-$(CONFIG_A10_OLINUXINO_L) += dram_a10_olinuxino_l.o
-obj-$(CONFIG_A10S_OLINUXINO_M) += dram_a10s_olinuxino_m.o
-obj-$(CONFIG_A13_OLINUXINO) += dram_a13_olinuxino.o
-obj-$(CONFIG_A13_OLINUXINOM) += dram_a13_oli_micro.o
-obj-$(CONFIG_A20_OLINUXINO_L) += dram_a20_olinuxino_l.o
-obj-$(CONFIG_A20_OLINUXINO_M) += dram_sun7i_384_1024_iow16.o
+obj-$(CONFIG_TARGET_A10_OLINUXINO_L) += dram_a10_olinuxino_l.o
+obj-$(CONFIG_TARGET_A10S_OLINUXINO_M) += dram_a10s_olinuxino_m.o
+obj-$(CONFIG_TARGET_A13_OLINUXINO) += dram_a13_olinuxino.o
+obj-$(CONFIG_TARGET_A13_OLINUXINOM) += dram_a13_oli_micro.o
+obj-$(CONFIG_TARGET_A20_OLINUXINO_L) += dram_a20_olinuxino_l.o
+obj-$(CONFIG_TARGET_A20_OLINUXINO_L2) += dram_a20_olinuxino_l2.o
+obj-$(CONFIG_TARGET_A20_OLINUXINO_M) += dram_sun7i_384_1024_iow16.o
# This is not a typo, uses the same mem settings as the a10s-olinuxino-m
-obj-$(CONFIG_AUXTEK_T004) += dram_a10s_olinuxino_m.o
-obj-$(CONFIG_BA10_TV_BOX) += dram_sun4i_384_1024_iow8.o
-obj-$(CONFIG_BANANAPI) += dram_bananapi.o
-obj-$(CONFIG_CUBIEBOARD) += dram_cubieboard.o
-obj-$(CONFIG_CUBIEBOARD2) += dram_cubieboard2.o
-obj-$(CONFIG_CUBIETRUCK) += dram_cubietruck.o
-obj-$(CONFIG_I12_TVBOX) += dram_sun7i_384_1024_iow16.o
-obj-$(CONFIG_MELE_A1000) += dram_sun4i_360_512.o
-obj-$(CONFIG_MELE_A1000G) += dram_sun4i_360_1024_iow8.o
-obj-$(CONFIG_MINI_X) += dram_sun4i_360_512.o
-obj-$(CONFIG_MINI_X_1GB) += dram_sun4i_360_1024_iow16.o
-obj-$(CONFIG_PCDUINO3) += dram_linksprite_pcduino3.o
-obj-$(CONFIG_QT840A) += dram_sun7i_384_512_busw16_iow16.o
-obj-$(CONFIG_R7DONGLE) += dram_r7dongle.o
+obj-$(CONFIG_TARGET_AUXTEK_T004) += dram_a10s_olinuxino_m.o
+obj-$(CONFIG_TARGET_BA10_TV_BOX) += dram_sun4i_384_1024_iow8.o
+obj-$(CONFIG_TARGET_BANANAPI) += dram_bananapi.o
+obj-$(CONFIG_TARGET_CUBIEBOARD) += dram_cubieboard.o
+obj-$(CONFIG_TARGET_CUBIEBOARD2) += dram_cubieboard2.o
+obj-$(CONFIG_TARGET_CUBIETRUCK) += dram_cubietruck.o
+obj-$(CONFIG_TARGET_I12_TVBOX) += dram_sun7i_384_1024_iow16.o
+obj-$(CONFIG_TARGET_MELE_A1000) += dram_sun4i_360_512.o
+obj-$(CONFIG_TARGET_MELE_A1000G) += dram_sun4i_360_1024_iow8.o
+obj-$(CONFIG_TARGET_MELE_M3) += dram_sun7i_384_1024_iow16.o
+obj-$(CONFIG_TARGET_MINI_X) += dram_sun4i_360_512.o
+obj-$(CONFIG_TARGET_MINI_X_1GB) += dram_sun4i_360_1024_iow16.o
+obj-$(CONFIG_TARGET_PCDUINO3) += dram_linksprite_pcduino3.o
+obj-$(CONFIG_TARGET_QT840A) += dram_sun7i_384_512_busw16_iow16.o
+obj-$(CONFIG_TARGET_R7DONGLE) += dram_r7dongle.o
{
printf("SUNXI SCSI INIT\n");
#ifdef CONFIG_SATAPWR
+ gpio_request(CONFIG_SATAPWR, "satapwr");
gpio_direction_output(CONFIG_SATAPWR, 1);
#endif
*/
#include <common.h>
+#include <mmc.h>
#ifdef CONFIG_AXP152_POWER
#include <axp152.h>
#endif
break;
case 1:
- /* CMD-PH22, CLK-PH23, D0~D3-PH24~27 : 5 */
- for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN4I_GPH22_SDC1);
+ /* CMD-PG3, CLK-PG4, D0~D3-PG5-8 */
+ for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN5I_GPG3_SDC1);
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(pin, 2);
}
int board_mmc_init(bd_t *bis)
{
+ __maybe_unused struct mmc *mmc0, *mmc1;
+ __maybe_unused char buf[512];
+
mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
- sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
-#if !defined (CONFIG_SPL_BUILD) && defined (CONFIG_MMC_SUNXI_SLOT_EXTRA)
+ mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
+ if (!mmc0)
+ return -1;
+
+#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
- sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
+ mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
+ if (!mmc1)
+ return -1;
+#endif
+
+#if CONFIG_MMC_SUNXI_SLOT == 0 && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2
+ /*
+ * Both mmc0 and mmc2 are bootable, figure out where we're booting
+ * from. Try mmc0 first, just like the brom does.
+ */
+ if (mmc_getcd(mmc0) && mmc_init(mmc0) == 0 &&
+ mmc0->block_dev.block_read(0, 16, 1, buf) == 1) {
+ buf[12] = 0;
+ if (strcmp(&buf[4], "eGON.BT0") == 0)
+ return 0;
+ }
+
+ /* no bootable card in mmc0, so we must be booting from mmc2, swap */
+ mmc0->block_dev.dev = 1;
+ mmc1->block_dev.dev = 0;
#endif
return 0;
--- /dev/null
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 480,
+ .type = 3,
+ .rank_num = 1,
+ .density = 4096,
+ .io_width = 16,
+ .bus_width = 32,
+ .cas = 9,
+ .zq = 0x7f,
+ .odt_en = 0,
+ .size = 1024,
+ .tpr0 = 0x42d899b7,
+ .tpr1 = 0xa090,
+ .tpr2 = 0x22a00,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = 0x4,
+ .emr2 = 0x10,
+ .emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
if TARGET_JADECPU
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "jadecpu"
if TARGET_ZMX25
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "zmx25"
if TARGET_STAMP9G20
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "stamp9g20"
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
#include <asm/omap_gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <i2c.h>
+#include <spl.h>
+#include <mmc.h>
#include <asm/gpio.h>
#ifdef CONFIG_USB_EHCI
#include <usb.h>
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
/* JTAG */\
- MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
/* gpio_10 */\
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
/* JTAG */\
- MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
if TARGET_AM335X_EVM
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "am335x"
board you may want something other than UART0 as for example the IDK
uses UART3 so enter 4 here.
+config NOR
+ bool "Support for NOR flash"
+ help
+ The AM335x SoC supports having a NOR flash connected to the GPMC.
+ In practice this is seen as a NOR flash module connected to the
+ "memory cape" for the BeagleBone family.
+
+config NOR_BOOT
+ bool "Support for booting from NOR flash"
+ depends on NOR
+ help
+ Enabling this will make a U-Boot binary that is capable of being
+ booted via NOR. In this case we will enable certain pinmux early
+ as the ROM only partially sets up pinmux. We also default to using
+ NOR for environment.
endif
configure_module_pin_mux(i2c1_pin_mux);
configure_module_pin_mux(mii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
-#if defined(CONFIG_NAND)
+#if defined(CONFIG_NAND) && defined(CONFIG_EMMC_BOOT)
configure_module_pin_mux(nand_pin_mux);
-#elif defined(CONFIG_NOR)
+#elif defined(CONFIG_NOR) && defined(CONFIG_EMMC_BOOT)
configure_module_pin_mux(bone_norcape_pin_mux);
#else
configure_module_pin_mux(mmc1_pin_mux);
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))/*GPIO_10 TP*/\
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0))\
/*JTAG*/\
- MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\
if TARGET_AM43XX_EVM
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "am43xx"
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
#ifdef CONFIG_STATUS_LED
#include <status_led.h>
#endif
char env_setting[64];
} expansion_config;
+static const struct ns16550_platdata beagle_serial = {
+ OMAP34XX_UART3,
+ 2,
+ V_NS16550_CLK
+};
+
+U_BOOT_DEVICE(beagle_uart) = {
+ "serial_omap",
+ &beagle_serial
+};
+
/*
* Routine: board_init
* Description: Early hardware init.
*/
static int get_board_revision(void)
{
- int revision;
-
- if (!gpio_request(171, "") &&
- !gpio_request(172, "") &&
- !gpio_request(173, "")) {
-
- gpio_direction_input(171);
- gpio_direction_input(172);
- gpio_direction_input(173);
-
- revision = gpio_get_value(173) << 2 |
- gpio_get_value(172) << 1 |
- gpio_get_value(171);
- } else {
- printf("Error: unable to acquire board revision GPIOs\n");
- revision = -1;
+ static int revision = -1;
+
+ if (revision == -1) {
+ if (!gpio_request(171, "rev0") &&
+ !gpio_request(172, "rev1") &&
+ !gpio_request(173, "rev2")) {
+ gpio_direction_input(171);
+ gpio_direction_input(172);
+ gpio_direction_input(173);
+
+ revision = gpio_get_value(173) << 2 |
+ gpio_get_value(172) << 1 |
+ gpio_get_value(171);
+ } else {
+ printf("Error: unable to acquire board revision GPIOs\n");
+ }
}
return revision;
case REVISION_AXBX:
case REVISION_CX:
case REVISION_C4:
- gpio_request(170, "");
+ gpio_request(170, "dvi");
gpio_direction_output(170, 0);
gpio_set_value(170, 1);
break;
}
#endif
+static int get_led_gpio(led_id_t mask)
+{
+#ifdef STATUS_LED_BIT
+ if (STATUS_LED_BIT & mask)
+ return BEAGLE_LED_USR0;
+#endif
+#ifdef STATUS_LED_BIT1
+ if (STATUS_LED_BIT1 & mask)
+ return BEAGLE_LED_USR1;
+#endif
+
+ return 0;
+}
+
void __led_init (led_id_t mask, int state)
{
- __led_set (mask, state);
+ int toggle_gpio;
+
+ toggle_gpio = get_led_gpio(mask);
+
+ if (toggle_gpio && !gpio_request(toggle_gpio, "led"))
+ __led_set(mask, state);
}
void __led_toggle (led_id_t mask)
{
- int state, toggle_gpio = 0;
-#ifdef STATUS_LED_BIT
- if (!toggle_gpio && STATUS_LED_BIT & mask)
- toggle_gpio = BEAGLE_LED_USR0;
-#endif
-#ifdef STATUS_LED_BIT1
- if (!toggle_gpio && STATUS_LED_BIT1 & mask)
- toggle_gpio = BEAGLE_LED_USR1;
-#endif
+ int state, toggle_gpio;
+
+ toggle_gpio = get_led_gpio(mask);
if (toggle_gpio) {
- if (!gpio_request(toggle_gpio, "")) {
- gpio_direction_output(toggle_gpio, 0);
- state = gpio_get_value(toggle_gpio);
- gpio_set_value(toggle_gpio, !state);
- }
+ state = gpio_get_value(toggle_gpio);
+ gpio_direction_output(toggle_gpio, !state);
}
}
void __led_set (led_id_t mask, int state)
{
-#ifdef STATUS_LED_BIT
- if (STATUS_LED_BIT & mask) {
- if (!gpio_request(BEAGLE_LED_USR0, "")) {
- gpio_direction_output(BEAGLE_LED_USR0, 0);
- gpio_set_value(BEAGLE_LED_USR0, state);
- }
- }
-#endif
-#ifdef STATUS_LED_BIT1
- if (STATUS_LED_BIT1 & mask) {
- if (!gpio_request(BEAGLE_LED_USR1, "")) {
- gpio_direction_output(BEAGLE_LED_USR1, 0);
- gpio_set_value(BEAGLE_LED_USR1, state);
- }
- }
-#endif
+ int toggle_gpio;
+
+ toggle_gpio = get_led_gpio(mask);
+ if (toggle_gpio)
+ gpio_direction_output(toggle_gpio, state);
}
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) /*SYS_CLKOUT2*/\
- MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /*JTAG_NTRST*/\
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
default "k2hk_evm"
endif
+
+if TARGET_K2L_EVM
+
+config SYS_BOARD
+ string
+ default "ks2_evm"
+
+config SYS_VENDOR
+ string
+ default "ti"
+
+config SYS_CONFIG_NAME
+ string
+ default "k2l_evm"
+
+endif
F: configs/k2hk_evm_defconfig
F: include/configs/k2e_evm.h
F: configs/k2e_evm_defconfig
+F: include/configs/k2l_evm.h
+F: configs/k2l_evm_defconfig
obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o
obj-$(CONFIG_K2E_EVM) += board_k2e.o
obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o
+obj-$(CONFIG_K2L_EVM) += board_k2l.o
+obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o
Author: Murali Karicheri <m-karicheri2@ti.com>
-This README has information on the u-boot port for K2HK, K2E boards.
+This README has information on the u-boot port for K2HK, K2E, and K2L EVM boards.
Documentation for this board can be found at
http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx
https://www.einfochips.com/index.php/partnerships/texas-instruments/k2e-evm.html
+https://www.einfochips.com/index.php/partnerships/texas-instruments/k2l-evm.html
The K2HK board is based on Texas Instruments Keystone2 family of SoCs: K2H, K2K.
More details on these SoCs are available at company websites
K2H: http://www.ti.com/product/tci6638k2h
The K2E SoC details are available at
- K2E http://www.ti.com/lit/ds/symlink/66ak2e05.pdf
+ http://www.ti.com/lit/ds/symlink/66ak2e05.pdf
+
+The K2L SoC details are available at
+ http://www.ti.com/lit/ds/symlink/tci6630k2l.pdf
Board configuration:
====================
+------+-------+-------+-----------+-----------+-------+-------+----+
|K2HK |2 |512MB |6MB |4(2) |2 |3 |3 |
|K2E |4 |512MB |2MB |8(2) |2 |3 |3 |
+|K2L |2 |512MB |2MB |4(2) |4 |3 |3 |
+------+-------+-------+-----------+-----------+-------+-------+----+
There are only 2 eth port installed on the boards.
Board configuration files:
include/configs/k2hk_evm.h
include/configs/k2e_evm.h
+include/configs/k2l_evm.h
+include/configs/k2l_evm.h
As u-boot is migrating to Kconfig there is also board defconfig files
configs/k2e_evm_defconfig
configs/k2hk_evm_defconfig
+configs/k2l_evm_defconfig
Supported boot modes:
- SPI NOR boot
Build instructions:
===================
-Examples for k2hk, for k2e just replace k2hk prefix accordingly.
+Examples for k2hk, for k2e and k2l just replace k2hk prefix accordingly.
Don't forget to add ARCH=arm and CROSS_COMPILE.
To build u-boot.bin
on EVM. Follow instructions at
K2HK http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup
K2E http://processors.wiki.ti.com/index.php/EVMK2E_Hardware_Setup
+K2L http://processors.wiki.ti.com/index.php/TCIEVMK2L_Hardware_Setup
+
to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode"
and Power ON the EVM. Follow instructions to connect serial port of EVM to
PC and start TeraTerm or Hyper Terminal.
2. Suspend Target. Select Run -> Suspend from top level menu
CortexA15_1 (Free Running)"
3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000
- through CCS as described in step 2 of "Load and Run U-Boot on K2HK/K2E EVM
- using CCS", but using address 0x87000000.
+ through CCS as described in step 2 of "Load and Run U-Boot on K2HK/K2E/K2L
+ EVM using CCS", but using address 0x87000000.
4. Free Run the target as described earlier (step 4) to get u-boot prompt
5. At the U-Boot console type following to setup u-boot environment variables.
setenv addr_uboot 0x87000000
#include "board.h"
#include <common.h>
+#include <spl.h>
#include <exports.h>
#include <fdt_support.h>
#include <asm/arch/ddr3.h>
-#include <asm/arch/emac_defs.h>
+#include <asm/arch/psc_defs.h>
#include <asm/ti-common/ti-aemif.h>
+#include <asm/ti-common/keystone_net.h>
DECLARE_GLOBAL_DATA_PTR;
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
+ ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE);
return 0;
}
int port_num;
char link_type_name[32];
+ /* By default, select PA PLL clock as PA clock source */
+ if (psc_enable_module(KS2_LPSC_PA))
+ return -1;
+ if (psc_enable_module(KS2_LPSC_CPGMAC))
+ return -1;
+ if (psc_enable_module(KS2_LPSC_CRYPTO))
+ return -1;
+ pass_pll_pa_clk_enable();
+
port_num = get_num_eth_ports();
for (j = 0; j < port_num; j++) {
}
#endif
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+ spl_init_keystone_plls();
+ preloader_console_init();
+}
+
+u32 spl_boot_device(void)
+{
+#if defined(CONFIG_SPL_SPI_LOAD)
+ return BOOT_DEVICE_SPI;
+#else
+ puts("Unknown boot device\n");
+ hang();
+#endif
+}
+#endif
+
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
int nbanks;
u64 size[2];
u64 start[2];
- char name[32];
int nodeoffset;
u32 ddr3a_size;
int unitrd_fixup = 0;
}
/* reserve memory at start of bank */
- sprintf(name, "mem_reserve_head");
- env = getenv(name);
+ env = getenv("mem_reserve_head");
if (env) {
start[0] += ustrtoul(env, &endp, 0);
size[0] -= ustrtoul(env, &endp, 0);
}
- sprintf(name, "mem_reserve");
- env = getenv(name);
+ env = getenv("mem_reserve");
if (env)
size[0] -= ustrtoul(env, &endp, 0);
reserve_start += 2;
}
}
+
+ ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
}
#endif
#ifndef _KS2_BOARD
#define _KS2_BOARD
-#include <asm/arch/emac_defs.h>
+#include <asm/ti-common/keystone_net.h>
extern struct eth_priv_t eth_priv_cfg[];
int get_num_eth_ports(void);
+void spl_init_keystone_plls(void);
#endif
#include <common.h>
#include <asm/arch/ddr3.h>
#include <asm/arch/hardware.h>
+#include <asm/ti-common/keystone_net.h>
DECLARE_GLOBAL_DATA_PTR;
CORE_PLL_1500,
};
-
static struct pll_init_data pa_pll_config =
PASS_PLL_1000;
+#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
+struct eth_priv_t eth_priv_cfg[] = {
+ {
+ .int_name = "K2E_EMAC0",
+ .rx_flow = 0,
+ .phy_addr = 0,
+ .slave_port = 1,
+ .sgmii_link_type = SGMII_LINK_MAC_PHY,
+ },
+ {
+ .int_name = "K2E_EMAC1",
+ .rx_flow = 8,
+ .phy_addr = 1,
+ .slave_port = 2,
+ .sgmii_link_type = SGMII_LINK_MAC_PHY,
+ },
+ {
+ .int_name = "K2E_EMAC2",
+ .rx_flow = 16,
+ .phy_addr = 2,
+ .slave_port = 3,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+ {
+ .int_name = "K2E_EMAC3",
+ .rx_flow = 24,
+ .phy_addr = 3,
+ .slave_port = 4,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+ {
+ .int_name = "K2E_EMAC4",
+ .rx_flow = 32,
+ .phy_addr = 4,
+ .slave_port = 5,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+ {
+ .int_name = "K2E_EMAC5",
+ .rx_flow = 40,
+ .phy_addr = 5,
+ .slave_port = 6,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+ {
+ .int_name = "K2E_EMAC6",
+ .rx_flow = 48,
+ .phy_addr = 6,
+ .slave_port = 7,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+ {
+ .int_name = "K2E_EMAC7",
+ .rx_flow = 56,
+ .phy_addr = 7,
+ .slave_port = 8,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+};
+
+int get_num_eth_ports(void)
+{
+ return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
+}
+#endif
+
#if defined(CONFIG_BOARD_EARLY_INIT_F)
int board_early_init_f(void)
{
return 0;
}
#endif
+
+#ifdef CONFIG_SPL_BUILD
+static struct pll_init_data spl_pll_config[] = {
+ CORE_PLL_800,
+};
+
+void spl_init_keystone_plls(void)
+{
+ init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
+}
+#endif
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
-#include <asm/arch/emac_defs.h>
+#include <asm/ti-common/keystone_net.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
#endif
+
+#ifdef CONFIG_SPL_BUILD
+static struct pll_init_data spl_pll_config[] = {
+ CORE_PLL_799,
+ TETRIS_PLL_500,
+};
+
+void spl_init_keystone_plls(void)
+{
+ init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
+}
+#endif
--- /dev/null
+/*
+ * K2L EVM : Board initialization
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+#include <asm/ti-common/keystone_net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int external_clk[ext_clk_count] = {
+ [sys_clk] = 122880000,
+ [alt_core_clk] = 100000000,
+ [pa_clk] = 122880000,
+ [tetris_clk] = 122880000,
+ [ddr3_clk] = 100000000,
+ [pcie_clk] = 100000000,
+ [sgmii_clk] = 156250000,
+ [usb_clk] = 100000000,
+};
+
+static struct pll_init_data core_pll_config[] = {
+ CORE_PLL_799,
+ CORE_PLL_1000,
+ CORE_PLL_1198,
+};
+
+static struct pll_init_data tetris_pll_config[] = {
+ TETRIS_PLL_799,
+ TETRIS_PLL_1000,
+ TETRIS_PLL_1198,
+ TETRIS_PLL_1352,
+ TETRIS_PLL_1401,
+};
+
+static struct pll_init_data pa_pll_config =
+ PASS_PLL_983;
+
+#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
+struct eth_priv_t eth_priv_cfg[] = {
+ {
+ .int_name = "K2L_EMAC",
+ .rx_flow = 0,
+ .phy_addr = 0,
+ .slave_port = 1,
+ .sgmii_link_type = SGMII_LINK_MAC_PHY,
+ },
+ {
+ .int_name = "K2L_EMAC1",
+ .rx_flow = 8,
+ .phy_addr = 1,
+ .slave_port = 2,
+ .sgmii_link_type = SGMII_LINK_MAC_PHY,
+ },
+ {
+ .int_name = "K2L_EMAC2",
+ .rx_flow = 16,
+ .phy_addr = 2,
+ .slave_port = 3,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+ {
+ .int_name = "K2L_EMAC3",
+ .rx_flow = 32,
+ .phy_addr = 3,
+ .slave_port = 4,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+};
+
+int get_num_eth_ports(void)
+{
+ return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ int speed;
+
+ speed = get_max_dev_speed();
+ init_pll(&core_pll_config[speed]);
+
+ init_pll(&pa_pll_config);
+
+ speed = get_max_arm_speed();
+ init_pll(&tetris_pll_config[speed]);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+static struct pll_init_data spl_pll_config[] = {
+ CORE_PLL_799,
+ TETRIS_PLL_491,
+};
+
+void spl_init_keystone_plls(void)
+{
+ init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
+}
+#endif
};
#endif
+struct ddr3_phy_config ddr3phy_1600_2g = {
+ .pllcr = 0x0001C000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0, /* not set in gel */
+ .ptr3 = 0x0D861A80ul,
+ .ptr4 = 0x0C827100ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+ .dcr_val = ((1 << 10)),
+ .dtpr0 = 0x9D5CBB66ul,
+ .dtpr1 = 0x12868300ul,
+ .dtpr2 = 0x5002D200ul,
+ .mr0 = 0x00001C70ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000018ul,
+ .dtcr = 0x710035C7ul,
+ .pgcr2 = 0x00F07A12ul,
+ .zq0cr1 = 0x0001005Dul,
+ .zq1cr1 = 0x0001005Bul,
+ .zq2cr1 = 0x0001005Bul,
+ .pir_v1 = 0x00000033ul,
+ .pir_v2 = 0x0000FF81ul,
+};
+
+struct ddr3_emif_config ddr3_1600_2g = {
+ .sdcfg = 0x6200CE62ul,
+ .sdtim1 = 0x166C9855ul,
+ .sdtim2 = 0x00001D4Aul,
+ .sdtim3 = 0x435DFF53ul,
+ .sdtim4 = 0x543F0CFFul,
+ .zqcfg = 0x70073200ul,
+ .sdrfc = 0x00001869ul,
+};
+
int ddr3_get_dimm_params(char *dimm_name)
{
int ret;
extern struct ddr3_phy_config ddr3phy_1600_4g;
extern struct ddr3_emif_config ddr3_1600_4g;
+extern struct ddr3_phy_config ddr3phy_1600_2g;
+extern struct ddr3_emif_config ddr3_1600_2g;
+
int ddr3_get_dimm_params(char *dimm_name);
#endif /* __DDR3_CFG_H */
#include <asm/arch/ddr3.h>
#include <asm/arch/hardware.h>
+static int ddr3_size;
+
struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
&ddr3_1600_8g);
printf("DRAM: Capacity 8 GiB (includes reported below)\n");
+ ddr3_size = 8;
} else {
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
ddr3_1600_8g.sdcfg |= 0x1000;
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
&ddr3_1600_8g);
printf("DRAM: Capacity 4 GiB (includes reported below)\n");
+ ddr3_size = 4;
}
} else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
init_pll(&ddr3a_333);
}
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
&ddr3_1333_2g);
+ ddr3_size = 2;
+ printf("DRAM: 2 GiB");
} else {
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g);
ddr3_1333_2g.sdcfg |= 0x1000;
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
&ddr3_1333_2g);
+ ddr3_size = 1;
+ printf("DRAM: 1 GiB");
}
} else {
printf("Unknown SO-DIMM. Cannot configure DDR3\n");
if (cpu_revision() <= 1)
ddr3_err_reset_workaround();
}
+
+/**
+ * ddr3_get_size - return ddr3 size in GiB
+ */
+int ddr3_get_size(void)
+{
+ return ddr3_size;
+}
--- /dev/null
+/*
+ * Keystone2: DDR3 initialization
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include "ddr3_cfg.h"
+#include <asm/arch/ddr3.h>
+
+static int ddr3_size;
+static struct pll_init_data ddr3_400 = DDR3_PLL_400;
+
+void ddr3_init(void)
+{
+ init_pll(&ddr3_400);
+
+ /* No SO-DIMM, 2GB discreet DDR */
+ printf("DRAM: 2 GiB\n");
+ ddr3_size = 2;
+
+ /* Reset DDR3 PHY after PLL enabled */
+ ddr3_reset_ddrphy();
+
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g);
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g);
+}
+
+/**
+ * ddr3_get_size - return ddr3 size in GiB
+ */
+int ddr3_get_size(void)
+{
+ return ddr3_size;
+}
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SYS_CLKOUT2), (OFF_IN_PD | IEN | PTU | EN | M4))/*GPIO_186*/\
- MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\
if TARGET_TI814X_EVM
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "ti814x"
if TARGET_TI816X_EVM
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "ti816x"
if TARGET_TNETV107X_EVM
-config SYS_CPU
- default "arm1176"
-
config SYS_BOARD
default "tnetv107xevm"
if TARGET_DEVKIT3250
-config SYS_CPU
- default "arm926ejs"
-
config SYS_BOARD
default "devkit3250"
if TARGET_COLIBRI_PXA270
-config SYS_CPU
- default "pxa"
-
config SYS_BOARD
default "colibri_pxa270"
+++ /dev/null
-if TARGET_TQM8260
-
-config SYS_BOARD
- default "tqm8260"
-
-config SYS_VENDOR
- default "tqc"
-
-config SYS_CONFIG_NAME
- default "TQM8260"
-
-endif
+++ /dev/null
-TQM8260 BOARD
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-F: board/tqc/tqm8260/
-F: include/configs/TQM8260.h
-F: configs/TQM8255_AA_defconfig
-F: configs/TQM8260_AA_defconfig
-F: configs/TQM8260_AB_defconfig
-F: configs/TQM8260_AC_defconfig
-F: configs/TQM8260_AD_defconfig
-F: configs/TQM8260_AE_defconfig
-F: configs/TQM8260_AF_defconfig
-F: configs/TQM8260_AG_defconfig
-F: configs/TQM8260_AH_defconfig
-F: configs/TQM8260_AI_defconfig
-F: configs/TQM8265_AA_defconfig
+++ /dev/null
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = tqm8260.o ../tqm8xx/load_sernum_ethaddr.o
+++ /dev/null
-
-This file contains basic information on the port of U-Boot to TQM8260.
-All the changes fit in the common U-Boot infrastructure, providing a
-new TQM8260-specific entry in makefiles. To build U-Boot for TQM8260,
-type "make TQM8260_config", edit the "include/config_TQM8260.h" file
-if necessary, then type "make".
-
-
-Common file modifications:
---------------------------
-
-The following common files have been modified by this project:
-(starting from the ppcboot-0.9.3/ directory)
-
-MAKEALL - TQM8260 entry added
-Makefile - TQM8260_config entry added
-arch/powerpc/cpu/mpc8260/Makefile - soft_i2c.o module added
-arch/powerpc/cpu/mpc8260/ether_scc.c - TQM8260-specific definitions added, an obvious
- bug fixed (fcr -> scr)
-arch/powerpc/cpu/mpc8260/ether_fcc.c - TQM8260-specific definitions added
-include/flash.h - added definitions for the AM29LV640D Flash chip
-
-
-New files:
-----------
-
-The following new files have been added by this project:
-(starting from the ppcboot-0.9.3/ directory)
-
-board/tqm8260/ - board-specific directory
-board/tqm8260/Makefile - board-specific makefile
-board/tqm8260/config.mk - config file
-board/tqm8260/flash.c - flash driver (for AM29LV640D)
-board/tqm8260/ppcboot.lds - linker script
-board/tqm8260/tqm8260.c - ioport and memory initialization
-arch/powerpc/cpu/mpc8260/soft_i2c.c - software i2c EEPROM driver
-include/config_TQM8260.h - main configuration file
-
-
-New configuration options:
---------------------------
-
-CONFIG_TQM8260
-
- Main board-specific option (should be defined for TQM8260).
-
-CONFIG_82xx_CONS_SMC1
-
- If defined, SMC1 will be used as the console
-
-CONFIG_82xx_CONS_SMC2
-
- If defined, SMC2 will be used as the console
-
-CONFIG_SYS_INIT_LOCAL_SDRAM
-
- If defined, the SDRAM on the local bus will be initialized and
- mapped at BR2.
-
-
-Acceptance criteria tests:
---------------------------
-
-The following tests have been conducted to validate the port of U-Boot
-to TQM8260:
-
-1. Operation on serial console:
-
-With the CONFIG_82xx_CONS_SMC1 option defined in the main configuration file,
-the U-Boot output appeared on the serial terminal connected to COM1 as
-follows:
-
-------------------------------------------------------------------------------
-=> help
-go - start application at address 'addr'
-run - run commands in an environment variable
-bootm - boot application image from memory
-bootp - boot image via network using BootP/TFTP protocol
-tftpboot- boot image via network using TFTP protocol
- and env variables ipaddr and serverip
-rarpboot- boot image via network using RARP/TFTP protocol
-bootd - boot default, i.e., run 'bootcmd'
-loads - load S-Record file over serial line
-loadb - load binary file over serial line (kermit mode)
-md - memory display
-mm - memory modify (auto-incrementing)
-nm - memory modify (constant address)
-mw - memory write (fill)
-cp - memory copy
-cmp - memory compare
-crc32 - checksum calculation
-base - print or set address offset
-printenv- print environment variables
-setenv - set environment variables
-saveenv - save environment variables to persistent storage
-protect - enable or disable FLASH write protection
-erase - erase FLASH memory
-flinfo - print FLASH memory information
-bdinfo - print Board Info structure
-iminfo - print header information for application image
-coninfo - print console devices and informations
-eeprom - EEPROM sub-system
-loop - infinite loop on address range
-mtest - simple RAM test
-icache - enable or disable instruction cache
-dcache - enable or disable data cache
-reset - Perform RESET of the CPU
-echo - echo args to console
-version - print monitor version
-help - print online help
-? - alias for 'help'
-=>
-------------------------------------------------------------------------------
-
-
-2. Flash driver operation
-
-The following sequence was performed to test the "flinfo" command:
-
-------------------------------------------------------------------------------
-=> flinfo
-
-Bank # 1: AMD 29LV640D (64 M, uniform sector)
- Size: 32 MB in 128 Sectors
- Sector Start Addresses:
- 40000000 40040000 (RO) 40080000 400C0000 40100000
- 40140000 40180000 401C0000 40200000 40240000
- 40280000 402C0000 40300000 40340000 40380000
- 403C0000 40400000 40440000 40480000 404C0000
- 40500000 40540000 40580000 405C0000 40600000
- 40640000 40680000 406C0000 40700000 40740000
- 40780000 407C0000 40800000 40840000 40880000
- 408C0000 40900000 40940000 40980000 409C0000
- 40A00000 40A40000 40A80000 40AC0000 40B00000
- 40B40000 40B80000 40BC0000 40C00000 40C40000
- 40C80000 40CC0000 40D00000 40D40000 40D80000
- 40DC0000 40E00000 40E40000 40E80000 40EC0000
- 40F00000 40F40000 40F80000 40FC0000 41000000
- 41040000 41080000 410C0000 41100000 41140000
- 41180000 411C0000 41200000 41240000 41280000
- 412C0000 41300000 41340000 41380000 413C0000
- 41400000 41440000 41480000 414C0000 41500000
- 41540000 41580000 415C0000 41600000 41640000
- 41680000 416C0000 41700000 41740000 41780000
- 417C0000 41800000 41840000 41880000 418C0000
- 41900000 41940000 41980000 419C0000 41A00000
- 41A40000 41A80000 41AC0000 41B00000 41B40000
- 41B80000 41BC0000 41C00000 41C40000 41C80000
- 41CC0000 41D00000 41D40000 41D80000 41DC0000
- 41E00000 41E40000 41E80000 41EC0000 41F00000
- 41F40000 41F80000 41FC0000
-=>
-------------------------------------------------------------------------------
-
-
-The following sequence was performed to test the erase command:
-
-------------------------------------------------------------------------------
-=> cp 0 40080000 10
-Copy to Flash... done
-=> erase 40080000 400bffff
-Erase Flash from 0x40080000 to 0x400bffff
-.. done
-Erased 1 sectors
-=> md 40080000
-40080000: ffffffff ffffffff ffffffff ffffffff ................
-40080010: ffffffff ffffffff ffffffff ffffffff ................
-40080020: ffffffff ffffffff ffffffff ffffffff ................
-40080030: ffffffff ffffffff ffffffff ffffffff ................
-40080040: ffffffff ffffffff ffffffff ffffffff ................
-40080050: ffffffff ffffffff ffffffff ffffffff ................
-40080060: ffffffff ffffffff ffffffff ffffffff ................
-40080070: ffffffff ffffffff ffffffff ffffffff ................
-40080080: ffffffff ffffffff ffffffff ffffffff ................
-40080090: ffffffff ffffffff ffffffff ffffffff ................
-400800a0: ffffffff ffffffff ffffffff ffffffff ................
-400800b0: ffffffff ffffffff ffffffff ffffffff ................
-400800c0: ffffffff ffffffff ffffffff ffffffff ................
-400800d0: ffffffff ffffffff ffffffff ffffffff ................
-400800e0: ffffffff ffffffff ffffffff ffffffff ................
-400800f0: ffffffff ffffffff ffffffff ffffffff ................
-=> cp 0 40080000 10
-Copy to Flash... done
-=> erase 1:2
-Erase Flash Sectors 2-2 in Bank # 1
-.. done
-=> md 40080000
-40080000: ffffffff ffffffff ffffffff ffffffff ................
-40080010: ffffffff ffffffff ffffffff ffffffff ................
-40080020: ffffffff ffffffff ffffffff ffffffff ................
-40080030: ffffffff ffffffff ffffffff ffffffff ................
-40080040: ffffffff ffffffff ffffffff ffffffff ................
-40080050: ffffffff ffffffff ffffffff ffffffff ................
-40080060: ffffffff ffffffff ffffffff ffffffff ................
-40080070: ffffffff ffffffff ffffffff ffffffff ................
-40080080: ffffffff ffffffff ffffffff ffffffff ................
-40080090: ffffffff ffffffff ffffffff ffffffff ................
-400800a0: ffffffff ffffffff ffffffff ffffffff ................
-400800b0: ffffffff ffffffff ffffffff ffffffff ................
-400800c0: ffffffff ffffffff ffffffff ffffffff ................
-400800d0: ffffffff ffffffff ffffffff ffffffff ................
-400800e0: ffffffff ffffffff ffffffff ffffffff ................
-400800f0: ffffffff ffffffff ffffffff ffffffff ................
-=> cp 0 40080000 10
-Copy to Flash... done
-=> cp 0 400c0000 10
-Copy to Flash... done
-=> erase 1:2-3
-Erase Flash Sectors 2-3 in Bank # 1
-... done
-=> md 40080000
-40080000: ffffffff ffffffff ffffffff ffffffff ................
-40080010: ffffffff ffffffff ffffffff ffffffff ................
-40080020: ffffffff ffffffff ffffffff ffffffff ................
-40080030: ffffffff ffffffff ffffffff ffffffff ................
-40080040: ffffffff ffffffff ffffffff ffffffff ................
-40080050: ffffffff ffffffff ffffffff ffffffff ................
-40080060: ffffffff ffffffff ffffffff ffffffff ................
-40080070: ffffffff ffffffff ffffffff ffffffff ................
-40080080: ffffffff ffffffff ffffffff ffffffff ................
-40080090: ffffffff ffffffff ffffffff ffffffff ................
-400800a0: ffffffff ffffffff ffffffff ffffffff ................
-400800b0: ffffffff ffffffff ffffffff ffffffff ................
-400800c0: ffffffff ffffffff ffffffff ffffffff ................
-400800d0: ffffffff ffffffff ffffffff ffffffff ................
-400800e0: ffffffff ffffffff ffffffff ffffffff ................
-400800f0: ffffffff ffffffff ffffffff ffffffff ................
-=> md 400c0000
-400c0000: ffffffff ffffffff ffffffff ffffffff ................
-400c0010: ffffffff ffffffff ffffffff ffffffff ................
-400c0020: ffffffff ffffffff ffffffff ffffffff ................
-400c0030: ffffffff ffffffff ffffffff ffffffff ................
-400c0040: ffffffff ffffffff ffffffff ffffffff ................
-400c0050: ffffffff ffffffff ffffffff ffffffff ................
-400c0060: ffffffff ffffffff ffffffff ffffffff ................
-400c0070: ffffffff ffffffff ffffffff ffffffff ................
-400c0080: ffffffff ffffffff ffffffff ffffffff ................
-400c0090: ffffffff ffffffff ffffffff ffffffff ................
-400c00a0: ffffffff ffffffff ffffffff ffffffff ................
-400c00b0: ffffffff ffffffff ffffffff ffffffff ................
-400c00c0: ffffffff ffffffff ffffffff ffffffff ................
-400c00d0: ffffffff ffffffff ffffffff ffffffff ................
-400c00e0: ffffffff ffffffff ffffffff ffffffff ................
-400c00f0: ffffffff ffffffff ffffffff ffffffff ................
-=>
-------------------------------------------------------------------------------
-
-
-The following sequence was performed to test the Flash programming commands:
-
-------------------------------------------------------------------------------
-=> erase 40080000 400bffff
-Erase Flash from 0x40080000 to 0x400bffff
-.. done
-Erased 1 sectors
-=> cp 0 40080000 10
-Copy to Flash... done
-=> md 0
-00000000: 00000000 00000104 61100200 01000000 ........a.......
-00000010: 00000000 00000000 81140000 82000100 ................
-00000020: 01080000 00004000 22800000 00000600 ......@.".......
-00000030: 00200800 00000000 10000100 00008000 . ..............
-00000040: 00812000 00000200 00020000 80000000 .. .............
-00000050: 00028001 00001000 00040400 00000200 ................
-00000060: 20480000 00000000 20090000 00142000 H...... ..... .
-00000070: 00000000 00004000 24210000 10000000 ......@.$!......
-00000080: 02440002 10000000 00200008 00000000 .D....... ......
-00000090: 02440900 00000000 30a40000 00004400 .D......0.....D.
-000000a0: 04420800 00000000 00000040 00020000 .B.........@....
-000000b0: 05020000 00100000 00060000 00000000 ................
-000000c0: 00400000 00000000 00080000 00040000 .@..............
-000000d0: 10400000 00800004 00000000 00000200 .@..............
-000000e0: 80890000 00010004 00080000 00000020 ...............
-000000f0: 08000000 10000000 00010000 00000000 ................
-=> md 40080000
-40080000: 00000000 00000104 61100200 01000000 ........a.......
-40080010: 00000000 00000000 81140000 82000100 ................
-40080020: 01080000 00004000 22800000 00000600 ......@.".......
-40080030: 00200800 00000000 10000100 00008000 . ..............
-40080040: ffffffff ffffffff ffffffff ffffffff ................
-40080050: ffffffff ffffffff ffffffff ffffffff ................
-40080060: ffffffff ffffffff ffffffff ffffffff ................
-40080070: ffffffff ffffffff ffffffff ffffffff ................
-40080080: ffffffff ffffffff ffffffff ffffffff ................
-40080090: ffffffff ffffffff ffffffff ffffffff ................
-400800a0: ffffffff ffffffff ffffffff ffffffff ................
-400800b0: ffffffff ffffffff ffffffff ffffffff ................
-400800c0: ffffffff ffffffff ffffffff ffffffff ................
-400800d0: ffffffff ffffffff ffffffff ffffffff ................
-400800e0: ffffffff ffffffff ffffffff ffffffff ................
-400800f0: ffffffff ffffffff ffffffff ffffffff ................
-=>
-------------------------------------------------------------------------------
-
-
-The following sequence was performed to test storage of the environment
-variables in Flash:
-
-------------------------------------------------------------------------------
-=> setenv foo bar
-=> saveenv
-Un-Protected 1 sectors
-Erasing Flash...
-.. done
-Erased 1 sectors
-Saving Environment to Flash...
-Protected 1 sectors
-=> reset
-...
-=> printenv
-bootdelay=CONFIG_BOOTDELAY
-baudrate=9600
-ipaddr=192.168.4.7
-serverip=192.168.4.1
-ethaddr=66:55:44:33:22:11
-foo=bar
-stdin=serial
-stdout=serial
-stderr=serial
-
-Environment size: 170/262140 bytes
-=>
-------------------------------------------------------------------------------
-
-
-The following sequence was performed to test image download and run over
-Ethernet interface (both interfaces were tested):
-
-------------------------------------------------------------------------------
-=> tftpboot 40000 hello_world.bin
-ARP broadcast 1
-TFTP from server 192.168.2.2; our IP address is 192.168.2.7
-Filename 'hello_world.bin'.
-Load address: 0x40000
-Loading: #############
-done
-Bytes transferred = 65912 (10178 hex)
-=> go 40004
-## Starting application at 0x00040004 ...
-Hello World
-argc = 1
-argv[0] = "40004"
-argv[1] = "<NULL>"
-Hit any key to exit ...
-
-## Application terminated, rc = 0x0
-=>
-------------------------------------------------------------------------------
-
-
-The following sequence was performed to test eeprom read/write commands:
-
-------------------------------------------------------------------------------
-=> md 40000
-00040000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a..
-00040010: 90010024 48000005 7fc802a6 801effe8 ...$H...........
-00040020: 7fc0f214 7c7f1b78 813f004c 7c9c2378 ....|..x.?.L|.#x
-00040030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`..
-00040040: 7c0803a6 4e800021 813f004c 7f84e378 |...N..!.?.L...x
-00040050: 807e8004 80090010 7c0803a6 4e800021 .~......|...N..!
-00040060: 7c1be000 4181003c 80bd0000 813f004c |...A..<.....?.L
-00040070: 3bbd0004 2c050000 40820008 80be8008 ;...,...@.......
-00040080: 80090010 7f64db78 807e800c 3b7b0001 .....d.x.~..;{..
-00040090: 7c0803a6 4e800021 7c1be000 4081ffcc |...N..!|...@...
-000400a0: 813f004c 807e8010 80090010 7c0803a6 .?.L.~......|...
-000400b0: 4e800021 813f004c 80090004 7c0803a6 N..!.?.L....|...
-000400c0: 4e800021 2c030000 4182ffec 813f004c N..!,...A....?.L
-000400d0: 80090000 7c0803a6 4e800021 813f004c ....|...N..!.?.L
-000400e0: 807e8014 80090010 7c0803a6 4e800021 .~......|...N..!
-000400f0: 38600000 80010024 7c0803a6 bb61000c 8`.....$|....a..
-=> eeprom write 40000 0 40
-
-EEPROM write: addr 00040000 off 0000 count 64 ... done
-=> mw 50000 0 1000
-=> eeprom read 50000 0 40
-
-EEPROM read: addr 00050000 off 0000 count 64 ... done
-=> md 50000
-00050000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a..
-00050010: 90010024 48000005 7fc802a6 801effe8 ...$H...........
-00050020: 7fc0f214 7c7f1b78 813f004c 7c9c2378 ....|..x.?.L|.#x
-00050030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`..
-00050040: 00000000 00000000 00000000 00000000 ................
-00050050: 00000000 00000000 00000000 00000000 ................
-00050060: 00000000 00000000 00000000 00000000 ................
-00050070: 00000000 00000000 00000000 00000000 ................
-00050080: 00000000 00000000 00000000 00000000 ................
-00050090: 00000000 00000000 00000000 00000000 ................
-000500a0: 00000000 00000000 00000000 00000000 ................
-000500b0: 00000000 00000000 00000000 00000000 ................
-000500c0: 00000000 00000000 00000000 00000000 ................
-000500d0: 00000000 00000000 00000000 00000000 ................
-000500e0: 00000000 00000000 00000000 00000000 ................
-000500f0: 00000000 00000000 00000000 00000000 ................
-=>
-------------------------------------------------------------------------------
-
-
-Patch per Mon, 06 Aug 2001 17:57:27:
-
-- upgraded Flash support (added support for the following chips:
- AM29LV800T/B, AM29LV160T/B, AM29DL322T/B, AM29DL323T/B)
-- BCR tweakage for the 8260 bus mode
-- SIUMCR tweakage enabling the MI interrupt (IRQ7)
-
-To simplify switching between the bus modes, a new configuration
-option (CONFIG_BUSMODE_60x) has been added to the "config_TQM8260.h"
-file. If it is defined, BCR will be configured for the 60x mode,
-otherwise - for the 8260 mode.
-
-Concerning the SIUMCR modification: it's hard to predict whether it
-will induce any problems on the other (60x mode) board. However, the
-problems (if they appear) should be easy to notice - if the board
-does not boot, it's most likely caused by the DPPC configuration in
-SIUMCR.
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */
- /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */
- /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */
- /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */
- /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */
- /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */
- /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
- /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
- /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
- /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
- /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
- /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
- /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
- /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
- /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */
- /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */
- /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */
- /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */
- /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */
- /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */
- /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */
- /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */
- /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
- /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
- /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
- /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
- /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
- /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
- /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
- /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
- /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
- /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
- /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
- /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
- /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
- /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
- /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
- /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
- /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
- /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
- /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
- /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
- /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
- /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
- /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
- /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
- /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
- /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */
- /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */
- /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
- /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
- /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
- /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
- /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
- /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
- /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
-#if defined(CONFIG_SYS_I2C_SOFT)
- /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
- /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
-#else
-#if defined(CONFIG_HARD_I2C)
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
-#else /* normal I/O port pins */
- /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
-#endif
-#endif
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-/* ------------------------------------------------------------------------- */
-
-/* Check Board Identity:
- */
-int checkboard (void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- puts ("Board: ");
-
- if (i < 0 || strncmp(buf, "TQM82", 5)) {
- puts ("### No HW ID - assuming TQM8260\n");
- return (0);
- }
-
- puts (buf);
- putc ('\n');
-
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
- *
- * This routine performs standard 8260 initialization sequence
- * and calculates the available memory size. It may be called
- * several times to try different SDRAM configurations on both
- * 60x and local buses.
- */
-static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
- ulong orx, volatile uchar * base)
-{
- volatile uchar c = 0xff;
- volatile uint *sdmr_ptr;
- volatile uint *orx_ptr;
- ulong maxsize, size;
- int i;
-
- /* We must be able to test a location outsize the maximum legal size
- * to find out THAT we are outside; but this address still has to be
- * mapped by the controller. That means, that the initial mapping has
- * to be (at least) twice as large as the maximum expected size.
- */
- maxsize = (1 + (~orx | 0x7fff)) / 2;
-
- /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
- * we are configuring CS1 if base != 0
- */
- sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
- orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
-
- *orx_ptr = orx;
-
- /*
- * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
- *
- * "At system reset, initialization software must set up the
- * programmable parameters in the memory controller banks registers
- * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
- * system software should execute the following initialization sequence
- * for each SDRAM device.
- *
- * 1. Issue a PRECHARGE-ALL-BANKS command
- * 2. Issue eight CBR REFRESH commands
- * 3. Issue a MODE-SET command to initialize the mode register
- *
- * The initial commands are executed by setting P/LSDMR[OP] and
- * accessing the SDRAM with a single-byte transaction."
- *
- * The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
- */
-
- *sdmr_ptr = sdmr | PSDMR_OP_PREA;
- *base = c;
-
- *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
- *base = c;
-
- *sdmr_ptr = sdmr | PSDMR_OP_MRW;
- *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
-
- *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
- *base = c;
-
- size = get_ram_size((long *)base, maxsize);
- *orx_ptr = orx | ~(size - 1);
-
- return (size);
-}
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
-
-#ifndef CONFIG_SYS_RAMBOOT
- long size8, size9;
-#endif
- long psize, lsize;
-
- psize = 16 * 1024 * 1024;
- lsize = 0;
-
- memctl->memc_psrt = CONFIG_SYS_PSRT;
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-#if 0 /* Just for debugging */
-#define prt_br_or(brX,orX) do { \
- ulong start = memctl->memc_ ## brX & 0xFFFF8000; \
- ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF; \
- printf ("\n" \
- #brX " 0x%08x " #orX " 0x%08x " \
- "==> 0x%08lx ... 0x%08lx = %ld MB\n", \
- memctl->memc_ ## brX, memctl->memc_ ## orX, \
- start, start+sizem, (sizem+1)>>20); \
- } while (0)
- prt_br_or (br0, or0);
- prt_br_or (br1, or1);
- prt_br_or (br2, or2);
- prt_br_or (br3, or3);
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
- /* 60x SDRAM setup:
- */
- size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
- size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
-
- if (size8 < size9) {
- psize = size9;
- printf ("(60x:9COL - %ld MB, ", psize >> 20);
- } else {
- psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
- printf ("(60x:8COL - %ld MB, ", psize >> 20);
- }
-
- /* Local SDRAM setup:
- */
-#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
- memctl->memc_lsrt = CONFIG_SYS_LSRT;
- size8 = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
- (uchar *) SDRAM_BASE2_PRELIM);
- size9 = try_init (memctl, CONFIG_SYS_LSDMR_9COL, CONFIG_SYS_OR2_9COL,
- (uchar *) SDRAM_BASE2_PRELIM);
-
- if (size8 < size9) {
- lsize = size9;
- printf ("Local:9COL - %ld MB) using ", lsize >> 20);
- } else {
- lsize = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
- (uchar *) SDRAM_BASE2_PRELIM);
- printf ("Local:8COL - %ld MB) using ", lsize >> 20);
- }
-
-#if 0
- /* Set up BR2 so that the local SDRAM goes
- * right after the 60x SDRAM
- */
- memctl->memc_br2 = (CONFIG_SYS_BR2_PRELIM & ~BRx_BA_MSK) |
- (CONFIG_SYS_SDRAM_BASE + psize);
-#endif
-#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
-#endif /* CONFIG_SYS_RAMBOOT */
-
- icache_enable ();
-
- return (psize);
-}
-
-/* ------------------------------------------------------------------------- */
+++ /dev/null
-if TARGET_TQM8272
-
-config SYS_BOARD
- default "tqm8272"
-
-config SYS_VENDOR
- default "tqc"
-
-config SYS_CONFIG_NAME
- default "TQM8272"
-
-endif
+++ /dev/null
-TQM8272 BOARD
-#M: -
-S: Maintained
-F: board/tqc/tqm8272/
-F: include/configs/TQM8272.h
-F: configs/TQM8272_defconfig
+++ /dev/null
-#
-# (C) Copyright 2001-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = tqm8272.o ../tqm8xx/load_sernum_ethaddr.o nand.o
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-
-#include "tqm8272.h"
-
-/* UPM pattern for bus clock = 66.7 MHz */
-static const uint upmTable67[] =
-{
- /* Offset UPM Read Single RAM array entry -> NAND Read Data */
- /* 0x00 */ 0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000,
- /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> unused */
- /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> unused */
- /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
- /* 0x18 */ 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00,
- /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
-
- /* UPM Write Burst RAM array entry -> unused */
- /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Refresh Timer RAM array entry -> unused */
- /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Exception RAM array entry -> unsused */
- /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for bus clock = 100 MHz */
-static const uint upmTable100[] =
-{
- /* Offset UPM Read Single RAM array entry -> NAND Read Data */
- /* 0x00 */ 0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
- /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> unused */
- /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> unused */
- /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
- /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00,
- /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
-
- /* UPM Write Burst RAM array entry -> unused */
- /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Refresh Timer RAM array entry -> unused */
- /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Exception RAM array entry -> unsused */
- /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for bus clock = 133.3 MHz */
-static const uint upmTable133[] =
-{
- /* Offset UPM Read Single RAM array entry -> NAND Read Data */
- /* 0x00 */ 0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
- /* 0x04 */ 0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> unused */
- /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> unused */
- /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
- /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00,
- /* 0x1C */ 0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
-
- /* UPM Write Burst RAM array entry -> unused */
- /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Refresh Timer RAM array entry -> unused */
- /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Exception RAM array entry -> unsused */
- /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-static int chipsel = 0;
-
-#if defined(CONFIG_CMD_NAND)
-
-#include <nand.h>
-#include <linux/mtd/mtd.h>
-
-static u8 hwctl = 0;
-
-static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte)
-{
- struct nand_chip *this = mtdinfo->priv;
- ulong base = (ulong) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST);
-
- if (hwctl & 0x1) {
- WRITE_NAND_UPM(byte, base, CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS);
- } else if (hwctl & 0x2) {
- WRITE_NAND_UPM(byte, base, CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS);
- } else {
- WRITE_NAND(byte, base);
- }
-}
-
-static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- if (ctrl & NAND_CTRL_CHANGE) {
- if ( ctrl & NAND_CLE )
- hwctl |= 0x1;
- else
- hwctl &= ~0x1;
- if ( ctrl & NAND_ALE )
- hwctl |= 0x2;
- else
- hwctl &= ~0x2;
- }
- if (cmd != NAND_CMD_NONE)
- upmnand_write_byte (mtd, cmd);
-}
-
-static u_char upmnand_read_byte(struct mtd_info *mtdinfo)
-{
- struct nand_chip *this = mtdinfo->priv;
- ulong base = (ulong) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST);
-
- return READ_NAND(base);
-}
-
-static int tqm8272_dev_ready(struct mtd_info *mtdinfo)
-{
- /* constant delay (see also tR in the datasheet) */
- udelay(12); \
- return 1;
-}
-
-#ifndef CONFIG_NAND_SPL
-static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
-{
- struct nand_chip *this = mtdinfo->priv;
- unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST);
- int i;
-
- for (i = 0; i< len; i++)
- buf[i] = *base;
-}
-
-static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
-{
- struct nand_chip *this = mtdinfo->priv;
- unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST);
- int i;
-
- for (i = 0; i< len; i++)
- *base = buf[i];
-}
-
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
-static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
-{
- struct nand_chip *this = mtdinfo->priv;
- unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST);
- int i;
-
- for (i = 0; i < len; i++)
- if (buf[i] != *base)
- return -1;
- return 0;
-}
-#endif
-#endif /* #ifndef CONFIG_NAND_SPL */
-
-void board_nand_select_device(struct nand_chip *nand, int chip)
-{
- chipsel = chip;
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
- static int UpmInit = 0;
- volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immr->im_memctl;
-
- if (hwinf.nand == 0) return -1;
-
- /* Setup the UPM */
- if (UpmInit == 0) {
- switch (hwinf.busclk_real) {
- case 100000000:
- upmconfig (UPMB, (uint *) upmTable100,
- sizeof (upmTable100) / sizeof (uint));
- break;
- case 133333333:
- upmconfig (UPMB, (uint *) upmTable133,
- sizeof (upmTable133) / sizeof (uint));
- break;
- default:
- upmconfig (UPMB, (uint *) upmTable67,
- sizeof (upmTable67) / sizeof (uint));
- break;
- }
- UpmInit = 1;
- }
-
- /* Setup the memctrl */
- memctl->memc_or3 = CONFIG_SYS_NAND_OR;
- memctl->memc_br3 = CONFIG_SYS_NAND_BR;
- memctl->memc_mbmr = (MxMR_OP_NORM);
-
- nand->ecc.mode = NAND_ECC_SOFT;
-
- nand->cmd_ctrl = upmnand_hwcontrol;
- nand->read_byte = upmnand_read_byte;
- nand->dev_ready = tqm8272_dev_ready;
-
-#ifndef CONFIG_NAND_SPL
- nand->write_buf = tqm8272_write_buf;
- nand->read_buf = tqm8272_read_buf;
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
- nand->verify_buf = tqm8272_verify_buf;
-#endif
-#endif
-
- /*
- * Select required NAND chip
- */
- board_nand_select_device(nand, 0);
- return 0;
-}
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-
-#include <command.h>
-#include <netdev.h>
-#ifdef CONFIG_PCI
-#include <pci.h>
-#include <asm/m8260_pci.h>
-#endif
-#include "tqm8272.h"
-
-#if 0
-#define deb_printf(fmt,arg...) \
- printf ("TQM8272 %s %s: " fmt,__FILE__, __FUNCTION__, ##arg)
-#else
-#define deb_printf(fmt,arg...) \
- do { } while (0)
-#endif
-
-#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
-unsigned long board_get_cpu_clk_f (void);
-#endif
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */
- /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */
- /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */
- /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */
- /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */
- /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */
- /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
- /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
- /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
- /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
- /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
- /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
- /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
- /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
- /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */
- /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */
- /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */
- /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */
- /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */
- /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */
- /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */
- /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */
- /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
- /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
- /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
- /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
- /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
- /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
- /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
- /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
- /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
- /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
- /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
- /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
- /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
- /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
- /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
- /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
- /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
- /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
- /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
- /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
- /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
- /* PC17 */ { 1, 0, 0, 1, 0, 0 }, /* PC17 MDC */
- /* PC16 */ { 1, 0, 0, 0, 0, 0 }, /* PC16 MDIO*/
- /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
- /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
- /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
- /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* PC10 */
- /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* PC9 */
- /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
- /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* PC5 SMC1 TXD */
- /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* PC4 SMC1 RXD */
- /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
- /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
- /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
- /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
- /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
- /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
- /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
-#if defined(CONFIG_SYS_I2C_SOFT)
- /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
- /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
-#else
-#if defined(CONFIG_HARD_I2C)
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
-#else /* normal I/O port pins */
- /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
-#endif
-#endif
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-/* UPM pattern for slow init */
-static const uint upmTableSlow[] =
-{
- /* Offset UPM Read Single RAM array entry */
- /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcf00, 0x00ffdc00,
- /* 0x04 */ 0x00ffce80, 0x00ffcc00, 0x00ffee00, 0x3fffcc07,
-
- /* UPM Read Burst RAM array entry -> unused */
- /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> unused */
- /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Write Single RAM array entry */
- /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffef00, 0x00fffc80,
- /* 0x1C */ 0x00fffe00, 0x00ffec00, 0x0fffef00, 0x3fffec05,
-
- /* UPM Write Burst RAM array entry -> unused */
- /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Refresh Timer RAM array entry -> unused */
- /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Exception RAM array entry -> unused */
- /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for fast init */
-static const uint upmTableFast[] =
-{
- /* Offset UPM Read Single RAM array entry */
- /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcd80, 0x00ffdc00,
- /* 0x04 */ 0x00ffdc00, 0x00ffcf00, 0x00ffec00, 0x3fffcc07,
-
- /* UPM Read Burst RAM array entry -> unused */
- /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Read Burst RAM array entry -> unused */
- /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
- /* UPM Write Single RAM array entry */
- /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffee80, 0x00fffc00,
- /* 0x1C */ 0x00fffc00, 0x00ffec00, 0x0fffef00, 0x3fffec05,
-
- /* UPM Write Burst RAM array entry -> unused */
- /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Refresh Timer RAM array entry -> unused */
- /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
- /* UPM Exception RAM array entry -> unused */
- /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-
-/* ------------------------------------------------------------------------- */
-
-/* Check Board Identity:
- */
-int checkboard (void)
-{
- char *p = (char *) HWIB_INFO_START_ADDR;
-
- puts ("Board: ");
- if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) {
- puts (p);
- } else {
- puts ("No HWIB assuming TQM8272");
- }
- putc ('\n');
-
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
-static int get_cas_latency (void)
-{
- /* get it from the option -ts in CIB */
- /* default is 3 */
- int ret = 3;
- int pos = 0;
- char *p = (char *) CIB_INFO_START_ADDR;
-
- while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
- if (*p < ' ' || *p > '~') { /* ASCII strings! */
- return ret;
- }
- if (*p == '-') {
- if ((p[1] == 't') && (p[2] == 's')) {
- return (p[4] - '0');
- }
- }
- p++;
- pos++;
- }
- return ret;
-}
-#endif
-
-static ulong set_sdram_timing (volatile uint *sdmr_ptr, ulong sdmr, int col)
-{
-#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
- int clk = board_get_cpu_clk_f ();
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- int busmode = (immr->im_siu_conf.sc_bcr & BCR_EBM ? 1 : 0);
- int cas;
-
- sdmr = sdmr & ~(PSDMR_RFRC_MSK | PSDMR_PRETOACT_MSK | PSDMR_WRC_MSK | \
- PSDMR_BUFCMD);
- if (busmode) {
- switch (clk) {
- case 66666666:
- sdmr |= (PSDMR_RFRC_66MHZ_60X | \
- PSDMR_PRETOACT_66MHZ_60X | \
- PSDMR_WRC_66MHZ_60X | \
- PSDMR_BUFCMD_66MHZ_60X);
- break;
- case 100000000:
- sdmr |= (PSDMR_RFRC_100MHZ_60X | \
- PSDMR_PRETOACT_100MHZ_60X | \
- PSDMR_WRC_100MHZ_60X | \
- PSDMR_BUFCMD_100MHZ_60X);
- break;
-
- }
- } else {
- switch (clk) {
- case 66666666:
- sdmr |= (PSDMR_RFRC_66MHZ_SINGLE | \
- PSDMR_PRETOACT_66MHZ_SINGLE | \
- PSDMR_WRC_66MHZ_SINGLE | \
- PSDMR_BUFCMD_66MHZ_SINGLE);
- break;
- case 100000000:
- sdmr |= (PSDMR_RFRC_100MHZ_SINGLE | \
- PSDMR_PRETOACT_100MHZ_SINGLE | \
- PSDMR_WRC_100MHZ_SINGLE | \
- PSDMR_BUFCMD_100MHZ_SINGLE);
- break;
- case 133333333:
- sdmr |= (PSDMR_RFRC_133MHZ_SINGLE | \
- PSDMR_PRETOACT_133MHZ_SINGLE | \
- PSDMR_WRC_133MHZ_SINGLE | \
- PSDMR_BUFCMD_133MHZ_SINGLE);
- break;
- }
- }
- cas = get_cas_latency();
- sdmr &=~ (PSDMR_CL_MSK | PSDMR_LDOTOPRE_MSK);
- sdmr |= cas;
- sdmr |= ((cas - 1) << 6);
- return sdmr;
-#else
- return sdmr;
-#endif
-}
-
-/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
- *
- * This routine performs standard 8260 initialization sequence
- * and calculates the available memory size. It may be called
- * several times to try different SDRAM configurations on both
- * 60x and local buses.
- */
-static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
- ulong orx, volatile uchar * base, int col)
-{
- volatile uchar c = 0xff;
- volatile uint *sdmr_ptr;
- volatile uint *orx_ptr;
- ulong maxsize, size;
- int i;
-
- /* We must be able to test a location outsize the maximum legal size
- * to find out THAT we are outside; but this address still has to be
- * mapped by the controller. That means, that the initial mapping has
- * to be (at least) twice as large as the maximum expected size.
- */
- maxsize = (1 + (~orx | 0x7fff)) / 2;
-
- /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
- * we are configuring CS1 if base != 0
- */
- sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
- orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
-
- *orx_ptr = orx;
- sdmr = set_sdram_timing (sdmr_ptr, sdmr, col);
- /*
- * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
- *
- * "At system reset, initialization software must set up the
- * programmable parameters in the memory controller banks registers
- * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
- * system software should execute the following initialization sequence
- * for each SDRAM device.
- *
- * 1. Issue a PRECHARGE-ALL-BANKS command
- * 2. Issue eight CBR REFRESH commands
- * 3. Issue a MODE-SET command to initialize the mode register
- *
- * The initial commands are executed by setting P/LSDMR[OP] and
- * accessing the SDRAM with a single-byte transaction."
- *
- * The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
- */
-
- *sdmr_ptr = sdmr | PSDMR_OP_PREA;
- *base = c;
-
- *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
- *base = c;
-
- *sdmr_ptr = sdmr | PSDMR_OP_MRW;
- *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
-
- *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
- *base = c;
-
- size = get_ram_size((long *)base, maxsize);
- *orx_ptr = orx | ~(size - 1);
-
- return (size);
-}
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
-
-#ifndef CONFIG_SYS_RAMBOOT
- long size8, size9;
-#endif
- long psize;
-
- psize = 16 * 1024 * 1024;
-
- memctl->memc_psrt = CONFIG_SYS_PSRT;
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-#ifndef CONFIG_SYS_RAMBOOT
- /* 60x SDRAM setup:
- */
- size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE, 8);
- size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE, 9);
-
- if (size8 < size9) {
- psize = size9;
- printf ("(60x:9COL - %ld MB, ", psize >> 20);
- } else {
- psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
- (uchar *) CONFIG_SYS_SDRAM_BASE, 8);
- printf ("(60x:8COL - %ld MB, ", psize >> 20);
- }
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
- icache_enable ();
-
- return (psize);
-}
-
-
-static inline int scanChar (char *p, int len, unsigned long *number)
-{
- int akt = 0;
-
- *number = 0;
- while (akt < len) {
- if ((*p >= '0') && (*p <= '9')) {
- *number *= 10;
- *number += *p - '0';
- p += 1;
- } else {
- if (*p == '-') return akt;
- return -1;
- }
- akt ++;
- }
- return akt;
-}
-
-static int dump_hwib(void)
-{
- HWIB_INFO *hw = &hwinf;
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-
- if (i < 0)
- buf[0] = '\0';
-
- if (hw->OK) {
- printf ("HWIB on %x\n", HWIB_INFO_START_ADDR);
- printf ("serial : %s\n", buf);
- printf ("ethaddr: %s\n", hw->ethaddr);
- printf ("FLASH : %x nr:%d\n", hw->flash, hw->flash_nr);
- printf ("RAM : %x cs:%d\n", hw->ram, hw->ram_cs);
- printf ("CPU : %lu\n", hw->cpunr);
- printf ("CAN : %d\n", hw->can);
- if (hw->eeprom) printf ("EEprom : %x\n", hw->eeprom);
- else printf ("No EEprom\n");
- if (hw->nand) {
- printf ("NAND : %x\n", hw->nand);
- printf ("NAND CS: %d\n", hw->nand_cs);
- } else { printf ("No NAND\n");}
- printf ("Bus %s mode.\n", (hw->Bus ? "60x" : "Single PQII"));
- printf (" real : %s\n", (immr->im_siu_conf.sc_bcr & BCR_EBM ? \
- "60x" : "Single PQII"));
- printf ("Option : %lx\n", hw->option);
- printf ("%s Security Engine\n", (hw->SecEng ? "with" : "no"));
- printf ("CPM Clk: %d\n", hw->cpmcl);
- printf ("CPU Clk: %d\n", hw->cpucl);
- printf ("Bus Clk: %d\n", hw->buscl);
- if (hw->busclk_real_ok) {
- printf (" real Clk: %d\n", hw->busclk_real);
- }
- printf ("CAS : %d\n", get_cas_latency());
- } else {
- printf("HWIB @%x not OK\n", HWIB_INFO_START_ADDR);
- }
- return 0;
-}
-
-static inline int search_real_busclk (int *clk)
-{
- int part = 0, pos = 0;
- char *p = (char *) CIB_INFO_START_ADDR;
- int ok = 0;
-
- while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
- if (*p < ' ' || *p > '~') { /* ASCII strings! */
- return 0;
- }
- switch (part) {
- default:
- if (*p == '-') {
- ++part;
- }
- break;
- case 3:
- if (*p == '-') {
- ++part;
- break;
- }
- if (*p == 'b') {
- ok = 1;
- p++;
- break;
- }
- if (ok) {
- switch (*p) {
- case '6':
- *clk = 66666666;
- return 1;
- break;
- case '1':
- if (p[1] == '3') {
- *clk = 133333333;
- } else {
- *clk = 100000000;
- }
- return 1;
- break;
- }
- }
- break;
- }
- p++;
- }
- return 0;
-}
-
-int analyse_hwib (void)
-{
- char *p = (char *) HWIB_INFO_START_ADDR;
- int anz;
- int part = 1, i = 0, pos = 0;
- HWIB_INFO *hw = &hwinf;
-
- deb_printf(" %s pointer: %p\n", __FUNCTION__, p);
- /* Head = TQM */
- if (*((unsigned long *)p) != (unsigned long)CONFIG_SYS_HWINFO_MAGIC) {
- deb_printf("No HWIB\n");
- return -1;
- }
- p += 3;
- if (scanChar (p, 4, &hw->cpunr) < 0) {
- deb_printf("No CPU\n");
- return -2;
- }
- p +=4;
-
- hw->flash = 0x200000 << (*p - 'A');
- p++;
- hw->flash_nr = *p - '0';
- p++;
-
- hw->ram = 0x2000000 << (*p - 'A');
- p++;
- if (*p == '2') {
- hw->ram_cs = 2;
- p++;
- }
-
- if (*p == 'A') hw->can = 1;
- if (*p == 'B') hw->can = 2;
- p +=1;
- p +=1; /* connector */
- if (*p != '0') {
- hw->eeprom = 0x1000 << (*p - 'A');
- }
- p++;
-
- if ((*p < '0') || (*p > '9')) {
- /* NAND before z-option */
- hw->nand = 0x8000000 << (*p - 'A');
- p++;
- hw->nand_cs = *p - '0';
- p += 2;
- }
- /* z-option */
- anz = scanChar (p, 4, &hw->option);
- if (anz < 0) {
- deb_printf("No option\n");
- return -3;
- }
- if (hw->option & 0x8) hw->Bus = 1;
- p += anz;
- if (*p != '-') {
- deb_printf("No -\n");
- return -4;
- }
- p++;
- /* C option */
- if (*p == 'E') {
- hw->SecEng = 1;
- p++;
- }
- switch (*p) {
- case 'M': hw->cpucl = 266666666;
- break;
- case 'P': hw->cpucl = 300000000;
- break;
- case 'T': hw->cpucl = 400000000;
- break;
- default:
- deb_printf("No CPU Clk: %c\n", *p);
- return -5;
- break;
- }
- p++;
- switch (*p) {
- case 'I': hw->cpmcl = 200000000;
- break;
- case 'M': hw->cpmcl = 300000000;
- break;
- default:
- deb_printf("No CPM Clk\n");
- return -6;
- break;
- }
- p++;
- switch (*p) {
- case 'B': hw->buscl = 66666666;
- break;
- case 'E': hw->buscl = 100000000;
- break;
- case 'F': hw->buscl = 133333333;
- break;
- default:
- deb_printf("No BUS Clk\n");
- return -7;
- break;
- }
- p++;
-
- hw->OK = 1;
- /* search MAC Address */
- while ((*p != '\0') && (pos < CONFIG_SYS_HWINFO_SIZE)) {
- if (*p < ' ' || *p > '~') { /* ASCII strings! */
- return 0;
- }
- switch (part) {
- default:
- if (*p == ' ') {
- ++part;
- i = 0;
- }
- break;
- case 3: /* Copy MAC address */
- if (*p == ' ') {
- ++part;
- i = 0;
- break;
- }
- hw->ethaddr[i++] = *p;
- if ((i % 3) == 2)
- hw->ethaddr[i++] = ':';
- break;
-
- }
- p++;
- }
-
- hw->busclk_real_ok = search_real_busclk (&hw->busclk_real);
- return 0;
-}
-
-#if defined(CONFIG_GET_CPU_STR_F)
-/* !! This routine runs from Flash */
-char get_cpu_str_f (char *buf)
-{
- char *p = (char *) HWIB_INFO_START_ADDR;
- int i = 0;
-
- buf[i++] = 'M';
- buf[i++] = 'P';
- buf[i++] = 'C';
- if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) {
- buf[i++] = *&p[3];
- buf[i++] = *&p[4];
- buf[i++] = *&p[5];
- buf[i++] = *&p[6];
- } else {
- buf[i++] = '8';
- buf[i++] = '2';
- buf[i++] = '7';
- buf[i++] = 'x';
- }
- buf[i++] = 0;
- return 0;
-}
-#endif
-
-#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
-/* !! This routine runs from Flash */
-unsigned long board_get_cpu_clk_f (void)
-{
- char *p = (char *) HWIB_INFO_START_ADDR;
- int i = 0;
-
- if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) {
- if (search_real_busclk (&i))
- return i;
- }
- return CONFIG_8260_CLKIN;
-}
-#endif
-
-#if CONFIG_BOARD_EARLY_INIT_R
-
-static int can_test (unsigned long off)
-{
- volatile unsigned char *base = (unsigned char *) (CONFIG_SYS_CAN_BASE + off);
-
- *(base + 0x17) = 'T';
- *(base + 0x18) = 'Q';
- *(base + 0x19) = 'M';
- if ((*(base + 0x17) != 'T') ||
- (*(base + 0x18) != 'Q') ||
- (*(base + 0x19) != 'M')) {
- return 0;
- }
- return 1;
-}
-
-static int can_config_one (unsigned long off)
-{
- volatile unsigned char *ctrl = (unsigned char *) (CONFIG_SYS_CAN_BASE + off);
- volatile unsigned char *cpu_if = (unsigned char *) (CONFIG_SYS_CAN_BASE + off + 0x02);
- volatile unsigned char *clkout = (unsigned char *) (CONFIG_SYS_CAN_BASE + off + 0x1f);
- unsigned char temp;
-
- *cpu_if = 0x45;
- temp = *ctrl;
- temp |= 0x40;
- *ctrl = temp;
- *clkout = 0x20;
- temp = *ctrl;
- temp &= ~0x40;
- *ctrl = temp;
- return 0;
-}
-
-static int can_config (void)
-{
- int ret = 0;
- can_config_one (0);
- if (hwinf.can == 2) {
- can_config_one (0x100);
- }
- /* make Test if they really there */
- ret += can_test (0);
- ret += can_test (0x100);
- return ret;
-}
-
-static int init_can (void)
-{
- volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immr->im_memctl;
- int count = 0;
-
- if ((hwinf.OK) && (hwinf.can)) {
- memctl->memc_or4 = CONFIG_SYS_CAN_OR;
- memctl->memc_br4 = CONFIG_SYS_CAN_BR;
- /* upm Init */
- upmconfig (UPMC, (uint *) upmTableFast,
- sizeof (upmTableFast) / sizeof (uint));
- memctl->memc_mcmr = (MxMR_DSx_3_CYCL |
- MxMR_GPL_x4DIS |
- MxMR_RLFx_2X |
- MxMR_WLFx_2X |
- MxMR_OP_NORM);
- /* can configure */
- count = can_config ();
- printf ("CAN: %d @ %x\n", count, CONFIG_SYS_CAN_BASE);
- if (hwinf.can != count) printf("!!! difference to HWIB\n");
- } else {
- printf ("CAN: No\n");
- }
- return 0;
-}
-
-int board_early_init_r(void)
-{
- analyse_hwib ();
- init_can ();
- return 0;
-}
-#endif
-
-int do_hwib_dump (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- dump_hwib ();
- return 0;
-}
-
-U_BOOT_CMD(
- hwib, 1, 1, do_hwib_dump,
- "dump HWIB'",
- ""
-);
-
-#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE
-static int get_flash_timing (void)
-{
- /* get it from the option -tf in CIB */
- /* default is 0x00000c84 */
- int ret = 0x00000c84;
- int pos = 0;
- int nr = 0;
- char *p = (char *) CIB_INFO_START_ADDR;
-
- while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
- if (*p < ' ' || *p > '~') { /* ASCII strings! */
- return ret;
- }
- if (*p == '-') {
- if ((p[1] == 't') && (p[2] == 'f')) {
- p += 6;
- ret = 0;
- while (nr < 8) {
- if ((*p >= '0') && (*p <= '9')) {
- ret *= 0x10;
- ret += *p - '0';
- p += 1;
- nr ++;
- } else if ((*p >= 'A') && (*p <= 'F')) {
- ret *= 10;
- ret += *p - '7';
- p += 1;
- nr ++;
- } else {
- if (nr < 8) return 0x00000c84;
- return ret;
- }
- }
- }
- }
- p++;
- pos++;
- }
- return ret;
-}
-
-/* Update the Flash_Size and the Flash Timing */
-int update_flash_size (int flash_size)
-{
- volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immr->im_memctl;
- unsigned long reg;
- unsigned long tim;
-
- /* I must use reg, otherwise the board hang */
- reg = memctl->memc_or0;
- reg &= ~ORxU_AM_MSK;
- reg |= MEG_TO_AM(flash_size >> 20);
- tim = get_flash_timing ();
- reg &= ~0xfff;
- reg |= (tim & 0xfff);
- memctl->memc_or0 = reg;
- return 0;
-}
-#endif
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-int board_early_init_f (void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
- return 0;
-}
-
-extern void pci_mpc8250_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc8250_init(&hose);
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _TQM8272_HEADER_H
-#define _TQM8272_HEADER_H
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-typedef struct{
- int Bus;
- int flash;
- int flash_nr;
- int ram;
- int ram_cs;
- int nand;
- int nand_cs;
- int eeprom;
- int can;
- unsigned long cpunr;
- unsigned long option;
- int SecEng;
- int cpucl;
- int cpmcl;
- int buscl;
- int busclk_real_ok;
- int busclk_real;
- unsigned char OK;
- unsigned char ethaddr[20];
-} HWIB_INFO;
-
-static HWIB_INFO hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0,
- 0, 0, 0, 0, 0, 0};
-#endif /* __CONFIG_H */
if TARGET_TQMA6
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "tqma6"
NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
};
+#define TQMA6_SF_CS_GPIO IMX_GPIO_NR(3, 19)
+
static unsigned const tqma6_ecspi1_cs[] = {
- IMX_GPIO_NR(3, 19),
+ TQMA6_SF_CS_GPIO,
};
static void tqma6_iomuxc_spi(void)
ARRAY_SIZE(tqma6_ecspi1_pads));
}
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return ((bus == CONFIG_SF_DEFAULT_BUS) &&
+ (cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1;
+}
+
static struct i2c_pads_info tqma6_i2c3_pads = {
/* I2C3: on board LM75, M24C64, */
.scl = {
*/
#ifndef __TQMA6_BB__
-#define __TQMA6_BB
+#define __TQMA6_BB__
#include <common.h>
if TARGET_TRIZEPSIV
-config SYS_CPU
- default "pxa"
-
config SYS_BOARD
default "trizepsiv"
if TARGET_VISION2
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "vision2"
#include <asm/arch/iomux-mx51.h>
#include <asm/gpio.h>
#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/spi.h>
#include <i2c.h>
#include <mmc.h>
#include <power/pmic.h>
if TARGET_UDOO
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "udoo"
if TARGET_VPAC270
-config SYS_CPU
- default "pxa"
-
config SYS_BOARD
default "vpac270"
#include <common.h>
#include <config.h>
#include <command.h>
+#include <elf.h>
/*
* FIXME: Add code to test image and it's header.
*/
-extern int valid_elf_image (unsigned long addr);
-
static int
image_check(ulong addr)
{
if TARGET_WANDBOARD
-config SYS_CPU
- default "armv7"
-
config SYS_BOARD
default "wandboard"
if TARGET_WOODBURN
-config SYS_CPU
- default "arm1136"
-
config SYS_BOARD
default "woodburn"
if TARGET_WOODBURN_SD
-config SYS_CPU
- default "arm1136"
-
config SYS_BOARD
default "woodburn"
if TARGET_XAENIAX
-config SYS_CPU
- default "pxa"
-
config SYS_BOARD
default "xaeniax"
if TARGET_ZIPITZ2
-config SYS_CPU
- default "pxa"
-
config SYS_BOARD
default "zipitz2"
obj-$(CONFIG_SPL_ENV_SUPPORT) += env_callback.o
obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
obj-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o
+obj-$(CONFIG_ENV_IS_IN_FAT) += env_fat.o
obj-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
break;
case CHUNK_TYPE_DONT_CARE:
+ blk += blkcnt;
total_blocks += chunk_header->chunk_sz;
break;
}
#endif /* CONFIG_WATCHDOG */
-void __board_add_ram_info(int use_default)
+__weak void board_add_ram_info(int use_default)
{
/* please define platform specific board_add_ram_info() */
}
-void board_add_ram_info(int)
- __attribute__ ((weak, alias("__board_add_ram_info")));
-
static int init_baud_rate(void)
{
gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
return 0;
}
-void __dram_init_banksize(void)
+__weak void dram_init_banksize(void)
{
#if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
#endif
}
-void dram_init_banksize(void)
- __attribute__((weak, alias("__dram_init_banksize")));
-
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
static int init_func_i2c(void)
{
ulong monitor_flash_len;
-int __board_flash_wp_on(void)
+__weak int board_flash_wp_on(void)
{
/*
* Most flashes can't be detected when write protection is enabled,
return 0;
}
-int board_flash_wp_on(void)
- __attribute__ ((weak, alias("__board_flash_wp_on")));
-
-void __cpu_secondary_init_r(void)
+__weak void cpu_secondary_init_r(void)
{
}
-void cpu_secondary_init_r(void)
- __attribute__ ((weak, alias("__cpu_secondary_init_r")));
-
static int initr_secondary_cpu(void)
{
/*
#ifdef CONFIG_CMD_NAND
/* go init the NAND */
-int initr_nand(void)
+static int initr_nand(void)
{
puts("NAND: ");
nand_init();
#if defined(CONFIG_CMD_ONENAND)
/* go init the NAND */
-int initr_onenand(void)
+static int initr_onenand(void)
{
puts("NAND: ");
onenand_init();
#endif
#ifdef CONFIG_GENERIC_MMC
-int initr_mmc(void)
+static int initr_mmc(void)
{
puts("MMC: ");
mmc_initialize(gd->bd);
#endif
#ifdef CONFIG_HAS_DATAFLASH
-int initr_dataflash(void)
+static int initr_dataflash(void)
{
AT91F_DataflashInit();
dataflash_print_info();
images.os.type = IH_TYPE_KERNEL;
images.os.comp = IH_COMP_NONE;
images.os.os = IH_OS_LINUX;
- images.ep = images.os.load;
- ep_found = true;
images.os.end = android_image_get_end(os_hdr);
images.os.load = android_image_get_kload(os_hdr);
+ images.ep = images.os.load;
+ ep_found = true;
break;
#endif
default:
}
/* If we have a valid setup.bin, we will use that for entry (x86) */
- if (images.os.arch == IH_ARCH_I386) {
+ if (images.os.arch == IH_ARCH_I386 ||
+ images.os.arch == IH_ARCH_X86_64) {
ulong len;
ret = boot_get_setup(&images, IH_ARCH_I386, &images.ep, &len);
return 0;
#else
- return parse_string_outer(cmd,
- FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP);
+ int hush_flags = FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP;
+
+ if (flag & CMD_FLAG_ENV)
+ hush_flags |= FLAG_CONT_ON_NEWLINE;
+ return parse_string_outer(cmd, hush_flags);
#endif
}
return 1;
}
- if (run_command(arg, flag) != 0)
+ if (run_command(arg, flag | CMD_FLAG_ENV) != 0)
return 1;
}
return 0;
o_string temp=NULL_O_STRING;
int rcode;
#ifdef __U_BOOT__
- int code = 0;
+ int code = 1;
#endif
do {
ctx.type = flag;
update_ifs_map();
if (!(flag & FLAG_PARSE_SEMICOLON) || (flag & FLAG_REPARSING)) mapset((uchar *)";$&|", 0);
inp->promptmode=1;
- rcode = parse_stream(&temp, &ctx, inp, '\n');
+ rcode = parse_stream(&temp, &ctx, inp,
+ flag & FLAG_CONT_ON_NEWLINE ? -1 : '\n');
#ifdef __U_BOOT__
if (rcode == 1) flag_repeat = 0;
#endif
}
b_free(&temp);
/* loop on syntax errors, return on EOF */
- } while (rcode != -1 && !(flag & FLAG_EXIT_FROM_LOOP) &&
+ } while (rcode != 1 && !(flag & FLAG_EXIT_FROM_LOOP) &&
(inp->peek != static_peek || b_peek(inp)));
#ifndef __U_BOOT__
return 0;
#ifdef __U_BOOT__
char *p = NULL;
int rcode;
- if ( !s || !*s)
+ if (!s)
return 1;
+ if (!*s)
+ return 0;
if (!(p = strchr(s, '\n')) || *++p) {
p = xmalloc(strlen(s) + 2);
strcpy(p, s);
#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
spi_init_f ();
#endif
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT) || \
- defined(CONFIG_SYS_I2C)
-#ifdef CONFIG_SYS_I2C
- i2c_init_all();
-#else
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
+ i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
}
*/
#include <common.h>
+#include <bootm.h>
#include <command.h>
#include <linux/ctype.h>
#include <net.h>
static unsigned long load_elf_image_shdr(unsigned long addr);
/* Allow ports to override the default behavior */
-__attribute__((weak))
-unsigned long do_bootelf_exec(ulong (*entry)(int, char * const[]),
+static unsigned long do_bootelf_exec(ulong (*entry)(int, char * const[]),
int argc, char * const argv[])
{
unsigned long ret;
-de <net.h>
-
-#if !defined(CONFIG_UPDATE_TFTP)
-#error "CONFIG_UPDATE_TFTP required"
-#endif
-
-static int do_fitupd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong addr = 0Un the root directory of the source tree for details.
+/*
+ * (C) Copyright 2011
+ * Andreas Pretzsch, carpe noctem engineering, apr@cn-eng.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <asm/gpio.h>
-int __weak name_to_gpio(const char *name)
+__weak int name_to_gpio(const char *name)
{
return simple_strtoul(name, NULL, 10);
}
};
#if defined(CONFIG_DM_GPIO) && !defined(gpio_status)
-static const char * const gpio_function[GPIOF_COUNT] = {
- "input",
- "output",
- "unused",
- "unknown",
- "func",
-};
/* A few flags used by show_gpio() */
enum {
FLAG_SHOW_NEWLINE = 1 << 2,
};
-static void show_gpio(struct udevice *dev, const char *bank_name, int offset,
- int *flagsp)
+static void gpio_get_description(struct udevice *dev, const char *bank_name,
+ int offset, int *flagsp)
{
- struct dm_gpio_ops *ops = gpio_get_ops(dev);
- int func = GPIOF_UNKNOWN;
char buf[80];
int ret;
- BUILD_BUG_ON(GPIOF_COUNT != ARRAY_SIZE(gpio_function));
-
- if (ops->get_function) {
- ret = ops->get_function(dev, offset);
- if (ret >= 0 && ret < ARRAY_SIZE(gpio_function))
- func = ret;
- }
- if (!(*flagsp & FLAG_SHOW_ALL) && func == GPIOF_UNUSED)
+ ret = gpio_get_function(dev, offset, NULL);
+ if (ret < 0)
+ goto err;
+ if (!(*flagsp & FLAG_SHOW_ALL) && ret == GPIOF_UNUSED)
return;
if ((*flagsp & FLAG_SHOW_BANK) && bank_name) {
if (*flagsp & FLAG_SHOW_NEWLINE) {
printf("Bank %s:\n", bank_name);
*flagsp &= ~FLAG_SHOW_BANK;
}
- *buf = '\0';
- if (ops->get_state) {
- ret = ops->get_state(dev, offset, buf, sizeof(buf));
- if (ret) {
- puts("<unknown>");
- return;
- }
- } else {
- sprintf(buf, "%s%u: %8s %d", bank_name, offset,
- gpio_function[func], ops->get_value(dev, offset));
- }
- puts(buf);
- puts("\n");
+ ret = gpio_get_status(dev, offset, buf, sizeof(buf));
+ if (ret)
+ goto err;
+
+ printf("%s\n", buf);
+ return;
+err:
+ printf("Error %d\n", ret);
}
static int do_gpio_status(bool all, const char *gpio_name)
if (all)
flags |= FLAG_SHOW_ALL;
bank_name = gpio_get_bank_info(dev, &num_bits);
- if (!num_bits)
+ if (!num_bits) {
+ debug("GPIO device %s has no bits\n", dev->name);
continue;
+ }
banklen = bank_name ? strlen(bank_name) : 0;
if (!gpio_name || !bank_name ||
p = gpio_name + banklen;
if (gpio_name && *p) {
offset = simple_strtoul(p, NULL, 10);
- show_gpio(dev, bank_name, offset, &flags);
+ gpio_get_description(dev, bank_name, offset,
+ &flags);
} else {
for (offset = 0; offset < num_bits; offset++) {
- show_gpio(dev, bank_name, offset,
- &flags);
+ gpio_get_description(dev, bank_name,
+ offset, &flags);
}
}
}
/**************************************************/
U_BOOT_CMD(iod, 2, 0, do_io_iod,
- "IO space display", "[.b, .w, .l] address [# of objects]");
+ "IO space display", "[.b, .w, .l] address");
U_BOOT_CMD(iow, 3, 0, do_io_iow,
- "IO space modify (auto-incrementing address)",
- "[.b, .w, .l] address");
+ "IO space modify",
+ "[.b, .w, .l] address value");
if ((count % (64 << 10)) == 0)
WATCHDOG_RESET();
}
+ unmap_sysmem(buf);
+ unmap_sysmem(src);
+
return 0;
}
*/
#include <common.h>
#include <command.h>
+#include <inttypes.h>
#include <asm/processor.h>
#include <scsi.h>
#include <image.h>
blks=0;
}
debug("scsi_read_ext: startblk " LBAF
- ", blccnt %x buffer %lx\n",
+ ", blccnt %x buffer %" PRIXPTR "\n",
start, smallblks, buf_addr);
if (scsi_exec(pccb) != true) {
scsi_print_error(pccb);
buf_addr+=pccb->datalen;
} while(blks!=0);
debug("scsi_read_ext: end startblk " LBAF
- ", blccnt %x buffer %lx\n", start, smallblks, buf_addr);
+ ", blccnt %x buffer %" PRIXPTR "\n", start, smallblks, buf_addr);
return(blkcnt);
}
start += blks;
blks = 0;
}
- debug("%s: startblk " LBAF ", blccnt %x buffer %lx\n",
+ debug("%s: startblk " LBAF ", blccnt %x buffer %" PRIXPTR "\n",
__func__, start, smallblks, buf_addr);
if (scsi_exec(pccb) != true) {
scsi_print_error(pccb);
}
buf_addr += pccb->datalen;
} while (blks != 0);
- debug("%s: end startblk " LBAF ", blccnt %x buffer %lx\n",
+ debug("%s: end startblk " LBAF ", blccnt %x buffer %" PRIXPTR "\n",
__func__, start, smallblks, buf_addr);
return blkcnt;
}
* for long help messages
*/
-int _do_help (cmd_tbl_t *cmd_start, int cmd_items, cmd_tbl_t * cmdtp, int
- flag, int argc, char * const argv[])
+int _do_help(cmd_tbl_t *cmd_start, int cmd_items, cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
{
int i;
int rcode = 0;
- if (argc == 1) { /*show list of commands */
+ if (argc == 1) { /* show list of commands */
cmd_tbl_t *cmd_array[cmd_items];
int i, j, swaps;
for (i = cmd_items - 1; i > 0; --i) {
swaps = 0;
for (j = 0; j < i; ++j) {
- if (strcmp (cmd_array[j]->name,
- cmd_array[j + 1]->name) > 0) {
+ if (strcmp(cmd_array[j]->name,
+ cmd_array[j + 1]->name) > 0) {
cmd_tbl_t *tmp;
tmp = cmd_array[j];
cmd_array[j] = cmd_array[j + 1];
const char *usage = cmd_array[i]->usage;
/* allow user abort */
- if (ctrlc ())
+ if (ctrlc())
return 1;
if (usage == NULL)
continue;
* command help (long version)
*/
for (i = 1; i < argc; ++i) {
- if ((cmdtp = find_cmd_tbl (argv[i], cmd_start, cmd_items )) != NULL) {
+ cmdtp = find_cmd_tbl(argv[i], cmd_start, cmd_items);
+ if (cmdtp != NULL) {
rcode |= cmd_usage(cmdtp);
} else {
- printf ("Unknown command '%s' - try 'help'"
- " without arguments for list of all"
- " known commands\n\n", argv[i]
- );
+ printf("Unknown command '%s' - try 'help' without arguments for list of all known commands\n\n",
+ argv[i]);
rcode = 1;
}
}
return rcode;
}
-/***************************************************************************
- * find command table entry for a command
- */
-cmd_tbl_t *find_cmd_tbl (const char *cmd, cmd_tbl_t *table, int table_len)
+/* find command table entry for a command */
+cmd_tbl_t *find_cmd_tbl(const char *cmd, cmd_tbl_t *table, int table_len)
{
cmd_tbl_t *cmdtp;
- cmd_tbl_t *cmdtp_temp = table; /*Init value */
+ cmd_tbl_t *cmdtp_temp = table; /* Init value */
const char *p;
int len;
int n_found = 0;
*/
len = ((p = strchr(cmd, '.')) == NULL) ? strlen (cmd) : (p - cmd);
- for (cmdtp = table;
- cmdtp != table + table_len;
- cmdtp++) {
- if (strncmp (cmd, cmdtp->name, len) == 0) {
- if (len == strlen (cmdtp->name))
+ for (cmdtp = table; cmdtp != table + table_len; cmdtp++) {
+ if (strncmp(cmd, cmdtp->name, len) == 0) {
+ if (len == strlen(cmdtp->name))
return cmdtp; /* full match */
cmdtp_temp = cmdtp; /* abbreviated command ? */
return NULL; /* not found or ambiguous command */
}
-cmd_tbl_t *find_cmd (const char *cmd)
+cmd_tbl_t *find_cmd(const char *cmd)
{
cmd_tbl_t *start = ll_entry_start(cmd_tbl_t, cmd);
const int len = ll_entry_count(cmd_tbl_t, cmd);
return 1;
}
- puts (cmdtp->help);
- putc ('\n');
+ puts(cmdtp->help);
+ putc('\n');
#endif /* CONFIG_SYS_LONGHELP */
return 1;
}
}
/* more than one arg or one but the start of the next */
- if (argc > 1 || (last_char == '\0' || isblank(last_char))) {
+ if (argc > 1 || last_char == '\0' || isblank(last_char)) {
cmdtp = find_cmd(argv[0]);
if (cmdtp == NULL || cmdtp->complete == NULL) {
cmdv[0] = NULL;
argc = make_argv(tmp_buf, sizeof(argv)/sizeof(argv[0]), argv);
/* do the completion and return the possible completions */
- i = complete_cmdv(argc, argv, last_char, sizeof(cmdv)/sizeof(cmdv[0]), cmdv);
+ i = complete_cmdv(argc, argv, last_char,
+ sizeof(cmdv) / sizeof(cmdv[0]), cmdv);
/* no match; bell and out */
if (i == 0) {
len = strlen(s);
sep = " ";
seplen = 1;
- } else if (i > 1 && (j = find_common_prefix(cmdv)) != 0) { /* more */
+ } else if (i > 1 && (j = find_common_prefix(cmdv)) != 0) { /* more */
k = strlen(argv[argc - 1]);
j -= k;
if (j > 0) {
*/
int len = strlen(arg);
if (len > 2 && arg[len-2] == '.') {
- switch(arg[len-1]) {
+ switch (arg[len-1]) {
case 'b':
return 1;
case 'w':
for (i = 0; i < size; i++) {
ulong addr;
- addr = (ulong) (cmdtp->cmd) + gd->reloc_off;
+ addr = (ulong)(cmdtp->cmd) + gd->reloc_off;
#if DEBUG_COMMANDS
printf("Command \"%s\": 0x%08lx => 0x%08lx\n",
- cmdtp->name, (ulong) (cmdtp->cmd), addr);
+ cmdtp->name, (ulong)(cmdtp->cmd), addr);
#endif
cmdtp->cmd =
(int (*)(struct cmd_tbl_s *, int, int, char * const []))addr;
#include <common.h>
#include <stdarg.h>
+#include <iomux.h>
#include <malloc.h>
#include <os.h>
#include <serial.h>
}
#else
-inline void dbg(const char *fmt, ...)
+static inline void dbg(const char *fmt, ...)
{
}
#endif
INTERNAL_SIZE_T nb;
#ifdef CONFIG_SYS_MALLOC_F_LEN
- if (!(gd->flags & GD_FLG_RELOC)) {
+ if (gd && !(gd->flags & GD_FLG_RELOC)) {
ulong new_ptr;
void *ptr;
* The legacy NAND code saved the environment in the first NAND device i.e.,
* nand_dev_desc + 0. This is also the behaviour using the new NAND code.
*/
-int writeenv(size_t offset, u_char *buf)
+static int writeenv(size_t offset, u_char *buf)
{
size_t end = offset + CONFIG_ENV_RANGE;
size_t amount_saved = 0;
}
#endif /* CMD_SAVEENV */
-int readenv(size_t offset, u_char *buf)
+static int readenv(size_t offset, u_char *buf)
{
size_t end = offset + CONFIG_ENV_RANGE;
size_t amount_loaded = 0;
#include <common.h>
#include <image.h>
#include <android_image.h>
+#include <malloc.h>
+#include <errno.h>
static char andr_tmp_str[ANDR_BOOT_ARGS_SIZE + 1];
+/**
+ * android_image_get_kernel() - processes kernel part of Android boot images
+ * @hdr: Pointer to image header, which is at the start
+ * of the image.
+ * @verify: Checksum verification flag. Currently unimplemented.
+ * @os_data: Pointer to a ulong variable, will hold os data start
+ * address.
+ * @os_len: Pointer to a ulong variable, will hold os data length.
+ *
+ * This function returns the os image's start address and length. Also,
+ * it appends the kernel command line to the bootargs env variable.
+ *
+ * Return: Zero, os start address and length on success,
+ * otherwise on failure.
+ */
int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify,
ulong *os_data, ulong *os_len)
{
printf("Kernel load addr 0x%08x size %u KiB\n",
hdr->kernel_addr, DIV_ROUND_UP(hdr->kernel_size, 1024));
- strncpy(andr_tmp_str, hdr->cmdline, ANDR_BOOT_ARGS_SIZE);
- andr_tmp_str[ANDR_BOOT_ARGS_SIZE] = '\0';
- if (strlen(andr_tmp_str)) {
- printf("Kernel command line: %s\n", andr_tmp_str);
- setenv("bootargs", andr_tmp_str);
+
+ int len = 0;
+ if (*hdr->cmdline) {
+ printf("Kernel command line: %s\n", hdr->cmdline);
+ len += strlen(hdr->cmdline);
+ }
+
+ char *bootargs = getenv("bootargs");
+ if (bootargs)
+ len += strlen(bootargs);
+
+ char *newbootargs = malloc(len + 2);
+ if (!newbootargs) {
+ puts("Error: malloc in android_image_get_kernel failed!\n");
+ return -ENOMEM;
+ }
+ *newbootargs = '\0';
+
+ if (bootargs) {
+ strcpy(newbootargs, bootargs);
+ strcat(newbootargs, " ");
}
- if (hdr->ramdisk_size)
- printf("RAM disk load addr 0x%08x size %u KiB\n",
- hdr->ramdisk_addr,
- DIV_ROUND_UP(hdr->ramdisk_size, 1024));
+ if (*hdr->cmdline)
+ strcat(newbootargs, hdr->cmdline);
+
+ setenv("bootargs", newbootargs);
if (os_data) {
*os_data = (ulong)hdr;
ulong android_image_get_end(const struct andr_img_hdr *hdr)
{
- u32 size = 0;
+ ulong end;
/*
* The header takes a full page, the remaining components are aligned
* on page boundary
*/
- size += hdr->page_size;
- size += ALIGN(hdr->kernel_size, hdr->page_size);
- size += ALIGN(hdr->ramdisk_size, hdr->page_size);
- size += ALIGN(hdr->second_size, hdr->page_size);
+ end = (ulong)hdr;
+ end += hdr->page_size;
+ end += ALIGN(hdr->kernel_size, hdr->page_size);
+ end += ALIGN(hdr->ramdisk_size, hdr->page_size);
+ end += ALIGN(hdr->second_size, hdr->page_size);
- return size;
+ return end;
}
ulong android_image_get_kload(const struct andr_img_hdr *hdr)
{
if (!hdr->ramdisk_size)
return -1;
+
+ printf("RAM disk load addr 0x%08x size %u KiB\n",
+ hdr->ramdisk_addr, DIV_ROUND_UP(hdr->ramdisk_size, 1024));
+
*rd_data = (unsigned long)hdr;
*rd_data += hdr->page_size;
*rd_data += ALIGN(hdr->kernel_size, hdr->page_size);
}
} else {
debug("## No Flattened Device Tree\n");
- return 0;
+ goto error;
}
} else {
debug("## No Flattened Device Tree\n");
- return 0;
+ goto error;
}
*of_flat_tree = fdt_blob;
if (fit_image_get_arch(fit, noffset, &image_arch))
return 0;
- return (arch == image_arch);
+ return (arch == image_arch) ||
+ (arch == IH_ARCH_I386 && image_arch == IH_ARCH_X86_64);
}
/**
printf("%s FDT: %s\n", p, uname);
}
-int fit_image_select(const void *fit, int rd_noffset, int verify)
+static int fit_image_select(const void *fit, int rd_noffset, int verify)
{
fit_image_print(fit, rd_noffset, " ");
{ IH_ARCH_SANDBOX, "sandbox", "Sandbox", },
{ IH_ARCH_ARM64, "arm64", "AArch64", },
{ IH_ARCH_ARC, "arc", "ARC", },
+ { IH_ARCH_X86_64, "x86_64", "AMD x86_64", },
{ -1, "", "", },
};
image_multi_getimg(images->legacy_hdr_os, 1, &rd_data, &rd_len);
}
#ifdef CONFIG_ANDROID_BOOT_IMAGE
- else if ((genimg_get_format(images) == IMAGE_FORMAT_ANDROID) &&
+ else if ((genimg_get_format((void *)images->os.start)
+ == IMAGE_FORMAT_ANDROID) &&
(!android_image_get_ramdisk((void *)images->os.start,
&rd_data, &rd_len))) {
/* empty */
#if defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
defined(CONFIG_CPU_MONAHANS)
-#define CONFIG_CPU_PXA
#include <asm/byteorder.h>
#endif
return NULL;
}
-void __menu_display_statusline(struct menu *m)
+__weak void menu_display_statusline(struct menu *m)
{
- return;
}
-void menu_display_statusline(struct menu *m)
- __attribute__ ((weak, alias("__menu_display_statusline")));
/*
* Display a menu so the user can make a choice of an item. First display its
for(;;) {
c = serial_getc();
- /* dbg("(%c)", c); */
+ debug("(%c)", c);
switch(c) {
case '\r':
}
}
-extern void dbg(const char *fmt, ...);
int mdm_init (void)
{
char env_str[16];
serial_puts("\n");
for(;;) {
mdm_readline(console_buffer, CONFIG_SYS_CBSIZE);
- dbg("ini%d: [%s]", i, console_buffer);
+ debug("ini%d: [%s]", i, console_buffer);
if ((strcmp(console_buffer, "OK") == 0) ||
(strcmp(console_buffer, "ERROR") == 0)) {
- dbg("ini%d: cmd done", i);
+ debug("ini%d: cmd done", i);
break;
} else /* in case we are originating call ... */
if (strncmp(console_buffer, "CONNECT", 7) == 0) {
- dbg("ini%d: connect", i);
+ debug("ini%d: connect", i);
return 0;
}
}
for(;i > 1;) { /* if 'i' > 1 - wait for connection
message from modem */
mdm_readline(console_buffer, CONFIG_SYS_CBSIZE);
- dbg("ini_f: [%s]", console_buffer);
+ debug("ini_f: [%s]", console_buffer);
if (strncmp(console_buffer, "CONNECT", 7) == 0) {
- dbg("ini_f: connected");
+ debug("ini_f: connected");
return 0;
}
}
obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o
obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o
obj-$(CONFIG_SPL_FAT_SUPPORT) += spl_fat.o
+obj-$(CONFIG_SPL_EXT_SUPPORT) += spl_ext.o
obj-$(CONFIG_SPL_SATA_SUPPORT) += spl_sata.o
endif
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
#endif
#ifndef CONFIG_SYS_MONITOR_LEN
+/* Unknown U-Boot size, let's assume it will not be more than 200 KB */
#define CONFIG_SYS_MONITOR_LEN (200 * 1024)
#endif
/* Signature not found - assume u-boot.bin */
debug("mkimage signature not found - ih_magic = %x\n",
header->ih_magic);
- /* Let's assume U-Boot will not be more than 200 KB */
spl_image.size = CONFIG_SYS_MONITOR_LEN;
spl_image.entry_point = CONFIG_SYS_UBOOT_START;
spl_image.load_addr = CONFIG_SYS_TEXT_BASE;
--- /dev/null
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/u-boot.h>
+#include <ext4fs.h>
+#include <image.h>
+
+#ifdef CONFIG_SPL_EXT_SUPPORT
+int spl_load_image_ext(block_dev_desc_t *block_dev,
+ int partition,
+ const char *filename)
+{
+ s32 err;
+ struct image_header *header;
+ int filelen;
+ disk_partition_t part_info = {};
+
+ header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
+ sizeof(struct image_header));
+
+ if (get_partition_info(block_dev,
+ partition, &part_info)) {
+ printf("spl: no partition table found\n");
+ return -1;
+ }
+
+ ext4fs_set_blk_dev(block_dev, &part_info);
+
+ err = ext4fs_mount(0);
+ if (!err) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+ printf("%s: ext4fs mount err - %d\n", __func__, err);
+#endif
+ goto end;
+ }
+
+ filelen = err = ext4fs_open(filename);
+ if (err < 0) {
+ puts("spl: ext4fs_open failed\n");
+ goto end;
+ }
+ err = ext4fs_read((char *)header, sizeof(struct image_header));
+ if (err <= 0) {
+ puts("spl: ext4fs_read failed\n");
+ goto end;
+ }
+
+ spl_parse_image_header(header);
+
+ err = ext4fs_read((char *)spl_image.load_addr, filelen);
+
+end:
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+ if (err <= 0)
+ printf("%s: error reading image %s, err - %d\n",
+ __func__, filename, err);
+#endif
+
+ return err <= 0;
+}
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_load_image_ext_os(block_dev_desc_t *block_dev, int partition)
+{
+ int err;
+ int filelen;
+ disk_partition_t part_info = {};
+ __maybe_unused char *file;
+
+ if (get_partition_info(block_dev,
+ partition, &part_info)) {
+ printf("spl: no partition table found\n");
+ return -1;
+ }
+
+ ext4fs_set_blk_dev(block_dev, &part_info);
+
+ err = ext4fs_mount(0);
+ if (!err) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+ printf("%s: ext4fs mount err - %d\n", __func__, err);
+#endif
+ return -1;
+ }
+
+#if defined(CONFIG_SPL_ENV_SUPPORT) && defined(CONFIG_SPL_OS_BOOT)
+ file = getenv("falcon_args_file");
+ if (file) {
+ filelen = err = ext4fs_open(file);
+ if (err < 0) {
+ puts("spl: ext4fs_open failed\n");
+ goto defaults;
+ }
+ err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen);
+ if (err <= 0) {
+ printf("spl: error reading image %s, err - %d, falling back to default\n",
+ file, err);
+ goto defaults;
+ }
+ file = getenv("falcon_image_file");
+ if (file) {
+ err = spl_load_image_ext(block_dev, partition, file);
+ if (err != 0) {
+ puts("spl: falling back to default\n");
+ goto defaults;
+ }
+
+ return 0;
+ } else {
+ puts("spl: falcon_image_file not set in environment, falling back to default\n");
+ }
+ } else {
+ puts("spl: falcon_args_file not set in environment, falling back to default\n");
+ }
+
+defaults:
+#endif
+
+ filelen = err = ext4fs_open(CONFIG_SPL_FS_LOAD_ARGS_NAME);
+ if (err < 0)
+ puts("spl: ext4fs_open failed\n");
+
+ err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen);
+ if (err <= 0) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+ printf("%s: error reading image %s, err - %d\n",
+ __func__, CONFIG_SPL_FS_LOAD_ARGS_NAME, err);
+#endif
+ return -1;
+ }
+
+ return spl_load_image_ext(block_dev, partition,
+ CONFIG_SPL_FS_LOAD_KERNEL_NAME);
+}
+#endif
+#endif
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: fat register err - %d\n", __func__, err);
#endif
- hang();
+ return err;
}
fat_registered = 1;
defaults:
#endif
- err = file_fat_read(CONFIG_SPL_FAT_LOAD_ARGS_NAME,
+ err = file_fat_read(CONFIG_SPL_FS_LOAD_ARGS_NAME,
(void *)CONFIG_SYS_SPL_ARGS_ADDR, 0);
if (err <= 0) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: error reading image %s, err - %d\n",
- __func__, CONFIG_SPL_FAT_LOAD_ARGS_NAME, err);
+ __func__, CONFIG_SPL_FS_LOAD_ARGS_NAME, err);
#endif
return -1;
}
return spl_load_image_fat(block_dev, partition,
- CONFIG_SPL_FAT_LOAD_KERNEL_NAME);
+ CONFIG_SPL_FS_LOAD_KERNEL_NAME);
}
#endif
#endif
#endif
err = mmc_load_image_raw(mmc,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
+#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+ } else if (boot_mode == MMCSD_MODE_FS) {
+ debug("boot mode - FS\n");
#ifdef CONFIG_SPL_FAT_SUPPORT
- } else if (boot_mode == MMCSD_MODE_FAT) {
- debug("boot mode - FAT\n");
#ifdef CONFIG_SPL_OS_BOOT
if (spl_start_uboot() || spl_load_image_fat_os(&mmc->block_dev,
- CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION))
+ CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION))
#endif
err = spl_load_image_fat(&mmc->block_dev,
- CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION,
- CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME);
+ CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION,
+ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
+ if(err)
+#endif /* CONFIG_SPL_FAT_SUPPORT */
+ {
+#ifdef CONFIG_SPL_EXT_SUPPORT
+#ifdef CONFIG_SPL_OS_BOOT
+ if (spl_start_uboot() || spl_load_image_ext_os(&mmc->block_dev,
+ CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION))
#endif
+ err = spl_load_image_ext(&mmc->block_dev,
+ CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION,
+ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
+#endif /* CONFIG_SPL_EXT_SUPPORT */
+ }
+#endif /* defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) */
#ifdef CONFIG_SUPPORT_EMMC_BOOT
} else if (boot_mode == MMCSD_MODE_EMMCBOOT) {
/*
#endif
err = spl_load_image_fat(stor_dev,
CONFIG_SYS_SATA_FAT_BOOT_PARTITION,
- CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME);
+ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
if (err) {
puts("Error loading sata device\n");
hang();
#endif
err = spl_load_image_fat(stor_dev,
CONFIG_SYS_USB_FAT_BOOT_PARTITION,
- CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME);
+ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
if (err) {
puts("Error loading USB device\n");
#endif
#ifdef CONFIG_SYS_DEVICE_NULLDEV
-void nulldev_putc(struct stdio_dev *dev, const char c)
+static void nulldev_putc(struct stdio_dev *dev, const char c)
{
/* nulldev is empty! */
}
-void nulldev_puts(struct stdio_dev *dev, const char *s)
+static void nulldev_puts(struct stdio_dev *dev, const char *s)
{
/* nulldev is empty! */
}
-int nulldev_input(struct stdio_dev *dev)
+static int nulldev_input(struct stdio_dev *dev)
{
/* nulldev is empty! */
return 0;
}
#endif
-void stdio_serial_putc(struct stdio_dev *dev, const char c)
+static void stdio_serial_putc(struct stdio_dev *dev, const char c)
{
serial_putc(c);
}
-void stdio_serial_puts(struct stdio_dev *dev, const char *s)
+static void stdio_serial_puts(struct stdio_dev *dev, const char *s)
{
serial_puts(s);
}
-int stdio_serial_getc(struct stdio_dev *dev)
+static int stdio_serial_getc(struct stdio_dev *dev)
{
return serial_getc();
}
-int stdio_serial_tstc(struct stdio_dev *dev)
+static int stdio_serial_tstc(struct stdio_dev *dev)
{
return serial_tstc();
}
}
list_del(&(dev->list));
+ free(dev);
/* reassign Device list */
list_for_each(pos, &(devs.list)) {
* thread_id=5729457&forum_id=5398
*/
__maybe_unused struct usb_device_descriptor *desc;
- int port = -1;
struct usb_device *parent = dev->parent;
unsigned short portstatus;
#endif
if (parent) {
- int j;
-
- /* find the port number we're at */
- for (j = 0; j < parent->maxchild; j++) {
- if (parent->children[j] == dev) {
- port = j;
- break;
- }
- }
- if (port < 0) {
- printf("usb_new_device:cannot locate device's port.\n");
- return 1;
- }
-
/* reset the port for the second time */
- err = hub_port_reset(dev->parent, port, &portstatus);
+ err = hub_port_reset(dev->parent, dev->portnr - 1, &portstatus);
if (err < 0) {
- printf("\n Couldn't reset port %i\n", port);
+ printf("\n Couldn't reset port %i\n", dev->portnr);
return 1;
}
}
int i;
struct usb_device *dev;
unsigned pgood_delay = hub->desc.bPwrOn2PwrGood * 2;
- ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
- unsigned short portstatus;
- int ret;
dev = hub->pusb_dev;
- /*
- * Enable power to the ports:
- * Here we Power-cycle the ports: aka,
- * turning them off and turning on again.
- */
debug("enabling power on all ports\n");
- for (i = 0; i < dev->maxchild; i++) {
- usb_clear_port_feature(dev, i + 1, USB_PORT_FEAT_POWER);
- debug("port %d returns %lX\n", i + 1, dev->status);
- }
-
- /* Wait at least 2*bPwrOn2PwrGood for PP to change */
- mdelay(pgood_delay);
-
- for (i = 0; i < dev->maxchild; i++) {
- ret = usb_get_port_status(dev, i + 1, portsts);
- if (ret < 0) {
- debug("port %d: get_port_status failed\n", i + 1);
- continue;
- }
-
- /*
- * Check to confirm the state of Port Power:
- * xHCI says "After modifying PP, s/w shall read
- * PP and confirm that it has reached the desired state
- * before modifying it again, undefined behavior may occur
- * if this procedure is not followed".
- * EHCI doesn't say anything like this, but no harm in keeping
- * this.
- */
- portstatus = le16_to_cpu(portsts->wPortStatus);
- if (portstatus & (USB_PORT_STAT_POWER << 1)) {
- debug("port %d: Port power change failed\n", i + 1);
- continue;
- }
- }
-
for (i = 0; i < dev->maxchild; i++) {
usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_POWER);
debug("port %d returns %lX\n", i + 1, dev->status);
#define USB_KBD_BOOT_REPORT_SIZE 8
struct usb_kbd_pdata {
+ unsigned long intpipe;
+ int intpktsize;
+ int intinterval;
+ struct int_queue *intq;
+
uint32_t repeat_delay;
uint32_t usb_in_pointer;
/* The period of time between two calls of usb_kbd_testc(). */
static unsigned long __maybe_unused kbd_testc_tms;
-/* Generic keyboard event polling. */
-void usb_kbd_generic_poll(void)
-{
- struct stdio_dev *dev;
- struct usb_device *usb_kbd_dev;
- struct usb_kbd_pdata *data;
- struct usb_interface *iface;
- struct usb_endpoint_descriptor *ep;
- int pipe;
- int maxp;
-
- /* Get the pointer to USB Keyboard device pointer */
- dev = stdio_get_by_name(DEVNAME);
- usb_kbd_dev = (struct usb_device *)dev->priv;
- data = usb_kbd_dev->privptr;
- iface = &usb_kbd_dev->config.if_desc[0];
- ep = &iface->ep_desc[0];
- pipe = usb_rcvintpipe(usb_kbd_dev, ep->bEndpointAddress);
-
- /* Submit a interrupt transfer request */
- maxp = usb_maxpacket(usb_kbd_dev, pipe);
- usb_submit_int_msg(usb_kbd_dev, pipe, data->new,
- min(maxp, USB_KBD_BOOT_REPORT_SIZE),
- ep->bInterval);
-}
-
/* Puts character in the queue and sets up the in and out pointer. */
static void usb_kbd_put_queue(struct usb_kbd_pdata *data, char c)
{
static inline void usb_kbd_poll_for_event(struct usb_device *dev)
{
#if defined(CONFIG_SYS_USB_EVENT_POLL)
- struct usb_interface *iface;
- struct usb_endpoint_descriptor *ep;
- struct usb_kbd_pdata *data;
- int pipe;
- int maxp;
-
- /* Get the pointer to USB Keyboard device pointer */
- data = dev->privptr;
- iface = &dev->config.if_desc[0];
- ep = &iface->ep_desc[0];
- pipe = usb_rcvintpipe(dev, ep->bEndpointAddress);
+ struct usb_kbd_pdata *data = dev->privptr;
/* Submit a interrupt transfer request */
- maxp = usb_maxpacket(dev, pipe);
- usb_submit_int_msg(dev, pipe, &data->new[0],
- min(maxp, USB_KBD_BOOT_REPORT_SIZE),
- ep->bInterval);
+ usb_submit_int_msg(dev, data->intpipe, &data->new[0], data->intpktsize,
+ data->intinterval);
usb_kbd_irq_worker(dev);
#elif defined(CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP)
1, 0, data->new, USB_KBD_BOOT_REPORT_SIZE);
if (memcmp(data->old, data->new, USB_KBD_BOOT_REPORT_SIZE))
usb_kbd_irq_worker(dev);
+#elif defined(CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE)
+ struct usb_kbd_pdata *data = dev->privptr;
+ if (poll_int_queue(dev, data->intq)) {
+ usb_kbd_irq_worker(dev);
+ /* We've consumed all queued int packets, create new */
+ destroy_int_queue(dev, data->intq);
+ data->intq = create_int_queue(dev, data->intpipe, 1,
+ USB_KBD_BOOT_REPORT_SIZE, data->new);
+ }
#endif
}
struct usb_interface *iface;
struct usb_endpoint_descriptor *ep;
struct usb_kbd_pdata *data;
- int pipe, maxp;
if (dev->descriptor.bNumConfigurations != 1)
return 0;
/* Set IRQ handler */
dev->irq_handle = usb_kbd_irq;
- pipe = usb_rcvintpipe(dev, ep->bEndpointAddress);
- maxp = usb_maxpacket(dev, pipe);
+ data->intpipe = usb_rcvintpipe(dev, ep->bEndpointAddress);
+ data->intpktsize = min(usb_maxpacket(dev, data->intpipe),
+ USB_KBD_BOOT_REPORT_SIZE);
+ data->intinterval = ep->bInterval;
/* We found a USB Keyboard, install it. */
usb_set_protocol(dev, iface->desc.bInterfaceNumber, 0);
usb_set_idle(dev, iface->desc.bInterfaceNumber, REPEAT_RATE, 0);
debug("USB KBD: enable interrupt pipe...\n");
- if (usb_submit_int_msg(dev, pipe, data->new,
- min(maxp, USB_KBD_BOOT_REPORT_SIZE),
- ep->bInterval) < 0) {
+#ifdef CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
+ data->intq = create_int_queue(dev, data->intpipe, 1,
+ USB_KBD_BOOT_REPORT_SIZE, data->new);
+ if (!data->intq) {
+#else
+ if (usb_submit_int_msg(dev, data->intpipe, data->new, data->intpktsize,
+ data->intinterval) < 0) {
+#endif
printf("Failed to get keyboard state from device %04x:%04x\n",
dev->descriptor.idVendor, dev->descriptor.idProduct);
/* Abort, we don't want to use that non-functional keyboard. */
int usb_kbd_deregister(int force)
{
#ifdef CONFIG_SYS_STDIO_DEREGISTER
- int ret = stdio_deregister(DEVNAME, force);
- if (ret && ret != -ENODEV)
- return ret;
+ struct stdio_dev *dev;
+ struct usb_device *usb_kbd_dev;
+ struct usb_kbd_pdata *data;
+
+ dev = stdio_get_by_name(DEVNAME);
+ if (dev) {
+ usb_kbd_dev = (struct usb_device *)dev->priv;
+ data = usb_kbd_dev->privptr;
+ if (stdio_deregister_dev(dev, force) != 0)
+ return 1;
+#ifdef CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
+ destroy_int_queue(usb_kbd_dev, data->intq);
+#endif
+ free(data->new);
+ free(data);
+ }
return 0;
#else
#include <common.h>
#include <command.h>
+#include <inttypes.h>
#include <asm/byteorder.h>
#include <asm/processor.h>
blks = blkcnt;
debug("\nusb_read: dev %d startblk " LBAF ", blccnt " LBAF
- " buffer %lx\n", device, start, blks, buf_addr);
+ " buffer %" PRIxPTR "\n", device, start, blks, buf_addr);
do {
/* XXX need some comment here */
ss->flags &= ~USB_READY;
debug("usb_read: end startblk " LBAF
- ", blccnt %x buffer %lx\n",
+ ", blccnt %x buffer %" PRIxPTR "\n",
start, smallblks, buf_addr);
usb_disable_asynch(0); /* asynch transfer allowed */
blks = blkcnt;
debug("\nusb_write: dev %d startblk " LBAF ", blccnt " LBAF
- " buffer %lx\n", device, start, blks, buf_addr);
+ " buffer %" PRIxPTR "\n", device, start, blks, buf_addr);
do {
/* If write fails retry for max retry count else
} while (blks != 0);
ss->flags &= ~USB_READY;
- debug("usb_write: end startblk " LBAF ", blccnt %x buffer %lx\n",
- start, smallblks, buf_addr);
+ debug("usb_write: end startblk " LBAF ", blccnt %x buffer %"
+ PRIxPTR "\n", start, smallblks, buf_addr);
usb_disable_asynch(0); /* asynch transfer allowed */
if (blkcnt >= USB_MAX_XFER_BLK)
PLATFORM_CPPFLAGS += -finstrument-functions -DFTRACE
endif
+# Allow use of stdint.h if available
+ifneq ($(USE_STDINT),)
+PLATFORM_CPPFLAGS += -DCONFIG_USE_STDINT
+endif
+
#########################################################################
RELFLAGS := $(PLATFORM_RELFLAGS)
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="A10_OLINUXINO_L,AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-olinuxino-lime.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN4I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_TARGET_A10_OLINUXINO_L=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="A10S_OLINUXINO_M,AXP152_POWER,SUNXI_EMAC,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPB(10)"
+CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,SUNXI_EMAC,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPB(10)"
CONFIG_FDTFILE="sun5i-a10s-olinuxino-micro.dtb"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=1
++S:CONFIG_MMC0_CD_PIN="PG1"
++S:CONFIG_MMC1_CD_PIN="PG13"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN5I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN5I=y
++S:CONFIG_TARGET_A10S_OLINUXINO_M=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="A13_OLINUXINOM,CONS_INDEX=2,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(11)"
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(11)"
CONFIG_FDTFILE="sun5i-a13-olinuxino-micro.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN5I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN5I=y
++S:CONFIG_TARGET_A13_OLINUXINOM=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="A13_OLINUXINO,CONS_INDEX=2,AXP209_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(11)"
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(11)"
CONFIG_FDTFILE="sun5i-a13-olinuxino.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN5I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN5I=y
++S:CONFIG_TARGET_A13_OLINUXINO=y
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
+CONFIG_FDTFILE="sun7i-a20-olinuxino-lime2.dtb"
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_A20_OLINUXINO_L2=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="A20_OLINUXINO_L,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-olinuxino-lime.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_A20_OLINUXINO_L=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="A20_OLINUXINO_M,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-olinuxino-micro.dtb"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=3
++S:CONFIG_MMC0_CD_PIN="PH1"
++S:CONFIG_MMC3_CD_PIN="PH11"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_A20_OLINUXINO_M=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="AUXTEK_T004,AXP152_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(13)"
+CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(13)"
CONFIG_FDTFILE="sun5i-a10s-auxtek-t004.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN5I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN5I=y
++S:CONFIG_TARGET_AUXTEK_T004=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="BANANAPI,AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-bananapi.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_BANANAPI=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_74xx_7xx=y
-CONFIG_TARGET_CPCI750=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN6I=y
+CONFIG_TARGET_COLOMBUS=y
+CONFIG_FDTFILE="sun6i-a31-colombus.dtb"
+++ /dev/null
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CUBIEBOARD2,SPL_FEL,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
-CONFIG_FDTFILE="sun7i-a20-cubieboard2.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CUBIEBOARD2,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-cubieboard2.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_CUBIEBOARD2=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CUBIEBOARD,AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-cubieboard.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN4I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_TARGET_CUBIEBOARD=y
+++ /dev/null
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CUBIETRUCK,SPL_FEL,AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12),USB_EHCI"
-CONFIG_FDTFILE="sun7i-a20-cubietruck.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CUBIETRUCK,AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-cubietruck.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_CUBIETRUCK=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_74xx_7xx=y
-CONFIG_TARGET_DB64360=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_74xx_7xx=y
-CONFIG_TARGET_DB64460=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="EVAL5200"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TOP5200=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_HWW1U1A=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="100MHz"
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_ICU862=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_ICU862=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_IDS8247=y
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I=y
+CONFIG_TARGET_IPPO_Q8H_V5=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-ippo-q8h-v5.dtb"
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="PCDUINO3,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-pcduino3.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_PCDUINO3=y
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI"
+CONFIG_FDTFILE="sun7i-a20-pcduino3.dtb"
+CONFIG_DM=y
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
+CONFIG_OF_CONTROL=y
+CONFIG_OF_SEPARATE=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_PCDUINO3=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_MHPC=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="MINI5200"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TOP5200=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="MELE_A1000G,AXP209_POWER,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI,USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI,USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-a1000.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN4I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_TARGET_MELE_A1000G=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="MELE_A1000,AXP209_POWER,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI,USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI,USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-a1000.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN4I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_TARGET_MELE_A1000=y
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,USB_EHCI"
+CONFIG_FDTFILE="sun7i-a20-m3.dtb"
++S:CONFIG_MMC_SUNXI_SLOT_EXTRA=2
++S:CONFIG_MMC0_CD_PIN="PH1"
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_MELE_M3=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="MINI_X_1GB,AXP209_POWER,USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-mini-xplus.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN4I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_TARGET_MINI_X_1GB=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="MINI_X,AXP209_POWER,USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-mini-xplus.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN4I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_TARGET_MINI_X=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="TOP5200"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TOP5200=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_TOP860=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="MPC8255,300MHz"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_TQM8260=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="MPC8260,200MHz"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_TQM8260=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="MPC8260,200MHz,L2_CACHE,BUSMODE_60x"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_TQM8260=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="MPC8260,200MHz,L2_CACHE,BUSMODE_60x"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_TQM8260=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="MPC8260,300MHz,BUSMODE_60x"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_TQM8260=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="MPC8260,266MHz"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_TQM8260=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="MPC8260,300MHz,BUSMODE_60x"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_TQM8260=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="MPC8260,300MHz"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_TQM8260=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="MPC8260,300MHz,L2_CACHE,BUSMODE_60x"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_TQM8260=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="MPC8260,300MHz,BUSMODE_60x"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_TQM8260=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="MPC8265,300MHz,BUSMODE_60x"
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_TQM8260=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_TQM8272=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_AM335X_EVM=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT,ENABLE_VBOOT"
+CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT,ENABLE_VBOOT"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_AM335X_EVM=y
CONFIG_OF_CONTROL=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND,NOR"
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_CONS_INDEX=1
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_AM335X_EVM=y
+CONFIG_NOR=y
-CONFIG_SYS_EXTRA_OPTIONS="NOR,NOR_BOOT"
CONFIG_CONS_INDEX=1
CONFIG_ARM=y
CONFIG_TARGET_AM335X_EVM=y
+CONFIG_NOR=y
+CONFIG_NOR_BOOT=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="BA10_TV_BOX,AXP209_POWER,SUNXI_EMAC,USB_EHCI,SUNXI_USB_VBUS1_GPIO=SUNXI_GPH(12)"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI,SUNXI_USB_VBUS1_GPIO=SUNXI_GPH(12)"
CONFIG_FDTFILE="sun4i-a10-ba10-tvbox.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN4I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_TARGET_BA10_TV_BOX=y
--- /dev/null
+CONFIG_SPL=n
++S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
++S:CONFIG_TARGET_CM_T3517=y
CONFIG_SYS_EXTRA_OPTIONS="DBAU1000"
CONFIG_MIPS=y
CONFIG_TARGET_DBAU1X00=y
+CONFIG_SYS_BIG_ENDIAN=y
-CONFIG_SYS_EXTRA_OPTIONS="DBAU1100"
CONFIG_MIPS=y
CONFIG_TARGET_DBAU1X00=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_DBAU1100=y
-CONFIG_SYS_EXTRA_OPTIONS="DBAU1500"
CONFIG_MIPS=y
CONFIG_TARGET_DBAU1X00=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_DBAU1500=y
-CONFIG_SYS_EXTRA_OPTIONS="DBAU1550"
CONFIG_MIPS=y
CONFIG_TARGET_DBAU1X00=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_DBAU1550=y
-CONFIG_SYS_EXTRA_OPTIONS="DBAU1550,SYS_LITTLE_ENDIAN"
CONFIG_MIPS=y
CONFIG_TARGET_DBAU1X00=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_DBAU1550=y
+CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SPARC=y
CONFIG_TARGET_GR_CPCI_AX2000=y
+CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SPARC=y
CONFIG_TARGET_GR_EP2S60=y
+CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SPARC=y
CONFIG_TARGET_GR_XC3S_1500=y
+CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SPARC=y
CONFIG_TARGET_GRSIM=y
+CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SPARC=y
CONFIG_TARGET_GRSIM_LEON2=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_HYMOD=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="I12_TVBOX,AXP209_POWER,SUNXI_GMAC,MACPWR=SUNXI_GPH(21),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,MACPWR=SUNXI_GPH(21),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-i12-tvbox.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_I12_TVBOX=y
--- /dev/null
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_KEYSTONE=y
++S:CONFIG_TARGET_K2L_EVM=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_BIG_ENDIAN"
CONFIG_MIPS=y
CONFIG_TARGET_MALTA=y
+CONFIG_SYS_BIG_ENDIAN=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_LITTLE_ENDIAN"
CONFIG_MIPS=y
CONFIG_TARGET_MALTA=y
+CONFIG_SYS_LITTLE_ENDIAN=y
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/kosagi/novena/setup.cfg,MX6Q,SPL"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_KOSAGI_NOVENA=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="P3M7448"
-CONFIG_PPC=y
-CONFIG_74xx_7xx=y
-CONFIG_TARGET_P3MX=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="P3M750"
-CONFIG_PPC=y
-CONFIG_74xx_7xx=y
-CONFIG_TARGET_P3MX=y
CONFIG_SYS_EXTRA_OPTIONS="PB1000"
CONFIG_MIPS=y
CONFIG_TARGET_PB1X00=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_UNIPHIER=y
+S:CONFIG_MACH_PH1_LD4=y
+CONFIG_DM=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
+CONFIG_DM_SERIAL=y
+CONFIG_UNIPHIER_SERIAL=y
S:CONFIG_SPL_NAND_DENALI=y
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_UNIPHIER=y
+S:CONFIG_MACH_PH1_PRO4=y
+CONFIG_DM=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
+CONFIG_DM_SERIAL=y
+CONFIG_UNIPHIER_SERIAL=y
S:CONFIG_SPL_NAND_DENALI=y
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_UNIPHIER=y
+S:CONFIG_MACH_PH1_SLD8=y
+CONFIG_DM=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
+CONFIG_DM_SERIAL=y
+CONFIG_UNIPHIER_SERIAL=y
S:CONFIG_SPL_NAND_DENALI=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_BIG_ENDIAN"
CONFIG_MIPS=y
-CONFIG_TARGET_QEMU_MIPS64=y
+CONFIG_TARGET_QEMU_MIPS=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_CPU_MIPS64_R1=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_LITTLE_ENDIAN"
CONFIG_MIPS=y
-CONFIG_TARGET_QEMU_MIPS64=y
+CONFIG_TARGET_QEMU_MIPS=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS64_R1=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_BIG_ENDIAN"
CONFIG_MIPS=y
CONFIG_TARGET_QEMU_MIPS=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_CPU_MIPS32_R2=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_LITTLE_ENDIAN"
CONFIG_MIPS=y
CONFIG_TARGET_QEMU_MIPS=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32_R2=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="QT840A,AXP209_POWER,SUNXI_GMAC,MACPWR=SUNXI_GPH(21),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,MACPWR=SUNXI_GPH(21),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-i12-tvbox.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_QT840A=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="R7DONGLE,AXP152_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(13)"
+CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(13)"
CONFIG_FDTFILE="sun5i-a10s-r7-tv-dongle.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN5I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN5I=y
++S:CONFIG_TARGET_R7DONGLE=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="EVAL9000"
-CONFIG_ARM=y
-CONFIG_TARGET_TOP9000=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="SU9000"
-CONFIG_ARM=y
-CONFIG_TARGET_TOP9000=y
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUM"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PLATINUM=y
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUM,VCT_ONENAND"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PLATINUM=y
+CONFIG_VCT_ONENAND=y
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PLATINUM=y
+CONFIG_VCT_ONENAND=y
+CONFIG_VCT_SMALL_IMAGE=y
# CONFIG_CMD_CRC32 is not set
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUM,VCT_SMALL_IMAGE"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PLATINUM=y
+CONFIG_VCT_SMALL_IMAGE=y
# CONFIG_CMD_CRC32 is not set
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUMAVC"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PLATINUMAVC=y
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUMAVC,VCT_ONENAND"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PLATINUMAVC=y
+CONFIG_VCT_ONENAND=y
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PLATINUMAVC=y
+CONFIG_VCT_ONENAND=y
+CONFIG_VCT_SMALL_IMAGE=y
# CONFIG_CMD_CRC32 is not set
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUMAVC,VCT_SMALL_IMAGE"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PLATINUMAVC=y
+CONFIG_VCT_SMALL_IMAGE=y
# CONFIG_CMD_CRC32 is not set
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PREMIUM"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PREMIUM=y
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PREMIUM,VCT_ONENAND"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PREMIUM=y
+CONFIG_VCT_ONENAND=y
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PREMIUM=y
+CONFIG_VCT_ONENAND=y
+CONFIG_VCT_SMALL_IMAGE=y
# CONFIG_CMD_CRC32 is not set
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PREMIUM,VCT_SMALL_IMAGE"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PREMIUM=y
+CONFIG_VCT_SMALL_IMAGE=y
# CONFIG_CMD_CRC32 is not set
DECLARE_GLOBAL_DATA_PTR;
#ifdef HAVE_BLOCK_DEVICE
-block_dev_desc_t *get_dev_hwpart(const char *ifname, int dev, int hwpart)
+static block_dev_desc_t *get_dev_hwpart(const char *ifname, int dev, int hwpart)
{
const struct block_drvr *drvr = block_drvr;
block_dev_desc_t* (*reloc_get_dev)(int dev);
CONFIG_SPL_SPI_FLASH_SUPPORT (drivers/mtd/spi/libspi_flash.o)
CONFIG_SPL_SPI_SUPPORT (drivers/spi/libspi.o)
CONFIG_SPL_FAT_SUPPORT (fs/fat/libfat.o)
+CONFIG_SPL_EXT_SUPPORT
CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o)
CONFIG_SPL_POWER_SUPPORT (drivers/power/libpower.o)
CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o)
ST: - the line is valid for SPL and TPL images
+S: - the line is valid for Normal and SPL images
+T: - the line is valid for Normal and TPL images
- +ST: - the line is valid for Normal, SPL and SPL images
+ +ST: - the line is valid for Normal, SPL and TPL images
So, if neither CONFIG_SPL nor CONFIG_TPL is defined, the defconfig file
has no "<condition>:" part and therefore has the same form as in Linux.
image that can be flashed on the board NAND/SPI flash. The make target
which uses mkimage to produce such an image is "u-boot.kwb". For example:
- export BUILD_DIR=/tmp/build
+ export KBUILD_OUTPUT=/tmp/build
make distclean
make yourboard_config
- make $BUILD_DIR/u-boot.kwb
+ make u-boot.kwb
Board specific configuration file specifications:
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
-MVBC_P powerpc mpc5xxx - - Andre Schwarz <andre.schwarz@matrix-vision.de>
-MVSMR powerpc mpc5xxx - - Andre Schwarz <andre.schwarz@matrix-vision.de>
-MERGERBOX powerpc mpc83xx - - Andre Schwarz <andre.schwarz@matrix-vision.de>
-MVBLM7 powerpc mpc83xx - - Andre Schwarz <andre.schwarz@matrix-vision.de>
-bluestone powerpc ppc4xx - - Tirumala Marri <tmarri@apm.com>
-CRAYL1 powerpc ppc4xx - - David Updegraff <dave@cray.com>
-KAREF powerpc ppc4xx - - Travis Sawyer <travis.sawyer@sandburst.com>
-METROBOX powerpc ppc4xx - - Travis Sawyer <travis.sawyer@sandburst.com>
+TOP5200 powerpc mpc5200 - - Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
+TOP860 powerpc mpc860 - - Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
+TOP9000 arm at91sam9xeXXX - - Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
+TQM8272 powerpc mpc8260 f06f9a1 2014-10-27 Wolfgang Denk <wd@denx.de>
+TQM8260 powerpc mpc8260 ccc1950 2014-10-27 Wolfgang Denk <wd@denx.de>
+IDS8247 powerpc mpc8260 6afb357 2014-10-27 Heiko Schocher <hs@denx.de>
+HWW1U1A powerpc mpc85xx 4109cb0 2014-10-27 Kyle Moffett <Kyle.D.Moffett@boeing.com>
+hymod powerpc mpc8260 5038d7f 2014-10-27 Murray Jensen <Murray.Jensen@csiro.au>
+MHPC powerpc mpc8xx 1655f9f 2014-10-27 Frank Gottschling <fgottschling@eltec.de>
+ICU862 powerpc mpc8xx 4af5f0f 2014-10-27 Wolfgang Denk <wd@denx.de>
+CPCI750 powerpc 74xx_7xx 03b0040 2014-10-27 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+DB64360 powerpc 74xx_7xx 03b0040 2014-10-27
+DB64460 powerpc 74xx_7xx 03b0040 2014-10-27
+p3m750 powerpc 74xx_7xx 03b0040 2014-10-27 Stefan Roese <sr@denx.de>
+p3m7448 powerpc 74xx_7xx 03b0040 2014-10-27 Stefan Roese <sr@denx.de>
+MVBC_P powerpc mpc5xxx af55e35 2014-10-10 Andre Schwarz <andre.schwarz@matrix-vision.de>
+MVSMR powerpc mpc5xxx af55e35 2014-10-10 Andre Schwarz <andre.schwarz@matrix-vision.de>
+MERGERBOX powerpc mpc83xx e7a5656 2014-10-10 Andre Schwarz <andre.schwarz@matrix-vision.de>
+MVBLM7 powerpc mpc83xx e7a5656 2014-10-10 Andre Schwarz <andre.schwarz@matrix-vision.de>
+bluestone powerpc ppc4xx 9ed3246 2014-10-10 Tirumala Marri <tmarri@apm.com>
+CRAYL1 powerpc ppc4xx 1521cdc 2014-10-10 David Updegraff <dave@cray.com>
+KAREF powerpc ppc4xx dc9617e 2014-10-10 Travis Sawyer <travis.sawyer@sandburst.com>
+METROBOX powerpc ppc4xx dc9617e 2014-10-10 Travis Sawyer <travis.sawyer@sandburst.com>
PK1C20 nios2 - 70fbc461 2014-08-24 Scott McNutt <smcnutt@psyent.com>
PCI5441 nios2 - 70fbc461 2014-08-24 Scott McNutt <smcnutt@psyent.com>
flagadm powerpc mpc8xx aec6f8c5 2014-08-22 Kári DavÃðsson <kd@flaga.is>
2. The pointer to the jump table is passed to the application in a
machine-dependent way. PowerPC, ARM, MIPS, Blackfin and Nios II
architectures use a dedicated register to hold the pointer to the
- 'global_data' structure: r2 on PowerPC, r8 on ARM, k0 on MIPS,
+ 'global_data' structure: r2 on PowerPC, r9 on ARM, k0 on MIPS,
P3 on Blackfin and gp on Nios II. The x86 architecture does not
use such a register; instead, the pointer to the 'global_data'
structure is passed as 'argv[-1]' pointer.
#else
const u16 *a = (const u16 *)addr1;
const u16 *b = (const u16 *)addr2;
- return ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2])) != 0;
+ return ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2])) == 0;
#endif
}
--- /dev/null
+SoCFPGA EPCS/EPCQx1 mini howto:
+- Instantiate EPCS/EPCQx1 Serial flash controller in QSys and rebuild
+- The controller base address is the "Base" in QSys + 0x400
+- Set MSEL[4:0]=10010 (AS Standard)
+- Load the bitstream into FPGA, enable bridges
+- Only then will the driver work
You should see something like this:
<...U-Boot banner...>
- Running 22 driver model tests
+ Running 29 driver model tests
Test: dm_test_autobind
Test: dm_test_autoprobe
Test: dm_test_bus_children
Device 'd-test': seq 3 is in use by 'b-test'
Device 'a-test': seq 0 is in use by 'd-test'
Test: dm_test_gpio
- sandbox_gpio: sb_gpio_get_value: error: offset 4 not reserved
+ extra-gpios: get_value: error: gpio b5 not reserved
+ Test: dm_test_gpio_anon
+ Test: dm_test_gpio_copy
+ Test: dm_test_gpio_leak
+ extra-gpios: get_value: error: gpio b5 not reserved
+ Test: dm_test_gpio_requestf
Test: dm_test_leak
Test: dm_test_lifecycle
Test: dm_test_operations
Test: dm_test_platdata
Test: dm_test_pre_reloc
Test: dm_test_remove
+ Test: dm_test_spi_find
+ Invalid chip select 0:0 (err=-19)
+ SF: Failed to get idcodes
+ Device 'name-emul': seq 0 is in use by 'name-emul'
+ SF: Detected M25P16 with page size 256 Bytes, erase size 64 KiB, total 2 MiB
+ Test: dm_test_spi_flash
+ 2097152 bytes written in 0 ms
+ SF: Detected M25P16 with page size 256 Bytes, erase size 64 KiB, total 2 MiB
+ SPI flash test:
+ 0 erase: 0 ticks, 65536000 KiB/s 524288.000 Mbps
+ 1 check: 0 ticks, 65536000 KiB/s 524288.000 Mbps
+ 2 write: 0 ticks, 65536000 KiB/s 524288.000 Mbps
+ 3 read: 0 ticks, 65536000 KiB/s 524288.000 Mbps
+ Test passed
+ 0 erase: 0 ticks, 65536000 KiB/s 524288.000 Mbps
+ 1 check: 0 ticks, 65536000 KiB/s 524288.000 Mbps
+ 2 write: 0 ticks, 65536000 KiB/s 524288.000 Mbps
+ 3 read: 0 ticks, 65536000 KiB/s 524288.000 Mbps
+ Test: dm_test_spi_xfer
+ SF: Detected M25P16 with page size 256 Bytes, erase size 64 KiB, total 2 MiB
Test: dm_test_uclass
Test: dm_test_uclass_before_ready
Failures: 0
alias monstr Michal Simek <monstr@monstr.eu>
alias panto Pantelis Antoniou <panto@antoniou-consulting.com>
alias prafulla Prafulla Wadaskar <prafulla@marvell.com>
+alias bobenstein Przemyslaw Marczak <p.marczak@samsung.com>
alias prom Minkyu Kang <mk7.kang@samsung.com>
alias rbohmer Remy Bohmer <linux@bohmer.net>
alias reinhardm Reinhard Meyer <u-boot@emk-elektronik.de>
alias video uboot, ag
alias patman uboot, sjg
alias buildman uboot, sjg
+alias pmic uboot, bobenstein
.TP
.BI "\-F"
Indicates that an existing FIT image should be modified. No dtc
-compilation is performed and the -f flag should not be given.
+compilation is performed and the \-f flag should not be given.
This can be used to sign images with additional keys after initial image
creation.
skipping those for which keys cannot be found. Also add a comment.
.nf
.B mkimage -f kernel.its -k /public/signing-keys -K u-boot.dtb \\\\
--c "Kernel 3.8 image for production devices" kernel.itb
+.br
+.B -c "Kernel 3.8 image for production devices" kernel.itb
.fi
.P
with unavailable keys are skipped.
.nf
.B mkimage -F -k /secret/signing-keys -K u-boot.dtb \\\\
--c "Kernel 3.8 image for production devices" kernel.itb
+.br
+.B -c "Kernel 3.8 image for production devices" kernel.itb
.fi
.SH HOMEPAGE
obj-y += memory/
obj-y += pwm/
obj-y += input/
+# SOC specific infrastructure drivers.
+obj-y += soc/
probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
port_mmio = (struct sata_port_regs *)probe_ent->port[port].port_mmio;
- return readl(&(port_mmio->ssts)) && SATA_PORT_SSTS_DET_MASK;
+ return readl(&(port_mmio->ssts)) & SATA_PORT_SSTS_DET_MASK;
}
/*
+config DM
+ bool "Enable Driver Model"
+ depends on !SPL_BUILD
+ help
+ This config option enables Driver Model.
+ To use legacy drivers, say N.
obj-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
obj-$(CONFIG_APBH_DMA) += apbh_dma.o
obj-$(CONFIG_FSL_DMA) += fsl_dma.o
+obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o
+obj-$(CONFIG_TI_EDMA3) += ti-edma3.o
*/
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/keystone_nav.h>
-
-static int soc_type =
-#ifdef CONFIG_SOC_K2HK
- k2hk;
-#endif
-
-struct qm_config k2hk_qm_memmap = {
- .stat_cfg = 0x02a40000,
- .queue = (struct qm_reg_queue *)0x02a80000,
- .mngr_vbusm = 0x23a80000,
- .i_lram = 0x00100000,
- .proxy = (struct qm_reg_queue *)0x02ac0000,
- .status_ram = 0x02a06000,
- .mngr_cfg = (struct qm_cfg_reg *)0x02a02000,
- .intd_cfg = 0x02a0c000,
- .desc_mem = (struct descr_mem_setup_reg *)0x02a03000,
- .region_num = 64,
- .pdsp_cmd = 0x02a20000,
- .pdsp_ctl = 0x02a0f000,
- .pdsp_iram = 0x02a10000,
- .qpool_num = 4000,
+#include <asm/ti-common/keystone_nav.h>
+
+struct qm_config qm_memmap = {
+ .stat_cfg = CONFIG_KSNAV_QM_QUEUE_STATUS_BASE,
+ .queue = (void *)CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE,
+ .mngr_vbusm = CONFIG_KSNAV_QM_BASE_ADDRESS,
+ .i_lram = CONFIG_KSNAV_QM_LINK_RAM_BASE,
+ .proxy = (void *)CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE,
+ .status_ram = CONFIG_KSNAV_QM_STATUS_RAM_BASE,
+ .mngr_cfg = (void *)CONFIG_KSNAV_QM_CONF_BASE,
+ .intd_cfg = CONFIG_KSNAV_QM_INTD_CONF_BASE,
+ .desc_mem = (void *)CONFIG_KSNAV_QM_DESC_SETUP_BASE,
+ .region_num = CONFIG_KSNAV_QM_REGION_NUM,
+ .pdsp_cmd = CONFIG_KSNAV_QM_PDSP1_CMD_BASE,
+ .pdsp_ctl = CONFIG_KSNAV_QM_PDSP1_CTRL_BASE,
+ .pdsp_iram = CONFIG_KSNAV_QM_PDSP1_IRAM_BASE,
+ .qpool_num = CONFIG_KSNAV_QM_QPOOL_NUM,
};
/*
return 15;
}
-static int _qm_init(struct qm_config *cfg)
+int _qm_init(struct qm_config *cfg)
{
- u32 j;
-
- if (cfg == NULL)
- return QM_ERR;
+ u32 j;
qm_cfg = cfg;
int qm_init(void)
{
- switch (soc_type) {
- case k2hk:
- return _qm_init(&k2hk_qm_memmap);
- }
-
- return QM_ERR;
+ return _qm_init(&qm_memmap);
}
void qm_close(void)
{
u32 j;
- if (qm_cfg == NULL)
- return;
-
queue_close(qm_cfg->qpool_num);
qm_cfg->mngr_cfg->link_ram_base0 = 0;
{
u32 regd;
- if (!qm_cfg)
- return;
-
cpu_to_bus((u32 *)hd, sizeof(struct qm_host_desc)/4);
regd = (u32)hd | ((sizeof(struct qm_host_desc) >> 4) - 1);
writel(regd, &qm_cfg->queue[qnum].ptr_size_thresh);
{
u32 uhd;
- if (!qm_cfg)
- return NULL;
-
uhd = readl(&qm_cfg->queue[qnum].ptr_size_thresh) & ~0xf;
if (uhd)
cpu_to_bus((u32 *)uhd, sizeof(struct qm_host_desc)/4);
struct qm_host_desc *qm_pop_from_free_pool(void)
{
- if (!qm_cfg)
- return NULL;
-
return qm_pop(qm_cfg->qpool_num);
}
;
}
-/*
+/**
* DMA API
*/
-struct pktdma_cfg k2hk_netcp_pktdma = {
- .global = (struct global_ctl_regs *)0x02004000,
- .tx_ch = (struct tx_chan_regs *)0x02004400,
- .tx_ch_num = 9,
- .rx_ch = (struct rx_chan_regs *)0x02004800,
- .rx_ch_num = 26,
- .tx_sched = (u32 *)0x02004c00,
- .rx_flows = (struct rx_flow_regs *)0x02005000,
- .rx_flow_num = 32,
- .rx_free_q = 4001,
- .rx_rcv_q = 4002,
- .tx_snd_q = 648,
-};
-
-struct pktdma_cfg *netcp;
-
-static int netcp_rx_disable(void)
+static int ksnav_rx_disable(struct pktdma_cfg *pktdma)
{
u32 j, v, k;
- for (j = 0; j < netcp->rx_ch_num; j++) {
- v = readl(&netcp->rx_ch[j].cfg_a);
+ for (j = 0; j < pktdma->rx_ch_num; j++) {
+ v = readl(&pktdma->rx_ch[j].cfg_a);
if (!(v & CPDMA_CHAN_A_ENABLE))
continue;
- writel(v | CPDMA_CHAN_A_TDOWN, &netcp->rx_ch[j].cfg_a);
+ writel(v | CPDMA_CHAN_A_TDOWN, &pktdma->rx_ch[j].cfg_a);
for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) {
udelay(100);
- v = readl(&netcp->rx_ch[j].cfg_a);
+ v = readl(&pktdma->rx_ch[j].cfg_a);
if (!(v & CPDMA_CHAN_A_ENABLE))
continue;
}
}
/* Clear all of the flow registers */
- for (j = 0; j < netcp->rx_flow_num; j++) {
- writel(0, &netcp->rx_flows[j].control);
- writel(0, &netcp->rx_flows[j].tags);
- writel(0, &netcp->rx_flows[j].tag_sel);
- writel(0, &netcp->rx_flows[j].fdq_sel[0]);
- writel(0, &netcp->rx_flows[j].fdq_sel[1]);
- writel(0, &netcp->rx_flows[j].thresh[0]);
- writel(0, &netcp->rx_flows[j].thresh[1]);
- writel(0, &netcp->rx_flows[j].thresh[2]);
+ for (j = 0; j < pktdma->rx_flow_num; j++) {
+ writel(0, &pktdma->rx_flows[j].control);
+ writel(0, &pktdma->rx_flows[j].tags);
+ writel(0, &pktdma->rx_flows[j].tag_sel);
+ writel(0, &pktdma->rx_flows[j].fdq_sel[0]);
+ writel(0, &pktdma->rx_flows[j].fdq_sel[1]);
+ writel(0, &pktdma->rx_flows[j].thresh[0]);
+ writel(0, &pktdma->rx_flows[j].thresh[1]);
+ writel(0, &pktdma->rx_flows[j].thresh[2]);
}
return QM_OK;
}
-static int netcp_tx_disable(void)
+static int ksnav_tx_disable(struct pktdma_cfg *pktdma)
{
u32 j, v, k;
- for (j = 0; j < netcp->tx_ch_num; j++) {
- v = readl(&netcp->tx_ch[j].cfg_a);
+ for (j = 0; j < pktdma->tx_ch_num; j++) {
+ v = readl(&pktdma->tx_ch[j].cfg_a);
if (!(v & CPDMA_CHAN_A_ENABLE))
continue;
- writel(v | CPDMA_CHAN_A_TDOWN, &netcp->tx_ch[j].cfg_a);
+ writel(v | CPDMA_CHAN_A_TDOWN, &pktdma->tx_ch[j].cfg_a);
for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) {
udelay(100);
- v = readl(&netcp->tx_ch[j].cfg_a);
+ v = readl(&pktdma->tx_ch[j].cfg_a);
if (!(v & CPDMA_CHAN_A_ENABLE))
continue;
}
return QM_OK;
}
-static int _netcp_init(struct pktdma_cfg *netcp_cfg,
- struct rx_buff_desc *rx_buffers)
+int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc *rx_buffers)
{
u32 j, v;
struct qm_host_desc *hd;
u8 *rx_ptr;
- if (netcp_cfg == NULL || rx_buffers == NULL ||
+ if (pktdma == NULL || rx_buffers == NULL ||
rx_buffers->buff_ptr == NULL || qm_cfg == NULL)
return QM_ERR;
- netcp = netcp_cfg;
- netcp->rx_flow = rx_buffers->rx_flow;
+ pktdma->rx_flow = rx_buffers->rx_flow;
/* init rx queue */
rx_ptr = rx_buffers->buff_ptr;
if (hd == NULL)
return QM_ERR;
- qm_buff_push(hd, netcp->rx_free_q,
+ qm_buff_push(hd, pktdma->rx_free_q,
rx_ptr, rx_buffers->buff_len);
rx_ptr += rx_buffers->buff_len;
}
- netcp_rx_disable();
+ ksnav_rx_disable(pktdma);
/* configure rx channels */
- v = CPDMA_REG_VAL_MAKE_RX_FLOW_A(1, 1, 0, 0, 0, 0, 0, netcp->rx_rcv_q);
- writel(v, &netcp->rx_flows[netcp->rx_flow].control);
- writel(0, &netcp->rx_flows[netcp->rx_flow].tags);
- writel(0, &netcp->rx_flows[netcp->rx_flow].tag_sel);
+ v = CPDMA_REG_VAL_MAKE_RX_FLOW_A(1, 1, 0, 0, 0, 0, 0, pktdma->rx_rcv_q);
+ writel(v, &pktdma->rx_flows[pktdma->rx_flow].control);
+ writel(0, &pktdma->rx_flows[pktdma->rx_flow].tags);
+ writel(0, &pktdma->rx_flows[pktdma->rx_flow].tag_sel);
- v = CPDMA_REG_VAL_MAKE_RX_FLOW_D(0, netcp->rx_free_q, 0,
- netcp->rx_free_q);
+ v = CPDMA_REG_VAL_MAKE_RX_FLOW_D(0, pktdma->rx_free_q, 0,
+ pktdma->rx_free_q);
- writel(v, &netcp->rx_flows[netcp->rx_flow].fdq_sel[0]);
- writel(v, &netcp->rx_flows[netcp->rx_flow].fdq_sel[1]);
- writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[0]);
- writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[1]);
- writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[2]);
+ writel(v, &pktdma->rx_flows[pktdma->rx_flow].fdq_sel[0]);
+ writel(v, &pktdma->rx_flows[pktdma->rx_flow].fdq_sel[1]);
+ writel(0, &pktdma->rx_flows[pktdma->rx_flow].thresh[0]);
+ writel(0, &pktdma->rx_flows[pktdma->rx_flow].thresh[1]);
+ writel(0, &pktdma->rx_flows[pktdma->rx_flow].thresh[2]);
- for (j = 0; j < netcp->rx_ch_num; j++)
- writel(CPDMA_CHAN_A_ENABLE, &netcp->rx_ch[j].cfg_a);
+ for (j = 0; j < pktdma->rx_ch_num; j++)
+ writel(CPDMA_CHAN_A_ENABLE, &pktdma->rx_ch[j].cfg_a);
/* configure tx channels */
/* Disable loopback in the tx direction */
- writel(0, &netcp->global->emulation_control);
+ writel(0, &pktdma->global->emulation_control);
-/* TODO: make it dependend on a soc type variable */
-#ifdef CONFIG_SOC_K2HK
/* Set QM base address, only for K2x devices */
- writel(0x23a80000, &netcp->global->qm_base_addr[0]);
-#endif
+ writel(CONFIG_KSNAV_QM_BASE_ADDRESS, &pktdma->global->qm_base_addr[0]);
/* Enable all channels. The current state isn't important */
- for (j = 0; j < netcp->tx_ch_num; j++) {
- writel(0, &netcp->tx_ch[j].cfg_b);
- writel(CPDMA_CHAN_A_ENABLE, &netcp->tx_ch[j].cfg_a);
+ for (j = 0; j < pktdma->tx_ch_num; j++) {
+ writel(0, &pktdma->tx_ch[j].cfg_b);
+ writel(CPDMA_CHAN_A_ENABLE, &pktdma->tx_ch[j].cfg_a);
}
return QM_OK;
}
-int netcp_init(struct rx_buff_desc *rx_buffers)
-{
- switch (soc_type) {
- case k2hk:
- _netcp_init(&k2hk_netcp_pktdma, rx_buffers);
- return QM_OK;
- }
- return QM_ERR;
-}
-
-int netcp_close(void)
+int ksnav_close(struct pktdma_cfg *pktdma)
{
- if (!netcp)
+ if (!pktdma)
return QM_ERR;
- netcp_tx_disable();
- netcp_rx_disable();
+ ksnav_tx_disable(pktdma);
+ ksnav_rx_disable(pktdma);
- queue_close(netcp->rx_free_q);
- queue_close(netcp->rx_rcv_q);
- queue_close(netcp->tx_snd_q);
+ queue_close(pktdma->rx_free_q);
+ queue_close(pktdma->rx_rcv_q);
+ queue_close(pktdma->tx_snd_q);
return QM_OK;
}
-int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2)
+int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes, u32 swinfo2)
{
struct qm_host_desc *hd;
hd->swinfo[2] = swinfo2;
hd->packet_info = qm_cfg->qpool_num;
- qm_buff_push(hd, netcp->tx_snd_q, pkt, num_bytes);
+ qm_buff_push(hd, pktdma->tx_snd_q, pkt, num_bytes);
return QM_OK;
}
-void *netcp_recv(u32 **pkt, int *num_bytes)
+void *ksnav_recv(struct pktdma_cfg *pktdma, u32 **pkt, int *num_bytes)
{
struct qm_host_desc *hd;
- hd = qm_pop(netcp->rx_rcv_q);
+ hd = qm_pop(pktdma->rx_rcv_q);
if (!hd)
return NULL;
return hd;
}
-void netcp_release_rxhd(void *hd)
+void ksnav_release_rxhd(struct pktdma_cfg *pktdma, void *hd)
{
struct qm_host_desc *_hd = (struct qm_host_desc *)hd;
_hd->buff_len = _hd->orig_buff_len;
_hd->buff_ptr = _hd->orig_buff_ptr;
- qm_push(_hd, netcp->rx_free_q);
+ qm_push(_hd, pktdma->rx_free_q);
}
--- /dev/null
+/*
+ * Multicore Navigator driver for TI Keystone 2 devices.
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/ti-common/keystone_nav.h>
+
+#ifdef CONFIG_KSNAV_PKTDMA_NETCP
+/* NETCP Pktdma */
+struct pktdma_cfg netcp_pktdma = {
+ .global = (void *)CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE,
+ .tx_ch = (void *)CONFIG_KSNAV_NETCP_PDMA_TX_BASE,
+ .tx_ch_num = CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM,
+ .rx_ch = (void *)CONFIG_KSNAV_NETCP_PDMA_RX_BASE,
+ .rx_ch_num = CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM,
+ .tx_sched = (u32 *)CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE,
+ .rx_flows = (void *)CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE,
+ .rx_flow_num = CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM,
+ .rx_free_q = CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE,
+ .rx_rcv_q = CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE,
+ .tx_snd_q = CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE,
+};
+#endif
--- /dev/null
+/*
+ * Enhanced Direct Memory Access (EDMA3) Controller
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * Author: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <asm/ti-common/ti-edma3.h>
+
+#define EDMA3_SL_BASE(slot) (0x4000 + ((slot) << 5))
+#define EDMA3_SL_MAX_NUM 512
+#define EDMA3_SLOPT_FIFO_WIDTH_MASK (0x7 << 8)
+
+#define EDMA3_QCHMAP(ch) 0x0200 + ((ch) << 2)
+#define EDMA3_CHMAP_PARSET_MASK 0x1ff
+#define EDMA3_CHMAP_PARSET_SHIFT 0x5
+#define EDMA3_CHMAP_TRIGWORD_SHIFT 0x2
+
+#define EDMA3_QEMCR 0x314
+#define EDMA3_IPR 0x1068
+#define EDMA3_IPRH 0x106c
+#define EDMA3_ICR 0x1070
+#define EDMA3_ICRH 0x1074
+#define EDMA3_QEECR 0x1088
+#define EDMA3_QEESR 0x108c
+#define EDMA3_QSECR 0x1094
+
+/**
+ * qedma3_start - start qdma on a channel
+ * @base: base address of edma
+ * @cfg: pinter to struct edma3_channel_config where you can set
+ * the slot number to associate with, the chnum, which corresponds
+ * your quick channel number 0-7, complete code - transfer complete code
+ * and trigger slot word - which has to correspond to the word number in
+ * edma3_slot_layout struct for generating event.
+ *
+ */
+void qedma3_start(u32 base, struct edma3_channel_config *cfg)
+{
+ u32 qchmap;
+
+ /* Clear the pending int bit */
+ if (cfg->complete_code < 32)
+ __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR);
+ else
+ __raw_writel(1 << cfg->complete_code, base + EDMA3_ICRH);
+
+ /* Map parameter set and trigger word 7 to quick channel */
+ qchmap = ((EDMA3_CHMAP_PARSET_MASK & cfg->slot)
+ << EDMA3_CHMAP_PARSET_SHIFT) |
+ (cfg->trigger_slot_word << EDMA3_CHMAP_TRIGWORD_SHIFT);
+
+ __raw_writel(qchmap, base + EDMA3_QCHMAP(cfg->chnum));
+
+ /* Clear missed event if set*/
+ __raw_writel(1 << cfg->chnum, base + EDMA3_QSECR);
+ __raw_writel(1 << cfg->chnum, base + EDMA3_QEMCR);
+
+ /* Enable qdma channel event */
+ __raw_writel(1 << cfg->chnum, base + EDMA3_QEESR);
+}
+
+/**
+ * edma3_set_dest - set initial DMA destination address in parameter RAM slot
+ * @base: base address of edma
+ * @slot: parameter RAM slot being configured
+ * @dst: physical address of destination (memory, controller FIFO, etc)
+ * @addressMode: INCR, except in very rare cases
+ * @width: ignored unless @addressMode is FIFO, else specifies the
+ * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
+ *
+ * Note that the destination address is modified during the DMA transfer
+ * according to edma3_set_dest_index().
+ */
+void edma3_set_dest(u32 base, int slot, u32 dst, enum edma3_address_mode mode,
+ enum edma3_fifo_width width)
+{
+ u32 opt;
+ struct edma3_slot_layout *rg;
+
+ rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
+
+ opt = __raw_readl(&rg->opt);
+ if (mode == FIFO)
+ opt = (opt & EDMA3_SLOPT_FIFO_WIDTH_MASK) |
+ (EDMA3_SLOPT_DST_ADDR_CONST_MODE |
+ EDMA3_SLOPT_FIFO_WIDTH_SET(width));
+ else
+ opt &= ~EDMA3_SLOPT_DST_ADDR_CONST_MODE;
+
+ __raw_writel(opt, &rg->opt);
+ __raw_writel(dst, &rg->dst);
+}
+
+/**
+ * edma3_set_dest_index - configure DMA destination address indexing
+ * @base: base address of edma
+ * @slot: parameter RAM slot being configured
+ * @bidx: byte offset between destination arrays in a frame
+ * @cidx: byte offset between destination frames in a block
+ *
+ * Offsets are specified to support either contiguous or discontiguous
+ * memory transfers, or repeated access to a hardware register, as needed.
+ * When accessing hardware registers, both offsets are normally zero.
+ */
+void edma3_set_dest_index(u32 base, unsigned slot, int bidx, int cidx)
+{
+ u32 src_dst_bidx;
+ u32 src_dst_cidx;
+ struct edma3_slot_layout *rg;
+
+ rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
+
+ src_dst_bidx = __raw_readl(&rg->src_dst_bidx);
+ src_dst_cidx = __raw_readl(&rg->src_dst_cidx);
+
+ __raw_writel((src_dst_bidx & 0x0000ffff) | (bidx << 16),
+ &rg->src_dst_bidx);
+ __raw_writel((src_dst_cidx & 0x0000ffff) | (cidx << 16),
+ &rg->src_dst_cidx);
+}
+
+/**
+ * edma3_set_dest_addr - set destination address for slot only
+ */
+void edma3_set_dest_addr(u32 base, int slot, u32 dst)
+{
+ struct edma3_slot_layout *rg;
+
+ rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
+ __raw_writel(dst, &rg->dst);
+}
+
+/**
+ * edma3_set_src - set initial DMA source address in parameter RAM slot
+ * @base: base address of edma
+ * @slot: parameter RAM slot being configured
+ * @src_port: physical address of source (memory, controller FIFO, etc)
+ * @mode: INCR, except in very rare cases
+ * @width: ignored unless @addressMode is FIFO, else specifies the
+ * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
+ *
+ * Note that the source address is modified during the DMA transfer
+ * according to edma3_set_src_index().
+ */
+void edma3_set_src(u32 base, int slot, u32 src, enum edma3_address_mode mode,
+ enum edma3_fifo_width width)
+{
+ u32 opt;
+ struct edma3_slot_layout *rg;
+
+ rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
+
+ opt = __raw_readl(&rg->opt);
+ if (mode == FIFO)
+ opt = (opt & EDMA3_SLOPT_FIFO_WIDTH_MASK) |
+ (EDMA3_SLOPT_DST_ADDR_CONST_MODE |
+ EDMA3_SLOPT_FIFO_WIDTH_SET(width));
+ else
+ opt &= ~EDMA3_SLOPT_DST_ADDR_CONST_MODE;
+
+ __raw_writel(opt, &rg->opt);
+ __raw_writel(src, &rg->src);
+}
+
+/**
+ * edma3_set_src_index - configure DMA source address indexing
+ * @base: base address of edma
+ * @slot: parameter RAM slot being configured
+ * @bidx: byte offset between source arrays in a frame
+ * @cidx: byte offset between source frames in a block
+ *
+ * Offsets are specified to support either contiguous or discontiguous
+ * memory transfers, or repeated access to a hardware register, as needed.
+ * When accessing hardware registers, both offsets are normally zero.
+ */
+void edma3_set_src_index(u32 base, unsigned slot, int bidx, int cidx)
+{
+ u32 src_dst_bidx;
+ u32 src_dst_cidx;
+ struct edma3_slot_layout *rg;
+
+ rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
+
+ src_dst_bidx = __raw_readl(&rg->src_dst_bidx);
+ src_dst_cidx = __raw_readl(&rg->src_dst_cidx);
+
+ __raw_writel((src_dst_bidx & 0xffff0000) | bidx,
+ &rg->src_dst_bidx);
+ __raw_writel((src_dst_cidx & 0xffff0000) | cidx,
+ &rg->src_dst_cidx);
+}
+
+/**
+ * edma3_set_src_addr - set source address for slot only
+ */
+void edma3_set_src_addr(u32 base, int slot, u32 src)
+{
+ struct edma3_slot_layout *rg;
+
+ rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
+ __raw_writel(src, &rg->src);
+}
+
+/**
+ * edma3_set_transfer_params - configure DMA transfer parameters
+ * @base: base address of edma
+ * @slot: parameter RAM slot being configured
+ * @acnt: how many bytes per array (at least one)
+ * @bcnt: how many arrays per frame (at least one)
+ * @ccnt: how many frames per block (at least one)
+ * @bcnt_rld: used only for A-Synchronized transfers; this specifies
+ * the value to reload into bcnt when it decrements to zero
+ * @sync_mode: ASYNC or ABSYNC
+ *
+ * See the EDMA3 documentation to understand how to configure and link
+ * transfers using the fields in PaRAM slots. If you are not doing it
+ * all at once with edma3_write_slot(), you will use this routine
+ * plus two calls each for source and destination, setting the initial
+ * address and saying how to index that address.
+ *
+ * An example of an A-Synchronized transfer is a serial link using a
+ * single word shift register. In that case, @acnt would be equal to
+ * that word size; the serial controller issues a DMA synchronization
+ * event to transfer each word, and memory access by the DMA transfer
+ * controller will be word-at-a-time.
+ *
+ * An example of an AB-Synchronized transfer is a device using a FIFO.
+ * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
+ * The controller with the FIFO issues DMA synchronization events when
+ * the FIFO threshold is reached, and the DMA transfer controller will
+ * transfer one frame to (or from) the FIFO. It will probably use
+ * efficient burst modes to access memory.
+ */
+void edma3_set_transfer_params(u32 base, int slot, int acnt,
+ int bcnt, int ccnt, u16 bcnt_rld,
+ enum edma3_sync_dimension sync_mode)
+{
+ u32 opt;
+ u32 link_bcntrld;
+ struct edma3_slot_layout *rg;
+
+ rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
+
+ link_bcntrld = __raw_readl(&rg->link_bcntrld);
+
+ __raw_writel((bcnt_rld << 16) | (0x0000ffff & link_bcntrld),
+ &rg->link_bcntrld);
+
+ opt = __raw_readl(&rg->opt);
+ if (sync_mode == ASYNC)
+ __raw_writel(opt & ~EDMA3_SLOPT_AB_SYNC, &rg->opt);
+ else
+ __raw_writel(opt | EDMA3_SLOPT_AB_SYNC, &rg->opt);
+
+ /* Set the acount, bcount, ccount registers */
+ __raw_writel((bcnt << 16) | (acnt & 0xffff), &rg->a_b_cnt);
+ __raw_writel(0xffff & ccnt, &rg->ccnt);
+}
+
+/**
+ * edma3_write_slot - write parameter RAM data for slot
+ * @base: base address of edma
+ * @slot: number of parameter RAM slot being modified
+ * @param: data to be written into parameter RAM slot
+ *
+ * Use this to assign all parameters of a transfer at once. This
+ * allows more efficient setup of transfers than issuing multiple
+ * calls to set up those parameters in small pieces, and provides
+ * complete control over all transfer options.
+ */
+void edma3_write_slot(u32 base, int slot, struct edma3_slot_layout *param)
+{
+ int i;
+ u32 *p = (u32 *)param;
+ u32 *addr = (u32 *)(base + EDMA3_SL_BASE(slot));
+
+ for (i = 0; i < sizeof(struct edma3_slot_layout)/4; i += 4)
+ __raw_writel(*p++, addr++);
+}
+
+/**
+ * edma3_read_slot - read parameter RAM data from slot
+ * @base: base address of edma
+ * @slot: number of parameter RAM slot being copied
+ * @param: where to store copy of parameter RAM data
+ *
+ * Use this to read data from a parameter RAM slot, perhaps to
+ * save them as a template for later reuse.
+ */
+void edma3_read_slot(u32 base, int slot, struct edma3_slot_layout *param)
+{
+ int i;
+ u32 *p = (u32 *)param;
+ u32 *addr = (u32 *)(base + EDMA3_SL_BASE(slot));
+
+ for (i = 0; i < sizeof(struct edma3_slot_layout)/4; i += 4)
+ *p++ = __raw_readl(addr++);
+}
+
+void edma3_slot_configure(u32 base, int slot, struct edma3_slot_config *cfg)
+{
+ struct edma3_slot_layout *rg;
+
+ rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
+
+ __raw_writel(cfg->opt, &rg->opt);
+ __raw_writel(cfg->src, &rg->src);
+ __raw_writel((cfg->bcnt << 16) | (cfg->acnt & 0xffff), &rg->a_b_cnt);
+ __raw_writel(cfg->dst, &rg->dst);
+ __raw_writel((cfg->dst_bidx << 16) |
+ (cfg->src_bidx & 0xffff), &rg->src_dst_bidx);
+ __raw_writel((cfg->bcntrld << 16) |
+ (cfg->link & 0xffff), &rg->link_bcntrld);
+ __raw_writel((cfg->dst_cidx << 16) |
+ (cfg->src_cidx & 0xffff), &rg->src_dst_cidx);
+ __raw_writel(0xffff & cfg->ccnt, &rg->ccnt);
+}
+
+/**
+ * edma3_check_for_transfer - check if transfer coplete by checking
+ * interrupt pending bit. Clear interrupt pending bit if complete.
+ * @base: base address of edma
+ * @cfg: pinter to struct edma3_channel_config which was passed
+ * to qedma3_start when you started qdma channel
+ *
+ * Return 0 if complete, 1 if not.
+ */
+int edma3_check_for_transfer(u32 base, struct edma3_channel_config *cfg)
+{
+ u32 inum;
+ u32 ipr_base;
+ u32 icr_base;
+
+ if (cfg->complete_code < 32) {
+ ipr_base = base + EDMA3_IPR;
+ icr_base = base + EDMA3_ICR;
+ inum = 1 << cfg->complete_code;
+ } else {
+ ipr_base = base + EDMA3_IPRH;
+ icr_base = base + EDMA3_ICRH;
+ inum = 1 << (cfg->complete_code - 32);
+ }
+
+ /* check complete interrupt */
+ if (!(__raw_readl(ipr_base) & inum))
+ return 1;
+
+ /* clean up the pending int bit */
+ __raw_writel(inum, icr_base);
+
+ return 0;
+}
+
+/**
+ * qedma3_stop - stops dma on the channel passed
+ * @base: base address of edma
+ * @cfg: pinter to struct edma3_channel_config which was passed
+ * to qedma3_start when you started qdma channel
+ */
+void qedma3_stop(u32 base, struct edma3_channel_config *cfg)
+{
+ /* Disable qdma channel event */
+ __raw_writel(1 << cfg->chnum, base + EDMA3_QEECR);
+
+ /* clean up the interrupt indication */
+ if (cfg->complete_code < 32)
+ __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR);
+ else
+ __raw_writel(1 << cfg->complete_code, base + EDMA3_ICRH);
+
+ /* Clear missed event if set*/
+ __raw_writel(1 << cfg->chnum, base + EDMA3_QSECR);
+ __raw_writel(1 << cfg->chnum, base + EDMA3_QEMCR);
+
+ /* Clear the channel map */
+ __raw_writel(0, base + EDMA3_QCHMAP(cfg->chnum));
+}
+config DM_GPIO
+ bool "Enable Driver Model for GPIO drivers"
+ depends on DM
+ help
+ If you want to use driver model for GPIO drivers, say Y.
+ To use legacy GPIO drivers, say N.
#include <asm/gpio.h>
#include <asm/io.h>
-#define GPIO_NAME_SIZE 20
-
struct bcm2835_gpios {
- char label[BCM2835_GPIO_COUNT][GPIO_NAME_SIZE];
struct bcm2835_gpio_regs *reg;
};
-/**
- * gpio_is_requested() - check if a GPIO has been requested
- *
- * @bank: Bank to check
- * @offset: GPIO offset within bank to check
- * @return true if marked as requested, false if not
- */
-static inline bool gpio_is_requested(struct bcm2835_gpios *gpios, int offset)
-{
- return *gpios->label[offset] != '\0';
-}
-
-static int check_requested(struct udevice *dev, unsigned offset,
- const char *func)
-{
- struct bcm2835_gpios *gpios = dev_get_priv(dev);
- struct gpio_dev_priv *uc_priv = dev->uclass_priv;
-
- if (!gpio_is_requested(gpios, offset)) {
- printf("omap_gpio: %s: error: gpio %s%d not requested\n",
- func, uc_priv->bank_name, offset);
- return -EPERM;
- }
-
- return 0;
-}
-
-static int bcm2835_gpio_request(struct udevice *dev, unsigned offset,
- const char *label)
-{
- struct bcm2835_gpios *gpios = dev_get_priv(dev);
-
- if (gpio_is_requested(gpios, offset))
- return -EBUSY;
-
- strncpy(gpios->label[offset], label, GPIO_NAME_SIZE);
- gpios->label[offset][GPIO_NAME_SIZE - 1] = '\0';
-
- return 0;
-}
-
-static int bcm2835_gpio_free(struct udevice *dev, unsigned offset)
-{
- struct bcm2835_gpios *gpios = dev_get_priv(dev);
- int ret;
-
- ret = check_requested(dev, offset, __func__);
- if (ret)
- return ret;
- gpios->label[offset][0] = '\0';
-
- return 0;
-}
-
static int bcm2835_gpio_direction_input(struct udevice *dev, unsigned gpio)
{
struct bcm2835_gpios *gpios = dev_get_priv(dev);
{
struct bcm2835_gpios *gpios = dev_get_priv(dev);
- if (!gpio_is_requested(gpios, offset))
- return GPIOF_UNUSED;
-
/* GPIOF_FUNC is not implemented yet */
if (bcm2835_gpio_is_output(gpios, offset))
return GPIOF_OUTPUT;
return GPIOF_INPUT;
}
-static int bcm2835_gpio_get_state(struct udevice *dev, unsigned int offset,
- char *buf, int bufsize)
-{
- struct gpio_dev_priv *uc_priv = dev->uclass_priv;
- struct bcm2835_gpios *gpios = dev_get_priv(dev);
- const char *label;
- bool requested;
- bool is_output;
- int size;
-
- label = gpios->label[offset];
- is_output = bcm2835_gpio_is_output(gpios, offset);
- size = snprintf(buf, bufsize, "%s%d: ",
- uc_priv->bank_name ? uc_priv->bank_name : "", offset);
- buf += size;
- bufsize -= size;
- requested = gpio_is_requested(gpios, offset);
- snprintf(buf, bufsize, "%s: %d [%c]%s%s",
- is_output ? "out" : " in",
- bcm2835_get_value(gpios, offset),
- requested ? 'x' : ' ',
- requested ? " " : "",
- label);
-
- return 0;
-}
static const struct dm_gpio_ops gpio_bcm2835_ops = {
- .request = bcm2835_gpio_request,
- .free = bcm2835_gpio_free,
.direction_input = bcm2835_gpio_direction_input,
.direction_output = bcm2835_gpio_direction_output,
.get_value = bcm2835_gpio_get_value,
.set_value = bcm2835_gpio_set_value,
.get_function = bcm2835_gpio_get_function,
- .get_state = bcm2835_gpio_get_state,
};
static int bcm2835_gpio_probe(struct udevice *dev)
#include <common.h>
#include <dm.h>
#include <errno.h>
+#include <malloc.h>
#include <asm/gpio.h>
+#include <linux/ctype.h>
/**
* gpio_to_device() - Convert global GPIO number to device, number
int gpio_lookup_name(const char *name, struct udevice **devp,
unsigned int *offsetp, unsigned int *gpiop)
{
- struct gpio_dev_priv *uc_priv;
+ struct gpio_dev_priv *uc_priv = NULL;
struct udevice *dev;
+ ulong offset;
+ int numeric;
int ret;
if (devp)
*devp = NULL;
+ numeric = isdigit(*name) ? simple_strtoul(name, NULL, 10) : -1;
for (ret = uclass_first_device(UCLASS_GPIO, &dev);
dev;
ret = uclass_next_device(&dev)) {
- ulong offset;
int len;
uc_priv = dev->uclass_priv;
+ if (numeric != -1) {
+ offset = numeric - uc_priv->gpio_base;
+ /* Allow GPIOs to be numbered from 0 */
+ if (offset >= 0 && offset < uc_priv->gpio_count)
+ break;
+ }
+
len = uc_priv->bank_name ? strlen(uc_priv->bank_name) : 0;
if (!strncasecmp(name, uc_priv->bank_name, len)) {
- if (strict_strtoul(name + len, 10, &offset))
- continue;
- if (devp)
- *devp = dev;
- if (offsetp)
- *offsetp = offset;
- if (gpiop)
- *gpiop = uc_priv->gpio_base + offset;
- return 0;
+ if (!strict_strtoul(name + len, 10, &offset))
+ break;
}
}
- return ret ? ret : -EINVAL;
+ if (!dev)
+ return ret ? ret : -EINVAL;
+
+ if (devp)
+ *devp = dev;
+ if (offsetp)
+ *offsetp = offset;
+ if (gpiop)
+ *gpiop = uc_priv->gpio_base + offset;
+
+ return 0;
}
/**
* gpio: GPIO number
* label: Name for the requested GPIO
*
+ * The label is copied and allocated so the caller does not need to keep
+ * the pointer around.
+ *
* This function implements the API that's compatible with current
* GPIO API used in U-Boot. The request is forwarded to particular
* GPIO driver. Returns 0 on success, negative value on error.
*/
int gpio_request(unsigned gpio, const char *label)
{
+ struct gpio_dev_priv *uc_priv;
unsigned int offset;
struct udevice *dev;
+ char *str;
int ret;
ret = gpio_to_device(gpio, &dev, &offset);
if (ret)
return ret;
- if (!gpio_get_ops(dev)->request)
- return 0;
+ uc_priv = dev->uclass_priv;
+ if (uc_priv->name[offset])
+ return -EBUSY;
+ str = strdup(label);
+ if (!str)
+ return -ENOMEM;
+ if (gpio_get_ops(dev)->request) {
+ ret = gpio_get_ops(dev)->request(dev, offset, label);
+ if (ret) {
+ free(str);
+ return ret;
+ }
+ }
+ uc_priv->name[offset] = str;
+
+ return 0;
+}
+
+/**
+ * gpio_requestf() - [COMPAT] Request GPIO
+ * @gpio: GPIO number
+ * @fmt: Format string for the requested GPIO
+ * @...: Arguments for the printf() format string
+ *
+ * This function implements the API that's compatible with current
+ * GPIO API used in U-Boot. The request is forwarded to particular
+ * GPIO driver. Returns 0 on success, negative value on error.
+ */
+int gpio_requestf(unsigned gpio, const char *fmt, ...)
+{
+ va_list args;
+ char buf[40];
- return gpio_get_ops(dev)->request(dev, offset, label);
+ va_start(args, fmt);
+ vscnprintf(buf, sizeof(buf), fmt, args);
+ va_end(args);
+ return gpio_request(gpio, buf);
}
/**
*/
int gpio_free(unsigned gpio)
{
+ struct gpio_dev_priv *uc_priv;
unsigned int offset;
struct udevice *dev;
int ret;
if (ret)
return ret;
- if (!gpio_get_ops(dev)->free)
- return 0;
- return gpio_get_ops(dev)->free(dev, offset);
+ uc_priv = dev->uclass_priv;
+ if (!uc_priv->name[offset])
+ return -ENXIO;
+ if (gpio_get_ops(dev)->free) {
+ ret = gpio_get_ops(dev)->free(dev, offset);
+ if (ret)
+ return ret;
+ }
+
+ free(uc_priv->name[offset]);
+ uc_priv->name[offset] = NULL;
+
+ return 0;
+}
+
+static int check_reserved(struct udevice *dev, unsigned offset,
+ const char *func)
+{
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+
+ if (!uc_priv->name[offset]) {
+ printf("%s: %s: error: gpio %s%d not reserved\n",
+ dev->name, func,
+ uc_priv->bank_name ? uc_priv->bank_name : "", offset);
+ return -EBUSY;
+ }
+
+ return 0;
}
/**
ret = gpio_to_device(gpio, &dev, &offset);
if (ret)
return ret;
+ ret = check_reserved(dev, offset, "dir_input");
- return gpio_get_ops(dev)->direction_input(dev, offset);
+ return ret ? ret : gpio_get_ops(dev)->direction_input(dev, offset);
}
/**
ret = gpio_to_device(gpio, &dev, &offset);
if (ret)
return ret;
+ ret = check_reserved(dev, offset, "dir_output");
- return gpio_get_ops(dev)->direction_output(dev, offset, value);
+ return ret ? ret :
+ gpio_get_ops(dev)->direction_output(dev, offset, value);
}
/**
ret = gpio_to_device(gpio, &dev, &offset);
if (ret)
return ret;
+ ret = check_reserved(dev, offset, "get_value");
- return gpio_get_ops(dev)->get_value(dev, offset);
+ return ret ? ret : gpio_get_ops(dev)->get_value(dev, offset);
}
/**
ret = gpio_to_device(gpio, &dev, &offset);
if (ret)
return ret;
+ ret = check_reserved(dev, offset, "set_value");
- return gpio_get_ops(dev)->set_value(dev, offset, value);
+ return ret ? ret : gpio_get_ops(dev)->set_value(dev, offset, value);
}
const char *gpio_get_bank_info(struct udevice *dev, int *bit_count)
return priv->bank_name;
}
+static const char * const gpio_function[GPIOF_COUNT] = {
+ "input",
+ "output",
+ "unused",
+ "unknown",
+ "func",
+};
+
+int get_function(struct udevice *dev, int offset, bool skip_unused,
+ const char **namep)
+{
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+ struct dm_gpio_ops *ops = gpio_get_ops(dev);
+
+ BUILD_BUG_ON(GPIOF_COUNT != ARRAY_SIZE(gpio_function));
+ if (!device_active(dev))
+ return -ENODEV;
+ if (offset < 0 || offset >= uc_priv->gpio_count)
+ return -EINVAL;
+ if (namep)
+ *namep = uc_priv->name[offset];
+ if (skip_unused && !uc_priv->name[offset])
+ return GPIOF_UNUSED;
+ if (ops->get_function) {
+ int ret;
+
+ ret = ops->get_function(dev, offset);
+ if (ret < 0)
+ return ret;
+ if (ret >= ARRAY_SIZE(gpio_function))
+ return -ENODATA;
+ return ret;
+ }
+
+ return GPIOF_UNKNOWN;
+}
+
+int gpio_get_function(struct udevice *dev, int offset, const char **namep)
+{
+ return get_function(dev, offset, true, namep);
+}
+
+int gpio_get_raw_function(struct udevice *dev, int offset, const char **namep)
+{
+ return get_function(dev, offset, false, namep);
+}
+
+int gpio_get_status(struct udevice *dev, int offset, char *buf, int buffsize)
+{
+ struct dm_gpio_ops *ops = gpio_get_ops(dev);
+ struct gpio_dev_priv *priv;
+ char *str = buf;
+ int func;
+ int ret;
+ int len;
+
+ BUILD_BUG_ON(GPIOF_COUNT != ARRAY_SIZE(gpio_function));
+
+ *buf = 0;
+ priv = dev->uclass_priv;
+ ret = gpio_get_raw_function(dev, offset, NULL);
+ if (ret < 0)
+ return ret;
+ func = ret;
+ len = snprintf(str, buffsize, "%s%d: %s",
+ priv->bank_name ? priv->bank_name : "",
+ offset, gpio_function[func]);
+ if (func == GPIOF_INPUT || func == GPIOF_OUTPUT ||
+ func == GPIOF_UNUSED) {
+ const char *label;
+ bool used;
+
+ ret = ops->get_value(dev, offset);
+ if (ret < 0)
+ return ret;
+ used = gpio_get_function(dev, offset, &label) != GPIOF_UNUSED;
+ snprintf(str + len, buffsize - len, ": %d [%c]%s%s",
+ ret,
+ used ? 'x' : ' ',
+ used ? " " : "",
+ label ? label : "");
+ }
+
+ return 0;
+}
+
/* We need to renumber the GPIOs when any driver is probed/removed */
-static int gpio_renumber(void)
+static int gpio_renumber(struct udevice *removed_dev)
{
struct gpio_dev_priv *uc_priv;
struct udevice *dev;
/* Ensure that we have a base for each bank */
base = 0;
uclass_foreach_dev(dev, uc) {
- if (device_active(dev)) {
+ if (device_active(dev) && dev != removed_dev) {
uc_priv = dev->uclass_priv;
uc_priv->gpio_base = base;
base += uc_priv->gpio_count;
static int gpio_post_probe(struct udevice *dev)
{
- return gpio_renumber();
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+
+ uc_priv->name = calloc(uc_priv->gpio_count, sizeof(char *));
+ if (!uc_priv->name)
+ return -ENOMEM;
+
+ return gpio_renumber(NULL);
}
static int gpio_pre_remove(struct udevice *dev)
{
- return gpio_renumber();
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+ int i;
+
+ for (i = 0; i < uc_priv->gpio_count; i++) {
+ if (uc_priv->name[i])
+ free(uc_priv->name[i]);
+ }
+ free(uc_priv->name);
+
+ return gpio_renumber(dev);
}
UCLASS_DRIVER(gpio) = {
*/
#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
#include <pci.h>
#include <asm/gpio.h>
#include <asm/io.h>
+#define GPIO_PER_BANK 32
+
/* Where in config space is the register that points to the GPIO registers? */
#define PCI_CFG_GPIOBASE 0x48
-#define NUM_BANKS 3
-
-/* Within the I/O space, where are the registers to control the GPIOs? */
-static struct {
- u8 use_sel;
- u8 io_sel;
- u8 lvl;
-} gpio_bank[NUM_BANKS] = {
- { 0x00, 0x04, 0x0c }, /* Bank 0 */
- { 0x30, 0x34, 0x38 }, /* Bank 1 */
- { 0x40, 0x44, 0x48 } /* Bank 2 */
+struct ich6_bank_priv {
+ /* These are I/O addresses */
+ uint32_t use_sel;
+ uint32_t io_sel;
+ uint32_t lvl;
};
-static pci_dev_t dev; /* handle for 0:1f:0 */
-static u32 gpiobase; /* offset into I/O space */
-static int found_it_once; /* valid GPIO device? */
-static u32 lock[NUM_BANKS]; /* "lock" for access to pins */
-
-static int bad_arg(int num, int *bank, int *bitnum)
-{
- int i = num / 32;
- int j = num % 32;
-
- if (num < 0 || i > NUM_BANKS) {
- debug("%s: bogus gpio num: %d\n", __func__, num);
- return -1;
- }
- *bank = i;
- *bitnum = j;
- return 0;
-}
-
-static int mark_gpio(int bank, int bitnum)
-{
- if (lock[bank] & (1UL << bitnum)) {
- debug("%s: %d.%d already marked\n", __func__, bank, bitnum);
- return -1;
- }
- lock[bank] |= (1 << bitnum);
- return 0;
-}
-
-static void clear_gpio(int bank, int bitnum)
-{
- lock[bank] &= ~(1 << bitnum);
-}
-
-static int notmine(int num, int *bank, int *bitnum)
-{
- if (bad_arg(num, bank, bitnum))
- return -1;
- return !(lock[*bank] & (1UL << *bitnum));
-}
-
-static int gpio_init(void)
+static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
{
+ struct ich6_bank_platdata *plat = dev_get_platdata(dev);
+ pci_dev_t pci_dev; /* handle for 0:1f:0 */
u8 tmpbyte;
u16 tmpword;
u32 tmplong;
-
- /* Have we already done this? */
- if (found_it_once)
- return 0;
+ u32 gpiobase;
+ int offset;
/* Where should it be? */
- dev = PCI_BDF(0, 0x1f, 0);
+ pci_dev = PCI_BDF(0, 0x1f, 0);
/* Is the device present? */
- pci_read_config_word(dev, PCI_VENDOR_ID, &tmpword);
+ pci_read_config_word(pci_dev, PCI_VENDOR_ID, &tmpword);
if (tmpword != PCI_VENDOR_ID_INTEL) {
debug("%s: wrong VendorID\n", __func__);
- return -1;
+ return -ENODEV;
}
- pci_read_config_word(dev, PCI_DEVICE_ID, &tmpword);
+ pci_read_config_word(pci_dev, PCI_DEVICE_ID, &tmpword);
debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL, tmpword);
/*
* We'd like to validate the Device ID too, but pretty much any
*/
/* I/O should already be enabled (it's a RO bit). */
- pci_read_config_word(dev, PCI_COMMAND, &tmpword);
+ pci_read_config_word(pci_dev, PCI_COMMAND, &tmpword);
if (!(tmpword & PCI_COMMAND_IO)) {
debug("%s: device IO not enabled\n", __func__);
- return -1;
+ return -ENODEV;
}
/* Header Type must be normal (bits 6-0 only; see spec.) */
- pci_read_config_byte(dev, PCI_HEADER_TYPE, &tmpbyte);
+ pci_read_config_byte(pci_dev, PCI_HEADER_TYPE, &tmpbyte);
if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) {
debug("%s: invalid Header type\n", __func__);
- return -1;
+ return -ENODEV;
}
/* Base Class must be a bridge device */
- pci_read_config_byte(dev, PCI_CLASS_CODE, &tmpbyte);
+ pci_read_config_byte(pci_dev, PCI_CLASS_CODE, &tmpbyte);
if (tmpbyte != PCI_CLASS_CODE_BRIDGE) {
debug("%s: invalid class\n", __func__);
- return -1;
+ return -ENODEV;
}
/* Sub Class must be ISA */
- pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &tmpbyte);
+ pci_read_config_byte(pci_dev, PCI_CLASS_SUB_CODE, &tmpbyte);
if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) {
debug("%s: invalid subclass\n", __func__);
- return -1;
+ return -ENODEV;
}
/* Programming Interface must be 0x00 (no others exist) */
- pci_read_config_byte(dev, PCI_CLASS_PROG, &tmpbyte);
+ pci_read_config_byte(pci_dev, PCI_CLASS_PROG, &tmpbyte);
if (tmpbyte != 0x00) {
debug("%s: invalid interface type\n", __func__);
- return -1;
+ return -ENODEV;
}
/*
* that it was unused (or undocumented). Check that it looks
* okay: not all ones or zeros, and mapped to I/O space (bit 0).
*/
- pci_read_config_dword(dev, PCI_CFG_GPIOBASE, &tmplong);
+ pci_read_config_dword(pci_dev, PCI_CFG_GPIOBASE, &tmplong);
if (tmplong == 0x00000000 || tmplong == 0xffffffff ||
!(tmplong & 0x00000001)) {
debug("%s: unexpected GPIOBASE value\n", __func__);
- return -1;
+ return -ENODEV;
}
/*
* an I/O address, not a memory address, so mask that off.
*/
gpiobase = tmplong & 0xfffffffe;
+ offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
+ if (offset == -1) {
+ debug("%s: Invalid register offset %d\n", __func__, offset);
+ return -EINVAL;
+ }
+ plat->base_addr = gpiobase + offset;
+ plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ "bank-name", NULL);
- /* Finally. These are the droids we're looking for. */
- found_it_once = 1;
return 0;
}
-int gpio_request(unsigned num, const char *label /* UNUSED */)
+int ich6_gpio_probe(struct udevice *dev)
{
- u32 tmplong;
- int i = 0, j = 0;
+ struct ich6_bank_platdata *plat = dev_get_platdata(dev);
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+ struct ich6_bank_priv *bank = dev_get_priv(dev);
+
+ uc_priv->gpio_count = GPIO_PER_BANK;
+ uc_priv->bank_name = plat->bank_name;
+ bank->use_sel = plat->base_addr;
+ bank->io_sel = plat->base_addr + 4;
+ bank->lvl = plat->base_addr + 8;
- /* Is the hardware ready? */
- if (gpio_init())
- return -1;
+ return 0;
+}
- if (bad_arg(num, &i, &j))
- return -1;
+int ich6_gpio_request(struct udevice *dev, unsigned offset, const char *label)
+{
+ struct ich6_bank_priv *bank = dev_get_priv(dev);
+ u32 tmplong;
/*
* Make sure that the GPIO pin we want isn't already in use for some
* built-in hardware function. We have to check this for every
* requested pin.
*/
- tmplong = inl(gpiobase + gpio_bank[i].use_sel);
- if (!(tmplong & (1UL << j))) {
+ tmplong = inl(bank->use_sel);
+ if (!(tmplong & (1UL << offset))) {
debug("%s: gpio %d is reserved for internal use\n", __func__,
- num);
- return -1;
+ offset);
+ return -EPERM;
}
- return mark_gpio(i, j);
-}
-
-int gpio_free(unsigned num)
-{
- int i = 0, j = 0;
-
- if (notmine(num, &i, &j))
- return -1;
-
- clear_gpio(i, j);
return 0;
}
-int gpio_direction_input(unsigned num)
+static int ich6_gpio_direction_input(struct udevice *dev, unsigned offset)
{
+ struct ich6_bank_priv *bank = dev_get_priv(dev);
u32 tmplong;
- int i = 0, j = 0;
-
- if (notmine(num, &i, &j))
- return -1;
- tmplong = inl(gpiobase + gpio_bank[i].io_sel);
- tmplong |= (1UL << j);
- outl(gpiobase + gpio_bank[i].io_sel, tmplong);
+ tmplong = inl(bank->io_sel);
+ tmplong |= (1UL << offset);
+ outl(bank->io_sel, tmplong);
return 0;
}
-int gpio_direction_output(unsigned num, int value)
+static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset,
+ int value)
{
+ struct ich6_bank_priv *bank = dev_get_priv(dev);
u32 tmplong;
- int i = 0, j = 0;
- if (notmine(num, &i, &j))
- return -1;
-
- tmplong = inl(gpiobase + gpio_bank[i].io_sel);
- tmplong &= ~(1UL << j);
- outl(gpiobase + gpio_bank[i].io_sel, tmplong);
+ tmplong = inl(bank->io_sel);
+ tmplong &= ~(1UL << offset);
+ outl(bank->io_sel, tmplong);
return 0;
}
-int gpio_get_value(unsigned num)
+static int ich6_gpio_get_value(struct udevice *dev, unsigned offset)
+
{
+ struct ich6_bank_priv *bank = dev_get_priv(dev);
u32 tmplong;
- int i = 0, j = 0;
int r;
- if (notmine(num, &i, &j))
- return -1;
-
- tmplong = inl(gpiobase + gpio_bank[i].lvl);
- r = (tmplong & (1UL << j)) ? 1 : 0;
+ tmplong = inl(bank->lvl);
+ r = (tmplong & (1UL << offset)) ? 1 : 0;
return r;
}
-int gpio_set_value(unsigned num, int value)
+static int ich6_gpio_set_value(struct udevice *dev, unsigned offset,
+ int value)
{
+ struct ich6_bank_priv *bank = dev_get_priv(dev);
u32 tmplong;
- int i = 0, j = 0;
- if (notmine(num, &i, &j))
- return -1;
-
- tmplong = inl(gpiobase + gpio_bank[i].lvl);
+ tmplong = inl(bank->lvl);
if (value)
- tmplong |= (1UL << j);
+ tmplong |= (1UL << offset);
else
- tmplong &= ~(1UL << j);
- outl(gpiobase + gpio_bank[i].lvl, tmplong);
+ tmplong &= ~(1UL << offset);
+ outl(bank->lvl, tmplong);
return 0;
}
+
+static int ich6_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+ struct ich6_bank_priv *bank = dev_get_priv(dev);
+ u32 mask = 1UL << offset;
+
+ if (!(inl(bank->use_sel) & mask))
+ return GPIOF_FUNC;
+ if (inl(bank->io_sel) & mask)
+ return GPIOF_INPUT;
+ else
+ return GPIOF_OUTPUT;
+}
+
+static const struct dm_gpio_ops gpio_ich6_ops = {
+ .request = ich6_gpio_request,
+ .direction_input = ich6_gpio_direction_input,
+ .direction_output = ich6_gpio_direction_output,
+ .get_value = ich6_gpio_get_value,
+ .set_value = ich6_gpio_set_value,
+ .get_function = ich6_gpio_get_function,
+};
+
+static const struct udevice_id intel_ich6_gpio_ids[] = {
+ { .compatible = "intel,ich6-gpio" },
+ { }
+};
+
+U_BOOT_DRIVER(gpio_ich6) = {
+ .name = "gpio_ich6",
+ .id = UCLASS_GPIO,
+ .of_match = intel_ich6_gpio_ids,
+ .ops = &gpio_ich6_ops,
+ .ofdata_to_platdata = gpio_ich6_ofdata_to_platdata,
+ .probe = ich6_gpio_probe,
+ .priv_auto_alloc_size = sizeof(struct ich6_bank_priv),
+ .platdata_auto_alloc_size = sizeof(struct ich6_bank_platdata),
+};
u = readl(GPIO_IO_CONF(pin));
}
-void __set_level(unsigned pin, int high)
+static void __set_level(unsigned pin, int high)
{
u32 u;
writel(u, GPIO_OUT(pin));
}
-void __set_blinking(unsigned pin, int blink)
+static void __set_blinking(unsigned pin, int blink)
{
u32 u;
MXC_GPIO_DIRECTION_OUT,
};
-#define GPIO_NAME_SIZE 20
#define GPIO_PER_BANK 32
struct mxc_gpio_plat {
};
struct mxc_bank_info {
- char label[GPIO_PER_BANK][GPIO_NAME_SIZE];
struct gpio_regs *regs;
};
#endif
#ifdef CONFIG_DM_GPIO
-/**
- * gpio_is_requested() - check if a GPIO has been requested
- *
- * @bank: Bank to check
- * @offset: GPIO offset within bank to check
- * @return true if marked as requested, false if not
- */
-static inline bool gpio_is_requested(struct mxc_bank_info *bank, int offset)
-{
- return *bank->label[offset] != '\0';
-}
-
static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)
{
u32 val;
return (readl(®s->gpio_psr) >> offset) & 0x01;
}
-static int mxc_gpio_bank_get_output_value(struct gpio_regs *regs, int offset)
-{
- return (readl(®s->gpio_dr) >> offset) & 0x01;
-}
-
-static int check_requested(struct udevice *dev, unsigned offset,
- const char *func)
-{
- struct mxc_bank_info *bank = dev_get_priv(dev);
- struct gpio_dev_priv *uc_priv = dev->uclass_priv;
-
- if (!gpio_is_requested(bank, offset)) {
- printf("mxc_gpio: %s: error: gpio %s%d not requested\n",
- func, uc_priv->bank_name, offset);
- return -EPERM;
- }
-
- return 0;
-}
-
/* set GPIO pin 'gpio' as an input */
static int mxc_gpio_direction_input(struct udevice *dev, unsigned offset)
{
struct mxc_bank_info *bank = dev_get_priv(dev);
- int ret;
-
- ret = check_requested(dev, offset, __func__);
- if (ret)
- return ret;
/* Configure GPIO direction as input. */
mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_IN);
int value)
{
struct mxc_bank_info *bank = dev_get_priv(dev);
- int ret;
-
- ret = check_requested(dev, offset, __func__);
- if (ret)
- return ret;
/* Configure GPIO output value. */
mxc_gpio_bank_set_value(bank->regs, offset, value);
static int mxc_gpio_get_value(struct udevice *dev, unsigned offset)
{
struct mxc_bank_info *bank = dev_get_priv(dev);
- int ret;
-
- ret = check_requested(dev, offset, __func__);
- if (ret)
- return ret;
return mxc_gpio_bank_get_value(bank->regs, offset);
}
int value)
{
struct mxc_bank_info *bank = dev_get_priv(dev);
- int ret;
-
- ret = check_requested(dev, offset, __func__);
- if (ret)
- return ret;
mxc_gpio_bank_set_value(bank->regs, offset, value);
return 0;
}
-static int mxc_gpio_get_state(struct udevice *dev, unsigned int offset,
- char *buf, int bufsize)
-{
- struct gpio_dev_priv *uc_priv = dev->uclass_priv;
- struct mxc_bank_info *bank = dev_get_priv(dev);
- const char *label;
- bool requested;
- bool is_output;
- int size;
-
- label = bank->label[offset];
- is_output = mxc_gpio_is_output(bank->regs, offset);
- size = snprintf(buf, bufsize, "%s%d: ",
- uc_priv->bank_name ? uc_priv->bank_name : "", offset);
- buf += size;
- bufsize -= size;
- requested = gpio_is_requested(bank, offset);
- snprintf(buf, bufsize, "%s: %d [%c]%s%s",
- is_output ? "out" : " in",
- is_output ?
- mxc_gpio_bank_get_output_value(bank->regs, offset) :
- mxc_gpio_bank_get_value(bank->regs, offset),
- requested ? 'x' : ' ',
- requested ? " " : "",
- label);
-
- return 0;
-}
-
-static int mxc_gpio_request(struct udevice *dev, unsigned offset,
- const char *label)
-{
- struct mxc_bank_info *bank = dev_get_priv(dev);
-
- if (gpio_is_requested(bank, offset))
- return -EBUSY;
-
- strncpy(bank->label[offset], label, GPIO_NAME_SIZE);
- bank->label[offset][GPIO_NAME_SIZE - 1] = '\0';
-
- return 0;
-}
-
-static int mxc_gpio_free(struct udevice *dev, unsigned offset)
-{
- struct mxc_bank_info *bank = dev_get_priv(dev);
- int ret;
-
- ret = check_requested(dev, offset, __func__);
- if (ret)
- return ret;
- bank->label[offset][0] = '\0';
-
- return 0;
-}
-
static int mxc_gpio_get_function(struct udevice *dev, unsigned offset)
{
struct mxc_bank_info *bank = dev_get_priv(dev);
- if (!gpio_is_requested(bank, offset))
- return GPIOF_UNUSED;
-
/* GPIOF_FUNC is not implemented yet */
if (mxc_gpio_is_output(bank->regs, offset))
return GPIOF_OUTPUT;
}
static const struct dm_gpio_ops gpio_mxc_ops = {
- .request = mxc_gpio_request,
- .free = mxc_gpio_free,
.direction_input = mxc_gpio_direction_input,
.direction_output = mxc_gpio_direction_output,
.get_value = mxc_gpio_get_value,
.set_value = mxc_gpio_set_value,
.get_function = mxc_gpio_get_function,
- .get_state = mxc_gpio_get_state,
};
static const struct mxc_gpio_plat mxc_plat[] = {
* Written by Juha Yrjölä <juha.yrjola@nokia.com>
*/
#include <common.h>
+#include <dm.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/errno.h>
#define OMAP_GPIO_DIR_OUT 0
#define OMAP_GPIO_DIR_IN 1
-static inline const struct gpio_bank *get_gpio_bank(int gpio)
-{
- return &omap_gpio_bank[gpio >> 5];
-}
+#ifdef CONFIG_DM_GPIO
+
+#define GPIO_PER_BANK 32
+
+struct gpio_bank {
+ /* TODO(sjg@chromium.org): Can we use a struct here? */
+ void *base; /* address of registers in physical memory */
+ enum gpio_method method;
+};
+
+#endif
static inline int get_gpio_index(int gpio)
{
return (gpio >= 0) && (gpio < OMAP_MAX_GPIO);
}
-static int check_gpio(int gpio)
-{
- if (!gpio_is_valid(gpio)) {
- printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
- return -1;
- }
- return 0;
-}
-
static void _set_gpio_direction(const struct gpio_bank *bank, int gpio,
int is_input)
{
__raw_writel(l, reg);
}
+static int _get_gpio_value(const struct gpio_bank *bank, int gpio)
+{
+ void *reg = bank->base;
+ int input;
+
+ switch (bank->method) {
+ case METHOD_GPIO_24XX:
+ input = _get_gpio_direction(bank, gpio);
+ switch (input) {
+ case OMAP_GPIO_DIR_IN:
+ reg += OMAP_GPIO_DATAIN;
+ break;
+ case OMAP_GPIO_DIR_OUT:
+ reg += OMAP_GPIO_DATAOUT;
+ break;
+ default:
+ return -1;
+ }
+ break;
+ default:
+ return -1;
+ }
+
+ return (__raw_readl(reg) & (1 << gpio)) != 0;
+}
+
+#ifndef CONFIG_DM_GPIO
+
+static inline const struct gpio_bank *get_gpio_bank(int gpio)
+{
+ return &omap_gpio_bank[gpio >> 5];
+}
+
+static int check_gpio(int gpio)
+{
+ if (!gpio_is_valid(gpio)) {
+ printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
+ return -1;
+ }
+ return 0;
+}
+
/**
* Set value of the specified gpio
*/
int gpio_get_value(unsigned gpio)
{
const struct gpio_bank *bank;
- void *reg;
- int input;
if (check_gpio(gpio) < 0)
return -1;
bank = get_gpio_bank(gpio);
- reg = bank->base;
- switch (bank->method) {
- case METHOD_GPIO_24XX:
- input = _get_gpio_direction(bank, get_gpio_index(gpio));
- switch (input) {
- case OMAP_GPIO_DIR_IN:
- reg += OMAP_GPIO_DATAIN;
- break;
- case OMAP_GPIO_DIR_OUT:
- reg += OMAP_GPIO_DATAOUT;
- break;
- default:
- return -1;
- }
- break;
- default:
- return -1;
- }
- return (__raw_readl(reg)
- & (1 << get_gpio_index(gpio))) != 0;
+
+ return _get_gpio_value(bank, get_gpio_index(gpio));
}
/**
{
return 0;
}
+
+#else /* new driver model interface CONFIG_DM_GPIO */
+
+/* set GPIO pin 'gpio' as an input */
+static int omap_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+ struct gpio_bank *bank = dev_get_priv(dev);
+
+ /* Configure GPIO direction as input. */
+ _set_gpio_direction(bank, offset, 1);
+
+ return 0;
+}
+
+/* set GPIO pin 'gpio' as an output, with polarity 'value' */
+static int omap_gpio_direction_output(struct udevice *dev, unsigned offset,
+ int value)
+{
+ struct gpio_bank *bank = dev_get_priv(dev);
+
+ _set_gpio_dataout(bank, offset, value);
+ _set_gpio_direction(bank, offset, 0);
+
+ return 0;
+}
+
+/* read GPIO IN value of pin 'gpio' */
+static int omap_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+ struct gpio_bank *bank = dev_get_priv(dev);
+
+ return _get_gpio_value(bank, offset);
+}
+
+/* write GPIO OUT value to pin 'gpio' */
+static int omap_gpio_set_value(struct udevice *dev, unsigned offset,
+ int value)
+{
+ struct gpio_bank *bank = dev_get_priv(dev);
+
+ _set_gpio_dataout(bank, offset, value);
+
+ return 0;
+}
+
+static int omap_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+ struct gpio_bank *bank = dev_get_priv(dev);
+
+ /* GPIOF_FUNC is not implemented yet */
+ if (_get_gpio_direction(bank->base, offset) == OMAP_GPIO_DIR_OUT)
+ return GPIOF_OUTPUT;
+ else
+ return GPIOF_INPUT;
+}
+
+static const struct dm_gpio_ops gpio_omap_ops = {
+ .direction_input = omap_gpio_direction_input,
+ .direction_output = omap_gpio_direction_output,
+ .get_value = omap_gpio_get_value,
+ .set_value = omap_gpio_set_value,
+ .get_function = omap_gpio_get_function,
+};
+
+static int omap_gpio_probe(struct udevice *dev)
+{
+ struct gpio_bank *bank = dev_get_priv(dev);
+ struct omap_gpio_platdata *plat = dev_get_platdata(dev);
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+ char name[18], *str;
+
+ sprintf(name, "GPIO%d_", plat->bank_index);
+ str = strdup(name);
+ if (!str)
+ return -ENOMEM;
+ uc_priv->bank_name = str;
+ uc_priv->gpio_count = GPIO_PER_BANK;
+ bank->base = (void *)plat->base;
+ bank->method = plat->method;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(gpio_omap) = {
+ .name = "gpio_omap",
+ .id = UCLASS_GPIO,
+ .ops = &gpio_omap_ops,
+ .probe = omap_gpio_probe,
+ .priv_auto_alloc_size = sizeof(struct gpio_bank),
+};
+
+#endif /* CONFIG_DM_GPIO */
#define RATE_MASK(gpio) (0x1 << (gpio + 16))
#define RATE_SET(gpio) (0x1 << (gpio + 16))
-#define GPIO_NAME_SIZE 20
-
/* Platform data for each bank */
struct exynos_gpio_platdata {
struct s5p_gpio_bank *bank;
/* Information about each bank at run-time */
struct exynos_bank_info {
- char label[GPIO_PER_BANK][GPIO_NAME_SIZE];
struct s5p_gpio_bank *bank;
};
/* Driver model interface */
#ifndef CONFIG_SPL_BUILD
-static int exynos_gpio_get_state(struct udevice *dev, unsigned int offset,
- char *buf, int bufsize)
-{
- struct gpio_dev_priv *uc_priv = dev->uclass_priv;
- struct exynos_bank_info *state = dev_get_priv(dev);
- const char *label;
- bool is_output;
- int size;
- int cfg;
-
- label = state->label[offset];
- cfg = s5p_gpio_get_cfg_pin(state->bank, offset);
- is_output = cfg == S5P_GPIO_OUTPUT;
- size = snprintf(buf, bufsize, "%s%d: ",
- uc_priv->bank_name ? uc_priv->bank_name : "", offset);
- buf += size;
- bufsize -= size;
- if (is_output || cfg == S5P_GPIO_INPUT) {
- snprintf(buf, bufsize, "%s: %d [%c]%s%s",
- is_output ? "out" : " in",
- s5p_gpio_get_value(state->bank, offset),
- *label ? 'x' : ' ',
- *label ? " " : "",
- label);
- } else {
- snprintf(buf, bufsize, "sfpio");
- }
-
- return 0;
-}
-
-static int check_reserved(struct udevice *dev, unsigned offset,
- const char *func)
-{
- struct exynos_bank_info *state = dev_get_priv(dev);
- struct gpio_dev_priv *uc_priv = dev->uclass_priv;
-
- if (!*state->label[offset]) {
- printf("exynos_gpio: %s: error: gpio %s%d not reserved\n",
- func, uc_priv->bank_name, offset);
- return -EPERM;
- }
-
- return 0;
-}
-
/* set GPIO pin 'gpio' as an input */
static int exynos_gpio_direction_input(struct udevice *dev, unsigned offset)
{
struct exynos_bank_info *state = dev_get_priv(dev);
- int ret;
-
- ret = check_reserved(dev, offset, __func__);
- if (ret)
- return ret;
/* Configure GPIO direction as input. */
s5p_gpio_cfg_pin(state->bank, offset, S5P_GPIO_INPUT);
int value)
{
struct exynos_bank_info *state = dev_get_priv(dev);
- int ret;
-
- ret = check_reserved(dev, offset, __func__);
- if (ret)
- return ret;
/* Configure GPIO output value. */
s5p_gpio_set_value(state->bank, offset, value);
static int exynos_gpio_get_value(struct udevice *dev, unsigned offset)
{
struct exynos_bank_info *state = dev_get_priv(dev);
- int ret;
-
- ret = check_reserved(dev, offset, __func__);
- if (ret)
- return ret;
return s5p_gpio_get_value(state->bank, offset);
}
int value)
{
struct exynos_bank_info *state = dev_get_priv(dev);
- int ret;
-
- ret = check_reserved(dev, offset, __func__);
- if (ret)
- return ret;
s5p_gpio_set_value(state->bank, offset, value);
return 0;
}
-
-static int exynos_gpio_request(struct udevice *dev, unsigned offset,
- const char *label)
-{
- struct exynos_bank_info *state = dev_get_priv(dev);
-
- if (*state->label[offset])
- return -EBUSY;
-
- strncpy(state->label[offset], label, GPIO_NAME_SIZE);
- state->label[offset][GPIO_NAME_SIZE - 1] = '\0';
-
- return 0;
-}
-
-static int exynos_gpio_free(struct udevice *dev, unsigned offset)
-{
- struct exynos_bank_info *state = dev_get_priv(dev);
- int ret;
-
- ret = check_reserved(dev, offset, __func__);
- if (ret)
- return ret;
- state->label[offset][0] = '\0';
-
- return 0;
-}
#endif /* nCONFIG_SPL_BUILD */
/*
struct exynos_bank_info *state = dev_get_priv(dev);
int cfg;
- if (!*state->label[offset])
- return GPIOF_UNUSED;
cfg = s5p_gpio_get_cfg_pin(state->bank, offset);
if (cfg == S5P_GPIO_OUTPUT)
return GPIOF_OUTPUT;
}
static const struct dm_gpio_ops gpio_exynos_ops = {
- .request = exynos_gpio_request,
- .free = exynos_gpio_free,
.direction_input = exynos_gpio_direction_input,
.direction_output = exynos_gpio_direction_output,
.get_value = exynos_gpio_get_value,
.set_value = exynos_gpio_set_value,
.get_function = exynos_gpio_get_function,
- .get_state = exynos_gpio_get_state,
};
static int gpio_exynos_probe(struct udevice *dev)
/* Flags for each GPIO */
#define GPIOF_OUTPUT (1 << 0) /* Currently set as an output */
#define GPIOF_HIGH (1 << 1) /* Currently set high */
-#define GPIOF_RESERVED (1 << 2) /* Is in use / requested */
struct gpio_state {
const char *label; /* label given by requester */
return 0;
}
-static int check_reserved(struct udevice *dev, unsigned offset,
- const char *func)
-{
- if (!get_gpio_flag(dev, offset, GPIOF_RESERVED)) {
- printf("sandbox_gpio: %s: error: offset %u not reserved\n",
- func, offset);
- return -1;
- }
-
- return 0;
-}
-
/*
* Back-channel sandbox-internal-only access to GPIO state
*/
{
debug("%s: offset:%u\n", __func__, offset);
- if (check_reserved(dev, offset, __func__))
- return -1;
-
return sandbox_gpio_set_direction(dev, offset, 0);
}
{
debug("%s: offset:%u, value = %d\n", __func__, offset, value);
- if (check_reserved(dev, offset, __func__))
- return -1;
-
return sandbox_gpio_set_direction(dev, offset, 1) |
sandbox_gpio_set_value(dev, offset, value);
}
{
debug("%s: offset:%u\n", __func__, offset);
- if (check_reserved(dev, offset, __func__))
- return -1;
-
return sandbox_gpio_get_value(dev, offset);
}
{
debug("%s: offset:%u, value = %d\n", __func__, offset, value);
- if (check_reserved(dev, offset, __func__))
- return -1;
-
if (!sandbox_gpio_get_direction(dev, offset)) {
printf("sandbox_gpio: error: set_value on input gpio %u\n",
offset);
return sandbox_gpio_set_value(dev, offset, value);
}
-static int sb_gpio_request(struct udevice *dev, unsigned offset,
- const char *label)
+static int sb_gpio_get_function(struct udevice *dev, unsigned offset)
{
- struct gpio_dev_priv *uc_priv = dev->uclass_priv;
- struct gpio_state *state = dev_get_priv(dev);
-
- debug("%s: offset:%u, label:%s\n", __func__, offset, label);
-
- if (offset >= uc_priv->gpio_count) {
- printf("sandbox_gpio: error: invalid gpio %u\n", offset);
- return -1;
- }
-
- if (get_gpio_flag(dev, offset, GPIOF_RESERVED)) {
- printf("sandbox_gpio: error: gpio %u already reserved\n",
- offset);
- return -1;
- }
-
- state[offset].label = label;
- return set_gpio_flag(dev, offset, GPIOF_RESERVED, 1);
-}
-
-static int sb_gpio_free(struct udevice *dev, unsigned offset)
-{
- struct gpio_state *state = dev_get_priv(dev);
-
- debug("%s: offset:%u\n", __func__, offset);
-
- if (check_reserved(dev, offset, __func__))
- return -1;
-
- state[offset].label = NULL;
- return set_gpio_flag(dev, offset, GPIOF_RESERVED, 0);
-}
-
-static int sb_gpio_get_state(struct udevice *dev, unsigned int offset,
- char *buf, int bufsize)
-{
- struct gpio_dev_priv *uc_priv = dev->uclass_priv;
- struct gpio_state *state = dev_get_priv(dev);
- const char *label;
-
- label = state[offset].label;
- snprintf(buf, bufsize, "%s%d: %s: %d [%c]%s%s",
- uc_priv->bank_name ? uc_priv->bank_name : "", offset,
- sandbox_gpio_get_direction(dev, offset) ? "out" : " in",
- sandbox_gpio_get_value(dev, offset),
- get_gpio_flag(dev, offset, GPIOF_RESERVED) ? 'x' : ' ',
- label ? " " : "",
- label ? label : "");
-
- return 0;
+ if (get_gpio_flag(dev, offset, GPIOF_OUTPUT))
+ return GPIOF_OUTPUT;
+ return GPIOF_INPUT;
}
static const struct dm_gpio_ops gpio_sandbox_ops = {
- .request = sb_gpio_request,
- .free = sb_gpio_free,
.direction_input = sb_gpio_direction_input,
.direction_output = sb_gpio_direction_output,
.get_value = sb_gpio_get_value,
.set_value = sb_gpio_set_value,
- .get_state = sb_gpio_get_state,
+ .get_function = sb_gpio_get_function,
};
static int sandbox_gpio_ofdata_to_platdata(struct udevice *dev)
return 0;
}
+static int gpio_sandbox_remove(struct udevice *dev)
+{
+ free(dev->priv);
+
+ return 0;
+}
+
static const struct udevice_id sandbox_gpio_ids[] = {
{ .compatible = "sandbox,gpio" },
{ }
.of_match = sandbox_gpio_ids,
.ofdata_to_platdata = sandbox_gpio_ofdata_to_platdata,
.probe = gpio_sandbox_probe,
+ .remove = gpio_sandbox_remove,
.ops = &gpio_sandbox_ops,
};
*/
#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
#include <asm/io.h>
#include <asm/gpio.h>
+#include <dm/device-internal.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SUNXI_GPIOS_PER_BANK SUNXI_GPIO_A_NR
+
+struct sunxi_gpio_platdata {
+ struct sunxi_gpio *regs;
+ const char *bank_name; /* Name of bank, e.g. "B" */
+ int gpio_count;
+};
+
+#ifndef CONFIG_DM_GPIO
static int sunxi_gpio_output(u32 pin, u32 val)
{
u32 dat;
return -1;
return group * 32 + pin;
}
+#endif
+
+#ifdef CONFIG_DM_GPIO
+static int sunxi_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+ struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+
+ sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_INPUT);
+
+ return 0;
+}
+
+static int sunxi_gpio_direction_output(struct udevice *dev, unsigned offset,
+ int value)
+{
+ struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+ u32 num = GPIO_NUM(offset);
+
+ sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT);
+ clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0);
+
+ return 0;
+}
+
+static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+ struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+ u32 num = GPIO_NUM(offset);
+ unsigned dat;
+
+ dat = readl(&plat->regs->dat);
+ dat >>= num;
+
+ return dat & 0x1;
+}
+
+static int sunxi_gpio_set_value(struct udevice *dev, unsigned offset,
+ int value)
+{
+ struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+ u32 num = GPIO_NUM(offset);
+
+ clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0);
+ return 0;
+}
+
+static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+ struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+ int func;
+
+ func = sunxi_gpio_get_cfgbank(plat->regs, offset);
+ if (func == SUNXI_GPIO_OUTPUT)
+ return GPIOF_OUTPUT;
+ else if (func == SUNXI_GPIO_INPUT)
+ return GPIOF_INPUT;
+ else
+ return GPIOF_FUNC;
+}
+
+static const struct dm_gpio_ops gpio_sunxi_ops = {
+ .direction_input = sunxi_gpio_direction_input,
+ .direction_output = sunxi_gpio_direction_output,
+ .get_value = sunxi_gpio_get_value,
+ .set_value = sunxi_gpio_set_value,
+ .get_function = sunxi_gpio_get_function,
+};
+
+/**
+ * Returns the name of a GPIO bank
+ *
+ * GPIO banks are named A, B, C, ...
+ *
+ * @bank: Bank number (0, 1..n-1)
+ * @return allocated string containing the name
+ */
+static char *gpio_bank_name(int bank)
+{
+ char *name;
+
+ name = malloc(2);
+ if (name) {
+ name[0] = 'A' + bank;
+ name[1] = '\0';
+ }
+
+ return name;
+}
+
+static int gpio_sunxi_probe(struct udevice *dev)
+{
+ struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+
+ /* Tell the uclass how many GPIOs we have */
+ if (plat) {
+ uc_priv->gpio_count = plat->gpio_count;
+ uc_priv->bank_name = plat->bank_name;
+ }
+
+ return 0;
+}
+/**
+ * We have a top-level GPIO device with no actual GPIOs. It has a child
+ * device for each Sunxi bank.
+ */
+static int gpio_sunxi_bind(struct udevice *parent)
+{
+ struct sunxi_gpio_platdata *plat = parent->platdata;
+ struct sunxi_gpio_reg *ctlr;
+ int bank;
+ int ret;
+
+ /* If this is a child device, there is nothing to do here */
+ if (plat)
+ return 0;
+
+ ctlr = (struct sunxi_gpio_reg *)fdtdec_get_addr(gd->fdt_blob,
+ parent->of_offset, "reg");
+ for (bank = 0; bank < SUNXI_GPIO_BANKS; bank++) {
+ struct sunxi_gpio_platdata *plat;
+ struct udevice *dev;
+
+ plat = calloc(1, sizeof(*plat));
+ if (!plat)
+ return -ENOMEM;
+ plat->regs = &ctlr->gpio_bank[bank];
+ plat->bank_name = gpio_bank_name(bank);
+ plat->gpio_count = SUNXI_GPIOS_PER_BANK;
+
+ ret = device_bind(parent, parent->driver,
+ plat->bank_name, plat, -1, &dev);
+ if (ret)
+ return ret;
+ dev->of_offset = parent->of_offset;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id sunxi_gpio_ids[] = {
+ { .compatible = "allwinner,sun7i-a20-pinctrl" },
+ { }
+};
+
+U_BOOT_DRIVER(gpio_sunxi) = {
+ .name = "gpio_sunxi",
+ .id = UCLASS_GPIO,
+ .ops = &gpio_sunxi_ops,
+ .of_match = sunxi_gpio_ids,
+ .bind = gpio_sunxi_bind,
+ .probe = gpio_sunxi_probe,
+};
+#endif
/* Information about each port at run-time */
struct tegra_port_info {
- char label[TEGRA_GPIOS_PER_PORT][GPIO_NAME_SIZE];
struct gpio_ctlr_bank *bank;
int base_gpio; /* Port number for this port (0, 1,.., n-1) */
};
writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
}
-static int check_reserved(struct udevice *dev, unsigned offset,
- const char *func)
-{
- struct tegra_port_info *state = dev_get_priv(dev);
- struct gpio_dev_priv *uc_priv = dev->uclass_priv;
-
- if (!*state->label[offset]) {
- printf("tegra_gpio: %s: error: gpio %s%d not reserved\n",
- func, uc_priv->bank_name, offset);
- return -EBUSY;
- }
-
- return 0;
-}
-
/* set GPIO pin 'gpio' as an output, with polarity 'value' */
int tegra_spl_gpio_direction_output(int gpio, int value)
{
{
struct tegra_port_info *state = dev_get_priv(dev);
- if (!label)
- return -EINVAL;
-
- if (*state->label[offset])
- return -EBUSY;
-
- strncpy(state->label[offset], label, GPIO_NAME_SIZE);
- state->label[offset][GPIO_NAME_SIZE - 1] = '\0';
-
/* Configure as a GPIO */
set_config(state->base_gpio + offset, 1);
return 0;
}
-static int tegra_gpio_free(struct udevice *dev, unsigned offset)
-{
- struct tegra_port_info *state = dev_get_priv(dev);
- int ret;
-
- ret = check_reserved(dev, offset, __func__);
- if (ret)
- return ret;
- state->label[offset][0] = '\0';
-
- return 0;
-}
-
-/* read GPIO OUT value of pin 'gpio' */
-static int tegra_gpio_get_output_value(unsigned gpio)
-{
- struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
- struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
- int val;
-
- debug("gpio_get_output_value: pin = %d (port %d:bit %d)\n",
- gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
-
- val = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
-
- return (val >> GPIO_BIT(gpio)) & 1;
-}
-
-
/* set GPIO pin 'gpio' as an input */
static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset)
{
struct tegra_port_info *state = dev_get_priv(dev);
- int ret;
-
- ret = check_reserved(dev, offset, __func__);
- if (ret)
- return ret;
/* Configure GPIO direction as input. */
set_direction(state->base_gpio + offset, 0);
{
struct tegra_port_info *state = dev_get_priv(dev);
int gpio = state->base_gpio + offset;
- int ret;
-
- ret = check_reserved(dev, offset, __func__);
- if (ret)
- return ret;
/* Configure GPIO output value. */
set_level(gpio, value);
{
struct tegra_port_info *state = dev_get_priv(dev);
int gpio = state->base_gpio + offset;
- int ret;
int val;
- ret = check_reserved(dev, offset, __func__);
- if (ret)
- return ret;
-
debug("%s: pin = %d (port %d:bit %d)\n", __func__,
gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
{
struct tegra_port_info *state = dev_get_priv(dev);
int gpio = state->base_gpio + offset;
- int ret;
-
- ret = check_reserved(dev, offset, __func__);
- if (ret)
- return ret;
debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value);
struct tegra_port_info *state = dev_get_priv(dev);
int gpio = state->base_gpio + offset;
- if (!*state->label[offset])
- return GPIOF_UNUSED;
if (!get_config(gpio))
return GPIOF_FUNC;
else if (get_direction(gpio))
return GPIOF_INPUT;
}
-static int tegra_gpio_get_state(struct udevice *dev, unsigned int offset,
- char *buf, int bufsize)
-{
- struct gpio_dev_priv *uc_priv = dev->uclass_priv;
- struct tegra_port_info *state = dev_get_priv(dev);
- int gpio = state->base_gpio + offset;
- const char *label;
- int is_output;
- int is_gpio;
- int size;
-
- label = state->label[offset];
- is_gpio = get_config(gpio); /* GPIO, not SFPIO */
- size = snprintf(buf, bufsize, "%s%d: ",
- uc_priv->bank_name ? uc_priv->bank_name : "", offset);
- buf += size;
- bufsize -= size;
- if (is_gpio) {
- is_output = get_direction(gpio);
-
- snprintf(buf, bufsize, "%s: %d [%c]%s%s",
- is_output ? "out" : " in",
- is_output ?
- tegra_gpio_get_output_value(gpio) :
- tegra_gpio_get_value(dev, offset),
- *label ? 'x' : ' ',
- *label ? " " : "",
- label);
- } else {
- snprintf(buf, bufsize, "sfpio");
- }
-
- return 0;
-}
-
static const struct dm_gpio_ops gpio_tegra_ops = {
.request = tegra_gpio_request,
- .free = tegra_gpio_free,
.direction_input = tegra_gpio_direction_input,
.direction_output = tegra_gpio_direction_output,
.get_value = tegra_gpio_get_value,
.set_value = tegra_gpio_set_value,
.get_function = tegra_gpio_get_function,
- .get_state = tegra_gpio_get_state,
};
/**
#
obj-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
-obj-$(CONFIG_DW_I2C) += designware_i2c.o
obj-$(CONFIG_I2C_MV) += mv_i2c.o
-obj-$(CONFIG_I2C_MXS) += mxs_i2c.o
obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
obj-$(CONFIG_U8500_I2C) += u8500_i2c.o
obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
obj-$(CONFIG_SYS_I2C) += i2c_core.o
obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
+obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
+obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o
obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
*/
#include <common.h>
+#include <i2c.h>
#include <asm/io.h>
#include "designware_i2c.h"
-#ifdef CONFIG_I2C_MULTI_BUS
-static unsigned int bus_initialized[CONFIG_SYS_I2C_BUS_MAX];
-static unsigned int current_bus = 0;
+static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
+{
+ switch (adap->hwadapnr) {
+#if CONFIG_SYS_I2C_BUS_MAX >= 4
+ case 3:
+ return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
+#endif
+#if CONFIG_SYS_I2C_BUS_MAX >= 3
+ case 2:
+ return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
#endif
+#if CONFIG_SYS_I2C_BUS_MAX >= 2
+ case 1:
+ return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
+#endif
+ case 0:
+ return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
+ default:
+ printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
+ }
-static struct i2c_regs *i2c_regs_p =
- (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
+ return NULL;
+}
/*
* set_speed - Set the i2c speed mode (standard, high, fast)
*
* Set the i2c speed mode (standard, high, fast)
*/
-static void set_speed(int i2c_spd)
+static void set_speed(struct i2c_adapter *adap, int i2c_spd)
{
+ struct i2c_regs *i2c_base = i2c_get_base(adap);
unsigned int cntl;
unsigned int hcnt, lcnt;
unsigned int enbl;
/* to set speed cltr must be disabled */
- enbl = readl(&i2c_regs_p->ic_enable);
+ enbl = readl(&i2c_base->ic_enable);
enbl &= ~IC_ENABLE_0B;
- writel(enbl, &i2c_regs_p->ic_enable);
+ writel(enbl, &i2c_base->ic_enable);
- cntl = (readl(&i2c_regs_p->ic_con) & (~IC_CON_SPD_MSK));
+ cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
switch (i2c_spd) {
case IC_SPEED_MODE_MAX:
cntl |= IC_CON_SPD_HS;
hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
- writel(hcnt, &i2c_regs_p->ic_hs_scl_hcnt);
+ writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
- writel(lcnt, &i2c_regs_p->ic_hs_scl_lcnt);
+ writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
break;
case IC_SPEED_MODE_STANDARD:
cntl |= IC_CON_SPD_SS;
hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
- writel(hcnt, &i2c_regs_p->ic_ss_scl_hcnt);
+ writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
- writel(lcnt, &i2c_regs_p->ic_ss_scl_lcnt);
+ writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
break;
case IC_SPEED_MODE_FAST:
default:
cntl |= IC_CON_SPD_FS;
hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
- writel(hcnt, &i2c_regs_p->ic_fs_scl_hcnt);
+ writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
- writel(lcnt, &i2c_regs_p->ic_fs_scl_lcnt);
+ writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
break;
}
- writel(cntl, &i2c_regs_p->ic_con);
+ writel(cntl, &i2c_base->ic_con);
/* Enable back i2c now speed set */
enbl |= IC_ENABLE_0B;
- writel(enbl, &i2c_regs_p->ic_enable);
+ writel(enbl, &i2c_base->ic_enable);
}
/*
*
* Set the i2c speed.
*/
-int i2c_set_bus_speed(int speed)
+static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
+ unsigned int speed)
{
+ int i2c_spd;
+
if (speed >= I2C_MAX_SPEED)
- set_speed(IC_SPEED_MODE_MAX);
+ i2c_spd = IC_SPEED_MODE_MAX;
else if (speed >= I2C_FAST_SPEED)
- set_speed(IC_SPEED_MODE_FAST);
+ i2c_spd = IC_SPEED_MODE_FAST;
else
- set_speed(IC_SPEED_MODE_STANDARD);
+ i2c_spd = IC_SPEED_MODE_STANDARD;
- return 0;
-}
-
-/*
- * i2c_get_bus_speed - Gets the i2c speed
- *
- * Gets the i2c speed.
- */
-int i2c_get_bus_speed(void)
-{
- u32 cntl;
-
- cntl = (readl(&i2c_regs_p->ic_con) & IC_CON_SPD_MSK);
-
- if (cntl == IC_CON_SPD_HS)
- return I2C_MAX_SPEED;
- else if (cntl == IC_CON_SPD_FS)
- return I2C_FAST_SPEED;
- else if (cntl == IC_CON_SPD_SS)
- return I2C_STANDARD_SPEED;
+ set_speed(adap, i2c_spd);
+ adap->speed = speed;
return 0;
}
/*
* i2c_init - Init function
* @speed: required i2c speed
- * @slaveadd: slave address for the device
+ * @slaveaddr: slave address for the device
*
* Initialization function.
*/
-void i2c_init(int speed, int slaveadd)
+static void dw_i2c_init(struct i2c_adapter *adap, int speed,
+ int slaveaddr)
{
+ struct i2c_regs *i2c_base = i2c_get_base(adap);
unsigned int enbl;
/* Disable i2c */
- enbl = readl(&i2c_regs_p->ic_enable);
+ enbl = readl(&i2c_base->ic_enable);
enbl &= ~IC_ENABLE_0B;
- writel(enbl, &i2c_regs_p->ic_enable);
+ writel(enbl, &i2c_base->ic_enable);
- writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_regs_p->ic_con);
- writel(IC_RX_TL, &i2c_regs_p->ic_rx_tl);
- writel(IC_TX_TL, &i2c_regs_p->ic_tx_tl);
- i2c_set_bus_speed(speed);
- writel(IC_STOP_DET, &i2c_regs_p->ic_intr_mask);
- writel(slaveadd, &i2c_regs_p->ic_sar);
+ writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con);
+ writel(IC_RX_TL, &i2c_base->ic_rx_tl);
+ writel(IC_TX_TL, &i2c_base->ic_tx_tl);
+ dw_i2c_set_bus_speed(adap, speed);
+ writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
+ writel(slaveaddr, &i2c_base->ic_sar);
/* Enable i2c */
- enbl = readl(&i2c_regs_p->ic_enable);
+ enbl = readl(&i2c_base->ic_enable);
enbl |= IC_ENABLE_0B;
- writel(enbl, &i2c_regs_p->ic_enable);
-
-#ifdef CONFIG_I2C_MULTI_BUS
- bus_initialized[current_bus] = 1;
-#endif
+ writel(enbl, &i2c_base->ic_enable);
}
/*
*
* Sets the target slave address.
*/
-static void i2c_setaddress(unsigned int i2c_addr)
+static void i2c_setaddress(struct i2c_adapter *adap, unsigned int i2c_addr)
{
+ struct i2c_regs *i2c_base = i2c_get_base(adap);
unsigned int enbl;
/* Disable i2c */
- enbl = readl(&i2c_regs_p->ic_enable);
+ enbl = readl(&i2c_base->ic_enable);
enbl &= ~IC_ENABLE_0B;
- writel(enbl, &i2c_regs_p->ic_enable);
+ writel(enbl, &i2c_base->ic_enable);
- writel(i2c_addr, &i2c_regs_p->ic_tar);
+ writel(i2c_addr, &i2c_base->ic_tar);
/* Enable i2c */
- enbl = readl(&i2c_regs_p->ic_enable);
+ enbl = readl(&i2c_base->ic_enable);
enbl |= IC_ENABLE_0B;
- writel(enbl, &i2c_regs_p->ic_enable);
+ writel(enbl, &i2c_base->ic_enable);
}
/*
*
* Flushes the i2c RX FIFO
*/
-static void i2c_flush_rxfifo(void)
+static void i2c_flush_rxfifo(struct i2c_adapter *adap)
{
- while (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE)
- readl(&i2c_regs_p->ic_cmd_data);
+ struct i2c_regs *i2c_base = i2c_get_base(adap);
+
+ while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
+ readl(&i2c_base->ic_cmd_data);
}
/*
*
* Waits for bus busy
*/
-static int i2c_wait_for_bb(void)
+static int i2c_wait_for_bb(struct i2c_adapter *adap)
{
+ struct i2c_regs *i2c_base = i2c_get_base(adap);
unsigned long start_time_bb = get_timer(0);
- while ((readl(&i2c_regs_p->ic_status) & IC_STATUS_MA) ||
- !(readl(&i2c_regs_p->ic_status) & IC_STATUS_TFE)) {
+ while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
+ !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
/* Evaluate timeout */
if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
return 0;
}
-static int i2c_xfer_init(uchar chip, uint addr, int alen)
+static int i2c_xfer_init(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen)
{
- if (i2c_wait_for_bb())
+ struct i2c_regs *i2c_base = i2c_get_base(adap);
+
+ if (i2c_wait_for_bb(adap))
return 1;
- i2c_setaddress(chip);
+ i2c_setaddress(adap, chip);
while (alen) {
alen--;
/* high byte address going out first */
writel((addr >> (alen * 8)) & 0xff,
- &i2c_regs_p->ic_cmd_data);
+ &i2c_base->ic_cmd_data);
}
return 0;
}
-static int i2c_xfer_finish(void)
+static int i2c_xfer_finish(struct i2c_adapter *adap)
{
+ struct i2c_regs *i2c_base = i2c_get_base(adap);
ulong start_stop_det = get_timer(0);
while (1) {
- if ((readl(&i2c_regs_p->ic_raw_intr_stat) & IC_STOP_DET)) {
- readl(&i2c_regs_p->ic_clr_stop_det);
+ if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
+ readl(&i2c_base->ic_clr_stop_det);
break;
} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
break;
}
}
- if (i2c_wait_for_bb()) {
+ if (i2c_wait_for_bb(adap)) {
printf("Timed out waiting for bus\n");
return 1;
}
- i2c_flush_rxfifo();
+ i2c_flush_rxfifo(adap);
return 0;
}
*
* Read from i2c memory.
*/
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
+ int alen, u8 *buffer, int len)
{
+ struct i2c_regs *i2c_base = i2c_get_base(adap);
unsigned long start_time_rx;
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
* still be one byte because the extra address bits are
* hidden in the chip address.
*/
- chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
+ dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
- debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip,
+ debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
addr);
#endif
- if (i2c_xfer_init(chip, addr, alen))
+ if (i2c_xfer_init(adap, dev, addr, alen))
return 1;
start_time_rx = get_timer(0);
while (len) {
if (len == 1)
- writel(IC_CMD | IC_STOP, &i2c_regs_p->ic_cmd_data);
+ writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
else
- writel(IC_CMD, &i2c_regs_p->ic_cmd_data);
+ writel(IC_CMD, &i2c_base->ic_cmd_data);
- if (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE) {
- *buffer++ = (uchar)readl(&i2c_regs_p->ic_cmd_data);
+ if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
+ *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
len--;
start_time_rx = get_timer(0);
}
}
- return i2c_xfer_finish();
+ return i2c_xfer_finish(adap);
}
/*
*
* Write to i2c memory.
*/
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
+ int alen, u8 *buffer, int len)
{
+ struct i2c_regs *i2c_base = i2c_get_base(adap);
int nb = len;
unsigned long start_time_tx;
* still be one byte because the extra address bits are
* hidden in the chip address.
*/
- chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
+ dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
- debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip,
+ debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
addr);
#endif
- if (i2c_xfer_init(chip, addr, alen))
+ if (i2c_xfer_init(adap, dev, addr, alen))
return 1;
start_time_tx = get_timer(0);
while (len) {
- if (readl(&i2c_regs_p->ic_status) & IC_STATUS_TFNF) {
- if (--len == 0)
- writel(*buffer | IC_STOP, &i2c_regs_p->ic_cmd_data);
- else
- writel(*buffer, &i2c_regs_p->ic_cmd_data);
+ if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
+ if (--len == 0) {
+ writel(*buffer | IC_STOP,
+ &i2c_base->ic_cmd_data);
+ } else {
+ writel(*buffer, &i2c_base->ic_cmd_data);
+ }
buffer++;
start_time_tx = get_timer(0);
}
}
- return i2c_xfer_finish();
+ return i2c_xfer_finish(adap);
}
/*
* i2c_probe - Probe the i2c chip
*/
-int i2c_probe(uchar chip)
+static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
{
u32 tmp;
int ret;
/*
* Try to read the first location of the chip.
*/
- ret = i2c_read(chip, 0, 1, (uchar *)&tmp, 1);
+ ret = dw_i2c_read(adap, dev, 0, 1, (uchar *)&tmp, 1);
if (ret)
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ dw_i2c_init(adap, adap->speed, adap->slaveaddr);
return ret;
}
-#ifdef CONFIG_I2C_MULTI_BUS
-int i2c_set_bus_num(unsigned int bus)
-{
- switch (bus) {
- case 0:
- i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE;
- break;
-#ifdef CONFIG_SYS_I2C_BASE1
- case 1:
- i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE1;
- break;
-#endif
-#ifdef CONFIG_SYS_I2C_BASE2
- case 2:
- i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE2;
- break;
-#endif
-#ifdef CONFIG_SYS_I2C_BASE3
- case 3:
- i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE3;
- break;
-#endif
-#ifdef CONFIG_SYS_I2C_BASE4
- case 4:
- i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE4;
- break;
-#endif
-#ifdef CONFIG_SYS_I2C_BASE5
- case 5:
- i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE5;
- break;
-#endif
-#ifdef CONFIG_SYS_I2C_BASE6
- case 6:
- i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE6;
- break;
-#endif
-#ifdef CONFIG_SYS_I2C_BASE7
- case 7:
- i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE7;
- break;
-#endif
-#ifdef CONFIG_SYS_I2C_BASE8
- case 8:
- i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE8;
- break;
-#endif
-#ifdef CONFIG_SYS_I2C_BASE9
- case 9:
- i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE9;
- break;
-#endif
- default:
- printf("Bad bus: %d\n", bus);
- return -1;
- }
+U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
+ dw_i2c_write, dw_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
- current_bus = bus;
-
- if (!bus_initialized[current_bus])
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#if CONFIG_SYS_I2C_BUS_MAX >= 2
+U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
+ dw_i2c_write, dw_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
+#endif
- return 0;
-}
+#if CONFIG_SYS_I2C_BUS_MAX >= 3
+U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
+ dw_i2c_write, dw_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
+#endif
-int i2c_get_bus_num(void)
-{
- return current_bus;
-}
+#if CONFIG_SYS_I2C_BUS_MAX >= 4
+U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
+ dw_i2c_write, dw_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
#endif
}
/* implement possible board specific board init */
-static void __def_i2c_init_board(void)
+__weak void i2c_init_board(void)
{
}
-void i2c_init_board(void)
- __attribute__((weak, alias("__def_i2c_init_board")));
/*
* i2c_init_all():
i2c_write(addr, reg, 1, &val, 1);
}
-void __i2c_init(int speed, int slaveaddr)
+__weak void i2c_init(int speed, int slaveaddr)
{
i2c_init_bus(i2c_get_bus_num(), speed, slaveaddr);
}
-void i2c_init(int speed, int slaveaddr)
- __attribute__((weak, alias("__i2c_init")));
#define MXS_I2C_MAX_TIMEOUT 1000000
-static void mxs_i2c_reset(void)
+static struct mxs_i2c_regs *mxs_i2c_get_base(struct i2c_adapter *adap)
{
- struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
+ if (adap->hwadapnr == 0)
+ return (struct mxs_i2c_regs *)MXS_I2C0_BASE;
+ else
+ return (struct mxs_i2c_regs *)MXS_I2C1_BASE;
+}
+
+static unsigned int mxs_i2c_get_bus_speed(struct i2c_adapter *adap)
+{
+ struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
+ uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
+ uint32_t timing0;
+
+ timing0 = readl(&i2c_regs->hw_i2c_timing0);
+ /*
+ * This is a reverse version of the algorithm presented in
+ * i2c_set_bus_speed(). Please refer there for details.
+ */
+ return clk / ((((timing0 >> 16) - 3) * 2) + 38);
+}
+
+static uint mxs_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
+{
+ struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
+ /*
+ * The timing derivation algorithm. There is no documentation for this
+ * algorithm available, it was derived by using the scope and fiddling
+ * with constants until the result observed on the scope was good enough
+ * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be
+ * possible to assume the algorithm works for other frequencies as well.
+ *
+ * Note it was necessary to cap the frequency on both ends as it's not
+ * possible to configure completely arbitrary frequency for the I2C bus
+ * clock.
+ */
+ uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
+ uint32_t base = ((clk / speed) - 38) / 2;
+ uint16_t high_count = base + 3;
+ uint16_t low_count = base - 3;
+ uint16_t rcv_count = (high_count * 3) / 4;
+ uint16_t xmit_count = low_count / 4;
+
+ if (speed > 540000) {
+ printf("MXS I2C: Speed too high (%d Hz)\n", speed);
+ return -EINVAL;
+ }
+
+ if (speed < 12000) {
+ printf("MXS I2C: Speed too low (%d Hz)\n", speed);
+ return -EINVAL;
+ }
+
+ writel((high_count << 16) | rcv_count, &i2c_regs->hw_i2c_timing0);
+ writel((low_count << 16) | xmit_count, &i2c_regs->hw_i2c_timing1);
+
+ writel((0x0030 << I2C_TIMING2_BUS_FREE_OFFSET) |
+ (0x0030 << I2C_TIMING2_LEADIN_COUNT_OFFSET),
+ &i2c_regs->hw_i2c_timing2);
+
+ return 0;
+}
+
+static void mxs_i2c_reset(struct i2c_adapter *adap)
+{
+ struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
int ret;
- int speed = i2c_get_bus_speed();
+ int speed = mxs_i2c_get_bus_speed(adap);
ret = mxs_reset_block(&i2c_regs->hw_i2c_ctrl0_reg);
if (ret) {
writel(I2C_QUEUECTRL_PIO_QUEUE_MODE, &i2c_regs->hw_i2c_queuectrl_set);
- i2c_set_bus_speed(speed);
+ mxs_i2c_set_bus_speed(adap, speed);
}
-static void mxs_i2c_setup_read(uint8_t chip, int len)
+static void mxs_i2c_setup_read(struct i2c_adapter *adap, uint8_t chip, int len)
{
- struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
+ struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
writel(I2C_QUEUECMD_RETAIN_CLOCK | I2C_QUEUECMD_PRE_SEND_START |
I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
}
-static int mxs_i2c_write(uchar chip, uint addr, int alen,
- uchar *buf, int blen, int stop)
+static int mxs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buf, int blen, int stop)
{
- struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
+ struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
uint32_t data, tmp;
int i, remain, off;
int timeout = MXS_I2C_MAX_TIMEOUT;
return 0;
}
-static int mxs_i2c_wait_for_ack(void)
+static int mxs_i2c_wait_for_ack(struct i2c_adapter *adap)
{
- struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
+ struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
uint32_t tmp;
int timeout = MXS_I2C_MAX_TIMEOUT;
return 0;
err:
- mxs_i2c_reset();
+ mxs_i2c_reset(adap);
return 1;
}
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int mxs_i2c_if_read(struct i2c_adapter *adap, uint8_t chip,
+ uint addr, int alen, uint8_t *buffer,
+ int len)
{
- struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
+ struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
uint32_t tmp = 0;
int timeout = MXS_I2C_MAX_TIMEOUT;
int ret;
int i;
- ret = mxs_i2c_write(chip, addr, alen, NULL, 0, 0);
+ ret = mxs_i2c_write(adap, chip, addr, alen, NULL, 0, 0);
if (ret) {
debug("MXS I2C: Failed writing address\n");
return ret;
}
- ret = mxs_i2c_wait_for_ack();
+ ret = mxs_i2c_wait_for_ack(adap);
if (ret) {
debug("MXS I2C: Failed writing address\n");
return ret;
}
- mxs_i2c_setup_read(chip, len);
- ret = mxs_i2c_wait_for_ack();
+ mxs_i2c_setup_read(adap, chip, len);
+ ret = mxs_i2c_wait_for_ack(adap);
if (ret) {
debug("MXS I2C: Failed reading address\n");
return ret;
return 0;
}
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int mxs_i2c_if_write(struct i2c_adapter *adap, uint8_t chip,
+ uint addr, int alen, uint8_t *buffer,
+ int len)
{
int ret;
- ret = mxs_i2c_write(chip, addr, alen, buffer, len, 1);
+ ret = mxs_i2c_write(adap, chip, addr, alen, buffer, len, 1);
if (ret) {
debug("MXS I2C: Failed writing address\n");
return ret;
}
- ret = mxs_i2c_wait_for_ack();
+ ret = mxs_i2c_wait_for_ack(adap);
if (ret)
debug("MXS I2C: Failed writing address\n");
return ret;
}
-int i2c_probe(uchar chip)
+static int mxs_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
{
int ret;
- ret = mxs_i2c_write(chip, 0, 1, NULL, 0, 1);
+ ret = mxs_i2c_write(adap, chip, 0, 1, NULL, 0, 1);
if (!ret)
- ret = mxs_i2c_wait_for_ack();
- mxs_i2c_reset();
+ ret = mxs_i2c_wait_for_ack(adap);
+ mxs_i2c_reset(adap);
return ret;
}
-int i2c_set_bus_speed(unsigned int speed)
+static void mxs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
{
- struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
- /*
- * The timing derivation algorithm. There is no documentation for this
- * algorithm available, it was derived by using the scope and fiddling
- * with constants until the result observed on the scope was good enough
- * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be
- * possible to assume the algorithm works for other frequencies as well.
- *
- * Note it was necessary to cap the frequency on both ends as it's not
- * possible to configure completely arbitrary frequency for the I2C bus
- * clock.
- */
- uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
- uint32_t base = ((clk / speed) - 38) / 2;
- uint16_t high_count = base + 3;
- uint16_t low_count = base - 3;
- uint16_t rcv_count = (high_count * 3) / 4;
- uint16_t xmit_count = low_count / 4;
-
- if (speed > 540000) {
- printf("MXS I2C: Speed too high (%d Hz)\n", speed);
- return -EINVAL;
- }
-
- if (speed < 12000) {
- printf("MXS I2C: Speed too low (%d Hz)\n", speed);
- return -EINVAL;
- }
-
- writel((high_count << 16) | rcv_count, &i2c_regs->hw_i2c_timing0);
- writel((low_count << 16) | xmit_count, &i2c_regs->hw_i2c_timing1);
-
- writel((0x0030 << I2C_TIMING2_BUS_FREE_OFFSET) |
- (0x0030 << I2C_TIMING2_LEADIN_COUNT_OFFSET),
- &i2c_regs->hw_i2c_timing2);
-
- return 0;
-}
-
-unsigned int i2c_get_bus_speed(void)
-{
- struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
- uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
- uint32_t timing0;
-
- timing0 = readl(&i2c_regs->hw_i2c_timing0);
- /*
- * This is a reverse version of the algorithm presented in
- * i2c_set_bus_speed(). Please refer there for details.
- */
- return clk / ((((timing0 >> 16) - 3) * 2) + 38);
-}
-
-void i2c_init(int speed, int slaveadd)
-{
- mxs_i2c_reset();
- i2c_set_bus_speed(speed);
+ mxs_i2c_reset(adap);
+ mxs_i2c_set_bus_speed(adap, speed);
return;
}
+
+U_BOOT_I2C_ADAP_COMPLETE(mxs0, mxs_i2c_init, mxs_i2c_probe,
+ mxs_i2c_if_read, mxs_i2c_if_write,
+ mxs_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_SPEED, 0, 0)
+U_BOOT_I2C_ADAP_COMPLETE(mxs1, mxs_i2c_init, mxs_i2c_probe,
+ mxs_i2c_if_read, mxs_i2c_if_write,
+ mxs_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_SPEED, 0, 1)
}
/* i2c write version without the register address */
-int i2c_write_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len,
- bool end_with_repeated_start)
+static int i2c_write_data(struct i2c_bus *bus, uchar chip, uchar *buffer,
+ int len, bool end_with_repeated_start)
{
int rc;
}
/* i2c read version without the register address */
-int i2c_read_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len)
+static int i2c_read_data(struct i2c_bus *bus, uchar chip, uchar *buffer,
+ int len)
{
int rc;
* @param input Input configuration
* @return 1, to indicate that we have something to look at
*/
-int tegra_kbc_check(struct input_config *input)
+static int tegra_kbc_check(struct input_config *input)
{
kbd_wait_for_fifo_init(&config);
check_for_keys(&config);
# SPDX-License-Identifier: GPL-2.0+
#
+obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
+obj-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o
obj-$(CONFIG_BFIN_SDH) += bfin_sdh.o
obj-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
+obj-$(CONFIG_DWMMC) += dw_mmc.o
+obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o
obj-$(CONFIG_FTSDC021) += ftsdc021_sdhci.o
obj-$(CONFIG_GENERIC_MMC) += mmc.o
obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
+obj-$(CONFIG_KONA_SDHCI) += kona_sdhci.o
obj-$(CONFIG_MMC_SPI) += mmc_spi.o
-obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
+obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
obj-$(CONFIG_MV_SDHCI) += mv_sdhci.o
+obj-$(CONFIG_MVEBU_MMC) += mvebu_mmc.o
obj-$(CONFIG_MXC_MMC) += mxcmmc.o
obj-$(CONFIG_MXS_MMC) += mxsmmc.o
obj-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o
obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
-obj-$(CONFIG_SDHCI) += sdhci.o
-obj-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o
-obj-$(CONFIG_KONA_SDHCI) += kona_sdhci.o
+obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o
obj-$(CONFIG_S3C_SDI) += s3c_sdi.o
obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
+obj-$(CONFIG_SDHCI) += sdhci.o
obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
+obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o
obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o
obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
-obj-$(CONFIG_DWMMC) += dw_mmc.o
-obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
-obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
-obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o
-obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o
+
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
else
obj-$(CONFIG_GENERIC_MMC) += mmc_write.o
endif
-obj-$(CONFIG_MVEBU_MMC) += mvebu_mmc.o
+
#include <malloc.h>
#include <sdhci.h>
#include <asm/arch/timer.h>
+#include <asm/arch-bcm2835/sdhci.h>
/* 400KHz is max freq for card ID etc. Use that as min */
#define MIN_FREQ 400000
#ifdef OMAP_HSMMC_USE_GPIO
static int omap_mmc_setup_gpio_in(int gpio, const char *label)
{
- if (!gpio_is_valid(gpio))
- return -1;
+ int ret;
- if (gpio_request(gpio, label) < 0)
+#ifndef CONFIG_DM_GPIO
+ if (!gpio_is_valid(gpio))
return -1;
+#endif
+ ret = gpio_request(gpio, label);
+ if (ret)
+ return ret;
- if (gpio_direction_input(gpio) < 0)
- return -1;
+ ret = gpio_direction_input(gpio);
+ if (ret)
+ return ret;
return gpio;
}
if (cd_gpio < 0)
return 1;
- return gpio_get_value(cd_gpio);
+ /* NOTE: assumes card detect signal is active-low */
+ return !gpio_get_value(cd_gpio);
}
static int omap_hsmmc_getwp(struct mmc *mmc)
if (wp_gpio < 0)
return 0;
+ /* NOTE: assumes write protect signal is active-high */
return gpio_get_value(wp_gpio);
}
#endif
if (fdt_gpio_isvalid(&host->cd_gpio)) {
sprintf(str, "sdhci%d_cd", host->index & 0xf);
gpio_request(host->cd_gpio.gpio, str);
- gpio_direction_output(host->cd_gpio.gpio, 1);
+ gpio_direction_input(host->cd_gpio.gpio);
if (gpio_get_value(host->cd_gpio.gpio))
return -ENODEV;
#endif
#define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT 100
-int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
+static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
struct sdhci_host *host = mmc->priv;
sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
}
-void sdhci_set_ios(struct mmc *mmc)
+static void sdhci_set_ios(struct mmc *mmc)
{
u32 ctrl;
struct sdhci_host *host = mmc->priv;
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
}
-int sdhci_init(struct mmc *mmc)
+static int sdhci_init(struct mmc *mmc)
{
struct sdhci_host *host = mmc->priv;
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
+#include <asm-generic/gpio.h>
struct sunxi_mmc_host {
unsigned mmc_no;
uint32_t *mclkreg;
- unsigned database;
unsigned fatal_err;
unsigned mod_clk;
struct sunxi_mmc *reg;
/* support 4 mmc hosts */
struct sunxi_mmc_host mmc_host[4];
+static int sunxi_mmc_getcd_gpio(int sdc_no)
+{
+ switch (sdc_no) {
+ case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
+ case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
+ case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
+ case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
+ }
+ return -1;
+}
+
static int mmc_resource_init(int sdc_no)
{
struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ int cd_pin, ret = 0;
debug("init mmc %d resource\n", sdc_no);
printf("Wrong mmc number %d\n", sdc_no);
return -1;
}
- mmchost->database = (unsigned int)mmchost->reg + 0x100;
mmchost->mmc_no = sdc_no;
- return 0;
+ cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
+ if (cd_pin != -1)
+ ret = gpio_request(cd_pin, "mmc_cd");
+
+ return ret;
}
static int mmc_clk_io_on(int sdc_no)
/* config ahb clock */
setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
+ /* unassert reset */
+ setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
+#endif
+
/* config mod clock */
pll_clk = clock_get_pll6();
/* should be close to 100 MHz but no more, so round up */
}
if (reading)
- buff[i] = readl(mmchost->database);
+ buff[i] = readl(&mmchost->reg->fifo);
else
- writel(buff[i], mmchost->database);
+ writel(buff[i], &mmchost->reg->fifo);
}
return 0;
return error;
}
+static int sunxi_mmc_getcd(struct mmc *mmc)
+{
+ struct sunxi_mmc_host *mmchost = mmc->priv;
+ int cd_pin;
+
+ cd_pin = sunxi_mmc_getcd_gpio(mmchost->mmc_no);
+ if (cd_pin == -1)
+ return 1;
+
+ return !gpio_direction_input(cd_pin);
+}
+
static const struct mmc_ops sunxi_mmc_ops = {
.send_cmd = mmc_send_cmd,
.set_ios = mmc_set_ios,
.init = mmc_core_init,
+ .getcd = sunxi_mmc_getcd,
};
-int sunxi_mmc_init(int sdc_no)
+struct mmc *sunxi_mmc_init(int sdc_no)
{
struct mmc_config *cfg = &mmc_host[sdc_no].cfg;
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
cfg->host_caps = MMC_MODE_4BIT;
cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I)
+ cfg->host_caps |= MMC_MODE_HC;
+#endif
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
cfg->f_min = 400000;
cfg->f_max = 52000000;
- mmc_resource_init(sdc_no);
- mmc_clk_io_on(sdc_no);
+ if (mmc_resource_init(sdc_no) != 0)
+ return NULL;
- if (mmc_create(cfg, &mmc_host[sdc_no]) == NULL)
- return -1;
+ mmc_clk_io_on(sdc_no);
- return 0;
+ return mmc_create(cfg, &mmc_host[sdc_no]);
}
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/mmc.h>
#include <asm/arch-tegra/tegra_mmc.h>
#include <mmc.h>
return 0;
}
-int tegra_mmc_getcd(struct mmc *mmc)
+static int tegra_mmc_getcd(struct mmc *mmc)
{
struct mmc_host *host = mmc->priv;
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
#endif
+#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define __maybe_weak __weak
+#else
+#define __maybe_weak static
+#endif
+
/*
* 0xffff is an undefined value for the configuration register. When
* this value is returned, the configuration register shall not be
int cfi_flash_num_flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT;
#endif
-static phys_addr_t __cfi_flash_bank_addr(int i)
+__weak phys_addr_t cfi_flash_bank_addr(int i)
{
return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i];
}
-phys_addr_t cfi_flash_bank_addr(int i)
- __attribute__((weak, alias("__cfi_flash_bank_addr")));
-static unsigned long __cfi_flash_bank_size(int i)
+__weak unsigned long cfi_flash_bank_size(int i)
{
#ifdef CONFIG_SYS_FLASH_BANKS_SIZES
return ((unsigned long [])CONFIG_SYS_FLASH_BANKS_SIZES)[i];
return 0;
#endif
}
-unsigned long cfi_flash_bank_size(int i)
- __attribute__((weak, alias("__cfi_flash_bank_size")));
-static void __flash_write8(u8 value, void *addr)
+__maybe_weak void flash_write8(u8 value, void *addr)
{
__raw_writeb(value, addr);
}
-static void __flash_write16(u16 value, void *addr)
+__maybe_weak void flash_write16(u16 value, void *addr)
{
__raw_writew(value, addr);
}
-static void __flash_write32(u32 value, void *addr)
+__maybe_weak void flash_write32(u32 value, void *addr)
{
__raw_writel(value, addr);
}
-static void __flash_write64(u64 value, void *addr)
+__maybe_weak void flash_write64(u64 value, void *addr)
{
/* No architectures currently implement __raw_writeq() */
*(volatile u64 *)addr = value;
}
-static u8 __flash_read8(void *addr)
+__maybe_weak u8 flash_read8(void *addr)
{
return __raw_readb(addr);
}
-static u16 __flash_read16(void *addr)
+__maybe_weak u16 flash_read16(void *addr)
{
return __raw_readw(addr);
}
-static u32 __flash_read32(void *addr)
+__maybe_weak u32 flash_read32(void *addr)
{
return __raw_readl(addr);
}
-static u64 __flash_read64(void *addr)
+__maybe_weak u64 flash_read64(void *addr)
{
/* No architectures currently implement __raw_readq() */
return *(volatile u64 *)addr;
}
-#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-void flash_write8(u8 value, void *addr)__attribute__((weak, alias("__flash_write8")));
-void flash_write16(u16 value, void *addr)__attribute__((weak, alias("__flash_write16")));
-void flash_write32(u32 value, void *addr)__attribute__((weak, alias("__flash_write32")));
-void flash_write64(u64 value, void *addr)__attribute__((weak, alias("__flash_write64")));
-u8 flash_read8(void *addr)__attribute__((weak, alias("__flash_read8")));
-u16 flash_read16(void *addr)__attribute__((weak, alias("__flash_read16")));
-u32 flash_read32(void *addr)__attribute__((weak, alias("__flash_read32")));
-u64 flash_read64(void *addr)__attribute__((weak, alias("__flash_read64")));
-#else
-#define flash_write8 __flash_write8
-#define flash_write16 __flash_write16
-#define flash_write32 __flash_write32
-#define flash_write64 __flash_write64
-#define flash_read8 __flash_read8
-#define flash_read16 __flash_read16
-#define flash_read32 __flash_read32
-#define flash_read64 __flash_read64
-#endif
-
/*-----------------------------------------------------------------------
*/
#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
uint32_t page_oob_size)
{
- if (page_data_size == 2048)
- return 8;
+ if (page_data_size == 2048) {
+ if (page_oob_size == 64)
+ return 8;
+
+ if (page_oob_size == 112)
+ return 14;
+ }
if (page_data_size == 4096) {
if (page_oob_size == 128)
#ifdef CONFIG_SPL_BUILD
/* Check wait pin as dev ready indicator */
-int omap_spl_dev_ready(struct mtd_info *mtd)
+static int omap_spl_dev_ready(struct mtd_info *mtd)
{
return gpmc_cfg->status & (1 << 8);
}
return 0;
}
-/*
- * omap_reverse_list - re-orders list elements in reverse order [internal]
- * @list: pointer to start of list
- * @length: length of list
-*/
-void omap_reverse_list(u8 *list, unsigned int length)
-{
- unsigned int i, j;
- unsigned int half_length = length / 2;
- u8 tmp;
- for (i = 0, j = length - 1; i < half_length; i++, j--) {
- tmp = list[i];
- list[i] = list[j];
- list[j] = tmp;
- }
-}
-
/*
* omap_enable_hwecc - configures GPMC as per ECC scheme before read/write
* @mtd: MTD device structure
}
#ifdef CONFIG_NAND_OMAP_ELM
+/*
+ * omap_reverse_list - re-orders list elements in reverse order [internal]
+ * @list: pointer to start of list
+ * @length: length of list
+*/
+static void omap_reverse_list(u8 *list, unsigned int length)
+{
+ unsigned int i, j;
+ unsigned int half_length = length / 2;
+ u8 tmp;
+ for (i = 0, j = length - 1; i < half_length; i++, j--) {
+ tmp = list[i];
+ list[i] = list[j];
+ list[j] = tmp;
+ }
+}
+
/*
* omap_correct_data_bch - Compares the ecc read from nand spare area
* with ECC registers values and corrects one bit error if it has occured
#include <net.h>
#include <miiphy.h>
#include <malloc.h>
+#include <netdev.h>
#include <linux/compiler.h>
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS},
if (e1000_get_hw_eeprom_semaphore(hw))
return -E1000_ERR_SWFW_SYNC;
- swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
- if ((swfw_sync & swmask) && !(swfw_sync & fwmask))
+ if (hw->mac_type == e1000_igb)
+ swfw_sync = E1000_READ_REG(hw, I210_SW_FW_SYNC);
+ else
+ swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
+ if (!(swfw_sync & (fwmask | swmask)))
break;
/* firmware currently using resource (fwmask) */
case E1000_DEV_ID_ICH8_IGP_M:
hw->mac_type = e1000_ich8lan;
break;
+ case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
+ case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
case PCI_DEVICE_ID_INTEL_I210_COPPER:
+ case PCI_DEVICE_ID_INTEL_I211_COPPER:
case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
case PCI_DEVICE_ID_INTEL_I210_SERDES:
case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
if (hw->mac_type >= e1000_82571)
mdelay(10);
-
} else {
/* Read the Extended Device Control Register, assert the PHY_RESET_DIR
* bit to put the PHY into reset. Then, take it out of reset.
#define ICH_GFPREG_BASE_MASK 0x1FFF
#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
+#define E1000_I210_SW_FW_SYNC 0x5B50 /* Software-Firmware Synchronization - RW */
#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
/* SPI EEPROM Status Register */
static int eepro100_recv (struct eth_device *dev);
static void eepro100_halt (struct eth_device *dev);
-#if defined(CONFIG_E500) || defined(CONFIG_DB64360) || defined(CONFIG_DB64460)
+#if defined(CONFIG_E500)
#define bus_to_phys(a) (a)
#define phys_to_bus(a) (a)
#else
#include <common.h>
#include <malloc.h>
#include <net.h>
+#include <netdev.h>
#include <miiphy.h>
#include "fec_mxc.h"
return 0;
}
-int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr)
+static int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr,
+ int regAddr)
{
return fec_mdio_read(bus->priv, phyAddr, regAddr);
}
-int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr,
- u16 data)
+static int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr,
+ int regAddr, u16 data)
{
return fec_mdio_write(bus->priv, phyAddr, regAddr, data);
}
#include <command.h>
#include <net.h>
+#include <phy.h>
+#include <errno.h>
#include <miiphy.h>
#include <malloc.h>
-#include <asm/arch/emac_defs.h>
-#include <asm/arch/psc_defs.h>
-#include <asm/arch/keystone_nav.h>
-
-unsigned int emac_dbg;
+#include <asm/ti-common/keystone_nav.h>
+#include <asm/ti-common/keystone_net.h>
+#include <asm/ti-common/keystone_serdes.h>
unsigned int emac_open;
+static struct mii_dev *mdio_bus;
static unsigned int sys_has_mdio = 1;
#ifdef KEYSTONE2_EMAC_GIG_ENABLE
#define RX_BUFF_NUMS 24
#define RX_BUFF_LEN 1520
#define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
+#define SGMII_ANEG_TIMEOUT 4000
static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
.rx_flow = 22,
};
-static void keystone2_eth_mdio_enable(void);
-
-static int gen_get_link_speed(int phy_addr);
-
-/* EMAC Addresses */
-static volatile struct emac_regs *adap_emac =
- (struct emac_regs *)EMAC_EMACSL_BASE_ADDR;
-static volatile struct mdio_regs *adap_mdio =
- (struct mdio_regs *)EMAC_MDIO_BASE_ADDR;
+static void keystone2_net_serdes_setup(void);
int keystone2_eth_read_mac_addr(struct eth_device *dev)
{
return 0;
}
-static void keystone2_eth_mdio_enable(void)
+/* MDIO */
+
+static int keystone2_mdio_reset(struct mii_dev *bus)
{
- u_int32_t clkdiv;
+ u_int32_t clkdiv;
+ struct mdio_regs *adap_mdio = bus->priv;
clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
- writel((clkdiv & 0xffff) |
- MDIO_CONTROL_ENABLE |
- MDIO_CONTROL_FAULT |
- MDIO_CONTROL_FAULT_ENABLE,
+ writel((clkdiv & 0xffff) | MDIO_CONTROL_ENABLE |
+ MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE,
&adap_mdio->control);
while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE)
;
+
+ return 0;
}
-/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
-int keystone2_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
+/**
+ * keystone2_mdio_read - read a PHY register via MDIO interface.
+ * Blocks until operation is complete.
+ */
+static int keystone2_mdio_read(struct mii_dev *bus,
+ int addr, int devad, int reg)
{
- int tmp;
+ int tmp;
+ struct mdio_regs *adap_mdio = bus->priv;
while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
;
- writel(MDIO_USERACCESS0_GO |
- MDIO_USERACCESS0_WRITE_READ |
- ((reg_num & 0x1f) << 21) |
- ((phy_addr & 0x1f) << 16),
+ writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ |
+ ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16),
&adap_mdio->useraccess0);
/* Wait for command to complete */
while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO)
;
- if (tmp & MDIO_USERACCESS0_ACK) {
- *data = tmp & 0xffff;
- return 0;
- }
+ if (tmp & MDIO_USERACCESS0_ACK)
+ return tmp & 0xffff;
- *data = -1;
return -1;
}
-/*
- * Write to a PHY register via MDIO inteface.
+/**
+ * keystone2_mdio_write - write to a PHY register via MDIO interface.
* Blocks until operation is complete.
*/
-int keystone2_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
+static int keystone2_mdio_write(struct mii_dev *bus,
+ int addr, int devad, int reg, u16 val)
{
+ struct mdio_regs *adap_mdio = bus->priv;
+
while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
;
- writel(MDIO_USERACCESS0_GO |
- MDIO_USERACCESS0_WRITE_WRITE |
- ((reg_num & 0x1f) << 21) |
- ((phy_addr & 0x1f) << 16) |
- (data & 0xffff),
- &adap_mdio->useraccess0);
+ writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE |
+ ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) |
+ (val & 0xffff), &adap_mdio->useraccess0);
/* Wait for command to complete */
while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
return 0;
}
-/* PHY functions for a generic PHY */
-static int gen_get_link_speed(int phy_addr)
-{
- u_int16_t tmp;
-
- if ((!keystone2_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp)) &&
- (tmp & 0x04)) {
- return 0;
- }
-
- return -1;
-}
-
static void __attribute__((unused))
keystone2_eth_gigabit_enable(struct eth_device *dev)
{
struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
if (sys_has_mdio) {
- if (keystone2_eth_phy_read(eth_priv->phy_addr, 0, &data) ||
- !(data & (1 << 6))) /* speed selection MSB */
+ data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr,
+ MDIO_DEVAD_NONE, 0);
+ /* speed selection MSB */
+ if (!(data & (1 << 6)))
return;
}
* Check if link detected is giga-bit
* If Gigabit mode detected, enable gigbit in MAC
*/
- writel(readl(&(adap_emac[eth_priv->slave_port - 1].maccontrol)) |
+ writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) +
+ CPGMACSL_REG_CTL) |
EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
- &(adap_emac[eth_priv->slave_port - 1].maccontrol))
- ;
+ DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL);
}
int keystone_sgmii_link_status(int port)
status = __raw_readl(SGMII_STATUS_REG(port));
- return status & SGMII_REG_STATUS_LINK;
+ return (status & SGMII_REG_STATUS_LOCK) &&
+ (status & SGMII_REG_STATUS_LINK);
}
-
-int keystone_get_link_status(struct eth_device *dev)
-{
- struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
- int sgmii_link;
- int link_state = 0;
-#if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1
- int j;
-
- for (j = 0; (j < CONFIG_GET_LINK_STATUS_ATTEMPTS) && (link_state == 0);
- j++) {
-#endif
- sgmii_link =
- keystone_sgmii_link_status(eth_priv->slave_port - 1);
-
- if (sgmii_link) {
- link_state = 1;
-
- if (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY)
- if (gen_get_link_speed(eth_priv->phy_addr))
- link_state = 0;
- }
-#if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1
- }
-#endif
- return link_state;
-}
-
-int keystone_sgmii_config(int port, int interface)
+int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
{
unsigned int i, status, mask;
unsigned int mr_adv_ability, control;
if (control & SGMII_REG_CONTROL_AUTONEG)
mask |= SGMII_REG_STATUS_AUTONEG;
- for (i = 0; i < 1000; i++) {
+ status = __raw_readl(SGMII_STATUS_REG(port));
+ if ((status & mask) == mask)
+ return 0;
+
+ printf("\n%s Waiting for SGMII auto negotiation to complete",
+ phy_dev->dev->name);
+ while ((status & mask) != mask) {
+ /*
+ * Timeout reached ?
+ */
+ if (i > SGMII_ANEG_TIMEOUT) {
+ puts(" TIMEOUT !\n");
+ phy_dev->link = 0;
+ return 0;
+ }
+
+ if (ctrlc()) {
+ puts("user interrupt!\n");
+ phy_dev->link = 0;
+ return -EINTR;
+ }
+
+ if ((i++ % 500) == 0)
+ printf(".");
+
+ udelay(1000); /* 1 ms */
status = __raw_readl(SGMII_STATUS_REG(port));
- if ((status & mask) == mask)
- break;
}
+ puts(" done\n");
return 0;
}
writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
+#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
+ /* Map RX packet flow priority to 0 */
+ writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
+#endif
+
return ret;
}
if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE)
num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;
- return netcp_send(buffer, num_bytes, (slave_port_num) << 16);
+ return ksnav_send(&netcp_pktdma, buffer,
+ num_bytes, (slave_port_num) << 16);
}
/* Eth device open */
static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
{
- u_int32_t clkdiv;
- int link;
struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
+ struct phy_device *phy_dev = eth_priv->phy_dev;
debug("+ emac_open\n");
sys_has_mdio =
(eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;
- psc_enable_module(KS2_LPSC_PA);
- psc_enable_module(KS2_LPSC_CPGMAC);
-
- sgmii_serdes_setup_156p25mhz();
+ keystone2_net_serdes_setup();
if (sys_has_mdio)
- keystone2_eth_mdio_enable();
+ keystone2_mdio_reset(mdio_bus);
- keystone_sgmii_config(eth_priv->slave_port - 1,
+ keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1,
eth_priv->sgmii_link_type);
udelay(10000);
printf("ERROR: qm_init()\n");
return -1;
}
- if (netcp_init(&net_rx_buffs)) {
+ if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) {
qm_close();
printf("ERROR: netcp_init()\n");
return -1;
hw_config_streaming_switch();
if (sys_has_mdio) {
- /* Init MDIO & get link state */
- clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
- writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE |
- MDIO_CONTROL_FAULT, &adap_mdio->control)
- ;
-
- /* We need to wait for MDIO to start */
- udelay(1000);
-
- link = keystone_get_link_status(dev);
- if (link == 0) {
- netcp_close();
+ keystone2_mdio_reset(mdio_bus);
+
+ phy_startup(phy_dev);
+ if (phy_dev->link == 0) {
+ ksnav_close(&netcp_pktdma);
qm_close();
return -1;
}
/* Eth device close */
void keystone2_eth_close(struct eth_device *dev)
{
+ struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
+ struct phy_device *phy_dev = eth_priv->phy_dev;
+
debug("+ emac_close\n");
if (!emac_open)
ethss_stop();
- netcp_close();
+ ksnav_close(&netcp_pktdma);
qm_close();
+ phy_shutdown(phy_dev);
emac_open = 0;
debug("- emac_close\n");
}
-static int tx_send_loop;
-
/*
* This function sends a single packet on the network and returns
* positive number (number of bytes transmitted) or negative for error
{
int ret_status = -1;
struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
+ struct phy_device *phy_dev = eth_priv->phy_dev;
- tx_send_loop = 0;
-
- if (keystone_get_link_status(dev) == 0)
+ genphy_update_link(phy_dev);
+ if (phy_dev->link == 0)
return -1;
- emac_gigabit_enable(dev);
-
if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0)
return ret_status;
- if (keystone_get_link_status(dev) == 0)
- return -1;
-
- emac_gigabit_enable(dev);
-
return length;
}
int pkt_size;
u32 *pkt;
- hd = netcp_recv(&pkt, &pkt_size);
+ hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size);
if (hd == NULL)
return 0;
NetReceive((uchar *)pkt, pkt_size);
- netcp_release_rxhd(hd);
+ ksnav_release_rxhd(&netcp_pktdma, hd);
return pkt_size;
}
*/
int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
{
+ int res;
struct eth_device *dev;
+ struct phy_device *phy_dev;
dev = malloc(sizeof(struct eth_device));
if (dev == NULL)
eth_register(dev);
- return 0;
-}
-
-void sgmii_serdes_setup_156p25mhz(void)
-{
- unsigned int cnt;
-
- /*
- * configure Serializer/Deserializer (SerDes) hardware. SerDes IP
- * hardware vendor published only register addresses and their values
- * to be used for configuring SerDes. So had to use hardcoded values
- * below.
- */
- clrsetbits_le32(0x0232a000, 0xffff0000, 0x00800000);
- clrsetbits_le32(0x0232a014, 0x0000ffff, 0x00008282);
- clrsetbits_le32(0x0232a060, 0x00ffffff, 0x00142438);
- clrsetbits_le32(0x0232a064, 0x00ffff00, 0x00c3c700);
- clrsetbits_le32(0x0232a078, 0x0000ff00, 0x0000c000);
-
- clrsetbits_le32(0x0232a204, 0xff0000ff, 0x38000080);
- clrsetbits_le32(0x0232a208, 0x000000ff, 0x00000000);
- clrsetbits_le32(0x0232a20c, 0xff000000, 0x02000000);
- clrsetbits_le32(0x0232a210, 0xff000000, 0x1b000000);
- clrsetbits_le32(0x0232a214, 0x0000ffff, 0x00006fb8);
- clrsetbits_le32(0x0232a218, 0xffff00ff, 0x758000e4);
- clrsetbits_le32(0x0232a2ac, 0x0000ff00, 0x00004400);
- clrsetbits_le32(0x0232a22c, 0x00ffff00, 0x00200800);
- clrsetbits_le32(0x0232a280, 0x00ff00ff, 0x00820082);
- clrsetbits_le32(0x0232a284, 0xffffffff, 0x1d0f0385);
-
- clrsetbits_le32(0x0232a404, 0xff0000ff, 0x38000080);
- clrsetbits_le32(0x0232a408, 0x000000ff, 0x00000000);
- clrsetbits_le32(0x0232a40c, 0xff000000, 0x02000000);
- clrsetbits_le32(0x0232a410, 0xff000000, 0x1b000000);
- clrsetbits_le32(0x0232a414, 0x0000ffff, 0x00006fb8);
- clrsetbits_le32(0x0232a418, 0xffff00ff, 0x758000e4);
- clrsetbits_le32(0x0232a4ac, 0x0000ff00, 0x00004400);
- clrsetbits_le32(0x0232a42c, 0x00ffff00, 0x00200800);
- clrsetbits_le32(0x0232a480, 0x00ff00ff, 0x00820082);
- clrsetbits_le32(0x0232a484, 0xffffffff, 0x1d0f0385);
-
- clrsetbits_le32(0x0232a604, 0xff0000ff, 0x38000080);
- clrsetbits_le32(0x0232a608, 0x000000ff, 0x00000000);
- clrsetbits_le32(0x0232a60c, 0xff000000, 0x02000000);
- clrsetbits_le32(0x0232a610, 0xff000000, 0x1b000000);
- clrsetbits_le32(0x0232a614, 0x0000ffff, 0x00006fb8);
- clrsetbits_le32(0x0232a618, 0xffff00ff, 0x758000e4);
- clrsetbits_le32(0x0232a6ac, 0x0000ff00, 0x00004400);
- clrsetbits_le32(0x0232a62c, 0x00ffff00, 0x00200800);
- clrsetbits_le32(0x0232a680, 0x00ff00ff, 0x00820082);
- clrsetbits_le32(0x0232a684, 0xffffffff, 0x1d0f0385);
-
- clrsetbits_le32(0x0232a804, 0xff0000ff, 0x38000080);
- clrsetbits_le32(0x0232a808, 0x000000ff, 0x00000000);
- clrsetbits_le32(0x0232a80c, 0xff000000, 0x02000000);
- clrsetbits_le32(0x0232a810, 0xff000000, 0x1b000000);
- clrsetbits_le32(0x0232a814, 0x0000ffff, 0x00006fb8);
- clrsetbits_le32(0x0232a818, 0xffff00ff, 0x758000e4);
- clrsetbits_le32(0x0232a8ac, 0x0000ff00, 0x00004400);
- clrsetbits_le32(0x0232a82c, 0x00ffff00, 0x00200800);
- clrsetbits_le32(0x0232a880, 0x00ff00ff, 0x00820082);
- clrsetbits_le32(0x0232a884, 0xffffffff, 0x1d0f0385);
-
- clrsetbits_le32(0x0232aa00, 0x0000ff00, 0x00000800);
- clrsetbits_le32(0x0232aa08, 0xffff0000, 0x38a20000);
- clrsetbits_le32(0x0232aa30, 0x00ffff00, 0x008a8a00);
- clrsetbits_le32(0x0232aa84, 0x0000ff00, 0x00000600);
- clrsetbits_le32(0x0232aa94, 0xff000000, 0x10000000);
- clrsetbits_le32(0x0232aaa0, 0xff000000, 0x81000000);
- clrsetbits_le32(0x0232aabc, 0xff000000, 0xff000000);
- clrsetbits_le32(0x0232aac0, 0x000000ff, 0x0000008b);
- clrsetbits_le32(0x0232ab08, 0xffff0000, 0x583f0000);
- clrsetbits_le32(0x0232ab0c, 0x000000ff, 0x0000004e);
- clrsetbits_le32(0x0232a000, 0x000000ff, 0x00000003);
- clrsetbits_le32(0x0232aa00, 0x000000ff, 0x0000005f);
-
- clrsetbits_le32(0x0232aa48, 0x00ffff00, 0x00fd8c00);
- clrsetbits_le32(0x0232aa54, 0x00ffffff, 0x002fec72);
- clrsetbits_le32(0x0232aa58, 0xffffff00, 0x00f92100);
- clrsetbits_le32(0x0232aa5c, 0xffffffff, 0x00040060);
- clrsetbits_le32(0x0232aa60, 0xffffffff, 0x00008000);
- clrsetbits_le32(0x0232aa64, 0xffffffff, 0x0c581220);
- clrsetbits_le32(0x0232aa68, 0xffffffff, 0xe13b0602);
- clrsetbits_le32(0x0232aa6c, 0xffffffff, 0xb8074cc1);
- clrsetbits_le32(0x0232aa70, 0xffffffff, 0x3f02e989);
- clrsetbits_le32(0x0232aa74, 0x000000ff, 0x00000001);
- clrsetbits_le32(0x0232ab20, 0x00ff0000, 0x00370000);
- clrsetbits_le32(0x0232ab1c, 0xff000000, 0x37000000);
- clrsetbits_le32(0x0232ab20, 0x000000ff, 0x0000005d);
-
- /*Bring SerDes out of Reset if SerDes is Shutdown & is in Reset Mode*/
- clrbits_le32(0x0232a010, 1 << 28);
-
- /* Enable TX and RX via the LANExCTL_STS 0x0000 + x*4 */
- clrbits_le32(0x0232a228, 1 << 29);
- writel(0xF800F8C0, 0x0232bfe0);
- clrbits_le32(0x0232a428, 1 << 29);
- writel(0xF800F8C0, 0x0232bfe4);
- clrbits_le32(0x0232a628, 1 << 29);
- writel(0xF800F8C0, 0x0232bfe8);
- clrbits_le32(0x0232a828, 1 << 29);
- writel(0xF800F8C0, 0x0232bfec);
-
- /*Enable pll via the pll_ctrl 0x0014*/
- writel(0xe0000000, 0x0232bff4)
- ;
-
- /*Waiting for SGMII Serdes PLL lock.*/
- for (cnt = 10000; cnt > 0 && ((readl(0x02090114) & 0x10) == 0); cnt--)
- ;
-
- for (cnt = 10000; cnt > 0 && ((readl(0x02090214) & 0x10) == 0); cnt--)
- ;
-
- for (cnt = 10000; cnt > 0 && ((readl(0x02090414) & 0x10) == 0); cnt--)
- ;
+ /* Register MDIO bus if it's not registered yet */
+ if (!mdio_bus) {
+ mdio_bus = mdio_alloc();
+ mdio_bus->read = keystone2_mdio_read;
+ mdio_bus->write = keystone2_mdio_write;
+ mdio_bus->reset = keystone2_mdio_reset;
+ mdio_bus->priv = (void *)EMAC_MDIO_BASE_ADDR;
+ sprintf(mdio_bus->name, "ethernet-mdio");
+
+ res = mdio_register(mdio_bus);
+ if (res)
+ return res;
+ }
- for (cnt = 10000; cnt > 0 && ((readl(0x02090514) & 0x10) == 0); cnt--)
- ;
+ /* Create phy device and bind it with driver */
+#ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
+ phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr,
+ dev, PHY_INTERFACE_MODE_SGMII);
+ phy_config(phy_dev);
+#else
+ phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr,
+ PHY_INTERFACE_MODE_SGMII);
+ phy_dev->dev = dev;
+#endif
+ eth_priv->phy_dev = phy_dev;
- udelay(45000);
+ return 0;
}
-void sgmii_serdes_shutdown(void)
+struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
+ .clk = SERDES_CLOCK_156P25M,
+ .rate = SERDES_RATE_5G,
+ .rate_mode = SERDES_QUARTER_RATE,
+ .intf = SERDES_PHY_SGMII,
+ .loopback = 0,
+};
+
+static void keystone2_net_serdes_setup(void)
{
- /*
- * shutdown SerDes hardware. SerDes hardware vendor published only
- * register addresses and their values. So had to use hardcoded
- * values below.
- */
- clrbits_le32(0x0232bfe0, 3 << 29 | 3 << 13);
- setbits_le32(0x02320228, 1 << 29);
- clrbits_le32(0x0232bfe4, 3 << 29 | 3 << 13);
- setbits_le32(0x02320428, 1 << 29);
- clrbits_le32(0x0232bfe8, 3 << 29 | 3 << 13);
- setbits_le32(0x02320628, 1 << 29);
- clrbits_le32(0x0232bfec, 3 << 29 | 3 << 13);
- setbits_le32(0x02320828, 1 << 29);
-
- clrbits_le32(0x02320034, 3 << 29);
- setbits_le32(0x02320010, 1 << 28);
+ ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
+ &ks2_serdes_sgmii_156p25mhz,
+ CONFIG_KSNET_SERDES_LANES_PER_SGMII);
+
+#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
+ ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
+ &ks2_serdes_sgmii_156p25mhz,
+ CONFIG_KSNET_SERDES_LANES_PER_SGMII);
+#endif
+
+ /* wait till setup */
+ udelay(5000);
}
return 0;
}
+/**
+ * m88e1518_phy_writebits - write bits to a register
+ */
+void m88e1518_phy_writebits(struct phy_device *phydev,
+ u8 reg_num, u16 offset, u16 len, u16 data)
+{
+ u16 reg, mask;
+
+ if ((len + offset) >= 16)
+ mask = 0 - (1 << offset);
+ else
+ mask = (1 << (len + offset)) - (1 << offset);
+
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num);
+
+ reg &= ~mask;
+ reg |= data << offset;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg);
+}
+
+static int m88e1518_config(struct phy_device *phydev)
+{
+ /*
+ * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512
+ * /88E1514 Rev A0, Errata Section 3.1
+ */
+ if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00ff); /* page 0xff */
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B);
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144);
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28);
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146);
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233);
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C);
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159);
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); /* reg page 0 */
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 18); /* reg page 18 */
+ /* Write HWCFG_MODE = SGMII to Copper */
+ m88e1518_phy_writebits(phydev, 20, 0, 3, 1);
+
+ /* Phy reset */
+ m88e1518_phy_writebits(phydev, 20, 15, 1, 1);
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); /* reg page 18 */
+ udelay(100);
+ }
+
+ return m88e1111s_config(phydev);
+}
+
/* Marvell 88E1118 */
static int m88e1118_config(struct phy_device *phydev)
{
.uid = 0x1410dd1,
.mask = 0xffffff0,
.features = PHY_GBIT_FEATURES,
- .config = &m88e1111s_config,
+ .config = &m88e1518_config,
.startup = &m88e1011s_startup,
.shutdown = &genphy_shutdown,
};
* Description: Reads the ID registers of the PHY at @addr on the
* @bus, stores it in @phy_id and returns zero on success.
*/
-int __weak get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
+static int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
{
int phy_reg;
if (phydev)
return phydev;
}
- printf("Phy not found\n");
+ printf("Phy %d not found\n", ffs(phy_mask) - 1);
return phy_device_create(bus, ffs(phy_mask) - 1, 0xffffffff, interface);
}
return 0;
}
-static int __board_phy_config(struct phy_device *phydev)
+__weak int board_phy_config(struct phy_device *phydev)
{
if (phydev->drv->config)
return phydev->drv->config(phydev);
return 0;
}
-int board_phy_config(struct phy_device *phydev)
- __attribute__((weak, alias("__board_phy_config")));
-
int phy_config(struct phy_device *phydev)
{
/* Invoke an optional board-specific helper */
* sh_eth.c - Driver for Renesas ethernet controler.
*
* Copyright (C) 2008, 2011 Renesas Solutions Corp.
- * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
+ * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
- * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013, 2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
else
port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
+ flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
+
/* Restart the transmitter if disabled */
if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS))
sh_eth_write(eth, EDTRR_TRNS, EDTRR);
port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
else
port_info->rx_desc_cur->rd0 = RD_RACT;
+
+ flush_cache_wback(port_info->rx_desc_cur,
+ sizeof(struct rx_desc_s));
+
/* Point to the next descriptor */
port_info->rx_desc_cur++;
if (port_info->rx_desc_cur >=
static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
{
int port = eth->port, i, ret = 0;
- u32 tmp_addr;
+ u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
struct sh_eth_info *port_info = ð->port_info[port];
struct tx_desc_s *cur_tx_desc;
/*
- * Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned
+ * Allocate rx descriptors. They must be aligned to size of struct
+ * tx_desc_s.
*/
- port_info->tx_desc_malloc = malloc(NUM_TX_DESC *
- sizeof(struct tx_desc_s) +
- TX_DESC_SIZE - 1);
- if (!port_info->tx_desc_malloc) {
- printf(SHETHER_NAME ": malloc failed\n");
+ port_info->tx_desc_alloc =
+ memalign(sizeof(struct tx_desc_s), alloc_desc_size);
+ if (!port_info->tx_desc_alloc) {
+ printf(SHETHER_NAME ": memalign failed\n");
ret = -ENOMEM;
goto err;
}
- tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) &
- ~(TX_DESC_SIZE - 1));
- flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s));
+ flush_cache_wback((u32)port_info->tx_desc_alloc, alloc_desc_size);
+
/* Make sure we use a P2 address (non-cacheable) */
- port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr);
+ port_info->tx_desc_base =
+ (struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc);
port_info->tx_desc_cur = port_info->tx_desc_base;
/* Initialize all descriptors */
static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
{
int port = eth->port, i , ret = 0;
+ u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
struct sh_eth_info *port_info = ð->port_info[port];
struct rx_desc_s *cur_rx_desc;
- u32 tmp_addr;
u8 *rx_buf;
/*
- * Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned
+ * Allocate rx descriptors. They must be aligned to size of struct
+ * rx_desc_s.
*/
- port_info->rx_desc_malloc = malloc(NUM_RX_DESC *
- sizeof(struct rx_desc_s) +
- RX_DESC_SIZE - 1);
- if (!port_info->rx_desc_malloc) {
- printf(SHETHER_NAME ": malloc failed\n");
+ port_info->rx_desc_alloc =
+ memalign(sizeof(struct rx_desc_s), alloc_desc_size);
+ if (!port_info->rx_desc_alloc) {
+ printf(SHETHER_NAME ": memalign failed\n");
ret = -ENOMEM;
goto err;
}
- tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) &
- ~(RX_DESC_SIZE - 1));
- flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s));
+ flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
+
/* Make sure we use a P2 address (non-cacheable) */
- port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr);
+ port_info->rx_desc_base =
+ (struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc);
port_info->rx_desc_cur = port_info->rx_desc_base;
/*
- * Allocate rx data buffers. They must be 32 bytes aligned and in
- * P2 area
+ * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
+ * aligned and in P2 area.
*/
- port_info->rx_buf_malloc = malloc(
- NUM_RX_DESC * MAX_BUF_SIZE + RX_BUF_ALIGNE_SIZE - 1);
- if (!port_info->rx_buf_malloc) {
- printf(SHETHER_NAME ": malloc failed\n");
+ port_info->rx_buf_alloc =
+ memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
+ if (!port_info->rx_buf_alloc) {
+ printf(SHETHER_NAME ": alloc failed\n");
ret = -ENOMEM;
- goto err_buf_malloc;
+ goto err_buf_alloc;
}
- tmp_addr = (u32)(((int)port_info->rx_buf_malloc
- + (RX_BUF_ALIGNE_SIZE - 1)) &
- ~(RX_BUF_ALIGNE_SIZE - 1));
- port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);
+ port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc);
/* Initialize all descriptors */
for (cur_rx_desc = port_info->rx_desc_base,
return ret;
-err_buf_malloc:
- free(port_info->rx_desc_malloc);
- port_info->rx_desc_malloc = NULL;
+err_buf_alloc:
+ free(port_info->rx_desc_alloc);
+ port_info->rx_desc_alloc = NULL;
err:
return ret;
int port = eth->port;
struct sh_eth_info *port_info = ð->port_info[port];
- if (port_info->tx_desc_malloc) {
- free(port_info->tx_desc_malloc);
- port_info->tx_desc_malloc = NULL;
+ if (port_info->tx_desc_alloc) {
+ free(port_info->tx_desc_alloc);
+ port_info->tx_desc_alloc = NULL;
}
}
int port = eth->port;
struct sh_eth_info *port_info = ð->port_info[port];
- if (port_info->rx_desc_malloc) {
- free(port_info->rx_desc_malloc);
- port_info->rx_desc_malloc = NULL;
+ if (port_info->rx_desc_alloc) {
+ free(port_info->rx_desc_alloc);
+ port_info->rx_desc_alloc = NULL;
}
- if (port_info->rx_buf_malloc) {
- free(port_info->rx_buf_malloc);
- port_info->rx_buf_malloc = NULL;
+ if (port_info->rx_buf_alloc) {
+ free(port_info->rx_buf_alloc);
+ port_info->rx_buf_alloc = NULL;
}
}
#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
- defined(CONFIG_R8A7794)
+ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR);
#endif
/* Configure phy */
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
sh_eth_write(eth, 1, RTRATE);
#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
- defined(CONFIG_R8A7791) || defined(CONFIG_R8A7794)
+ defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
+ defined(CONFIG_R8A7794)
val = ECMR_RTM;
#endif
} else if (phy->speed == 10) {
/* The size of the tx descriptor is determined by how much padding is used.
4, 20, or 52 bytes of padding can be used */
#define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
-/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
-#define TX_DESC_SIZE (12 + TX_DESC_PADDING)
/* Tx descriptor. We always use 3 bytes of padding */
struct tx_desc_s {
/* The size of the rx descriptor is determined by how much padding is used.
4, 20, or 52 bytes of padding can be used */
#define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
-/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
-#define RX_DESC_SIZE (12 + RX_DESC_PADDING)
/* aligned cache line size */
#define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
};
struct sh_eth_info {
- struct tx_desc_s *tx_desc_malloc;
+ struct tx_desc_s *tx_desc_alloc;
struct tx_desc_s *tx_desc_base;
struct tx_desc_s *tx_desc_cur;
- struct rx_desc_s *rx_desc_malloc;
+ struct rx_desc_s *rx_desc_alloc;
struct rx_desc_s *rx_desc_base;
struct rx_desc_s *rx_desc_cur;
- u8 *rx_buf_malloc;
+ u8 *rx_buf_alloc;
u8 *rx_buf_base;
u8 mac_addr[6];
u8 phy_addr;
#define SH_ETH_TYPE_GETHER
#define BASE_IO_ADDR 0xE9A00000
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
- defined(CONFIG_R8A7794)
+ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
#define SH_ETH_TYPE_ETHER
#define BASE_IO_ADDR 0xEE700200
#elif defined(CONFIG_R7S72100)
#ifdef CONFIG_CPU_SH7724
ECMR_RTM = 0x00000010,
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
- defined(CONFIG_R8A7794)
+ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
ECMR_RTM = 0x00000004,
#endif
static void smc911x_halt(struct eth_device *dev)
{
smc911x_reset(dev);
+ smc911x_handle_mac_address(dev);
}
static int smc911x_rx(struct eth_device *dev)
rdes0 = le32_to_cpu(rxptr->rdes0);
#ifdef RX_DEBUG
- printf("%s(): rxptr->rdes0=%x:%x\n", __FUNCTION__, rxptr->rdes0);
+ printf("%s(): rxptr->rdes0=%x\n", __FUNCTION__, rxptr->rdes0);
#endif
if (!(rdes0 & 0x80000000)) { /* packet owner check */
if ((rdes0 & 0x300) != 0x300) {
}
#endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */
-int __pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
+__weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
{
/*
* Check if pci device should be skipped in configuration
return 0;
}
-int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
- __attribute__((weak, alias("__pci_skip_dev")));
#ifdef CONFIG_PCI_SCAN_SHOW
-int __pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
+__weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
{
if (dev == PCI_BDF(hose->first_busno, 0, 0))
return 0;
return 1;
}
-int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
- __attribute__((weak, alias("__pci_print_dev")));
#endif /* CONFIG_PCI_SCAN_SHOW */
int pci_hose_scan_bus(struct pci_controller *hose, int bus)
static struct spi_slave *slave;
-void pmic_spi_free(struct spi_slave *slave)
-{
- if (slave)
- spi_free_slave(slave);
-}
-
-struct spi_slave *pmic_spi_probe(struct pmic *p)
-{
- return spi_setup_slave(p->bus,
- p->hw.spi.cs,
- p->hw.spi.clk,
- p->hw.spi.mode);
-}
-
static u32 pmic_reg(struct pmic *p, u32 reg, u32 *val, u32 write)
{
u32 pmic_tx, pmic_rx;
u32 tmp;
if (!slave) {
- slave = pmic_spi_probe(p);
+ slave = spi_setup_slave(p->bus, p->hw.spi.cs, p->hw.spi.clk,
+ p->hw.spi.mode);
if (!slave)
return -1;
tmp = cpu_to_be32(pmic_tx);
if (spi_xfer(slave, pmic_spi_bitlen, &tmp, &pmic_rx,
- pmic_spi_flags)) {
- spi_release_bus(slave);
- return -1;
- }
+ pmic_spi_flags))
+ goto err;
if (write) {
pmic_tx = p->hw.spi.prepare_tx(reg, val, 0);
tmp = cpu_to_be32(pmic_tx);
if (spi_xfer(slave, pmic_spi_bitlen, &tmp, &pmic_rx,
- pmic_spi_flags)) {
- spi_release_bus(slave);
- return -1;
- }
+ pmic_spi_flags))
+ goto err;
}
spi_release_bus(slave);
*val = cpu_to_be32(pmic_rx);
return 0;
+
+err:
+ spi_release_bus(slave);
+ return -1;
}
int pmic_reg_write(struct pmic *p, u32 reg, u32 val)
TWL4030_PM_RECEIVER_VMMC1_VSEL_32,
TWL4030_PM_RECEIVER_VMMC1_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
+
+ /* Set VMMC2 to 3.15 Volts */
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC2_DEDICATED,
+ TWL4030_PM_RECEIVER_VMMC2_VSEL_32,
+ TWL4030_PM_RECEIVER_VMMC2_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
}
+config DM_SERIAL
+ bool "Enable Driver Model for serial drivers"
+ depends on DM
+ help
+ If you want to use driver model for serial drivers, say Y.
+ To use legacy serial drivers, say N.
+
+config UNIPHIER_SERIAL
+ bool "UniPhier on-chip UART support"
+ depends on ARCH_UNIPHIER && DM_SERIAL
+ help
+ Support for the on-chip UARTs on the Panasonic UniPhier platform.
obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
obj-$(CONFIG_ARM_DCC) += arm_dcc.o
obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
+obj-$(CONFIG_DW_SERIAL) += serial_dw.o
obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
obj-$(CONFIG_MCFUART) += mcfuart.o
obj-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o
obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
+obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
+obj-$(CONFIG_COREBOOT_SERIAL) += serial_coreboot.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_TTY) += usbtty.o
unsigned char *addr;
offset *= 1 << plat->reg_shift;
- addr = plat->base + offset;
+ addr = map_sysmem(plat->base, 0) + offset;
/*
* As far as we know it doesn't make sense to support selection of
* these options at run-time, so use the existing CONFIG options.
*/
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
- outb(value, addr);
+ outb(value, (ulong)addr);
#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN)
out_le32(addr, value);
#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
unsigned char *addr;
offset *= 1 << plat->reg_shift;
- addr = plat->base + offset;
+ addr = map_sysmem(plat->base, 0) + offset;
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
- return inb(addr);
+ return inb((ulong)addr);
#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN)
return in_le32(addr);
#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
{
struct NS16550 *const com_port = dev_get_priv(dev);
- if (!serial_in(&com_port->lsr) & UART_LSR_DR)
+ if (!(serial_in(&com_port->lsr) & UART_LSR_DR))
return -EAGAIN;
return serial_in(&com_port->rbr);
{
struct NS16550 *const com_port = dev_get_priv(dev);
+ com_port->plat = dev_get_platdata(dev);
NS16550_init(com_port, -1);
return 0;
}
+#ifdef CONFIG_OF_CONTROL
int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
{
- struct NS16550 *const com_port = dev_get_priv(dev);
struct ns16550_platdata *plat = dev->platdata;
fdt_addr_t addr;
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
- plat->base = (unsigned char *)addr;
+ plat->base = addr;
plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"reg-shift", 1);
- com_port->plat = plat;
return 0;
}
+#endif
const struct dm_serial_ops ns16550_serial_ops = {
.putc = ns16550_serial_putc,
#include <os.h>
#include <serial.h>
#include <stdio_dev.h>
+#include <watchdog.h>
#include <dm/lists.h>
#include <dm/device-internal.h>
+#include <ns16550.h>
+
DECLARE_GLOBAL_DATA_PTR;
/* The currently-selected console serial device */
}
#endif
/*
+ * Try to use CONFIG_CONS_INDEX if available (it is numbered from 1!).
+ *
* Failing that, get the device with sequence number 0, or in extremis
* just the first serial device we can find. But we insist on having
* a console (even if it is silent).
*/
- if (uclass_get_device_by_seq(UCLASS_SERIAL, 0, &cur_dev) &&
+#ifdef CONFIG_CONS_INDEX
+#define INDEX (CONFIG_CONS_INDEX - 1)
+#else
+#define INDEX 0
+#endif
+ if (uclass_get_device_by_seq(UCLASS_SERIAL, INDEX, &cur_dev) &&
+ uclass_get_device(UCLASS_SERIAL, INDEX, &cur_dev) &&
(uclass_first_device(UCLASS_SERIAL, &cur_dev) || !cur_dev))
panic("No serial driver found");
+#undef INDEX
}
/* Called prior to relocation */
serial_find_console_or_panic();
}
-static void serial_putc_dev(struct udevice *dev, char ch)
+static void _serial_putc(struct udevice *dev, char ch)
{
- struct dm_serial_ops *ops = serial_get_ops(cur_dev);
+ struct dm_serial_ops *ops = serial_get_ops(dev);
int err;
do {
- err = ops->putc(cur_dev, ch);
+ err = ops->putc(dev, ch);
} while (err == -EAGAIN);
if (ch == '\n')
- serial_putc('\r');
+ _serial_putc(dev, '\r');
}
-void serial_putc(char ch)
+static void _serial_puts(struct udevice *dev, const char *str)
{
- serial_putc_dev(cur_dev, ch);
+ while (*str)
+ _serial_putc(dev, *str++);
}
-void serial_setbrg(void)
+static int _serial_getc(struct udevice *dev)
{
- struct dm_serial_ops *ops = serial_get_ops(cur_dev);
+ struct dm_serial_ops *ops = serial_get_ops(dev);
+ int err;
- if (ops->setbrg)
- ops->setbrg(cur_dev, gd->baudrate);
-}
+ do {
+ err = ops->getc(dev);
+ if (err == -EAGAIN)
+ WATCHDOG_RESET();
+ } while (err == -EAGAIN);
-void serial_puts(const char *str)
-{
- while (*str)
- serial_putc(*str++);
+ return err >= 0 ? err : 0;
}
-int serial_tstc(void)
+static int _serial_tstc(struct udevice *dev)
{
- struct dm_serial_ops *ops = serial_get_ops(cur_dev);
+ struct dm_serial_ops *ops = serial_get_ops(dev);
if (ops->pending)
- return ops->pending(cur_dev, true);
+ return ops->pending(dev, true);
return 1;
}
-static int serial_getc_dev(struct udevice *dev)
+void serial_putc(char ch)
{
- struct dm_serial_ops *ops = serial_get_ops(dev);
- int err;
-
- do {
- err = ops->getc(dev);
- } while (err == -EAGAIN);
+ _serial_putc(cur_dev, ch);
+}
- return err >= 0 ? err : 0;
+void serial_puts(const char *str)
+{
+ _serial_puts(cur_dev, str);
}
int serial_getc(void)
{
- return serial_getc_dev(cur_dev);
+ return _serial_getc(cur_dev);
+}
+
+int serial_tstc(void)
+{
+ return _serial_tstc(cur_dev);
+}
+
+void serial_setbrg(void)
+{
+ struct dm_serial_ops *ops = serial_get_ops(cur_dev);
+
+ if (ops->setbrg)
+ ops->setbrg(cur_dev, gd->baudrate);
}
void serial_stdio_init(void)
static void serial_stub_putc(struct stdio_dev *sdev, const char ch)
{
- struct udevice *dev = sdev->priv;
-
- serial_putc_dev(dev, ch);
+ _serial_putc(sdev->priv, ch);
}
void serial_stub_puts(struct stdio_dev *sdev, const char *str)
{
- while (*str)
- serial_stub_putc(sdev, *str++);
+ _serial_puts(sdev->priv, str);
}
int serial_stub_getc(struct stdio_dev *sdev)
{
- struct udevice *dev = sdev->priv;
-
- return serial_getc_dev(dev);
+ return _serial_getc(sdev->priv);
}
int serial_stub_tstc(struct stdio_dev *sdev)
{
- struct udevice *dev = sdev->priv;
- struct dm_serial_ops *ops = serial_get_ops(dev);
-
- if (ops->pending)
- return ops->pending(dev, true);
-
- return 1;
+ return _serial_tstc(sdev->priv);
}
static int serial_post_probe(struct udevice *dev)
void name(void) \
__attribute__((weak, alias("serial_null")));
-serial_initfunc(mpc8xx_serial_initialize);
-serial_initfunc(ns16550_serial_initialize);
-serial_initfunc(pxa_serial_initialize);
-serial_initfunc(s3c24xx_serial_initialize);
-serial_initfunc(s5p_serial_initialize);
-serial_initfunc(zynq_serial_initialize);
-serial_initfunc(bfin_serial_initialize);
-serial_initfunc(bfin_jtag_initialize);
-serial_initfunc(mpc512x_serial_initialize);
-serial_initfunc(uartlite_serial_initialize);
-serial_initfunc(au1x00_serial_initialize);
-serial_initfunc(asc_serial_initialize);
-serial_initfunc(jz_serial_initialize);
-serial_initfunc(mpc5xx_serial_initialize);
-serial_initfunc(mpc8260_scc_serial_initialize);
-serial_initfunc(mpc8260_smc_serial_initialize);
-serial_initfunc(mpc85xx_serial_initialize);
-serial_initfunc(iop480_serial_initialize);
-serial_initfunc(leon2_serial_initialize);
-serial_initfunc(leon3_serial_initialize);
-serial_initfunc(marvell_serial_initialize);
+serial_initfunc(altera_jtag_serial_initialize);
+serial_initfunc(altera_serial_initialize);
serial_initfunc(amirix_serial_initialize);
+serial_initfunc(arc_serial_initialize);
+serial_initfunc(arm_dcc_initialize);
+serial_initfunc(asc_serial_initialize);
+serial_initfunc(atmel_serial_initialize);
+serial_initfunc(au1x00_serial_initialize);
+serial_initfunc(bfin_jtag_initialize);
+serial_initfunc(bfin_serial_initialize);
serial_initfunc(bmw_serial_initialize);
+serial_initfunc(clps7111_serial_initialize);
serial_initfunc(cogent_serial_initialize);
serial_initfunc(cpci750_serial_initialize);
serial_initfunc(evb64260_serial_initialize);
-serial_initfunc(ml2_serial_initialize);
-serial_initfunc(sconsole_serial_initialize);
-serial_initfunc(p3mx_serial_initialize);
-serial_initfunc(altera_jtag_serial_initialize);
-serial_initfunc(altera_serial_initialize);
-serial_initfunc(atmel_serial_initialize);
-serial_initfunc(lpc32xx_serial_initialize);
-serial_initfunc(mcf_serial_initialize);
-serial_initfunc(oc_serial_initialize);
-serial_initfunc(sandbox_serial_initialize);
-serial_initfunc(clps7111_serial_initialize);
serial_initfunc(imx_serial_initialize);
+serial_initfunc(iop480_serial_initialize);
+serial_initfunc(jz_serial_initialize);
serial_initfunc(ks8695_serial_initialize);
+serial_initfunc(leon2_serial_initialize);
+serial_initfunc(leon3_serial_initialize);
serial_initfunc(lh7a40x_serial_initialize);
+serial_initfunc(lpc32xx_serial_initialize);
+serial_initfunc(marvell_serial_initialize);
serial_initfunc(max3100_serial_initialize);
+serial_initfunc(mcf_serial_initialize);
+serial_initfunc(ml2_serial_initialize);
+serial_initfunc(mpc512x_serial_initialize);
+serial_initfunc(mpc5xx_serial_initialize);
+serial_initfunc(mpc8260_scc_serial_initialize);
+serial_initfunc(mpc8260_smc_serial_initialize);
+serial_initfunc(mpc85xx_serial_initialize);
+serial_initfunc(mpc8xx_serial_initialize);
serial_initfunc(mxc_serial_initialize);
+serial_initfunc(mxs_auart_initialize);
+serial_initfunc(ns16550_serial_initialize);
+serial_initfunc(oc_serial_initialize);
+serial_initfunc(p3mx_serial_initialize);
serial_initfunc(pl01x_serial_initialize);
+serial_initfunc(pxa_serial_initialize);
+serial_initfunc(s3c24xx_serial_initialize);
+serial_initfunc(s5p_serial_initialize);
serial_initfunc(sa1100_serial_initialize);
+serial_initfunc(sandbox_serial_initialize);
+serial_initfunc(sconsole_serial_initialize);
serial_initfunc(sh_serial_initialize);
-serial_initfunc(arm_dcc_initialize);
-serial_initfunc(mxs_auart_initialize);
-serial_initfunc(arc_serial_initialize);
-serial_initfunc(uniphier_serial_initialize);
+serial_initfunc(uartlite_serial_initialize);
+serial_initfunc(zynq_serial_initialize);
/**
* serial_register() - Register serial driver with serial driver core
*/
void serial_initialize(void)
{
- mpc8xx_serial_initialize();
- ns16550_serial_initialize();
- pxa_serial_initialize();
- s3c24xx_serial_initialize();
- s5p_serial_initialize();
- mpc512x_serial_initialize();
- bfin_serial_initialize();
- bfin_jtag_initialize();
- uartlite_serial_initialize();
- zynq_serial_initialize();
- au1x00_serial_initialize();
- asc_serial_initialize();
- jz_serial_initialize();
- mpc5xx_serial_initialize();
- mpc8260_scc_serial_initialize();
- mpc8260_smc_serial_initialize();
- mpc85xx_serial_initialize();
- iop480_serial_initialize();
- leon2_serial_initialize();
- leon3_serial_initialize();
- marvell_serial_initialize();
+ altera_jtag_serial_initialize();
+ altera_serial_initialize();
amirix_serial_initialize();
+ arc_serial_initialize();
+ arm_dcc_initialize();
+ asc_serial_initialize();
+ atmel_serial_initialize();
+ au1x00_serial_initialize();
+ bfin_jtag_initialize();
+ bfin_serial_initialize();
bmw_serial_initialize();
+ clps7111_serial_initialize();
cogent_serial_initialize();
cpci750_serial_initialize();
evb64260_serial_initialize();
- ml2_serial_initialize();
- sconsole_serial_initialize();
- p3mx_serial_initialize();
- altera_jtag_serial_initialize();
- altera_serial_initialize();
- atmel_serial_initialize();
- lpc32xx_serial_initialize();
- mcf_serial_initialize();
- oc_serial_initialize();
- sandbox_serial_initialize();
- clps7111_serial_initialize();
imx_serial_initialize();
+ iop480_serial_initialize();
+ jz_serial_initialize();
ks8695_serial_initialize();
+ leon2_serial_initialize();
+ leon3_serial_initialize();
lh7a40x_serial_initialize();
+ lpc32xx_serial_initialize();
+ marvell_serial_initialize();
max3100_serial_initialize();
+ mcf_serial_initialize();
+ ml2_serial_initialize();
+ mpc512x_serial_initialize();
+ mpc5xx_serial_initialize();
+ mpc8260_scc_serial_initialize();
+ mpc8260_smc_serial_initialize();
+ mpc85xx_serial_initialize();
+ mpc8xx_serial_initialize();
mxc_serial_initialize();
+ mxs_auart_initialize();
+ ns16550_serial_initialize();
+ oc_serial_initialize();
+ p3mx_serial_initialize();
pl01x_serial_initialize();
+ pxa_serial_initialize();
+ s3c24xx_serial_initialize();
+ s5p_serial_initialize();
sa1100_serial_initialize();
+ sandbox_serial_initialize();
+ sconsole_serial_initialize();
sh_serial_initialize();
- arm_dcc_initialize();
- mxs_auart_initialize();
- arc_serial_initialize();
- uniphier_serial_initialize();
+ uartlite_serial_initialize();
+ zynq_serial_initialize();
serial_assign(default_serial_console()->name);
}
-int serial_stub_start(struct stdio_dev *sdev)
+static int serial_stub_start(struct stdio_dev *sdev)
{
struct serial_device *dev = sdev->priv;
return dev->start();
}
-int serial_stub_stop(struct stdio_dev *sdev)
+static int serial_stub_stop(struct stdio_dev *sdev)
{
struct serial_device *dev = sdev->priv;
return dev->stop();
}
-void serial_stub_putc(struct stdio_dev *sdev, const char ch)
+static void serial_stub_putc(struct stdio_dev *sdev, const char ch)
{
struct serial_device *dev = sdev->priv;
dev->putc(ch);
}
-void serial_stub_puts(struct stdio_dev *sdev, const char *str)
+static void serial_stub_puts(struct stdio_dev *sdev, const char *str)
{
struct serial_device *dev = sdev->priv;
--- /dev/null
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <serial.h>
+
+static const struct udevice_id coreboot_serial_ids[] = {
+ { .compatible = "coreboot-uart" },
+ { }
+};
+
+static int coreboot_serial_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ns16550_platdata *plat = dev_get_platdata(dev);
+ int ret;
+
+ ret = ns16550_serial_ofdata_to_platdata(dev);
+ if (ret)
+ return ret;
+ plat->clock = 1843200;
+
+ return 0;
+}
+U_BOOT_DRIVER(serial_ns16550) = {
+ .name = "serial_coreboot",
+ .id = UCLASS_SERIAL,
+ .of_match = coreboot_serial_ids,
+ .ofdata_to_platdata = coreboot_serial_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+ .priv_auto_alloc_size = sizeof(struct NS16550),
+ .probe = ns16550_serial_probe,
+ .ops = &ns16550_serial_ops,
+};
--- /dev/null
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <serial.h>
+
+static const struct udevice_id dw_serial_ids[] = {
+ { .compatible = "snps,dw-apb-uart" },
+ { }
+};
+
+static int dw_serial_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ns16550_platdata *plat = dev_get_platdata(dev);
+ int ret;
+
+ ret = ns16550_serial_ofdata_to_platdata(dev);
+ if (ret)
+ return ret;
+ plat->clock = CONFIG_SYS_NS16550_CLK;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(serial_ns16550) = {
+ .name = "serial_dw",
+ .id = UCLASS_SERIAL,
+ .of_match = dw_serial_ids,
+ .ofdata_to_platdata = dw_serial_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+ .priv_auto_alloc_size = sizeof(struct NS16550),
+ .probe = ns16550_serial_probe,
+ .ops = &ns16550_serial_ops,
+};
#include <common.h>
#include <dm.h>
#include <errno.h>
-#include <serial_mxc.h>
#include <watchdog.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
+#include <dm/platform_data/serial_mxc.h>
#include <serial.h>
#include <linux/compiler.h>
.puts = eserial##port##_puts, \
}
-void
-_serial_putc(const char c,const int port)
+static void _serial_putc(const char c, const int port)
{
if (c == '\n')
NS16550_putc(PORT, '\r');
NS16550_putc(PORT, c);
}
-void
-_serial_putc_raw(const char c,const int port)
+static void _serial_putc_raw(const char c, const int port)
{
NS16550_putc(PORT, c);
}
-void
-_serial_puts (const char *s,const int port)
+static void _serial_puts(const char *s, const int port)
{
while (*s) {
- _serial_putc (*s++,port);
+ _serial_putc(*s++, port);
}
}
-
-int
-_serial_getc(const int port)
+static int _serial_getc(const int port)
{
return NS16550_getc(PORT);
}
-int
-_serial_tstc(const int port)
+static int _serial_tstc(const int port)
{
return NS16550_tstc(PORT);
}
-void
-_serial_setbrg (const int port)
+static void _serial_setbrg(const int port)
{
int clock_divisor;
--- /dev/null
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <ns16550.h>
+#include <serial.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_OF_CONTROL
+static const struct udevice_id omap_serial_ids[] = {
+ { .compatible = "ti,omap3-uart" },
+ { }
+};
+
+static int omap_serial_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ns16550_platdata *plat = dev_get_platdata(dev);
+ int ret;
+
+ ret = ns16550_serial_ofdata_to_platdata(dev);
+ if (ret)
+ return ret;
+ plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "clock-frequency", -1);
+ plat->reg_shift = 2;
+
+ return 0;
+}
+#endif
+
+U_BOOT_DRIVER(serial_omap_ns16550) = {
+ .name = "serial_omap",
+ .id = UCLASS_SERIAL,
+ .of_match = of_match_ptr(omap_serial_ids),
+ .ofdata_to_platdata = of_match_ptr(omap_serial_ofdata_to_platdata),
+ .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+ .priv_auto_alloc_size = sizeof(struct NS16550),
+ .probe = ns16550_serial_probe,
+ .ops = &ns16550_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
#include <watchdog.h>
#include <asm/io.h>
#include <serial.h>
-#include <serial_pl01x.h>
+#include <dm/platform_data/serial_pl01x.h>
#include <linux/compiler.h>
#include "serial_pl01x_internal.h"
static int hwflow;
#endif
-void _serial_setbrg(const int dev_index)
+static void _serial_setbrg(const int dev_index)
{
struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
unsigned int reg = 0;
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int _serial_getc(const int dev_index)
+static int _serial_getc(const int dev_index)
{
struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
/*
* Output a single byte to the serial port.
*/
-void _serial_putc(const char c, const int dev_index)
+static void _serial_putc(const char c, const int dev_index)
{
struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
#ifdef CONFIG_MODEM_SUPPORT
/*
* Test whether a character is in the RX buffer
*/
-int _serial_tstc(const int dev_index)
+static int _serial_tstc(const int dev_index)
{
struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
return _serial_tstc(dev_index);
}
-void _serial_puts(const char *s, const int dev_index)
+static void _serial_puts(const char *s, const int dev_index)
{
while (*s) {
_serial_putc(*s++, dev_index);
sci_out(&sh_sci, SCLSR, 0x00);
}
-void serial_raw_putc(const char c)
+static void serial_raw_putc(const char c)
{
while (1) {
/* Tx fifo is empty */
}
-int serial_getc_check(void)
+static int serial_getc_check(void)
{
unsigned short status;
# define SCIF_ORER 0x0001 /* Overrun error bit */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
- defined(CONFIG_R8A7794)
+ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
# define SCIF_ORER 0x0001
# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
#else
/* SH7763 SCIF2 support */
# define SCIF2_RFDC_MASK 0x001f
# define SCIF2_TXROOM_MAX 16
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
# define SCIF_RFDC_MASK 0x003f
#else
SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
#endif
#if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
- defined(CONFIG_R8A7794)
+ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
SCIF_FNS(DL, 0, 0, 0x30, 16)
SCIF_FNS(CKS, 0, 0, 0x34, 16)
#endif
#define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk)
#elif defined(__H8300H__) || defined(__H8300S__)
#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
#define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) /* Internal Clock */
#else /* Generic SH */
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
- * Based on serial_ns16550.c
- * (C) Copyright 2000
- * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
- *
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <dm/device.h>
+#include <dm/platform_data/serial-uniphier.h>
#include <serial.h>
#define UART_REG(x) \
#define UART_LSR_DR 0x01 /* Data ready */
#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
-DECLARE_GLOBAL_DATA_PTR;
+struct uniphier_serial_private_data {
+ struct uniphier_serial __iomem *membase;
+};
+
+#define uniphier_serial_port(dev) \
+ ((struct uniphier_serial_private_data *)dev_get_priv(dev))->membase
-static void uniphier_serial_init(struct uniphier_serial *port)
+static int uniphier_serial_setbrg(struct udevice *dev, int baudrate)
{
+ struct uniphier_serial_platform_data *plat = dev_get_platdata(dev);
+ struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
const unsigned int mode_x_div = 16;
unsigned int divisor;
writeb(UART_LCR_WLS_8, &port->lcr);
- divisor = DIV_ROUND_CLOSEST(CONFIG_SYS_UNIPHIER_UART_CLK,
- mode_x_div * gd->baudrate);
+ divisor = DIV_ROUND_CLOSEST(plat->uartclk, mode_x_div * baudrate);
writew(divisor, &port->dlr);
-}
-static void uniphier_serial_setbrg(struct uniphier_serial *port)
-{
- uniphier_serial_init(port);
+ return 0;
}
-static int uniphier_serial_tstc(struct uniphier_serial *port)
+static int uniphier_serial_getc(struct udevice *dev)
{
- return (readb(&port->lsr) & UART_LSR_DR) != 0;
-}
+ struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
-static int uniphier_serial_getc(struct uniphier_serial *port)
-{
- while (!uniphier_serial_tstc(port))
- ;
+ if (!(readb(&port->lsr) & UART_LSR_DR))
+ return -EAGAIN;
return readb(&port->rbr);
}
-static void uniphier_serial_putc(struct uniphier_serial *port, const char c)
+static int uniphier_serial_putc(struct udevice *dev, const char c)
{
- if (c == '\n')
- uniphier_serial_putc(port, '\r');
+ struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
- while (!(readb(&port->lsr) & UART_LSR_THRE))
- ;
+ if (!(readb(&port->lsr) & UART_LSR_THRE))
+ return -EAGAIN;
writeb(c, &port->thr);
+
+ return 0;
}
-static struct uniphier_serial *serial_ports[4] = {
-#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE0
- (struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE0,
-#else
- NULL,
-#endif
-#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE1
- (struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE1,
-#else
- NULL,
-#endif
-#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE2
- (struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE2,
-#else
- NULL,
-#endif
-#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE3
- (struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE3,
-#else
- NULL,
-#endif
-};
+static int uniphier_serial_pending(struct udevice *dev, bool input)
+{
+ struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
-/* Multi serial device functions */
-#define DECLARE_ESERIAL_FUNCTIONS(port) \
- static int eserial##port##_init(void) \
- { \
- uniphier_serial_init(serial_ports[port]); \
- return 0 ; \
- } \
- static void eserial##port##_setbrg(void) \
- { \
- uniphier_serial_setbrg(serial_ports[port]); \
- } \
- static int eserial##port##_getc(void) \
- { \
- return uniphier_serial_getc(serial_ports[port]); \
- } \
- static int eserial##port##_tstc(void) \
- { \
- return uniphier_serial_tstc(serial_ports[port]); \
- } \
- static void eserial##port##_putc(const char c) \
- { \
- uniphier_serial_putc(serial_ports[port], c); \
- }
-
-/* Serial device descriptor */
-#define INIT_ESERIAL_STRUCTURE(port, __name) { \
- .name = __name, \
- .start = eserial##port##_init, \
- .stop = NULL, \
- .setbrg = eserial##port##_setbrg, \
- .getc = eserial##port##_getc, \
- .tstc = eserial##port##_tstc, \
- .putc = eserial##port##_putc, \
- .puts = default_serial_puts, \
+ if (input)
+ return readb(&port->lsr) & UART_LSR_DR;
+ else
+ return !(readb(&port->lsr) & UART_LSR_THRE);
}
-#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE0)
-DECLARE_ESERIAL_FUNCTIONS(0);
-struct serial_device uniphier_serial0_device =
- INIT_ESERIAL_STRUCTURE(0, "ttyS0");
-#endif
-#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE1)
-DECLARE_ESERIAL_FUNCTIONS(1);
-struct serial_device uniphier_serial1_device =
- INIT_ESERIAL_STRUCTURE(1, "ttyS1");
-#endif
-#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE2)
-DECLARE_ESERIAL_FUNCTIONS(2);
-struct serial_device uniphier_serial2_device =
- INIT_ESERIAL_STRUCTURE(2, "ttyS2");
-#endif
-#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE3)
-DECLARE_ESERIAL_FUNCTIONS(3);
-struct serial_device uniphier_serial3_device =
- INIT_ESERIAL_STRUCTURE(3, "ttyS3");
-#endif
+static int uniphier_serial_probe(struct udevice *dev)
+{
+ struct uniphier_serial_private_data *priv = dev_get_priv(dev);
+ struct uniphier_serial_platform_data *plat = dev_get_platdata(dev);
+
+ priv->membase = map_sysmem(plat->base, sizeof(struct uniphier_serial));
+
+ if (!priv->membase)
+ return -ENOMEM;
+
+ return 0;
+}
-__weak struct serial_device *default_serial_console(void)
+static int uniphier_serial_remove(struct udevice *dev)
{
-#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE0)
- return &uniphier_serial0_device;
-#elif defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE1)
- return &uniphier_serial1_device;
-#elif defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE2)
- return &uniphier_serial2_device;
-#elif defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE3)
- return &uniphier_serial3_device;
-#else
-#error "No uniphier serial ports configured."
-#endif
+ unmap_sysmem(uniphier_serial_port(dev));
+
+ return 0;
}
-void uniphier_serial_initialize(void)
+#ifdef CONFIG_OF_CONTROL
+static const struct udevice_id uniphier_uart_of_match = {
+ { .compatible = "panasonic,uniphier-uart"},
+ {},
+};
+
+static int uniphier_serial_ofdata_to_platdata(struct udevice *dev)
{
-#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE0)
- serial_register(&uniphier_serial0_device);
-#endif
-#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE1)
- serial_register(&uniphier_serial1_device);
-#endif
-#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE2)
- serial_register(&uniphier_serial2_device);
-#endif
-#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE3)
- serial_register(&uniphier_serial3_device);
-#endif
+ /*
+ * TODO: Masahiro Yamada (yamada.m@jp.panasonic.com)
+ *
+ * Implement conversion code from DTB to platform data
+ * when supporting CONFIG_OF_CONTROL on UniPhir platform.
+ */
}
+#endif
+
+static const struct dm_serial_ops uniphier_serial_ops = {
+ .setbrg = uniphier_serial_setbrg,
+ .getc = uniphier_serial_getc,
+ .putc = uniphier_serial_putc,
+ .pending = uniphier_serial_pending,
+};
+
+U_BOOT_DRIVER(uniphier_serial) = {
+ .name = DRIVER_NAME,
+ .id = UCLASS_SERIAL,
+ .of_match = of_match_ptr(uniphier_uart_of_match),
+ .ofdata_to_platdata = of_match_ptr(uniphier_serial_ofdata_to_platdata),
+ .probe = uniphier_serial_probe,
+ .remove = uniphier_serial_remove,
+ .priv_auto_alloc_size = sizeof(struct uniphier_serial_private_data),
+ .platdata_auto_alloc_size =
+ sizeof(struct uniphier_serial_platform_data),
+ .ops = &uniphier_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--- /dev/null
+#
+# Makefile for the U-boot SOC specific device drivers.
+#
+
+obj-$(CONFIG_ARCH_KEYSTONE) += keystone/
--- /dev/null
+obj-$(CONFIG_TI_KEYSTONE_SERDES) += keystone_serdes.o
--- /dev/null
+/*
+ * TI serdes driver for keystone2.
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <errno.h>
+#include <common.h>
+#include <asm/ti-common/keystone_serdes.h>
+
+#define SERDES_CMU_REGS(x) (0x0000 + (0x0c00 * (x)))
+#define SERDES_LANE_REGS(x) (0x0200 + (0x200 * (x)))
+#define SERDES_COMLANE_REGS 0x0a00
+#define SERDES_WIZ_REGS 0x1fc0
+
+#define SERDES_CMU_REG_000(x) (SERDES_CMU_REGS(x) + 0x000)
+#define SERDES_CMU_REG_010(x) (SERDES_CMU_REGS(x) + 0x010)
+#define SERDES_COMLANE_REG_000 (SERDES_COMLANE_REGS + 0x000)
+#define SERDES_LANE_REG_000(x) (SERDES_LANE_REGS(x) + 0x000)
+#define SERDES_LANE_REG_028(x) (SERDES_LANE_REGS(x) + 0x028)
+#define SERDES_LANE_CTL_STATUS_REG(x) (SERDES_WIZ_REGS + 0x0020 + (4 * (x)))
+#define SERDES_PLL_CTL_REG (SERDES_WIZ_REGS + 0x0034)
+
+#define SERDES_RESET BIT(28)
+#define SERDES_LANE_RESET BIT(29)
+#define SERDES_LANE_LOOPBACK BIT(30)
+#define SERDES_LANE_EN_VAL(x, y, z) (x[y] | (z << 26) | (z << 10))
+
+#define SERDES_CMU_CFG_NUM 5
+#define SERDES_COMLANE_CFG_NUM 10
+#define SERDES_LANE_CFG_NUM 10
+
+struct serdes_cfg {
+ u32 ofs;
+ u32 val;
+ u32 mask;
+};
+
+struct cfg_entry {
+ enum ks2_serdes_clock clk;
+ enum ks2_serdes_rate rate;
+ struct serdes_cfg cmu[SERDES_CMU_CFG_NUM];
+ struct serdes_cfg comlane[SERDES_COMLANE_CFG_NUM];
+ struct serdes_cfg lane[SERDES_LANE_CFG_NUM];
+};
+
+/* SERDES PHY lane enable configuration value, indexed by PHY interface */
+static u32 serdes_cfg_lane_enable[] = {
+ 0xf000f0c0, /* SGMII */
+ 0xf0e9f038, /* PCSR */
+};
+
+/* SERDES PHY PLL enable configuration value, indexed by PHY interface */
+static u32 serdes_cfg_pll_enable[] = {
+ 0xe0000000, /* SGMII */
+ 0xee000000, /* PCSR */
+};
+
+/**
+ * Array to hold all possible serdes configurations.
+ * Combination for 5 clock settings and 6 baud rates.
+ */
+static struct cfg_entry cfgs[] = {
+ {
+ .clk = SERDES_CLOCK_156P25M,
+ .rate = SERDES_RATE_5G,
+ .cmu = {
+ {0x0000, 0x00800000, 0xffff0000},
+ {0x0014, 0x00008282, 0x0000ffff},
+ {0x0060, 0x00142438, 0x00ffffff},
+ {0x0064, 0x00c3c700, 0x00ffff00},
+ {0x0078, 0x0000c000, 0x0000ff00}
+ },
+ .comlane = {
+ {0x0a00, 0x00000800, 0x0000ff00},
+ {0x0a08, 0x38a20000, 0xffff0000},
+ {0x0a30, 0x008a8a00, 0x00ffff00},
+ {0x0a84, 0x00000600, 0x0000ff00},
+ {0x0a94, 0x10000000, 0xff000000},
+ {0x0aa0, 0x81000000, 0xff000000},
+ {0x0abc, 0xff000000, 0xff000000},
+ {0x0ac0, 0x0000008b, 0x000000ff},
+ {0x0b08, 0x583f0000, 0xffff0000},
+ {0x0b0c, 0x0000004e, 0x000000ff}
+ },
+ .lane = {
+ {0x0004, 0x38000080, 0xff0000ff},
+ {0x0008, 0x00000000, 0x000000ff},
+ {0x000c, 0x02000000, 0xff000000},
+ {0x0010, 0x1b000000, 0xff000000},
+ {0x0014, 0x00006fb8, 0x0000ffff},
+ {0x0018, 0x758000e4, 0xffff00ff},
+ {0x00ac, 0x00004400, 0x0000ff00},
+ {0x002c, 0x00100800, 0x00ffff00},
+ {0x0080, 0x00820082, 0x00ff00ff},
+ {0x0084, 0x1d0f0385, 0xffffffff}
+ },
+ },
+};
+
+static inline void ks2_serdes_rmw(u32 addr, u32 value, u32 mask)
+{
+ writel(((readl(addr) & (~mask)) | (value & mask)), addr);
+}
+
+static void ks2_serdes_cfg_setup(u32 base, struct serdes_cfg *cfg, u32 size)
+{
+ u32 i;
+
+ for (i = 0; i < size; i++)
+ ks2_serdes_rmw(base + cfg[i].ofs, cfg[i].val, cfg[i].mask);
+}
+
+static void ks2_serdes_lane_config(u32 base, struct serdes_cfg *cfg_lane,
+ u32 size, u32 lane)
+{
+ u32 i;
+
+ for (i = 0; i < size; i++)
+ ks2_serdes_rmw(base + cfg_lane[i].ofs + SERDES_LANE_REGS(lane),
+ cfg_lane[i].val, cfg_lane[i].mask);
+}
+
+static int ks2_serdes_init_cfg(u32 base, struct cfg_entry *cfg, u32 num_lanes)
+{
+ u32 i;
+
+ ks2_serdes_cfg_setup(base, cfg->cmu, SERDES_CMU_CFG_NUM);
+ ks2_serdes_cfg_setup(base, cfg->comlane, SERDES_COMLANE_CFG_NUM);
+
+ for (i = 0; i < num_lanes; i++)
+ ks2_serdes_lane_config(base, cfg->lane, SERDES_LANE_CFG_NUM, i);
+
+ return 0;
+}
+
+static void ks2_serdes_cmu_comlane_enable(u32 base, struct ks2_serdes *serdes)
+{
+ /* Bring SerDes out of Reset */
+ ks2_serdes_rmw(base + SERDES_CMU_REG_010(0), 0x0, SERDES_RESET);
+ if (serdes->intf == SERDES_PHY_PCSR)
+ ks2_serdes_rmw(base + SERDES_CMU_REG_010(1), 0x0, SERDES_RESET);
+
+ /* Enable CMU and COMLANE */
+ ks2_serdes_rmw(base + SERDES_CMU_REG_000(0), 0x03, 0x000000ff);
+ if (serdes->intf == SERDES_PHY_PCSR)
+ ks2_serdes_rmw(base + SERDES_CMU_REG_000(1), 0x03, 0x000000ff);
+
+ ks2_serdes_rmw(base + SERDES_COMLANE_REG_000, 0x5f, 0x000000ff);
+}
+
+static void ks2_serdes_pll_enable(u32 base, struct ks2_serdes *serdes)
+{
+ writel(serdes_cfg_pll_enable[serdes->intf],
+ base + SERDES_PLL_CTL_REG);
+}
+
+static void ks2_serdes_lane_reset(u32 base, u32 reset, u32 lane)
+{
+ if (reset)
+ ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane),
+ 0x1, SERDES_LANE_RESET);
+ else
+ ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane),
+ 0x0, SERDES_LANE_RESET);
+}
+
+static void ks2_serdes_lane_enable(u32 base,
+ struct ks2_serdes *serdes, u32 lane)
+{
+ /* Bring lane out of reset */
+ ks2_serdes_lane_reset(base, 0, lane);
+
+ writel(SERDES_LANE_EN_VAL(serdes_cfg_lane_enable, serdes->intf,
+ serdes->rate_mode),
+ base + SERDES_LANE_CTL_STATUS_REG(lane));
+
+ /* Set NES bit if Loopback Enabled */
+ if (serdes->loopback)
+ ks2_serdes_rmw(base + SERDES_LANE_REG_000(lane),
+ 0x1, SERDES_LANE_LOOPBACK);
+}
+
+int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes)
+{
+ int i;
+ int ret = 0;
+
+ for (i = 0; i < ARRAY_SIZE(cfgs); i++)
+ if (serdes->clk == cfgs[i].clk && serdes->rate == cfgs[i].rate)
+ break;
+
+ if (i >= ARRAY_SIZE(cfgs)) {
+ puts("Cannot find keystone SerDes configuration");
+ return -EINVAL;
+ }
+
+ ks2_serdes_init_cfg(base, &cfgs[i], num_lanes);
+
+ ks2_serdes_cmu_comlane_enable(base, serdes);
+ for (i = 0; i < num_lanes; i++)
+ ks2_serdes_lane_enable(base, serdes, i);
+
+ ks2_serdes_pll_enable(base, serdes);
+
+ return ret;
+}
+config DM_SPI
+ bool "Enable Driver Model for SPI drivers"
+ depends on DM
+ help
+ If you want to use driver model for SPI drivers, say Y.
+ To use legacy SPI drivers, say N.
#include <malloc.h>
#include <spi.h>
-#define ALTERA_SPI_RXDATA 0
-#define ALTERA_SPI_TXDATA 4
-#define ALTERA_SPI_STATUS 8
-#define ALTERA_SPI_CONTROL 12
-#define ALTERA_SPI_SLAVE_SEL 20
-
-#define ALTERA_SPI_STATUS_ROE_MSK (0x8)
-#define ALTERA_SPI_STATUS_TOE_MSK (0x10)
-#define ALTERA_SPI_STATUS_TMT_MSK (0x20)
-#define ALTERA_SPI_STATUS_TRDY_MSK (0x40)
-#define ALTERA_SPI_STATUS_RRDY_MSK (0x80)
-#define ALTERA_SPI_STATUS_E_MSK (0x100)
-
-#define ALTERA_SPI_CONTROL_IROE_MSK (0x8)
-#define ALTERA_SPI_CONTROL_ITOE_MSK (0x10)
-#define ALTERA_SPI_CONTROL_ITRDY_MSK (0x40)
-#define ALTERA_SPI_CONTROL_IRRDY_MSK (0x80)
-#define ALTERA_SPI_CONTROL_IE_MSK (0x100)
-#define ALTERA_SPI_CONTROL_SSO_MSK (0x400)
+#ifndef CONFIG_ALTERA_SPI_IDLE_VAL
+#define CONFIG_ALTERA_SPI_IDLE_VAL 0xff
+#endif
#ifndef CONFIG_SYS_ALTERA_SPI_LIST
#define CONFIG_SYS_ALTERA_SPI_LIST { CONFIG_SYS_SPI_BASE }
#endif
+struct altera_spi_regs {
+ u32 rxdata;
+ u32 txdata;
+ u32 status;
+ u32 control;
+ u32 _reserved;
+ u32 slave_sel;
+};
+
+#define ALTERA_SPI_STATUS_ROE_MSK (1 << 3)
+#define ALTERA_SPI_STATUS_TOE_MSK (1 << 4)
+#define ALTERA_SPI_STATUS_TMT_MSK (1 << 5)
+#define ALTERA_SPI_STATUS_TRDY_MSK (1 << 6)
+#define ALTERA_SPI_STATUS_RRDY_MSK (1 << 7)
+#define ALTERA_SPI_STATUS_E_MSK (1 << 8)
+
+#define ALTERA_SPI_CONTROL_IROE_MSK (1 << 3)
+#define ALTERA_SPI_CONTROL_ITOE_MSK (1 << 4)
+#define ALTERA_SPI_CONTROL_ITRDY_MSK (1 << 6)
+#define ALTERA_SPI_CONTROL_IRRDY_MSK (1 << 7)
+#define ALTERA_SPI_CONTROL_IE_MSK (1 << 8)
+#define ALTERA_SPI_CONTROL_SSO_MSK (1 << 10)
+
static ulong altera_spi_base_list[] = CONFIG_SYS_ALTERA_SPI_LIST;
struct altera_spi_slave {
- struct spi_slave slave;
- ulong base;
+ struct spi_slave slave;
+ struct altera_spi_regs *regs;
};
#define to_altera_spi_slave(s) container_of(s, struct altera_spi_slave, slave)
-__attribute__((weak))
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+__weak int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus < ARRAY_SIZE(altera_spi_base_list) && cs < 32;
}
-__attribute__((weak))
-void spi_cs_activate(struct spi_slave *slave)
+__weak void spi_cs_activate(struct spi_slave *slave)
{
struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
- writel(1 << slave->cs, altspi->base + ALTERA_SPI_SLAVE_SEL);
- writel(ALTERA_SPI_CONTROL_SSO_MSK, altspi->base + ALTERA_SPI_CONTROL);
+ writel(1 << slave->cs, &altspi->regs->slave_sel);
+ writel(ALTERA_SPI_CONTROL_SSO_MSK, &altspi->regs->control);
}
-__attribute__((weak))
-void spi_cs_deactivate(struct spi_slave *slave)
+__weak void spi_cs_deactivate(struct spi_slave *slave)
{
struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
- writel(0, altspi->base + ALTERA_SPI_CONTROL);
- writel(0, altspi->base + ALTERA_SPI_SLAVE_SEL);
+ writel(0, &altspi->regs->control);
+ writel(0, &altspi->regs->slave_sel);
}
void spi_init(void)
if (!altspi)
return NULL;
- altspi->base = altera_spi_base_list[bus];
- debug("%s: bus:%i cs:%i base:%lx\n", __func__,
- bus, cs, altspi->base);
+ altspi->regs = (struct altera_spi_regs *)altera_spi_base_list[bus];
+ debug("%s: bus:%i cs:%i base:%p\n", __func__, bus, cs, altspi->regs);
return &altspi->slave;
}
struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
- writel(0, altspi->base + ALTERA_SPI_CONTROL);
- writel(0, altspi->base + ALTERA_SPI_SLAVE_SEL);
+ writel(0, &altspi->regs->control);
+ writel(0, &altspi->regs->slave_sel);
return 0;
}
struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
- writel(0, altspi->base + ALTERA_SPI_SLAVE_SEL);
+ writel(0, &altspi->regs->slave_sel);
}
-#ifndef CONFIG_ALTERA_SPI_IDLE_VAL
-# define CONFIG_ALTERA_SPI_IDLE_VAL 0xff
-#endif
-
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
/* assume spi core configured to do 8 bit transfers */
- uint bytes = bitlen / 8;
- const uchar *txp = dout;
- uchar *rxp = din;
+ unsigned int bytes = bitlen / 8;
+ const unsigned char *txp = dout;
+ unsigned char *rxp = din;
+ uint32_t reg, data, start;
debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
- slave->bus, slave->cs, bitlen, bytes, flags);
+ slave->bus, slave->cs, bitlen, bytes, flags);
+
if (bitlen == 0)
goto done;
}
/* empty read buffer */
- if (readl(altspi->base + ALTERA_SPI_STATUS) &
- ALTERA_SPI_STATUS_RRDY_MSK)
- readl(altspi->base + ALTERA_SPI_RXDATA);
+ if (readl(&altspi->regs->status) & ALTERA_SPI_STATUS_RRDY_MSK)
+ readl(&altspi->regs->rxdata);
+
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(slave);
while (bytes--) {
- uchar d = txp ? *txp++ : CONFIG_ALTERA_SPI_IDLE_VAL;
- debug("%s: tx:%x ", __func__, d);
- writel(d, altspi->base + ALTERA_SPI_TXDATA);
- while (!(readl(altspi->base + ALTERA_SPI_STATUS) &
- ALTERA_SPI_STATUS_RRDY_MSK))
- ;
- d = readl(altspi->base + ALTERA_SPI_RXDATA);
+ if (txp)
+ data = *txp++;
+ else
+ data = CONFIG_ALTERA_SPI_IDLE_VAL;
+
+ debug("%s: tx:%x ", __func__, data);
+ writel(data, &altspi->regs->txdata);
+
+ start = get_timer(0);
+ while (1) {
+ reg = readl(&altspi->regs->status);
+ if (reg & ALTERA_SPI_STATUS_RRDY_MSK)
+ break;
+ if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
+ printf("%s: Transmission timed out!\n", __func__);
+ goto done;
+ }
+ }
+
+ data = readl(&altspi->regs->rxdata);
if (rxp)
- *rxp++ = d;
- debug("rx:%x\n", d);
+ *rxp++ = data & 0xff;
+
+ debug("rx:%x\n", data);
}
- done:
+
+done:
if (flags & SPI_XFER_END)
spi_cs_deactivate(slave);
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
+#include <asm/imx-common/spi.h>
#ifdef CONFIG_MX27
/* i.MX27 has a completely wrong register layout and register definitions in the
#endif
int gpio;
int ss_pol;
+ unsigned int max_hz;
+ unsigned int mode;
};
static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
}
#ifdef MXC_CSPI
-static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
+static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
{
unsigned int ctrl_reg;
u32 clk_src;
u32 div;
+ unsigned int max_hz = mxcs->max_hz;
+ unsigned int mode = mxcs->mode;
clk_src = mxc_get_clock(MXC_CSPI_CLK);
#endif
#ifdef MXC_ECSPI
-static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
+static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
{
u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
s32 reg_ctrl, reg_config;
u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
u32 pre_div = 0, post_div = 0;
struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
-
- if (max_hz == 0) {
- printf("Error: desired clock is 0\n");
- return -1;
- }
+ unsigned int max_hz = mxcs->max_hz;
+ unsigned int mode = mxcs->mode;
/*
* Reset SPI and set all CSs to master mode, if toggling
reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
MXC_CSPICTRL_POSTDIV(post_div);
- /* We need to disable SPI before changing registers */
- reg_ctrl &= ~MXC_CSPICTRL_EN;
-
if (mode & SPI_CS_HIGH)
ss_pol = 1;
if (bus >= ARRAY_SIZE(spi_bases))
return NULL;
+ if (max_hz == 0) {
+ printf("Error: desired clock is 0\n");
+ return NULL;
+ }
+
mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
if (!mxcs) {
puts("mxc_spi: SPI Slave not allocated !\n");
}
mxcs->base = spi_bases[bus];
+ mxcs->max_hz = max_hz;
+ mxcs->mode = mode;
- ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
- if (ret) {
- printf("mxc_spi: cannot setup SPI controller\n");
- free(mxcs);
- return NULL;
- }
return &mxcs->slave;
}
int spi_claim_bus(struct spi_slave *slave)
{
+ int ret;
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
reg_write(®s->rxdata, 1);
udelay(1);
- reg_write(®s->ctrl, mxcs->ctrl_reg);
+ ret = spi_cfg_mxc(mxcs, slave->cs);
+ if (ret) {
+ printf("mxc_spi: cannot setup SPI controller\n");
+ return ret;
+ }
reg_write(®s->period, MXC_CSPIPERIOD_32KHZ);
reg_write(®s->intr, 0);
{ 0x2001, 0x3c05, FLAG_TYPE_AX88772 },
/* ASIX 88772B */
{ 0x0b95, 0x772b, FLAG_TYPE_AX88772B | FLAG_EEPROM_MAC },
+ { 0x0b95, 0x7e2b, FLAG_TYPE_AX88772B },
{ 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */
};
# xhci
obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
+obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
+
+# designware
+obj-$(CONFIG_USB_DWC2) += dwc2.o
--- /dev/null
+/*
+ * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <usb.h>
+#include <malloc.h>
+#include <usbroothubdes.h>
+#include <asm/io.h>
+
+#include "dwc2.h"
+
+/* Use only HC channel 0. */
+#define DWC2_HC_CHANNEL 0
+
+#define DWC2_STATUS_BUF_SIZE 64
+#define DWC2_DATA_BUF_SIZE (64 * 1024)
+
+/* We need doubleword-aligned buffers for DMA transfers */
+DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer, DWC2_DATA_BUF_SIZE, 8);
+DEFINE_ALIGN_BUFFER(uint8_t, status_buffer, DWC2_STATUS_BUF_SIZE, 8);
+
+#define MAX_DEVICE 16
+#define MAX_ENDPOINT 16
+static int bulk_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
+static int control_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
+
+static int root_hub_devnum;
+
+static struct dwc2_core_regs *regs =
+ (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
+
+/*
+ * DWC2 IP interface
+ */
+static int wait_for_bit(void *reg, const uint32_t mask, bool set)
+{
+ unsigned int timeout = 1000000;
+ uint32_t val;
+
+ while (--timeout) {
+ val = readl(reg);
+ if (!set)
+ val = ~val;
+
+ if ((val & mask) == mask)
+ return 0;
+
+ udelay(1);
+ }
+
+ debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
+ __func__, reg, mask, set);
+
+ return -ETIMEDOUT;
+}
+
+/*
+ * Initializes the FSLSPClkSel field of the HCFG register
+ * depending on the PHY type.
+ */
+static void init_fslspclksel(struct dwc2_core_regs *regs)
+{
+ uint32_t phyclk;
+
+#if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
+ phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
+#else
+ /* High speed PHY running at full speed or high speed */
+ phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
+#endif
+
+#ifdef CONFIG_DWC2_ULPI_FS_LS
+ uint32_t hwcfg2 = readl(®s->ghwcfg2);
+ uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
+ DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
+ uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
+ DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
+
+ if (hval == 2 && fval == 1)
+ phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
+#endif
+
+ clrsetbits_le32(®s->host_regs.hcfg,
+ DWC2_HCFG_FSLSPCLKSEL_MASK,
+ phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
+}
+
+/*
+ * Flush a Tx FIFO.
+ *
+ * @param regs Programming view of DWC_otg controller.
+ * @param num Tx FIFO to flush.
+ */
+static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
+{
+ int ret;
+
+ writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
+ ®s->grstctl);
+ ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_TXFFLSH, 0);
+ if (ret)
+ printf("%s: Timeout!\n", __func__);
+
+ /* Wait for 3 PHY Clocks */
+ udelay(1);
+}
+
+/*
+ * Flush Rx FIFO.
+ *
+ * @param regs Programming view of DWC_otg controller.
+ */
+static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
+{
+ int ret;
+
+ writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl);
+ ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_RXFFLSH, 0);
+ if (ret)
+ printf("%s: Timeout!\n", __func__);
+
+ /* Wait for 3 PHY Clocks */
+ udelay(1);
+}
+
+/*
+ * Do core a soft reset of the core. Be careful with this because it
+ * resets all the internal state machines of the core.
+ */
+static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
+{
+ int ret;
+
+ /* Wait for AHB master IDLE state. */
+ ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_AHBIDLE, 1);
+ if (ret)
+ printf("%s: Timeout!\n", __func__);
+
+ /* Core Soft Reset */
+ writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl);
+ ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_CSFTRST, 0);
+ if (ret)
+ printf("%s: Timeout!\n", __func__);
+
+ /*
+ * Wait for core to come out of reset.
+ * NOTE: This long sleep is _very_ important, otherwise the core will
+ * not stay in host mode after a connector ID change!
+ */
+ mdelay(100);
+}
+
+/*
+ * This function initializes the DWC_otg controller registers for
+ * host mode.
+ *
+ * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
+ * request queues. Host channels are reset to ensure that they are ready for
+ * performing transfers.
+ *
+ * @param regs Programming view of DWC_otg controller
+ *
+ */
+static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
+{
+ uint32_t nptxfifosize = 0;
+ uint32_t ptxfifosize = 0;
+ uint32_t hprt0 = 0;
+ int i, ret, num_channels;
+
+ /* Restart the Phy Clock */
+ writel(0, ®s->pcgcctl);
+
+ /* Initialize Host Configuration Register */
+ init_fslspclksel(regs);
+#ifdef CONFIG_DWC2_DFLT_SPEED_FULL
+ setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
+#endif
+
+ /* Configure data FIFO sizes */
+#ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
+ if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
+ /* Rx FIFO */
+ writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz);
+
+ /* Non-periodic Tx FIFO */
+ nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
+ DWC2_FIFOSIZE_DEPTH_OFFSET;
+ nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
+ DWC2_FIFOSIZE_STARTADDR_OFFSET;
+ writel(nptxfifosize, ®s->gnptxfsiz);
+
+ /* Periodic Tx FIFO */
+ ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
+ DWC2_FIFOSIZE_DEPTH_OFFSET;
+ ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
+ CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
+ DWC2_FIFOSIZE_STARTADDR_OFFSET;
+ writel(ptxfifosize, ®s->hptxfsiz);
+ }
+#endif
+
+ /* Clear Host Set HNP Enable in the OTG Control Register */
+ clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
+
+ /* Make sure the FIFOs are flushed. */
+ dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */
+ dwc_otg_flush_rx_fifo(regs);
+
+ /* Flush out any leftover queued requests. */
+ num_channels = readl(®s->ghwcfg2);
+ num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
+ num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
+ num_channels += 1;
+
+ for (i = 0; i < num_channels; i++)
+ clrsetbits_le32(®s->hc_regs[i].hcchar,
+ DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
+ DWC2_HCCHAR_CHDIS);
+
+ /* Halt all channels to put them into a known state. */
+ for (i = 0; i < num_channels; i++) {
+ clrsetbits_le32(®s->hc_regs[i].hcchar,
+ DWC2_HCCHAR_EPDIR,
+ DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
+ ret = wait_for_bit(®s->hc_regs[i].hcchar,
+ DWC2_HCCHAR_CHEN, 0);
+ if (ret)
+ printf("%s: Timeout!\n", __func__);
+ }
+
+ /* Turn on the vbus power. */
+ if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
+ hprt0 = readl(®s->hprt0);
+ hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
+ hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
+ if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
+ hprt0 |= DWC2_HPRT0_PRTPWR;
+ writel(hprt0, ®s->hprt0);
+ }
+ }
+}
+
+/*
+ * This function initializes the DWC_otg controller registers and
+ * prepares the core for device mode or host mode operation.
+ *
+ * @param regs Programming view of the DWC_otg controller
+ */
+static void dwc_otg_core_init(struct dwc2_core_regs *regs)
+{
+ uint32_t ahbcfg = 0;
+ uint32_t usbcfg = 0;
+ uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
+
+ /* Common Initialization */
+ usbcfg = readl(®s->gusbcfg);
+
+ /* Program the ULPI External VBUS bit if needed */
+#ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
+ usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
+#else
+ usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
+#endif
+
+ /* Set external TS Dline pulsing */
+#ifdef CONFIG_DWC2_TS_DLINE
+ usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
+#else
+ usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
+#endif
+ writel(usbcfg, ®s->gusbcfg);
+
+ /* Reset the Controller */
+ dwc_otg_core_reset(regs);
+
+ /*
+ * This programming sequence needs to happen in FS mode before
+ * any other programming occurs
+ */
+#if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
+ (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
+ /* If FS mode with FS PHY */
+ setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL);
+
+ /* Reset after a PHY select */
+ dwc_otg_core_reset(regs);
+
+ /*
+ * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
+ * Also do this on HNP Dev/Host mode switches (done in dev_init
+ * and host_init).
+ */
+ if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
+ init_fslspclksel(regs);
+
+#ifdef CONFIG_DWC2_I2C_ENABLE
+ /* Program GUSBCFG.OtgUtmifsSel to I2C */
+ setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
+
+ /* Program GI2CCTL.I2CEn */
+ clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN |
+ DWC2_GI2CCTL_I2CDEVADDR_MASK,
+ 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
+ setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN);
+#endif
+
+#else
+ /* High speed PHY. */
+
+ /*
+ * HS PHY parameters. These parameters are preserved during
+ * soft reset so only program the first time. Do a soft reset
+ * immediately after setting phyif.
+ */
+ usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
+ usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
+
+ if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
+#ifdef CONFIG_DWC2_PHY_ULPI_DDR
+ usbcfg |= DWC2_GUSBCFG_DDRSEL;
+#else
+ usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
+#endif
+ } else { /* UTMI+ interface */
+#if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16)
+ usbcfg |= DWC2_GUSBCFG_PHYIF;
+#endif
+ }
+
+ writel(usbcfg, ®s->gusbcfg);
+
+ /* Reset after setting the PHY parameters */
+ dwc_otg_core_reset(regs);
+#endif
+
+ usbcfg = readl(®s->gusbcfg);
+ usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
+#ifdef CONFIG_DWC2_ULPI_FS_LS
+ uint32_t hwcfg2 = readl(®s->ghwcfg2);
+ uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
+ DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
+ uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
+ DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
+ if (hval == 2 && fval == 1) {
+ usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
+ usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
+ }
+#endif
+ writel(usbcfg, ®s->gusbcfg);
+
+ /* Program the GAHBCFG Register. */
+ switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
+ case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
+ break;
+ case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
+ while (brst_sz > 1) {
+ ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
+ ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
+ brst_sz >>= 1;
+ }
+
+#ifdef CONFIG_DWC2_DMA_ENABLE
+ ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
+#endif
+ break;
+
+ case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
+ ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
+#ifdef CONFIG_DWC2_DMA_ENABLE
+ ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
+#endif
+ break;
+ }
+
+ writel(ahbcfg, ®s->gahbcfg);
+
+ /* Program the GUSBCFG register for HNP/SRP. */
+ setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
+
+#ifdef CONFIG_DWC2_IC_USB_CAP
+ setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
+#endif
+}
+
+/*
+ * Prepares a host channel for transferring packets to/from a specific
+ * endpoint. The HCCHARn register is set up with the characteristics specified
+ * in _hc. Host channel interrupts that may need to be serviced while this
+ * transfer is in progress are enabled.
+ *
+ * @param regs Programming view of DWC_otg controller
+ * @param hc Information needed to initialize the host channel
+ */
+static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
+ uint8_t dev_addr, uint8_t ep_num, uint8_t ep_is_in,
+ uint8_t ep_type, uint16_t max_packet)
+{
+ struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num];
+ const uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
+ (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
+ (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
+ (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
+ (max_packet << DWC2_HCCHAR_MPS_OFFSET);
+
+ /* Clear old interrupt conditions for this host channel. */
+ writel(0x3fff, &hc_regs->hcint);
+
+ /*
+ * Program the HCCHARn register with the endpoint characteristics
+ * for the current transfer.
+ */
+ writel(hcchar, &hc_regs->hcchar);
+
+ /* Program the HCSPLIT register for SPLITs */
+ writel(0, &hc_regs->hcsplt);
+}
+
+/*
+ * DWC2 to USB API interface
+ */
+/* Direction: In ; Request: Status */
+static int dwc_otg_submit_rh_msg_in_status(struct usb_device *dev, void *buffer,
+ int txlen, struct devrequest *cmd)
+{
+ uint32_t hprt0 = 0;
+ uint32_t port_status = 0;
+ uint32_t port_change = 0;
+ int len = 0;
+ int stat = 0;
+
+ switch (cmd->requesttype & ~USB_DIR_IN) {
+ case 0:
+ *(uint16_t *)buffer = cpu_to_le16(1);
+ len = 2;
+ break;
+ case USB_RECIP_INTERFACE:
+ case USB_RECIP_ENDPOINT:
+ *(uint16_t *)buffer = cpu_to_le16(0);
+ len = 2;
+ break;
+ case USB_TYPE_CLASS:
+ *(uint32_t *)buffer = cpu_to_le32(0);
+ len = 4;
+ break;
+ case USB_RECIP_OTHER | USB_TYPE_CLASS:
+ hprt0 = readl(®s->hprt0);
+ if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
+ port_status |= USB_PORT_STAT_CONNECTION;
+ if (hprt0 & DWC2_HPRT0_PRTENA)
+ port_status |= USB_PORT_STAT_ENABLE;
+ if (hprt0 & DWC2_HPRT0_PRTSUSP)
+ port_status |= USB_PORT_STAT_SUSPEND;
+ if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
+ port_status |= USB_PORT_STAT_OVERCURRENT;
+ if (hprt0 & DWC2_HPRT0_PRTRST)
+ port_status |= USB_PORT_STAT_RESET;
+ if (hprt0 & DWC2_HPRT0_PRTPWR)
+ port_status |= USB_PORT_STAT_POWER;
+
+ port_status |= USB_PORT_STAT_HIGH_SPEED;
+
+ if (hprt0 & DWC2_HPRT0_PRTENCHNG)
+ port_change |= USB_PORT_STAT_C_ENABLE;
+ if (hprt0 & DWC2_HPRT0_PRTCONNDET)
+ port_change |= USB_PORT_STAT_C_CONNECTION;
+ if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
+ port_change |= USB_PORT_STAT_C_OVERCURRENT;
+
+ *(uint32_t *)buffer = cpu_to_le32(port_status |
+ (port_change << 16));
+ len = 4;
+ break;
+ default:
+ puts("unsupported root hub command\n");
+ stat = USB_ST_STALLED;
+ }
+
+ dev->act_len = min(len, txlen);
+ dev->status = stat;
+
+ return stat;
+}
+
+/* Direction: In ; Request: Descriptor */
+static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
+ void *buffer, int txlen,
+ struct devrequest *cmd)
+{
+ unsigned char data[32];
+ uint32_t dsc;
+ int len = 0;
+ int stat = 0;
+ uint16_t wValue = cpu_to_le16(cmd->value);
+ uint16_t wLength = cpu_to_le16(cmd->length);
+
+ switch (cmd->requesttype & ~USB_DIR_IN) {
+ case 0:
+ switch (wValue & 0xff00) {
+ case 0x0100: /* device descriptor */
+ len = min3(txlen, sizeof(root_hub_dev_des), wLength);
+ memcpy(buffer, root_hub_dev_des, len);
+ break;
+ case 0x0200: /* configuration descriptor */
+ len = min3(txlen, sizeof(root_hub_config_des), wLength);
+ memcpy(buffer, root_hub_config_des, len);
+ break;
+ case 0x0300: /* string descriptors */
+ switch (wValue & 0xff) {
+ case 0x00:
+ len = min3(txlen, sizeof(root_hub_str_index0),
+ wLength);
+ memcpy(buffer, root_hub_str_index0, len);
+ break;
+ case 0x01:
+ len = min3(txlen, sizeof(root_hub_str_index1),
+ wLength);
+ memcpy(buffer, root_hub_str_index1, len);
+ break;
+ }
+ break;
+ default:
+ stat = USB_ST_STALLED;
+ }
+ break;
+
+ case USB_TYPE_CLASS:
+ /* Root port config, set 1 port and nothing else. */
+ dsc = 0x00000001;
+
+ data[0] = 9; /* min length; */
+ data[1] = 0x29;
+ data[2] = dsc & RH_A_NDP;
+ data[3] = 0;
+ if (dsc & RH_A_PSM)
+ data[3] |= 0x1;
+ if (dsc & RH_A_NOCP)
+ data[3] |= 0x10;
+ else if (dsc & RH_A_OCPM)
+ data[3] |= 0x8;
+
+ /* corresponds to data[4-7] */
+ data[5] = (dsc & RH_A_POTPGT) >> 24;
+ data[7] = dsc & RH_B_DR;
+ if (data[2] < 7) {
+ data[8] = 0xff;
+ } else {
+ data[0] += 2;
+ data[8] = (dsc & RH_B_DR) >> 8;
+ data[9] = 0xff;
+ data[10] = data[9];
+ }
+
+ len = min3(txlen, data[0], wLength);
+ memcpy(buffer, data, len);
+ break;
+ default:
+ puts("unsupported root hub command\n");
+ stat = USB_ST_STALLED;
+ }
+
+ dev->act_len = min(len, txlen);
+ dev->status = stat;
+
+ return stat;
+}
+
+/* Direction: In ; Request: Configuration */
+static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
+ void *buffer, int txlen,
+ struct devrequest *cmd)
+{
+ int len = 0;
+ int stat = 0;
+
+ switch (cmd->requesttype & ~USB_DIR_IN) {
+ case 0:
+ *(uint8_t *)buffer = 0x01;
+ len = 1;
+ break;
+ default:
+ puts("unsupported root hub command\n");
+ stat = USB_ST_STALLED;
+ }
+
+ dev->act_len = min(len, txlen);
+ dev->status = stat;
+
+ return stat;
+}
+
+/* Direction: In */
+static int dwc_otg_submit_rh_msg_in(struct usb_device *dev,
+ void *buffer, int txlen,
+ struct devrequest *cmd)
+{
+ switch (cmd->request) {
+ case USB_REQ_GET_STATUS:
+ return dwc_otg_submit_rh_msg_in_status(dev, buffer,
+ txlen, cmd);
+ case USB_REQ_GET_DESCRIPTOR:
+ return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
+ txlen, cmd);
+ case USB_REQ_GET_CONFIGURATION:
+ return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
+ txlen, cmd);
+ default:
+ puts("unsupported root hub command\n");
+ return USB_ST_STALLED;
+ }
+}
+
+/* Direction: Out */
+static int dwc_otg_submit_rh_msg_out(struct usb_device *dev,
+ void *buffer, int txlen,
+ struct devrequest *cmd)
+{
+ int len = 0;
+ int stat = 0;
+ uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
+ uint16_t wValue = cpu_to_le16(cmd->value);
+
+ switch (bmrtype_breq & ~USB_DIR_IN) {
+ case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
+ case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
+ break;
+
+ case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
+ switch (wValue) {
+ case USB_PORT_FEAT_C_CONNECTION:
+ setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET);
+ break;
+ }
+ break;
+
+ case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
+ switch (wValue) {
+ case USB_PORT_FEAT_SUSPEND:
+ break;
+
+ case USB_PORT_FEAT_RESET:
+ clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
+ DWC2_HPRT0_PRTCONNDET |
+ DWC2_HPRT0_PRTENCHNG |
+ DWC2_HPRT0_PRTOVRCURRCHNG,
+ DWC2_HPRT0_PRTRST);
+ mdelay(50);
+ clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST);
+ break;
+
+ case USB_PORT_FEAT_POWER:
+ clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
+ DWC2_HPRT0_PRTCONNDET |
+ DWC2_HPRT0_PRTENCHNG |
+ DWC2_HPRT0_PRTOVRCURRCHNG,
+ DWC2_HPRT0_PRTRST);
+ break;
+
+ case USB_PORT_FEAT_ENABLE:
+ break;
+ }
+ break;
+ case (USB_REQ_SET_ADDRESS << 8):
+ root_hub_devnum = wValue;
+ break;
+ case (USB_REQ_SET_CONFIGURATION << 8):
+ break;
+ default:
+ puts("unsupported root hub command\n");
+ stat = USB_ST_STALLED;
+ }
+
+ len = min(len, txlen);
+
+ dev->act_len = len;
+ dev->status = stat;
+
+ return stat;
+}
+
+static int dwc_otg_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int txlen,
+ struct devrequest *cmd)
+{
+ int stat = 0;
+
+ if (usb_pipeint(pipe)) {
+ puts("Root-Hub submit IRQ: NOT implemented\n");
+ return 0;
+ }
+
+ if (cmd->requesttype & USB_DIR_IN)
+ stat = dwc_otg_submit_rh_msg_in(dev, buffer, txlen, cmd);
+ else
+ stat = dwc_otg_submit_rh_msg_out(dev, buffer, txlen, cmd);
+
+ mdelay(1);
+
+ return stat;
+}
+
+/* U-Boot USB transmission interface */
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int len)
+{
+ int devnum = usb_pipedevice(pipe);
+ int ep = usb_pipeendpoint(pipe);
+ int max = usb_maxpacket(dev, pipe);
+ int done = 0;
+ uint32_t hctsiz, sub, tmp;
+ struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
+ uint32_t hcint;
+ uint32_t xfer_len;
+ uint32_t num_packets;
+ int stop_transfer = 0;
+ unsigned int timeout = 1000000;
+
+ if (devnum == root_hub_devnum) {
+ dev->status = 0;
+ return -EINVAL;
+ }
+
+ if (len > DWC2_DATA_BUF_SIZE) {
+ printf("%s: %d is more then available buffer size (%d)\n",
+ __func__, len, DWC2_DATA_BUF_SIZE);
+ dev->status = 0;
+ dev->act_len = 0;
+ return -EINVAL;
+ }
+
+ while ((done < len) && !stop_transfer) {
+ /* Initialize channel */
+ dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep,
+ usb_pipein(pipe), DWC2_HCCHAR_EPTYPE_BULK, max);
+
+ xfer_len = len - done;
+ /* Make sure that xfer_len is a multiple of max packet size. */
+ if (xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
+ xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE - max + 1;
+
+ if (xfer_len > 0) {
+ num_packets = (xfer_len + max - 1) / max;
+ if (num_packets > CONFIG_DWC2_MAX_PACKET_COUNT) {
+ num_packets = CONFIG_DWC2_MAX_PACKET_COUNT;
+ xfer_len = num_packets * max;
+ }
+ } else {
+ num_packets = 1;
+ }
+
+ if (usb_pipein(pipe))
+ xfer_len = num_packets * max;
+
+ writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
+ (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
+ (bulk_data_toggle[devnum][ep] <<
+ DWC2_HCTSIZ_PID_OFFSET),
+ &hc_regs->hctsiz);
+
+ memcpy(aligned_buffer, (char *)buffer + done, len - done);
+ writel((uint32_t)aligned_buffer, &hc_regs->hcdma);
+
+ /* Set host channel enable after all other setup is complete. */
+ clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
+ DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
+ (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
+ DWC2_HCCHAR_CHEN);
+
+ while (1) {
+ hcint = readl(&hc_regs->hcint);
+
+ if (!(hcint & DWC2_HCINT_CHHLTD))
+ continue;
+
+ if (hcint & DWC2_HCINT_XFERCOMP) {
+ hctsiz = readl(&hc_regs->hctsiz);
+ done += xfer_len;
+
+ sub = hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK;
+ sub >>= DWC2_HCTSIZ_XFERSIZE_OFFSET;
+
+ if (usb_pipein(pipe)) {
+ done -= sub;
+ if (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK)
+ stop_transfer = 1;
+ }
+
+ tmp = hctsiz & DWC2_HCTSIZ_PID_MASK;
+ tmp >>= DWC2_HCTSIZ_PID_OFFSET;
+ if (tmp == DWC2_HC_PID_DATA1) {
+ bulk_data_toggle[devnum][ep] =
+ DWC2_HC_PID_DATA1;
+ } else {
+ bulk_data_toggle[devnum][ep] =
+ DWC2_HC_PID_DATA0;
+ }
+ break;
+ }
+
+ if (hcint & DWC2_HCINT_STALL) {
+ puts("DWC OTG: Channel halted\n");
+ bulk_data_toggle[devnum][ep] =
+ DWC2_HC_PID_DATA0;
+
+ stop_transfer = 1;
+ break;
+ }
+
+ if (!--timeout) {
+ printf("%s: Timeout!\n", __func__);
+ break;
+ }
+ }
+ }
+
+ if (done && usb_pipein(pipe))
+ memcpy(buffer, aligned_buffer, done);
+
+ writel(0, &hc_regs->hcintmsk);
+ writel(0xFFFFFFFF, &hc_regs->hcint);
+
+ dev->status = 0;
+ dev->act_len = done;
+
+ return 0;
+}
+
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int len, struct devrequest *setup)
+{
+ struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
+ int done = 0;
+ int devnum = usb_pipedevice(pipe);
+ int ep = usb_pipeendpoint(pipe);
+ int max = usb_maxpacket(dev, pipe);
+ uint32_t hctsiz = 0, sub, tmp, ret;
+ uint32_t hcint;
+ const uint32_t hcint_comp_hlt_ack = DWC2_HCINT_XFERCOMP |
+ DWC2_HCINT_CHHLTD | DWC2_HCINT_ACK;
+ unsigned int timeout = 1000000;
+
+ /* For CONTROL endpoint pid should start with DATA1 */
+ int status_direction;
+
+ if (devnum == root_hub_devnum) {
+ dev->status = 0;
+ dev->speed = USB_SPEED_HIGH;
+ return dwc_otg_submit_rh_msg(dev, pipe, buffer, len, setup);
+ }
+
+ if (len > DWC2_DATA_BUF_SIZE) {
+ printf("%s: %d is more then available buffer size(%d)\n",
+ __func__, len, DWC2_DATA_BUF_SIZE);
+ dev->status = 0;
+ dev->act_len = 0;
+ return -EINVAL;
+ }
+
+ /* Initialize channel, OUT for setup buffer */
+ dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep, 0,
+ DWC2_HCCHAR_EPTYPE_CONTROL, max);
+
+ /* SETUP stage */
+ writel((8 << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
+ (1 << DWC2_HCTSIZ_PKTCNT_OFFSET) |
+ (DWC2_HC_PID_SETUP << DWC2_HCTSIZ_PID_OFFSET),
+ &hc_regs->hctsiz);
+
+ writel((uint32_t)setup, &hc_regs->hcdma);
+
+ /* Set host channel enable after all other setup is complete. */
+ clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
+ DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
+ (1 << DWC2_HCCHAR_MULTICNT_OFFSET) | DWC2_HCCHAR_CHEN);
+
+ ret = wait_for_bit(&hc_regs->hcint, DWC2_HCINT_CHHLTD, 1);
+ if (ret)
+ printf("%s: Timeout!\n", __func__);
+
+ hcint = readl(&hc_regs->hcint);
+
+ if (!(hcint & DWC2_HCINT_CHHLTD) || !(hcint & DWC2_HCINT_XFERCOMP)) {
+ printf("%s: Error (HCINT=%08x)\n", __func__, hcint);
+ dev->status = 0;
+ dev->act_len = 0;
+ return -EINVAL;
+ }
+
+ /* Clear interrupts */
+ writel(0, &hc_regs->hcintmsk);
+ writel(0xFFFFFFFF, &hc_regs->hcint);
+
+ if (buffer) {
+ /* DATA stage */
+ dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep,
+ usb_pipein(pipe),
+ DWC2_HCCHAR_EPTYPE_CONTROL, max);
+
+ /* TODO: check if len < 64 */
+ control_data_toggle[devnum][ep] = DWC2_HC_PID_DATA1;
+ writel((len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
+ (1 << DWC2_HCTSIZ_PKTCNT_OFFSET) |
+ (control_data_toggle[devnum][ep] <<
+ DWC2_HCTSIZ_PID_OFFSET),
+ &hc_regs->hctsiz);
+
+ writel((uint32_t)buffer, &hc_regs->hcdma);
+
+ /* Set host channel enable after all other setup is complete */
+ clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
+ DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
+ (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
+ DWC2_HCCHAR_CHEN);
+
+ while (1) {
+ hcint = readl(&hc_regs->hcint);
+ if (!(hcint & DWC2_HCINT_CHHLTD))
+ continue;
+
+ if (hcint & DWC2_HCINT_XFERCOMP) {
+ hctsiz = readl(&hc_regs->hctsiz);
+ done = len;
+
+ sub = hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK;
+ sub >>= DWC2_HCTSIZ_XFERSIZE_OFFSET;
+
+ if (usb_pipein(pipe))
+ done -= sub;
+ }
+
+ if (hcint & DWC2_HCINT_ACK) {
+ tmp = hctsiz & DWC2_HCTSIZ_PID_MASK;
+ tmp >>= DWC2_HCTSIZ_PID_OFFSET;
+ if (tmp == DWC2_HC_PID_DATA0) {
+ control_data_toggle[devnum][ep] =
+ DWC2_HC_PID_DATA0;
+ } else {
+ control_data_toggle[devnum][ep] =
+ DWC2_HC_PID_DATA1;
+ }
+ }
+
+ if (hcint != hcint_comp_hlt_ack) {
+ printf("%s: Error (HCINT=%08x)\n",
+ __func__, hcint);
+ goto out;
+ }
+
+ if (!--timeout) {
+ printf("%s: Timeout!\n", __func__);
+ goto out;
+ }
+
+ break;
+ }
+ } /* End of DATA stage */
+
+ /* STATUS stage */
+ if ((len == 0) || usb_pipeout(pipe))
+ status_direction = 1;
+ else
+ status_direction = 0;
+
+ dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep,
+ status_direction, DWC2_HCCHAR_EPTYPE_CONTROL, max);
+
+ writel((1 << DWC2_HCTSIZ_PKTCNT_OFFSET) |
+ (DWC2_HC_PID_DATA1 << DWC2_HCTSIZ_PID_OFFSET),
+ &hc_regs->hctsiz);
+
+ writel((uint32_t)status_buffer, &hc_regs->hcdma);
+
+ /* Set host channel enable after all other setup is complete. */
+ clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
+ DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
+ (1 << DWC2_HCCHAR_MULTICNT_OFFSET) | DWC2_HCCHAR_CHEN);
+
+ while (1) {
+ hcint = readl(&hc_regs->hcint);
+ if (hcint & DWC2_HCINT_CHHLTD)
+ break;
+ }
+
+ if (hcint != hcint_comp_hlt_ack)
+ printf("%s: Error (HCINT=%08x)\n", __func__, hcint);
+
+out:
+ dev->act_len = done;
+ dev->status = 0;
+
+ return done;
+}
+
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int len, int interval)
+{
+ printf("dev = %p pipe = %#lx buf = %p size = %d int = %d\n",
+ dev, pipe, buffer, len, interval);
+ return -ENOSYS;
+}
+
+/* U-Boot USB control interface */
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
+{
+ uint32_t snpsid;
+ int i, j;
+
+ root_hub_devnum = 0;
+
+ snpsid = readl(®s->gsnpsid);
+ printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
+
+ if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx) {
+ printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
+ return -ENODEV;
+ }
+
+ dwc_otg_core_init(regs);
+ dwc_otg_core_host_init(regs);
+
+ clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
+ DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
+ DWC2_HPRT0_PRTOVRCURRCHNG,
+ DWC2_HPRT0_PRTRST);
+ mdelay(50);
+ clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
+ DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
+ DWC2_HPRT0_PRTRST);
+
+ for (i = 0; i < MAX_DEVICE; i++) {
+ for (j = 0; j < MAX_ENDPOINT; j++) {
+ control_data_toggle[i][j] = DWC2_HC_PID_DATA1;
+ bulk_data_toggle[i][j] = DWC2_HC_PID_DATA0;
+ }
+ }
+
+ return 0;
+}
+
+int usb_lowlevel_stop(int index)
+{
+ /* Put everything in reset. */
+ clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
+ DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
+ DWC2_HPRT0_PRTOVRCURRCHNG,
+ DWC2_HPRT0_PRTRST);
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DWC2_H__
+#define __DWC2_H__
+
+struct dwc2_hc_regs {
+ u32 hcchar; /* 0x00 */
+ u32 hcsplt;
+ u32 hcint;
+ u32 hcintmsk;
+ u32 hctsiz; /* 0x10 */
+ u32 hcdma;
+ u32 reserved;
+ u32 hcdmab;
+};
+
+struct dwc2_host_regs {
+ u32 hcfg; /* 0x00 */
+ u32 hfir;
+ u32 hfnum;
+ u32 _pad_0x40c;
+ u32 hptxsts; /* 0x10 */
+ u32 haint;
+ u32 haintmsk;
+ u32 hflbaddr;
+};
+
+struct dwc2_core_regs {
+ u32 gotgctl; /* 0x000 */
+ u32 gotgint;
+ u32 gahbcfg;
+ u32 gusbcfg;
+ u32 grstctl; /* 0x010 */
+ u32 gintsts;
+ u32 gintmsk;
+ u32 grxstsr;
+ u32 grxstsp; /* 0x020 */
+ u32 grxfsiz;
+ u32 gnptxfsiz;
+ u32 gnptxsts;
+ u32 gi2cctl; /* 0x030 */
+ u32 gpvndctl;
+ u32 ggpio;
+ u32 guid;
+ u32 gsnpsid; /* 0x040 */
+ u32 ghwcfg1;
+ u32 ghwcfg2;
+ u32 ghwcfg3;
+ u32 ghwcfg4; /* 0x050 */
+ u32 glpmcfg;
+ u32 _pad_0x58_0x9c[42];
+ u32 hptxfsiz; /* 0x100 */
+ u32 dptxfsiz_dieptxf[15];
+ u32 _pad_0x140_0x3fc[176];
+ struct dwc2_host_regs host_regs; /* 0x400 */
+ u32 _pad_0x420_0x43c[8];
+ u32 hprt0; /* 0x440 */
+ u32 _pad_0x444_0x4fc[47];
+ struct dwc2_hc_regs hc_regs[16]; /* 0x500 */
+ u32 _pad_0x700_0xe00[448];
+ u32 pcgcctl; /* 0xe00 */
+};
+
+#define DWC2_GOTGCTL_SESREQSCS (1 << 0)
+#define DWC2_GOTGCTL_SESREQSCS_OFFSET 0
+#define DWC2_GOTGCTL_SESREQ (1 << 1)
+#define DWC2_GOTGCTL_SESREQ_OFFSET 1
+#define DWC2_GOTGCTL_HSTNEGSCS (1 << 8)
+#define DWC2_GOTGCTL_HSTNEGSCS_OFFSET 8
+#define DWC2_GOTGCTL_HNPREQ (1 << 9)
+#define DWC2_GOTGCTL_HNPREQ_OFFSET 9
+#define DWC2_GOTGCTL_HSTSETHNPEN (1 << 10)
+#define DWC2_GOTGCTL_HSTSETHNPEN_OFFSET 10
+#define DWC2_GOTGCTL_DEVHNPEN (1 << 11)
+#define DWC2_GOTGCTL_DEVHNPEN_OFFSET 11
+#define DWC2_GOTGCTL_CONIDSTS (1 << 16)
+#define DWC2_GOTGCTL_CONIDSTS_OFFSET 16
+#define DWC2_GOTGCTL_DBNCTIME (1 << 17)
+#define DWC2_GOTGCTL_DBNCTIME_OFFSET 17
+#define DWC2_GOTGCTL_ASESVLD (1 << 18)
+#define DWC2_GOTGCTL_ASESVLD_OFFSET 18
+#define DWC2_GOTGCTL_BSESVLD (1 << 19)
+#define DWC2_GOTGCTL_BSESVLD_OFFSET 19
+#define DWC2_GOTGCTL_OTGVER (1 << 20)
+#define DWC2_GOTGCTL_OTGVER_OFFSET 20
+#define DWC2_GOTGINT_SESENDDET (1 << 2)
+#define DWC2_GOTGINT_SESENDDET_OFFSET 2
+#define DWC2_GOTGINT_SESREQSUCSTSCHNG (1 << 8)
+#define DWC2_GOTGINT_SESREQSUCSTSCHNG_OFFSET 8
+#define DWC2_GOTGINT_HSTNEGSUCSTSCHNG (1 << 9)
+#define DWC2_GOTGINT_HSTNEGSUCSTSCHNG_OFFSET 9
+#define DWC2_GOTGINT_RESERVER10_16_MASK (0x7F << 10)
+#define DWC2_GOTGINT_RESERVER10_16_OFFSET 10
+#define DWC2_GOTGINT_HSTNEGDET (1 << 17)
+#define DWC2_GOTGINT_HSTNEGDET_OFFSET 17
+#define DWC2_GOTGINT_ADEVTOUTCHNG (1 << 18)
+#define DWC2_GOTGINT_ADEVTOUTCHNG_OFFSET 18
+#define DWC2_GOTGINT_DEBDONE (1 << 19)
+#define DWC2_GOTGINT_DEBDONE_OFFSET 19
+#define DWC2_GAHBCFG_GLBLINTRMSK (1 << 0)
+#define DWC2_GAHBCFG_GLBLINTRMSK_OFFSET 0
+#define DWC2_GAHBCFG_HBURSTLEN_SINGLE (0 << 1)
+#define DWC2_GAHBCFG_HBURSTLEN_INCR (1 << 1)
+#define DWC2_GAHBCFG_HBURSTLEN_INCR4 (3 << 1)
+#define DWC2_GAHBCFG_HBURSTLEN_INCR8 (5 << 1)
+#define DWC2_GAHBCFG_HBURSTLEN_INCR16 (7 << 1)
+#define DWC2_GAHBCFG_HBURSTLEN_MASK (0xF << 1)
+#define DWC2_GAHBCFG_HBURSTLEN_OFFSET 1
+#define DWC2_GAHBCFG_DMAENABLE (1 << 5)
+#define DWC2_GAHBCFG_DMAENABLE_OFFSET 5
+#define DWC2_GAHBCFG_NPTXFEMPLVL_TXFEMPLVL (1 << 7)
+#define DWC2_GAHBCFG_NPTXFEMPLVL_TXFEMPLVL_OFFSET 7
+#define DWC2_GAHBCFG_PTXFEMPLVL (1 << 8)
+#define DWC2_GAHBCFG_PTXFEMPLVL_OFFSET 8
+#define DWC2_GUSBCFG_TOUTCAL_MASK (0x7 << 0)
+#define DWC2_GUSBCFG_TOUTCAL_OFFSET 0
+#define DWC2_GUSBCFG_PHYIF (1 << 3)
+#define DWC2_GUSBCFG_PHYIF_OFFSET 3
+#define DWC2_GUSBCFG_ULPI_UTMI_SEL (1 << 4)
+#define DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET 4
+#define DWC2_GUSBCFG_FSINTF (1 << 5)
+#define DWC2_GUSBCFG_FSINTF_OFFSET 5
+#define DWC2_GUSBCFG_PHYSEL (1 << 6)
+#define DWC2_GUSBCFG_PHYSEL_OFFSET 6
+#define DWC2_GUSBCFG_DDRSEL (1 << 7)
+#define DWC2_GUSBCFG_DDRSEL_OFFSET 7
+#define DWC2_GUSBCFG_SRPCAP (1 << 8)
+#define DWC2_GUSBCFG_SRPCAP_OFFSET 8
+#define DWC2_GUSBCFG_HNPCAP (1 << 9)
+#define DWC2_GUSBCFG_HNPCAP_OFFSET 9
+#define DWC2_GUSBCFG_USBTRDTIM_MASK (0xF << 10)
+#define DWC2_GUSBCFG_USBTRDTIM_OFFSET 10
+#define DWC2_GUSBCFG_NPTXFRWNDEN (1 << 14)
+#define DWC2_GUSBCFG_NPTXFRWNDEN_OFFSET 14
+#define DWC2_GUSBCFG_PHYLPWRCLKSEL (1 << 15)
+#define DWC2_GUSBCFG_PHYLPWRCLKSEL_OFFSET 15
+#define DWC2_GUSBCFG_OTGUTMIFSSEL (1 << 16)
+#define DWC2_GUSBCFG_OTGUTMIFSSEL_OFFSET 16
+#define DWC2_GUSBCFG_ULPI_FSLS (1 << 17)
+#define DWC2_GUSBCFG_ULPI_FSLS_OFFSET 17
+#define DWC2_GUSBCFG_ULPI_AUTO_RES (1 << 18)
+#define DWC2_GUSBCFG_ULPI_AUTO_RES_OFFSET 18
+#define DWC2_GUSBCFG_ULPI_CLK_SUS_M (1 << 19)
+#define DWC2_GUSBCFG_ULPI_CLK_SUS_M_OFFSET 19
+#define DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV (1 << 20)
+#define DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV_OFFSET 20
+#define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR (1 << 21)
+#define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR_OFFSET 21
+#define DWC2_GUSBCFG_TERM_SEL_DL_PULSE (1 << 22)
+#define DWC2_GUSBCFG_TERM_SEL_DL_PULSE_OFFSET 22
+#define DWC2_GUSBCFG_IC_USB_CAP (1 << 26)
+#define DWC2_GUSBCFG_IC_USB_CAP_OFFSET 26
+#define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE (1 << 27)
+#define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE_OFFSET 27
+#define DWC2_GUSBCFG_TX_END_DELAY (1 << 28)
+#define DWC2_GUSBCFG_TX_END_DELAY_OFFSET 28
+#define DWC2_GUSBCFG_FORCEHOSTMODE (1 << 29)
+#define DWC2_GUSBCFG_FORCEHOSTMODE_OFFSET 29
+#define DWC2_GUSBCFG_FORCEDEVMODE (1 << 30)
+#define DWC2_GUSBCFG_FORCEDEVMODE_OFFSET 30
+#define DWC2_GLPMCTL_LPM_CAP_EN (1 << 0)
+#define DWC2_GLPMCTL_LPM_CAP_EN_OFFSET 0
+#define DWC2_GLPMCTL_APPL_RESP (1 << 1)
+#define DWC2_GLPMCTL_APPL_RESP_OFFSET 1
+#define DWC2_GLPMCTL_HIRD_MASK (0xF << 2)
+#define DWC2_GLPMCTL_HIRD_OFFSET 2
+#define DWC2_GLPMCTL_REM_WKUP_EN (1 << 6)
+#define DWC2_GLPMCTL_REM_WKUP_EN_OFFSET 6
+#define DWC2_GLPMCTL_EN_UTMI_SLEEP (1 << 7)
+#define DWC2_GLPMCTL_EN_UTMI_SLEEP_OFFSET 7
+#define DWC2_GLPMCTL_HIRD_THRES_MASK (0x1F << 8)
+#define DWC2_GLPMCTL_HIRD_THRES_OFFSET 8
+#define DWC2_GLPMCTL_LPM_RESP_MASK (0x3 << 13)
+#define DWC2_GLPMCTL_LPM_RESP_OFFSET 13
+#define DWC2_GLPMCTL_PRT_SLEEP_STS (1 << 15)
+#define DWC2_GLPMCTL_PRT_SLEEP_STS_OFFSET 15
+#define DWC2_GLPMCTL_SLEEP_STATE_RESUMEOK (1 << 16)
+#define DWC2_GLPMCTL_SLEEP_STATE_RESUMEOK_OFFSET 16
+#define DWC2_GLPMCTL_LPM_CHAN_INDEX_MASK (0xF << 17)
+#define DWC2_GLPMCTL_LPM_CHAN_INDEX_OFFSET 17
+#define DWC2_GLPMCTL_RETRY_COUNT_MASK (0x7 << 21)
+#define DWC2_GLPMCTL_RETRY_COUNT_OFFSET 21
+#define DWC2_GLPMCTL_SEND_LPM (1 << 24)
+#define DWC2_GLPMCTL_SEND_LPM_OFFSET 24
+#define DWC2_GLPMCTL_RETRY_COUNT_STS_MASK (0x7 << 25)
+#define DWC2_GLPMCTL_RETRY_COUNT_STS_OFFSET 25
+#define DWC2_GLPMCTL_HSIC_CONNECT (1 << 30)
+#define DWC2_GLPMCTL_HSIC_CONNECT_OFFSET 30
+#define DWC2_GLPMCTL_INV_SEL_HSIC (1 << 31)
+#define DWC2_GLPMCTL_INV_SEL_HSIC_OFFSET 31
+#define DWC2_GRSTCTL_CSFTRST (1 << 0)
+#define DWC2_GRSTCTL_CSFTRST_OFFSET 0
+#define DWC2_GRSTCTL_HSFTRST (1 << 1)
+#define DWC2_GRSTCTL_HSFTRST_OFFSET 1
+#define DWC2_GRSTCTL_HSTFRM (1 << 2)
+#define DWC2_GRSTCTL_HSTFRM_OFFSET 2
+#define DWC2_GRSTCTL_INTKNQFLSH (1 << 3)
+#define DWC2_GRSTCTL_INTKNQFLSH_OFFSET 3
+#define DWC2_GRSTCTL_RXFFLSH (1 << 4)
+#define DWC2_GRSTCTL_RXFFLSH_OFFSET 4
+#define DWC2_GRSTCTL_TXFFLSH (1 << 5)
+#define DWC2_GRSTCTL_TXFFLSH_OFFSET 5
+#define DWC2_GRSTCTL_TXFNUM_MASK (0x1F << 6)
+#define DWC2_GRSTCTL_TXFNUM_OFFSET 6
+#define DWC2_GRSTCTL_DMAREQ (1 << 30)
+#define DWC2_GRSTCTL_DMAREQ_OFFSET 30
+#define DWC2_GRSTCTL_AHBIDLE (1 << 31)
+#define DWC2_GRSTCTL_AHBIDLE_OFFSET 31
+#define DWC2_GINTMSK_MODEMISMATCH (1 << 1)
+#define DWC2_GINTMSK_MODEMISMATCH_OFFSET 1
+#define DWC2_GINTMSK_OTGINTR (1 << 2)
+#define DWC2_GINTMSK_OTGINTR_OFFSET 2
+#define DWC2_GINTMSK_SOFINTR (1 << 3)
+#define DWC2_GINTMSK_SOFINTR_OFFSET 3
+#define DWC2_GINTMSK_RXSTSQLVL (1 << 4)
+#define DWC2_GINTMSK_RXSTSQLVL_OFFSET 4
+#define DWC2_GINTMSK_NPTXFEMPTY (1 << 5)
+#define DWC2_GINTMSK_NPTXFEMPTY_OFFSET 5
+#define DWC2_GINTMSK_GINNAKEFF (1 << 6)
+#define DWC2_GINTMSK_GINNAKEFF_OFFSET 6
+#define DWC2_GINTMSK_GOUTNAKEFF (1 << 7)
+#define DWC2_GINTMSK_GOUTNAKEFF_OFFSET 7
+#define DWC2_GINTMSK_I2CINTR (1 << 9)
+#define DWC2_GINTMSK_I2CINTR_OFFSET 9
+#define DWC2_GINTMSK_ERLYSUSPEND (1 << 10)
+#define DWC2_GINTMSK_ERLYSUSPEND_OFFSET 10
+#define DWC2_GINTMSK_USBSUSPEND (1 << 11)
+#define DWC2_GINTMSK_USBSUSPEND_OFFSET 11
+#define DWC2_GINTMSK_USBRESET (1 << 12)
+#define DWC2_GINTMSK_USBRESET_OFFSET 12
+#define DWC2_GINTMSK_ENUMDONE (1 << 13)
+#define DWC2_GINTMSK_ENUMDONE_OFFSET 13
+#define DWC2_GINTMSK_ISOOUTDROP (1 << 14)
+#define DWC2_GINTMSK_ISOOUTDROP_OFFSET 14
+#define DWC2_GINTMSK_EOPFRAME (1 << 15)
+#define DWC2_GINTMSK_EOPFRAME_OFFSET 15
+#define DWC2_GINTMSK_EPMISMATCH (1 << 17)
+#define DWC2_GINTMSK_EPMISMATCH_OFFSET 17
+#define DWC2_GINTMSK_INEPINTR (1 << 18)
+#define DWC2_GINTMSK_INEPINTR_OFFSET 18
+#define DWC2_GINTMSK_OUTEPINTR (1 << 19)
+#define DWC2_GINTMSK_OUTEPINTR_OFFSET 19
+#define DWC2_GINTMSK_INCOMPLISOIN (1 << 20)
+#define DWC2_GINTMSK_INCOMPLISOIN_OFFSET 20
+#define DWC2_GINTMSK_INCOMPLISOOUT (1 << 21)
+#define DWC2_GINTMSK_INCOMPLISOOUT_OFFSET 21
+#define DWC2_GINTMSK_PORTINTR (1 << 24)
+#define DWC2_GINTMSK_PORTINTR_OFFSET 24
+#define DWC2_GINTMSK_HCINTR (1 << 25)
+#define DWC2_GINTMSK_HCINTR_OFFSET 25
+#define DWC2_GINTMSK_PTXFEMPTY (1 << 26)
+#define DWC2_GINTMSK_PTXFEMPTY_OFFSET 26
+#define DWC2_GINTMSK_LPMTRANRCVD (1 << 27)
+#define DWC2_GINTMSK_LPMTRANRCVD_OFFSET 27
+#define DWC2_GINTMSK_CONIDSTSCHNG (1 << 28)
+#define DWC2_GINTMSK_CONIDSTSCHNG_OFFSET 28
+#define DWC2_GINTMSK_DISCONNECT (1 << 29)
+#define DWC2_GINTMSK_DISCONNECT_OFFSET 29
+#define DWC2_GINTMSK_SESSREQINTR (1 << 30)
+#define DWC2_GINTMSK_SESSREQINTR_OFFSET 30
+#define DWC2_GINTMSK_WKUPINTR (1 << 31)
+#define DWC2_GINTMSK_WKUPINTR_OFFSET 31
+#define DWC2_GINTSTS_CURMODE_DEVICE (0 << 0)
+#define DWC2_GINTSTS_CURMODE_HOST (1 << 0)
+#define DWC2_GINTSTS_CURMODE (1 << 0)
+#define DWC2_GINTSTS_CURMODE_OFFSET 0
+#define DWC2_GINTSTS_MODEMISMATCH (1 << 1)
+#define DWC2_GINTSTS_MODEMISMATCH_OFFSET 1
+#define DWC2_GINTSTS_OTGINTR (1 << 2)
+#define DWC2_GINTSTS_OTGINTR_OFFSET 2
+#define DWC2_GINTSTS_SOFINTR (1 << 3)
+#define DWC2_GINTSTS_SOFINTR_OFFSET 3
+#define DWC2_GINTSTS_RXSTSQLVL (1 << 4)
+#define DWC2_GINTSTS_RXSTSQLVL_OFFSET 4
+#define DWC2_GINTSTS_NPTXFEMPTY (1 << 5)
+#define DWC2_GINTSTS_NPTXFEMPTY_OFFSET 5
+#define DWC2_GINTSTS_GINNAKEFF (1 << 6)
+#define DWC2_GINTSTS_GINNAKEFF_OFFSET 6
+#define DWC2_GINTSTS_GOUTNAKEFF (1 << 7)
+#define DWC2_GINTSTS_GOUTNAKEFF_OFFSET 7
+#define DWC2_GINTSTS_I2CINTR (1 << 9)
+#define DWC2_GINTSTS_I2CINTR_OFFSET 9
+#define DWC2_GINTSTS_ERLYSUSPEND (1 << 10)
+#define DWC2_GINTSTS_ERLYSUSPEND_OFFSET 10
+#define DWC2_GINTSTS_USBSUSPEND (1 << 11)
+#define DWC2_GINTSTS_USBSUSPEND_OFFSET 11
+#define DWC2_GINTSTS_USBRESET (1 << 12)
+#define DWC2_GINTSTS_USBRESET_OFFSET 12
+#define DWC2_GINTSTS_ENUMDONE (1 << 13)
+#define DWC2_GINTSTS_ENUMDONE_OFFSET 13
+#define DWC2_GINTSTS_ISOOUTDROP (1 << 14)
+#define DWC2_GINTSTS_ISOOUTDROP_OFFSET 14
+#define DWC2_GINTSTS_EOPFRAME (1 << 15)
+#define DWC2_GINTSTS_EOPFRAME_OFFSET 15
+#define DWC2_GINTSTS_INTOKENRX (1 << 16)
+#define DWC2_GINTSTS_INTOKENRX_OFFSET 16
+#define DWC2_GINTSTS_EPMISMATCH (1 << 17)
+#define DWC2_GINTSTS_EPMISMATCH_OFFSET 17
+#define DWC2_GINTSTS_INEPINT (1 << 18)
+#define DWC2_GINTSTS_INEPINT_OFFSET 18
+#define DWC2_GINTSTS_OUTEPINTR (1 << 19)
+#define DWC2_GINTSTS_OUTEPINTR_OFFSET 19
+#define DWC2_GINTSTS_INCOMPLISOIN (1 << 20)
+#define DWC2_GINTSTS_INCOMPLISOIN_OFFSET 20
+#define DWC2_GINTSTS_INCOMPLISOOUT (1 << 21)
+#define DWC2_GINTSTS_INCOMPLISOOUT_OFFSET 21
+#define DWC2_GINTSTS_PORTINTR (1 << 24)
+#define DWC2_GINTSTS_PORTINTR_OFFSET 24
+#define DWC2_GINTSTS_HCINTR (1 << 25)
+#define DWC2_GINTSTS_HCINTR_OFFSET 25
+#define DWC2_GINTSTS_PTXFEMPTY (1 << 26)
+#define DWC2_GINTSTS_PTXFEMPTY_OFFSET 26
+#define DWC2_GINTSTS_LPMTRANRCVD (1 << 27)
+#define DWC2_GINTSTS_LPMTRANRCVD_OFFSET 27
+#define DWC2_GINTSTS_CONIDSTSCHNG (1 << 28)
+#define DWC2_GINTSTS_CONIDSTSCHNG_OFFSET 28
+#define DWC2_GINTSTS_DISCONNECT (1 << 29)
+#define DWC2_GINTSTS_DISCONNECT_OFFSET 29
+#define DWC2_GINTSTS_SESSREQINTR (1 << 30)
+#define DWC2_GINTSTS_SESSREQINTR_OFFSET 30
+#define DWC2_GINTSTS_WKUPINTR (1 << 31)
+#define DWC2_GINTSTS_WKUPINTR_OFFSET 31
+#define DWC2_GRXSTS_EPNUM_MASK (0xF << 0)
+#define DWC2_GRXSTS_EPNUM_OFFSET 0
+#define DWC2_GRXSTS_BCNT_MASK (0x7FF << 4)
+#define DWC2_GRXSTS_BCNT_OFFSET 4
+#define DWC2_GRXSTS_DPID_MASK (0x3 << 15)
+#define DWC2_GRXSTS_DPID_OFFSET 15
+#define DWC2_GRXSTS_PKTSTS_MASK (0xF << 17)
+#define DWC2_GRXSTS_PKTSTS_OFFSET 17
+#define DWC2_GRXSTS_FN_MASK (0xF << 21)
+#define DWC2_GRXSTS_FN_OFFSET 21
+#define DWC2_FIFOSIZE_STARTADDR_MASK (0xFFFF << 0)
+#define DWC2_FIFOSIZE_STARTADDR_OFFSET 0
+#define DWC2_FIFOSIZE_DEPTH_MASK (0xFFFF << 16)
+#define DWC2_FIFOSIZE_DEPTH_OFFSET 16
+#define DWC2_GNPTXSTS_NPTXFSPCAVAIL_MASK (0xFFFF << 0)
+#define DWC2_GNPTXSTS_NPTXFSPCAVAIL_OFFSET 0
+#define DWC2_GNPTXSTS_NPTXQSPCAVAIL_MASK (0xFF << 16)
+#define DWC2_GNPTXSTS_NPTXQSPCAVAIL_OFFSET 16
+#define DWC2_GNPTXSTS_NPTXQTOP_TERMINATE (1 << 24)
+#define DWC2_GNPTXSTS_NPTXQTOP_TERMINATE_OFFSET 24
+#define DWC2_GNPTXSTS_NPTXQTOP_TOKEN_MASK (0x3 << 25)
+#define DWC2_GNPTXSTS_NPTXQTOP_TOKEN_OFFSET 25
+#define DWC2_GNPTXSTS_NPTXQTOP_CHNEP_MASK (0xF << 27)
+#define DWC2_GNPTXSTS_NPTXQTOP_CHNEP_OFFSET 27
+#define DWC2_DTXFSTS_TXFSPCAVAIL_MASK (0xFFFF << 0)
+#define DWC2_DTXFSTS_TXFSPCAVAIL_OFFSET 0
+#define DWC2_GI2CCTL_RWDATA_MASK (0xFF << 0)
+#define DWC2_GI2CCTL_RWDATA_OFFSET 0
+#define DWC2_GI2CCTL_REGADDR_MASK (0xFF << 8)
+#define DWC2_GI2CCTL_REGADDR_OFFSET 8
+#define DWC2_GI2CCTL_ADDR_MASK (0x7F << 16)
+#define DWC2_GI2CCTL_ADDR_OFFSET 16
+#define DWC2_GI2CCTL_I2CEN (1 << 23)
+#define DWC2_GI2CCTL_I2CEN_OFFSET 23
+#define DWC2_GI2CCTL_ACK (1 << 24)
+#define DWC2_GI2CCTL_ACK_OFFSET 24
+#define DWC2_GI2CCTL_I2CSUSPCTL (1 << 25)
+#define DWC2_GI2CCTL_I2CSUSPCTL_OFFSET 25
+#define DWC2_GI2CCTL_I2CDEVADDR_MASK (0x3 << 26)
+#define DWC2_GI2CCTL_I2CDEVADDR_OFFSET 26
+#define DWC2_GI2CCTL_RW (1 << 30)
+#define DWC2_GI2CCTL_RW_OFFSET 30
+#define DWC2_GI2CCTL_BSYDNE (1 << 31)
+#define DWC2_GI2CCTL_BSYDNE_OFFSET 31
+#define DWC2_HWCFG1_EP_DIR0_MASK (0x3 << 0)
+#define DWC2_HWCFG1_EP_DIR0_OFFSET 0
+#define DWC2_HWCFG1_EP_DIR1_MASK (0x3 << 2)
+#define DWC2_HWCFG1_EP_DIR1_OFFSET 2
+#define DWC2_HWCFG1_EP_DIR2_MASK (0x3 << 4)
+#define DWC2_HWCFG1_EP_DIR2_OFFSET 4
+#define DWC2_HWCFG1_EP_DIR3_MASK (0x3 << 6)
+#define DWC2_HWCFG1_EP_DIR3_OFFSET 6
+#define DWC2_HWCFG1_EP_DIR4_MASK (0x3 << 8)
+#define DWC2_HWCFG1_EP_DIR4_OFFSET 8
+#define DWC2_HWCFG1_EP_DIR5_MASK (0x3 << 10)
+#define DWC2_HWCFG1_EP_DIR5_OFFSET 10
+#define DWC2_HWCFG1_EP_DIR6_MASK (0x3 << 12)
+#define DWC2_HWCFG1_EP_DIR6_OFFSET 12
+#define DWC2_HWCFG1_EP_DIR7_MASK (0x3 << 14)
+#define DWC2_HWCFG1_EP_DIR7_OFFSET 14
+#define DWC2_HWCFG1_EP_DIR8_MASK (0x3 << 16)
+#define DWC2_HWCFG1_EP_DIR8_OFFSET 16
+#define DWC2_HWCFG1_EP_DIR9_MASK (0x3 << 18)
+#define DWC2_HWCFG1_EP_DIR9_OFFSET 18
+#define DWC2_HWCFG1_EP_DIR10_MASK (0x3 << 20)
+#define DWC2_HWCFG1_EP_DIR10_OFFSET 20
+#define DWC2_HWCFG1_EP_DIR11_MASK (0x3 << 22)
+#define DWC2_HWCFG1_EP_DIR11_OFFSET 22
+#define DWC2_HWCFG1_EP_DIR12_MASK (0x3 << 24)
+#define DWC2_HWCFG1_EP_DIR12_OFFSET 24
+#define DWC2_HWCFG1_EP_DIR13_MASK (0x3 << 26)
+#define DWC2_HWCFG1_EP_DIR13_OFFSET 26
+#define DWC2_HWCFG1_EP_DIR14_MASK (0x3 << 28)
+#define DWC2_HWCFG1_EP_DIR14_OFFSET 28
+#define DWC2_HWCFG1_EP_DIR15_MASK (0x3 << 30)
+#define DWC2_HWCFG1_EP_DIR15_OFFSET 30
+#define DWC2_HWCFG2_OP_MODE_MASK (0x7 << 0)
+#define DWC2_HWCFG2_OP_MODE_OFFSET 0
+#define DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY (0x0 << 3)
+#define DWC2_HWCFG2_ARCHITECTURE_EXT_DMA (0x1 << 3)
+#define DWC2_HWCFG2_ARCHITECTURE_INT_DMA (0x2 << 3)
+#define DWC2_HWCFG2_ARCHITECTURE_MASK (0x3 << 3)
+#define DWC2_HWCFG2_ARCHITECTURE_OFFSET 3
+#define DWC2_HWCFG2_POINT2POINT (1 << 5)
+#define DWC2_HWCFG2_POINT2POINT_OFFSET 5
+#define DWC2_HWCFG2_HS_PHY_TYPE_MASK (0x3 << 6)
+#define DWC2_HWCFG2_HS_PHY_TYPE_OFFSET 6
+#define DWC2_HWCFG2_FS_PHY_TYPE_MASK (0x3 << 8)
+#define DWC2_HWCFG2_FS_PHY_TYPE_OFFSET 8
+#define DWC2_HWCFG2_NUM_DEV_EP_MASK (0xF << 10)
+#define DWC2_HWCFG2_NUM_DEV_EP_OFFSET 10
+#define DWC2_HWCFG2_NUM_HOST_CHAN_MASK (0xF << 14)
+#define DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET 14
+#define DWC2_HWCFG2_PERIO_EP_SUPPORTED (1 << 18)
+#define DWC2_HWCFG2_PERIO_EP_SUPPORTED_OFFSET 18
+#define DWC2_HWCFG2_DYNAMIC_FIFO (1 << 19)
+#define DWC2_HWCFG2_DYNAMIC_FIFO_OFFSET 19
+#define DWC2_HWCFG2_MULTI_PROC_INT (1 << 20)
+#define DWC2_HWCFG2_MULTI_PROC_INT_OFFSET 20
+#define DWC2_HWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22)
+#define DWC2_HWCFG2_NONPERIO_TX_Q_DEPTH_OFFSET 22
+#define DWC2_HWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24)
+#define DWC2_HWCFG2_HOST_PERIO_TX_Q_DEPTH_OFFSET 24
+#define DWC2_HWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1F << 26)
+#define DWC2_HWCFG2_DEV_TOKEN_Q_DEPTH_OFFSET 26
+#define DWC2_HWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xF << 0)
+#define DWC2_HWCFG3_XFER_SIZE_CNTR_WIDTH_OFFSET 0
+#define DWC2_HWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4)
+#define DWC2_HWCFG3_PACKET_SIZE_CNTR_WIDTH_OFFSET 4
+#define DWC2_HWCFG3_OTG_FUNC (1 << 7)
+#define DWC2_HWCFG3_OTG_FUNC_OFFSET 7
+#define DWC2_HWCFG3_I2C (1 << 8)
+#define DWC2_HWCFG3_I2C_OFFSET 8
+#define DWC2_HWCFG3_VENDOR_CTRL_IF (1 << 9)
+#define DWC2_HWCFG3_VENDOR_CTRL_IF_OFFSET 9
+#define DWC2_HWCFG3_OPTIONAL_FEATURES (1 << 10)
+#define DWC2_HWCFG3_OPTIONAL_FEATURES_OFFSET 10
+#define DWC2_HWCFG3_SYNCH_RESET_TYPE (1 << 11)
+#define DWC2_HWCFG3_SYNCH_RESET_TYPE_OFFSET 11
+#define DWC2_HWCFG3_OTG_ENABLE_IC_USB (1 << 12)
+#define DWC2_HWCFG3_OTG_ENABLE_IC_USB_OFFSET 12
+#define DWC2_HWCFG3_OTG_ENABLE_HSIC (1 << 13)
+#define DWC2_HWCFG3_OTG_ENABLE_HSIC_OFFSET 13
+#define DWC2_HWCFG3_OTG_LPM_EN (1 << 15)
+#define DWC2_HWCFG3_OTG_LPM_EN_OFFSET 15
+#define DWC2_HWCFG3_DFIFO_DEPTH_MASK (0xFFFF << 16)
+#define DWC2_HWCFG3_DFIFO_DEPTH_OFFSET 16
+#define DWC2_HWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xF << 0)
+#define DWC2_HWCFG4_NUM_DEV_PERIO_IN_EP_OFFSET 0
+#define DWC2_HWCFG4_POWER_OPTIMIZ (1 << 4)
+#define DWC2_HWCFG4_POWER_OPTIMIZ_OFFSET 4
+#define DWC2_HWCFG4_MIN_AHB_FREQ_MASK (0x1FF << 5)
+#define DWC2_HWCFG4_MIN_AHB_FREQ_OFFSET 5
+#define DWC2_HWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14)
+#define DWC2_HWCFG4_UTMI_PHY_DATA_WIDTH_OFFSET 14
+#define DWC2_HWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xF << 16)
+#define DWC2_HWCFG4_NUM_DEV_MODE_CTRL_EP_OFFSET 16
+#define DWC2_HWCFG4_IDDIG_FILT_EN (1 << 20)
+#define DWC2_HWCFG4_IDDIG_FILT_EN_OFFSET 20
+#define DWC2_HWCFG4_VBUS_VALID_FILT_EN (1 << 21)
+#define DWC2_HWCFG4_VBUS_VALID_FILT_EN_OFFSET 21
+#define DWC2_HWCFG4_A_VALID_FILT_EN (1 << 22)
+#define DWC2_HWCFG4_A_VALID_FILT_EN_OFFSET 22
+#define DWC2_HWCFG4_B_VALID_FILT_EN (1 << 23)
+#define DWC2_HWCFG4_B_VALID_FILT_EN_OFFSET 23
+#define DWC2_HWCFG4_SESSION_END_FILT_EN (1 << 24)
+#define DWC2_HWCFG4_SESSION_END_FILT_EN_OFFSET 24
+#define DWC2_HWCFG4_DED_FIFO_EN (1 << 25)
+#define DWC2_HWCFG4_DED_FIFO_EN_OFFSET 25
+#define DWC2_HWCFG4_NUM_IN_EPS_MASK (0xF << 26)
+#define DWC2_HWCFG4_NUM_IN_EPS_OFFSET 26
+#define DWC2_HWCFG4_DESC_DMA (1 << 30)
+#define DWC2_HWCFG4_DESC_DMA_OFFSET 30
+#define DWC2_HWCFG4_DESC_DMA_DYN (1 << 31)
+#define DWC2_HWCFG4_DESC_DMA_DYN_OFFSET 31
+#define DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ 0
+#define DWC2_HCFG_FSLSPCLKSEL_48_MHZ 1
+#define DWC2_HCFG_FSLSPCLKSEL_6_MHZ 2
+#define DWC2_HCFG_FSLSPCLKSEL_MASK (0x3 << 0)
+#define DWC2_HCFG_FSLSPCLKSEL_OFFSET 0
+#define DWC2_HCFG_FSLSSUPP (1 << 2)
+#define DWC2_HCFG_FSLSSUPP_OFFSET 2
+#define DWC2_HCFG_DESCDMA (1 << 23)
+#define DWC2_HCFG_DESCDMA_OFFSET 23
+#define DWC2_HCFG_FRLISTEN_MASK (0x3 << 24)
+#define DWC2_HCFG_FRLISTEN_OFFSET 24
+#define DWC2_HCFG_PERSCHEDENA (1 << 26)
+#define DWC2_HCFG_PERSCHEDENA_OFFSET 26
+#define DWC2_HCFG_PERSCHEDSTAT (1 << 27)
+#define DWC2_HCFG_PERSCHEDSTAT_OFFSET 27
+#define DWC2_HFIR_FRINT_MASK (0xFFFF << 0)
+#define DWC2_HFIR_FRINT_OFFSET 0
+#define DWC2_HFNUM_FRNUM_MASK (0xFFFF << 0)
+#define DWC2_HFNUM_FRNUM_OFFSET 0
+#define DWC2_HFNUM_FRREM_MASK (0xFFFF << 16)
+#define DWC2_HFNUM_FRREM_OFFSET 16
+#define DWC2_HPTXSTS_PTXFSPCAVAIL_MASK (0xFFFF << 0)
+#define DWC2_HPTXSTS_PTXFSPCAVAIL_OFFSET 0
+#define DWC2_HPTXSTS_PTXQSPCAVAIL_MASK (0xFF << 16)
+#define DWC2_HPTXSTS_PTXQSPCAVAIL_OFFSET 16
+#define DWC2_HPTXSTS_PTXQTOP_TERMINATE (1 << 24)
+#define DWC2_HPTXSTS_PTXQTOP_TERMINATE_OFFSET 24
+#define DWC2_HPTXSTS_PTXQTOP_TOKEN_MASK (0x3 << 25)
+#define DWC2_HPTXSTS_PTXQTOP_TOKEN_OFFSET 25
+#define DWC2_HPTXSTS_PTXQTOP_CHNUM_MASK (0xF << 27)
+#define DWC2_HPTXSTS_PTXQTOP_CHNUM_OFFSET 27
+#define DWC2_HPTXSTS_PTXQTOP_ODD (1 << 31)
+#define DWC2_HPTXSTS_PTXQTOP_ODD_OFFSET 31
+#define DWC2_HPRT0_PRTCONNSTS (1 << 0)
+#define DWC2_HPRT0_PRTCONNSTS_OFFSET 0
+#define DWC2_HPRT0_PRTCONNDET (1 << 1)
+#define DWC2_HPRT0_PRTCONNDET_OFFSET 1
+#define DWC2_HPRT0_PRTENA (1 << 2)
+#define DWC2_HPRT0_PRTENA_OFFSET 2
+#define DWC2_HPRT0_PRTENCHNG (1 << 3)
+#define DWC2_HPRT0_PRTENCHNG_OFFSET 3
+#define DWC2_HPRT0_PRTOVRCURRACT (1 << 4)
+#define DWC2_HPRT0_PRTOVRCURRACT_OFFSET 4
+#define DWC2_HPRT0_PRTOVRCURRCHNG (1 << 5)
+#define DWC2_HPRT0_PRTOVRCURRCHNG_OFFSET 5
+#define DWC2_HPRT0_PRTRES (1 << 6)
+#define DWC2_HPRT0_PRTRES_OFFSET 6
+#define DWC2_HPRT0_PRTSUSP (1 << 7)
+#define DWC2_HPRT0_PRTSUSP_OFFSET 7
+#define DWC2_HPRT0_PRTRST (1 << 8)
+#define DWC2_HPRT0_PRTRST_OFFSET 8
+#define DWC2_HPRT0_PRTLNSTS_MASK (0x3 << 10)
+#define DWC2_HPRT0_PRTLNSTS_OFFSET 10
+#define DWC2_HPRT0_PRTPWR (1 << 12)
+#define DWC2_HPRT0_PRTPWR_OFFSET 12
+#define DWC2_HPRT0_PRTTSTCTL_MASK (0xF << 13)
+#define DWC2_HPRT0_PRTTSTCTL_OFFSET 13
+#define DWC2_HPRT0_PRTSPD_MASK (0x3 << 17)
+#define DWC2_HPRT0_PRTSPD_OFFSET 17
+#define DWC2_HAINT_CH0 (1 << 0)
+#define DWC2_HAINT_CH0_OFFSET 0
+#define DWC2_HAINT_CH1 (1 << 1)
+#define DWC2_HAINT_CH1_OFFSET 1
+#define DWC2_HAINT_CH2 (1 << 2)
+#define DWC2_HAINT_CH2_OFFSET 2
+#define DWC2_HAINT_CH3 (1 << 3)
+#define DWC2_HAINT_CH3_OFFSET 3
+#define DWC2_HAINT_CH4 (1 << 4)
+#define DWC2_HAINT_CH4_OFFSET 4
+#define DWC2_HAINT_CH5 (1 << 5)
+#define DWC2_HAINT_CH5_OFFSET 5
+#define DWC2_HAINT_CH6 (1 << 6)
+#define DWC2_HAINT_CH6_OFFSET 6
+#define DWC2_HAINT_CH7 (1 << 7)
+#define DWC2_HAINT_CH7_OFFSET 7
+#define DWC2_HAINT_CH8 (1 << 8)
+#define DWC2_HAINT_CH8_OFFSET 8
+#define DWC2_HAINT_CH9 (1 << 9)
+#define DWC2_HAINT_CH9_OFFSET 9
+#define DWC2_HAINT_CH10 (1 << 10)
+#define DWC2_HAINT_CH10_OFFSET 10
+#define DWC2_HAINT_CH11 (1 << 11)
+#define DWC2_HAINT_CH11_OFFSET 11
+#define DWC2_HAINT_CH12 (1 << 12)
+#define DWC2_HAINT_CH12_OFFSET 12
+#define DWC2_HAINT_CH13 (1 << 13)
+#define DWC2_HAINT_CH13_OFFSET 13
+#define DWC2_HAINT_CH14 (1 << 14)
+#define DWC2_HAINT_CH14_OFFSET 14
+#define DWC2_HAINT_CH15 (1 << 15)
+#define DWC2_HAINT_CH15_OFFSET 15
+#define DWC2_HAINT_CHINT_MASK 0xffff
+#define DWC2_HAINT_CHINT_OFFSET 0
+#define DWC2_HAINTMSK_CH0 (1 << 0)
+#define DWC2_HAINTMSK_CH0_OFFSET 0
+#define DWC2_HAINTMSK_CH1 (1 << 1)
+#define DWC2_HAINTMSK_CH1_OFFSET 1
+#define DWC2_HAINTMSK_CH2 (1 << 2)
+#define DWC2_HAINTMSK_CH2_OFFSET 2
+#define DWC2_HAINTMSK_CH3 (1 << 3)
+#define DWC2_HAINTMSK_CH3_OFFSET 3
+#define DWC2_HAINTMSK_CH4 (1 << 4)
+#define DWC2_HAINTMSK_CH4_OFFSET 4
+#define DWC2_HAINTMSK_CH5 (1 << 5)
+#define DWC2_HAINTMSK_CH5_OFFSET 5
+#define DWC2_HAINTMSK_CH6 (1 << 6)
+#define DWC2_HAINTMSK_CH6_OFFSET 6
+#define DWC2_HAINTMSK_CH7 (1 << 7)
+#define DWC2_HAINTMSK_CH7_OFFSET 7
+#define DWC2_HAINTMSK_CH8 (1 << 8)
+#define DWC2_HAINTMSK_CH8_OFFSET 8
+#define DWC2_HAINTMSK_CH9 (1 << 9)
+#define DWC2_HAINTMSK_CH9_OFFSET 9
+#define DWC2_HAINTMSK_CH10 (1 << 10)
+#define DWC2_HAINTMSK_CH10_OFFSET 10
+#define DWC2_HAINTMSK_CH11 (1 << 11)
+#define DWC2_HAINTMSK_CH11_OFFSET 11
+#define DWC2_HAINTMSK_CH12 (1 << 12)
+#define DWC2_HAINTMSK_CH12_OFFSET 12
+#define DWC2_HAINTMSK_CH13 (1 << 13)
+#define DWC2_HAINTMSK_CH13_OFFSET 13
+#define DWC2_HAINTMSK_CH14 (1 << 14)
+#define DWC2_HAINTMSK_CH14_OFFSET 14
+#define DWC2_HAINTMSK_CH15 (1 << 15)
+#define DWC2_HAINTMSK_CH15_OFFSET 15
+#define DWC2_HAINTMSK_CHINT_MASK 0xffff
+#define DWC2_HAINTMSK_CHINT_OFFSET 0
+#define DWC2_HCCHAR_MPS_MASK (0x7FF << 0)
+#define DWC2_HCCHAR_MPS_OFFSET 0
+#define DWC2_HCCHAR_EPNUM_MASK (0xF << 11)
+#define DWC2_HCCHAR_EPNUM_OFFSET 11
+#define DWC2_HCCHAR_EPDIR (1 << 15)
+#define DWC2_HCCHAR_EPDIR_OFFSET 15
+#define DWC2_HCCHAR_LSPDDEV (1 << 17)
+#define DWC2_HCCHAR_LSPDDEV_OFFSET 17
+#define DWC2_HCCHAR_EPTYPE_CONTROL 0
+#define DWC2_HCCHAR_EPTYPE_ISOC 1
+#define DWC2_HCCHAR_EPTYPE_BULK 2
+#define DWC2_HCCHAR_EPTYPE_INTR 3
+#define DWC2_HCCHAR_EPTYPE_MASK (0x3 << 18)
+#define DWC2_HCCHAR_EPTYPE_OFFSET 18
+#define DWC2_HCCHAR_MULTICNT_MASK (0x3 << 20)
+#define DWC2_HCCHAR_MULTICNT_OFFSET 20
+#define DWC2_HCCHAR_DEVADDR_MASK (0x7F << 22)
+#define DWC2_HCCHAR_DEVADDR_OFFSET 22
+#define DWC2_HCCHAR_ODDFRM (1 << 29)
+#define DWC2_HCCHAR_ODDFRM_OFFSET 29
+#define DWC2_HCCHAR_CHDIS (1 << 30)
+#define DWC2_HCCHAR_CHDIS_OFFSET 30
+#define DWC2_HCCHAR_CHEN (1 << 31)
+#define DWC2_HCCHAR_CHEN_OFFSET 31
+#define DWC2_HCSPLT_PRTADDR_MASK (0x7F << 0)
+#define DWC2_HCSPLT_PRTADDR_OFFSET 0
+#define DWC2_HCSPLT_HUBADDR_MASK (0x7F << 7)
+#define DWC2_HCSPLT_HUBADDR_OFFSET 7
+#define DWC2_HCSPLT_XACTPOS_MASK (0x3 << 14)
+#define DWC2_HCSPLT_XACTPOS_OFFSET 14
+#define DWC2_HCSPLT_COMPSPLT (1 << 16)
+#define DWC2_HCSPLT_COMPSPLT_OFFSET 16
+#define DWC2_HCSPLT_SPLTENA (1 << 31)
+#define DWC2_HCSPLT_SPLTENA_OFFSET 31
+#define DWC2_HCINT_XFERCOMP (1 << 0)
+#define DWC2_HCINT_XFERCOMP_OFFSET 0
+#define DWC2_HCINT_CHHLTD (1 << 1)
+#define DWC2_HCINT_CHHLTD_OFFSET 1
+#define DWC2_HCINT_AHBERR (1 << 2)
+#define DWC2_HCINT_AHBERR_OFFSET 2
+#define DWC2_HCINT_STALL (1 << 3)
+#define DWC2_HCINT_STALL_OFFSET 3
+#define DWC2_HCINT_NAK (1 << 4)
+#define DWC2_HCINT_NAK_OFFSET 4
+#define DWC2_HCINT_ACK (1 << 5)
+#define DWC2_HCINT_ACK_OFFSET 5
+#define DWC2_HCINT_NYET (1 << 6)
+#define DWC2_HCINT_NYET_OFFSET 6
+#define DWC2_HCINT_XACTERR (1 << 7)
+#define DWC2_HCINT_XACTERR_OFFSET 7
+#define DWC2_HCINT_BBLERR (1 << 8)
+#define DWC2_HCINT_BBLERR_OFFSET 8
+#define DWC2_HCINT_FRMOVRUN (1 << 9)
+#define DWC2_HCINT_FRMOVRUN_OFFSET 9
+#define DWC2_HCINT_DATATGLERR (1 << 10)
+#define DWC2_HCINT_DATATGLERR_OFFSET 10
+#define DWC2_HCINT_BNA (1 << 11)
+#define DWC2_HCINT_BNA_OFFSET 11
+#define DWC2_HCINT_XCS_XACT (1 << 12)
+#define DWC2_HCINT_XCS_XACT_OFFSET 12
+#define DWC2_HCINT_FRM_LIST_ROLL (1 << 13)
+#define DWC2_HCINT_FRM_LIST_ROLL_OFFSET 13
+#define DWC2_HCINTMSK_XFERCOMPL (1 << 0)
+#define DWC2_HCINTMSK_XFERCOMPL_OFFSET 0
+#define DWC2_HCINTMSK_CHHLTD (1 << 1)
+#define DWC2_HCINTMSK_CHHLTD_OFFSET 1
+#define DWC2_HCINTMSK_AHBERR (1 << 2)
+#define DWC2_HCINTMSK_AHBERR_OFFSET 2
+#define DWC2_HCINTMSK_STALL (1 << 3)
+#define DWC2_HCINTMSK_STALL_OFFSET 3
+#define DWC2_HCINTMSK_NAK (1 << 4)
+#define DWC2_HCINTMSK_NAK_OFFSET 4
+#define DWC2_HCINTMSK_ACK (1 << 5)
+#define DWC2_HCINTMSK_ACK_OFFSET 5
+#define DWC2_HCINTMSK_NYET (1 << 6)
+#define DWC2_HCINTMSK_NYET_OFFSET 6
+#define DWC2_HCINTMSK_XACTERR (1 << 7)
+#define DWC2_HCINTMSK_XACTERR_OFFSET 7
+#define DWC2_HCINTMSK_BBLERR (1 << 8)
+#define DWC2_HCINTMSK_BBLERR_OFFSET 8
+#define DWC2_HCINTMSK_FRMOVRUN (1 << 9)
+#define DWC2_HCINTMSK_FRMOVRUN_OFFSET 9
+#define DWC2_HCINTMSK_DATATGLERR (1 << 10)
+#define DWC2_HCINTMSK_DATATGLERR_OFFSET 10
+#define DWC2_HCINTMSK_BNA (1 << 11)
+#define DWC2_HCINTMSK_BNA_OFFSET 11
+#define DWC2_HCINTMSK_XCS_XACT (1 << 12)
+#define DWC2_HCINTMSK_XCS_XACT_OFFSET 12
+#define DWC2_HCINTMSK_FRM_LIST_ROLL (1 << 13)
+#define DWC2_HCINTMSK_FRM_LIST_ROLL_OFFSET 13
+#define DWC2_HCTSIZ_XFERSIZE_MASK 0x7ffff
+#define DWC2_HCTSIZ_XFERSIZE_OFFSET 0
+#define DWC2_HCTSIZ_SCHINFO_MASK 0xff
+#define DWC2_HCTSIZ_SCHINFO_OFFSET 0
+#define DWC2_HCTSIZ_NTD_MASK (0xff << 8)
+#define DWC2_HCTSIZ_NTD_OFFSET 8
+#define DWC2_HCTSIZ_PKTCNT_MASK (0x3ff << 19)
+#define DWC2_HCTSIZ_PKTCNT_OFFSET 19
+#define DWC2_HCTSIZ_PID_MASK (0x3 << 29)
+#define DWC2_HCTSIZ_PID_OFFSET 29
+#define DWC2_HCTSIZ_DOPNG (1 << 31)
+#define DWC2_HCTSIZ_DOPNG_OFFSET 31
+#define DWC2_HCDMA_CTD_MASK (0xFF << 3)
+#define DWC2_HCDMA_CTD_OFFSET 3
+#define DWC2_HCDMA_DMA_ADDR_MASK (0x1FFFFF << 11)
+#define DWC2_HCDMA_DMA_ADDR_OFFSET 11
+#define DWC2_PCGCCTL_STOPPCLK (1 << 0)
+#define DWC2_PCGCCTL_STOPPCLK_OFFSET 0
+#define DWC2_PCGCCTL_GATEHCLK (1 << 1)
+#define DWC2_PCGCCTL_GATEHCLK_OFFSET 1
+#define DWC2_PCGCCTL_PWRCLMP (1 << 2)
+#define DWC2_PCGCCTL_PWRCLMP_OFFSET 2
+#define DWC2_PCGCCTL_RSTPDWNMODULE (1 << 3)
+#define DWC2_PCGCCTL_RSTPDWNMODULE_OFFSET 3
+#define DWC2_PCGCCTL_PHYSUSPENDED (1 << 4)
+#define DWC2_PCGCCTL_PHYSUSPENDED_OFFSET 4
+#define DWC2_PCGCCTL_ENBL_SLEEP_GATING (1 << 5)
+#define DWC2_PCGCCTL_ENBL_SLEEP_GATING_OFFSET 5
+#define DWC2_PCGCCTL_PHY_IN_SLEEP (1 << 6)
+#define DWC2_PCGCCTL_PHY_IN_SLEEP_OFFSET 6
+#define DWC2_PCGCCTL_DEEP_SLEEP (1 << 7)
+#define DWC2_PCGCCTL_DEEP_SLEEP_OFFSET 7
+#define DWC2_SNPSID_DEVID_VER_2xx (0x4f542 << 12)
+#define DWC2_SNPSID_DEVID_MASK (0xfffff << 12)
+#define DWC2_SNPSID_DEVID_OFFSET 12
+
+/* Host controller specific */
+#define DWC2_HC_PID_DATA0 0
+#define DWC2_HC_PID_DATA2 1
+#define DWC2_HC_PID_DATA1 2
+#define DWC2_HC_PID_MDATA 3
+#define DWC2_HC_PID_SETUP 3
+
+/* roothub.a masks */
+#define RH_A_NDP (0xff << 0) /* number of downstream ports */
+#define RH_A_PSM (1 << 8) /* power switching mode */
+#define RH_A_NPS (1 << 9) /* no power switching */
+#define RH_A_DT (1 << 10) /* device type (mbz) */
+#define RH_A_OCPM (1 << 11) /* over current protection mode */
+#define RH_A_NOCP (1 << 12) /* no over current protection */
+#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
+
+/* roothub.b masks */
+#define RH_B_DR 0x0000ffff /* device removable flags */
+#define RH_B_PPCM 0xffff0000 /* port power control mask */
+
+/* Default driver configuration */
+#define CONFIG_DWC2_DMA_ENABLE
+#define CONFIG_DWC2_DMA_BURST_SIZE 32 /* DMA burst len */
+#undef CONFIG_DWC2_DFLT_SPEED_FULL /* Do not force DWC2 to FS */
+#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO /* Runtime FIFO size detect */
+#define CONFIG_DWC2_MAX_CHANNELS 16 /* Max # of EPs */
+#define CONFIG_DWC2_HOST_RX_FIFO_SIZE (516 + CONFIG_DWC2_MAX_CHANNELS)
+#define CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE 0x100 /* nPeriodic TX FIFO */
+#define CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE 0x200 /* Periodic TX FIFO */
+#define CONFIG_DWC2_MAX_TRANSFER_SIZE 65535
+#define CONFIG_DWC2_MAX_PACKET_COUNT 511
+
+#define DWC2_PHY_TYPE_FS 0
+#define DWC2_PHY_TYPE_UTMI 1
+#define DWC2_PHY_TYPE_ULPI 2
+#define CONFIG_DWC2_PHY_TYPE DWC2_PHY_TYPE_UTMI /* PHY type */
+#define CONFIG_DWC2_UTMI_WIDTH 8 /* UTMI bus width (8/16) */
+
+#undef CONFIG_DWC2_PHY_ULPI_DDR /* ULPI PHY uses DDR mode */
+#define CONFIG_DWC2_PHY_ULPI_EXT_VBUS /* ULPI PHY controls VBUS */
+#undef CONFIG_DWC2_I2C_ENABLE /* Enable I2C */
+#undef CONFIG_DWC2_ULPI_FS_LS /* ULPI is FS/LS */
+#undef CONFIG_DWC2_TS_DLINE /* External DLine pulsing */
+#undef CONFIG_DWC2_THR_CTL /* Threshold control */
+#define CONFIG_DWC2_TX_THR_LENGTH 64
+#undef CONFIG_DWC2_IC_USB_CAP /* IC Cap */
+
+#endif /* __DWC2_H__ */
#define ehci_is_TDI() (0)
#endif
-int __ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg)
+__weak int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg)
{
return PORTSC_PSPD(reg);
}
-int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg)
- __attribute__((weak, alias("__ehci_get_port_speed")));
-
-void __ehci_set_usbmode(int index)
+__weak void ehci_set_usbmode(int index)
{
uint32_t tmp;
uint32_t *reg_ptr;
ehci_writel(reg_ptr, tmp);
}
-void ehci_set_usbmode(int index)
- __attribute__((weak, alias("__ehci_set_usbmode")));
-
-void __ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
+__weak void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
{
mdelay(50);
}
-void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
- __attribute__((weak, alias("__ehci_powerup_fixup")));
-
static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
{
uint32_t result;
}
struct int_queue {
+ int elementsize;
struct QH *first;
struct QH *current;
struct QH *last;
struct int_queue *result = NULL;
int i;
+ /*
+ * Interrupt transfers requiring several transactions are not supported
+ * because bInterval is ignored.
+ *
+ * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
+ * <= PKT_ALIGN if several qTDs are required, while the USB
+ * specification does not constrain this for interrupt transfers. That
+ * means that ehci_submit_async() would support interrupt transfers
+ * requiring several transactions only as long as the transfer size does
+ * not require more than a single qTD.
+ */
+ if (elementsize > usb_maxpacket(dev, pipe)) {
+ printf("%s: xfers requiring several transactions are not supported.\n",
+ __func__);
+ return NULL;
+ }
+
debug("Enter create_int_queue\n");
if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
debug("ehci intr queue: out of memory\n");
goto fail1;
}
+ result->elementsize = elementsize;
result->first = memalign(USB_DMA_MINALIGN,
sizeof(struct QH) * queuesize);
if (!result->first) {
ALIGN_END_ADDR(struct qTD, result->tds,
queuesize));
- if (disable_periodic(ctrl) < 0) {
- debug("FATAL: periodic should never fail, but did");
- goto fail3;
+ if (ctrl->periodic_schedules > 0) {
+ if (disable_periodic(ctrl) < 0) {
+ debug("FATAL: periodic should never fail, but did");
+ goto fail3;
+ }
}
/* hook up to periodic list */
queue->current++;
else
queue->current = NULL;
+
+ invalidate_dcache_range((uint32_t)cur->buffer,
+ ALIGN_END_ADDR(char, cur->buffer,
+ queue->elementsize));
+
debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n",
hc32_to_cpu(cur_td->qt_token), cur, queue->first);
return cur->buffer;
debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
dev, pipe, buffer, length, interval);
- /*
- * Interrupt transfers requiring several transactions are not supported
- * because bInterval is ignored.
- *
- * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
- * <= PKT_ALIGN if several qTDs are required, while the USB
- * specification does not constrain this for interrupt transfers. That
- * means that ehci_submit_async() would support interrupt transfers
- * requiring several transactions only as long as the transfer size does
- * not require more than a single qTD.
- */
- if (length > usb_maxpacket(dev, pipe)) {
- printf("%s: Interrupt transfers requiring several "
- "transactions are not supported.\n", __func__);
- return -1;
- }
-
queue = create_int_queue(dev, pipe, 1, length, buffer);
+ if (!queue)
+ return -1;
timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
while ((backbuffer = poll_int_queue(dev, queue)) == NULL)
return -EINVAL;
}
- invalidate_dcache_range((uint32_t)buffer,
- ALIGN_END_ADDR(char, buffer, length));
-
ret = destroy_int_queue(dev, queue);
if (ret < 0)
return ret;
0xEE0A0000, /* USB1 */
0xEE0C0000, /* USB2 */
};
-#elif defined(CONFIG_R8A7791)
-static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
- 0xEE080000, /* USB0 (EHCI) */
- 0xEE0C0000, /* USB1 */
-};
-#elif defined(CONFIG_R8A7794)
+#elif defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
+ defined(CONFIG_R8A7794)
static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
0xEE080000, /* USB0 (EHCI) */
0xEE0C0000, /* USB1 */
usb_phy_write(sunxi_ehci, 0x20, 0x14, 5);
/* threshold adjustment disconnect */
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
usb_phy_write(sunxi_ehci, 0x2a, 3, 2);
#else
usb_phy_write(sunxi_ehci, 0x2a, 2, 2);
{
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct sunxi_ehci_hcd *sunxi_ehci = &sunxi_echi_hcd[index];
+ int err;
/* enable common PHY only once */
if (index == 0)
setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
+ err = gpio_request(sunxi_ehci->gpio_vbus, "ehci_vbus");
+ if (err)
+ return err;
+
sunxi_ehci_enable(sunxi_ehci);
*hccr = get_io_base(sunxi_ehci->id);
{
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct sunxi_ehci_hcd *sunxi_ehci = &sunxi_echi_hcd[index];
+ int err;
sunxi_ehci_disable(sunxi_ehci);
+ err = gpio_free(sunxi_ehci->gpio_vbus);
+ if (err)
+ return err;
+
/* disable common PHY only once, for the last enabled hcd */
if (enabled_hcd_count == 1)
clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
--- /dev/null
+/*
+ * USB 3.0 DRD Controller
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <usb.h>
+#include <asm/arch/psc_defs.h>
+#include <asm/io.h>
+#include <linux/usb/dwc3.h>
+#include <asm/arch/xhci-keystone.h>
+#include <asm-generic/errno.h>
+#include <linux/list.h>
+#include "xhci.h"
+
+struct kdwc3_irq_regs {
+ u32 revision; /* 0x000 */
+ u32 rsvd0[3];
+ u32 sysconfig; /* 0x010 */
+ u32 rsvd1[1];
+ u32 irq_eoi;
+ u32 rsvd2[1];
+ struct {
+ u32 raw_status;
+ u32 status;
+ u32 enable_set;
+ u32 enable_clr;
+ } irqs[16];
+};
+
+struct keystone_xhci {
+ struct xhci_hccr *hcd;
+ struct dwc3 *dwc3_reg;
+ struct xhci_hcor *hcor;
+ struct kdwc3_irq_regs *usbss;
+ struct keystone_xhci_phy *phy;
+};
+
+struct keystone_xhci keystone;
+
+static void keystone_xhci_phy_set(struct keystone_xhci_phy *phy)
+{
+ u32 val;
+
+ /*
+ * VBUSVLDEXTSEL has a default value of 1 in BootCfg but shouldn't.
+ * It should always be cleared because our USB PHY has an onchip VBUS
+ * analog comparator.
+ */
+ val = readl(&phy->phy_clock);
+ /* quit selecting the vbusvldextsel by default! */
+ val &= ~USB3_PHY_OTG_VBUSVLDECTSEL;
+ writel(val, &phy->phy_clock);
+}
+
+static void keystone_xhci_phy_unset(struct keystone_xhci_phy *phy)
+{
+ u32 val;
+
+ /* Disable the PHY REFCLK clock gate */
+ val = readl(&phy->phy_clock);
+ val &= ~USB3_PHY_REF_SSP_EN;
+ writel(val, &phy->phy_clock);
+}
+
+static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
+{
+ clrsetbits_le32(&dwc3_reg->g_ctl,
+ DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
+ DWC3_GCTL_PRTCAPDIR(mode));
+}
+
+static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
+{
+ /* Before Resetting PHY, put Core in Reset */
+ setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
+
+ /* Assert USB3 PHY reset */
+ setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Assert USB2 PHY reset */
+ setbits_le32(&dwc3_reg->g_usb2phycfg[0], DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+ mdelay(100);
+
+ /* Clear USB3 PHY reset */
+ clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Clear USB2 PHY reset */
+ clrbits_le32(&dwc3_reg->g_usb2phycfg[0], DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+ /* After PHYs are stable we can take Core out of reset state */
+ clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
+}
+
+static int dwc3_core_init(struct dwc3 *dwc3_reg)
+{
+ u32 revision, val;
+ unsigned long t_rst;
+ unsigned int dwc3_hwparams1;
+
+ revision = readl(&dwc3_reg->g_snpsid);
+ /* This should read as U3 followed by revision number */
+ if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
+ puts("this is not a DesignWare USB3 DRD Core\n");
+ return -EINVAL;
+ }
+
+ /* issue device SoftReset too */
+ writel(DWC3_DCTL_CSFTRST, &dwc3_reg->d_ctl);
+
+ t_rst = get_timer(0);
+ do {
+ val = readl(&dwc3_reg->d_ctl);
+ if (!(val & DWC3_DCTL_CSFTRST))
+ break;
+ WATCHDOG_RESET();
+ } while (get_timer(t_rst) < 500);
+
+ if (val & DWC3_DCTL_CSFTRST) {
+ debug("Reset timed out\n");
+ return -2;
+ }
+
+ dwc3_core_soft_reset(dwc3_reg);
+
+ dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
+
+ val = readl(&dwc3_reg->g_ctl);
+ val &= ~DWC3_GCTL_SCALEDOWN_MASK;
+ val &= ~DWC3_GCTL_DISSCRAMBLE;
+ switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
+ case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
+ val &= ~DWC3_GCTL_DSBLCLKGTNG;
+ break;
+ default:
+ printf("No power optimization available\n");
+ }
+
+ /*
+ * WORKAROUND: DWC3 revisions <1.90a have a bug
+ * where the device can fail to connect at SuperSpeed
+ * and falls back to high-speed mode which causes
+ * the device to enter a Connect/Disconnect loop
+ */
+ if ((revision & DWC3_REVISION_MASK) < 0x190a)
+ val |= DWC3_GCTL_U2RSTECN;
+
+ writel(val, &dwc3_reg->g_ctl);
+
+ return 0;
+}
+
+static int keystone_xhci_core_init(struct dwc3 *dwc3_reg)
+{
+ int ret;
+
+ ret = dwc3_core_init(dwc3_reg);
+ if (ret) {
+ debug("failed to initialize core\n");
+ return -EINVAL;
+ }
+
+ /* We are hard-coding DWC3 core to Host Mode */
+ dwc3_set_mode(dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+
+ return 0;
+}
+
+int xhci_hcd_init(int index,
+ struct xhci_hccr **ret_hccr, struct xhci_hcor **ret_hcor)
+{
+ u32 val;
+ int ret;
+ struct xhci_hccr *hcd;
+ struct xhci_hcor *hcor;
+ struct kdwc3_irq_regs *usbss;
+ struct keystone_xhci_phy *phy;
+
+ usbss = (struct kdwc3_irq_regs *)CONFIG_USB_SS_BASE;
+ phy = (struct keystone_xhci_phy *)CONFIG_DEV_USB_PHY_BASE;
+
+ /* Enable the PHY REFCLK clock gate with phy_ref_ssp_en = 1 */
+ val = readl(&(phy->phy_clock));
+ val |= USB3_PHY_REF_SSP_EN;
+ writel(val, &phy->phy_clock);
+
+ mdelay(100);
+
+ /* Release USB from reset */
+ ret = psc_enable_module(KS2_LPSC_USB);
+ if (ret) {
+ puts("Cannot enable USB module");
+ return -1;
+ }
+
+ mdelay(100);
+
+ /* Initialize usb phy */
+ keystone_xhci_phy_set(phy);
+
+ /* soft reset usbss */
+ writel(1, &usbss->sysconfig);
+ while (readl(&usbss->sysconfig) & 1)
+ ;
+
+ val = readl(&usbss->revision);
+ debug("usbss revision %x\n", val);
+
+ /* Initialize usb core */
+ hcd = (struct xhci_hccr *)CONFIG_USB_HOST_XHCI_BASE;
+ keystone.dwc3_reg = (struct dwc3 *)(CONFIG_USB_HOST_XHCI_BASE +
+ DWC3_REG_OFFSET);
+
+ keystone_xhci_core_init(keystone.dwc3_reg);
+
+ /* set register addresses */
+ hcor = (struct xhci_hcor *)((uint32_t)hcd +
+ HC_LENGTH(readl(&hcd->cr_capbase)));
+
+ debug("Keystone2-xhci: init hccr %08x and hcor %08x hc_length %d\n",
+ (u32)hcd, (u32)hcor,
+ (u32)HC_LENGTH(xhci_readl(&hcd->cr_capbase)));
+
+ keystone.usbss = usbss;
+ keystone.phy = phy;
+ keystone.hcd = hcd;
+ keystone.hcor = hcor;
+
+ *ret_hccr = hcd;
+ *ret_hcor = hcor;
+
+ return 0;
+}
+
+static int keystone_xhci_phy_suspend(void)
+{
+ int loop_cnt = 0;
+ struct xhci_hcor *hcor;
+ uint32_t *portsc_1 = NULL;
+ uint32_t *portsc_2 = NULL;
+ u32 val, usb2_pls, usb3_pls, event_q;
+ struct dwc3 *dwc3_reg = keystone.dwc3_reg;
+
+ /* set register addresses */
+ hcor = keystone.hcor;
+
+ /* Bypass Scrambling and Set Shorter Training sequence for simulation */
+ val = DWC3_GCTL_PWRDNSCALE(0x4b0) | DWC3_GCTL_PRTCAPDIR(0x2);
+ writel(val, &dwc3_reg->g_ctl);
+
+ /* GUSB2PHYCFG */
+ val = readl(&dwc3_reg->g_usb2phycfg[0]);
+
+ /* assert bit 6 (SusPhy) */
+ val |= DWC3_GUSB2PHYCFG_SUSPHY;
+ writel(val, &dwc3_reg->g_usb2phycfg[0]);
+
+ /* GUSB3PIPECTL */
+ val = readl(&dwc3_reg->g_usb3pipectl[0]);
+
+ /*
+ * assert bit 29 to allow PHY to go to suspend when idle
+ * and cause the USB3 SS PHY to enter suspend mode
+ */
+ val |= (BIT(29) | DWC3_GUSB3PIPECTL_SUSPHY);
+ writel(val, &dwc3_reg->g_usb3pipectl[0]);
+
+ /*
+ * Steps necessary to allow controller to suspend even when
+ * VBUS is HIGH:
+ * - Init DCFG[2:0] (DevSpd) to: 1=FS
+ * - Init GEVNTADR0 to point to an eventQ
+ * - Init GEVNTSIZ0 to 0x0100 to specify the size of the eventQ
+ * - Init DCTL::Run_nStop = 1
+ */
+ writel(0x00020001, &dwc3_reg->d_cfg);
+ /* TODO: local2global( (Uint32) eventQ )? */
+ writel((u32)&event_q, &dwc3_reg->g_evnt_buf[0].g_evntadrlo);
+ writel(0, &dwc3_reg->g_evnt_buf[0].g_evntadrhi);
+ writel(0x4, &dwc3_reg->g_evnt_buf[0].g_evntsiz);
+ /* Run */
+ writel(DWC3_DCTL_RUN_STOP, &dwc3_reg->d_ctl);
+
+ mdelay(100);
+
+ /* Wait for USB2 & USB3 PORTSC::PortLinkState to indicate suspend */
+ portsc_1 = (uint32_t *)(&hcor->portregs[0].or_portsc);
+ portsc_2 = (uint32_t *)(&hcor->portregs[1].or_portsc);
+ usb2_pls = 0;
+ usb3_pls = 0;
+ do {
+ ++loop_cnt;
+ usb2_pls = (readl(portsc_1) & PORT_PLS_MASK) >> 5;
+ usb3_pls = (readl(portsc_2) & PORT_PLS_MASK) >> 5;
+ } while (((usb2_pls != 0x4) || (usb3_pls != 0x4)) && loop_cnt < 1000);
+
+ if (usb2_pls != 0x4 || usb3_pls != 0x4) {
+ debug("USB suspend failed - PLS USB2=%02x, USB3=%02x\n",
+ usb2_pls, usb3_pls);
+ return -1;
+ }
+
+ debug("USB2 and USB3 PLS - Disabled, loop_cnt=%d\n", loop_cnt);
+ return 0;
+}
+
+void xhci_hcd_stop(int index)
+{
+ /* Disable USB */
+ if (keystone_xhci_phy_suspend())
+ return;
+
+ if (psc_disable_module(KS2_LPSC_USB)) {
+ debug("PSC disable module USB failed!\n");
+ return;
+ }
+
+ /* Disable PHY */
+ keystone_xhci_phy_unset(keystone.phy);
+
+/* memset(&keystone, 0, sizeof(struct keystone_xhci)); */
+ debug("xhci_hcd_stop OK.\n");
+}
CURSOR_SET;
}
-void video_putc(struct stdio_dev *dev, const char c)
+static void video_putc(struct stdio_dev *dev, const char c)
{
#ifdef CONFIG_CFB_CONSOLE_ANSI
int i;
flush_cache(VIDEO_FB_ADRS, VIDEO_SIZE);
}
-void video_puts(struct stdio_dev *dev, const char *s)
+static void video_puts(struct stdio_dev *dev, const char *s)
{
int count = strlen(s);
* video_set_lut() if they do not support 8 bpp format.
* Implement weak default function instead.
*/
-void __video_set_lut(unsigned int index, unsigned char r,
+__weak void video_set_lut(unsigned int index, unsigned char r,
unsigned char g, unsigned char b)
{
}
-void video_set_lut(unsigned int, unsigned char, unsigned char, unsigned char)
- __attribute__ ((weak, alias("__video_set_lut")));
-
#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN)
#define FILL_8BIT_332RGB(r,g,b) { \
* Implement a weak default function for boards that optionally
* need to skip the video initialization.
*/
-int __board_video_skip(void)
+__weak int board_video_skip(void)
{
/* As default, don't skip test */
return 0;
}
-int board_video_skip(void)
- __attribute__ ((weak, alias("__board_video_skip")));
-
int drv_video_init(void)
{
int skip_dev_init;
lcd_set_flush_dcache(1);
}
-void __exynos_cfg_lcd_gpio(void)
+__weak void exynos_cfg_lcd_gpio(void)
{
}
-void exynos_cfg_lcd_gpio(void)
- __attribute__((weak, alias("__exynos_cfg_lcd_gpio")));
-void __exynos_backlight_on(unsigned int onoff)
+__weak void exynos_backlight_on(unsigned int onoff)
{
}
-void exynos_backlight_on(unsigned int onoff)
- __attribute__((weak, alias("__exynos_cfg_lcd_gpio")));
-void __exynos_reset_lcd(void)
+__weak void exynos_reset_lcd(void)
{
}
-void exynos_reset_lcd(void)
- __attribute__((weak, alias("__exynos_reset_lcd")));
-void __exynos_lcd_power_on(void)
+__weak void exynos_lcd_power_on(void)
{
}
-void exynos_lcd_power_on(void)
- __attribute__((weak, alias("__exynos_lcd_power_on")));
-void __exynos_cfg_ldo(void)
+__weak void exynos_cfg_ldo(void)
{
}
-void exynos_cfg_ldo(void)
- __attribute__((weak, alias("__exynos_cfg_ldo")));
-void __exynos_enable_ldo(unsigned int onoff)
+__weak void exynos_enable_ldo(unsigned int onoff)
{
}
-void exynos_enable_ldo(unsigned int onoff)
- __attribute__((weak, alias("__exynos_enable_ldo")));
-void __exynos_backlight_reset(void)
+__weak void exynos_backlight_reset(void)
{
}
-void exynos_backlight_reset(void)
- __attribute__((weak, alias("__exynos_backlight_reset")));
-int __exynos_lcd_misc_init(vidinfo_t *vid)
+__weak int exynos_lcd_misc_init(vidinfo_t *vid)
{
return 0;
}
-int exynos_lcd_misc_init(vidinfo_t *vid)
- __attribute__((weak, alias("__exynos_lcd_misc_init")));
static void lcd_panel_on(vidinfo_t *vid)
{
/*
* This function resets IPU
*/
-void ipu_reset(void)
+static void ipu_reset(void)
{
u32 *reg;
u32 value;
static enum csc_type_t fg_csc_type = CSC_NONE, bg_csc_type = CSC_NONE;
static int color_key_4rgb = 1;
-void ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param,
+static void ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param,
unsigned char srm_mode_update)
{
u32 reg;
}
}
-int ipu_chan_is_interlaced(ipu_channel_t channel)
-{
- if (channel == MEM_DC_SYNC)
- return !!(__raw_readl(DC_WR_CH_CONF_1) &
- DC_WR_CH_CONF_FIELD_MODE);
- else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))
- return !!(__raw_readl(DC_WR_CH_CONF_5) &
- DC_WR_CH_CONF_FIELD_MODE);
- return 0;
-}
-
void ipu_dp_dc_enable(ipu_channel_t channel)
{
int di;
ipu_dc_map_config(4, 2, 21, 0xFC);
}
-int ipu_pixfmt_to_map(uint32_t fmt)
+static int ipu_pixfmt_to_map(uint32_t fmt)
{
switch (fmt) {
case IPU_PIX_FMT_GENERIC:
static uint8_t gdisp;
static uint32_t gpixfmt;
-void fb_videomode_to_var(struct fb_var_screeninfo *var,
+static void fb_videomode_to_var(struct fb_var_screeninfo *var,
const struct fb_videomode *mode)
{
var->xres = mode->xres;
string "Default Device Tree for DT control"
help
This option specifies the default Device Tree used for DT control.
- It can be overrided from the command line:
+ It can be overridden from the command line:
$ make DEVICE_TREE=<device-tree-name>
endmenu
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_FAT_SUPPORT) += fat/
+obj-$(CONFIG_SPL_EXT_SUPPORT) += ext4/
else
obj-y += fs.o
#include <common.h>
#include <ext_common.h>
#include <ext4fs.h>
+#include <inttypes.h>
#include <malloc.h>
#include <stddef.h>
#include <linux/stat.h>
if ((startblock + (size >> log2blksz)) >
(part_offset + fs->total_sect)) {
printf("part_offset is " LBAFU "\n", part_offset);
- printf("total_sector is %llu\n", fs->total_sect);
+ printf("total_sector is %" PRIu64 "\n", fs->total_sect);
printf("error: overflow occurs\n");
return;
}
uint64_t crc = salt;
if (table[128] == 0) {
- uint64_t *ct;
+ uint64_t *ct = NULL;
int i, j;
for (i = 0; i < 256; i++) {
for (ct = table + i, *ct = i, j = 8; j > 0; j--)
}
printf("unknown ZAP type\n");
+ free(zapbuf);
return ZFS_ERR_BAD_FS;
}
return ret;
}
printf("unknown ZAP type\n");
+ free(zapbuf);
return 0;
}
ubbest = malloc(sizeof(*ubbest));
if (!ubbest) {
+ free(ub_array);
zfs_unmount(data);
return 0;
}
if (err) {
printf("couldn't zio_read object directory\n");
zfs_unmount(data);
+ free(osp);
free(ubbest);
return 0;
}
hdrsize = SA_HDR_SIZE(((sa_hdr_phys_t *) sahdrp));
file->size = *(uint64_t *) ((char *) sahdrp + hdrsize + SA_SIZE_OFFSET);
+ if ((data->dnode.dn.dn_bonuslen == 0) &&
+ (data->dnode.dn.dn_flags & DNODE_FLAG_SPILL_BLKPTR))
+ free(sahdrp);
} else {
file->size = zfs_to_cpu64(((znode_phys_t *) DN_BONUS(&data->dnode.dn))->zp_size, data->dnode.endian);
}
* Request a GPIO. This should be called before any of the other functions
* are used on this GPIO.
*
+ * Note: With driver model, the label is allocated so there is no need for
+ * the caller to preserve it.
+ *
* @param gp GPIO number
* @param label User label for this GPIO
* @return 0 if ok, -1 on error
int gpio_set_value(unsigned gpio, int value);
/* State of a GPIO, as reported by get_function() */
-enum {
+enum gpio_func_t {
GPIOF_INPUT = 0,
GPIOF_OUTPUT,
GPIOF_UNUSED, /* Not claimed */
struct udevice;
+/**
+ * gpio_get_status() - get the current GPIO status as a string
+ *
+ * Obtain the current GPIO status as a string which can be presented to the
+ * user. A typical string is:
+ *
+ * "b4: in: 1 [x] sdmmc_cd"
+ *
+ * which means this is GPIO bank b, offset 4, currently set to input, current
+ * value 1, [x] means that it is requested and the owner is 'sdmmc_cd'
+ *
+ * @dev: Device to check
+ * @offset: Offset of device GPIO to check
+ * @buf: Place to put string
+ * @buffsize: Size of string including \0
+ */
+int gpio_get_status(struct udevice *dev, int offset, char *buf, int buffsize);
+
+/**
+ * gpio_get_function() - get the current function for a GPIO pin
+ *
+ * Note this returns GPIOF_UNUSED if the GPIO is not requested.
+ *
+ * @dev: Device to check
+ * @offset: Offset of device GPIO to check
+ * @namep: If non-NULL, this is set to the nane given when the GPIO
+ * was requested, or -1 if it has not been requested
+ * @return -ENODATA if the driver returned an unknown function,
+ * -ENODEV if the device is not active, -EINVAL if the offset is invalid.
+ * GPIOF_UNUSED if the GPIO has not been requested. Otherwise returns the
+ * function from enum gpio_func_t.
+ */
+int gpio_get_function(struct udevice *dev, int offset, const char **namep);
+
+/**
+ * gpio_get_raw_function() - get the current raw function for a GPIO pin
+ *
+ * Note this does not return GPIOF_UNUSED - it will always return the GPIO
+ * driver's view of a pin function, even if it is not correctly set up.
+ *
+ * @dev: Device to check
+ * @offset: Offset of device GPIO to check
+ * @namep: If non-NULL, this is set to the nane given when the GPIO
+ * was requested, or -1 if it has not been requested
+ * @return -ENODATA if the driver returned an unknown function,
+ * -ENODEV if the device is not active, -EINVAL if the offset is invalid.
+ * Otherwise returns the function from enum gpio_func_t.
+ */
+int gpio_get_raw_function(struct udevice *dev, int offset, const char **namep);
+
+/**
+ * gpio_requestf() - request a GPIO using a format string for the owner
+ *
+ * This is a helper function for gpio_request(). It allows you to provide
+ * a printf()-format string for the GPIO owner. It calls gpio_request() with
+ * the string that is created
+ */
+int gpio_requestf(unsigned gpio, const char *fmt, ...)
+ __attribute__ ((format (__printf__, 2, 3)));
+
/**
* struct struct dm_gpio_ops - Driver model GPIO operations
*
* @return current function - GPIOF_...
*/
int (*get_function)(struct udevice *dev, unsigned offset);
- int (*get_state)(struct udevice *dev, unsigned offset, char *state,
- int maxlen);
};
/**
* @gpio_base: Base GPIO number for this device. For the first active device
* this will be 0; the numbering for others will follow sequentially so that
* @gpio_base for device 1 will equal the number of GPIOs in device 0.
+ * @name: Array of pointers to the name for each GPIO in this bank. The
+ * value of the pointer will be NULL if the GPIO has not been claimed.
*/
struct gpio_dev_priv {
const char *bank_name;
unsigned gpio_count;
unsigned gpio_base;
+ char **name;
};
/* Access the GPIO operations for a device */
int gpio_lookup_name(const char *name, struct udevice **devp,
unsigned int *offsetp, unsigned int *gpiop);
+int name_to_gpio(const char *name);
+
#endif /* _ASM_GENERIC_GPIO_H_ */
unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
#endif
-#if defined(CONFIG_HYMOD)
- hymod_conf_t bi_hymod_conf; /* hymod configuration information */
-#endif
#ifdef CONFIG_HAS_ETH1
unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */
int do_bootm_states(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
int states, bootm_headers_t *images, int boot_progress);
+void arch_preboot_os(void);
+
#endif
#define FLAG_EXIT_FROM_LOOP 1
#define FLAG_PARSE_SEMICOLON (1 << 1) /* symbol ';' is special for parser */
#define FLAG_REPARSING (1 << 2) /* >=2nd pass */
+#define FLAG_CONT_ON_NEWLINE (1 << 3) /* continue when we see \n */
extern int u_boot_hush_start(void);
extern int parse_string_outer(const char *, int);
*/
#define CMD_FLAG_REPEAT 0x0001 /* repeat last command */
#define CMD_FLAG_BOOTD 0x0002 /* command is from bootd */
+#define CMD_FLAG_ENV 0x0004 /* command is from the environment */
#ifdef CONFIG_AUTO_COMPLETE
# define _CMD_COMPLETE(x) x,
#ifdef CONFIG_4xx
#include <asm/ppc4xx.h>
#endif
-#ifdef CONFIG_HYMOD
-#include <board/hymod/hymod.h>
-#endif
#ifdef CONFIG_ARM
#define asmlinkage /* nothing */
#endif
#include <flash.h>
#include <image.h>
+/* Bring in printf format macros if inttypes.h is included */
+#define __STDC_FORMAT_MACROS
+
#ifdef __LP64__
#define CONFIG_SYS_SUPPORT_64BIT_DATA
#endif
/* */
phys_size_t initdram (int);
int display_options (void);
-void print_size(unsigned long long, const char *);
+
+/**
+ * print_size() - Print a size with a suffic
+ *
+ * print sizes as "xxx KiB", "xxx.y KiB", "xxx MiB", "xxx.y MiB",
+ * xxx GiB, xxx.y GiB, etc as needed; allow for optional trailing string
+ * (like "\n")
+ *
+ * @size: Size to print
+ * @suffix String to print after the size
+ */
+void print_size(uint64_t size, const char *suffix);
+
int print_buffer(ulong addr, const void *data, uint width, uint count,
uint linelen);
int serial_stub_getc(struct stdio_dev *sdev);
int serial_stub_tstc(struct stdio_dev *sdev);
-void _serial_setbrg (const int);
-void _serial_putc (const char, const int);
-void _serial_putc_raw(const char, const int);
-void _serial_puts (const char *, const int);
-int _serial_getc (const int);
-int _serial_tstc (const int);
-
/* $(CPU)/speed.c */
int get_clocks (void);
int get_clocks_866 (void);
void invalidate_icache_all(void);
/* arch/$(ARCH)/lib/ticks.S */
-unsigned long long get_ticks(void);
+uint64_t get_ticks(void);
void wait_ticks (unsigned long);
/* arch/$(ARCH)/lib/time.c */
#endif /* CONFIG_HERMES */
-/*** ICU862 **********************************************************/
-
-#if defined(CONFIG_ICU862)
-
-#ifdef CONFIG_FEC_ENET
-#define FEC_ENET /* use FEC for EThernet */
-#endif /* CONFIG_FEC_ETHERNET */
-
-#endif /* CONFIG_ICU862 */
-
/*** IP860 **********************************************************/
#if defined(CONFIG_IP860)
#define SICR_ENET_CLKRT ((uint)0x00250000)
#endif /* CONFIG_KM8XX */
-
-/*** MHPC ********************************************************/
-
-#if defined(CONFIG_MHPC)
-/* This ENET stuff is for the MHPC with ethernet on SCC2.
- * Note TENA is on Port B.
- */
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
-#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
-#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
-#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
-#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
-#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
-#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
-
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00002e00) /* RCLK-CLK2, TCLK-CLK3 */
-#endif /* CONFIG_MHPC */
-
/*** NETVIA *******************************************************/
#if defined(CONFIG_NETVIA)
#else /* !USE_HOSTCC */
+#ifdef CONFIG_USE_STDINT
+/* Provided by gcc. */
+#include <stdint.h>
+#else
+/* Type for `void *' pointers. */
+typedef unsigned long int uintptr_t;
+#endif
+
#include <linux/string.h>
#include <linux/types.h>
#include <asm/byteorder.h>
#define __WORDSIZE 32
#endif
-/* Type for `void *' pointers. */
-typedef unsigned long int uintptr_t;
-
#endif /* USE_HOSTCC */
#define likely(x) __builtin_expect(!!(x), 1)
/*
* List of all commands and options that when defined enables support for
* features required by distros to support boards in a standardised and
- * consitant manner.
+ * consistent manner.
*/
#define CONFIG_BOOTP_BOOTPATH
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-/*************************************************************************
- * (c) 2004 esd gmbh Hannover
- *
- *
- * from db64360.h file
- * by Reinhard Arlt reinhard.arlt@esd-electronics.com
- *
- ************************************************************************/
-
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* This define must be before the core.h include */
-#define CONFIG_CPCI750 1 /* this is an CPCI750 board */
-
-#ifndef __ASSEMBLY__
-#include <../board/Marvell/include/core.h>
-#endif
-/*-----------------------------------------------------*/
-
-#include "../board/esd/cpci750/local.h"
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_750FX /* we have a 750FX (override local.h) */
-
-#define CONFIG_CPCI750 1 /* this is an CPCI750 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
-#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */
-
-#define CONFIG_MV64360_ECC /* enable ECC support */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* which initialization functions to call for this board */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_BOARD_PRE_INIT
-#define CONFIG_BOARD_EARLY_INIT_F 1
-
-#define CONFIG_SYS_BOARD_NAME "CPCI750"
-#define CONFIG_IDENT_STRING "Marvell 64360 + IBM750FX"
-
-/*#define CONFIG_SYS_HUSH_PARSER*/
-#define CONFIG_SYS_HUSH_PARSER
-
-
-#define CONFIG_CMDLINE_EDITING /* add command line history */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-
-/* Define which ETH port will be used for connecting the network */
-#define CONFIG_SYS_ETH_PORT ETH_0
-
-/*
- * The following defines let you select what serial you want to use
- * for your console driver.
- *
- * what to do:
- * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
- * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
- * to 0 below.
- *
- * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
- * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
- */
-#define CONFIG_MPSC
-#define CONFIG_MPSC_PORT 0
-
-/* to change the default ethernet port, use this define (options: 0, 1, 2) */
-#define MV_ETH_DEVS 1
-#define CONFIG_ETHER_PORT 0
-
-#undef CONFIG_ETHER_PORT_MII /* use RMII */
-
-#define CONFIG_BOOTDELAY 5 /* autoboot disabled */
-
-#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-
-#undef CONFIG_BOOTARGS
-
-/* -----------------------------------------------------------------------------
- * New bootcommands for Marvell CPCI750 c 2002 Ingo Assmus
- */
-
-#define CONFIG_IPADDR "192.168.0.185"
-
-#define CONFIG_SERIAL "AA000001"
-#define CONFIG_SERVERIP "10.0.0.79"
-#define CONFIG_ROOTPATH "/export/nfs_cpci750/%s"
-
-#define CONFIG_TESTDRAMDATA y
-#define CONFIG_TESTDRAMADDRESS n
-#define CONFIG_TESETDRAMWALK n
-
-/* ----------------------------------------------------------------------------- */
-
-
-#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-#undef CONFIG_ALTIVEC /* undef to disable */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-
-
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_USE_CPCIDVI
-
-#ifdef CONFIG_USE_CPCIDVI
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_CT69000
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_I8042_KBD
-#define CONFIG_SYS_ISA_IO 0
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed default */
-
-#define CONFIG_PRAM 0
-
-#define CONFIG_SYS_GT_DUAL_CPU /* also for JTAG even with one cpu */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-/*#define CONFIG_SYS_MEMTEST_START 0x00400000*/ /* memtest works on */
-/*#define CONFIG_SYS_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */
-/*#define CONFIG_SYS_MEMTEST_END 0x07c00000*/ /* 4 ... 124 MB in DRAM */
-
-/*
-#define CONFIG_SYS_DRAM_TEST
- * DRAM tests
- * CONFIG_SYS_DRAM_TEST - enables the following tests.
- *
- * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
- * Environment variable 'test_dram_data' must be
- * set to 'y'.
- * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
- * addressable. Environment variable
- * 'test_dram_address' must be set to 'y'.
- * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
- * This test takes about 6 minutes to test 64 MB.
- * Environment variable 'test_dram_walk' must be
- * set to 'y'.
- */
-#define CONFIG_SYS_DRAM_TEST
-#if defined(CONFIG_SYS_DRAM_TEST)
-#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
-/*#define CONFIG_SYS_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */
-#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
-#define CONFIG_SYS_DRAM_TEST_DATA
-#define CONFIG_SYS_DRAM_TEST_ADDRESS
-#define CONFIG_SYS_DRAM_TEST_WALK
-#endif /* CONFIG_SYS_DRAM_TEST */
-
-#define CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */
-#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */
-
-#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_SYS_TCLK 133000000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
- /*
- * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
- * To an unused memory region. The stack will remain in cache until RAM
- * is initialized
-*/
-#undef CONFIG_SYS_INIT_RAM_LOCK
-/* #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000*/ /* unused memory region */
-/* #define CONFIG_SYS_INIT_RAM_ADDR 0xfba00000*/ /* unused memory region */
-#define CONFIG_SYS_INIT_RAM_ADDR 0xf1080000 /* unused memory region */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#define RELOCATE_INTERNAL_RAM_ADDR
-#ifdef RELOCATE_INTERNAL_RAM_ADDR
-/*#define CONFIG_SYS_INTERNAL_RAM_ADDR 0xfba00000*/
-#define CONFIG_SYS_INTERNAL_RAM_ADDR 0xf1080000
-#endif
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-/* Dummies for BAT 4-7 */
-#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */
-#define CONFIG_SYS_SDRAM2_BASE 0x20000000
-#define CONFIG_SYS_SDRAM3_BASE 0x30000000
-#define CONFIG_SYS_SDRAM4_BASE 0x40000000
-#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE 0xfff00000
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of flash banks */
-#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */
-#define CONFIG_SYS_FLASH_INCREMENT 0x01000000 /* size of flash bank */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
- CONFIG_SYS_FLASH_BASE + 1*CONFIG_SYS_FLASH_INCREMENT, \
- CONFIG_SYS_FLASH_BASE + 2*CONFIG_SYS_FLASH_INCREMENT, \
- CONFIG_SYS_FLASH_BASE + 3*CONFIG_SYS_FLASH_INCREMENT }
-#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* show if bank is empty */
-
-/* areas to map different things with the GT in physical space */
-#define CONFIG_SYS_DRAM_BANKS 4
-
-/* What to put in the bats. */
-#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
-
-/* Peripheral Device section */
-
-/*******************************************************/
-/* We have on the cpci750 Board : */
-/* GT-Chipset Register Area */
-/* GT-Chipset internal SRAM 256k */
-/* SRAM on external device module */
-/* Real time clock on external device module */
-/* dobble UART on external device module */
-/* Data flash on external device module */
-/* Boot flash on external device module */
-/*******************************************************/
-#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
-#define CONFIG_SYS_CPCI750_RESET_ADDR 0x14000000 /* After power on Reset the CPCI750 is here */
-
-#undef MARVEL_STANDARD_CFG
-#ifndef MARVEL_STANDARD_CFG
-/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */
-/*#define CONFIG_SYS_DEV_BASE 0xfc000000*/ /* GT Devices CS start here */
-#define CONFIG_SYS_INT_SRAM_BASE 0xf1080000 /* GT offers 256k internal fast SRAM */
-
-#define CONFIG_SYS_BOOT_SPACE 0xff000000 /* BOOT_CS0 flash 0 */
-#define CONFIG_SYS_DEV0_SPACE 0xfc000000 /* DEV_CS0 flash 1 */
-#define CONFIG_SYS_DEV1_SPACE 0xfd000000 /* DEV_CS1 flash 2 */
-#define CONFIG_SYS_DEV2_SPACE 0xfe000000 /* DEV_CS2 flash 3 */
-#define CONFIG_SYS_DEV3_SPACE 0xf0000000 /* DEV_CS3 nvram/can */
-
-#define CONFIG_SYS_BOOT_SIZE _16M /* cpci750 flash 0 */
-#define CONFIG_SYS_DEV0_SIZE _16M /* cpci750 flash 1 */
-#define CONFIG_SYS_DEV1_SIZE _16M /* cpci750 flash 2 */
-#define CONFIG_SYS_DEV2_SIZE _16M /* cpci750 flash 3 */
-#define CONFIG_SYS_DEV3_SIZE _16M /* cpci750 nvram/can */
-
-/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-#endif
-
-/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
-#define CONFIG_SYS_DEV0_PAR 0x8FDFFFFF /* 16 bit flash */
-#define CONFIG_SYS_DEV1_PAR 0x8FDFFFFF /* 16 bit flash */
-#define CONFIG_SYS_DEV2_PAR 0x8FDFFFFF /* 16 bit flash */
-#define CONFIG_SYS_DEV3_PAR 0x8FCFFFFF /* nvram/can */
-#define CONFIG_SYS_BOOT_PAR 0x8FDFFFFF /* 16 bit flash */
-
- /* c 4 a 8 2 4 1 c */
- /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
- /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
- /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */
- /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */
-
-
-/* MPP Control MV64360 Appendix P P. 632*/
-#define CONFIG_SYS_MPP_CONTROL_0 0x00002222 /* */
-#define CONFIG_SYS_MPP_CONTROL_1 0x11110000 /* */
-#define CONFIG_SYS_MPP_CONTROL_2 0x11111111 /* */
-#define CONFIG_SYS_MPP_CONTROL_3 0x00001111 /* */
-/* #define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102*/ /* */
-
-
-#define CONFIG_SYS_GPP_LEVEL_CONTROL 0xffffffff /* 1111 1111 1111 1111 1111 1111 1111 1111*/
-
-/* setup new config_value for MV64360 DDR-RAM To_do !! */
-/*# define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200*/ /* 0x448 */
-/*# define CONFIG_SYS_SDRAM_CONFIG 0xd8e14400*/ /* 0x1400 */
- /* GB has high prio.
- idma has low prio
- MPSC has low prio
- pci has low prio 1 and 2
- cpu has high prio
- Data DQS pins == eight (DQS[7:0] foe x8 and x16 devices
- ECC disable
- non registered DRAM */
- /* 31:26 25:22 21:20 19 18 17 16 */
- /* 100001 0000 010 0 0 0 0 */
- /* refresh_count=0x400
- phisical interleaving disable
- virtual interleaving enable */
- /* 15 14 13:0 */
- /* 0 1 0x400 */
-# define CONFIG_SYS_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-
-#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */
-
-/* PCI MEMORY MAP section */
-#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI0_MEM_SIZE _128M
-#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
-#define CONFIG_SYS_PCI1_MEM_SIZE _128M
-
-#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
-#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
-
-/* PCI I/O MAP section */
-#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
-#define CONFIG_SYS_PCI0_IO_SIZE _16M
-#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
-#define CONFIG_SYS_PCI1_IO_SIZE _16M
-
-#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
-#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000
-#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
-#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000
-
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE)
-
-#if defined (CONFIG_750CX)
-#define CONFIG_SYS_PCI_IDSEL 0x0
-#else
-#define CONFIG_SYS_PCI_IDSEL 0x30
-#endif
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#define CONFIG_IDE_RESET /* no reset for ide supported */
-#define CONFIG_IDE_PREINIT /* check for units */
-
-#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 1 IDE busses */
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0
-#define CONFIG_SYS_ATA_IDE1_OFFSET 0
-
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
-#ifndef __ASSEMBLY__
-int ata_device(int dev);
-#endif
-#define ATA_DEVICE(dev) ata_device(dev)
-#define CONFIG_ATAPI 1
-
-/*----------------------------------------------------------------------
- * Initial BAT mappings
- */
-
-/* NOTES:
- * 1) GUARDED and WRITE_THRU not allowed in IBATS
- * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
- */
-
-/* SDRAM */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* init ram */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* PCI0, PCI1 in one BAT */
-#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* GT regs, bootrom, all the devices, PCI I/O */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
- * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7)
- * IBAT4 and DBAT4
- * FIXME: ingo disable BATs for Linux Kernel
- */
-/* #undef SETUP_HIGH_BATS_FX750 */ /* don't initialize BATS 4-7 */
-#define SETUP_HIGH_BATS_FX750 /* initialize BATS 4-7 */
-
-#ifdef SETUP_HIGH_BATS_FX750
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/* IBAT5 and DBAT5 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-/* IBAT6 and DBAT6 */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-
-/* IBAT7 and DBAT7 */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
-#else /* set em out of range for Linux !!!!!!!!!!! */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/* IBAT5 and DBAT5 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT4U
-
-/* IBAT6 and DBAT6 */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT4U
-
-/* IBAT7 and DBAT7 */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT4U
-
-#endif
-/* FIXME: ingo end: disable BATs for Linux Kernel */
-
-/* I2C addresses for the two DIMM SPD chips */
-#define DIMM0_I2C_ADDR 0x51
-#define DIMM1_I2C_ADDR 0x52
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_BOOT_FLASH_WIDTH 2 /* 16 bit */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */
-
-#if 0
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
-/* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
-#endif
-
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x050
-#define CONFIG_ENV_OFFSET 0x200 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x600 /* 2048 bytes may be used for env vars*/
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
-#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-0x40)
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * L2CR setup -- make sure this is right for your board!
- * look in include/mpc74xx.h for the defines used here
- */
-
-/*#define CONFIG_SYS_L2*/
-#undef CONFIG_SYS_L2
-
-/* #ifdef CONFIG_750CX*/
-#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
-#define L2_INIT 0
-#else
-#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
- L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
-#endif
-
-#define L2_ENABLE (L2_INIT | L2CR_L2E)
-
-#define CONFIG_SYS_BOARD_ASM_INIT 1
-
-#define CPCI750_SLAVE_TEST (((in8(0xf0300000) & 0x80) == 0) ? 0 : 1)
-#define CPCI750_ECC_TEST (((in8(0xf0300000) & 0x02) == 0) ? 1 : 0)
-#define CONFIG_SYS_PLD_VER 0xf0e00000
-
-#define CONFIG_OF_LIBFDT 1
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-/*************************************************************************
- * (c) 2002 Datentechnik AG - Project: Dino
- *
- *
- * $Id: DB64360.h,v 1.3 2003/04/26 04:58:13 brad Exp $
- *
- ************************************************************************/
-
-/*************************************************************************
- *
- * History:
- *
- * $Log: DB64360.h,v $
- * Revision 1.3 2003/04/26 04:58:13 brad
- * Cosmetic changes and compiler warning cleanups
- *
- * Revision 1.2 2003/04/23 15:48:15 ingo
- * mem. map output added
- *
- * Revision 1.1 2003/04/17 09:31:42 ias
- * keymile changes 17_04_2003
- *
- * Revision 1.10 2003/03/06 12:25:04 ias
- * 750 FX CPU HID settings updated
- *
- * Revision 1.9 2003/03/03 16:14:36 ias
- * cleanup compiler warnings of printf fuctions
- *
- * Revision 1.8 2003/03/03 15:11:44 ias
- * Marvell MPSC-UART is working
- *
- * Revision 1.7 2003/02/26 12:15:45 ssu
- * adapted default parameters to new board flash address
- *
- * Revision 1.6 2003/02/25 14:55:42 ssu
- * changed default environment parameters
- *
- * Revision 1.5 2003/02/21 17:14:23 ias
- * added extended SPD handling
- *
- * Revision 1.4 2003/01/14 09:16:08 ias
- * PPCBoot for Marvel Beta 0.9
- *
- * Revision 1.3 2002/12/03 13:56:26 ias
- * Environment in flash support added
- *
- * Revision 1.2 2002/11/29 16:53:29 ias
- * Flash support for STM added
- *
- * Revision 1.1 2002/11/29 13:36:31 ias
- * Revision 0.1 of PPCBOOT (1.1.5) for Marvell DB64360 IBM750FX Board
- * - working DDRRAM (only 32MByte of 128MB Modul)
- * - working I2C Driver for SPD EEPROM read
- * - working DUART 16650 for Serial Console
- * - working "console"
- *
- *
- *
- ************************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* This define must be before the core.h include */
-#define CONFIG_DB64360 1 /* this is an DB64360 board */
-
-#ifndef __ASSEMBLY__
-#include "../board/Marvell/include/core.h"
-#endif
-
-/*-----------------------------------------------------*/
-/* #include "../board/db64360/local.h" */
-#ifndef __LOCAL_H
-#define __LOCAL_H
-
-/* first ethernet */
-#define CONFIG_ETHADDR 64:36:00:00:00:01
- /* next two ethernet hwaddrs */
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 64:36:00:00:00:02
-/* in the atlantis 64360 we have only 2 ETH port on the board,
-if we use PCI it has its own MAC addr */
-
-#define CONFIG_ENV_OVERWRITE
-#endif /* __CONFIG_H */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_74xx /* we have a 750FX (override local.h) */
-
-#define CONFIG_DB64360 1 /* this is an DB64360 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
-#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
-/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the
- DRAM for ECC in the phase we are relocating to it, which isn't so sufficient.
- so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase,
- see sdram_init.c */
-#undef CONFIG_ECC /* enable ECC support */
-#define CONFIG_MV64360_ECC
-
-/* which initialization functions to call for this board */
-#define CONFIG_MISC_INIT_R /* initialize the icache L1 */
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#define CONFIG_SYS_BOARD_NAME "DB64360"
-#define CONFIG_IDENT_STRING "Marvell DB64360 (1.1)"
-
-/*#define CONFIG_SYS_HUSH_PARSER */
-#undef CONFIG_SYS_HUSH_PARSER
-
-
-/*
- * The following defines let you select what serial you want to use
- * for your console driver.
- *
- * what to do:
- * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
- * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
- * to 0 below.
- *
- * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
- * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
- */
-
-#define CONFIG_MPSC_PORT 0
-
-/* to change the default ethernet port, use this define (options: 0, 1, 2) */
-#define MV_ETH_DEVS 2
-
-/* #undef CONFIG_ETHER_PORT_MII */
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
-#endif
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-
-#undef CONFIG_BOOTARGS
-/*#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */
-
-/* ronen - autoboot using tftp */
-#if (CONFIG_BOOTDELAY >= 0)
-#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\
- setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \
- ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; "
-
-#define CONFIG_BOOTARGS "console=ttyS0,115200"
-
-#endif
-
-/* ronen - the u-boot.bin should be ~0x30000 bytes */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \
-cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \
- "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \
-cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \
- "bootargs_root=root=/dev/nfs rw\0" \
- "bootargs_end=:::DB64360:eth0:none \0"\
- "ethprime=mv_enet0\0"\
- "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \
-ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
-
-/* --------------------------------------------------------------------------------------------------------------- */
-/* New bootcommands for Marvell DB64360 c 2002 Ingo Assmus */
-
-#define CONFIG_IPADDR 10.2.40.90
-
-#define CONFIG_SERIAL "No. 1"
-#define CONFIG_SERVERIP 10.2.1.126
-#define CONFIG_ROOTPATH "/mnt/yellow_dog_mini"
-
-
-#define CONFIG_TESTDRAMDATA y
-#define CONFIG_TESTDRAMADDRESS n
-#define CONFIG_TESETDRAMWALK n
-
-/* --------------------------------------------------------------------------------------------------------------- */
-
-#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-#undef CONFIG_ALTIVEC /* undef to disable */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor1"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-
-/* Use first bank for JFFS2, second bank contains U-Boot.
- *
- * Note: fake mtd_id's used, no linux mtd map file.
- */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor1=db64360-1"
-#define MTDPARTS_DEFAULT "mtdparts=db64360-1:-(jffs2)"
-*/
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_NET
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-#define CONFIG_SYS_I2C_SPEED 40000 /* I2C speed default */
-
-/* #define CONFIG_SYS_GT_DUAL_CPU also for JTAG even with one cpu */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-/*#define CONFIG_SYS_MEMTEST_START 0x00400000 memtest works on */
-/*#define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
-/*#define CONFIG_SYS_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */
-
-/*
-#define CONFIG_SYS_DRAM_TEST
- * DRAM tests
- * CONFIG_SYS_DRAM_TEST - enables the following tests.
- *
- * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
- * Environment variable 'test_dram_data' must be
- * set to 'y'.
- * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
- * addressable. Environment variable
- * 'test_dram_address' must be set to 'y'.
- * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
- * This test takes about 6 minutes to test 64 MB.
- * Environment variable 'test_dram_walk' must be
- * set to 'y'.
- */
-#define CONFIG_SYS_DRAM_TEST
-#if defined(CONFIG_SYS_DRAM_TEST)
-#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
-/* #define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
-#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
-#define CONFIG_SYS_DRAM_TEST_DATA
-#define CONFIG_SYS_DRAM_TEST_ADDRESS
-#define CONFIG_SYS_DRAM_TEST_WALK
-#endif /* CONFIG_SYS_DRAM_TEST */
-
-#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */
-#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */
-
-/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
-#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */
-
-#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
-#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */
-
-/*ronen - this is the Tclk (MV64360 core) */
-#define CONFIG_SYS_TCLK 133000000
-
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_SYS_750FX_HID0 0x8000c084
-#define CONFIG_SYS_750FX_HID1 0x54800000
-#define CONFIG_SYS_750FX_HID2 0x00000000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-/*
- * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
- * To an unused memory region. The stack will remain in cache until RAM
- * is initialized
-*/
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* unused memory region */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#define RELOCATE_INTERNAL_RAM_ADDR
-#ifdef RELOCATE_INTERNAL_RAM_ADDR
- #define CONFIG_SYS_INTERNAL_RAM_ADDR 0xf8000000
-#endif
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-/* Dummies for BAT 4-7 */
-#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */
-#define CONFIG_SYS_SDRAM2_BASE 0x20000000
-#define CONFIG_SYS_SDRAM3_BASE 0x30000000
-#define CONFIG_SYS_SDRAM4_BASE 0x40000000
-#define CONFIG_SYS_FLASH_BASE 0xfff00000
-
-#define CONFIG_SYS_DFL_BOOTCS_BASE 0xff800000
-#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/
-
-#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */
-#define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */
-#define PCI0_IO_BASE_BOOTM 0xfd000000
-
-#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
-
-/* areas to map different things with the GT in physical space */
-#define CONFIG_SYS_DRAM_BANKS 4
-
-/* What to put in the bats. */
-#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
-
-/* Peripheral Device section */
-
-/*******************************************************/
-/* We have on the db64360 Board : */
-/* GT-Chipset Register Area */
-/* GT-Chipset internal SRAM 256k */
-/* SRAM on external device module */
-/* Real time clock on external device module */
-/* dobble UART on external device module */
-/* Data flash on external device module */
-/* Boot flash on external device module */
-/*******************************************************/
-#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
-#define CONFIG_SYS_DB64360_RESET_ADDR 0x14000000 /* After power on Reset the DB64360 is here */
-
-/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */
-#define CONFIG_SYS_DEV_BASE 0xfc000000 /* GT Devices CS start here */
-
-#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE /* DEV_CS0 device modul sram */
-#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */
-#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */
-#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) /* DEV_CS3 device modul large flash */
-
-#define CONFIG_SYS_DEV0_SIZE _8M /* db64360 sram @ 0xfc00.0000 */
-#define CONFIG_SYS_DEV1_SIZE _8M /* db64360 rtc @ 0xfc80.0000 */
-#define CONFIG_SYS_DEV2_SIZE _16M /* db64360 duart @ 0xfd00.0000 */
-#define CONFIG_SYS_DEV3_SIZE _16M /* db64360 flash @ 0xfe00.0000 */
-/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-
-/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
-#define CONFIG_SYS_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */
-#define CONFIG_SYS_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */
-#define CONFIG_SYS_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */
-#define CONFIG_SYS_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */
-#define CONFIG_SYS_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */
-
- /* c 4 a 8 2 4 1 c */
- /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
- /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
- /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */
- /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */
-
-
-/* ronen - update MPP Control MV64360*/
-#define CONFIG_SYS_MPP_CONTROL_0 0x02222222
-#define CONFIG_SYS_MPP_CONTROL_1 0x11333011
-#define CONFIG_SYS_MPP_CONTROL_2 0x40431111
-#define CONFIG_SYS_MPP_CONTROL_3 0x00000044
-
-/*# define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */
-
-
-# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/
- /* gpp[31] gpp[30] gpp[29] gpp[28] */
- /* gpp[27] gpp[24]*/
- /* gpp[19:14] */
-
-/* setup new config_value for MV64360 DDR-RAM !! */
-# define CONFIG_SYS_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/
-
-#define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE
-#define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */
-#define CONFIG_SYS_INIT_CHAN1
-#define CONFIG_SYS_INIT_CHAN2
-
-#define SRAM_BASE CONFIG_SYS_DEV0_SPACE
-#define SRAM_SIZE 0x00100000 /* 1 MB of sram */
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-
-#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */
-
-/* PCI MEMORY MAP section */
-#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI0_MEM_SIZE _128M
-#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
-#define CONFIG_SYS_PCI1_MEM_SIZE _128M
-
-#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
-#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
-
-/* PCI I/O MAP section */
-#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
-#define CONFIG_SYS_PCI0_IO_SIZE _16M
-#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
-#define CONFIG_SYS_PCI1_IO_SIZE _16M
-
-#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
-#define CONFIG_SYS_PCI0_IO_SPACE_PCI (CONFIG_SYS_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
-#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
-#define CONFIG_SYS_PCI1_IO_SPACE_PCI (CONFIG_SYS_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
-
-#if defined (CONFIG_750CX)
-#define CONFIG_SYS_PCI_IDSEL 0x0
-#else
-#define CONFIG_SYS_PCI_IDSEL 0x30
-#endif
-/*----------------------------------------------------------------------
- * Initial BAT mappings
- */
-
-/* NOTES:
- * 1) GUARDED and WRITE_THRU not allowed in IBATS
- * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
- */
-
-/* SDRAM */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* init ram */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* PCI0, PCI1 in one BAT */
-#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* GT regs, bootrom, all the devices, PCI I/O */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* I2C addresses for the two DIMM SPD chips */
-#define DIMM0_I2C_ADDR 0x56
-#define DIMM1_I2C_ADDR 0x54
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */
-#define CONFIG_SYS_EXTRA_FLASH_WIDTH 4 /* 32 bit */
-#define CONFIG_SYS_BOOT_FLASH_WIDTH 1 /* 8 bit */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */
-#define CONFIG_SYS_FLASH_CFI 1
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
-/* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * L2CR setup -- make sure this is right for your board!
- * look in include/mpc74xx.h for the defines used here
- */
-
-#define CONFIG_SYS_L2
-
-
-#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
-#define L2_INIT 0
-#else
-
-#define L2_INIT 0
-/*
-#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
- L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
-*/
-#endif
-
-#define L2_ENABLE (L2_INIT | L2CR_L2E)
-
-#define CONFIG_SYS_BOARD_ASM_INIT 1
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* This define must be before the core.h include */
-#define CONFIG_DB64460 1 /* this is an DB64460 board */
-
-#ifndef __ASSEMBLY__
-#include "../board/Marvell/include/core.h"
-#endif
-
-/*-----------------------------------------------------*/
-/* #include "../board/db64460/local.h" */
-#ifndef __LOCAL_H
-#define __LOCAL_H
-
-#define CONFIG_ETHADDR 64:46:00:00:00:01
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 64:46:00:00:00:02
-#define CONFIG_HAS_ETH2
-#define CONFIG_ETH2ADDR 64:46:00:00:00:03
-
-#define CONFIG_ENV_OVERWRITE
-#endif /* __CONFIG_H */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_74xx /* we have a 750FX (override local.h) */
-
-#define CONFIG_DB64460 1 /* this is an DB64460 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
-#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
-/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the
- DRAM for ECC in the phase we are relocating to it, which isn't so sufficient.
- so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase,
- see sdram_init.c */
-#undef CONFIG_ECC /* enable ECC support */
-#define CONFIG_MV64460_ECC
-
-/* which initialization functions to call for this board */
-#define CONFIG_MISC_INIT_R /* initialize the icache L1 */
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#define CONFIG_SYS_BOARD_NAME "DB64460"
-#define CONFIG_IDENT_STRING "Marvell DB64460 (1.0)"
-
-/*#define CONFIG_SYS_HUSH_PARSER */
-#undef CONFIG_SYS_HUSH_PARSER
-
-
-/*
- * The following defines let you select what serial you want to use
- * for your console driver.
- *
- * what to do:
- * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
- * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
- * to 0 below.
- *
- * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
- * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
- */
-
-#define CONFIG_MPSC_PORT 0
-
-/* to change the default ethernet port, use this define (options: 0, 1, 2) */
-#define MV_ETH_DEVS 3
-
-/* #undef CONFIG_ETHER_PORT_MII */
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
-#endif
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-
-#undef CONFIG_BOOTARGS
-/*#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */
-
-/* ronen - autoboot using tftp */
-#if (CONFIG_BOOTDELAY >= 0)
-#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\
- setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \
- ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; "
-
-#define CONFIG_BOOTARGS "console=ttyS0,115200"
-
-#endif
-
-/* ronen - the u-boot.bin should be ~0x30000 bytes */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \
-cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \
- "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \
-cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \
- "bootargs_root=root=/dev/nfs rw\0" \
- "bootargs_end=:::DB64460:eth0:none \0"\
- "ethprime=mv_enet0\0"\
- "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \
-ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
-
-/* --------------------------------------------------------------------------------------------------------------- */
-/* New bootcommands for Marvell DB64460 c 2002 Ingo Assmus */
-
-#define CONFIG_IPADDR 10.2.40.90
-
-#define CONFIG_SERIAL "No. 1"
-#define CONFIG_SERVERIP 10.2.1.126
-#define CONFIG_ROOTPATH "/mnt/yellow_dog_mini"
-
-
-#define CONFIG_TESTDRAMDATA y
-#define CONFIG_TESTDRAMADDRESS n
-#define CONFIG_TESETDRAMWALK n
-
-/* --------------------------------------------------------------------------------------------------------------- */
-
-#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-#undef CONFIG_ALTIVEC /* undef to disable */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor1"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-
-/* Use first bank for JFFS2, second bank contains U-Boot.
- *
- * Note: fake mtd_id's used, no linux mtd map file.
- */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor1=db64460-1"
-#define MTDPARTS_DEFAULT "mtdparts=db64460-1:-(jffs2)"
-*/
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_NET
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-#define CONFIG_SYS_I2C_SPEED 40000 /* I2C speed default */
-
-/* #define CONFIG_SYS_GT_DUAL_CPU also for JTAG even with one cpu */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-/*#define CONFIG_SYS_MEMTEST_START 0x00400000 memtest works on */
-/*#define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
-/*#define CONFIG_SYS_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */
-
-/*
-#define CONFIG_SYS_DRAM_TEST
- * DRAM tests
- * CONFIG_SYS_DRAM_TEST - enables the following tests.
- *
- * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
- * Environment variable 'test_dram_data' must be
- * set to 'y'.
- * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
- * addressable. Environment variable
- * 'test_dram_address' must be set to 'y'.
- * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
- * This test takes about 6 minutes to test 64 MB.
- * Environment variable 'test_dram_walk' must be
- * set to 'y'.
- */
-#define CONFIG_SYS_DRAM_TEST
-#if defined(CONFIG_SYS_DRAM_TEST)
-#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
-/* #define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
-#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
-#define CONFIG_SYS_DRAM_TEST_DATA
-#define CONFIG_SYS_DRAM_TEST_ADDRESS
-#define CONFIG_SYS_DRAM_TEST_WALK
-#endif /* CONFIG_SYS_DRAM_TEST */
-
-#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */
-#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */
-
-/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
-#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */
-
-#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
-#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 200MHZ -> 5.0 ns, 166MHZ -> 6.0, 133MHZ -> 7.50 ns */
-
-/*ronen - this is the Tclk (MV64460 core) */
-#define CONFIG_SYS_TCLK 133000000
-
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_SYS_750FX_HID0 0x8000c084
-#define CONFIG_SYS_750FX_HID1 0x54800000
-#define CONFIG_SYS_750FX_HID2 0x00000000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-/*
- * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
- * To an unused memory region. The stack will remain in cache until RAM
- * is initialized
-*/
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* unused memory region */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#define RELOCATE_INTERNAL_RAM_ADDR
-#ifdef RELOCATE_INTERNAL_RAM_ADDR
- #define CONFIG_SYS_INTERNAL_RAM_ADDR 0xf8000000
-#endif
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-/* Dummies for BAT 4-7 */
-#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */
-#define CONFIG_SYS_SDRAM2_BASE 0x20000000
-#define CONFIG_SYS_SDRAM3_BASE 0x30000000
-#define CONFIG_SYS_SDRAM4_BASE 0x40000000
-#define CONFIG_SYS_FLASH_BASE 0xfff00000
-
-#define CONFIG_SYS_DFL_BOOTCS_BASE 0xff800000
-#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/
-
-#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */
-#define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */
-#define PCI0_IO_BASE_BOOTM 0xfd000000
-
-#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
-
-/* areas to map different things with the GT in physical space */
-#define CONFIG_SYS_DRAM_BANKS 4
-
-/* What to put in the bats. */
-#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
-
-/* Peripheral Device section */
-
-/*******************************************************/
-/* We have on the db64460 Board : */
-/* GT-Chipset Register Area */
-/* GT-Chipset internal SRAM 256k */
-/* SRAM on external device module */
-/* Real time clock on external device module */
-/* dobble UART on external device module */
-/* Data flash on external device module */
-/* Boot flash on external device module */
-/*******************************************************/
-#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
-#define CONFIG_SYS_DB64460_RESET_ADDR 0x14000000 /* After power on Reset the DB64460 is here */
-
-/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */
-#define CONFIG_SYS_DEV_BASE 0xfc000000 /* GT Devices CS start here */
-
-#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE /* DEV_CS0 device modul sram */
-#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */
-#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */
-#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) /* DEV_CS3 device modul large flash */
-
-#define CONFIG_SYS_DEV0_SIZE _8M /* db64460 sram @ 0xfc00.0000 */
-#define CONFIG_SYS_DEV1_SIZE _8M /* db64460 rtc @ 0xfc80.0000 */
-#define CONFIG_SYS_DEV2_SIZE _16M /* db64460 duart @ 0xfd00.0000 */
-#define CONFIG_SYS_DEV3_SIZE _16M /* db64460 flash @ 0xfe00.0000 */
-/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-
-/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
-#define CONFIG_SYS_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */
-#define CONFIG_SYS_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */
-#define CONFIG_SYS_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */
-#define CONFIG_SYS_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */
-#define CONFIG_SYS_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */
-
- /* c 4 a 8 2 4 1 c */
- /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
- /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
- /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */
- /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */
-
-
-/* ronen - update MPP Control MV64460*/
-#define CONFIG_SYS_MPP_CONTROL_0 0x02222222
-#define CONFIG_SYS_MPP_CONTROL_1 0x11333011
-#define CONFIG_SYS_MPP_CONTROL_2 0x40431111
-#define CONFIG_SYS_MPP_CONTROL_3 0x00000044
-
-/*# define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */
-
-
-# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/
- /* gpp[31] gpp[30] gpp[29] gpp[28] */
- /* gpp[27] gpp[24]*/
- /* gpp[19:14] */
-
-/* setup new config_value for MV64460 DDR-RAM !! */
-# define CONFIG_SYS_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/
-
-#define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE
-#define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */
-#define CONFIG_SYS_INIT_CHAN1
-#define CONFIG_SYS_INIT_CHAN2
-
-#define SRAM_BASE CONFIG_SYS_DEV0_SPACE
-#define SRAM_SIZE 0x00100000 /* 1 MB of sram */
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-
-#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */
-
-/* PCI MEMORY MAP section */
-#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI0_MEM_SIZE _128M
-#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
-#define CONFIG_SYS_PCI1_MEM_SIZE _128M
-
-#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
-#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
-
-/* PCI I/O MAP section */
-#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
-#define CONFIG_SYS_PCI0_IO_SIZE _16M
-#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
-#define CONFIG_SYS_PCI1_IO_SIZE _16M
-
-#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
-#define CONFIG_SYS_PCI0_IO_SPACE_PCI (CONFIG_SYS_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
-#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
-#define CONFIG_SYS_PCI1_IO_SPACE_PCI (CONFIG_SYS_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
-
-#if defined (CONFIG_750CX)
-#define CONFIG_SYS_PCI_IDSEL 0x0
-#else
-#define CONFIG_SYS_PCI_IDSEL 0x30
-#endif
-/*----------------------------------------------------------------------
- * Initial BAT mappings
- */
-
-/* NOTES:
- * 1) GUARDED and WRITE_THRU not allowed in IBATS
- * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
- */
-
-/* SDRAM */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* init ram */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* PCI0, PCI1 in one BAT */
-#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* GT regs, bootrom, all the devices, PCI I/O */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* I2C addresses for the two DIMM SPD chips */
-#define DIMM0_I2C_ADDR 0x56
-#define DIMM1_I2C_ADDR 0x54
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */
-#define CONFIG_SYS_EXTRA_FLASH_WIDTH 4 /* 32 bit */
-#define CONFIG_SYS_BOOT_FLASH_WIDTH 1 /* 8 bit */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */
-#define CONFIG_SYS_FLASH_CFI 1
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
-/* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * L2CR setup -- make sure this is right for your board!
- * look in include/mpc74xx.h for the defines used here
- */
-
-#define CONFIG_SYS_L2
-
-
-#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
-#define L2_INIT 0
-#else
-
-#define L2_INIT 0
-/*
-#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
- L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
-*/
-#endif
-
-#define L2_ENABLE (L2_INIT | L2CR_L2E)
-
-#define CONFIG_SYS_BOARD_ASM_INIT 1
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Copyright 2009-2010 eXMeritus, A Boeing Company
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * HardwareWall HWW-1U-1A airborne unit configuration file
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High-level system configuration options */
-#define CONFIG_BOOKE /* Power/PowerPC Book-E */
-#define CONFIG_E500 /* e500 (Power ISA v2.03 with SPE) */
-#define CONFIG_FSL_ELBC /* FreeScale Enhanced LocalBus Cntlr */
-#define CONFIG_FSL_LAW /* FreeScale Local Access Window */
-#define CONFIG_P2020 /* FreeScale P2020 */
-#define CONFIG_HWW1U1A /* eXMeritus HardwareWall HWW-1U-1A */
-#define CONFIG_MP /* Multiprocessing support */
-#define CONFIG_HWCONFIG /* Use hwconfig from environment */
-
-#define CONFIG_L2_CACHE /* L2 cache enabled */
-#define CONFIG_BTB /* Branch predition enabled */
-
-#define CONFIG_PANIC_HANG /* No board reset on panic */
-#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r() */
-#define CONFIG_CMD_REGINFO /* Dump various CPU regs */
-
-/*
- * Allow the use of 36-bit physical addresses. Device-trees with 64-bit
- * addresses have known compatibility issues with some existing kernels.
- */
-#define CONFIG_ENABLE_36BIT_PHYS
-#define CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* Number of entries in TLB1 */
-
-/* Reserve plenty of RAM for malloc (we have 2GB+) */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
-
-/* How much L2 cache do we map so we can use it as RAM */
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-/* This is our temporary global data area just above the stack */
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/* The stack grows down from the global data area */
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/* Enable IRQs and watchdog with a 1000Hz system decrementer */
-#define CONFIG_CMD_IRQ
-
-/* -------------------------------------------------------------------- */
-
-/*
- * Clock crystal configuration:
- * (1) SYS: 66.666MHz +/- 50ppm (drives CPU/PCI/DDR)
- * (2) CCB: Multiplier from SYS_CLK
- * (3) RTC: 25.000MHz +/- 50ppm (sampled against CCB clock)
- */
-#define CONFIG_SYS_CLK_FREQ 66666000/*Hz*/
-#define CONFIG_DDR_CLK_FREQ 66666000/*Hz*/
-
-
-/* -------------------------------------------------------------------- */
-
-/*
- * Memory map
- *
- * 0x0000_0000 0x7fff_ffff 2G DDR2 ECC SDRAM
- * 0x8000_0000 0x9fff_ffff 512M PCI-E Bus 1
- * 0xa000_0000 0xbfff_ffff 512M PCI-E Bus 2 (unused)
- * 0xc000_0000 0xdfff_ffff 512M PCI-E Bus 3
- * 0xe000_0000 0xe7ff_ffff 128M Spansion FLASH
- * 0xe800_0000 0xefff_ffff 128M Spansion FLASH
- * 0xffd0_0000 0xffd0_3fff 16K L1 boot stack (TLB0)
- * 0xffe0_0000 0xffef_ffff 1M CCSR
- * 0xffe0_5000 0xffe0_5fff 4K Enhanced LocalBus Controller
- */
-
-/* Virtual Memory Map */
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
-#define CONFIG_SYS_FLASH_BASE 0xe0000000
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
-#define CONFIG_SYS_CCSRBAR 0xffe00000 /* CCSRBAR @ runtime */
-
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-/* Physical Memory Map */
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
-#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfffd00000ull
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf /* for ASM code */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xffd00000 /* for ASM code */
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf /* for ASM code */
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW 0xffe00000 /* for ASM code */
-
-
-/* -------------------------------------------------------------------- */
-
-/* U-Boot image (MONITOR_BASE == TEXT_BASE) */
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc /* Top address in flash */
-#define CONFIG_SYS_TEXT_BASE 0xeff80000 /* Start of U-Boot image */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN 0x80000 /* 512kB (4 flash sectors) */
-
-/*
- * U-Boot Environment Image: The two sectors immediately below U-Boot
- * form the U-Boot environment (regular and redundant).
- */
-#define CONFIG_ENV_IS_IN_FLASH /* The environment image is stored in FLASH */
-#define CONFIG_ENV_OVERWRITE /* Allow "protected" variables to be erased */
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128kB (1 flash sector) */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-
-/* Only use 8kB of each environment sector for data */
-#define CONFIG_ENV_SIZE 0x2000 /* 8kB */
-#define CONFIG_ENV_SIZE_REDUND 0x2000 /* 8kB */
-
-
-/* -------------------------------------------------------------------- */
-
-/* Serial Console Configuration */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/* Echo back characters received during a serial download */
-#define CONFIG_LOADS_ECHO
-
-/* Allow a serial-download to temporarily change baud */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE
-
-
-/* -------------------------------------------------------------------- */
-
-/* PCI and PCI-Express Support */
-#define CONFIG_PCI /* Enable PCI/PCIE */
-#define CONFIG_PCI_PNP /* Scan PCI busses */
-#define CONFIG_CMD_PCI /* Enable the "pci" command */
-#define CONFIG_FSL_PCI_INIT /* Common FreeScale PCI initialization */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET /* We have PCI-E reset errata */
-#define CONFIG_SYS_PCI_64BIT /* PCI resources are 64-bit */
-#define CONFIG_PCI_SCAN_SHOW /* Display PCI scan during boot */
-
-/* Enable 2 of the 3 PCI-E controllers */
-#define CONFIG_PCIE3
-#undef CONFIG_PCIE2
-#define CONFIG_PCIE1
-
-/* Display human-readable names when initializing */
-#define CONFIG_SYS_PCIE3_NAME "Intel 82571EB"
-#define CONFIG_SYS_PCIE2_NAME "Unused"
-#define CONFIG_SYS_PCIE1_NAME "Silicon Image SIL3531"
-
-/*
- * PCI bus addresses
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-
-
-/* -------------------------------------------------------------------- */
-
-/* Generic FreeScale hardware I2C support */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
-#define CONFIG_CMD_I2C
-
-/* DDR2 SO-RDIMM SPD EEPROM is at I2C0-0x51 */
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS 0x51
-
-/* DS1339 RTC is at I2C0-0x68 (I know it says "DS1337", it's a DS1339) */
-#define CONFIG_CMD_DATE
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_RTC_BUS_NUM 0
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-/* Turn off RTC square-wave output to save battery */
-#define CONFIG_SYS_RTC_DS1337_NOOSC
-
-/*
- * AT24C128N EEPROM at I2C0-0x53.
- *
- * That Atmel EEPROM has 128kbit of memory (16kByte) divided into 256 pages
- * of 64 bytes per page. The chip uses 2-byte addresses and has a max write
- * cycle time of 20ms according to the datasheet.
- *
- * NOTE: Our environment is stored on regular direct-attached FLASH, this
- * chip is only used as a write-protected backup for certain key settings
- * such as the serial# and macaddr values. (EG: "env import")
- */
-#define CONFIG_CMD_EEPROM
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 1 << 6 == 64 byte pages */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 21
-
-/*
- * PCA9554 is at I2C1-0x3f (I know it says "PCA953X", it's a PCA9554). You
- * must first select the I2C1 bus with "i2c dev 1" or the "pca953x" command
- * will not be able to access the chip.
- */
-#define CONFIG_PCA953X
-#define CONFIG_CMD_PCA953X
-#define CONFIG_CMD_PCA953X_INFO
-#define CONFIG_SYS_I2C_PCA953X_ADDR 0x3f
-
-
-/* -------------------------------------------------------------------- */
-
-/* FreeScale DDR2/3 SDRAM Controller */
-#define CONFIG_SYS_FSL_DDR2 /* Our SDRAM slot is DDR2 */
-#define CONFIG_DDR_ECC /* Enable ECC by default */
-#define CONFIG_DDR_SPD /* Detect DDR config from SPD EEPROM */
-#define CONFIG_SPD_EEPROM /* ...why 2 config variables for this? */
-#define CONFIG_VERY_BIG_RAM /* Allow 2GB+ of RAM */
-#define CONFIG_CMD_SDRAM
-
-/* Standard P2020 DDR controller parameters */
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 2
-
-/* Make sure to tell the DDR controller to preinitialze all of RAM */
-#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-
-
-/* -------------------------------------------------------------------- */
-
-/* FLASH Memory Configuration (2x 128MB SPANSION FLASH) */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
-
-/* Flash banks (2x 128MB) */
-#define FLASH0_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000ull)
-#define FLASH1_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x0000000ull)
-#define CONFIG_SYS_MAX_FLASH_BANKS 2
-#define CONFIG_SYS_MAX_FLASH_SECT 1024
-#define CONFIG_SYS_FLASH_BANKS_LIST { FLASH0_PHYS, FLASH1_PHYS }
-
-/*
- * Flash access modes and timings (values are the defaults after a RESET).
- *
- * NOTE: These could probably be optimized but are more than sufficient for
- * this particular system for the moment.
- */
-#define FLASH_BRx (BR_PS_16 | BR_MS_GPCM | BR_V)
-#define FLASH_ORx (OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
-
-/* Configure both flash banks */
-#define CONFIG_SYS_BR0_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH0_PHYS))
-#define CONFIG_SYS_BR1_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH1_PHYS))
-#define CONFIG_SYS_OR0_PRELIM (FLASH_ORx | OR_AM_128MB)
-#define CONFIG_SYS_OR1_PRELIM (FLASH_ORx | OR_AM_128MB)
-
-/* Flash timeouts (in ms) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000UL /* Erase (60s) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500UL /* Write (0.5s) */
-
-/* Quiet flash testing */
-#define CONFIG_SYS_FLASH_QUIET_TEST
-
-/* Make program/erase count down from 45/5 (9....8....7....) */
-#define CONFIG_FLASH_SHOW_PROGRESS 45
-
-
-/* -------------------------------------------------------------------- */
-
-/* Ethernet Device Support */
-#define CONFIG_MII /* Enable MII PHY code */
-#define CONFIG_MII_DEFAULT_TSEC /* ??? Copied from P2020DS */
-#define CONFIG_PHY_GIGE /* Support Gigabit PHYs */
-#define CONFIG_ETHPRIME "e1000#0" /* Default to external ports */
-
-/* Turn on various helpful networking commands */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-
-/* On-chip FreeScale P2020 "tsec" Ethernet (oneway fibers and peer) */
-#define CONFIG_TSEC_ENET
-#define CONFIG_TSEC1
-#define CONFIG_TSEC2
-#define CONFIG_TSEC3
-#define CONFIG_TSEC1_NAME "owt0"
-#define CONFIG_TSEC2_NAME "owt1"
-#define CONFIG_TSEC3_NAME "peer"
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-#define TSEC1_PHY_ADDR 2
-#define TSEC2_PHY_ADDR 3
-#define TSEC3_PHY_ADDR 4
-#define TSEC3_PHY_ADDR_CPUA 4
-#define TSEC3_PHY_ADDR_CPUB 5
-
-/* PCI-E dual-port E1000 (external ethernet ports) */
-#define CONFIG_E1000
-#define CONFIG_E1000_SPI
-#define CONFIG_E1000_SPI_GENERIC
-#define CONFIG_CMD_E1000
-
-/* We need the SPI infrastructure to poke the E1000's EEPROM */
-#define CONFIG_SPI
-#define CONFIG_SPI_X
-#define CONFIG_CMD_SPI
-#define MAX_SPI_BYTES 32
-
-
-/* -------------------------------------------------------------------- */
-
-/* USB Thumbdrive Device Support */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_USB_STORAGE
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_CMD_USB
-
-/* Partition and Filesystem support */
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-#define CONFIG_ISO_PARTITION
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-
-
-/* -------------------------------------------------------------------- */
-
-/* Command line configuration. */
-#define CONFIG_CMDLINE_EDITING /* Enable command editing */
-#define CONFIG_COMMAND_HISTORY /* Enable command history */
-#define CONFIG_AUTO_COMPLETE /* Enable command completion */
-#define CONFIG_SYS_LONGHELP /* Enable detailed command help */
-#define CONFIG_SYS_MAXARGS 128 /* Up to 128 command-line args */
-#define CONFIG_SYS_PBSIZE 8192 /* Allow up to 8k printed lines */
-#define CONFIG_SYS_CBSIZE 4096 /* Allow up to 4k command lines */
-#define CONFIG_SYS_BARGSIZE 4096 /* Allow up to 4k boot args */
-#define CONFIG_SYS_HUSH_PARSER /* Enable a fancier shell */
-
-/* A little extra magic here for the prompt */
-#define CONFIG_SYS_PROMPT hww1u1a_get_ps1()
-#ifndef __ASSEMBLY__
-const char *hww1u1a_get_ps1(void);
-#endif
-
-/* Include a bunch of default commands we probably want */
-#include <config_cmd_default.h>
-
-/* Other helpful shell-like commands */
-#define CONFIG_MD5
-#define CONFIG_SHA1
-#define CONFIG_CMD_MD5SUM
-#define CONFIG_CMD_SHA1SUM
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_SETEXPR
-
-
-/* -------------------------------------------------------------------- */
-
-/* Image manipulation and booting */
-
-/* We use the OpenFirmware-esque "Flattened Device Tree" */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_CMD_ELF
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Maximum kernel memory map */
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Maximum kernel size of 64MB */
-
-/* This is the default address for commands with an optional address arg */
-#define CONFIG_LOADADDR 100000
-#define CONFIG_SYS_LOAD_ADDR 0x100000
-
-/* Test memory starting from the default load address to just below 2GB */
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_LOAD_ADDR
-#define CONFIG_SYS_MEMTEST_END 0x7f000000
-
-#define CONFIG_BOOTDELAY 20
-#define CONFIG_BOOTCOMMAND "echo Not yet flashed"
-#define CONFIG_BOOTARGS ""
-#define CONFIG_BOOTARGS_DYNAMIC "console=ttyS0,${baudrate}n1"
-
-/* Extra environment parameters */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ethprime=e1000#0\0" \
- "ethrotate=no\0" \
- "setbootargs=setenv bootargs " \
- "\"${bootargs} "CONFIG_BOOTARGS_DYNAMIC"\"\0" \
- "perf_mode=performance\0" \
- "hwconfig=" "fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \
- "usb1:dr_mode=host,phy_type=ulpi\0" \
- "flkernel=0xe8000000\0" \
- "flinitramfs=0xe8800000\0" \
- "fldevicetree=0xeff20000\0" \
- "flbootm=bootm ${flkernel} ${flinitramfs} ${fldevicetree}\0" \
- "flboot=run preboot; run flbootm\0" \
- "restore_eeprom=i2c dev 0 && " \
- "eeprom read $loadaddr 0x0000 0x2000 && " \
- "env import -c $loadaddr 0x2000\0"
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <mpc8xx_irq.h>
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC860 1
-#define CONFIG_MPC860T 1
-#define CONFIG_ICU862 1
-#define CONFIG_MPC862 1
-
-#define CONFIG_SYS_TEXT_BASE 0x40F00000
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-
-#ifdef CONFIG_100MHz
-#define MPC8XX_FACT 24 /* Multiply by 24 */
-#define MPC8XX_XIN 4165000 /* 4.165 MHz in */
-#define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN)
- /* define if cant' use get_gclk_freq */
-#else
-#if 1 /* for 50MHz version of processor */
-#define MPC8XX_FACT 12 /* Multiply by 12 */
-#define MPC8XX_XIN 4000000 /* 4 MHz in */
-#define CONFIG_8xx_GCLK_FREQ 48000000 /* define if cant use get_gclk_freq */
-#else /* for 80MHz version of processor */
-#define MPC8XX_FACT 20 /* Multiply by 20 */
-#define MPC8XX_XIN 4000000 /* 4 MHz in */
-#define CONFIG_8xx_GCLK_FREQ 80000000 /* define if cant use get_gclk_freq */
-#endif
-#endif
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
- "bootm"
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
-#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
-#define CONFIG_MII 1
-#if 1
-#define CONFIG_SYS_DISCOVER_PHY 1
-#else
-#undef CONFIG_SYS_DISCOVER_PHY
-#endif
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL 0x00000020 /* PB 26 */
-#define PB_SDA 0x00000010 /* PB 27 */
-
-#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
-#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
-#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
- else immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
- else immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-
-#define CONFIG_SYS_EEPROM_X40430 /* Use a Xicor X40430 EEPROM */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16 bytes page write mode */
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xF0000000
-#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024))
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#define CONFIG_SYS_FLASH_SIZE ((uint)(16 * 1024 * 1024)) /* max 16Mbyte */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-
-#if 0
-#if defined(DEBUG)
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#endif
-#else
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x00F40000
-
-#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment sector */
-#define CONFIG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */
-#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * set the PLL, the low-power modes and the reset control (15-29)
- */
-#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
- PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#ifdef CONFIG_100MHz /* for 100 MHz, external bus is half CPU clock */
-#define SCCR_MASK 0
-#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \
- SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
- SCCR_DFLCD000 |SCCR_DFALCD00 | SCCR_EBDF01)
-#else /* up to 50 MHz we use a 1:1 clock */
-#define SCCR_MASK SCCR_EBDF11
-#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \
- SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
- SCCR_DFLCD000 |SCCR_DFALCD00 )
-#endif /* CONFIG_100MHz */
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register 19-4
- *-----------------------------------------------------------------------
- */
-/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */
-#define CONFIG_SYS_RCCR 0x0020
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * PCMCIA Power Switch
- *
- * The ICU862 uses a TPS2205 PC-Card Power-Interface Switch to
- * control the voltages on the PCMCIA slot which is connected to Port B
- *-----------------------------------------------------------------------
- */
- /* Output pins */
-#define TPS2205_VCC5 0x00008000 /* PB.16: 5V Voltage Control */
-#define TPS2205_VCC3 0x00004000 /* PB.17: 3V Voltage Control */
-#define TPS2205_VPP_PGM 0x00002000 /* PB.18: PGM Voltage Control */
-#define TPS2205_VPP_VCC 0x00001000 /* PB.19: VPP Voltage Control */
-#define TPS2205_SHDN 0x00000200 /* PB.22: Shutdown */
-#define TPS2205_OUTPUTS ( TPS2205_VCC5 | TPS2205_VCC3 | \
- TPS2205_VPP_PGM | TPS2205_VPP_VCC | \
- TPS2205_SHDN)
-
- /* Input pins */
-#define TPS2205_OC 0x00000100 /* PB.23: Over-Current */
-#define TPS2205_INPUTS ( TPS2205_OC )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
-#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-
- /*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/* Because of the way the 860 starts up and assigns CS0 the
-* entire address space, we have to set the memory controller
-* differently. Normally, you write the option register
-* first, and then enable the chip select by writing the
-* base register. For CS0, you must write the base register
-* first, followed by the option register.
-*/
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0x0 /* FLASH bank #1 */
-
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-
-#define CONFIG_SYS_OR0_PRELIM 0xFF000954 /* Real values for the board */
-#define CONFIG_SYS_BR0_PRELIM 0x40000001 /* Real values for the board */
-
-/*
- * BR1 and OR1 (SDRAM)
- */
-#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank */
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
-
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000800 /* BIH is not set */
-
-#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM)
-#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-#define CONFIG_SYS_MAMR 0x13a01114
-
-#ifdef CONFIG_MPC860T
-
-/* Interrupt level assignments.
-*/
-#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
-
-#endif /* CONFIG_MPC860T */
-
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8272_FAMILY 1
-#define CONFIG_IDS8247 1
-#define CPU_ID_STR "MPC8247"
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_BOOTCOUNT_LIMIT
-
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw " \
- "console=ttyS0,115200\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "rootpath=/opt/eldk/ppc_82xx\0" \
- "bootfile=/tftpboot/IDS8247/uImage\0" \
- "kernel_addr=ff800000\0" \
- "ramdisk_addr=ffa00000\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#define CONFIG_MISC_INIT_R 1
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 400000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
-/*
- * Software (bit-bang) I2C driver configuration
- */
-
-#define I2C_PORT 0 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00000080)
-#define I2C_TRISTATE (iop->pdir &= ~0x00000080)
-#define I2C_READ ((iop->pdat & 0x00000080) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000080; \
- else iop->pdat &= ~0x00000080
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000100; \
- else iop->pdat &= ~0x00000100
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-
-#if 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-#define CONFIG_I2C_X
-#endif
-
-/*
- * select serial console configuration
- * use the extern UART for the console
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-
-#define CONFIG_SYS_NS16550_CLK 14745600
-
-#define CONFIG_SYS_UART_BASE 0xE0000000
-#define CONFIG_SYS_UART_SIZE 0x10000
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0x8000)
-
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_TBCLK (bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000"
-
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
-#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
-#undef CONFIG_ETHER_NONE /* define if ether on something else */
-#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
-#define CONFIG_ETHER_ON_FCC1
-#define FCC_ENET
-
-/*
- * - Rx-CLK is CLK10
- * - Tx-CLK is CLK9
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9)
-# define CONFIG_SYS_CPMFCR_RAMTYPE 0
-# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#define CONFIG_8260_CLKIN 66666666 /* in Hz */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#define CONFIG_RTC_PCF8563
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_FLASH_BANKS_LIST { 0xFF800000 }
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ids8247/config.mk
- * The main FLASH is whichever is connected to *CS0.
- */
-#define CONFIG_SYS_FLASH0_BASE 0xFFF00000
-#define CONFIG_SYS_FLASH0_SIZE 8
-
-/* Flash bank size (for preliminary settings)
- */
-#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-/* Environment in flash */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x60000)
-#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#if defined(CONFIG_CMD_NAND)
-
-#define CONFIG_SYS_NAND0_BASE 0xE1000000
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-
-#endif /* CONFIG_CMD_NAND */
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000)
-
-/* no slaves so just fill with zeros */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- *
- * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-
-#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
-#define CONFIG_SYS_HID0_FINAL 0
-#define CONFIG_SYS_HID2 0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR 0
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration 4-25
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_BCR 0
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 4-31
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01)
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control 9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR (0x00000028 | SCCR_DFBRG01)
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration 13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR 0
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus Machine PortSz Device
- * ---- --- ------- ------ ------
- * 0 60x GPCM 16 bit FLASH
- * 1 60x GPCM 8 bit NAND
- * 2 60x SDRAM 32 bit SDRAM
- * 3 60x GPCM 8 bit UART
- *
- */
-
-#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
-
-/* Minimum mask to separate preliminary
- * address ranges for CS[0:2]
- */
-#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (32<<20) /* less than 32 MB */
-
-#define CONFIG_SYS_MPTPR 0x6600
-
-/*-----------------------------------------------------------------------------
- * Address for Mode Register Set (MRS) command
- *-----------------------------------------------------------------------------
- */
-#define CONFIG_SYS_MRS_OFFS 0x00000110
-
-
-/* Bank 0 - FLASH
- */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
- ORxG_SCY_6_CLK )
-
-#if defined(CONFIG_CMD_NAND)
-/* Bank 1 - NAND Flash
-*/
-#define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND0_BASE
-#define CONFIG_SYS_NAND_SIZE 0x8000
-
-#define CONFIG_SYS_OR_TIMING_NAND 0x000036
-
-#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )
-#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | CONFIG_SYS_OR_TIMING_NAND )
-#endif
-
-/* Bank 2 - 60x bus SDRAM
- */
-#define CONFIG_SYS_PSRT 0x20
-#define CONFIG_SYS_LSRT 0x20
-
-#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
- BRx_PS_32 |\
- BRx_MS_SDRAM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2
-
-
-/* SDRAM initialization values
-*/
-#define CONFIG_SYS_OR2 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI0_A9 |\
- ORxS_NUMR_12)
-
-#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\
- PSDMR_BSMA_A15_A17 |\
- PSDMR_SDA10_PBI0_A10 |\
- PSDMR_RFRC_5_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_BL |\
- PSDMR_LDOTOPRE_2C |\
- PSDMR_WRC_3C |\
- PSDMR_CL_3)
-
-/* Bank 3 - UART
-*/
-
-#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )
-#define CONFIG_SYS_OR3_PRELIM (((-CONFIG_SYS_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX )
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Configuation settings for the miniHiPerCam.
- *
- * -----------------------------------------------------------------
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
-#define CONFIG_MHPC 1 /* on a miniHiPerCam */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* do special hardware init. */
-#define CONFIG_MISC_INIT_R 1
-
-#define CONFIG_SYS_TEXT_BASE 0xfe000000
-
-#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED
-#undef CONFIG_8xx_CONS_SMC1
-#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#define CONFIG_ENV_OVERWRITE 1
-#define CONFIG_ETHADDR 00:00:5b:ee:de:ad
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
- "bootm"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-#undef CONFIG_UCODE_PATCH
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL 0x00000020 /* PB 26 */
-#define PB_SDA 0x00000010 /* PB 27 */
-
-#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
-#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
-#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
- else immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
- else immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C04 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-#define LCD_VIDEO_ADDR (SDRAM_MAX_SIZE-SDRAM_RES_SIZE)
-#define LCD_VIDEO_SIZE SDRAM_RES_SIZE /* 2MB */
-#define LCD_VIDEO_COLS 640
-#define LCD_VIDEO_ROWS 480
-#define LCD_VIDEO_FG 255
-#define LCD_VIDEO_BG 0
-
-#undef CONFIG_VIDEO /* test only ! s.a devices.c and 8xx */
-#define CONFIG_CFB_CONSOLE /* framebuffer console with std input */
-#define CONFIG_VIDEO_LOGO
-
-#define VIDEO_KBD_INIT_FCT 0 /* no KBD dev on MHPC - use serial */
-#define VIDEO_TSTC_FCT serial_stub_tstc
-#define VIDEO_GETC_FCT serial_stub_getc
-
-#define CONFIG_BR0_WORKAROUND 1
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_REGINFO
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x300000 /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Physical memory map
- */
-#define CONFIG_SYS_IMMR 0xFFF00000 /* Internal Memory Mapped Register*/
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xfe000000
-
-#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
-#undef CONFIG_SYS_MONITOR_BASE /* to run U-Boot from RAM */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor0=mhpc-0"
-#define MTDPARTS_DEFAULT "mtdparts=mhpc-0:-(jffs2)"
-*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map- for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN /* Offset of Environment */
-#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_SEME)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 12-18
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit - leave PLL multiplication factor unchanged !
- */
-#define MPC8XX_SPEED 50000000L
-#define MPC8XX_XIN 5000000L /* ref clk */
-#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN)
-#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
- PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-
-#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) /* SCCR_EBDF11 */
-#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_DFLCD001)
-
-
-/*-----------------------------------------------------------------------
- * MAMR settings for SDRAM - 16-14
- * => 0xC080200F
- *-----------------------------------------------------------------------
- * periodic timer for refresh
- */
-#define CONFIG_SYS_MAMR_PTA 0xC0
-#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK)
-
-/*
- * BR0 and OR0 (FLASH) used to re-map FLASH
- */
-
-/* allow for max 8 MB of Flash */
-#define FLASH_BASE 0xFE000000 /* FLASH bank #0*/
-#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0*/
-#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
-
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V )
-
-/*
- * BR1 and OR1 (SDRAM)
- */
-#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
-#define SDRAM_RES_SIZE 0x00200000 /* 2 MB for framebuffer */
-
-/* SDRAM timing: drive GPL5 high on first cycle */
-#define CONFIG_SYS_OR_TIMING_SDRAM (OR_G5LS)
-
-#define CONFIG_SYS_OR1_PRELIM ((~(SDRAM_MAX_SIZE)+1)| CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * BR2/OR2 - DIMM
- */
-#define CONFIG_SYS_OR2 (OR_ACS_DIV4)
-#define CONFIG_SYS_BR2 (BR_MS_UPMA)
-
-/*
- * BR3/OR3 - DIMM
- */
-#define CONFIG_SYS_OR3 (OR_ACS_DIV4)
-#define CONFIG_SYS_BR3 (BR_MS_UPMA)
-
-/*
- * BR4/OR4
- */
-#define CONFIG_SYS_OR4 0
-#define CONFIG_SYS_BR4 0
-
-/*
- * BR5/OR5
- */
-#define CONFIG_SYS_OR5 0
-#define CONFIG_SYS_BR5 0
-
-/*
- * BR6/OR6
- */
-#define CONFIG_SYS_OR6 0
-#define CONFIG_SYS_BR6 0
-
-/*
- * BR7/OR7
- */
-#define CONFIG_SYS_OR7 0
-#define CONFIG_SYS_BR7 0
-
-
-/*-----------------------------------------------------------------------
- * Debug Entry Mode
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-#endif /* __CONFIG_H */
#define CONFIG_SYS_TEXT_BASE 0xFFF90000
#endif
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_SYS_CLK_FREQ 33333400
#if 0 /* temporary disabled because OS/9 does not like dcache on startup */
#endif
#ifdef CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_I2C_ENV_EEPROM_BUS 0
#define CONFIG_ENV_OFFSET 0 /* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
#endif
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
- *
- * TOP5200 differences from IceCube:
- * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
- * bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
- * 1 SDRAM/DDRAM Bank up to 256 MB
- * local VPD I2C Bus is software driven and uses
- * GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
- * FLASH is re-located at 0xff000000
- * Internal regs are at 0xf0000000
- * Reset jumps to 0x00000100
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
-#define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */
-
-/*
- * allowed and functional CONFIG_SYS_TEXT_BASE values:
- * 0xff000000 low boot at 0x00000100 (default board setting)
- * 0xfff00000 high boot at 0xfff00100 (board needs modification)
- * 0x00100000 RAM load and test
- */
-#define CONFIG_SYS_TEXT_BASE 0xff000000
-
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
-#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-
-#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-# define CONFIG_PCI 1
-# define CONFIG_PCI_PNP 1
-# define CONFIG_PCI_SCAN_SHOW 1
-# define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-
-# define CONFIG_PCI_MEM_BUS 0x40000000
-# define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-# define CONFIG_PCI_MEM_SIZE 0x10000000
-
-# define CONFIG_PCI_IO_BUS 0x50000000
-# define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-# define CONFIG_PCI_IO_SIZE 0x01000000
-
-#endif
-
-/* USB */
-#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
-
-# define CONFIG_USB_OHCI
-# define CONFIG_USB_CLOCK 0x0001bbbb
-# if defined (CONFIG_EVAL5200)
-# define CONFIG_USB_CONFIG 0x00005100
-# else
-# define CONFIG_USB_CONFIG 0x00001000
-# endif
-# define CONFIG_DOS_PARTITION
-# define CONFIG_USB_STORAGE
-
-#endif
-
-/* IDE */
-#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
-# define CONFIG_DOS_PARTITION
-#endif
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_REGINFO
-
-#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_PCI
-#endif
-
-
-/*
- * MUST be low boot - HIGHBOOT is not supported anymore
- */
-#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
-# define CONFIG_SYS_LOWBOOT 1
-# define CONFIG_SYS_LOWBOOT16 1
-#else
-# error "CONFIG_SYS_TEXT_BASE must be 0xff000000"
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "rootpath=/opt/eldk/ppc_82xx\0" \
- "bootfile=/tftpboot/MPC5200/uImage\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-/*
- * IPB Bus clocking configuration.
- */
-#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-
-/*
- * I2C configuration
- */
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_SIZE 0x2000
-
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-
-#if defined(CONFIG_SYS_I2C_SOFT)
-# define CONFIG_SYS_I2C
-# define CONFIG_SYS_I2C_SOFT_SPEED 100000
-# define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
-/**/
-# define SDA0 0x40
-# define SCL0 0x80
-# define GPIOE0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c00))
-# define DDR0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c08))
-# define DVO0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c0c))
-# define DVI0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c20))
-# define ODE0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c04))
-# define I2C_INIT {GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
-# define I2C_READ ((DVI0&SDA0)?1:0)
-# define I2C_SDA(x) {if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
-# define I2C_SCL(x) {if(x)DVO0|=SCL0;else DVO0&=~SCL0;}
-# define I2C_DELAY {udelay(5);}
-# define I2C_ACTIVE {DDR0|=SDA0;}
-# define I2C_TRISTATE {DDR0&=~SDA0;}
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_FACT_ADDR 0x57
-#endif
-
-#if defined (CONFIG_HARD_I2C)
-# define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
-# define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-# define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
-#define CONFIG_SYS_I2C_FACT_ADDR 0x54
-#endif
-
-/*
- * Flash configuration, expect one 16 Megabyte Bank at most
- */
-#define CONFIG_SYS_FLASH_BASE 0xff000000
-#define CONFIG_SYS_FLASH_SIZE 0x01000000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0)
-
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
-
-/*
- * DRAM configuration - will be read from VPD later... TODO!
- */
-#if 0
-/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
-#define CONFIG_SYS_DRAM_DDR 0
-#define CONFIG_SYS_DRAM_EMODE 0
-#define CONFIG_SYS_DRAM_MODE 0x008D
-#define CONFIG_SYS_DRAM_CONTROL 0x514F0000
-#define CONFIG_SYS_DRAM_CONFIG1 0xC2233A00
-#define CONFIG_SYS_DRAM_CONFIG2 0x88B70004
-#define CONFIG_SYS_DRAM_TAP_DEL 0x08
-#define CONFIG_SYS_DRAM_RAM_SIZE 0x19
-#endif
-#if 1
-/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
-#define CONFIG_SYS_DRAM_DDR 0
-#define CONFIG_SYS_DRAM_EMODE 0
-#define CONFIG_SYS_DRAM_MODE 0x00CD
-#define CONFIG_SYS_DRAM_CONTROL 0x514F0000
-#define CONFIG_SYS_DRAM_CONFIG1 0xD2333A00
-#define CONFIG_SYS_DRAM_CONFIG2 0x8AD70004
-#define CONFIG_SYS_DRAM_TAP_DEL 0x08
-#define CONFIG_SYS_DRAM_RAM_SIZE 0x19
-#endif
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
-#define CONFIG_ENV_OFFSET 0x1000
-#define CONFIG_ENV_SIZE 0x0700
-
-/*
- * VPD settings
- */
-#define CONFIG_SYS_FACT_OFFSET 0x1800
-#define CONFIG_SYS_FACT_SIZE 0x0800
-
-/*
- * Memory map
- *
- * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
- */
-#define CONFIG_SYS_MBAR 0xf0000000 /* DO NOT CHANGE this */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC 1
-#define CONFIG_MPC5xxx_FEC_MII10 /* Workaround for FEC 100Mbit problem */
-#define CONFIG_PHY_ADDR 0x1f
-#define CONFIG_PHY_TYPE 0x79c874
-/*
- * GPIO configuration:
- * PSC1,2,3 predefined as UART
- * PCI disabled
- * Ethernet 100 with MD
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x00058044
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-
-#ifdef CONFIG_EVAL5200 /* M48T08 is available with the Evaluation board only */
- #define CONFIG_RTC_MK48T59 1 /* use M48T08 on EVAL5200 */
- #define RTC(reg) (0xf0010000+reg)
- /* setup CS2 for M48T08. Must MAP 64kB */
- #define CONFIG_SYS_CS2_START RTC(0)
- #define CONFIG_SYS_CS2_SIZE 0x10000
- /* setup CS2 configuration register: */
- /* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */
- /* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */
- #define CONFIG_SYS_CS2_CFG 0x00047800
-#else
- #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG 0x00047801
-#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_CS_BURST 0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
-
-#define CONFIG_SYS_RESET_ADDRESS 0x7f000000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-
-#define CONFIG_IDE_RESET 1
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x005c)
-
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE 4
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2003
- * EMK Elektronik GmbH <www.emk-elektronik.de>
- * Reinhard Meyer <r.meyer@emk-elektronik.de>
- *
- * Configuation settings for the TOP860 board.
- *
- * -----------------------------------------------------------------
- * SPDX-License-Identifier: GPL-2.0+
- */
-/*
- * TOP860 is a simple module:
- * 16-bit wide FLASH on CS0 (2MB or more)
- * 32-bit wide DRAM on CS2 (either 4MB or 16MB)
- * FEC with Am79C874 100-Base-T and Fiber Optic
- * Ports available, but we choose SMC1 for Console
- * 8k I2C EEPROM at address 0xae, 6k user available, 2k factory set
- * 32768Hz crystal PLL set for 49.152MHz Core and 24.576MHz Bus Clock
- *
- * This config has been copied from MBX.h / MBX860T.h
- */
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-/*-----------------------------------------------------------------------
- * CPU and BOARD type
- */
-#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
-#define CONFIG_MPC860T 1 /* even better... an FEC! */
-#define CONFIG_TOP860 1 /* ...on a TOP860 module */
-
-#define CONFIG_SYS_TEXT_BASE 0x80000000
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_IDENT_STRING " EMK TOP860"
-
-/*-----------------------------------------------------------------------
- * CLOCK settings
- */
-#define CONFIG_SYSCLK 49152000
-#define CONFIG_SYS_XTAL 32768
-#define CONFIG_EBDF 1
-#define CONFIG_COM 3
-#define CONFIG_RTC_MPC8xx
-
-/*-----------------------------------------------------------------------
- * Physical memory map as defined by EMK
- */
-#define CONFIG_SYS_IMMR 0xFFF00000 /* Internal Memory Mapped Register */
-#define CONFIG_SYS_FLASH_BASE 0x80000000 /* FLASH in final mapping */
-#define CONFIG_SYS_DRAM_BASE 0x00000000 /* DRAM in final mapping */
-#define CONFIG_SYS_FLASH_MAX 0x00400000 /* max FLASH to expect */
-#define CONFIG_SYS_DRAM_MAX 0x01000000 /* max DRAM to expect */
-
-/*-----------------------------------------------------------------------
- * derived values
- */
-#define CONFIG_SYS_MF (CONFIG_SYSCLK/CONFIG_SYS_XTAL)
-#define CONFIG_SYS_CPUCLOCK CONFIG_SYSCLK
-#define CONFIG_SYS_BRGCLOCK CONFIG_SYSCLK
-#define CONFIG_SYS_BUSCLOCK (CONFIG_SYSCLK >> CONFIG_EBDF)
-#define CONFIG_8xx_GCLK_FREQ CONFIG_SYSCLK
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_CFI
-
-/*-----------------------------------------------------------------------
- * Command interpreter
- */
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#define CONFIG_BAUDRATE 9600
-
-/*
- * Allow partial commands to be matched to uniqueness.
- */
-#define CONFIG_SYS_MATCH_PARTIAL_CMD
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_BEDBUG
-
-
-#define CONFIG_SOURCE 1
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
-#undef CONFIG_LOADS_ECHO /* NO echo on for serial download */
-
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot */
-
-
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
- #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-/*-----------------------------------------------------------------------
- * Memory Test Command
- */
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-/*-----------------------------------------------------------------------
- * Environment handler
- * only the first 6k in EEPROM are available for user. Of that we use 256b
- */
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
-#define CONFIG_ENV_OFFSET 0x1000
-#define CONFIG_ENV_SIZE 0x0700
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_FACT_OFFSET 0x1800
-#define CONFIG_SYS_FACT_SIZE 0x0800
-#define CONFIG_SYS_I2C_FACT_ADDR 0x57
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_SIZE 0x2000
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 100000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-/**/
-#define SDA 0x00010
-#define SCL 0x00020
-#define __I2C_DIR immr->im_cpm.cp_pbdir
-#define __I2C_DAT immr->im_cpm.cp_pbdat
-#define __I2C_PAR immr->im_cpm.cp_pbpar
-#define __I2C_ODR immr->im_cpm.cp_pbodr
-#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \
- __I2C_ODR &= ~(SDA|SCL); \
- __I2C_DAT |= (SDA|SCL); \
- __I2C_DIR|=(SDA|SCL); }
-#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0)
-#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; }
-#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; }
-#define I2C_DELAY { udelay(5); }
-#define I2C_ACTIVE { __I2C_DIR |= SDA; }
-#define I2C_TRISTATE { __I2C_DIR &= ~SDA; }
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*-----------------------------------------------------------------------
- * defines we need to get FEC running
- */
-#define CONFIG_FEC_ENET 1 /* Ethernet only via FEC */
-#define FEC_ENET 1 /* eth.c needs it that way... */
-#define CONFIG_SYS_DISCOVER_PHY 1
-#define CONFIG_MII 1
-#define CONFIG_MII_INIT 1
-#define CONFIG_PHY_ADDR 31
-
-/*-----------------------------------------------------------------------
- * adresses
- */
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x80000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */
-#define CONFIG_SYS_INIT_VPD_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_VPD_OFFSET-8)
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/* Interrupt level assignments.
-*/
-#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
-
-/*-----------------------------------------------------------------------
- * Debug Enable Register
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0 /* used in start.S */
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * set up PLPRCR (PLL, Low-Power, and Reset Control Register)
- * 12 MF calculated Multiplication factor
- * 4 0 0000
- * 1 SPLSS 0 System PLL lock status sticky
- * 1 TEXPS 1 Timer expired status
- * 1 0 0
- * 1 TMIST 0 Timers interrupt status
- * 1 0 0
- * 1 CSRC 0 Clock source (0=DFNH, 1=DFNL)
- * 2 LPM 00 Low-power modes
- * 1 CSR 0 Checkstop reset enable
- * 1 LOLRE 0 Loss-of-lock reset enable
- * 1 FIOPD 0 Force I/O pull down
- * 5 0 00000
- */
-#define CONFIG_SYS_PLPRCR (PLPRCR_TEXPS | ((CONFIG_SYS_MF-1)<<20))
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * set up SYPCR:
- * 16 SWTC 0xffff Software watchdog timer count
- * 8 BMT 0xff Bus monitor timing
- * 1 BME 1 Bus monitor enable
- * 3 0 000
- * 1 SWF 1 Software watchdog freeze
- * 1 SWE 0/1 Software watchdog enable
- * 1 SWRI 0/1 Software watchdog reset/interrupt select (1=HRESET)
- * 1 SWP 0/1 Software watchdog prescale (1=/2048)
- */
-#if defined (CONFIG_WATCHDOG)
- #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
- #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * set up SIUMCR
- * 1 EARB 0 External arbitration
- * 3 EARP 000 External arbitration request priority
- * 4 0 0000
- * 1 DSHW 0 Data show cycles
- * 2 DBGC 00 Debug pin configuration
- * 2 DBPC 00 Debug port pins configuration
- * 1 0 0
- * 1 FRC 0 FRZ pin configuration
- * 1 DLK 0 Debug register lock
- * 1 OPAR 0 Odd parity
- * 1 PNCS 0 Parity enable for non memory controller regions
- * 1 DPC 0 Data parity pins configuration
- * 1 MPRE 0 Multiprocessor reservation enable
- * 2 MLRC 11 Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT)
- * 1 AEME 0 Async external master enable
- * 1 SEME 0 Sync external master enable
- * 1 BSC 0 Byte strobe configuration
- * 1 GB5E 0 GPL_B5 enable
- * 1 B2DD 0 Bank 2 double drive
- * 1 B3DD 0 Bank 3 double drive
- * 4 0 0000
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC11)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * set up SCCR (System Clock and Reset Control Register)
- * 1 0 0
- * 2 COM 11 Clock output module (00=full, 01=half, 11=off)
- * 3 0 000
- * 1 TBS 1 Timebase source (0=OSCCLK, 1=GCLK2)
- * 1 RTDIV 0 Real-time clock divide (0=/4, 1=/512)
- * 1 RTSEL 0 Real-time clock select (0=OSCM, 1=EXTCLK)
- * 1 CRQEN 0 CPM request enable
- * 1 PRQEN 0 Power management request enable
- * 2 0 00
- * 2 EBDF xx External bus division factor
- * 2 0 00
- * 2 DFSYNC 00 Division factor for SYNCLK
- * 2 DFBRG 00 Division factor for BRGCLK
- * 3 DFNL 000 Division factor low frequency
- * 3 DFNH 000 Division factor high frequency
- * 5 0 00000
- */
-#define SCCR_MASK 0
-#ifdef CONFIG_EBDF
- #define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS | SCCR_EBDF01)
-#else
- #define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS)
-#endif
-
-/*-----------------------------------------------------------------------
- * Chip Select 0 - FLASH
- *-----------------------------------------------------------------------
- * Preliminary Values
- */
-/* FLASH timing: CSNT=1 ACS=10 BIH=1 SCY=4 SETA=0 TLRX=1 EHTR=1 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_4_CLK | OR_TRLX | OR_EHTR)
-#define CONFIG_SYS_OR0_PRELIM (-CONFIG_SYS_FLASH_MAX | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V )
-
-/*-----------------------------------------------------------------------
- * misc
- *-----------------------------------------------------------------------
- *
- */
-/*
- * Set the autoboot delay in seconds. A delay of -1 disables autoboot
- */
-#define CONFIG_BOOTDELAY 5
-
-/*
- * Pass the clock frequency to the Linux kernel in units of MHz
- */
-#define CONFIG_CLOCKS_IN_MHZ
-
-#define CONFIG_PREBOOT \
- "echo;echo"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Set default IP stuff just to get bootstrap entries into the
- * environment so that we can source the full default environment.
- */
-#define CONFIG_ETHADDR 9a:52:63:15:85:25
-#define CONFIG_SERVERIP 10.0.4.200
-#define CONFIG_IPADDR 10.0.4.111
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#endif /* __CONFIG_H */
/*
- * (C) Copyright 2003-2005
+ * (C) Copyright 2003-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004-2006
#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
/*
* Valid values for CONFIG_SYS_TEXT_BASE are:
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
+++ /dev/null
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Imported from global configuration:
- * CONFIG_MPC8255
- * CONFIG_MPC8265
- * CONFIG_200MHz
- * CONFIG_266MHz
- * CONFIG_300MHz
- * CONFIG_L2_CACHE
- * CONFIG_BUSMODE_60x
- */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-
-#if 0
-#define CONFIG_TQM8260 100 /* ...on a TQM8260 module Rev.100 */
-#else
-#define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */
-#endif
-
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_BOOTCOUNT_LIMIT
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "rootpath=/opt/eldk/ppc_6xx\0" \
- "bootfile=tqm8260/uImage\0" \
- "kernel_addr=400C0000\0" \
- "ramdisk_addr=40240000\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 400000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-
-/* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */
-#if (CONFIG_TQM8260 <= 100)
-
-#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00020000)
-#define I2C_TRISTATE (iop->pdir &= ~0x00020000)
-#define I2C_READ ((iop->pdat & 0x00020000) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00020000; \
- else iop->pdat &= ~0x00020000
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00010000; \
- else iop->pdat &= ~0x00010000
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-
-#else
-
-#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00010000)
-#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
-#define I2C_READ ((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
- else iop->pdat &= ~0x00010000
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
- else iop->pdat &= ~0x00020000
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-#endif
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-#define CONFIG_I2C_X
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#define CONFIG_CONS_ON_SMC /* define if console on SMC */
-#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else*/
-#ifdef CONFIG_82xx_CONS_SMC1
-#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
-#endif
-#ifdef CONFIG_82xx_CONS_SMC2
-#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
-#endif
-
-#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
-#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
-#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- *
- * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
- * X.29 connector, and FCC2 is hardwired to the X.1 connector)
- */
-#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
-#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
-#undef CONFIG_ETHER_NONE /* define if ether on something else */
-#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
-
-#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
-
-/*
- * - RX clk is CLK11
- * - TX clk is CLK12
- */
-# define CONFIG_SYS_CMXSCR_VALUE1 (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
-
-#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CONFIG_SYS_CPMFCR_RAMTYPE 0
-# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
-
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
-# define CONFIG_8260_CLKIN 66666666 /* in Hz */
-#else /* !CONFIG_MPC8255 && !CONFIG_MPC8265 */
-# ifndef CONFIG_300MHz
-# define CONFIG_8260_CLKIN 66666666 /* in Hz */
-# else
-# define CONFIG_8260_CLKIN 83333000 /* in Hz */
-# endif
-#endif /* CONFIG_MPC8255 */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8260/config.mk
- * The main FLASH is whichever is connected to *CS0.
- */
-#define CONFIG_SYS_FLASH0_BASE 0x40000000
-#define CONFIG_SYS_FLASH1_BASE 0x60000000
-#define CONFIG_SYS_FLASH0_SIZE 32
-#define CONFIG_SYS_FLASH1_SIZE 32
-
-/* Flash bank size (for preliminary settings)
- */
-#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-/* use CFI flash driver */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_FLASH_EMPTY_INFO 1
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
-#define CONFIG_ENV_SIZE 0x08000
-#define CONFIG_ENV_SECT_SIZE 0x40000
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
-#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
-#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
-
-#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
-# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111)
-#else /* ! MPC8255 && !MPC8265 */
-# if defined(CONFIG_266MHz)
-# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111)
-# elif defined(CONFIG_300MHz)
-# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0110)
-# else
-# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__)
-# endif
-#endif /* CONFIG_MPC8255 */
-
-/* no slaves so just fill with zeros */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- *
- * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
- * is mapped at SDRAM_BASE2_PRELIM.
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc()*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
- HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID2 0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration 4-25
- *-----------------------------------------------------------------------
- */
-#ifdef CONFIG_BUSMODE_60x
-#define CONFIG_SYS_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\
- BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */
-#else
-#define BCR_APD01 0x10000000
-#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 4-31
- *-----------------------------------------------------------------------
- */
-#if 0
-#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10)
-#else
-#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10)
-#endif
-
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control 9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR 0
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration 13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR 0
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus Machine PortSz Device
- * ---- --- ------- ------ ------
- * 0 60x GPCM 64 bit FLASH
- * 1 60x SDRAM 64 bit SDRAM
- * 2 Local SDRAM 32 bit SDRAM
- *
- */
-
- /* Initialize SDRAM on local bus
- */
-#define CONFIG_SYS_INIT_LOCAL_SDRAM
-
-#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
-
-/* Minimum mask to separate preliminary
- * address ranges for CS[0:2]
- */
-#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */
-#define CONFIG_SYS_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */
-
-#define CONFIG_SYS_MPTPR 0x4000
-
-/*-----------------------------------------------------------------------------
- * Address for Mode Register Set (MRS) command
- *-----------------------------------------------------------------------------
- * In fact, the address is rather configuration data presented to the SDRAM on
- * its address lines. Because the address lines may be mux'ed externally either
- * for 8 column or 9 column devices, some bits appear twice in the 8260's
- * address:
- *
- * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length |
- * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 |
- * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 |
- * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 |
- * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 |
- *-----------------------------------------------------------------------------
- */
-#define CONFIG_SYS_MRS_OFFS 0x00000110
-
-
-/* Bank 0 - FLASH
- */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_3_CLK |\
- ORxG_EHTR |\
- ORxG_TRLX)
-
- /* SDRAM on TQM8260 can have either 8 or 9 columns.
- * The number affects configuration values.
- */
-
-/* Bank 1 - 60x bus SDRAM
- */
-#define CONFIG_SYS_PSRT 0x20
-#define CONFIG_SYS_LSRT 0x20
-#ifndef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_SDRAM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL
-
-
- /* SDRAM initialization values for 8-column chips
- */
-#define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI1_A7 |\
- ORxS_NUMR_12)
-
-#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\
- PSDMR_SDAM_A15_IS_A5 |\
- PSDMR_BSMA_A12_A14 |\
- PSDMR_SDA10_PBI1_A8 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_2C |\
- PSDMR_EAMUX |\
- PSDMR_CL_2)
-
- /* SDRAM initialization values for 9-column chips
- */
-#define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI1_A5 |\
- ORxS_NUMR_13)
-
-#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\
- PSDMR_SDAM_A16_IS_A5 |\
- PSDMR_BSMA_A12_A14 |\
- PSDMR_SDA10_PBI1_A7 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_2C |\
- PSDMR_EAMUX |\
- PSDMR_CL_2)
-
-/* Bank 2 - Local bus SDRAM
- */
-#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
-#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
- BRx_PS_32 |\
- BRx_MS_SDRAM_L |\
- BRx_V)
-
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL
-
-#define SDRAM_BASE2_PRELIM 0x80000000
-
- /* SDRAM initialization values for 8-column chips
- */
-#define CONFIG_SYS_OR2_8COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI1_A8 |\
- ORxS_NUMR_12)
-
-#define CONFIG_SYS_LSDMR_8COL (PSDMR_PBI |\
- PSDMR_SDAM_A15_IS_A5 |\
- PSDMR_BSMA_A13_A15 |\
- PSDMR_SDA10_PBI1_A9 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_BL |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_2C |\
- PSDMR_CL_2)
-
- /* SDRAM initialization values for 9-column chips
- */
-#define CONFIG_SYS_OR2_9COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI1_A6 |\
- ORxS_NUMR_13)
-
-#define CONFIG_SYS_LSDMR_9COL (PSDMR_PBI |\
- PSDMR_SDAM_A16_IS_A5 |\
- PSDMR_BSMA_A13_A15 |\
- PSDMR_SDA10_PBI1_A8 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_BL |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_2C |\
- PSDMR_CL_2)
-
-#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8272_FAMILY 1
-#define CONFIG_TQM8272 1
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-#define CONFIG_GET_CPU_STR_F 1 /* Get the CPU ID STR */
-#define CONFIG_BOARD_GET_CPU_CLK_F 1 /* Get the CLKIN from board fct */
-
-#define STK82xx_150 1 /* on a STK82xx.150 */
-
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_BOARD_EARLY_INIT_R 1
-
-#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
-#define CONFIG_BAUDRATE 230400
-#else
-#define CONFIG_BAUDRATE 115200
-#endif
-
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consdev=ttyCPM0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "hostname=tqm8272\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addcons=setenv bootargs ${bootargs} " \
- "console=$(consdev),$(baudrate)\0" \
- "flash_nfs=run nfsargs addip addcons;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addcons;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 300000 ${bootfile};" \
- "run nfsargs addip addcons;bootm\0" \
- "rootpath=/opt/eldk/ppc_82xx\0" \
- "bootfile=/tftpboot/tqm8272/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40100000\0" \
- "load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0" \
- "update=protect off 40000000 4003ffff;era 40000000 4003ffff;" \
- "cp.b 300000 40000000 40000;" \
- "setenv filesize;saveenv\0" \
- "cphwib=cp.b 4003fc00 33fc00 400\0" \
- "upd=run load cphwib update\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#define CONFIG_I2C 1
-
-#if CONFIG_I2C
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 400000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00010000)
-#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
-#define I2C_READ ((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
- else iop->pdat &= ~0x00010000
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
- else iop->pdat &= ~0x00020000
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-
-#define CONFIG_I2C_X
-
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
-
-/* I2C RTC */
-#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
-
-/* I2C SYSMON (LM75) */
-#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
-#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
-#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_LOW_TEMP -30
-#define CONFIG_SYS_DTT_HYSTERESIS 3
-
-#else
-#undef CONFIG_SYS_I2C
-#undef CONFIG_HARD_I2C
-#undef CONFIG_SYS_I2C_SOFT
-#endif
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#define CONFIG_CONS_ON_SMC /* define if console on SMC */
-#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else*/
-#ifdef CONFIG_82xx_CONS_SMC1
-#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
-#endif
-#ifdef CONFIG_82xx_CONS_SMC2
-#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
-#endif
-
-#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
-#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
-#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- *
- * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
- * X.29 connector, and FCC2 is hardwired to the X.1 connector)
- */
-#define CONFIG_SYS_FCC_ETHERNET
-
-#if defined(CONFIG_SYS_FCC_ETHERNET)
-#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
-#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
-#undef CONFIG_ETHER_NONE /* define if ether on something else */
-#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
-#else
-#define CONFIG_ETHER_ON_SCC /* define if ether on SCC */
-#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */
-#undef CONFIG_ETHER_NONE /* define if ether on something else */
-#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
-#endif
-
-#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
-
-/*
- * - RX clk is CLK11
- * - TX clk is CLK12
- */
-# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
-
-#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CONFIG_SYS_CPMFCR_RAMTYPE 0
-# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
-
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
-/*
- * GPIO pins used for bit-banged MII communications
- */
-#define MDIO_PORT 2 /* Port C */
-#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-#define MDC_DECLARE MDIO_DECLARE
-
-#if STK82xx_150
-#define CONFIG_SYS_MDIO_PIN 0x00008000 /* PC16 */
-#define CONFIG_SYS_MDC_PIN 0x00004000 /* PC17 */
-#endif
-
-#if STK82xx_100
-#define CONFIG_SYS_MDIO_PIN 0x00000002 /* PC30 */
-#define CONFIG_SYS_MDC_PIN 0x00000001 /* PC31 */
-#endif
-
-#if 1
-#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
-#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
-#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
-
-#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
- else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
-
-#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
- else iop->pdat &= ~CONFIG_SYS_MDC_PIN
-#else
-#define MDIO_ACTIVE ({unsigned long tmp; tmp = iop->pdir; tmp |= CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
-#define MDIO_TRISTATE ({unsigned long tmp; tmp = iop->pdir; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
-#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
-
-#define MDIO(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}\
- else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}
-
-#define MDC(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}\
- else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}
-#endif
-
-#define MIIDELAY udelay(1)
-
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#define CONFIG_8260_CLKIN 66666666 /* in Hz */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SNTP
-
-#if CONFIG_I2C
- #define CONFIG_CMD_I2C
- #define CONFIG_CMD_DATE
- #define CONFIG_CMD_DTT
- #define CONFIG_CMD_EEPROM
-#endif
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#if 0
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x300000 /* default load address */
-
-#define CONFIG_SYS_RESET_ADDRESS 0x40000104 /* "bad" address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * CAN stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_CAN_BASE 0x51000000
-#define CONFIG_SYS_CAN_SIZE 1
-#define CONFIG_SYS_CAN_BR ((CONFIG_SYS_CAN_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_UPMC |\
- BRx_V)
-
-#define CONFIG_SYS_CAN_OR (MEG_TO_AM(CONFIG_SYS_CAN_SIZE) |\
- ORxU_BI)
-
-
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8272/config.mk
- * The main FLASH is whichever is connected to *CS0.
- */
-#define CONFIG_SYS_FLASH0_BASE 0x40000000
-#define CONFIG_SYS_FLASH0_SIZE 32 /* 32 MB */
-
-/* Flash bank size (for preliminary settings)
- */
-#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */
-#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-#define CONFIG_SYS_UPDATE_FLASH_SIZE
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
-#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND 0x20000
-
-/* Where is the Hardwareinformation Block (from Monitor Sources) */
-#define MON_RES_LENGTH (0x0003FC00)
-#define HWIB_INFO_START_ADDR (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH)
-#define HWIB_INFO_LEN 512
-#define CIB_INFO_START_ADDR (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN)
-#define CIB_INFO_LEN 512
-
-#define CONFIG_SYS_HWINFO_OFFSET 0x3fc00 /* offset of HW Info block */
-#define CONFIG_SYS_HWINFO_SIZE 0x00000060 /* size of HW Info block */
-#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#if defined(CONFIG_CMD_NAND)
-
-#define CONFIG_SYS_NAND_CS_DIST 0x80
-#define CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS 0x20
-#define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS 0x40
-
-#define CONFIG_SYS_NAND_BR ((CONFIG_SYS_NAND0_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_UPMB |\
- BRx_V)
-
-#define CONFIG_SYS_NAND_OR (MEG_TO_AM(CONFIG_SYS_NAND_SIZE) |\
- ORxU_BI |\
- ORxU_EHTR_8IDLE)
-
-#define CONFIG_SYS_NAND_SIZE 1
-#define CONFIG_SYS_NAND0_BASE 0x50000000
-#define CONFIG_SYS_NAND1_BASE (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST)
-#define CONFIG_SYS_NAND2_BASE (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST)
-#define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 4 /* Max number of NAND devices */
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
- CONFIG_SYS_NAND1_BASE, \
- CONFIG_SYS_NAND2_BASE, \
- CONFIG_SYS_NAND3_BASE, \
- }
-
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr)))
-#define WRITE_NAND_UPM(d, adr, off) do \
-{ \
- volatile unsigned char *addr = (unsigned char *) (adr + off); \
- WRITE_NAND(d, addr); \
-} while(0)
-
-#endif /* CONFIG_CMD_NAND */
-
-#define CONFIG_PCI
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_PCI_PNP
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define CONFIG_PCI_SCAN_SHOW
-#endif
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-#if 0
-#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
-
-# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111)
-#else
-#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111)
-#endif
-
-/* no slaves so just fill with zeros */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
- HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID2 0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration 4-25
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_BCR_60x (BCR_EBM|BCR_NPQM0|BCR_NPQM2) /* 60x mode */
-#define BCR_APD01 0x10000000
-#define CONFIG_SYS_BCR_SINGLE (BCR_APD01|BCR_ETM) /* 8260 mode */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 4-31
- *-----------------------------------------------------------------------
- */
-#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
-#define CONFIG_SYS_SIUMCR_LOW (SIUMCR_DPPC00)
-#define CONFIG_SYS_SIUMCR_HIGH (SIUMCR_DPPC00 | SIUMCR_ABE)
-#else
-#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00)
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control 9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR SCCR_DFBRG01
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration 13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR 0
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus Machine PortSz Device
- * ---- --- ------- ------ ------
- * 0 60x GPCM 32 bit FLASH
- * 1 60x SDRAM 64 bit SDRAM
- * 2 60x UPMB 8 bit NAND
- * 3 60x UPMC 8 bit CAN
- *
- */
-
-/* Initialize SDRAM
- */
-#undef CONFIG_SYS_INIT_LOCAL_SDRAM /* No SDRAM on Local Bus */
-
-#define SDRAM_MAX_SIZE 0x20000000 /* max. 512 MB */
-
-/* Minimum mask to separate preliminary
- * address ranges for CS[0:2]
- */
-#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */
-
-#define CONFIG_SYS_MPTPR 0x4000
-
-/*-----------------------------------------------------------------------------
- * Address for Mode Register Set (MRS) command
- *-----------------------------------------------------------------------------
- * In fact, the address is rather configuration data presented to the SDRAM on
- * its address lines. Because the address lines may be mux'ed externally either
- * for 8 column or 9 column devices, some bits appear twice in the 8260's
- * address:
- *
- * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length |
- * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 |
- * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 |
- * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 |
- * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 |
- *-----------------------------------------------------------------------------
- */
-#define CONFIG_SYS_MRS_OFFS 0x00000110
-
-/* Bank 0 - FLASH
- */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
- BRx_PS_32 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV4 |\
- ORxG_SCY_8_CLK |\
- ORxG_TRLX)
-
-/* SDRAM on TQM8272 can have either 8 or 9 columns.
- * The number affects configuration values.
- */
-
-/* Bank 1 - 60x bus SDRAM
- */
-#define CONFIG_SYS_PSRT 0x20 /* Low Value */
-/* #define CONFIG_SYS_PSRT 0x10 Fast Value */
-#define CONFIG_SYS_LSRT 0x20 /* Local Bus */
-#ifndef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_SDRAM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL
-
-/* SDRAM initialization values for 8-column chips
- */
-#define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI1_A7 |\
- ORxS_NUMR_12)
-
-#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\
- PSDMR_SDAM_A15_IS_A5 |\
- PSDMR_BSMA_A12_A14 |\
- PSDMR_SDA10_PBI1_A8 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_2C |\
- PSDMR_EAMUX |\
- PSDMR_BUFCMD |\
- PSDMR_CL_2)
-
-
-/* SDRAM initialization values for 9-column chips
- */
-#define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI1_A5 |\
- ORxS_NUMR_13)
-
-#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\
- PSDMR_SDAM_A16_IS_A5 |\
- PSDMR_BSMA_A12_A14 |\
- PSDMR_SDA10_PBI1_A7 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_2C |\
- PSDMR_EAMUX |\
- PSDMR_BUFCMD |\
- PSDMR_CL_2)
-
-#define CONFIG_SYS_OR1_10COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI1_A4 |\
- ORxS_NUMR_13)
-
-#define CONFIG_SYS_PSDMR_10COL (PSDMR_PBI |\
- PSDMR_SDAM_A17_IS_A5 |\
- PSDMR_BSMA_A12_A14 |\
- PSDMR_SDA10_PBI1_A4 |\
- PSDMR_RFRC_6_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_2C |\
- PSDMR_EAMUX |\
- PSDMR_BUFCMD |\
- PSDMR_CL_2)
-
-#define PSDMR_RFRC_66MHZ_SINGLE 0x00028000 /* PSDMR[RFRC] at 66 MHz single mode */
-#define PSDMR_RFRC_100MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 100 MHz single mode */
-#define PSDMR_RFRC_133MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 133 MHz single mode */
-#define PSDMR_RFRC_66MHZ_60X 0x00030000 /* PSDMR[RFRC] at 66 MHz 60x mode */
-#define PSDMR_RFRC_100MHZ_60X 0x00028000 /* PSDMR[RFRC] at 100 MHz 60x mode */
-#define PSDMR_RFRC_DEFAULT PSDMR_RFRC_133MHZ_SINGLE /* PSDMR[RFRC] default value */
-
-#define PSDMR_PRETOACT_66MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 66 MHz single mode */
-#define PSDMR_PRETOACT_100MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 100 MHz single mode */
-#define PSDMR_PRETOACT_133MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 133 MHz single mode */
-#define PSDMR_PRETOACT_66MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 66 MHz 60x mode */
-#define PSDMR_PRETOACT_100MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 100 MHz 60x mode */
-#define PSDMR_PRETOACT_DEFAULT PSDMR_PRETOACT_133MHZ_SINGLE /* PSDMR[PRETOACT] default value */
-
-#define PSDMR_WRC_66MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 66 MHz single mode */
-#define PSDMR_WRC_100MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 100 MHz single mode */
-#define PSDMR_WRC_133MHZ_SINGLE 0x00000010 /* PSDMR[WRC] at 133 MHz single mode */
-#define PSDMR_WRC_66MHZ_60X 0x00000010 /* PSDMR[WRC] at 66 MHz 60x mode */
-#define PSDMR_WRC_100MHZ_60X 0x00000010 /* PSDMR[WRC] at 100 MHz 60x mode */
-#define PSDMR_WRC_DEFAULT PSDMR_WRC_133MHZ_SINGLE /* PSDMR[WRC] default value */
-
-#define PSDMR_BUFCMD_66MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 66 MHz single mode */
-#define PSDMR_BUFCMD_100MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 100 MHz single mode */
-#define PSDMR_BUFCMD_133MHZ_SINGLE 0x00000004 /* PSDMR[BUFCMD] at 133 MHz single mode */
-#define PSDMR_BUFCMD_66MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 66 MHz 60x mode */
-#define PSDMR_BUFCMD_100MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 100 MHz 60x mode */
-#define PSDMR_BUFCMD_DEFAULT PSDMR_BUFCMD_133MHZ_SINGLE /* PSDMR[BUFCMD] default value */
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-#endif /* __CONFIG_H */
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
#define CONFIG_TQM855L 1 /* ...on a TQM8xxL module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
#define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
#define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
#define CONFIG_MPC860 1
#define CONFIG_MPC860T 1
#define CONFIG_MPC862 1
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
#define CONFIG_MPC860 1
#define CONFIG_MPC860T 1
#define CONFIG_MPC862 1
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
/*
- * (C) Copyright 2000-2005
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2006
#define CONFIG_MPC885 1 /* This is a MPC885 CPU */
#define CONFIG_TQM885D 1 /* ...on a TQM88D module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
#define __CONFIG_H
#define CONFIG_AC14XX 1
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
+
/*
* Memory map for the ifm AC14xx board:
*
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NFS
#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_TEXT_BASE 0x70000000
+#else
#define CONFIG_SYS_TEXT_BASE 0xE6304000
+#endif
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_TMU_TIMER
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
+#else
#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
+#endif
#define STACK_AREA_SIZE 0xC000
#define LOW_LEVEL_MERAM_STACK \
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
+/* Filesystems */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
+
+/* USB */
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_RMOBILE
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
#endif /* __ALT_H */
#define CONFIG_AM335X_USB1
#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+#ifndef CONFIG_SPL_USBETH_SUPPORT
+/* Fastboot */
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_ANDROID_BOOT_IMAGE
+#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
+#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000
+
+/* To support eMMC booting */
+#define CONFIG_STORAGE_EMMC
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#endif
+
#ifdef CONFIG_MUSB_HOST
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00"
/* USB TI's IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x0403
-#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
+#define CONFIG_G_DNL_VENDOR_NUM 0x0451
+#define CONFIG_G_DNL_PRODUCT_NUM 0xD022
#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
#endif /* CONFIG_MUSB_GADGET */
"boot part 0 1;" \
"rootfs part 0 2;" \
"MLO fat 0 1;" \
- "MLO.raw mmc 0x100 0x100;" \
- "u-boot.img.raw mmc 0x300 0x400;" \
- "spl-os-args.raw mmc 0x80 0x80;" \
- "spl-os-image.raw mmc 0x900 0x2000;" \
+ "MLO.raw raw 0x100 0x100;" \
+ "u-boot.img.raw raw 0x300 0x400;" \
+ "spl-os-args.raw raw 0x80 0x80;" \
+ "spl-os-image.raw raw 0x900 0x2000;" \
"spl-os-args fat 0 1;" \
"spl-os-image fat 0 1;" \
"u-boot.img fat 0 1;" \
"fdt ram 0x80F80000 0x80000;" \
"ramdisk ram 0x81000000 0x4000000\0"
#define DFUARGS \
- "dfu_alt_info_emmc=rawemmc mmc 0 3751936\0" \
+ "dfu_alt_info_emmc=rawemmc raw 0 3751936\0" \
DFU_ALT_INFO_MMC \
DFU_ALT_INFO_RAM \
DFU_ALT_INFO_NAND
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_AM43XX
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_SAVEENV
+
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_CACHELINE_SIZE 32
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
-#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_FAT
+#define FAT_ENV_INTERFACE "mmc"
+#define FAT_ENV_DEVICE_AND_PART "0:1"
+#define FAT_ENV_FILE "uboot.env"
+#define CONFIG_FAT_WRITE
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#ifdef CONFIG_QSPI_BOOT
#define CONFIG_SYS_TEXT_BASE 0x30000000
-#undef CONFIG_ENV_IS_NOWHERE
+#undef CONFIG_ENV_IS_IN_FAT
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#define __CONFIG_H
#define CONFIG_ARIA 1
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
+
/*
* Memory map for the ARIA board:
*
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 3
-#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 20)<<8))
+#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
/*
* I2C configuration
*/
-#define CONFIG_HARD_I2C
-#define CONFIG_DW_I2C
-#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DW
#define CONFIG_I2C_ENV_EEPROM_BUS 2
#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SPEED1 100000
+#define CONFIG_SYS_I2C_SPEED2 100000
#define CONFIG_SYS_I2C_SLAVE 0
+#define CONFIG_SYS_I2C_SLAVE1 0
+#define CONFIG_SYS_I2C_SLAVE2 0
#define CONFIG_SYS_I2C_BASE 0xE001D000
#define CONFIG_SYS_I2C_BASE1 0xE001E000
#define CONFIG_SYS_I2C_BASE2 0xE001F000
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
--- /dev/null
+/*
+ * (C) Copyright 2013 CompuLab, Ltd.
+ * Author: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * Configuration settings for the CompuLab CM-T3517 board
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_OMAP /* in a TI OMAP core */
+#define CONFIG_CM_T3517 /* working with CM-T3517 */
+#define CONFIG_OMAP_COMMON
+#define CONFIG_SYS_GENERIC_BOARD
+
+#define CONFIG_SYS_TEXT_BASE 0x80008000
+
+/*
+ * This is needed for the DMA stuff.
+ * Although the default iss 64, we still define it
+ * to be on the safe side once the default is changed.
+ */
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
+#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_OF_LIBFDT
+/*
+ * The early kernel mapping on ARM currently only maps from the base of DRAM
+ * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000.
+ * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
+ * so that leaves DRAM base to DRAM base + 0x4000 available.
+ */
+#define CONFIG_SYS_BOOTMAPSZ 0x4000
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SERIAL_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CONFIG_SERIAL3 3 /* UART3 */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+
+#define CONFIG_OMAP_GPIO
+
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#define CONFIG_USB_MUSB_AM35X
+
+#ifndef CONFIG_USB_MUSB_AM35X
+#define CONFIG_USB_OMAP3
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_OMAP
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
+#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
+#else /* !CONFIG_USB_MUSB_AM35X */
+#define CONFIG_MUSB_HOST
+#define CONFIG_MUSB_PIO_ONLY
+#endif /* CONFIG_USB_MUSB_AM35X */
+
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nand0=nand"
+#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
+ "1920k(u-boot),256k(u-boot-env),"\
+ "4m(kernel),-(fs)"
+
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_NAND /* NAND support */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_GPIO
+
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP34XX
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_EEPROM_BUS 0
+#define CONFIG_I2C_MULTI_BUS
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_QUIET_TEST
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
+ /* to access nand */
+#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
+ /* to access nand at */
+ /* CS0 */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
+ /* devices */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "baudrate=115200\0" \
+ "console=ttyO2,115200n8\0" \
+ "mpurate=auto\0" \
+ "vram=12M\0" \
+ "dvimode=1024x768MR-16@60\0" \
+ "defaultdisplay=dvi\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
+ "mmcrootfstype=ext4\0" \
+ "nandroot=/dev/mtdblock4 rw\0" \
+ "nandrootfstype=ubifs\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source ${loadaddr}\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "run nandargs; " \
+ "nand read ${loadaddr} 2a0000 400000; " \
+ "bootm ${loadaddr}\0" \
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run nandboot; " \
+ "fi; " \
+ "fi; " \
+ "else run nandboot; fi"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_TIMESTAMP
+#define CONFIG_SYS_AUTOLOAD "no"
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT "CM-T3517 # "
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
+
+/*
+ * AM3517 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* CM-T3517 DRAM is only on CS0 */
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define CONFIG_SYS_CS0_SIZE (256 << 20)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
+
+#define CONFIG_ENV_IS_IN_NAND
+#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define CONFIG_MII
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_SMC911X_BASE (0x2C000000 + (16 << 20))
+#endif /* CONFIG_CMD_NET */
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+/* Status LED */
+#define CONFIG_STATUS_LED /* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED
+#define CONFIG_GPIO_LED
+#define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */
+#define GREEN_LED_DEV 0
+#define STATUS_LED_BIT GREEN_LED_GPIO
+#define STATUS_LED_STATE STATUS_LED_ON
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BOOT GREEN_LED_DEV
+
+/* GPIO banks */
+#ifdef CONFIG_STATUS_LED
+#define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */
+#endif
+
+/* Display Configuration */
+#define CONFIG_OMAP3_GPIO_2
+#define CONFIG_OMAP3_GPIO_5
+#define CONFIG_VIDEO_OMAP3
+#define LCD_BPP LCD_COLOR16
+
+#define CONFIG_LCD
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASHIMAGE_GUARD
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_SCF0403_LCD
+
+#define CONFIG_OMAP3_SPI
+
+#endif /* __CONFIG_H */
#define CONFIG_PHYSMEM
#define CONFIG_SYS_EARLY_PCI_INIT
#define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_DM
+#define CONFIG_CMD_DM
+#define CONFIG_DM_GPIO
+#define CONFIG_DM_SERIAL
#define CONFIG_LMB
#define CONFIG_OF_LIBFDT
#define CONFIG_FIT
#undef CONFIG_ZLIB
#undef CONFIG_GZIP
+#define CONFIG_SYS_BOOTM_LEN (16 << 20)
/*-----------------------------------------------------------------------
* Watchdog Configuration
/*-----------------------------------------------------------------------
* Serial Configuration
*/
-#define CONFIG_CONS_INDEX 1
+#define CONFIG_COREBOOT_SERIAL
#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK 1843200
-#define CONFIG_BAUDRATE 9600
+#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \
9600, 19200, 38400, 115200}
-#define CONFIG_SYS_NS16550_COM1 UART0_BASE
-#define CONFIG_SYS_NS16550_COM2 UART1_BASE
#define CONFIG_SYS_NS16550_PORT_MAPPED
-#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,eserial0\0" \
- "stdout=vga,eserial0,cbmem\0" \
- "stderr=vga,eserial0,cbmem\0"
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
+ "stdout=vga,serial,cbmem\0" \
+ "stderr=vga,serial,cbmem\0"
#define CONFIG_CONSOLE_MUX
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SYS_MEMTEST_START 0x00100000
#define CONFIG_SYS_MEMTEST_END 0x01000000
-#define CONFIG_SYS_LOAD_ADDR 0x02000000
+#define CONFIG_SYS_LOAD_ADDR 0x20000000
/*-----------------------------------------------------------------------
* SDRAM Configuration
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (0x20000 + 128 * 1024)
-
+#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
0x400000)
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
-#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "uImage"
-#define CONFIG_SPL_FAT_LOAD_ARGS_NAME "args"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */
#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
/*
* Valid values for CONFIG_SYS_TEXT_BASE are:
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FAT
#define CONFIG_FAT_WRITE
+#define CONFIG_CMD_FS_GENERIC
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Murray Jensen <Murray.Jensen@cmst.csiro.au>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Config header file for Hymod board
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_HYMOD 1 /* ...on a Hymod board */
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
-
-#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
-#define CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else*/
-#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
-#define CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
-#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
-#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
-#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
-#undef CONFIG_ETHER_NONE /* define if ether on something else */
-#define CONFIG_ETHER_INDEX 1 /* which channel for ether */
-#define CONFIG_ETHER_LOOPBACK_TEST /* add ether external loopback test */
-
-#ifdef CONFIG_ETHER_ON_FCC
-
-#if (CONFIG_ETHER_INDEX == 1)
-
-/*
- * - Rx-CLK is CLK10
- * - Tx-CLK is CLK11
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11)
-# define CONFIG_SYS_CPMFCR_RAMTYPE 0
-# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-# define MDIO_PORT 0 /* Port A */
-# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-# define MDC_DECLARE MDIO_DECLARE
-
-# define MDIO_DATA_PINMASK 0x00040000 /* Pin 13 */
-# define MDIO_CLCK_PINMASK 0x00080000 /* Pin 12 */
-
-#elif (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CONFIG_SYS_CPMFCR_RAMTYPE 0
-# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-# define MDIO_PORT 0 /* Port A */
-# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-# define MDC_DECLARE MDIO_DECLARE
-
-# define MDIO_DATA_PINMASK 0x00000040 /* Pin 25 */
-# define MDIO_CLCK_PINMASK 0x00000080 /* Pin 24 */
-
-#elif (CONFIG_ETHER_INDEX == 3)
-
-/*
- * - Rx-CLK is CLK15
- * - Tx-CLK is CLK16
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
-# define CONFIG_SYS_CPMFCR_RAMTYPE 0
-# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-# define MDIO_PORT 0 /* Port A */
-# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-# define MDC_DECLARE MDIO_DECLARE
-
-# define MDIO_DATA_PINMASK 0x00000100 /* Pin 23 */
-# define MDIO_CLCK_PINMASK 0x00000200 /* Pin 22 */
-
-#endif /* CONFIG_ETHER_INDEX */
-
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
-
-#define MDIO_ACTIVE (iop->pdir |= MDIO_DATA_PINMASK)
-#define MDIO_TRISTATE (iop->pdir &= ~MDIO_DATA_PINMASK)
-#define MDIO_READ ((iop->pdat & MDIO_DATA_PINMASK) != 0)
-
-#define MDIO(bit) if(bit) iop->pdat |= MDIO_DATA_PINMASK; \
- else iop->pdat &= ~MDIO_DATA_PINMASK
-
-#define MDC(bit) if(bit) iop->pdat |= MDIO_CLCK_PINMASK; \
- else iop->pdat &= ~MDIO_CLCK_PINMASK
-
-#define MIIDELAY udelay(1)
-
-#endif /* CONFIG_ETHER_ON_FCC */
-
-
-/* other options */
-#define CONFIG_HARD_I2C 1 /* To enable I2C hardware support */
-#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#ifdef DEBUG
-#define CONFIG_8260_CLKIN 33333333 /* in Hz */
-#else
-#define CONFIG_8260_CLKIN 66666666 /* in Hz */
-#endif
-
-#if defined(CONFIG_CONS_USE_EXTC)
-#define CONFIG_BAUDRATE 115200
-#else
-#define CONFIG_BAUDRATE 9600
-#endif
-
-/* default ip addresses - these will be overridden */
-#define CONFIG_IPADDR 192.168.1.1 /* hymod "boot" address */
-#define CONFIG_SERVERIP 192.168.1.254 /* hymod "server" address */
-
-#define CONFIG_LAST_STAGE_INIT
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_CDP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_DTT
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_KGDB
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_PORTIO
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
-
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_XIMG
-
-#ifdef DEBUG
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_BOOT_RETRY_TIME 30 /* retry autoboot after 30 secs */
-#define CONFIG_BOOT_RETRY_MIN 1 /* can go down to 1 second timeout */
-/* Be selective on what keys can delay or stop the autoboot process
- * To stop use: " "
- */
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \
- "press <SPACE> to stop\n", bootdelay
-#define CONFIG_AUTOBOOT_STOP_STR " "
-#undef CONFIG_AUTOBOOT_DELAY_STR
-#define DEBUG_BOOTKEYS 0
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
-#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
-#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
-#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
-#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */
-#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
-# if defined(CONFIG_KGDB_USE_EXTC)
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
-# else
-#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */
-# endif
-#endif
-
-#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
-
-#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
-
-/*
- * Hymod specific configurable options
- */
-#undef CONFIG_SYS_HYMOD_DBLEDS /* walk mezz board LEDs */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x03c00000 /* 4 ... 60 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0x7e
-
-/* these are for the ST M24C02 2kbit serial i2c eeprom */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16 byte write page size */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* hymod has two eeproms */
-
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* philips PCF8563 RTC address */
-
-/*
- * standard dtt sensor configuration - bottom bit will determine local or
- * remote sensor of the ADM1021, the rest determines index into
- * CONFIG_SYS_DTT_ADM1021 array below.
- *
- * On HYMOD board, the remote sensor should be connected to the MPC8260
- * temperature diode thingy, but an errata said this didn't work and
- * should be disabled - so it isn't connected.
- */
-#if 0
-#define CONFIG_DTT_SENSORS { 0, 1 }
-#else
-#define CONFIG_DTT_SENSORS { 0 }
-#endif
-
-/*
- * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
- * there will be one entry in this array for each two (dummy) sensors in
- * CONFIG_DTT_SENSORS.
- *
- * For HYMOD board:
- * - only one ADM1021
- * - i2c addr 0x2a (both ADD0 and ADD1 are N/C)
- * - conversion rate 0x02 = 0.25 conversions/second
- * - ALERT ouput disabled
- * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
- * - remote temp sensor disabled (see comment for CONFIG_DTT_SENSORS above)
- */
-#define CONFIG_SYS_DTT_ADM1021 { { 0x2a, 0x02, 0, 1, 0, 85, 0, } }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-#ifdef DEBUG
-#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
- HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
- HRCW_MODCK_H0010)
-#else
-#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
- HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
- HRCW_MODCK_H0101)
-#endif
-/* no slaves so just duplicate the master hrcw */
-#define CONFIG_SYS_HRCW_SLAVE1 CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE2 CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE3 CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE4 CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE5 CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE6 CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE7 CONFIG_SYS_HRCW_MASTER
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_FPGA_BASE 0x80000000
-/*
- * unfortunately, CONFIG_SYS_MONITOR_LEN must include the
- * (very large i.e. 256kB) environment flash sector
- */
-#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor*/
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
- HID0_IFEM|HID0_ABE)
-#ifdef DEBUG
-#define CONFIG_SYS_HID0_FINAL 0
-#else
-#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
-#endif
-#define CONFIG_SYS_HID2 0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#ifdef DEBUG
-#define CONFIG_SYS_RMR 0
-#else
-#define CONFIG_SYS_RMR RMR_CSRE
-#endif
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration 4-25
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_BCR (BCR_ETM)
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 4-31
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_L2CPC01|\
- SIUMCR_APPC10|SIUMCR_MMR11)
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control 9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR (SCCR_DFBRG01)
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration 13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR 0
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus Machine PortSz Device
- * ---- --- ------- ------ ------
- * 0 60x GPCM 32 bit FLASH
- * 1 60x GPCM 32 bit FLASH (same as 0 - unused for now)
- * 2 60x SDRAM 64 bit SDRAM
- * 3 Local UPMC 8 bit Main Xilinx configuration
- * 4 Local GPCM 32 bit Main Xilinx register mode
- * 5 Local UPMB 32 bit Main Xilinx port mode
- * 6 Local UPMC 8 bit Mezz Xilinx configuration
- */
-
-/*
- * Bank 0 - FLASH
- *
- * Quotes from the HYMOD IO Board Reference manual:
- *
- * "The flash memory is two Intel StrataFlash chips, each configured for
- * 16 bit operation and connected to give a 32 bit wide port."
- *
- * "The chip select logic is configured to respond to both *CS0 and *CS1.
- * Therefore the FLASH memory will be mapped to both bank 0 and bank 1.
- * It is suggested that bank 0 be read-only and bank 1 be read/write. The
- * FLASH will then appear as ROM during boot."
- *
- * Initially, we are only going to use bank 0 in read/write mode.
- */
-
-/* 32 bit, read-write, GPCM on 60x bus */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE&BRx_BA_MSK)|\
- BRx_PS_32|BRx_MS_GPCM_P|BRx_V)
-/* up to 32 Mb */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
-
-/*
- * Bank 2 - SDRAM
- *
- * Quotes from the HYMOD IO Board Reference manual:
- *
- * "The main memory is implemented using TC59SM716FTL-10 SDRAM and has a
- * fixed size of 64 Mbytes. The Toshiba TC59SM716FTL-10 is a CMOS synchronous
- * dynamic random access memory organised as 4 banks by 4096 rows by 512
- * columns by 16 bits. Four chips provide a 64-bit port on the 60x bus."
- *
- * "The locations in SDRAM are accessed using multiplexed address pins to
- * specify row and column. The pins also act to specify commands. The state
- * of the inputs *RAS, *CAS and *WE defines the required action. The a10/AP
- * pin may function as a row address or as the AUTO PRECHARGE control line,
- * depending on the cycle type. The 60x bus SDRAM machine allows the MPC8260
- * address lines to be configured to the required multiplexing scheme."
- */
-
-#define CONFIG_SYS_SDRAM_SIZE 64
-
-/* 64 bit, read-write, SDRAM on 60x bus */
-#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE&BRx_BA_MSK)|\
- BRx_PS_64|BRx_MS_SDRAM_P|BRx_V)
-/* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE)|\
- ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12)
-
-/*
- * The 60x Bus SDRAM Mode Register (PDSMR) is set as follows:
- *
- * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5
- * is output on A16 pin (A6 on A17, and so on), use address pins A14-A16
- * as bank select, A7 is output on SDA10 during an ACTIVATE command,
- * earliest timing for ACTIVATE command after REFRESH command is 6 clocks,
- * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
- * is 2 clocks, earliest timing for READ/WRITE command after ACTIVATE
- * command is 2 clocks, earliest timing for PRECHARGE after last data
- * was read is 1 clock, earliest timing for PRECHARGE after last data
- * was written is 1 clock, CAS Latency is 2.
- */
-
-#define CONFIG_SYS_PSDMR (PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\
- PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\
- PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\
- PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\
- PSDMR_WRC_1C|PSDMR_CL_2)
-
-/*
- * The 60x bus-assigned SDRAM Refresh Timer (PSRT) (10-31) and the Refresh
- * Timers Prescale (PTP) value in the Memory Refresh Timer Prescaler Register
- * (MPTPR) (10-32) must also be set up (it used to be called the Periodic Timer
- * Prescaler, hence the P instead of the R). The refresh timer period is given
- * by (note that there was a change in the 8260 UM Errata):
- *
- * TimerPeriod = (PSRT + 1) / Fmptc
- *
- * where Fmptc is the BusClock divided by PTP. i.e.
- *
- * TimerPeriod = (PSRT + 1) / (BusClock / PTP)
- *
- * or
- *
- * TImerPeriod = (PTP * (PSRT + 1)) / BusClock
- *
- * The requirement for the Toshiba TC59SM716FTL-10 is that there must be
- * 4K refresh cycles every 64 ms. i.e. one refresh cycle every 64000/4096
- * = 15.625 usecs.
- *
- * So PTP * (PSRT + 1) <= 15.625 * BusClock. At 66.666MHz, PSRT=31 and PTP=32
- * appear to be reasonable.
- */
-
-#ifdef DEBUG
-#define CONFIG_SYS_PSRT 39
-#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8
-#else
-#define CONFIG_SYS_PSRT 31
-#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
-#endif
-
-/*
- * Banks 3,4,5 and 6 - FPGA access
- *
- * Quotes from the HYMOD IO Board Reference manual:
- *
- * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made
- * for configuring an optional FPGA on the mezzanine interface.
- *
- * Access to the FPGAs may be divided into several catagories:
- *
- * 1. Configuration
- * 2. Register mode access
- * 3. Port mode access
- *
- * The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be
- * configured only (mode 1). Consequently there are four access types.
- *
- * To improve interface performance and simplify software design, the four
- * possible access types are separately mapped to different memory banks.
- *
- * All are accessed using the local bus."
- *
- * Device Mode Memory Bank Machine Port Size Access
- *
- * Main Configuration 3 UPMC 8bit R/W
- * Main Register 4 GPCM 32bit R/W
- * Main Port 5 UPMB 32bit R/W
- * Mezzanine Configuration 6 UPMC 8bit W/O
- *
- * "Note that mezzanine mode 1 access is write-only."
- */
-
-/* all the bank sizes must be a power of two, greater or equal to 32768 */
-#define FPGA_MAIN_CFG_BASE (CONFIG_SYS_FPGA_BASE)
-#define FPGA_MAIN_CFG_SIZE 32768
-#define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE)
-#define FPGA_MAIN_REG_SIZE 32768
-#define FPGA_MAIN_PORT_BASE (FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE)
-#define FPGA_MAIN_PORT_SIZE 32768
-#define FPGA_MEZZ_CFG_BASE (FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE)
-#define FPGA_MEZZ_CFG_SIZE 32768
-
-/* 8 bit, read-write, UPMC */
-#define CONFIG_SYS_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
-/* up to 32Kbyte, burst inhibit */
-#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI)
-
-/* 32 bit, read-write, GPCM */
-#define CONFIG_SYS_BR4_PRELIM (FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V)
-/* up to 32Kbyte */
-#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(FPGA_MAIN_REG_SIZE))
-
-/* 32 bit, read-write, UPMB */
-#define CONFIG_SYS_BR5_PRELIM (FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V)
-/* up to 32Kbyte */
-#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI)
-
-/* 8 bit, write-only, UPMC */
-#define CONFIG_SYS_BR6_PRELIM (FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
-/* up to 32Kbyte, burst inhibit */
-#define CONFIG_SYS_OR6_PRELIM (P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI)
-
-/*-----------------------------------------------------------------------
- * MBMR - Machine B Mode 10-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_MBMR (MxMR_BSEL|MxMR_OP_NORM) /* XXX - needs more */
-
-/*-----------------------------------------------------------------------
- * MCMR - Machine C Mode 10-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_MCMR (MxMR_BSEL|MxMR_DSx_2_CYCL) /* XXX - needs more */
-
-/*
- * FPGA I/O Port/Bit information
- */
-
-#define FPGA_MAIN_PROG_PORT IOPIN_PORTA
-#define FPGA_MAIN_PROG_PIN 4 /* PA4 */
-#define FPGA_MAIN_INIT_PORT IOPIN_PORTA
-#define FPGA_MAIN_INIT_PIN 5 /* PA5 */
-#define FPGA_MAIN_DONE_PORT IOPIN_PORTA
-#define FPGA_MAIN_DONE_PIN 6 /* PA6 */
-
-#define FPGA_MEZZ_PROG_PORT IOPIN_PORTA
-#define FPGA_MEZZ_PROG_PIN 0 /* PA0 */
-#define FPGA_MEZZ_INIT_PORT IOPIN_PORTA
-#define FPGA_MEZZ_INIT_PIN 1 /* PA1 */
-#define FPGA_MEZZ_DONE_PORT IOPIN_PORTA
-#define FPGA_MEZZ_DONE_PIN 2 /* PA2 */
-#define FPGA_MEZZ_ENABLE_PORT IOPIN_PORTA
-#define FPGA_MEZZ_ENABLE_PIN 3 /* PA3 */
-
-/*
- * FPGA Interrupt configuration
- */
-#define FPGA_MAIN_IRQ SIU_INT_IRQ2
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT ""
-#define MTDPARTS_DEFAULT ""
-*/
-
-#endif /* __CONFIG_H */
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
#define CONFIG_SPL_TEXT_BASE 0x00908000
-#define CONFIG_SPL_MAX_SIZE (64 * 1024)
+#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7"
#define CONFIG_SPL_STACK 0x0091FFB8
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#if defined(CONFIG_SPL_MMC_SUPPORT)
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 138 /* offset 69KB */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS/2*1024)
#endif
/* Define the payload for FAT/EXT support */
#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_LIBDISK_SUPPORT
#endif
/* U-Boot general configuration */
#define CONFIG_SYS_PROMPT "K2E EVM # "
-#define KS2_ARGS_UBI "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
- "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0"
-
-#define KS2_FDT_NAME "name_fdt=k2e-evm.dtb\0"
-#define KS2_ADDR_MON "addr_mon=0x0c140000\0"
-#define KS2_NAME_MON "name_mon=skern-k2e-evm.bin\0"
-#define NAME_UBOOT "name_uboot=u-boot-spi-k2e-evm.gph\0"
-#define NAME_UBI "name_ubi=k2e-evm-ubifs.ubi\0"
+#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
+ "addr_mon=0x0c140000\0" \
+ "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \
+ "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" \
+ "name_fdt=uImage-k2e-evm.dtb\0" \
+ "name_mon=skern-k2e-evm.bin\0" \
+ "name_ubi=k2e-evm-ubifs.ubi\0" \
+ "name_uboot=u-boot-spi-k2e-evm.gph\0" \
+ "name_fs=arago-console-image-k2e-evm.cpio.gz\0"
#include <configs/ks2_evm.h>
/* NAND Configuration */
#define CONFIG_SYS_NAND_PAGE_2K
+/* Network */
+#define CONFIG_KSNET_NETCP_V1_5
+#define CONFIG_KSNET_CPSW_NUM_PORTS 9
+#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
+
#endif /* __CONFIG_K2E_EVM_H */
/* U-Boot general configuration */
#define CONFIG_SYS_PROMPT "K2HK EVM # "
-#define KS2_ARGS_UBI "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
- "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0"
-
-#define KS2_FDT_NAME "name_fdt=k2hk-evm.dtb\0"
-#define KS2_ADDR_MON "addr_mon=0x0c5f0000\0"
-#define KS2_NAME_MON "name_mon=skern-k2hk-evm.bin\0"
-#define NAME_UBOOT "name_uboot=u-boot-spi-k2hk-evm.gph\0"
-#define NAME_UBI "name_ubi=k2hk-evm-ubifs.ubi\0"
+#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
+ "addr_mon=0x0c5f0000\0" \
+ "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \
+ "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" \
+ "name_fdt=uImage-k2hk-evm.dtb\0" \
+ "name_mon=skern-k2hk-evm.bin\0" \
+ "name_ubi=k2hk-evm-ubifs.ubi\0" \
+ "name_uboot=u-boot-spi-k2hk-evm.gph\0" \
+ "name_fs=arago-console-image-k2hk-evm.cpio.gz\0"
#include <configs/ks2_evm.h>
#define CONFIG_SYS_NAND_PAGE_2K
/* Network */
-#define CONFIG_DRIVER_TI_KEYSTONE_NET
+#define CONFIG_KSNET_NETCP_V1_0
+#define CONFIG_KSNET_CPSW_NUM_PORTS 5
#endif /* __CONFIG_K2HK_EVM_H */
--- /dev/null
+/*
+ * Configuration header file for TI's k2l-evm
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_K2L_EVM_H
+#define __CONFIG_K2L_EVM_H
+
+/* Platform type */
+#define CONFIG_SOC_K2L
+#define CONFIG_K2L_EVM
+
+/* U-Boot general configuration */
+#define CONFIG_SYS_PROMPT "K2L EVM # "
+
+#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
+ "addr_mon=0x0c140000\0" \
+ "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \
+ "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,4096\0" \
+ "name_fdt=uImage-k2l-evm.dtb\0" \
+ "name_mon=skern-k2l-evm.bin\0" \
+ "name_ubi=k2l-evm-ubifs.ubi\0" \
+ "name_uboot=u-boot-spi-k2l-evm.gph\0" \
+ "name_fs=arago-console-image-k2l-evm.cpio.gz\0"
+
+#include <configs/ks2_evm.h>
+
+/* SPL SPI Loader Configuration */
+#define CONFIG_SPL_TEXT_BASE 0x0c100000
+
+/* NAND Configuration */
+#define CONFIG_SYS_NAND_PAGE_4K
+
+/* Network */
+#define CONFIG_KSNET_NETCP_V1_5
+#define CONFIG_KSNET_CPSW_NUM_PORTS 5
+#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
+
+#endif /* __CONFIG_K2L_EVM_H */
#define CONFIG_FAT_WRITE
#define CONFIG_EXT4_WRITE
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_TEXT_BASE 0x70000000
+#else
#define CONFIG_SYS_TEXT_BASE 0xE6304000
+#endif
+
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_TMU_TIMER
/* STACK */
-#define CONFIG_SYS_INIT_SP_ADDR 0xE633fffc
-#define STACK_AREA_SIZE 0xC000
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
+#else
+#define CONFIG_SYS_INIT_SP_ADDR 0xE633fffC
+#endif
+
+#define STACK_AREA_SIZE 0xC000
#define LOW_LEVEL_MERAM_STACK \
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
#define CONFIG_SYS_SPI2_NUM_CS 4
/* Network Configuration */
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MARVELL
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 32
#define CONFIG_NET_MULTI
-#define CONFIG_GET_LINK_STATUS_ATTEMPTS 5
#define CONFIG_SYS_SGMII_REFCLK_MHZ 312
#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250
#define CONFIG_SYS_SGMII_RATESCALE 2
+/* Keyston Navigator Configuration */
+#define CONFIG_TI_KSNAV
+#define CONFIG_KSNAV_QM_BASE_ADDRESS KS2_QM_BASE_ADDRESS
+#define CONFIG_KSNAV_QM_CONF_BASE KS2_QM_CONF_BASE
+#define CONFIG_KSNAV_QM_DESC_SETUP_BASE KS2_QM_DESC_SETUP_BASE
+#define CONFIG_KSNAV_QM_STATUS_RAM_BASE KS2_QM_STATUS_RAM_BASE
+#define CONFIG_KSNAV_QM_INTD_CONF_BASE KS2_QM_INTD_CONF_BASE
+#define CONFIG_KSNAV_QM_PDSP1_CMD_BASE KS2_QM_PDSP1_CMD_BASE
+#define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE KS2_QM_PDSP1_CTRL_BASE
+#define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE KS2_QM_PDSP1_IRAM_BASE
+#define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE KS2_QM_MANAGER_QUEUES_BASE
+#define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE KS2_QM_MANAGER_Q_PROXY_BASE
+#define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE KS2_QM_QUEUE_STATUS_BASE
+#define CONFIG_KSNAV_QM_LINK_RAM_BASE KS2_QM_LINK_RAM_BASE
+#define CONFIG_KSNAV_QM_REGION_NUM KS2_QM_REGION_NUM
+#define CONFIG_KSNAV_QM_QPOOL_NUM KS2_QM_QPOOL_NUM
+
+/* NETCP pktdma */
+#define CONFIG_KSNAV_PKTDMA_NETCP
+#define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE KS2_NETCP_PDMA_CTRL_BASE
+#define CONFIG_KSNAV_NETCP_PDMA_TX_BASE KS2_NETCP_PDMA_TX_BASE
+#define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM KS2_NETCP_PDMA_TX_CH_NUM
+#define CONFIG_KSNAV_NETCP_PDMA_RX_BASE KS2_NETCP_PDMA_RX_BASE
+#define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM KS2_NETCP_PDMA_RX_CH_NUM
+#define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE KS2_NETCP_PDMA_SCHED_BASE
+#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE KS2_NETCP_PDMA_RX_FLOW_BASE
+#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM KS2_NETCP_PDMA_RX_FLOW_NUM
+#define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE KS2_NETCP_PDMA_RX_FREE_QUEUE
+#define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE KS2_NETCP_PDMA_RX_RCV_QUEUE
+#define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE
+
+/* Keystone net */
+#define CONFIG_DRIVER_TI_KEYSTONE_NET
+#define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR
+#define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE
+#define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE
+#define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE
+#define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES
+
+/* SerDes */
+#define CONFIG_TI_KEYSTONE_SERDES
+
/* AEMIF */
#define CONFIG_TI_AEMIF
#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
"1024k(bootloader)ro,512k(params)ro," \
"-(ubifs)"
+/* USB Configuration */
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_KEYSTONE
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_FS_FAT
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_USB_SS_BASE KS2_USB_SS_BASE
+#define CONFIG_USB_HOST_XHCI_BASE KS2_USB_HOST_XHCI_BASE
+#define CONFIG_DEV_USB_PHY_BASE KS2_DEV_USB_PHY_BASE
+#define CONFIG_USB_PHY_CFG_BASE KS2_USB_PHY_CFG_BASE
+
/* U-Boot command configuration */
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_UBIFS
#define CONFIG_CMD_SF
#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
/* U-Boot general configuration */
#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_MISC_INIT_R
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_PBSIZE 2048
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_EXTRA_ENV_SETTINGS \
- "boot=ramfs\0" \
+ CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
+ "boot=ubi\0" \
"tftp_root=/\0" \
"nfs_root=/export\0" \
"mem_lpae=1\0" \
"mem_reserve=512M\0" \
"addr_fdt=0x87000000\0" \
"addr_kern=0x88000000\0" \
- KS2_ADDR_MON \
"addr_uboot=0x87000000\0" \
"addr_fs=0x82000000\0" \
"addr_ubi=0x82000000\0" \
"addr_secdb_key=0xc000000\0" \
"fdt_high=0xffffffff\0" \
- KS2_FDT_NAME \
- "name_fs=arago-console-image.cpio.gz\0" \
- "name_kern=uImage\0" \
- KS2_NAME_MON \
- NAME_UBOOT \
- NAME_UBI \
+ "name_kern=uImage-keystone-evm.bin\0" \
"run_mon=mon_install ${addr_mon}\0" \
"run_kern=bootm ${addr_kern} - ${addr_fdt}\0" \
"init_net=run args_all args_net\0" \
"init_ubi=run args_all args_ubi; " \
- "ubi part ubifs; ubifsmount boot;" \
+ "ubi part ubifs; ubifsmount ubi:boot;" \
"ubifsload ${addr_secdb_key} securedb.key.bin;\0" \
"get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \
"get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0" \
"burn_uboot_nand=nand erase 0 0x100000; " \
"nand write ${addr_uboot} 0 ${filesize}\0" \
"args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \
- KS2_ARGS_UBI \
"args_net=setenv bootargs ${bootargs} rootfstype=nfs " \
"root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \
"${nfs_options} ip=dhcp\0" \
#include <asm/arch/clock.h>
#define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6)
-/* Maximum memory size for relocated U-boot at the end of the DDR3 memory
- which is NOT applicable for DDR ECC test */
-#define CONFIG_MAX_UBOOT_MEM_SIZE (4 << 20) /* 4 MiB */
-
#endif /* __CONFIG_KS2_EVM_H */
#define CONFIG_FAT_WRITE
#define CONFIG_EXT4_WRITE
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_TEXT_BASE 0xB0000000
+#else
#define CONFIG_SYS_TEXT_BASE 0xE8080000
+#endif
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_TMU_TIMER
/* STACK */
-#define CONFIG_SYS_INIT_SP_ADDR 0xE827fffc
-#define STACK_AREA_SIZE 0xC000
+#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC
+#else
+#define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC
+#endif
+#define STACK_AREA_SIZE 0xC000
#define LOW_LEVEL_MERAM_STACK \
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
#define CONFIG_EXTRA_ENV_SETTINGS \
"consdev=ttyAMA0\0" \
"baudrate=115200\0" \
+ "bootscript=boot.scr\0" \
"bootdev=/dev/mmcblk0p2\0" \
"rootdev=/dev/mmcblk0p3\0" \
"netdev=eth0\0" \
#define CONFIG_BOOTFILE "uImage"
-#define xstr(s) str(s)
-#define str(s) #s
-
/* Setup MTD for NAND on the SOM */
#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"baudrate=115200\0" \
"consoledev=ttyO2\0" \
- "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
+ "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
"loadaddr=0x82000000\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
"load_k=tftp ${loadaddr} ${bootfile}\0" \
"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
"loadmlo=tftp ${loadaddr} ${mlo}\0" \
- "mlo=" xstr(CONFIG_HOSTNAME) "/MLO\0" \
+ "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \
"mmcargs=root=/dev/mmcblk0p2 rw " \
"rootfstype=ext3 rootwait\0" \
"mmcboot=echo Booting from mmc ...; " \
"bootm ${loadaddr}\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.img\0" \
+ "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \
"uboot_addr=0x80000\0" \
"update=nandecc sw;nand erase ${uboot_addr} 100000;" \
"nand write ${loadaddr} ${uboot_addr} 80000\0" \
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
/* NAND boot config */
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define __CONFIG_H
#define CONFIG_MECP5123 1
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
+
/*
* Memory map for the MECP5123 board:
*
#define __CONFIG_H
#define CONFIG_MPC5121ADS 1
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
+
/*
* Memory map for the MPC5121ADS board:
*
#endif
#define CONFIG_MP
+#define CONFIG_MXC_GPT_HCLK
#endif
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
+
#include "mx6sabre_common.h"
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_CMD_CACHE
#endif
+/* Framebuffer */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+
#endif /* __MX6QSABRE_COMMON_CONFIG_H */
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */
#endif
-/* Framebuffer */
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_IPUV3
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SPLASH_SCREEN_ALIGN
-#define CONFIG_BMP_16BPP
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IPUV3_CLK 260000000
-#define CONFIG_IMX_HDMI
-#define CONFIG_IMX_VIDEO_SKIP
-
#define CONFIG_CMD_PCI
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI
#define CONFIG_ENV_OFFSET (6 * SZ_64K)
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#endif
+#define CONFIG_SYS_FSL_USDHC_NUM 3
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC2*/
+#endif
+
#endif /* __CONFIG_H */
/* I2C */
#ifdef CONFIG_CMD_I2C
-#define CONFIG_I2C_MXS
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXS
#define CONFIG_HARD_I2C
#ifndef CONFIG_SYS_I2C_SPEED
#define CONFIG_SYS_I2C_SPEED 400000
--- /dev/null
+/*
+ * Configuration settings for the Novena U-boot.
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* System configurations */
+#define CONFIG_MX6
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_FIT
+#define CONFIG_KEYBOARD
+#define CONFIG_MXC_GPIO
+#define CONFIG_OF_LIBFDT
+#define CONFIG_REGEX
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SYS_NO_FLASH
+
+#include "configs/mx6_common.h"
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+#include <config_cmd_default.h>
+
+/* U-Boot Commands */
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_FUSE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SATA
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_TIME
+#define CONFIG_CMD_USB
+#define CONFIG_VIDEO
+
+/* U-Boot general configurations */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+ /* Print buffer size */
+#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE /* Command auto complete */
+#define CONFIG_CMDLINE_EDITING /* Command history etc */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* U-Boot environment */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_SIZE (16 * 1024)
+/*
+ * Environment is on MMC, starting at offset 512KiB from start of the card.
+ * Please place first partition at offset 1MiB from the start of the card
+ * as recommended by GNU/fdisk. See below for details:
+ * http://homepage.ntlworld.com./jonathan.deboynepollard/FGA/disc-partition-alignment.html
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_OFFSET (512 * 1024)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+#define CONFIG_ENV_OFFSET_REDUND \
+ (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_BOOTFILE "fitImage"
+#define CONFIG_BOOTARGS "console=ttymxc1,115200 "
+#define CONFIG_BOOTCOMMAND "run net_nfs"
+#define CONFIG_LOADADDR 0x18000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_HOSTNAME novena
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE 0xF0000000
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END 0x20000000
+
+#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
+
+/* SPL */
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#include "imx6_spl.h" /* common IMX6 SPL configuration */
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Ethernet Configuration */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 0x7
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#define CONFIG_ARP_TIMEOUT 200UL
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* I2C EEPROM */
+#ifdef CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_SPD_BUS_NUM 2
+#endif
+
+/* MMC Configs */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#endif
+
+/* OCOTP Configs */
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+/* PCI express */
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(3, 29)
+#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(7, 12)
+#endif
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+
+/* SATA Configs */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE 1
+#define CONFIG_DWC_AHSATA_PORT_ID 0
+#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
+/* UART */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART2_BASE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONS_INDEX 1
+
+/* USB Configs */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+/* Gadget part */
+#define CONFIG_CI_UDC
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_CDC
+#define CONFIG_NETCONSOLE
+#endif
+
+/* Video output */
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_CMD_HDMIDETECT
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+#endif
+
+/* Extra U-Boot environment. */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "consdev=ttymxc1\0" \
+ "baudrate=115200\0" \
+ "bootdev=/dev/mmcblk0p1\0" \
+ "rootdev=/dev/mmcblk0p2\0" \
+ "netdev=eth0\0" \
+ "kernel_addr_r=0x18000000\0" \
+ "addcons=" \
+ "setenv bootargs ${bootargs} " \
+ "console=${consdev},${baudrate}\0" \
+ "addip=" \
+ "setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}:${netdev}:off\0" \
+ "addmisc=" \
+ "setenv bootargs ${bootargs} ${miscargs}\0" \
+ "addargs=run addcons addmisc\0" \
+ "mmcload=" \
+ "mmc rescan ; " \
+ "ext4load mmc 0:1 ${kernel_addr_r} ${bootfile}\0" \
+ "netload=" \
+ "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
+ "miscargs=nohlt panic=1\0" \
+ "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \
+ "nfsargs=" \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath},v3,tcp\0" \
+ "mmc_mmc=" \
+ "run mmcload mmcargs addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "mmc_nfs=" \
+ "run mmcload nfsargs addip addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "net_mmc=" \
+ "run netload mmcargs addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "net_nfs=" \
+ "run netload nfsargs addip addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "update_sd_spl_filename=SPL\0" \
+ "update_sd_uboot_filename=u-boot.img\0" \
+ "update_sd_firmware=" /* Update the SD firmware partition */ \
+ "if mmc rescan ; then " \
+ "if dhcp ${update_sd_spl_filename} ; then " \
+ "mmc write ${loadaddr} 2 0x200 ; " \
+ "fi ; " \
+ "if dhcp ${update_sd_uboot_filename} ; then " \
+ "fatwrite mmc 0:1 ${loadaddr} u-boot.img ${filesize} ; "\
+ "fi ; " \
+ "fi\0" \
+
+#endif /* __CONFIG_H */
#define CONFIG_BOARD_NAME "o2d"
#define CONFIG_BOARD_BOOTCMD "run dhcp_boot"
-#define CONFIG_BOARD_MEM_LIMIT xstr(126)
-#define BOARD_POST_CRC32_END xstr(0x01000000)
+#define CONFIG_BOARD_MEM_LIMIT __stringify(126)
+#define BOARD_POST_CRC32_END __stringify(0x01000000)
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_IFM_DEFAULT_ENV_SETTINGS \
"ramtop=fc55ffff\0" \
"jffbot=fc560000\0" \
"jfftop=fcffffff\0" \
- "ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0" \
+ "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \
"ubotop=fc03ffff\0" \
"kernel_addr=0xfc060000\0" \
"ramdisk_addr=0xfc160000\0" \
#define CONFIG_BOARD_NAME "o2d300"
#define CONFIG_BOARD_BOOTCMD "run dhcp_boot"
-#define CONFIG_BOARD_MEM_LIMIT xstr(126)
-#define BOARD_POST_CRC32_END xstr(0x02000000)
+#define CONFIG_BOARD_MEM_LIMIT __stringify(126)
+#define BOARD_POST_CRC32_END __stringify(0x02000000)
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_IFM_DEFAULT_ENV_SETTINGS \
"ramtop=fc57ffff\0" \
"jffbot=fc580000\0" \
"jfftop=fd39ffff\0" \
- "ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0" \
+ "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \
"ubotop=fc03ffff\0" \
"halname="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME"_halcon\0" \
"halbot=fd3a0000\0" \
* High Level Configuration Options
*/
#define CONFIG_MPC5200
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* running at 33.000000MHz */
#undef CONFIG_BOOTARGS
-#define xstr(s) str(s)
-#define str(s) #s
-
#if !defined(CONFIG_CONSOLE_DEV)
#define CONFIG_CONSOLE_DEV "ttyPSC1"
#endif
"kernel_addr_r=600000\0" \
"initrd_high=0x03e00000\0" \
"memlimit=mem="CONFIG_BOARD_MEM_LIMIT"M\0" \
- "memtest=mtest 0x00100000 "xstr(CONFIG_SYS_MEMTEST_END)" 0 1\0" \
+ "memtest=mtest 0x00100000 "__stringify(CONFIG_SYS_MEMTEST_END)" 0 1\0" \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"unlock=yes\0" \
"post=echo !!! "CONFIG_BOARD_NAME" POWER ON SELF TEST !!!;" \
"setenv bootdelay 1;" \
- "crc32 "xstr(CONFIG_SYS_TEXT_BASE)" " \
+ "crc32 "__stringify(CONFIG_SYS_TEXT_BASE)" " \
BOARD_POST_CRC32_END";" \
"setenv bootcmd "CONFIG_BOARD_BOOTCMD";saveenv;reset\0"
#define CONFIG_BOARD_NAME "o2dnt2"
#define CONFIG_BOARD_BOOTCMD "run flash_self"
-#define CONFIG_BOARD_MEM_LIMIT xstr(126)
-#define BOARD_POST_CRC32_END xstr(0x01000000)
+#define CONFIG_BOARD_MEM_LIMIT __stringify(126)
+#define BOARD_POST_CRC32_END __stringify(0x01000000)
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_IFM_DEFAULT_ENV_SETTINGS \
"ramtop=fc55ffff\0" \
"jffbot=fc560000\0" \
"jfftop=fce5ffff\0" \
- "ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0" \
+ "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \
"ubotop=fc03ffff\0" \
"calname="CONFIG_BOARD_NAME"/uCal_"CONFIG_BOARD_NAME"_act\0" \
"calbot=fce60000\0" \
#define CONFIG_BOARD_NAME "o2i"
#define CONFIG_BOARD_BOOTCMD "run dhcp_boot"
-#define CONFIG_BOARD_MEM_LIMIT xstr(62)
-#define BOARD_POST_CRC32_END xstr(0x01000000)
+#define CONFIG_BOARD_MEM_LIMIT __stringify(62)
+#define BOARD_POST_CRC32_END __stringify(0x01000000)
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_IFM_DEFAULT_ENV_SETTINGS \
"jfftop=ffebffff\0" \
"kernel_addr=0xff060000\0" \
"ramdisk_addr=0xff160000\0" \
- "ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0" \
+ "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \
"ubotop=ff03ffff\0" \
"autoload=no\0" \
"dhcp_boot=run dhcpcmd; run flash_mtd\0" \
#define CONFIG_BOARD_NAME "o2mnt"
#define CONFIG_BOARD_BOOTCMD "${newcmd}"
-#define CONFIG_BOARD_MEM_LIMIT xstr(62)
-#define BOARD_POST_CRC32_END xstr(0x01000000)
+#define CONFIG_BOARD_MEM_LIMIT __stringify(62)
+#define BOARD_POST_CRC32_END __stringify(0x01000000)
#ifndef CONFIG_IFM_SENSOR_TYPE
#define CONFIG_IFM_SENSOR_TYPE "O2M110"
"ramtop=ffc5ffff\0" \
"jffbot=ffc60000\0" \
"jfftop=ffffffff\0" \
- "ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0" \
+ "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \
"ubotop=ff03ffff\0" \
"kernel_addr=0xff060000\0" \
"ramdisk_addr=0xff260000\0" \
#define CONFIG_BOARD_NAME "o3dnt"
#define CONFIG_BOARD_BOOTCMD "run flash_self"
-#define CONFIG_BOARD_MEM_LIMIT xstr(62)
-#define BOARD_POST_CRC32_END xstr(0x01000000)
+#define CONFIG_BOARD_MEM_LIMIT __stringify(62)
+#define BOARD_POST_CRC32_END __stringify(0x01000000)
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_IFM_DEFAULT_ENV_SETTINGS \
"ramtop=fc55ffff\0" \
"jffbot=fc560000\0" \
"jfftop=fce5ffff\0" \
- "ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0" \
+ "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \
"ubotop=fc03ffff\0" \
"calname="CONFIG_BOARD_NAME"/uCal_"CONFIG_BOARD_NAME"_act\0" \
"calbot=fce60000\0" \
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
/* Partition tables */
#define CONFIG_EFI_PARTITION
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif /* __OMAP3_EVM_QUICK_MMC_H */
#define CONFIG_REVISION_TAG 1
-#define CONFIG_SUPPORT_RAW_INITRD
-
/* define to enable boot progress via leds */
#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
(CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
/* TWL4030 LED */
#define CONFIG_TWL4030_LED
+/* USB EHCI */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 183
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+
/* Initialize GPIOs by default */
#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO Bank 2 */
#define CONFIG_OMAP3_GPIO_3 /* GPIO64..95 is in GPIO Bank 3 */
/* commands to include */
#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_USB
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#undef CONFIG_CMD_IMI /* iminfo */
#undef CONFIG_CMD_NFS /* NFS support */
"bootz ${loadaddr} - ${fdtaddr}\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
- "nand read ${loadaddr} linux; " \
- "bootm ${loadaddr}\0" \
+ "if nand read ${loadaddr} linux; then " \
+ "bootm ${loadaddr};" \
+ "fi;\0" \
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
#define CONFIG_SPI_FLASH_SST
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 2
-#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(1, 3)<<8))
+#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 25000000
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Based on original work by
- * Roel Loeffen, (C) Copyright 2006 Prodrive B.V.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/************************************************************************
- * p3mx.h - configuration for Prodrive P3M750 & P3M7448 boards
- *
- * The defines:
- * CONFIG_P3M750 or
- * CONFIG_P3M7448
- * are written into include/config.h by the "make xxx_config" command
- ***********************************************************************/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_P3Mx /* used for both board versions */
-
-#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
-#if defined (CONFIG_P3M750)
-#define CONFIG_750FX /* 750GL/GX/FX */
-#define CONFIG_HIGH_BATS /* High BATs supported */
-#define CONFIG_SYS_BOARD_NAME "P3M750"
-#define CONFIG_SYS_BUS_CLK 100000000
-#define CONFIG_SYS_TCLK 100000000
-#elif defined (CONFIG_P3M7448)
-#define CONFIG_74xx
-#define CONFIG_SYS_BOARD_NAME "P3M7448"
-#define CONFIG_SYS_BUS_CLK 133333333
-#define CONFIG_SYS_TCLK 133333333
-#endif
-#define CONFIG_SYS_GT_DUAL_CPU /* also for JTAG even with one cpu */
-
-/* which initialization functions to call for this board */
-#define CONFIG_SYS_BOARD_ASM_INIT 1
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#ifdef CONFIG_P3M750
-#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#if defined (CONFIG_P3M750)
-#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of flash banks */
-#define CONFIG_SYS_BOOT_SIZE _8M /* boot flash */
-#elif defined (CONFIG_P3M7448)
-#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of flash banks */
-#define CONFIG_SYS_BOOT_SIZE _16M /* boot flash */
-#endif
-#define CONFIG_SYS_BOOT_SPACE CONFIG_SYS_FLASH_BASE /* BOOT_CS0 flash 0 */
-#define CONFIG_SYS_MONITOR_BASE 0xfff00000
-#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
-#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
-#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
-
-#define CONFIG_SYS_DFL_GT_REGS 0xf1000000 /* boot time GT_REGS */
-#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers are mapped here */
-#define CONFIG_SYS_INT_SRAM_BASE 0x42000000 /* GT offers 256k internal SRAM */
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
- /*
- * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
- * To an unused memory region. The stack will remain in cache until RAM
- * is initialized
-*/
-#undef CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0x42000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_MPSC /* MV64460 Serial */
-#define CONFIG_MPSC_PORT 0
-#define CONFIG_BAUDRATE 115200 /* console baudrate */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*-----------------------------------------------------------------------
- * Ethernet
- *----------------------------------------------------------------------*/
-/* Change the default ethernet port, use this define (options: 0, 1, 2) */
-#define CONFIG_SYS_ETH_PORT ETH_0
-#define MV_ETH_DEVS 2
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#if defined (CONFIG_P3M750)
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (1 device) */
-#elif defined (CONFIG_P3M7448)
-#define CONFIG_ENV_SECT_SIZE 0x40000 /* two sectors (2 devices parallel */
-#endif
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_MV64460_ECC
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed default */
-
-/* I2C RTC */
-#define CONFIG_RTC_M41T11 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *----------------------------------------------------------------------*/
-#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#undef CONFIG_PCI /* include pci support */
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */
-#endif /* CONFIG_PCI */
-
-/* PCI MEMORY MAP section */
-#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI0_MEM_SIZE _128M
-#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
-#define CONFIG_SYS_PCI1_MEM_SIZE _128M
-
-#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
-#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
-
-/* PCI I/O MAP section */
-#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
-#define CONFIG_SYS_PCI0_IO_SIZE _16M
-#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
-#define CONFIG_SYS_PCI1_IO_SIZE _16M
-
-#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
-#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000
-#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
-#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000
-
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE)
-#define CONFIG_SYS_PCI_IDSEL 0x30
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
- "rootpath=/opt/eldk/ppc_6xx\0" \
- "u-boot=p3mx/u-boot/u-boot.bin\0" \
- "load=tftp 100000 ${u-boot}\0" \
- "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \
- "cp.b 100000 fff00000 40000;" \
- "setenv filesize;saveenv\0" \
- "upd=run load update\0" \
- "serverip=11.0.0.152\0"
-
-#if defined (CONFIG_P3M750)
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_EXTRA_ENV_SETTINGS_COMMON \
- "hostname=p3m750\0" \
- "bootfile=/tftpboot/p3mx/vxWorks.st\0" \
- "kernel_addr=fc000000\0" \
- "ramdisk_addr=fc180000\0" \
- "vxfile=p3m750/vxWorks\0" \
- "vxuser=ddg\0" \
- "vxpass=ddg\0" \
- "vxtarget=target\0" \
- "vxflags=0x8\0" \
- "vxargs=setenv bootargs mgi(0,0)host:${vxfile} h=${serverip} " \
- "e=${ipaddr} u=${vxuser} pw=${vxpass} tn=${vxtarget} " \
- "f=${vxflags}\0"
-#elif defined (CONFIG_P3M7448)
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_EXTRA_ENV_SETTINGS_COMMON \
- "hostname=p3m7448\0"
-#endif
-
-#if defined (CONFIG_P3M750)
-#define CONFIG_BOOTCOMMAND "tftp;run vxargs;bootvx"
-#elif defined (CONFIG_P3M7448)
-#define CONFIG_BOOTCOMMAND " "
-#endif
-
-#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_SDRAM
-
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_HUSH_PARSER
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x08000000 /* default load address */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-/*-----------------------------------------------------------------------
- * Marvell MV64460 config settings
- *----------------------------------------------------------------------*/
-/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected device width */
-#if defined (CONFIG_P3M750)
-#define CONFIG_SYS_BOOT_PAR 0x8FDFF87F /* 16 bit flash, disable burst*/
-#elif defined (CONFIG_P3M7448)
-#define CONFIG_SYS_BOOT_PAR 0x8FEFFFFF /* 32 bit flash, burst enabled */
-#endif
-
-/*
- * MPP[0] Serial Port 0 TxD TxD OUT Connected to P14 (buffered)
- * MPP[1] Serial Port 0 RxD RxD IN Connected to P14 (buffered)
- * MPP[2] NC
- * MPP[3] Serial Port 1 TxD TxD OUT Connected to P14 (buffered)
- * MPP[4] PCI Monarch# GPIO IN Connected to P12
- * MPP[5] Serial Port 1 RxD RxD IN Connected to P14 (buffered)
- * MPP[6] PMC Carrier Interrupt 0 Int IN Connected to P14
- * MPP[7] PMC Carrier Interrupt 1 Int IN Connected to P14
- * MPP[8] Reserved Do not use
- * MPP[9] Reserved Do not use
- * MPP[10] Reserved Do not use
- * MPP[11] Reserved Do not use
- * MPP[12] Phy 0 Interrupt Int IN
- * MPP[13] Phy 1 Interrupt Int IN
- * MPP[14] NC
- * MPP[15] NC
- * MPP[16] PCI Interrupt C Int IN Connected to P11
- * MPP[17] PCI Interrupt D Int IN Connected to P11
- * MPP[18] Watchdog NMI# GPIO IN Connected to MPP[24]
- * MPP[19] Watchdog Expired# WDE OUT Connected to rst logic
- * MPP[20] Watchdog Status WD_STS IN Read back of rst by watchdog
- * MPP[21] NC
- * MPP[22] GP LED Green GPIO OUT
- * MPP[23] GP LED Red GPIO OUT
- * MPP[24] Watchdog NMI# Int OUT
- * MPP[25] NC
- * MPP[26] NC
- * MPP[27] PCI Interrupt A Int IN Connected to P11
- * MPP[28] NC
- * MPP[29] PCI Interrupt B Int IN Connected to P11
- * MPP[30] Module reset GPIO OUT Board reset
- * MPP[31] PCI EReady GPIO IN Connected to P12
- */
-#define CONFIG_SYS_MPP_CONTROL_0 0x00303022
-#define CONFIG_SYS_MPP_CONTROL_1 0x00000000
-#define CONFIG_SYS_MPP_CONTROL_2 0x00004000
-#define CONFIG_SYS_MPP_CONTROL_3 0x00000004
-#define CONFIG_SYS_GPP_LEVEL_CONTROL 0x280730D0
-
-/*----------------------------------------------------------------------
- * Initial BAT mappings
- */
-
-/* NOTES:
- * 1) GUARDED and WRITE_THRU not allowed in IBATS
- * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
- */
-/* SDRAM */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* init ram */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* PCI0, PCI1 in one BAT */
-#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* GT regs, bootrom, all the devices, PCI I/O */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/* set rest out of range for Linux !!!!!!!!!!! */
-
-/* IBAT5 and DBAT5 */
-#define CONFIG_SYS_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-/* IBAT6 and DBAT6 */
-#define CONFIG_SYS_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-
-/* IBAT7 and DBAT7 */
-#define CONFIG_SYS_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_VXWORKS_MAC_PTR 0x42010000 /* use some memory in SRAM that's not used!!! */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * L2CR setup -- make sure this is right for your board!
- * look in include/mpc74xx.h for the defines used here
- */
-#define CONFIG_SYS_L2
-
-#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
-#define L2_INIT 0
-#else
-#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
- L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
-#endif
-
-#define L2_ENABLE (L2_INIT | L2CR_L2E)
-
-#ifndef __ASSEMBLY__
-#include <../board/Marvell/include/core.h>
-#endif
-
-#endif /* __CONFIG_H */
#endif
#endif
-#define CONFIG_SYS_LITTLE_ENDIAN
-
#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
#define __CONFIG_H
#define CONFIG_PDM360NG 1
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
/*
* Memory map for the PDM360NG board:
* SoC UART : enable CONFIG_UNIPHIER_SERIAL
* On-board UART: enable CONFIG_SYS_NS16550_SERIAL
*/
-#if 1
-#define CONFIG_UNIPHIER_SERIAL
-#else
+#if 0
#define CONFIG_SYS_NS16550_SERIAL
#endif
-#define CONFIG_SYS_UNIPHIER_UART_CLK 36864000
-
#define CONFIG_SMC911X
#define CONFIG_DDR_NUM_CH0 1
* SoC UART : enable CONFIG_UNIPHIER_SERIAL
* On-board UART: enable CONFIG_SYS_NS16550_SERIAL
*/
-#if 1
-#define CONFIG_UNIPHIER_SERIAL
-#else
+#if 0
#define CONFIG_SYS_NS16550_SERIAL
#endif
-#define CONFIG_SYS_UNIPHIER_UART_CLK 73728000
-
#define CONFIG_SMC911X
#define CONFIG_DDR_NUM_CH0 2
* SoC UART : enable CONFIG_UNIPHIER_SERIAL
* On-board UART: enable CONFIG_SYS_NS16550_SERIAL
*/
-#if 1
-#define CONFIG_UNIPHIER_SERIAL
-#else
+#if 0
#define CONFIG_SYS_NS16550_SERIAL
#endif
-#define CONFIG_SYS_UNIPHIER_UART_CLK 80000000
-
#define CONFIG_SMC911X
#define CONFIG_DDR_NUM_CH0 1
#define CONFIG_MMC_SDHCI_IO_ACCESSORS
#define CONFIG_BCM2835_SDHCI
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2
+#define CONFIG_USB_DWC2_REG_ADDR 0x20980000
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_MISC_INIT_R
+#endif
+
/* Console UART */
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK 3000000
/* Some things don't make sense on this HW or yet */
#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_SAVEENV
-#undef CONFIG_CMD_DHCP
-#undef CONFIG_CMD_MII
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_PING
/* Environment */
#define ENV_DEVICE_SETTINGS \
"ramdisk_addr_r=0x02100000\0" \
#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0)
+ func(MMC, mmc, 0) \
+ func(USB, usb, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_FS_FAT
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_MISC_INIT_R
+#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_SYS_NO_FLASH
#define CONFIG_CLOCKS
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
+/*
+ * USB
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2
+#define CONFIG_USB_STORAGE
+/*
+ * NOTE: User must define either of the following to select which
+ * of the two USB controllers available on SoCFPGA to use.
+ * The DWC2 driver doesn't support multiple USB controllers.
+ * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB0_ADDRESS
+ * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
+ */
+#endif
+
/*
* U-Boot environment
*/
/*
* SPL
+ *
+ * SRAM Memory layout:
+ *
+ * 0xFFFF_0000 ...... Start of SRAM
+ * 0xFFFF_xxxx ...... Top of stack (grows down)
+ * 0xFFFF_yyyy ...... Malloc area
+ * 0xFFFF_zzzz ...... Global Data
+ * 0xFFFF_FF00 ...... End of SRAM
*/
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_RAM_DEVICE
-#define CONFIG_SPL_TEXT_BASE 0xFFFF0000
-#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
-#define CONFIG_SPL_STACK_SIZE (4 * 1024)
-#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) /* FIXME */
-#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
-#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
+#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
+#define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_SPL_MALLOC_SIZE (5 * 1024)
#define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */
#define CONFIG_CRC32_VERIFY
#if defined(CONFIG_CMD_NET)
#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS
#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
-#define CONFIG_EPHY0_PHY_ADDR 0
/* PHY */
-#define CONFIG_EPHY1_PHY_ADDR 4
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021
#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
#define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0"
/* I2C driver configuration */
-#define CONFIG_HARD_I2C
-#define CONFIG_DW_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DW
#if defined(CONFIG_SPEAR600)
#define CONFIG_SYS_I2C_BASE 0xD0200000
#elif defined(CONFIG_SPEAR300)
/*
* A10 specific configuration
*/
-#define CONFIG_SUN4I /* sun4i SoC generation */
#define CONFIG_CLK_FULL_SPEED 1008000000
#define CONFIG_SYS_PROMPT "sun4i# "
+#define CONFIG_MACH_TYPE 4104
#ifdef CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_SUNXI
/*
* High Level Configuration Options
*/
-#define CONFIG_SUN5I /* sun5i SoC generation */
#define CONFIG_CLK_FULL_SPEED 1008000000
#define CONFIG_SYS_PROMPT "sun5i# "
+#define CONFIG_MACH_TYPE 4138
#ifdef CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_SUNXI
--- /dev/null
+/*
+ * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+ * (C) Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * Configuration settings for the Allwinner A31 (sun6i) CPU
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A31 specific configuration
+ */
+
+#define CONFIG_SYS_PROMPT "sun6i# "
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */
/*
* A20 specific configuration
*/
-#define CONFIG_SUN7I /* sun7i SoC generation */
#define CONFIG_CLK_FULL_SPEED 912000000
#define CONFIG_SYS_PROMPT "sun7i# "
+#define CONFIG_MACH_TYPE 4283
#ifdef CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_SUNXI
--- /dev/null
+/*
+ * (C) Copyright 2014 Chen-Yu Tsai <wens@csie.org>
+ *
+ * Configuration settings for the Allwinner A23 (sun8i) CPU
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A23 specific configuration
+ */
+#define CONFIG_SYS_PROMPT "sun8i# "
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */
#define CONFIG_SYS_TEXT_BASE 0x4a000000
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM)
+# define CONFIG_CMD_DM
+# define CONFIG_DM_GPIO
+# define CONFIG_DM_SERIAL
+# define CONFIG_DW_SERIAL
+# define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
+#endif
+
/*
* Display CPU information
*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
/* ns16550 reg in the low bits of cpu reg */
-#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_CLK 24000000
-#define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE
-#define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE
-#define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE
-#define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE
+#ifndef CONFIG_DM_SERIAL
+# define CONFIG_SYS_NS16550_REG_SIZE -4
+# define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE
+# define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE
+# define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE
+# define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE
+# define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE
+#endif
/* DRAM Base */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_INITRD_TAG
/* mmc config */
+#if !defined(CONFIG_UART0_PORT_F)
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_CMD_MMC
#define CONFIG_MMC_SUNXI_SLOT 0
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */
+#endif
/* 4MB of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
* Miscellaneous configurable options
*/
#define CONFIG_CMD_ECHO
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_GENERIC_BOARD
/* GPIO */
#define CONFIG_SUNXI_GPIO
+#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_CMD_GPIO
/* Ethernet support */
"pxefile_addr_r=0x43200000\0" \
"ramdisk_addr_r=0x43300000\0"
+#ifdef CONFIG_MMC
+#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
+#else
+#define BOOT_TARGET_DEVICES_MMC(func)
+#endif
+
#ifdef CONFIG_AHCI
#define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0)
#else
#define BOOT_TARGET_DEVICES_SCSI(func)
#endif
+#ifdef CONFIG_USB_EHCI
+#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
+#else
+#define BOOT_TARGET_DEVICES_USB(func)
+#endif
+
#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
+ BOOT_TARGET_DEVICES_MMC(func) \
BOOT_TARGET_DEVICES_SCSI(func) \
- func(USB, usb, 0) \
+ BOOT_TARGET_DEVICES_USB(func) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_DM
+# define CONFIG_CMD_DM
+# define CONFIG_DM_GPIO
+# define CONFIG_DM_SERIAL
+# define CONFIG_OMAP_SERIAL
+# define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
+#endif
+
#include <asm/arch/omap.h>
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550
+#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#endif
#define CONFIG_SYS_NS16550_CLK 48000000
/* Network defines. */
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_BOOTZ
+#define CONFIG_SUPPORT_RAW_INITRD
/*
* Common filesystems support. When we have removable storage we
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
/* FAT sd card locations. */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#ifdef CONFIG_SPL_OS_BOOT
/* FAT */
-#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "uImage"
-#define CONFIG_SPL_FAT_LOAD_ARGS_NAME "args"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
/* RAW SD card / eMMC */
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
#include <asm/arch/cpu.h>
#include <asm/arch/omap3.h>
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_DM
+# define CONFIG_CMD_DM
+# define CONFIG_DM_GPIO
+# define CONFIG_DM_SERIAL
+# define CONFIG_OMAP_SERIAL
+# define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
+#endif
+
/* The chip has SDRC controller */
#define CONFIG_SDRC
/* NS16550 Configuration */
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+#ifdef CONFIG_SPL_BUILD
+# define CONFIG_SYS_NS16550_SERIAL
+# define CONFIG_SYS_NS16550_REG_SIZE (-4)
+# define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+#endif
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
115200}
/* Select serial console configuration */
#define CONFIG_CONS_INDEX 3
+#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3 3
+#endif
/* Physical Memory Map */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
(128 << 20))
+/* SPL: Allow to use an EXT partition */
+#define CONFIG_SPL_EXT_SUPPORT
+
#ifdef CONFIG_NAND
#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */
#endif
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
- *
- * Configuation settings for the TOP9000 CPU module with AT91SAM9XE.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-/*
- * top9000 with at91sam9xe256 or at91sam9xe512
- *
- * Initial Bootloader is in embedded flash.
- * Vital Product Data, U-Boot Environment are in I2C-EEPROM.
- * U-Boot is in embedded flash, a backup U-Boot can be in NAND flash.
- * kernel and file system are either in NAND flash or on a micro SD card.
- * NAND flash is optional.
- * I2C EEPROM is never optional.
- * SPI FRAM is optional.
- * SPI ENC28J60 is optional.
- * 16 or 32 bit wide SDRAM.
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* SoC must be defined first, before hardware.h is included */
-#define CONFIG_AT91SAM9XE
-#include <asm/hardware.h>
-
-/*
- * Warning: changing CONFIG_SYS_TEXT_BASE requires
- * adapting the initial boot program.
- */
-#define CONFIG_SYS_TEXT_BASE 0x20000000 /* start of SDRAM */
-
-/* Command line configuration */
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
-#undef CONFIG_CMD_XIMG
-#define CONFIG_CMD_ASKENV
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_PROMPT "TOP9000> "
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_CACHE
-
-/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
-
-/* Misc CPU related */
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_AT91RESET_EXTRST /* assert external reset */
-
-/* general purpose I/O */
-#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
-#define CONFIG_AT91_GPIO
-#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
-
-/* serial console */
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE ATMEL_BASE_DBGU
-#define CONFIG_USART_ID ATMEL_ID_SYS
-#define CONFIG_BAUDRATE 115200
-
-/* SD/MMC card */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_GENERIC_ATMEL_MCI
-#define CONFIG_SYS_MMC_CD_PIN AT91_PIN_PC9
-#define CONFIG_CMD_MMC
-
-/* Ethernet */
-#define CONFIG_MACB
-#define CONFIG_SYS_PHY_ID 1
-#define CONFIG_RMII
-#define CONFIG_NET_RETRY_COUNT 20
-
-/* real time clock */
-#define CONFIG_RTC_AT91SAM9_RTT
-#define CONFIG_CMD_DATE
-
-#if defined(CONFIG_AT91SAM9XE)
-/*
- * NOR flash - use embedded flash of SAM9XE256/512
- * U-Boot will not fit into 128K !
- * 2010.09 will not fit into 256K with all options enabled !
- *
- * Layout:
- * 16kB 1st Bootloader
- * Rest U-Boot
- * the first sector (16kB) of EFLASH cannot be unprotected
- * with u-boot commands
- */
-# define CONFIG_AT91_EFLASH
-# define CONFIG_SYS_FLASH_BASE ATMEL_BASE_FLASH
-# define CONFIG_SYS_MAX_FLASH_SECT 32
-# define CONFIG_SYS_MAX_FLASH_BANKS 1
-# define CONFIG_SYS_FLASH_PROTECTION
-# define CONFIG_EFLASH_PROTSECTORS 1 /* protect first sector */
-#endif
-
-/* SPI */
-#define CONFIG_ATMEL_SPI
-#define CONFIG_CMD_SPI
-
-/* RAMTRON FRAM */
-#define CONFIG_CMD_SF
-#define CONFIG_ATMEL_SPI0 /* SPI used for FRAM is SPI0 */
-#define FRAM_SPI_BUS 0
-#define FRAM_CS_NUM 0
-#define CONFIG_SPI_FRAM_RAMTRON
-#define CONFIG_SF_DEFAULT_SPEED 1000000 /* be conservative here... */
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-#define CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC "FM25H20"
-
-/* Microchip ENC28J60 (second LAN) */
-#if defined(CONFIG_EVAL9000)
-# define CONFIG_ENC28J60
-# define CONFIG_ATMEL_SPI1 /* SPI used for ENC28J60 is SPI1 */
-# define ENC_SPI_BUS 1
-# define ENC_CS_NUM 0
-# define ENC_SPI_CLOCK 1000000
-#endif /* CONFIG_EVAL9000 */
-
-/*
- * SDRAM: 1 bank, min 32, max 128 MB
- * Initialized before u-boot gets started.
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE 0x08000000
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01e00000)
-#define CONFIG_SYS_LOAD_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 0x01000000)
-/*
- * Initial stack pointer: 16k - GENERATED_GBL_DATA_SIZE in internal SRAM,
- * leaving the correct space for initial global data structure above
- * that address while providing maximum stack area below.
- */
-#define CONFIG_SYS_INIT_SP_ADDR \
- (ATMEL_BASE_SRAM + 0x4000 - GENERATED_GBL_DATA_SIZE)
-
-/*
- * NAND flash: 256 MB (optional)
- *
- * Layout:
- * 640kB: u-boot (includes space for spare sectors, handled by
- * initial loader)
- * 2MB: kernel
- * rest: file system
- */
-#define CONFIG_NAND_ATMEL
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
-#define CONFIG_CMD_NAND
-
-/* USB */
-#define CONFIG_USB_ATMEL
-#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "top9000"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
-
-/* I2C support must always be enabled */
-#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 400000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
-
-#define I2C0_PORT AT91_PIO_PORTA
-#define SDA0_PIN 23
-#define SCL0_PIN 24
-#define I2C1_PORT AT91_PIO_PORTB
-#define SDA1_PIN 12
-#define SCL1_PIN 13
-#define I2C_SOFT_DECLARATIONS void iic_init(void);\
- int iic_read(void);\
- void iic_sda(int);\
- void iic_scl(int);
-#define I2C_ACTIVE
-#define I2C_TRISTATE
-#define I2C_INIT iic_init()
-#define I2C_READ iic_read()
-#define I2C_SDA(bit) iic_sda(bit)
-#define I2C_SCL(bit) iic_scl(bit)
-#define I2C_DELAY udelay(3)
-/* EEPROM configuration */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_SIZE 0x2000
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-/* later: #define CONFIG_I2C_ENV_EEPROM_BUS 0 */
-/* ENV is always in I2C-EEPROM */
-#define CONFIG_ENV_IS_IN_EEPROM
-#define CONFIG_ENV_OFFSET 0x1000
-#define CONFIG_ENV_SIZE 0x0f00
-/* VPD settings */
-#define CONFIG_SYS_I2C_FACT_ADDR 0x57
-#define CONFIG_SYS_FACT_OFFSET 0x1F00
-#define CONFIG_SYS_FACT_SIZE 0x0100
-/* later: #define CONFIG_MISC_INIT_R */
-/* define the next only if you want to allow users to enter VPD data */
-#define CONFIG_SYS_FACT_ENTRY
-#ifndef __ASSEMBLY__
-extern void read_factory_r(void);
-#endif
-
-/*
- * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
- * data on the serial line may interrupt the boot sequence.
- */
-#define CONFIG_BOOTDELAY 1
-#define CONFIG_AUTOBOOT
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT \
- "Press SPACE to abort autoboot in %d seconds\n", bootdelay
-#define CONFIG_AUTOBOOT_DELAY_STR "d"
-#define CONFIG_AUTOBOOT_STOP_STR " "
-
-/*
- * add filesystem commands if we have at least 1 storage
- * media with filesystem
- */
-#if defined(CONFIG_NAND_ATMEL) \
- || defined(CONFIG_USB_ATMEL) \
- || defined(CONFIG_MMC)
-# define CONFIG_DOS_PARTITION
-# define CONFIG_CMD_FAT
-# define CONFIG_CMD_EXT2
-/* later: #define CONFIG_CMD_JFFS2 */
-#endif
-
-/* add NET commands if we have at least 1 LAN */
-#if defined(CONFIG_MACB) || defined(CONFIG_ENC28J60)
-# define CONFIG_CMD_PING
-# define CONFIG_CMD_DHCP
-# define CONFIG_CMD_MII
-/* is this really needed ? */
-# define CONFIG_RESET_PHY_R
-/* BOOTP options */
-# define CONFIG_BOOTP_BOOTFILESIZE
-# define CONFIG_BOOTP_BOOTPATH
-# define CONFIG_BOOTP_GATEWAY
-# define CONFIG_BOOTP_HOSTNAME
-#endif
-
-/* linux in NAND flash */
-#define CONFIG_BOOTCOUNT_LIMIT 1
-#define CONFIG_BOOTCOMMAND \
- "nand read 0x21000000 0xA0000 0x200000; bootm"
-#define CONFIG_BOOTARGS \
- "console=ttyS0,115200 " \
- "root=/dev/mtdblock2 " \
- "mtdparts=atmel_nand:" \
- "640k(uboot)ro," \
- "2M(linux)," \
- "16M(root)," \
- "-(rest) " \
- "rw "\
- "rootfstype=jffs2"
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN \
- ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-
-#endif
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_MX6
+
+/* SPL */
+/* #if defined(CONFIG_SPL_BUILD) */
+
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_EXT_SUPPORT
+
+/* common IMX6 SPL configuration */
+#include "imx6_spl.h"
+
+/* #endif */
+
#include "mx6_common.h"
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/gpio.h>
#include <linux/sizes.h>
-#define CONFIG_MX6
-
#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
#define PHYS_SDRAM_SIZE (512u * SZ_1M)
#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_BUS 0
-#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(3, 19) << 8))
+#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 50000000
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00200000)
#endif
+#ifdef CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE
#define CONFIG_SYS_NS16550_CLK 12288000
#define CONFIG_SYS_NS16550_REG_SIZE -2
+#endif
#define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE
#define CONFIG_SMC911X_32_BIT
-#define CONFIG_SYS_UNIPHIER_SERIAL_BASE0 0x54006800
-#define CONFIG_SYS_UNIPHIER_SERIAL_BASE1 0x54006900
-#define CONFIG_SYS_UNIPHIER_SERIAL_BASE2 0x54006a00
-#define CONFIG_SYS_UNIPHIER_SERIAL_BASE3 0x54006b00
+#define CONFIG_SYS_MALLOC_F_LEN 0x7000
/*-----------------------------------------------------------------------
* MMU and Cache Setting
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+
/* Ethernet Configuration */
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
* Default environment and default scripts
* to update uboot and load kernel
*/
-#define xstr(s) str(s)
-#define str(s) #s
#define CONFIG_HOSTNAME woodburn
#define CONFIG_EXTRA_ENV_SETTINGS \
"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
"loadaddr=80800000\0" \
"kernel_addr_r=80800000\0" \
- "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
- "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
- "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \
"flash_self=run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
"run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
"else echo Images not loades;fi\0" \
- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
- "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
+ "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
"update=protect off ${uboot_addr} +80000;" \
"erase ${uboot_addr} +80000;" \
"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
#define CONFIG_SPEAR_GPIO
/* I2C config options */
-#define CONFIG_HARD_I2C
-#define CONFIG_DW_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DW
#define CONFIG_SYS_I2C_BASE 0xD0200000
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_SYS_I2C_SLAVE 0x02
#define CONFIG_UBI_PART ubi0
#define CONFIG_UBIFS_VOLUME rootfs
-#define xstr(s) str(s)
-#define str(s) #s
-
#define MTDIDS_DEFAULT "nand0=nand"
#define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)"
#define CONFIG_EXTRA_ENV_SETTINGS \
"u-boot_addr=1000000\0" \
- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.spr\0" \
+ "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0" \
"load=tftp ${u-boot_addr} ${u-boot}\0" \
- "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};"\
- "erase " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
- "cp.b ${u-boot_addr} " xstr(CONFIG_SYS_MONITOR_BASE) \
+ "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize};" \
+ "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
+ "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \
" ${filesize};" \
- "protect on " xstr(CONFIG_SYS_MONITOR_BASE) \
+ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
" +${filesize}\0" \
"upd=run load update\0" \
- "ubifs=" xstr(CONFIG_HOSTNAME) "/ubifs.img\0" \
- "part=" xstr(CONFIG_UBI_PART) "\0" \
- "vol=" xstr(CONFIG_UBIFS_VOLUME) "\0" \
+ "ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0" \
+ "part=" __stringify(CONFIG_UBI_PART) "\0" \
+ "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \
"load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \
"update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \
" ${filesize}\0" \
"saveenv;boot\0" \
"ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \
"root=ubi0:rootfs rootfstype=ubifs\0" \
- "kernel=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ "kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
"kernel_fs=/boot/uImage \0" \
"kernel_addr=1000000\0" \
- "dtb=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0" \
- "dtb_fs=/boot/" xstr(CONFIG_HOSTNAME) ".dtb\0" \
+ "dtb=" __stringify(CONFIG_HOSTNAME) "/" \
+ __stringify(CONFIG_HOSTNAME) ".dtb\0" \
+ "dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0" \
"dtb_addr=1800000\0" \
"load_kernel=tftp ${kernel_addr} ${kernel}\0" \
"load_dtb=tftp ${dtb_addr} ${dtb}\0" \
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
+#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
#endif
/* Disable dcache for SPL just for sure */
/* Address in RAM where the parameters must be copied by SPL. */
#define CONFIG_SYS_SPL_ARGS_ADDR 0x10000000
-#define CONFIG_SPL_FAT_LOAD_ARGS_NAME "system.dtb"
-#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "uImage"
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME "system.dtb"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
/* Not using MMC raw mode - just for compilation purpose */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PLAT_UNIPHIER_SERIAL_H
+#define __PLAT_UNIPHIER_SERIAL_H
+
+#define DRIVER_NAME "uniphier-uart"
+
+struct uniphier_serial_platform_data {
+ unsigned long base;
+ unsigned int uartclk;
+};
+
+#endif /* __PLAT_UNIPHIER_SERIAL_H */
#define __DM_TEST_H
#include <dm.h>
+#include <malloc.h>
/**
* struct dm_test_cdata - configuration data for test instance
int force_fail_alloc;
int skip_post_probe;
struct udevice *removed;
+ struct mallinfo start;
};
/* Test flags for each test */
*/
int dm_check_devices(struct dm_test_state *dms, int num_devices);
+/**
+ * dm_leak_check_start() - Prepare to check for a memory leak
+ *
+ * Call this before allocating memory to record the amount of memory being
+ * used.
+ *
+ * @dms: Overall test state
+ */
+void dm_leak_check_start(struct dm_test_state *dms);
+
+/**
+ * dm_leak_check_end() - Check that no memory has leaked
+ *
+ * Call this after dm_leak_check_start() and after you have hopefuilly freed
+ * all the memory that was allocated. This function will print an error if
+ * it sees a different amount of total memory allocated than before.
+ *
+ * @dms: Overall test state
+ */int dm_leak_check_end(struct dm_test_state *dms);
+
+
/**
* dm_test_main() - Run all the tests
*
--- /dev/null
+/*
+ * This header provides constants for most input bindings.
+ *
+ * Most input bindings include key code, matrix key code format.
+ * In most cases, key code and matrix key code format uses
+ * the standard values/macro defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_INPUT_INPUT_H
+#define _DT_BINDINGS_INPUT_INPUT_H
+
+#define KEY_RESERVED 0
+#define KEY_ESC 1
+#define KEY_1 2
+#define KEY_2 3
+#define KEY_3 4
+#define KEY_4 5
+#define KEY_5 6
+#define KEY_6 7
+#define KEY_7 8
+#define KEY_8 9
+#define KEY_9 10
+#define KEY_0 11
+#define KEY_MINUS 12
+#define KEY_EQUAL 13
+#define KEY_BACKSPACE 14
+#define KEY_TAB 15
+#define KEY_Q 16
+#define KEY_W 17
+#define KEY_E 18
+#define KEY_R 19
+#define KEY_T 20
+#define KEY_Y 21
+#define KEY_U 22
+#define KEY_I 23
+#define KEY_O 24
+#define KEY_P 25
+#define KEY_LEFTBRACE 26
+#define KEY_RIGHTBRACE 27
+#define KEY_ENTER 28
+#define KEY_LEFTCTRL 29
+#define KEY_A 30
+#define KEY_S 31
+#define KEY_D 32
+#define KEY_F 33
+#define KEY_G 34
+#define KEY_H 35
+#define KEY_J 36
+#define KEY_K 37
+#define KEY_L 38
+#define KEY_SEMICOLON 39
+#define KEY_APOSTROPHE 40
+#define KEY_GRAVE 41
+#define KEY_LEFTSHIFT 42
+#define KEY_BACKSLASH 43
+#define KEY_Z 44
+#define KEY_X 45
+#define KEY_C 46
+#define KEY_V 47
+#define KEY_B 48
+#define KEY_N 49
+#define KEY_M 50
+#define KEY_COMMA 51
+#define KEY_DOT 52
+#define KEY_SLASH 53
+#define KEY_RIGHTSHIFT 54
+#define KEY_KPASTERISK 55
+#define KEY_LEFTALT 56
+#define KEY_SPACE 57
+#define KEY_CAPSLOCK 58
+#define KEY_F1 59
+#define KEY_F2 60
+#define KEY_F3 61
+#define KEY_F4 62
+#define KEY_F5 63
+#define KEY_F6 64
+#define KEY_F7 65
+#define KEY_F8 66
+#define KEY_F9 67
+#define KEY_F10 68
+#define KEY_NUMLOCK 69
+#define KEY_SCROLLLOCK 70
+#define KEY_KP7 71
+#define KEY_KP8 72
+#define KEY_KP9 73
+#define KEY_KPMINUS 74
+#define KEY_KP4 75
+#define KEY_KP5 76
+#define KEY_KP6 77
+#define KEY_KPPLUS 78
+#define KEY_KP1 79
+#define KEY_KP2 80
+#define KEY_KP3 81
+#define KEY_KP0 82
+#define KEY_KPDOT 83
+
+#define KEY_ZENKAKUHANKAKU 85
+#define KEY_102ND 86
+#define KEY_F11 87
+#define KEY_F12 88
+#define KEY_RO 89
+#define KEY_KATAKANA 90
+#define KEY_HIRAGANA 91
+#define KEY_HENKAN 92
+#define KEY_KATAKANAHIRAGANA 93
+#define KEY_MUHENKAN 94
+#define KEY_KPJPCOMMA 95
+#define KEY_KPENTER 96
+#define KEY_RIGHTCTRL 97
+#define KEY_KPSLASH 98
+#define KEY_SYSRQ 99
+#define KEY_RIGHTALT 100
+#define KEY_LINEFEED 101
+#define KEY_HOME 102
+#define KEY_UP 103
+#define KEY_PAGEUP 104
+#define KEY_LEFT 105
+#define KEY_RIGHT 106
+#define KEY_END 107
+#define KEY_DOWN 108
+#define KEY_PAGEDOWN 109
+#define KEY_INSERT 110
+#define KEY_DELETE 111
+#define KEY_MACRO 112
+#define KEY_MUTE 113
+#define KEY_VOLUMEDOWN 114
+#define KEY_VOLUMEUP 115
+#define KEY_POWER 116 /* SC System Power Down */
+#define KEY_KPEQUAL 117
+#define KEY_KPPLUSMINUS 118
+#define KEY_PAUSE 119
+#define KEY_SCALE 120 /* AL Compiz Scale (Expose) */
+
+#define KEY_KPCOMMA 121
+#define KEY_HANGEUL 122
+#define KEY_HANGUEL KEY_HANGEUL
+#define KEY_HANJA 123
+#define KEY_YEN 124
+#define KEY_LEFTMETA 125
+#define KEY_RIGHTMETA 126
+#define KEY_COMPOSE 127
+
+#define KEY_STOP 128 /* AC Stop */
+#define KEY_AGAIN 129
+#define KEY_PROPS 130 /* AC Properties */
+#define KEY_UNDO 131 /* AC Undo */
+#define KEY_FRONT 132
+#define KEY_COPY 133 /* AC Copy */
+#define KEY_OPEN 134 /* AC Open */
+#define KEY_PASTE 135 /* AC Paste */
+#define KEY_FIND 136 /* AC Search */
+#define KEY_CUT 137 /* AC Cut */
+#define KEY_HELP 138 /* AL Integrated Help Center */
+#define KEY_MENU 139 /* Menu (show menu) */
+#define KEY_CALC 140 /* AL Calculator */
+#define KEY_SETUP 141
+#define KEY_SLEEP 142 /* SC System Sleep */
+#define KEY_WAKEUP 143 /* System Wake Up */
+#define KEY_FILE 144 /* AL Local Machine Browser */
+#define KEY_SENDFILE 145
+#define KEY_DELETEFILE 146
+#define KEY_XFER 147
+#define KEY_PROG1 148
+#define KEY_PROG2 149
+#define KEY_WWW 150 /* AL Internet Browser */
+#define KEY_MSDOS 151
+#define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */
+#define KEY_SCREENLOCK KEY_COFFEE
+#define KEY_DIRECTION 153
+#define KEY_CYCLEWINDOWS 154
+#define KEY_MAIL 155
+#define KEY_BOOKMARKS 156 /* AC Bookmarks */
+#define KEY_COMPUTER 157
+#define KEY_BACK 158 /* AC Back */
+#define KEY_FORWARD 159 /* AC Forward */
+#define KEY_CLOSECD 160
+#define KEY_EJECTCD 161
+#define KEY_EJECTCLOSECD 162
+#define KEY_NEXTSONG 163
+#define KEY_PLAYPAUSE 164
+#define KEY_PREVIOUSSONG 165
+#define KEY_STOPCD 166
+#define KEY_RECORD 167
+#define KEY_REWIND 168
+#define KEY_PHONE 169 /* Media Select Telephone */
+#define KEY_ISO 170
+#define KEY_CONFIG 171 /* AL Consumer Control Configuration */
+#define KEY_HOMEPAGE 172 /* AC Home */
+#define KEY_REFRESH 173 /* AC Refresh */
+#define KEY_EXIT 174 /* AC Exit */
+#define KEY_MOVE 175
+#define KEY_EDIT 176
+#define KEY_SCROLLUP 177
+#define KEY_SCROLLDOWN 178
+#define KEY_KPLEFTPAREN 179
+#define KEY_KPRIGHTPAREN 180
+#define KEY_NEW 181 /* AC New */
+#define KEY_REDO 182 /* AC Redo/Repeat */
+
+#define KEY_F13 183
+#define KEY_F14 184
+#define KEY_F15 185
+#define KEY_F16 186
+#define KEY_F17 187
+#define KEY_F18 188
+#define KEY_F19 189
+#define KEY_F20 190
+#define KEY_F21 191
+#define KEY_F22 192
+#define KEY_F23 193
+#define KEY_F24 194
+
+#define KEY_PLAYCD 200
+#define KEY_PAUSECD 201
+#define KEY_PROG3 202
+#define KEY_PROG4 203
+#define KEY_DASHBOARD 204 /* AL Dashboard */
+#define KEY_SUSPEND 205
+#define KEY_CLOSE 206 /* AC Close */
+#define KEY_PLAY 207
+#define KEY_FASTFORWARD 208
+#define KEY_BASSBOOST 209
+#define KEY_PRINT 210 /* AC Print */
+#define KEY_HP 211
+#define KEY_CAMERA 212
+#define KEY_SOUND 213
+#define KEY_QUESTION 214
+#define KEY_EMAIL 215
+#define KEY_CHAT 216
+#define KEY_SEARCH 217
+#define KEY_CONNECT 218
+#define KEY_FINANCE 219 /* AL Checkbook/Finance */
+#define KEY_SPORT 220
+#define KEY_SHOP 221
+#define KEY_ALTERASE 222
+#define KEY_CANCEL 223 /* AC Cancel */
+#define KEY_BRIGHTNESSDOWN 224
+#define KEY_BRIGHTNESSUP 225
+#define KEY_MEDIA 226
+
+#define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video
+ outputs (Monitor/LCD/TV-out/etc) */
+#define KEY_KBDILLUMTOGGLE 228
+#define KEY_KBDILLUMDOWN 229
+#define KEY_KBDILLUMUP 230
+
+#define KEY_SEND 231 /* AC Send */
+#define KEY_REPLY 232 /* AC Reply */
+#define KEY_FORWARDMAIL 233 /* AC Forward Msg */
+#define KEY_SAVE 234 /* AC Save */
+#define KEY_DOCUMENTS 235
+
+#define KEY_BATTERY 236
+
+#define KEY_BLUETOOTH 237
+#define KEY_WLAN 238
+#define KEY_UWB 239
+
+#define KEY_UNKNOWN 240
+
+#define KEY_VIDEO_NEXT 241 /* drive next video source */
+#define KEY_VIDEO_PREV 242 /* drive previous video source */
+#define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */
+#define KEY_BRIGHTNESS_ZERO 244 /* brightness off, use ambient */
+#define KEY_DISPLAY_OFF 245 /* display device to off state */
+
+#define KEY_WIMAX 246
+#define KEY_RFKILL 247 /* Key that controls all radios */
+
+#define KEY_MICMUTE 248 /* Mute / unmute the microphone */
+
+/* Code 255 is reserved for special needs of AT keyboard driver */
+
+#define BTN_MISC 0x100
+#define BTN_0 0x100
+#define BTN_1 0x101
+#define BTN_2 0x102
+#define BTN_3 0x103
+#define BTN_4 0x104
+#define BTN_5 0x105
+#define BTN_6 0x106
+#define BTN_7 0x107
+#define BTN_8 0x108
+#define BTN_9 0x109
+
+#define BTN_MOUSE 0x110
+#define BTN_LEFT 0x110
+#define BTN_RIGHT 0x111
+#define BTN_MIDDLE 0x112
+#define BTN_SIDE 0x113
+#define BTN_EXTRA 0x114
+#define BTN_FORWARD 0x115
+#define BTN_BACK 0x116
+#define BTN_TASK 0x117
+
+#define BTN_JOYSTICK 0x120
+#define BTN_TRIGGER 0x120
+#define BTN_THUMB 0x121
+#define BTN_THUMB2 0x122
+#define BTN_TOP 0x123
+#define BTN_TOP2 0x124
+#define BTN_PINKIE 0x125
+#define BTN_BASE 0x126
+#define BTN_BASE2 0x127
+#define BTN_BASE3 0x128
+#define BTN_BASE4 0x129
+#define BTN_BASE5 0x12a
+#define BTN_BASE6 0x12b
+#define BTN_DEAD 0x12f
+
+#define BTN_GAMEPAD 0x130
+#define BTN_SOUTH 0x130
+#define BTN_A BTN_SOUTH
+#define BTN_EAST 0x131
+#define BTN_B BTN_EAST
+#define BTN_C 0x132
+#define BTN_NORTH 0x133
+#define BTN_X BTN_NORTH
+#define BTN_WEST 0x134
+#define BTN_Y BTN_WEST
+#define BTN_Z 0x135
+#define BTN_TL 0x136
+#define BTN_TR 0x137
+#define BTN_TL2 0x138
+#define BTN_TR2 0x139
+#define BTN_SELECT 0x13a
+#define BTN_START 0x13b
+#define BTN_MODE 0x13c
+#define BTN_THUMBL 0x13d
+#define BTN_THUMBR 0x13e
+
+#define BTN_DIGI 0x140
+#define BTN_TOOL_PEN 0x140
+#define BTN_TOOL_RUBBER 0x141
+#define BTN_TOOL_BRUSH 0x142
+#define BTN_TOOL_PENCIL 0x143
+#define BTN_TOOL_AIRBRUSH 0x144
+#define BTN_TOOL_FINGER 0x145
+#define BTN_TOOL_MOUSE 0x146
+#define BTN_TOOL_LENS 0x147
+#define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */
+#define BTN_TOUCH 0x14a
+#define BTN_STYLUS 0x14b
+#define BTN_STYLUS2 0x14c
+#define BTN_TOOL_DOUBLETAP 0x14d
+#define BTN_TOOL_TRIPLETAP 0x14e
+#define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */
+
+#define BTN_WHEEL 0x150
+#define BTN_GEAR_DOWN 0x150
+#define BTN_GEAR_UP 0x151
+
+#define KEY_OK 0x160
+#define KEY_SELECT 0x161
+#define KEY_GOTO 0x162
+#define KEY_CLEAR 0x163
+#define KEY_POWER2 0x164
+#define KEY_OPTION 0x165
+#define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */
+#define KEY_TIME 0x167
+#define KEY_VENDOR 0x168
+#define KEY_ARCHIVE 0x169
+#define KEY_PROGRAM 0x16a /* Media Select Program Guide */
+#define KEY_CHANNEL 0x16b
+#define KEY_FAVORITES 0x16c
+#define KEY_EPG 0x16d
+#define KEY_PVR 0x16e /* Media Select Home */
+#define KEY_MHP 0x16f
+#define KEY_LANGUAGE 0x170
+#define KEY_TITLE 0x171
+#define KEY_SUBTITLE 0x172
+#define KEY_ANGLE 0x173
+#define KEY_ZOOM 0x174
+#define KEY_MODE 0x175
+#define KEY_KEYBOARD 0x176
+#define KEY_SCREEN 0x177
+#define KEY_PC 0x178 /* Media Select Computer */
+#define KEY_TV 0x179 /* Media Select TV */
+#define KEY_TV2 0x17a /* Media Select Cable */
+#define KEY_VCR 0x17b /* Media Select VCR */
+#define KEY_VCR2 0x17c /* VCR Plus */
+#define KEY_SAT 0x17d /* Media Select Satellite */
+#define KEY_SAT2 0x17e
+#define KEY_CD 0x17f /* Media Select CD */
+#define KEY_TAPE 0x180 /* Media Select Tape */
+#define KEY_RADIO 0x181
+#define KEY_TUNER 0x182 /* Media Select Tuner */
+#define KEY_PLAYER 0x183
+#define KEY_TEXT 0x184
+#define KEY_DVD 0x185 /* Media Select DVD */
+#define KEY_AUX 0x186
+#define KEY_MP3 0x187
+#define KEY_AUDIO 0x188 /* AL Audio Browser */
+#define KEY_VIDEO 0x189 /* AL Movie Browser */
+#define KEY_DIRECTORY 0x18a
+#define KEY_LIST 0x18b
+#define KEY_MEMO 0x18c /* Media Select Messages */
+#define KEY_CALENDAR 0x18d
+#define KEY_RED 0x18e
+#define KEY_GREEN 0x18f
+#define KEY_YELLOW 0x190
+#define KEY_BLUE 0x191
+#define KEY_CHANNELUP 0x192 /* Channel Increment */
+#define KEY_CHANNELDOWN 0x193 /* Channel Decrement */
+#define KEY_FIRST 0x194
+#define KEY_LAST 0x195 /* Recall Last */
+#define KEY_AB 0x196
+#define KEY_NEXT 0x197
+#define KEY_RESTART 0x198
+#define KEY_SLOW 0x199
+#define KEY_SHUFFLE 0x19a
+#define KEY_BREAK 0x19b
+#define KEY_PREVIOUS 0x19c
+#define KEY_DIGITS 0x19d
+#define KEY_TEEN 0x19e
+#define KEY_TWEN 0x19f
+#define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */
+#define KEY_GAMES 0x1a1 /* Media Select Games */
+#define KEY_ZOOMIN 0x1a2 /* AC Zoom In */
+#define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */
+#define KEY_ZOOMRESET 0x1a4 /* AC Zoom */
+#define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */
+#define KEY_EDITOR 0x1a6 /* AL Text Editor */
+#define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */
+#define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */
+#define KEY_PRESENTATION 0x1a9 /* AL Presentation App */
+#define KEY_DATABASE 0x1aa /* AL Database App */
+#define KEY_NEWS 0x1ab /* AL Newsreader */
+#define KEY_VOICEMAIL 0x1ac /* AL Voicemail */
+#define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */
+#define KEY_MESSENGER 0x1ae /* AL Instant Messaging */
+#define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */
+#define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */
+#define KEY_LOGOFF 0x1b1 /* AL Logoff */
+
+#define KEY_DOLLAR 0x1b2
+#define KEY_EURO 0x1b3
+
+#define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */
+#define KEY_FRAMEFORWARD 0x1b5
+#define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */
+#define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */
+#define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */
+#define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */
+#define KEY_IMAGES 0x1ba /* AL Image Browser */
+
+#define KEY_DEL_EOL 0x1c0
+#define KEY_DEL_EOS 0x1c1
+#define KEY_INS_LINE 0x1c2
+#define KEY_DEL_LINE 0x1c3
+
+#define KEY_FN 0x1d0
+#define KEY_FN_ESC 0x1d1
+#define KEY_FN_F1 0x1d2
+#define KEY_FN_F2 0x1d3
+#define KEY_FN_F3 0x1d4
+#define KEY_FN_F4 0x1d5
+#define KEY_FN_F5 0x1d6
+#define KEY_FN_F6 0x1d7
+#define KEY_FN_F7 0x1d8
+#define KEY_FN_F8 0x1d9
+#define KEY_FN_F9 0x1da
+#define KEY_FN_F10 0x1db
+#define KEY_FN_F11 0x1dc
+#define KEY_FN_F12 0x1dd
+#define KEY_FN_1 0x1de
+#define KEY_FN_2 0x1df
+#define KEY_FN_D 0x1e0
+#define KEY_FN_E 0x1e1
+#define KEY_FN_F 0x1e2
+#define KEY_FN_S 0x1e3
+#define KEY_FN_B 0x1e4
+
+#define KEY_BRL_DOT1 0x1f1
+#define KEY_BRL_DOT2 0x1f2
+#define KEY_BRL_DOT3 0x1f3
+#define KEY_BRL_DOT4 0x1f4
+#define KEY_BRL_DOT5 0x1f5
+#define KEY_BRL_DOT6 0x1f6
+#define KEY_BRL_DOT7 0x1f7
+#define KEY_BRL_DOT8 0x1f8
+#define KEY_BRL_DOT9 0x1f9
+#define KEY_BRL_DOT10 0x1fa
+
+#define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */
+#define KEY_NUMERIC_1 0x201 /* and other keypads */
+#define KEY_NUMERIC_2 0x202
+#define KEY_NUMERIC_3 0x203
+#define KEY_NUMERIC_4 0x204
+#define KEY_NUMERIC_5 0x205
+#define KEY_NUMERIC_6 0x206
+#define KEY_NUMERIC_7 0x207
+#define KEY_NUMERIC_8 0x208
+#define KEY_NUMERIC_9 0x209
+#define KEY_NUMERIC_STAR 0x20a
+#define KEY_NUMERIC_POUND 0x20b
+
+#define KEY_CAMERA_FOCUS 0x210
+#define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */
+
+#define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */
+#define KEY_TOUCHPAD_ON 0x213
+#define KEY_TOUCHPAD_OFF 0x214
+
+#define KEY_CAMERA_ZOOMIN 0x215
+#define KEY_CAMERA_ZOOMOUT 0x216
+#define KEY_CAMERA_UP 0x217
+#define KEY_CAMERA_DOWN 0x218
+#define KEY_CAMERA_LEFT 0x219
+#define KEY_CAMERA_RIGHT 0x21a
+
+#define KEY_ATTENDANT_ON 0x21b
+#define KEY_ATTENDANT_OFF 0x21c
+#define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */
+#define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */
+
+#define BTN_DPAD_UP 0x220
+#define BTN_DPAD_DOWN 0x221
+#define BTN_DPAD_LEFT 0x222
+#define BTN_DPAD_RIGHT 0x223
+
+#define MATRIX_KEY(row, col, code) \
+ ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF))
+
+#endif /* _DT_BINDINGS_INPUT_INPUT_H */
that may still be in object files. */
#define R_PPC_TOC16 255
+int valid_elf_image(unsigned long addr);
+
#endif /* _ELF_H */
void of_bus_default_count_cells(void *blob, int parentoffset,
int *addrc, int *sizec);
+int ft_verify_fdt(void *fdt);
+int arch_fixup_memory_node(void *blob);
#endif /* ifdef CONFIG_OF_LIBFDT */
#define LED_IDE2 0x02
#define DEVICE_LED(d) ((d & 2) | ((d & 2) == 0)) /* depends on bit positions! */
+void ide_led(uchar led, uchar status);
#endif /* CONFIG_IDE_LED */
#ifdef CONFIG_SYS_64BIT_LBA
#define IH_ARCH_OPENRISC 21 /* OpenRISC 1000 */
#define IH_ARCH_ARM64 22 /* ARM64 */
#define IH_ARCH_ARC 23 /* Synopsys DesignWare ARC */
+#define IH_ARCH_X86_64 24 /* AMD x86_64, Intel and Via */
/*
* Image Types
--- /dev/null
+/*
+ * Copyright (C) 1997-2001, 2004, 2007 Free Software Foundation, Inc.
+ *
+ * This file is taken from the GNU C Library v2.15, with the unimplemented
+ * functions removed and a few style fixes.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * ISO C99: 7.8 Format conversion of integer types <inttypes.h>
+ */
+
+#ifndef _INTTYPES_H
+#define _INTTYPES_H 1
+
+#include <linux/compiler.h>
+
+/* Get a definition for wchar_t. But we must not define wchar_t itself. */
+#ifndef ____gwchar_t_defined
+# ifdef __cplusplus
+# define __gwchar_t wchar_t
+# elif defined __WCHAR_TYPE__
+typedef __WCHAR_TYPE__ __gwchar_t;
+# else
+# define __need_wchar_t
+# include <stddef.h>
+typedef wchar_t __gwchar_t;
+# endif
+# define ____gwchar_t_defined 1
+#endif
+
+
+/* The ISO C99 standard specifies that these macros must only be
+ defined if explicitly requested. */
+#if !defined __cplusplus || defined __STDC_FORMAT_MACROS
+
+#ifdef CONFIG_USE_STDINT
+# if __WORDSIZE == 64
+# define __PRI64_PREFIX "l"
+# define __PRIPTR_PREFIX "l"
+# else
+# define __PRI64_PREFIX "ll"
+# define __PRIPTR_PREFIX
+# endif
+#else
+/* linux/types.h always uses long long for 64-bit and long for uintptr_t */
+# define __PRI64_PREFIX "ll"
+# define __PRIPTR_PREFIX "l"
+#endif
+
+/* Macros for printing format specifiers. */
+
+/* Decimal notation. */
+# define PRId8 "d"
+# define PRId16 "d"
+# define PRId32 "d"
+# define PRId64 __PRI64_PREFIX "d"
+
+# define PRIdLEAST8 "d"
+# define PRIdLEAST16 "d"
+# define PRIdLEAST32 "d"
+# define PRIdLEAST64 __PRI64_PREFIX "d"
+
+# define PRIdFAST8 "d"
+# define PRIdFAST16 __PRIPTR_PREFIX "d"
+# define PRIdFAST32 __PRIPTR_PREFIX "d"
+# define PRIdFAST64 __PRI64_PREFIX "d"
+
+
+# define PRIi8 "i"
+# define PRIi16 "i"
+# define PRIi32 "i"
+# define PRIi64 __PRI64_PREFIX "i"
+
+# define PRIiLEAST8 "i"
+# define PRIiLEAST16 "i"
+# define PRIiLEAST32 "i"
+# define PRIiLEAST64 __PRI64_PREFIX "i"
+
+# define PRIiFAST8 "i"
+# define PRIiFAST16 __PRIPTR_PREFIX "i"
+# define PRIiFAST32 __PRIPTR_PREFIX "i"
+# define PRIiFAST64 __PRI64_PREFIX "i"
+
+/* Octal notation. */
+# define PRIo8 "o"
+# define PRIo16 "o"
+# define PRIo32 "o"
+# define PRIo64 __PRI64_PREFIX "o"
+
+# define PRIoLEAST8 "o"
+# define PRIoLEAST16 "o"
+# define PRIoLEAST32 "o"
+# define PRIoLEAST64 __PRI64_PREFIX "o"
+
+# define PRIoFAST8 "o"
+# define PRIoFAST16 __PRIPTR_PREFIX "o"
+# define PRIoFAST32 __PRIPTR_PREFIX "o"
+# define PRIoFAST64 __PRI64_PREFIX "o"
+
+/* Unsigned integers. */
+# define PRIu8 "u"
+# define PRIu16 "u"
+# define PRIu32 "u"
+# define PRIu64 __PRI64_PREFIX "u"
+
+# define PRIuLEAST8 "u"
+# define PRIuLEAST16 "u"
+# define PRIuLEAST32 "u"
+# define PRIuLEAST64 __PRI64_PREFIX "u"
+
+# define PRIuFAST8 "u"
+# define PRIuFAST16 __PRIPTR_PREFIX "u"
+# define PRIuFAST32 __PRIPTR_PREFIX "u"
+# define PRIuFAST64 __PRI64_PREFIX "u"
+
+/* lowercase hexadecimal notation. */
+# define PRIx8 "x"
+# define PRIx16 "x"
+# define PRIx32 "x"
+# define PRIx64 __PRI64_PREFIX "x"
+
+# define PRIxLEAST8 "x"
+# define PRIxLEAST16 "x"
+# define PRIxLEAST32 "x"
+# define PRIxLEAST64 __PRI64_PREFIX "x"
+
+# define PRIxFAST8 "x"
+# define PRIxFAST16 __PRIPTR_PREFIX "x"
+# define PRIxFAST32 __PRIPTR_PREFIX "x"
+# define PRIxFAST64 __PRI64_PREFIX "x"
+
+/* UPPERCASE hexadecimal notation. */
+# define PRIX8 "X"
+# define PRIX16 "X"
+# define PRIX32 "X"
+# define PRIX64 __PRI64_PREFIX "X"
+
+# define PRIXLEAST8 "X"
+# define PRIXLEAST16 "X"
+# define PRIXLEAST32 "X"
+# define PRIXLEAST64 __PRI64_PREFIX "X"
+
+# define PRIXFAST8 "X"
+# define PRIXFAST16 __PRIPTR_PREFIX "X"
+# define PRIXFAST32 __PRIPTR_PREFIX "X"
+# define PRIXFAST64 __PRI64_PREFIX "X"
+
+
+/* Macros for printing `intmax_t' and `uintmax_t'. */
+# define PRIdMAX __PRI64_PREFIX "d"
+# define PRIiMAX __PRI64_PREFIX "i"
+# define PRIoMAX __PRI64_PREFIX "o"
+# define PRIuMAX __PRI64_PREFIX "u"
+# define PRIxMAX __PRI64_PREFIX "x"
+# define PRIXMAX __PRI64_PREFIX "X"
+
+
+/* Macros for printing `intptr_t' and `uintptr_t'. */
+# define PRIdPTR __PRIPTR_PREFIX "d"
+# define PRIiPTR __PRIPTR_PREFIX "i"
+# define PRIoPTR __PRIPTR_PREFIX "o"
+# define PRIuPTR __PRIPTR_PREFIX "u"
+# define PRIxPTR __PRIPTR_PREFIX "x"
+# define PRIXPTR __PRIPTR_PREFIX "X"
+
+
+/* Macros for scanning format specifiers. */
+
+/* Signed decimal notation. */
+# define SCNd8 "hhd"
+# define SCNd16 "hd"
+# define SCNd32 "d"
+# define SCNd64 __PRI64_PREFIX "d"
+
+# define SCNdLEAST8 "hhd"
+# define SCNdLEAST16 "hd"
+# define SCNdLEAST32 "d"
+# define SCNdLEAST64 __PRI64_PREFIX "d"
+
+# define SCNdFAST8 "hhd"
+# define SCNdFAST16 __PRIPTR_PREFIX "d"
+# define SCNdFAST32 __PRIPTR_PREFIX "d"
+# define SCNdFAST64 __PRI64_PREFIX "d"
+
+/* Signed decimal notation. */
+# define SCNi8 "hhi"
+# define SCNi16 "hi"
+# define SCNi32 "i"
+# define SCNi64 __PRI64_PREFIX "i"
+
+# define SCNiLEAST8 "hhi"
+# define SCNiLEAST16 "hi"
+# define SCNiLEAST32 "i"
+# define SCNiLEAST64 __PRI64_PREFIX "i"
+
+# define SCNiFAST8 "hhi"
+# define SCNiFAST16 __PRIPTR_PREFIX "i"
+# define SCNiFAST32 __PRIPTR_PREFIX "i"
+# define SCNiFAST64 __PRI64_PREFIX "i"
+
+/* Unsigned decimal notation. */
+# define SCNu8 "hhu"
+# define SCNu16 "hu"
+# define SCNu32 "u"
+# define SCNu64 __PRI64_PREFIX "u"
+
+# define SCNuLEAST8 "hhu"
+# define SCNuLEAST16 "hu"
+# define SCNuLEAST32 "u"
+# define SCNuLEAST64 __PRI64_PREFIX "u"
+
+# define SCNuFAST8 "hhu"
+# define SCNuFAST16 __PRIPTR_PREFIX "u"
+# define SCNuFAST32 __PRIPTR_PREFIX "u"
+# define SCNuFAST64 __PRI64_PREFIX "u"
+
+/* Octal notation. */
+# define SCNo8 "hho"
+# define SCNo16 "ho"
+# define SCNo32 "o"
+# define SCNo64 __PRI64_PREFIX "o"
+
+# define SCNoLEAST8 "hho"
+# define SCNoLEAST16 "ho"
+# define SCNoLEAST32 "o"
+# define SCNoLEAST64 __PRI64_PREFIX "o"
+
+# define SCNoFAST8 "hho"
+# define SCNoFAST16 __PRIPTR_PREFIX "o"
+# define SCNoFAST32 __PRIPTR_PREFIX "o"
+# define SCNoFAST64 __PRI64_PREFIX "o"
+
+/* Hexadecimal notation. */
+# define SCNx8 "hhx"
+# define SCNx16 "hx"
+# define SCNx32 "x"
+# define SCNx64 __PRI64_PREFIX "x"
+
+# define SCNxLEAST8 "hhx"
+# define SCNxLEAST16 "hx"
+# define SCNxLEAST32 "x"
+# define SCNxLEAST64 __PRI64_PREFIX "x"
+
+# define SCNxFAST8 "hhx"
+# define SCNxFAST16 __PRIPTR_PREFIX "x"
+# define SCNxFAST32 __PRIPTR_PREFIX "x"
+# define SCNxFAST64 __PRI64_PREFIX "x"
+
+
+/* Macros for scanning `intmax_t' and `uintmax_t'. */
+# define SCNdMAX __PRI64_PREFIX "d"
+# define SCNiMAX __PRI64_PREFIX "i"
+# define SCNoMAX __PRI64_PREFIX "o"
+# define SCNuMAX __PRI64_PREFIX "u"
+# define SCNxMAX __PRI64_PREFIX "x"
+
+/* Macros for scaning `intptr_t' and `uintptr_t'. */
+# define SCNdPTR __PRIPTR_PREFIX "d"
+# define SCNiPTR __PRIPTR_PREFIX "i"
+# define SCNoPTR __PRIPTR_PREFIX "o"
+# define SCNuPTR __PRIPTR_PREFIX "u"
+# define SCNxPTR __PRIPTR_PREFIX "x"
+
+#endif /* C++ && format macros */
+
+
+#if __WORDSIZE == 64
+
+/* We have to define the `uintmax_t' type using `ldiv_t'. */
+typedef struct {
+ long int quot; /* Quotient. */
+ long int rem; /* Remainder. */
+} imaxdiv_t;
+
+#else
+
+/* We have to define the `uintmax_t' type using `lldiv_t'. */
+typedef struct {
+ long long int quot; /* Quotient. */
+ long long int rem; /* Remainder. */
+} imaxdiv_t;
+
+#endif
+
+#endif /* inttypes.h */
*/
#include <asm/string.h>
+#ifndef __HAVE_ARCH_BCOPY
+char *bcopy(const char *src, char *dest, int count);
+#endif
+
#ifndef __HAVE_ARCH_STRCPY
extern char * strcpy(char *,const char *);
#endif
void *memchr_inv(const void *, int, size_t);
#endif
+unsigned long ustrtoul(const char *cp, char **endp, unsigned int base);
+unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base);
+
#ifdef __cplusplus
}
#endif
typedef __u16 uint16_t;
typedef __u32 uint32_t;
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__) && \
+ (!defined(CONFIG_USE_STDINT) || !defined(__INT64_TYPE__))
typedef __u64 uint64_t;
typedef __u64 u_int64_t;
typedef __s64 int64_t;
#endif /* __KERNEL_STRICT_NAMES */
+#if defined(CONFIG_USE_STDINT) && defined(__INT64_TYPE__)
+typedef __UINT64_TYPE__ uint64_t;
+typedef __UINT64_TYPE__ u_int64_t;
+typedef __INT64_TYPE__ int64_t;
+#endif
+
/*
* Below are truly Linux-specific types that should never collide with
* any application/library that wants linux/types.h.
#define DWC3_REG_OFFSET 0xC100
struct g_event_buffer {
- u64 g_evntadr;
+ u32 g_evntadrlo;
+ u32 g_evntadrhi;
u32 g_evntsiz;
u32 g_evntcount;
};
#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
+/* Device Control Register */
+#define DWC3_DCTL_RUN_STOP (1 << 31)
+#define DWC3_DCTL_CSFTRST (1 << 30)
+#define DWC3_DCTL_LSFTRST (1 << 29)
+
#endif /* __DWC3_H_ */
#define __deprecated
#endif
+#include <linux/compat.h>
+
/* The USB role is defined by the connector used on the board, so long as
* standards are being followed. (Developer boards sometimes won't.)
*/
int board_mmc_init(bd_t *bis);
int cpu_mmc_init(bd_t *bis);
+int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
/* Set block count limit because of 16 bit register limit on some hardware*/
#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
* @clock: UART base clock speed in Hz
*/
struct ns16550_platdata {
- unsigned char *base;
+ unsigned long base;
int reg_shift;
int clock;
};
#define PCI_DEVICE_ID_INTEL_82380FB 0x124b
#define PCI_DEVICE_ID_INTEL_82439 0x1250
#define PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED 0x1531
+#define PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED 0x1532
#define PCI_DEVICE_ID_INTEL_I210_COPPER 0x1533
#define PCI_DEVICE_ID_INTEL_I210_SERDES 0x1536
#define PCI_DEVICE_ID_INTEL_I210_1000BASEKX 0x1537
#define PCI_DEVICE_ID_INTEL_I210_EXTPHY 0x1538
+#define PCI_DEVICE_ID_INTEL_I211_COPPER 0x1539
#define PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS 0x157b
#define PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS 0x157c
#define PCI_DEVICE_ID_INTEL_80960_RP 0x1960
# define CONFIG_PCMCIA_SLOT_A
#elif defined(CONFIG_LWMON) /* The LWMON use SLOT_B */
# define CONFIG_PCMCIA_SLOT_B
-#elif defined(CONFIG_ICU862) /* The ICU862 use SLOT_B */
-# define CONFIG_PCMCIA_SLOT_B
#elif defined(CONFIG_R360MPI) /* The R360MPI use SLOT_B */
# define CONFIG_PCMCIA_SLOT_B
#elif defined(CONFIG_ATC) /* The ATC use SLOT_A */
/* Access the serial operations for a device */
#define serial_get_ops(dev) ((struct dm_serial_ops *)(dev)->driver->ops)
+void altera_jtag_serial_initialize(void);
+void altera_serial_initialize(void);
+void amirix_serial_initialize(void);
+void arc_serial_initialize(void);
+void arm_dcc_initialize(void);
+void asc_serial_initialize(void);
+void atmel_serial_initialize(void);
+void au1x00_serial_initialize(void);
+void bfin_jtag_initialize(void);
+void bfin_serial_initialize(void);
+void bmw_serial_initialize(void);
+void clps7111_serial_initialize(void);
+void cogent_serial_initialize(void);
+void cpci750_serial_initialize(void);
+void evb64260_serial_initialize(void);
+void imx_serial_initialize(void);
+void iop480_serial_initialize(void);
+void jz_serial_initialize(void);
+void ks8695_serial_initialize(void);
+void leon2_serial_initialize(void);
+void leon3_serial_initialize(void);
+void lh7a40x_serial_initialize(void);
+void lpc32xx_serial_initialize(void);
+void marvell_serial_initialize(void);
+void max3100_serial_initialize(void);
+void mcf_serial_initialize(void);
+void ml2_serial_initialize(void);
+void mpc512x_serial_initialize(void);
+void mpc5xx_serial_initialize(void);
+void mpc8260_scc_serial_initialize(void);
+void mpc8260_smc_serial_initialize(void);
+void mpc85xx_serial_initialize(void);
+void mpc8xx_serial_initialize(void);
+void mxc_serial_initialize(void);
+void mxs_auart_initialize(void);
+void ns16550_serial_initialize(void);
+void oc_serial_initialize(void);
+void p3mx_serial_initialize(void);
+void pl01x_serial_initialize(void);
+void pxa_serial_initialize(void);
+void s3c24xx_serial_initialize(void);
+void s5p_serial_initialize(void);
+void sa1100_serial_initialize(void);
+void sandbox_serial_initialize(void);
+void sconsole_serial_initialize(void);
+void sh_serial_initialize(void);
+void uartlite_serial_initialize(void);
+void zynq_serial_initialize(void);
+
#endif
/* Boot type */
#define MMCSD_MODE_UNDEFINED 0
#define MMCSD_MODE_RAW 1
-#define MMCSD_MODE_FAT 2
+#define MMCSD_MODE_FS 2
#define MMCSD_MODE_EMMCBOOT 3
struct spl_image_info {
int spl_load_image_fat(block_dev_desc_t *block_dev, int partition, const char *filename);
int spl_load_image_fat_os(block_dev_desc_t *block_dev, int partition);
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image);
+
+/* SPL EXT image functions */
+int spl_load_image_ext(block_dev_desc_t *block_dev, int partition, const char *filename);
+int spl_load_image_ext_os(block_dev_desc_t *block_dev, int partition);
+
#ifdef CONFIG_SPL_BOARD_INIT
void spl_board_init(void);
#endif
# define STATUS_LED_GREEN 1
# define STATUS_LED_BOOT 2 /* IDE LED used for boot status */
-/***** ICU862 ********************************************************/
-#elif defined(CONFIG_ICU862)
-
-# define STATUS_LED_PAR im_ioport.iop_papar
-# define STATUS_LED_DIR im_ioport.iop_padir
-# define STATUS_LED_ODR im_ioport.iop_paodr
-# define STATUS_LED_DAT im_ioport.iop_padat
-
-# define STATUS_LED_BIT 0x4000 /* LED 0 is on PA.1 */
-# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
-# define STATUS_LED_STATE STATUS_LED_BLINKING
-# define STATUS_LED_BIT1 0x1000 /* LED 1 is on PA.3 */
-# define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ)
-# define STATUS_LED_STATE1 STATUS_LED_OFF
-
-# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
-
-# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
/***** Someone else defines these *************************************/
#elif defined(STATUS_LED_PAR)
--- /dev/null
+/*
+ * Copyright (C) 2013 Google Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __STDLIB_H_
+#define __STDLIB_H_
+
+#include <malloc.h>
+
+#endif /* __STDLIB_H_ */
/* Voltage Selection in PM Receiver Module */
#define TWL4030_PM_RECEIVER_VAUX2_VSEL_18 0x05
+#define TWL4030_PM_RECEIVER_VAUX2_VSEL_28 0x09
+#define TWL4030_PM_RECEIVER_VAUX3_VSEL_18 0x01
#define TWL4030_PM_RECEIVER_VAUX3_VSEL_28 0x03
#define TWL4030_PM_RECEIVER_VPLL2_VSEL_18 0x05
#define TWL4030_PM_RECEIVER_VDAC_VSEL_18 0x03
#define TWL4030_PM_RECEIVER_VMMC1_VSEL_30 0x02
#define TWL4030_PM_RECEIVER_VMMC1_VSEL_32 0x03
+#define TWL4030_PM_RECEIVER_VMMC2_VSEL_30 0x0B
+#define TWL4030_PM_RECEIVER_VMMC2_VSEL_32 0x0C
#define TWL4030_PM_RECEIVER_VSIM_VSEL_18 0x03
/* Device Selection in PM Receiver Module */
unsigned int slot_id;
};
+struct int_queue;
+
/*
* You can initialize platform's USB host or device
* ports by passing this enum as an argument to
defined(CONFIG_USB_OMAP3) || defined(CONFIG_USB_DA8XX) || \
defined(CONFIG_USB_BLACKFIN) || defined(CONFIG_USB_AM35X) || \
defined(CONFIG_USB_MUSB_DSPS) || defined(CONFIG_USB_MUSB_AM35X) || \
- defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined(CONFIG_USB_XHCI)
+ defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined(CONFIG_USB_XHCI) || \
+ defined(CONFIG_USB_DWC2)
int usb_lowlevel_init(int index, enum usb_init_type init, void **controller);
int usb_lowlevel_stop(int index);
int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
int transfer_len, int interval);
+#ifdef CONFIG_USB_EHCI /* Only the ehci code has pollable int support */
+struct int_queue *create_int_queue(struct usb_device *dev, unsigned long pipe,
+ int queuesize, int elementsize, void *buffer);
+int destroy_int_queue(struct usb_device *dev, struct int_queue *queue);
+void *poll_int_queue(struct usb_device *dev, struct int_queue *queue);
+#endif
+
/* Defines */
#define USB_UHCI_VEND_ID 0x8086
#define USB_UHCI_DEV_ID 0x7112
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Gerry Hamel, geh@ti.com, Texas Instruments
- *
- * Based on
- * linux/drivers/usb/device/bi/omap.h
- * Register definitions for TI OMAP1510 USB bus interface driver
- *
- * Author: MontaVista Software, Inc.
- * source@mvista.com
- *
- * 2003 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __USBDCORE_OMAP1510_H__
-#define __USBDCORE_OMAP1510_H__
-
-
-/*
- * 13.2 MPU Register Map
- */
-
-/* Table 13-1. USB Function Module Registers (endpoint) */
-#define UDC_BASE 0xFFFB4000
-#define UDC_OFFSET(offset) (UDC_BASE + (offset))
-#define UDC_REV UDC_OFFSET(0x0) /* Revision */
-#define UDC_EP_NUM UDC_OFFSET(0x4) /* Endpoint selection */
-#define UDC_DATA UDC_OFFSET(0x08) /* Data */
-#define UDC_CTRL UDC_OFFSET(0x0C) /* Control */
-#define UDC_STAT_FLG UDC_OFFSET(0x10) /* Status flag */
-#define UDC_RXFSTAT UDC_OFFSET(0x14) /* Receive FIFO status */
-#define UDC_SYSCON1 UDC_OFFSET(0x18) /* System configuration 1 */
-#define UDC_SYSCON2 UDC_OFFSET(0x1C) /* System configuration 2 */
-#define UDC_DEVSTAT UDC_OFFSET(0x20) /* Device status */
-#define UDC_SOF UDC_OFFSET(0x24) /* Start of frame */
-#define UDC_IRQ_EN UDC_OFFSET(0x28) /* Interrupt enable */
-#define UDC_DMA_IRQ_EN UDC_OFFSET(0x2C) /* DMA interrupt enable */
-#define UDC_IRQ_SRC UDC_OFFSET(0x30) /* Interrupt source */
-#define UDC_EPN_STAT UDC_OFFSET(0x34) /* Endpoint interrupt status */
-#define UDC_DMAN_STAT UDC_OFFSET(0x3C) /* DMA endpoint interrupt status */
-
-/* IRQ_EN register fields */
-#define UDC_Sof_IE (1 << 7) /* Start-of-frame interrupt enabled */
-#define UDC_EPn_RX_IE (1 << 5) /* Receive endpoint interrupt enabled */
-#define UDC_EPn_TX_IE (1 << 4) /* Transmit endpoint interrupt enabled */
-#define UDC_DS_Chg_IE (1 << 3) /* Device state changed interrupt enabled */
-#define UDC_EP0_IE (1 << 0) /* EP0 transaction interrupt enabled */
-
-/* IRQ_SRC register fields */
-#define UDC_TXn_Done (1 << 10) /* Transmit DMA channel n done */
-#define UDC_RXn_Cnt (1 << 9) /* Receive DMA channel n transactions count */
-#define UDC_RXn_EOT (1 << 8) /* Receive DMA channel n end of transfer */
-#define UDC_SOF_Flg (1 << 7) /* Start-of-frame interrupt flag */
-#define UDC_EPn_RX (1 << 5) /* Endpoint n OUT transaction */
-#define UDC_EPn_TX (1 << 4) /* Endpoint n IN transaction */
-#define UDC_DS_Chg (1 << 3) /* Device state changed */
-#define UDC_Setup (1 << 2) /* Setup transaction */
-#define UDC_EP0_RX (1 << 1) /* EP0 OUT transaction */
-#define UDC_EP0_TX (1 << 0) /* EP0 IN transaction */
-
-/* DEVSTAT register fields, 14.2.9 */
-#define UDC_R_WK_OK (1 << 6) /* Remote wakeup granted */
-#define UDC_USB_Reset (1 << 5) /* USB reset signalling is active */
-#define UDC_SUS (1 << 4) /* Suspended state */
-#define UDC_CFG (1 << 3) /* Configured state */
-#define UDC_ADD (1 << 2) /* Addressed state */
-#define UDC_DEF (1 << 1) /* Default state */
-#define UDC_ATT (1 << 0) /* Attached state */
-
-/* SYSCON1 register fields */
-#define UDC_Cfg_Lock (1 << 8) /* Device configuration locked */
-#define UDC_Nak_En (1 << 4) /* NAK enable */
-#define UDC_Self_Pwr (1 << 2) /* Device is self-powered */
-#define UDC_Soff_Dis (1 << 1) /* Shutoff disabled */
-#define UDC_Pullup_En (1 << 0) /* External pullup enabled */
-
-/* SYSCON2 register fields */
-#define UDC_Rmt_Wkp (1 << 6) /* Remote wakeup */
-#define UDC_Stall_Cmd (1 << 5) /* Stall endpoint */
-#define UDC_Dev_Cfg (1 << 3) /* Device configured */
-#define UDC_Clr_Cfg (1 << 2) /* Clear configured */
-
-/*
- * Select and enable endpoints
- */
-
-/* Table 13-1. USB Function Module Registers (endpoint configuration) */
-#define UDC_EPBASE UDC_OFFSET(0x80) /* Endpoints base address */
-#define UDC_EP0 UDC_EPBASE /* Control endpoint configuration */
-#define UDC_EP_RX_BASE UDC_OFFSET(0x84) /* Receive endpoints base address */
-#define UDC_EP_RX(endpoint) (UDC_EP_RX_BASE + ((endpoint) - 1) * 4)
-#define UDC_EP_TX_BASE UDC_OFFSET(0xC4) /* Transmit endpoints base address */
-#define UDC_EP_TX(endpoint) (UDC_EP_TX_BASE + ((endpoint) - 1) * 4)
-
-/* EP_NUM register fields */
-#define UDC_Setup_Sel (1 << 6) /* Setup FIFO select */
-#define UDC_EP_Sel (1 << 5) /* TX/RX FIFO select */
-#define UDC_EP_Dir (1 << 4) /* Endpoint direction */
-
-/* CTRL register fields */
-#define UDC_Clr_Halt (1 << 7) /* Clear halt endpoint */
-#define UDC_Set_Halt (1 << 6) /* Set halt endpoint */
-#define UDC_Set_FIFO_En (1 << 2) /* Set FIFO enable */
-#define UDC_Clr_EP (1 << 1) /* Clear endpoint */
-#define UDC_Reset_EP (1 << 0) /* Reset endpoint */
-
-/* STAT_FLG register fields */
-#define UDC_Miss_In (1 << 14)
-#define UDC_Data_Flush (1 << 13)
-#define UDC_ISO_Err (1 << 12)
-#define UDC_ISO_FIFO_Empty (1 << 9)
-#define UDC_ISO_FIFO_Full (1 << 8)
-#define UDC_EP_Halted (1 << 6)
-#define UDC_STALL (1 << 5)
-#define UDC_NAK (1 << 4)
-#define UDC_ACK (1 << 3)
-#define UDC_FIFO_En (1 << 2)
-#define UDC_Non_ISO_FIFO_Empty (1 << 1)
-#define UDC_Non_ISO_FIFO_Full (1 << 0)
-
-/* EPn_RX register fields */
-#define UDC_EPn_RX_Valid (1 << 15) /* valid */
-#define UDC_EPn_RX_Db (1 << 14) /* double-buffer */
-#define UDC_EPn_RX_Iso (1 << 11) /* isochronous */
-
-/* EPn_TX register fields */
-#define UDC_EPn_TX_Valid (1 << 15) /* valid */
-#define UDC_EPn_TX_Db (1 << 14) /* double-buffer */
-#define UDC_EPn_TX_Iso (1 << 11) /* isochronous */
-
-#define EP0_PACKETSIZE 0x40
-
-/* physical to logical endpoint mapping
- * Physical endpoints are an index into device->bus->endpoint_array.
- * Logical endpoints are endpoints 0 to 15 IN and OUT as defined in
- * the USB specification.
- *
- * physical ep logical ep direction endpoint_address
- * 0 0 IN and OUT 0x00
- * 1 to 15 1 to 15 OUT 0x01 to 0x0f
- * 16 to 30 1 to 15 IN 0x81 to 0x8f
- */
-#define PHYS_EP_TO_EP_ADDR(ep) (((ep) < 16) ? (ep) : (((ep) - 15) | 0x80))
-#define EP_ADDR_TO_PHYS_EP(a) (((a) & 0x80) ? (((a) & ~0x80) + 15) : (a))
-
-/* MOD_CONF_CTRL_0 bits (FIXME: move to board hardware.h ?) */
-#define CONF_MOD_USB_W2FC_VBUS_MODE_R (1 << 17)
-
-/* Other registers (may be) related to USB */
-
-#define CLOCK_CTRL (0xFFFE0830)
-#define APLL_CTRL (0xFFFE084C)
-#define DPLL_CTRL (0xFFFE083C)
-#define SOFT_REQ (0xFFFE0834)
-#define STATUS_REQ (0xFFFE0840)
-
-/* FUNC_MUX_CTRL_0 bits related to USB */
-#define UDC_VBUS_CTRL (1 << 19)
-#define UDC_VBUS_MODE (1 << 18)
-
-/* OMAP Endpoint parameters */
-#define UDC_OUT_PACKET_SIZE 64
-#define UDC_IN_PACKET_SIZE 64
-#define UDC_INT_PACKET_SIZE 16
-#define UDC_BULK_PACKET_SIZE 16
-
-#define UDC_INT_ENDPOINT 5
-#define UDC_OUT_ENDPOINT 2
-#define UDC_IN_ENDPOINT 1
-
-#endif
#include <config.h>
#include <common.h>
+#include <inttypes.h>
#include <version.h>
#include <linux/ctype.h>
#include <asm/io.h>
return 0;
}
-/*
- * print sizes as "xxx KiB", "xxx.y KiB", "xxx MiB", "xxx.y MiB",
- * xxx GiB, xxx.y GiB, etc as needed; allow for optional trailing string
- * (like "\n")
- */
-void print_size(unsigned long long size, const char *s)
+void print_size(uint64_t size, const char *s)
{
unsigned long m = 0, n;
- unsigned long long f;
+ uint64_t f;
static const char names[] = {'E', 'P', 'T', 'G', 'M', 'K'};
unsigned long d = 10 * ARRAY_SIZE(names);
char c = 0;
}
if (!c) {
- printf("%llu Bytes%s", size, s);
+ printf("%" PRIu64 " Bytes%s", size, s);
return;
}
else
x = lb.uc[i] = *(volatile uint8_t *)data;
#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
- printf(" %0*llx", width * 2, x);
+ printf(" %0*" PRIx64, width * 2, x);
#else
printf(" %0*x", width * 2, x);
#endif
return lmb_add_region(_rgn, base, size);
}
-long lmb_overlaps_region(struct lmb_region *rgn, phys_addr_t base,
+static long lmb_overlaps_region(struct lmb_region *rgn, phys_addr_t base,
phys_size_t size)
{
unsigned long i;
extern unsigned long __weak timer_read_counter(void);
#endif
-unsigned long long __weak notrace get_ticks(void)
+uint64_t __weak notrace get_ticks(void)
{
unsigned long now = timer_read_counter();
if (now < gd->timebase_l)
gd->timebase_h++;
gd->timebase_l = now;
- return ((unsigned long long)gd->timebase_h << 32) | gd->timebase_l;
+ return ((uint64_t)gd->timebase_h << 32) | gd->timebase_l;
}
/* Returns time in milliseconds */
-static unsigned long long notrace tick_to_time(unsigned long long tick)
+static uint64_t notrace tick_to_time(uint64_t tick)
{
ulong div = get_tbclk();
return tick_to_time(get_ticks() * 1000);
}
-static unsigned long long usec_to_tick(unsigned long usec)
+static uint64_t usec_to_tick(unsigned long usec)
{
- unsigned long long tick = usec;
+ uint64_t tick = usec;
tick *= get_tbclk();
do_div(tick, 1000000);
return tick;
void __weak __udelay(unsigned long usec)
{
- unsigned long long tmp;
+ uint64_t tmp;
tmp = get_ticks() + usec_to_tick(usec); /* get current timestamp */
return buf;
}
/* No inlining helps gcc to use registers better */
-static noinline char *put_dec(char *buf, u64 num)
+static noinline char *put_dec(char *buf, uint64_t num)
{
while (1) {
unsigned rem;
setenv("ethact", NULL);
}
-int eth_address_set(unsigned char *addr)
+static int eth_address_set(unsigned char *addr)
{
return memcmp(addr, "\0\0\0\0\0\0", 6);
}
* Boards with hotkey support can override this weak default function
* by defining one in their board specific code.
*/
-int __post_hotkeys_pressed(void)
+__weak int post_hotkeys_pressed(void)
{
#ifdef CONFIG_SYS_POST_HOTKEYS_GPIO
int ret;
return 0; /* No hotkeys supported */
}
-int post_hotkeys_pressed(void)
- __attribute__((weak, alias("__post_hotkeys_pressed")));
-
void post_bootmode_init(void)
{
test_flags[j] |= POST_SLOWTEST;
}
-void __show_post_progress(unsigned int test_num, int before, int result)
+__weak void show_post_progress(unsigned int test_num, int before, int result)
{
}
-void show_post_progress(unsigned int, int, int)
- __attribute__((weak, alias("__show_post_progress")));
static int post_run_single(struct post_test *test,
int test_flags, int flags, unsigned int i)
# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.build obj=
# Usage:
# $(Q)$(MAKE) $(build)=dir
-build := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.build obj
+build := -f $(srctree)/scripts/Makefile.build obj
###
# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.modbuiltin obj=
# Usage:
# $(Q)$(MAKE) $(modbuiltin)=dir
-modbuiltin := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.modbuiltin obj
+modbuiltin := -f $(srctree)/scripts/Makefile.modbuiltin obj
# Prefix -I with $(srctree) if it is not an absolute path.
# skip if -I has no parameter
arg-check = $(if $(strip $(cmd_$@)),,1)
endif
-# >'< substitution is for echo to work,
-# >$< substitution to preserve $ when reloading .cmd file
-# note: when using inline perl scripts [perl -e '...$$t=1;...']
-# in $(cmd_xxx) double $$ your perl vars
-make-cmd = $(subst \\,\\\\,$(subst \#,\\\#,$(subst $$,$$$$,$(call escsq,$(cmd_$(1))))))
+# Replace >$< with >$$< to preserve $ when reloading the .cmd file
+# (needed for make)
+# Replace >#< with >\#< to avoid starting a comment in the .cmd file
+# (needed for make)
+# Replace >'< with >'\''< to be able to enclose the whole string in '...'
+# (needed for the shell)
+make-cmd = $(call escsq,$(subst \#,\\\#,$(subst $$,$$$$,$(cmd_$(1)))))
# Find any prerequisites that is newer than target or that does not exist.
# PHONY targets skipped in both cases.
if_changed = $(if $(strip $(any-prereq) $(arg-check)), \
@set -e; \
$(echo-cmd) $(cmd_$(1)); \
- echo 'cmd_$@ := $(make-cmd)' > $(dot-target).cmd)
+ printf '%s\n' 'cmd_$@ := $(make-cmd)' > $(dot-target).cmd)
# Execute the command and also postprocess generated .d dependencies file.
if_changed_dep = $(if $(strip $(any-prereq) $(arg-check) ), \
create_symlink:
ifneq ($(KBUILD_SRC),)
$(Q)mkdir -p include/asm
+ $(Q)ln -fsn $(KBUILD_SRC)/arch/$(ARCH)/include/asm/arch-$(if $(SOC),$(SOC),$(CPU)) \
+ include/asm/arch
+else
+ $(Q)ln -fsn arch-$(if $(SOC),$(SOC),$(CPU)) \
+ arch/$(ARCH)/include/asm/arch
endif
- $(Q)ln -fsn $(srctree)/arch/$(ARCH)/include/asm/arch-$(if $(SOC),$(SOC),$(CPU)) \
- $(if $(KBUILD_SRC),,arch/$(ARCH)/)include/asm/arch
PHONY += FORCE
FORCE:
# ===========================================================================
-ifneq ($(strip $(lib-y) $(lib-m) $(lib-n) $(lib-)),)
+ifneq ($(strip $(lib-y) $(lib-m) $(lib-)),)
lib-target := $(obj)/lib.a
endif
-ifneq ($(strip $(obj-y) $(obj-m) $(obj-n) $(obj-) $(subdir-m) $(lib-target)),)
+ifneq ($(strip $(obj-y) $(obj-m) $(obj-) $(subdir-m) $(lib-target)),)
builtin-target := $(obj)/built-in.o
endif
quiet_cmd_link_multi-m = LD [M] $@
cmd_link_multi-m = $(cmd_link_multi-y)
-# We would rather have a list of rules like
-# foo.o: $(foo-objs)
-# but that's not so easy, so we rather make all composite objects depend
-# on the set of all their parts
-$(multi-used-y) : %.o: $(multi-objs-y) FORCE
+$(multi-used-y): FORCE
$(call if_changed,link_multi-y)
+$(call multi_depend, $(multi-used-y), .o, -objs -y)
-$(multi-used-m) : %.o: $(multi-objs-m) FORCE
+$(multi-used-m): FORCE
$(call if_changed,link_multi-m)
@{ echo $(@:.o=.ko); echo $(link_multi_deps); } > $(MODVERDIR)/$(@F:.o=.mod)
+$(call multi_depend, $(multi-used-m), .o, -objs -y)
targets += $(multi-used-y) $(multi-used-m)
# Shorthand for $(Q)$(MAKE) scripts/Makefile.clean obj=dir
# Usage:
# $(Q)$(MAKE) $(clean)=dir
-clean := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.clean obj
+clean := -f $(srctree)/scripts/Makefile.clean obj
# The filename Kbuild has precedence over Makefile
kbuild-dir := $(if $(filter /%,$(src)),$(src),$(srctree)/$(src))
subdir-y += $(__subdir-y)
__subdir-m := $(patsubst %/,%,$(filter %/, $(obj-m)))
subdir-m += $(__subdir-m)
-__subdir-n := $(patsubst %/,%,$(filter %/, $(obj-n)))
-subdir-n += $(__subdir-n)
__subdir- := $(patsubst %/,%,$(filter %/, $(obj-)))
subdir- += $(__subdir-)
# Subdirectories we need to descend into
subdir-ym := $(sort $(subdir-y) $(subdir-m))
-subdir-ymn := $(sort $(subdir-ym) $(subdir-n) $(subdir-))
+subdir-ymn := $(sort $(subdir-ym) $(subdir-))
# Add subdir path
warning-1 += $(call cc-option, -Wunused-but-set-variable)
warning-1 += $(call cc-disable-warning, missing-field-initializers)
-# Clang
-warning-1 += $(call cc-disable-warning, initializer-overrides)
-warning-1 += $(call cc-disable-warning, unused-value)
-warning-1 += $(call cc-disable-warning, format)
-warning-1 += $(call cc-disable-warning, unknown-warning-option)
-warning-1 += $(call cc-disable-warning, sign-compare)
-warning-1 += $(call cc-disable-warning, format-zero-length)
-warning-1 += $(call cc-disable-warning, uninitialized)
-warning-1 += $(call cc-option, -fcatch-undefined-behavior)
-
warning-2 := -Waggregate-return
warning-2 += -Wcast-align
warning-2 += -Wdisabled-optimization
# Will compile qconf as a C++ program, and menu as a C program.
# They are linked as C++ code to the executable qconf
-# hostprogs-y := conf
-# conf-objs := conf.o libkconfig.so
-# libkconfig-objs := expr.o type.o
-# Will create a shared library named libkconfig.so that consists of
-# expr.o and type.o (they are both compiled as C code and the object files
-# are made as position independent code).
-# conf.c is compiled as a C program, and conf.o is linked together with
-# libkconfig.so as the executable conf.
-# Note: Shared libraries consisting of C++ files are not supported
-
__hostprogs := $(sort $(hostprogs-y) $(hostprogs-m))
# C code
# Executables compiled from a single .c file
-host-csingle := $(foreach m,$(__hostprogs),$(if $($(m)-objs),,$(m)))
+host-csingle := $(foreach m,$(__hostprogs), \
+ $(if $($(m)-objs)$($(m)-cxxobjs),,$(m)))
# C executables linked based on several .o files
host-cmulti := $(foreach m,$(__hostprogs),\
host-cobjs := $(sort $(foreach m,$(__hostprogs),$($(m)-objs)))
# C++ code
-# C++ executables compiled from at least on .cc file
+# C++ executables compiled from at least one .cc file
# and zero or more .c files
host-cxxmulti := $(foreach m,$(__hostprogs),$(if $($(m)-cxxobjs),$(m)))
# C++ Object (.o) files compiled from .cc files
host-cxxobjs := $(sort $(foreach m,$(host-cxxmulti),$($(m)-cxxobjs)))
-# Shared libaries (only .c supported)
-# Shared libraries (.so) - all .so files referenced in "xxx-objs"
-host-cshlib := $(sort $(filter %.so, $(host-cobjs)))
-# Remove .so files from "xxx-objs"
-host-cobjs := $(filter-out %.so,$(host-cobjs))
-
-#Object (.o) files used by the shared libaries
-host-cshobjs := $(sort $(foreach m,$(host-cshlib),$($(m:.so=-objs))))
-
# output directory for programs/.o files
-# hostprogs-y := tools/build may have been specified. Retrieve directory
-host-objdirs := $(foreach f,$(__hostprogs), $(if $(dir $(f)),$(dir $(f))))
-# directory of .o files from prog-objs notation
-host-objdirs += $(foreach f,$(host-cmulti), \
- $(foreach m,$($(f)-objs), \
- $(if $(dir $(m)),$(dir $(m)))))
-# directory of .o files from prog-cxxobjs notation
-host-objdirs += $(foreach f,$(host-cxxmulti), \
- $(foreach m,$($(f)-cxxobjs), \
- $(if $(dir $(m)),$(dir $(m)))))
+# hostprogs-y := tools/build may have been specified.
+# Retrieve also directory of .o files from prog-objs or prog-cxxobjs notation
+host-objdirs := $(dir $(__hostprogs) $(host-cobjs) $(host-cxxobjs))
host-objdirs := $(strip $(sort $(filter-out ./,$(host-objdirs))))
host-cobjs := $(addprefix $(obj)/,$(host-cobjs))
host-cxxmulti := $(addprefix $(obj)/,$(host-cxxmulti))
host-cxxobjs := $(addprefix $(obj)/,$(host-cxxobjs))
-host-cshlib := $(addprefix $(obj)/,$(host-cshlib))
-host-cshobjs := $(addprefix $(obj)/,$(host-cshobjs))
host-objdirs := $(addprefix $(obj)/,$(host-objdirs))
obj-dirs += $(host-objdirs)
cmd_host-cmulti = $(HOSTCC) $(HOSTLDFLAGS) -o $@ \
$(addprefix $(obj)/,$($(@F)-objs)) \
$(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F))
-$(host-cmulti): $(obj)/%: $(host-cobjs) $(host-cshlib) FORCE
+$(host-cmulti): FORCE
$(call if_changed,host-cmulti)
+$(call multi_depend, $(host-cmulti), , -objs)
# Create .o file from a single .c file
# host-cobjs -> .o
$(foreach o,objs cxxobjs,\
$(addprefix $(obj)/,$($(@F)-$(o)))) \
$(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F))
-$(host-cxxmulti): $(obj)/%: $(host-cobjs) $(host-cxxobjs) $(host-cshlib) FORCE
+$(host-cxxmulti): FORCE
$(call if_changed,host-cxxmulti)
+$(call multi_depend, $(host-cxxmulti), , -objs -cxxobjs)
# Create .o file from a single .cc (C++) file
quiet_cmd_host-cxxobjs = HOSTCXX $@
$(host-cxxobjs): $(obj)/%.o: $(src)/%.cc FORCE
$(call if_changed_dep,host-cxxobjs)
-# Compile .c file, create position independent .o file
-# host-cshobjs -> .o
-quiet_cmd_host-cshobjs = HOSTCC -fPIC $@
- cmd_host-cshobjs = $(HOSTCC) $(hostc_flags) -fPIC -c -o $@ $<
-$(host-cshobjs): $(obj)/%.o: $(src)/%.c FORCE
- $(call if_changed_dep,host-cshobjs)
-
-# Link a shared library, based on position independent .o files
-# *.o -> .so shared library (host-cshlib)
-quiet_cmd_host-cshlib = HOSTLLD -shared $@
- cmd_host-cshlib = $(HOSTCC) $(HOSTLDFLAGS) -shared -o $@ \
- $(addprefix $(obj)/,$($(@F:.so=-objs))) \
- $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F))
-$(host-cshlib): $(obj)/%: $(host-cshobjs) FORCE
- $(call if_changed,host-cshlib)
-
targets += $(host-csingle) $(host-cmulti) $(host-cobjs)\
- $(host-cxxmulti) $(host-cxxobjs) $(host-cshlib) $(host-cshobjs)
+ $(host-cxxmulti) $(host-cxxobjs)
modname-multi = $(sort $(foreach m,$(multi-used),\
$(if $(filter $(subst $(obj)/,,$*.o), $($(m:.o=-objs)) $($(m:.o=-y))),$(m:.o=))))
+# Useful for describing the dependency of composite objects
+# Usage:
+# $(call multi_depend, multi_used_targets, suffix_to_remove, suffix_to_add)
+define multi_depend
+$(foreach m, $(notdir $1), \
+ $(eval $(obj)/$m: \
+ $(addprefix $(obj)/, $(foreach s, $3, $($(m:%$(strip $2)=%$(s)))))))
+endef
+
ifdef REGENERATE_PARSERS
# GPERF
%_defconfig: $(obj)/conf
$(Q)$< --defconfig=arch/$(SRCARCH)/configs/$@ $(Kconfig)
+configfiles=$(wildcard $(srctree)/kernel/configs/$(1).config $(srctree)/arch/$(SRCARCH)/configs/$(1).config)
+
+define mergeconfig
+$(if $(wildcard $(objtree)/.config),, $(error You need an existing .config for this target))
+$(if $(call configfiles,$(1)),, $(error No configuration exists for this target on this architecture))
+$(Q)$(CONFIG_SHELL) $(srctree)/scripts/kconfig/merge_config.sh -m -O $(objtree) $(objtree)/.config $(call configfiles,$(1))
+$(Q)yes "" | $(MAKE) -f $(srctree)/Makefile oldconfig
+endef
+
+PHONY += kvmconfig
+kvmconfig:
+ $(call mergeconfig,kvm_guest)
+
+PHONY += tinyconfig
+tinyconfig: allnoconfig
+ $(call mergeconfig,tiny)
+
# Help text used by make help
help:
@echo ' config - Update current config utilising a line-oriented program'
@echo ' randconfig - New config with random answer to all options'
@echo ' listnewconfig - List new options'
@echo ' olddefconfig - Same as silentoldconfig but sets new symbols to their default value'
+# @echo ' kvmconfig - Enable additional options for guest kernel support'
+# @echo ' tinyconfig - Configure the tiniest possible kernel'
# lxdialog stuff
check-lxdialog := $(srctree)/$(src)/lxdialog/check-lxdialog.sh
qconf-objs := zconf.tab.o
gconf-objs := gconf.o zconf.tab.o
-hostprogs-y := conf
-
-ifeq ($(MAKECMDGOALS),nconfig)
- hostprogs-y += nconf
-endif
-
-ifeq ($(MAKECMDGOALS),menuconfig)
- hostprogs-y += mconf
-endif
-
-ifeq ($(MAKECMDGOALS),update-po-config)
- hostprogs-y += kxgettext
-endif
-
-ifeq ($(MAKECMDGOALS),xconfig)
- qconf-target := 1
-endif
-ifeq ($(MAKECMDGOALS),gconfig)
- gconf-target := 1
-endif
-
-
-ifeq ($(qconf-target),1)
- hostprogs-y += qconf
-endif
-
-ifeq ($(gconf-target),1)
- hostprogs-y += gconf
-endif
+hostprogs-y := conf nconf mconf kxgettext qconf gconf
clean-files := qconf.moc .tmp_qtcheck .tmp_gtkcheck
clean-files += zconf.tab.c zconf.lex.c zconf.hash.c gconf.glade.h
-clean-files += mconf qconf gconf nconf
clean-files += config.pot linux.pot
# Check that we have the required ncurses stuff installed for lxdialog (menuconfig)
HOSTLOADLIBES_mconf = $(shell $(CONFIG_SHELL) $(check-lxdialog) -ldflags $(HOSTCC))
HOSTLOADLIBES_nconf = $(shell \
- pkg-config --libs menu panel ncurses 2>/dev/null \
+ pkg-config --libs menuw panelw ncursesw 2>/dev/null \
+ || pkg-config --libs menu panel ncurses 2>/dev/null \
|| echo "-lmenu -lpanel -lncurses" )
$(obj)/qconf.o: $(obj)/.tmp_qtcheck
-ifeq ($(qconf-target),1)
+ifeq ($(MAKECMDGOALS),xconfig)
$(obj)/.tmp_qtcheck: $(src)/Makefile
-include $(obj)/.tmp_qtcheck
$(obj)/gconf.o: $(obj)/.tmp_gtkcheck
-ifeq ($(gconf-target),1)
+ifeq ($(MAKECMDGOALS),gconfig)
-include $(obj)/.tmp_gtkcheck
# GTK needs some extra effort, too...
/* item list manipulation for lxdialog use */
#define MAXITEMSTR 200
struct dialog_item {
- char str[MAXITEMSTR]; /* promtp displayed */
+ char str[MAXITEMSTR]; /* prompt displayed */
char tag;
void *data; /* pointer to menu item - used by menubox+checklist */
int selected; /* Set to 1 by dialog_*() function if selected. */
echo "Using $INITFILE as base"
cat $INITFILE > $TMP_FILE
-# Merge files, printing warnings on overrided values
+# Merge files, printing warnings on overridden values
for MERGE_FILE in $MERGE_LIST ; do
echo "Merging $MERGE_FILE"
CFG_LIST=$(sed -n "$SED_CONFIG_EXP" $MERGE_FILE)
sub dump_function($$) {
my $prototype = shift;
my $file = shift;
+ my $noret = 0;
$prototype =~ s/^static +//;
$prototype =~ s/^extern +//;
$prototype =~ s/^noinline +//;
$prototype =~ s/__init +//;
$prototype =~ s/__init_or_module +//;
+ $prototype =~ s/__meminit +//;
$prototype =~ s/__must_check +//;
$prototype =~ s/__weak +//;
- $prototype =~ s/^#\s*define\s+//; #ak added
+ my $define = $prototype =~ s/^#\s*define\s+//; #ak added
$prototype =~ s/__attribute__\s*\(\([a-z,]*\)\)//;
# Yes, this truly is vile. We are looking for:
# - atomic_set (macro)
# - pci_match_device, __copy_to_user (long return type)
- if ($prototype =~ m/^()([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
+ if ($define && $prototype =~ m/^()([a-zA-Z0-9_~:]+)\s+/) {
+ # This is an object-like macro, it has no return type and no parameter
+ # list.
+ # Function-like macros are not allowed to have spaces between
+ # declaration_name and opening parenthesis (notice the \s+).
+ $return_type = $1;
+ $declaration_name = $2;
+ $noret = 1;
+ } elsif ($prototype =~ m/^()([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
$prototype =~ m/^(\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
$prototype =~ m/^(\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
$prototype =~ m/^(\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
# of warnings goes sufficiently down, the check is only performed in
# verbose mode.
# TODO: always perform the check.
- if ($verbose) {
+ if ($verbose && !$noret) {
check_return_section($file, $declaration_name, $return_type);
}
fi
}
+do_board_felconfig () {
+ do_board_defconfig ${1%%_felconfig}_defconfig
+ if ! grep -q CONFIG_ARCH_SUNXI=y .config || ! grep -q CONFIG_SPL=y .config ; then
+ echo "$progname: Cannot felconfig a non-sunxi or non-SPL platform" >&2
+ exit 1
+ fi
+ sed -i -e 's/\# CONFIG_SPL_FEL is not set/CONFIG_SPL_FEL=y/g' \
+ .config spl/.config
+}
+
do_savedefconfig () {
if [ -r "$KCONFIG_CONFIG" ]; then
subimages=$(get_enabled_subimages)
case $target in
*_defconfig)
do_board_defconfig $target;;
+*_felconfig)
+ do_board_felconfig $target;;
*_config)
# backward compatibility
do_board_defconfig ${target%_config}_defconfig;;
assert(run_command_list("false", -1, 0) == 1);
assert(run_command_list("echo", -1, 0) == 0);
+ run_command("setenv foo 'setenv monty 1; setenv python 2'", 0);
+ run_command("run foo", 0);
+ assert(getenv("monty") != NULL);
+ assert(!strcmp("1", getenv("monty")));
+ assert(getenv("python") != NULL);
+ assert(!strcmp("2", getenv("python")));
+
#ifdef CONFIG_SYS_HUSH_PARSER
+ run_command("setenv foo 'setenv black 1\nsetenv adder 2'", 0);
+ run_command("run foo", 0);
+ assert(getenv("black") != NULL);
+ assert(!strcmp("1", getenv("black")));
+ assert(getenv("adder") != NULL);
+ assert(!strcmp("2", getenv("adder")));
+
/* Test the 'test' command */
#define HUSH_TEST(name, expr, expected_result) \
#endif
#endif
+ assert(run_command("", 0) == 0);
+ assert(run_command(" ", 0) == 0);
+
+ assert(run_command("'", 0) == 1);
+
printf("%s: Everything went swimmingly\n", __func__);
return 0;
}
.platdata = &test_pdata_manual,
};
+void dm_leak_check_start(struct dm_test_state *dms)
+{
+ dms->start = mallinfo();
+ if (!dms->start.uordblks)
+ puts("Warning: Please add '#define DEBUG' to the top of common/dlmalloc.c\n");
+}
+
+int dm_leak_check_end(struct dm_test_state *dms)
+{
+ struct mallinfo end;
+ int id;
+
+ /* Don't delete the root class, since we started with that */
+ for (id = UCLASS_ROOT + 1; id < UCLASS_COUNT; id++) {
+ struct uclass *uc;
+
+ uc = uclass_find(id);
+ if (!uc)
+ continue;
+ ut_assertok(uclass_destroy(uc));
+ }
+
+ end = mallinfo();
+ ut_asserteq(dms->start.uordblks, end.uordblks);
+
+ return 0;
+}
+
/* Test that binding with platdata occurs correctly */
static int dm_test_autobind(struct dm_test_state *dms)
{
int i;
for (i = 0; i < 2; i++) {
- struct mallinfo start, end;
struct udevice *dev;
int ret;
int id;
- start = mallinfo();
- if (!start.uordblks)
- puts("Warning: Please add '#define DEBUG' to the top of common/dlmalloc.c\n");
+ dm_leak_check_start(dms);
ut_assertok(dm_scan_platdata(false));
ut_assertok(dm_scan_fdt(gd->fdt_blob, false));
ut_assertok(ret);
}
- /* Don't delete the root class, since we started with that */
- for (id = UCLASS_ROOT + 1; id < UCLASS_COUNT; id++) {
- struct uclass *uc;
-
- uc = uclass_find(id);
- if (!uc)
- continue;
- ut_assertok(uclass_destroy(uc));
- }
-
- end = mallinfo();
- ut_asserteq(start.uordblks, end.uordblks);
+ ut_assertok(dm_leak_check_end(dms));
}
return 0;
#include <common.h>
#include <fdtdec.h>
#include <dm.h>
+#include <dm/root.h>
#include <dm/ut.h>
#include <dm/test.h>
#include <dm/util.h>
#include <asm/gpio.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/* Test that sandbox GPIOs work correctly */
static int dm_test_gpio(struct dm_test_state *dms)
{
/* Get the operations for this device */
ops = gpio_get_ops(dev);
- ut_assert(ops->get_state);
+ ut_assert(ops->get_function);
/* Cannot get a value until it is reserved */
- ut_asserteq(-1, ops->get_value(dev, offset));
-
+ ut_asserteq(-EBUSY, gpio_get_value(gpio + 1));
/*
* Now some tests that use the 'sandbox' back door. All GPIOs
* should default to input, include b4 that we are using here.
*/
- ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
- ut_asserteq_str("b4: in: 0 [ ]", buf);
+ ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
+ ut_asserteq_str("b4: input: 0 [ ]", buf);
/* Change it to an output */
sandbox_gpio_set_direction(dev, offset, 1);
- ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
- ut_asserteq_str("b4: out: 0 [ ]", buf);
+ ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
+ ut_asserteq_str("b4: output: 0 [ ]", buf);
sandbox_gpio_set_value(dev, offset, 1);
- ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
- ut_asserteq_str("b4: out: 1 [ ]", buf);
+ ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
+ ut_asserteq_str("b4: output: 1 [ ]", buf);
- ut_assertok(ops->request(dev, offset, "testing"));
- ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
- ut_asserteq_str("b4: out: 1 [x] testing", buf);
+ ut_assertok(gpio_request(gpio, "testing"));
+ ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
+ ut_asserteq_str("b4: output: 1 [x] testing", buf);
/* Change the value a bit */
ut_asserteq(1, ops->get_value(dev, offset));
ut_assertok(ops->set_value(dev, offset, 0));
ut_asserteq(0, ops->get_value(dev, offset));
- ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
- ut_asserteq_str("b4: out: 0 [x] testing", buf);
+ ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
+ ut_asserteq_str("b4: output: 0 [x] testing", buf);
ut_assertok(ops->set_value(dev, offset, 1));
ut_asserteq(1, ops->get_value(dev, offset));
/* Make it an input */
ut_assertok(ops->direction_input(dev, offset));
- ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
- ut_asserteq_str("b4: in: 1 [x] testing", buf);
+ ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
+ ut_asserteq_str("b4: input: 1 [x] testing", buf);
sandbox_gpio_set_value(dev, offset, 0);
ut_asserteq(0, sandbox_gpio_get_value(dev, offset));
- ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
- ut_asserteq_str("b4: in: 0 [x] testing", buf);
+ ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
+ ut_asserteq_str("b4: input: 0 [x] testing", buf);
- ut_assertok(ops->free(dev, offset));
- ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
- ut_asserteq_str("b4: in: 0 [ ]", buf);
+ ut_assertok(gpio_free(gpio));
+ ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
+ ut_asserteq_str("b4: input: 0 [ ]", buf);
/* Check the 'a' bank also */
ut_assertok(gpio_lookup_name("a15", &dev, &offset, &gpio));
ut_asserteq_str("a", name);
ut_asserteq(20, offset_count);
+ return 0;
+}
+DM_TEST(dm_test_gpio, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that sandbox anonymous GPIOs work correctly */
+static int dm_test_gpio_anon(struct dm_test_state *dms)
+{
+ unsigned int offset, gpio;
+ struct udevice *dev;
+ const char *name;
+ int offset_count;
+
/* And the anonymous bank */
ut_assertok(gpio_lookup_name("14", &dev, &offset, &gpio));
ut_asserteq_str(dev->name, "gpio_sandbox");
return 0;
}
-DM_TEST(dm_test_gpio, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+DM_TEST(dm_test_gpio_anon, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that gpio_requestf() works as expected */
+static int dm_test_gpio_requestf(struct dm_test_state *dms)
+{
+ unsigned int offset, gpio;
+ struct udevice *dev;
+ char buf[80];
+
+ ut_assertok(gpio_lookup_name("b5", &dev, &offset, &gpio));
+ ut_assertok(gpio_requestf(gpio, "testing %d %s", 1, "hi"));
+ sandbox_gpio_set_direction(dev, offset, 1);
+ sandbox_gpio_set_value(dev, offset, 1);
+ ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
+ ut_asserteq_str("b5: output: 1 [x] testing 1 hi", buf);
+
+ return 0;
+}
+DM_TEST(dm_test_gpio_requestf, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that gpio_request() copies its string */
+static int dm_test_gpio_copy(struct dm_test_state *dms)
+{
+ unsigned int offset, gpio;
+ struct udevice *dev;
+ char buf[80], name[10];
+
+ ut_assertok(gpio_lookup_name("b6", &dev, &offset, &gpio));
+ strcpy(name, "odd_name");
+ ut_assertok(gpio_request(gpio, name));
+ sandbox_gpio_set_direction(dev, offset, 1);
+ sandbox_gpio_set_value(dev, offset, 1);
+ ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
+ ut_asserteq_str("b6: output: 1 [x] odd_name", buf);
+ strcpy(name, "nothing");
+ ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
+ ut_asserteq_str("b6: output: 1 [x] odd_name", buf);
+
+ return 0;
+}
+DM_TEST(dm_test_gpio_copy, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that we don't leak memory with GPIOs */
+static int dm_test_gpio_leak(struct dm_test_state *dms)
+{
+ ut_assertok(dm_test_gpio(dms));
+ ut_assertok(dm_test_gpio_anon(dms));
+ ut_assertok(dm_test_gpio_requestf(dms));
+ ut_assertok(dm_leak_check_end(dms));
+
+ return 0;
+}
+
+DM_TEST(dm_test_gpio_leak, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
#include <common.h>
#include <dm.h>
#include <errno.h>
+#include <malloc.h>
#include <dm/test.h>
#include <dm/root.h>
#include <dm/uclass-internal.h>
printf("Test: %s\n", test->name);
ut_assertok(dm_test_init(dms));
+ dms->start = mallinfo();
if (test->flags & DM_TESTF_SCAN_PDATA)
ut_assertok(dm_scan_platdata(false));
if (test->flags & DM_TESTF_PROBE_TEST)
--- /dev/null
+#include <common.h>
+#include <inttypes.h>
+
+int test_types(void)
+{
+ uintptr_t uintptr = 0;
+ uint64_t uint64 = 0;
+ u64 u64_val = 0;
+
+ printf("uintptr = %" PRIuPTR "\n", uintptr);
+ printf("uint64 = %" PRIu64 "\n", uint64);
+ printf("u64 = %" PRIu64 "\n", u64_val);
+}
--- /dev/null
+#!/bin/bash
+
+# Test script to check uintptr_t and 64-bit types for warnings
+#
+# It builds a few boards with different toolchains. If there are no warnings
+# then all is well.
+#
+# Usage:
+#
+# Make sure that your toolchains are correct at the bottom of this file
+#
+# Then:
+# ./test/stdint/test-includes.sh
+
+out=/tmp/test-includes.tmp
+
+try_test() {
+ local board=$1
+ local arch=$2
+ local soc=$3
+ local gcc=$4
+ local flags="$5"
+
+ echo $@
+ if ! which ${gcc} >/dev/null 2>&1; then
+ echo "Not found: ${gcc}"
+ return
+ fi
+
+ rm -rf ${out}
+ mkdir -p ${out}
+ touch ${out}/config.h
+ mkdir -p ${out}/generated
+ touch ${out}/generated/generic-asm-offsets.h
+ mkdir -p ${out}/include/asm
+ ln -s $(pwd)/arch/${arch}/include/asm/arch-${soc} \
+ ${out}/include/asm/arch
+
+ cmd="${gcc} -c -D__KERNEL__ ${flags} \
+ -fno-builtin -ffreestanding \
+ -Iarch/${arch}/include \
+ -Iinclude \
+ -I${out} -I${out}/include \
+ -include configs/${board}.h test/stdint/int-types.c \
+ -o /dev/null"
+ $cmd
+}
+
+# Run a test with and without CONFIG_USE_STDINT
+try_both() {
+ try_test $@
+ try_test $@ -DCONFIG_USE_STDINT
+}
+
+# board arch soc path-to-gcc
+try_both sandbox sandbox - gcc
+try_both coreboot x86 - x86_64-linux-gnu-gcc
+try_both seaboard arm tegra20 /opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.8-2013.08_linux/bin/arm-linux-gnueabihf-gcc
+/atmel_pmecc_params
/bmp_logo
/envcrc
/fit_check_sign
#HOSTCFLAGS_mpc86x_clk.o := -pedantic
quiet_cmd_wrap = WRAP $@
-cmd_wrap = echo "\#include <$(srctree)/$(patsubst $(obj)/%,%,$@)>" >$@
+cmd_wrap = echo "\#include <../$(patsubst $(obj)/%,%,$@)>" >$@
$(obj)/lib/%.c $(obj)/common/%.c:
$(call cmd,wrap)
+++ /dev/null
-Hymod Board Database
-
-(C) Copyright 2001
-Murray Jensen <Murray.Jensen@csiro.au>
-CSIRO Manufacturing Science and Technology, Preston Lab
-
-25-Jun-01
-
-This stuff is a set of PHP/MySQL scripts to implement a custom board
-database. It will need *extensive* hacking to modify it to keep the
-information about your custom boards that you want, however it is a good
-starting point.
-
-How it is used:
-
- 1. a board has gone through all the hardware testing etc and is
- ready to have the flash programmed for the first time - first you
- go to a web page and fill in information about the board in a form
- to register it in a database
-
- 2. the web stuff allocates a (unique) serial number and (optionally)
- a (locally administered) ethernet address and stores the information
- in a database using the serial number as the key (can do whole
- batches of boards in one go and/or use a previously registered board
- as defaults for the new board(s))
-
- 3. it then creates a file in the tftp area of a server somewhere
- containing the board information in a simple text format (one
- per serial number)
-
- 4. all hymod boards have an i2c eeprom, and when U-Boot sees that
- the eeprom is unitialised, it prompts for a serial number and
- ethernet address (if not set), then transfers the file created
- in step 3 from the server and initialises the eeprom from its
- contents
-
-What this means is you can't boot the board until you have allocated a serial
-number, but you don't have to type it all twice - you do it once on the web
-and the board then finds the info it needs to initialise its eeprom. The
-other side of the coin is the reading of the eeprom and how it gets passed
-to Linux (or another O/S).
-
-To see how this is all done for the hymod boards look at the code in the
-"board/hymod" directory and in the file "include/asm/hymod.h". Hymod boards
-can have a mezzanine card which also have an eeprom that needs allocating,
-the same process is used for these as well - just a different i2c address.
-
-Other forms provide the following functions:
-
- - browsing the board database
- - editing board information (one at a time)
- - maintaining/browsing a (simple) per board event log
-
-You will need: MySQL (I use version 3.23.7-alpha), PHP4 (with MySQL
-support enabled) and a web server (I use Apache 1.3.x).
-
-I originally started by using phpMyBuilder (http://kyber.dk/phpMyBuilder)
-but it soon got far more complicated than that could handle (but I left
-the copyright messages in there anyway). Most of the code resides in the
-common defs.php file, which shouldn't need much alteration - all the work
-will be in shaping the front-end php files to your liking.
-
-Here's a quick summary of what needs doing to use it for your boards:
-
-1. get phpMyAdmin (http://phpwizard.net/projects/phpMyAdmin/) - it's an
- invaluable tool for this sort of stuff (this step is optional of course)
-
-2. edit "bddb.css" to your taste, if you could be bothered - I have no
- idea what is in there or what it does - I copied it from somewhere else
- ("user.css" from the phpMyEdit (http://phpmyedit.sourcerforge.net) package,
- I think) - I figure one day I'll see what sort of things I can change
- in there.
-
-3. create a mysql database - call it whatever you like
-
-4. edit "create_tables.sql" and modify the "boards" table schema to
- reflect the information you want to keep about your boards. It may or
- may not be easier to do this and the next step in phpMyAdmin. Check out
- the MySQL documentation at http://www.mysql.com/doc/ in particular the
- column types at http://www.mysql.com/doc/C/o/Column_types.html - Note
- there is only support for a few data types:
-
- int - presented as an html text input
- char/text - presented as an html text input
- date - presented as an html text input
- enum - presented as an html radio input
-
- I also have what I call "enum_multi" which is a set of enums with the
- same name, but suffixed with a number e.g. fred0, fred1, fred2. These
- are presented as a number of html select's with a single label "fred"
- this is useful for board characteristics that have multiple items of
- the same type e.g. multiple banks of sdram.
-
-5. use the "create_tables.sql" file to create the "boards" table in the
- database e.g. mysql dbname < create_tables.sql
-
-6. create a user and password for the web server to log into the MySQL
- database with; give this user select, insert and update privileges
- to the database created in 3 (and delete, if you want the "delete"
- functions in the edit forms to work- I have this turned off). phpMyAdmin
- helps in this step.
-
-7. edit "config.php" and set the variables: $mysql_user, $mysql_pw, $mysql_db,
- $bddb_cfgdir and $bddb_label - keep the contents of this file secret - it
- contains the web servers username and password (the three $mysql_* vars
- are set from the previous step)
-
-8. edit "defs.php" and a. adjust the various enum value arrays and b. edit
- the function "pg_foot()" to remove my email address :-)
-
-9. do major hacking on the following files: browse.php, doedit.php, donew.php,
- edit.php and new.php to reflect your database schema - fortunately the
- hacking is fairly straight-forward, but it is boring and time-consuming.
-
-These notes were written rather hastily - if you find any obvious problems
-please let me know.
+++ /dev/null
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
- // (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@csiro.au>
- // CSIRO Manufacturing Science and Technology, Preston Lab
-
- require("defs.php");
- pg_head("$bddb_label - Unknown Submit Type");
-?>
-<center>
- <font size="+4">
- <b>
- The <?php echo "$bddb_label"; ?> form was submitted with an
- unknown SUBMIT type <?php echo "(value was '$submit')" ?>.
- <br></br>
- Perhaps you typed the URL in directly? Click here to go to the
- home page of the <a href="index.php"><?php echo "$bddb_label"; ?></a>.
- </b>
- </font>
-</center>
-<?php
- pg_foot();
-?>
+++ /dev/null
-BODY {
- background: #e0ffff;
- color: #000000;
- font-family: Arial, Verdana, Helvetica;
-}
-H1 {
- font-family: "Copperplate Gothic Bold";
- background: transparent;
- color: #993300;
- text-align: center;
-}
-H2, H3, H4, H5 {
- background: transparent;
- color: #993300;
- margin-top: 4%;
- text-align: center;
-}
-Body.Plain Div.Abstract, Body.Plain P.Abstract {
- background: #cccc99;
- color: #333300;
- border: white;
- padding: 3%;
- font-family: Times, Verdana;
-}
-TH.Nav {
- background: #0000cc;
- color: #ff9900;
-}
-TH.Menu {
- background: #3366cc;
- color: #ff9900;
-}
-A:hover {
- color: #ff6600;
-}
-A.Menu:hover {
- color: #ff6600;
-}
-A.HoMe:hover {
- color: #ff6600;
-}
-A.Menu {
- background: transparent;
- color: #ffcc33;
- font-family: Verdana, Helvetica, Arial;
- font-size: smaller;
- text-decoration: none;
-}
-A.Menu:visited {
- background: transparent;
- color: #ffcc99;
-}
-A.HoMe {
- background: transparent;
- color: #ffcc33;
- font-family: Verdana, Helvetica, Arial;
- text-decoration:none;
-}
-A.HoMe:visited {
- background: transparent;
- color: #ffcc99;
-}
-TH.Xmp {
- background: #eeeeee;
- color: #330066;
- font-family: courier;
- font-weight: normal;
-}
-TH.LuT {
- background: #cccccc;
- color: #000000;
-}
-TD.LuT {
- background: #ffffcc;
- color: #000000;
- font-size: 85%;
-}
-TH.Info, TD.Info {
- background: #ffffcc;
- color: #660000;
- font-family: "Comic Sans MS", Cursive, Verdana;
- font-size: smaller;
-}
-Div.Info, P.Info {
- background: #ffff99;
- color: #990033;
- text-align: left;
- padding: 2%;
- font-family: "Comic Sans MS", Cursive, Verdana;
- font-size: 85%;
- }
-Div.Info A {
- background: transparent;
- color: #ff6600;
-}
-.HL {
- background: #ffff99;
- color: #000000;
-}
-TD.HL {
- background: #ccffff;
- color: #000000;
-}
-Div.Margins {
- width: 512px;
- text-align: center;
-}
-TD.Plain {
- background: #ffffcc;
- color: #000033;
-}
-.Type {
- background: #cccccc;
- color: #660000;
-}
-.Name {
- background: #eeeeee;
- color: #660000;
- vertical-align: top;
- text-align: right;
-}
-.Value {
- background: #ffffee;
- color: #000066;
-}
-.Drop {
- background: #333366;
- color: #ffcc33;
- font-family: "Copperplate Gothic Light", Helvetica, Verdana, Arial;
-}
-A.Button:hover {
- color: #ff6600;
-}
-A.Button {
- text-decoration:none;
- color: #003366;
- background: #ffcc66;
-}
-.Button {
- font-size: 9pt;
- text-align: center;
- text-decoration:none;
- color: #003366;
- background: #ffcc66;
- margin-bottom: 2pt;
- border-top: 2px solid #ffff99;
- border-left: 2px solid #ffff99;
- border-right: 2px solid #cc9933;
- border-bottom: 2px solid #cc9933;
- font-family: Verdana, Arial, "Comic Sans MS";
-}
-.Banner {
- width: 468;
- font-size: 12pt;
- text-align: center;
- text-decoration:none;
- color: #003366;
- background: #ffcc66;
- border-top: 4px solid #ffff99;
- border-left: 4px solid #ffff99;
- border-right: 4px solid #cc9933;
- border-bottom: 4px solid #cc9933;
- font-family: Verdana, Arial, "Comic Sans MS";
-}
-TD.Nova, Body.Nova {
- background: #000000;
- font-family: "Times New Roman";
- font-weight: light;
- color: #ffcc00;
-}
-Body.Nova A.Button {
- background: gold;
- color: #003366;
-}
-Body.Nova A.Banner {
- background: transparent;
- color: #003366;
-}
-Body.Nova A {
- background: transparent;
- text-decoration:none;
- color: #ffd766;
-}
-Body.Nova H1, Body.Nova H2, Body.Nova H3, Body.Nova H4 {
- background: transparent;
- color: white;
- margin-top: 4%;
- text-align: center;
- filter: Blur(Add=1, Direction=0, Strength=8);
-}
-Body.Nova Div.Abstract {
- background: #000000;
- color: #ffffff;
- font-family: Times, Verdana;
-}
-Body.Nova A.Abstract {
- background: transparent;
- color: #ffeedd;
-}
-Body.Nova TH.LuT {
- background: black;
- color: #ffff99;
-}
-Body.Nova TD.LuT {
- background: navy;
- color: #ffff99;
-}
+++ /dev/null
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
- // (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@csiro.au>
- // CSIRO Manufacturing Science and Technology, Preston Lab
-
- // list page (hymod_bddb / boards)
-
- require("defs.php");
-
- pg_head("$bddb_label - Browse Board Log");
-
- $serno=intval($serno);
- if ($serno == 0)
- die("serial number not specified or invalid!");
-
- function print_cell($str) {
- if ($str == '')
- $str = ' ';
- echo "\t<td>$str</td>\n";
- }
-?>
-<table align=center border=1 cellpadding=10>
-<tr>
-<th>serno / edit</th>
-<th>ethaddr</th>
-<th>date</th>
-<th>batch</th>
-<th>type</th>
-<th>rev</th>
-<th>location</th>
-</tr>
-<?php
- $r=mysql_query("select * from boards where serno=$serno");
-
- while($row=mysql_fetch_array($r)){
- foreach ($columns as $key) {
- if (!key_in_array($key, $row))
- $row[$key] = '';
- }
-
- echo "<tr>\n";
- print_cell("<a href=\"edit.php?serno=$row[serno]\">$row[serno]</a>");
- print_cell($row['ethaddr']);
- print_cell($row['date']);
- print_cell($row['batch']);
- print_cell($row['type']);
- print_cell($row['rev']);
- print_cell($row['location']);
- echo "</tr>\n";
- }
-
- mysql_free_result($r);
-?>
-</table>
-<hr></hr>
-<p></p>
-<?php
- $limit=abs(isset($_REQUEST['limit'])?$_REQUEST['limit']:20);
- $offset=abs(isset($_REQUEST['offset'])?$_REQUEST['offset']:0);
- $lr=mysql_query("select count(*) as n from log where serno=$serno");
- $lrow=mysql_fetch_array($lr);
- if($lrow['n']>$limit){
- $preoffset=max(0,$offset-$limit);
- $postoffset=$offset+$limit;
- echo "<table width=\"100%\">\n<tr align=center>\n";
- printf("<td><%sa href=\"%s?submit=Log&serno=$serno&offset=%d\"><img border=0 alt=\"<\" src=\"/icons/left.gif\"></a></td>\n", $offset>0?"":"no", $PHP_SELF, $preoffset);
- printf("<td><%sa href=\"%s?submit=Log&serno=$serno&offset=%d\"><img border=0 alt=\">\" src=\"/icons/right.gif\"></a></td>\n", $postoffset<$lrow['n']?"":"no", $PHP_SELF, $postoffset);
- echo "</tr>\n</table>\n";
- }
- mysql_free_result($lr);
-?>
-<table width="100%" border=1 cellpadding=10>
-<tr valign=top>
-<th>logno / edit</th>
-<th>date</th>
-<th>who</th>
-<th width="70%">details</th>
-</tr>
-<?php
- $r=mysql_query("select * from log where serno=$serno order by logno limit $offset,$limit");
-
- while($row=mysql_fetch_array($r)){
- echo "<tr>\n";
- print_cell("<a href=\"edlog.php?serno=$row[serno]&logno=$row[logno]\">$row[logno]</a>");
- print_cell($row['date']);
- print_cell($row['who']);
- print_cell("<pre>" . urldecode($row['details']) . "</pre>");
- echo "</tr>\n";
- }
-
- mysql_free_result($r);
-?>
-</table>
-<hr></hr>
-<p></p>
-<table width="100%">
-<tr>
- <td align=center>
- <a href="newlog.php?serno=<?php echo "$serno"; ?>">Add to Log</a>
- </td>
- <td align=center>
- <a href="index.php">Back to Start</a>
- </td>
-</tr>
-</table>
-<?php
- pg_foot();
-?>
+++ /dev/null
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
- // (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@csiro.au>
- // CSIRO Manufacturing Science and Technology, Preston Lab
-
- // list page (hymod_bddb / boards)
-
- require("defs.php");
-
- $serno=isset($_REQUEST['serno'])?$_REQUEST['serno']:'';
-
- $verbose=isset($_REQUEST['verbose'])?intval($_REQUEST['verbose']):0;
-
- pg_head("$bddb_label - Browse database" . ($verbose?" (verbose)":""));
-?>
-<p></p>
-<?php
- $limit=isset($_REQUEST['limit'])?abs(intval($_REQUEST['limit'])):20;
- $offset=isset($_REQUEST['offset'])?abs(intval($_REQUEST['offset'])):0;
-
- if ($serno == '') {
-
- $lr=mysql_query("select count(*) as n from boards");
- $lrow=mysql_fetch_array($lr);
-
- if($lrow['n']>$limit){
- $preoffset=max(0,$offset-$limit);
- $postoffset=$offset+$limit;
- echo "<table width=\"100%\">\n<tr>\n";
- printf("<td align=left><%sa href=\"%s?submit=Browse&offset=%d&verbose=%d\"><img border=0 alt=\"<\" src=\"/icons/left.gif\"></a></td>\n", $offset>0?"":"no", $PHP_SELF, $preoffset, $verbose);
- printf("<td align=right><%sa href=\"%s?submit=Browse&offset=%d&verbose=%d\"><img border=0 alt=\">\" src=\"/icons/right.gif\"></a></td>\n", $postoffset<$lrow['n']?"":"no", $PHP_SELF, $postoffset, $offset);
- echo "</tr>\n</table>\n";
- }
-
- mysql_free_result($lr);
- }
-?>
-<table align=center border=1 cellpadding=10>
-<tr>
-<th></th>
-<th>serno / edit</th>
-<th>ethaddr</th>
-<th>date</th>
-<th>batch</th>
-<th>type</th>
-<th>rev</th>
-<th>location</th>
-<?php
- if ($verbose) {
- echo "<th>comments</th>\n";
- echo "<th>sdram</th>\n";
- echo "<th>flash</th>\n";
- echo "<th>zbt</th>\n";
- echo "<th>xlxtyp</th>\n";
- echo "<th>xlxspd</th>\n";
- echo "<th>xlxtmp</th>\n";
- echo "<th>xlxgrd</th>\n";
- echo "<th>cputyp</th>\n";
- echo "<th>cpuspd</th>\n";
- echo "<th>cpmspd</th>\n";
- echo "<th>busspd</th>\n";
- echo "<th>hstype</th>\n";
- echo "<th>hschin</th>\n";
- echo "<th>hschout</th>\n";
- }
-?>
-</tr>
-<?php
- $query = "select * from boards";
- if ($serno != '') {
- $pre = " where ";
- foreach (preg_split("/[\s,]+/", $serno) as $s) {
- if (preg_match('/^[0-9]+$/',$s))
- $query .= $pre . "serno=" . $s;
- else if (preg_match('/^([0-9]+)-([0-9]+)$/',$s,$m)) {
- $m1 = intval($m[1]); $m2 = intval($m[2]);
- if ($m2 <= $m1)
- die("bad serial number range ($s)");
- $query .= $pre . "(serno>=$m[1] and serno<=$m[2])";
- }
- else
- die("illegal serial number ($s)");
- $pre = " or ";
- }
- }
- $query .= " order by serno";
- if ($serno == '')
- $query .= " limit $offset,$limit";
-
- $r = mysql_query($query);
-
- function print_cell($str) {
- if ($str == '')
- $str = ' ';
- echo "\t<td>$str</td>\n";
- }
-
- while($row=mysql_fetch_array($r)){
- foreach ($columns as $key) {
- if (!key_in_array($key, $row))
- $row[$key] = '';
- }
-
- echo "<tr>\n";
- print_cell("<a href=\"brlog.php?serno=$row[serno]\">Log</a>");
- print_cell("<a href=\"edit.php?serno=$row[serno]\">$row[serno]</a>");
- print_cell($row['ethaddr']);
- print_cell($row['date']);
- print_cell($row['batch']);
- print_cell($row['type']);
- print_cell($row['rev']);
- print_cell($row['location']);
- if ($verbose) {
- print_cell("<pre>\n" . urldecode($row['comments']) .
- "\n\t</pre>");
- print_cell(gather_enum_multi_print("sdram", 4, $row));
- print_cell(gather_enum_multi_print("flash", 4, $row));
- print_cell(gather_enum_multi_print("zbt", 16, $row));
- print_cell(gather_enum_multi_print("xlxtyp", 4, $row));
- print_cell(gather_enum_multi_print("xlxspd", 4, $row));
- print_cell(gather_enum_multi_print("xlxtmp", 4, $row));
- print_cell(gather_enum_multi_print("xlxgrd", 4, $row));
- print_cell($row['cputyp']);
- print_cell($row['cpuspd']);
- print_cell($row['cpmspd']);
- print_cell($row['busspd']);
- print_cell($row['hstype']);
- print_cell($row['hschin']);
- print_cell($row['hschout']);
- }
- echo "</tr>\n";
- }
-?>
-</table>
-<p></p>
-<table width="100%">
-<tr>
- <td align=center><?php
- printf("<a href=\"%s?submit=Browse&offset=%d&verbose=%d%s\">%s Listing</a>\n", $PHP_SELF, $offset, $verbose?0:1, $serno!=''?"&serno=$serno":'', $verbose?"Terse":"Verbose");
- ?></td>
- <td align=center><a href="index.php">Back to Start</a></td>
-</tr>
-</table>
-<?php
- pg_foot();
-?>
+++ /dev/null
-<?php
- // (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@csiro.au>
- // CSIRO Manufacturing Science and Technology, Preston Lab
-
- // mysql database access info
- $mysql_user="fred";
- $mysql_pw="apassword";
- $mysql_db="mydbname";
-
- // where to put the eeprom config files
- $bddb_cfgdir = '/tftpboot/bddb';
-
- // what this database is called
- $bddb_label = 'Hymod Board Database';
-?>
+++ /dev/null
-# phpMyAdmin MySQL-Dump
-# http://phpwizard.net/phpMyAdmin/
-#
-# Host: localhost Database : hymod_bddb
-
-# (C) Copyright 2001
-# Murray Jensen <Murray.Jensen@csiro.au>
-# CSIRO Manufacturing and Infrastructure Technology, Preston Lab
-
-# --------------------------------------------------------
-#
-# Table structure for table 'boards'
-#
-
-DROP TABLE IF EXISTS boards;
-CREATE TABLE boards (
- serno int(10) unsigned zerofill NOT NULL auto_increment,
- ethaddr char(17),
- date date NOT NULL,
- batch char(32),
- type enum('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY') NOT NULL,
- rev tinyint(3) unsigned zerofill NOT NULL,
- location char(64),
- comments text,
- sdram0 enum('32M','64M','128M','256M','512M','1G','2G','4G'),
- sdram1 enum('32M','64M','128M','256M','512M','1G','2G','4G'),
- sdram2 enum('32M','64M','128M','256M','512M','1G','2G','4G'),
- sdram3 enum('32M','64M','128M','256M','512M','1G','2G','4G'),
- flash0 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'),
- flash1 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'),
- flash2 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'),
- flash3 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'),
- zbt0 enum('512K','1M','2M','4M','8M','16M'),
- zbt1 enum('512K','1M','2M','4M','8M','16M'),
- zbt2 enum('512K','1M','2M','4M','8M','16M'),
- zbt3 enum('512K','1M','2M','4M','8M','16M'),
- zbt4 enum('512K','1M','2M','4M','8M','16M'),
- zbt5 enum('512K','1M','2M','4M','8M','16M'),
- zbt6 enum('512K','1M','2M','4M','8M','16M'),
- zbt7 enum('512K','1M','2M','4M','8M','16M'),
- zbt8 enum('512K','1M','2M','4M','8M','16M'),
- zbt9 enum('512K','1M','2M','4M','8M','16M'),
- zbta enum('512K','1M','2M','4M','8M','16M'),
- zbtb enum('512K','1M','2M','4M','8M','16M'),
- zbtc enum('512K','1M','2M','4M','8M','16M'),
- zbtd enum('512K','1M','2M','4M','8M','16M'),
- zbte enum('512K','1M','2M','4M','8M','16M'),
- zbtf enum('512K','1M','2M','4M','8M','16M'),
- xlxtyp0 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'),
- xlxtyp1 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'),
- xlxtyp2 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'),
- xlxtyp3 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'),
- xlxspd0 enum('6','7','8','4','5','9','10','11','12'),
- xlxspd1 enum('6','7','8','4','5','9','10','11','12'),
- xlxspd2 enum('6','7','8','4','5','9','10','11','12'),
- xlxspd3 enum('6','7','8','4','5','9','10','11','12'),
- xlxtmp0 enum('COM','IND'),
- xlxtmp1 enum('COM','IND'),
- xlxtmp2 enum('COM','IND'),
- xlxtmp3 enum('COM','IND'),
- xlxgrd0 enum('NORMAL','ENGSAMP'),
- xlxgrd1 enum('NORMAL','ENGSAMP'),
- xlxgrd2 enum('NORMAL','ENGSAMP'),
- xlxgrd3 enum('NORMAL','ENGSAMP'),
- cputyp enum('MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)','MPC8560'),
- cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'),
- cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'),
- busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'),
- hstype enum('AMCC-S2064A','Xilinx-Rockets'),
- hschin enum('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16'),
- hschout enum('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16'),
- PRIMARY KEY (serno),
- KEY serno (serno),
- UNIQUE serno_2 (serno)
-);
-
-#
-# Table structure for table 'log'
-#
-
-DROP TABLE IF EXISTS log;
-CREATE TABLE log (
- logno int(10) unsigned zerofill NOT NULL auto_increment,
- serno int(10) unsigned zerofill NOT NULL,
- date date NOT NULL,
- details text NOT NULL,
- PRIMARY KEY (logno),
- KEY logno (logno, serno, date),
- UNIQUE logno_2 (logno)
-);
+++ /dev/null
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
- // (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@csiro.au>
- // CSIRO Manufacturing Science and Technology, Preston Lab
-
- // contains mysql user id and password - keep secret
- require("config.php");
-
- if (isset($_REQUEST['logout'])) {
- Header("status: 401 Unauthorized");
- Header("HTTP/1.0 401 Unauthorized");
- Header("WWW-authenticate: basic realm=\"$bddb_label\"");
-
- echo "<html><head><title>" .
- "Access to '$bddb_label' Denied" .
- "</title></head>\n";
- echo "<body bgcolor=#ffffff><br></br><br></br><center><h1>" .
- "You must be an Authorised User " .
- "to access the '$bddb_label'" .
- "</h1>\n</center></body></html>\n";
- exit;
- }
-
- // contents of the various enumerated types - if first item is
- // empty ('') then the enum is allowed to be null (ie "not null"
- // is not set on the column)
-
- // all column names in the database table
- $columns = array(
- 'serno','ethaddr','date','batch',
- 'type','rev','location','comments',
- 'sdram0','sdram1','sdram2','sdram3',
- 'flash0','flash1','flash2','flash3',
- 'zbt0','zbt1','zbt2','zbt3','zbt4','zbt5','zbt6','zbt7',
- 'zbt8','zbt9','zbta','zbtb','zbtc','zbtd','zbte','zbtf',
- 'xlxtyp0','xlxtyp1','xlxtyp2','xlxtyp3',
- 'xlxspd0','xlxspd1','xlxspd2','xlxspd3',
- 'xlxtmp0','xlxtmp1','xlxtmp2','xlxtmp3',
- 'xlxgrd0','xlxgrd1','xlxgrd2','xlxgrd3',
- 'cputyp','cpuspd','cpmspd','busspd',
- 'hstype','hschin','hschout'
- );
-
- // board type
- $type_vals = array('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY');
-
- // Xilinx fpga types
- $xlxtyp_vals = array('','XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140');
-
- // Xilinx fpga speeds
- $xlxspd_vals = array('','6','7','8','4','5','9','10','11','12');
-
- // Xilinx fpga temperatures (commercial or industrial)
- $xlxtmp_vals = array('','COM','IND');
-
- // Xilinx fpga grades (normal or engineering sample)
- $xlxgrd_vals = array('','NORMAL','ENGSAMP');
-
- // CPU types
- $cputyp_vals = array('','MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)','MPC8560');
-
- // CPU/BUS/CPM clock speeds
- $clk_vals = array('','33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ');
-
- // sdram sizes (nbits array is for eeprom config file)
- $sdram_vals = array('','32M','64M','128M','256M','512M','1G','2G','4G');
- $sdram_nbits = array(0,25,26,27,28,29,30,31,32);
-
- // flash sizes (nbits array is for eeprom config file)
- $flash_vals = array('','4M','8M','16M','32M','64M','128M','256M','512M','1G');
- $flash_nbits = array(0,22,23,24,25,26,27,28,29,30);
-
- // zbt ram sizes (nbits array is for write into eeprom config file)
- $zbt_vals = array('','512K','1M','2M','4M','8M','16M');
- $zbt_nbits = array(0,19,20,21,22,23,24);
-
- // high-speed serial attributes
- $hstype_vals = array('','AMCC-S2064A','Xilinx-Rockets');
- $hschin_vals = array('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16');
- $hschout_vals = array('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16');
-
- // value filters - used when outputting html
- function rev_filter($num) {
- if ($num == 0)
- return "001";
- else
- return sprintf("%03d", $num);
- }
-
- function text_filter($str) {
- return urldecode($str);
- }
-
- mt_srand(time() | getmypid());
-
- // set up MySQL connection
- mysql_connect("", $mysql_user, $mysql_pw) || die("cannot connect");
- mysql_select_db($mysql_db) || die("cannot select db");
-
- // page header
- function pg_head($title)
- {
- echo "<html>\n<head>\n";
- echo "<link rel=stylesheet href=\"bddb.css\" type=\"text/css\" title=\"style sheet\"></link>\n";
- echo "<title>$title</title>\n";
- echo "</head>\n";
- echo "<body>\n";
- echo "<center><h1>$title</h1></center>\n";
- echo "<hr></hr>\n";
- }
-
- // page footer
- function pg_foot()
- {
- echo "<hr></hr>\n";
- echo "<table width=\"100%\"><tr><td align=left>\n<address>" .
- "If you have any problems, email " .
- "<a href=\"mailto:Murray.Jensen@csiro.au\">" .
- "Murray Jensen" .
- "</a></address>\n" .
- "</td><td align=right>\n" .
- "<a href=\"index.php?logout=true\">logout</a>\n" .
- "</td></tr></table>\n";
- echo "<p><small><i>Made with " .
- "<a href=\"http://kyber.dk/phpMyBuilder/\">" .
- "Kyber phpMyBuilder</a></i></small></p>\n";
- echo "</body>\n";
- echo "</html>\n";
- }
-
- // some support functions
-
- if (!function_exists('array_search')) {
-
- function array_search($needle, $haystack, $strict = false) {
-
- if (is_array($haystack) && count($haystack)) {
-
- $ntype = gettype($needle);
-
- foreach ($haystack as $key => $value) {
-
- if ($value == $needle && (!$strict ||
- gettype($value) == $ntype))
- return $key;
- }
- }
-
- return false;
- }
- }
-
- if (!function_exists('in_array')) {
-
- function in_array($needle, $haystack, $strict = false) {
-
- if (is_array($haystack) && count($haystack)) {
-
- $ntype = gettype($needle);
-
- foreach ($haystack as $key => $value) {
-
- if ($value == $needle && (!$strict ||
- gettype($value) == $ntype))
- return true;
- }
- }
-
- return false;
- }
- }
-
- function key_in_array($key, $array) {
- return in_array($key, array_keys($array), true);
- }
-
- function enum_to_index($name, $vals) {
- $index = array_search($GLOBALS[$name], $vals);
- if ($vals[0] != '')
- $index++;
- return $index;
- }
-
- // fetch a value from an array - return empty string is not present
- function get_key_value($key, $array) {
- if (key_in_array($key, $array))
- return $array[$key];
- else
- return '';
- }
-
- function fprintf() {
- $n = func_num_args();
- if ($n < 2)
- return FALSE;
- $a = func_get_args();
- $fp = array_shift($a);
- $x = "\$s = sprintf";
- $sep = '(';
- foreach ($a as $z) {
- $x .= "$sep'$z'";
- $sep = ',';
- }
- $x .= ');';
- eval($x);
- $l = strlen($s);
- $r = fwrite($fp, $s, $l);
- if ($r != $l)
- return FALSE;
- else
- return TRUE;
- }
-
- // functions to display (print) a database table and its columns
-
- function begin_table($ncols) {
- global $table_ncols;
- $table_ncols = $ncols;
- echo "<table align=center width=\"100%\""
- . " border=1 cellpadding=4 cols=$table_ncols>\n";
- }
-
- function begin_field($name, $span = 0) {
- global $table_ncols;
- echo "<tr valign=top>\n";
- echo "\t<th align=center>$name</th>\n";
- if ($span <= 0)
- $span = $table_ncols - 1;
- if ($span > 1)
- echo "\t<td colspan=$span>\n";
- else
- echo "\t<td>\n";
- }
-
- function cont_field($span = 1) {
- echo "\t</td>\n";
- if ($span > 1)
- echo "\t<td colspan=$span>\n";
- else
- echo "\t<td>\n";
- }
-
- function end_field() {
- echo "\t</td>\n";
- echo "</tr>\n";
- }
-
- function end_table() {
- echo "</table>\n";
- }
-
- function print_field($name, $array, $size = 0, $filt='') {
-
- begin_field($name);
-
- if (key_in_array($name, $array))
- $value = $array[$name];
- else
- $value = '';
-
- if ($filt != '')
- $value = $filt($value);
-
- echo "\t\t<input name=$name value=\"$value\"";
- if ($size > 0)
- echo " size=$size maxlength=$size";
- echo "></input>\n";
-
- end_field();
- }
-
- function print_field_multiline($name, $array, $cols, $rows, $filt='') {
-
- begin_field($name);
-
- if (key_in_array($name, $array))
- $value = $array[$name];
- else
- $value = '';
-
- if ($filt != '')
- $value = $filt($value);
-
- echo "\t\t<textarea name=$name " .
- "cols=$cols rows=$rows wrap=off>\n";
- echo "$value";
- echo "</textarea>\n";
-
- end_field();
- }
-
- // print a mysql ENUM as an html RADIO INPUT
- function print_enum($name, $array, $vals, $def = -1) {
-
- begin_field($name);
-
- if (key_in_array($name, $array))
- $chk = array_search($array[$name], $vals, FALSE);
- else
- $chk = $def;
-
- $nval = count($vals);
-
- for ($i = 0; $i < $nval; $i++) {
-
- $val = $vals[$i];
- if ($val == '')
- $pval = "none";
- else
- $pval = "$val";
-
- printf("\t\t<input type=radio name=$name"
- . " value=\"$val\"%s>$pval</input>\n",
- $i == $chk ? " checked" : "");
- }
-
- end_field();
- }
-
- // print a mysql ENUM as an html SELECT INPUT
- function print_enum_select($name, $array, $vals, $def = -1) {
-
- begin_field($name);
-
- echo "\t\t<select name=$name>\n";
-
- if (key_in_array($name, $array))
- $chk = array_search($array[$name], $vals, FALSE);
- else
- $chk = $def;
-
- $nval = count($vals);
-
- for ($i = 0; $i < $nval; $i++) {
-
- $val = $vals[$i];
- if ($val == '')
- $pval = "none";
- else
- $pval = "$val";
-
- printf("\t\t\t<option " .
- "value=\"%s\"%s>%s</option>\n",
- $val, $i == $chk ? " selected" : "", $pval);
- }
-
- echo "\t\t</select>\n";
-
- end_field();
- }
-
- // print a group of mysql ENUMs (e.g. name0,name1,...) as an html SELECT
- function print_enum_multi($base, $array, $vals, $cnt, $defs, $grp = 0) {
-
- global $table_ncols;
-
- if ($grp <= 0)
- $grp = $cnt;
- $ncell = $cnt / $grp;
- $span = ($table_ncols - 1) / $ncell;
-
- begin_field($base, $span);
-
- $nval = count($vals);
-
- for ($i = 0; $i < $cnt; $i++) {
-
- if ($i > 0 && ($i % $grp) == 0)
- cont_field($span);
-
- $name = sprintf("%s%x", $base, $i);
-
- echo "\t\t<select name=$name>\n";
-
- if (key_in_array($name, $array))
- $ai = array_search($array[$name], $vals, FALSE);
- else {
- if (key_in_array($i, $defs))
- $ai = $defs[$i];
- else
- $ai = 0;
- }
-
- for ($j = 0; $j < $nval; $j++) {
-
- $val = $vals[$j];
- if ($val == '')
- $pval = " ";
- else
- $pval = "$val";
-
- printf("\t\t\t<option " .
- "value=\"%s\"%s>%s</option>\n",
- $val,
- $j == $ai ? " selected" : "",
- $pval);
- }
-
- echo "\t\t</select>\n";
- }
-
- end_field();
- }
-
- // functions to handle the form input
-
- // fetch all the parts of an "enum_multi" into a string suitable
- // for a MySQL query
- function gather_enum_multi_query($base, $cnt) {
-
- $retval = '';
-
- for ($i = 0; $i < $cnt; $i++) {
-
- $name = sprintf("%s%x", $base, $i);
-
- if (isset($_REQUEST[$name])) {
- $retval .= sprintf(", %s='%s'",
- $name, $_REQUEST[$name]);
- }
- }
-
- return $retval;
- }
-
- // fetch all the parts of an "enum_multi" into a string suitable
- // for a display e.g. in an html table cell
- function gather_enum_multi_print($base, $cnt, $array) {
-
- $retval = '';
-
- for ($i = 0; $i < $cnt; $i++) {
-
- $name = sprintf("%s%x", $base, $i);
-
- if ($array[$name] != '') {
- if ($retval != '')
- $retval .= ',';
- $retval .= $array[$name];
- }
- }
-
- return $retval;
- }
-
- // fetch all the parts of an "enum_multi" into a string suitable
- // for writing to the eeprom data file
- function gather_enum_multi_write($base, $cnt, $vals, $xfrm = array()) {
-
- $retval = '';
-
- for ($i = 0; $i < $cnt; $i++) {
-
- $name = sprintf("%s%x", $base, $i);
-
- if ($GLOBALS[$name] != '') {
- if ($retval != '')
- $retval .= ',';
- $index = enum_to_index($name, $vals);
- if ($xfrm != array())
- $retval .= $xfrm[$index];
- else
- $retval .= $index;
- }
- }
-
- return $retval;
- }
-
- // count how many parts of an "enum_multi" are actually set
- function count_enum_multi($base, $cnt) {
-
- $retval = 0;
-
- for ($i = 0; $i < $cnt; $i++) {
-
- $name = sprintf("%s%x", $base, $i);
-
- if (isset($_REQUEST[$name]))
- $retval++;
- }
-
- return $retval;
- }
-
- // ethernet address functions
-
- // generate a (possibly not unique) random vendor ethernet address
- // (setting bit 6 in the ethernet address - motorola wise i.e. bit 0
- // is the most significant bit - means it is not an assigned ethernet
- // address - it is a "locally administered" address). Also, make sure
- // it is NOT a multicast ethernet address (by setting bit 7 to 0).
- // e.g. the first byte of all ethernet addresses generated here will
- // have 2 in the bottom two bits (incidentally, these are the first
- // two bits transmitted on the wire, since the octets in ethernet
- // addresses are transmitted LSB first).
-
- function gen_eth_addr($serno) {
-
- $ethaddr_hgh = (mt_rand(0, 65535) & 0xfeff) | 0x0200;
- $ethaddr_mid = mt_rand(0, 65535);
- $ethaddr_low = mt_rand(0, 65535);
-
- return sprintf("%02lx:%02lx:%02lx:%02lx:%02lx:%02lx",
- $ethaddr_hgh >> 8, $ethaddr_hgh & 0xff,
- $ethaddr_mid >> 8, $ethaddr_mid & 0xff,
- $ethaddr_low >> 8, $ethaddr_low & 0xff);
- }
-
- // check that an ethernet address is valid
- function eth_addr_is_valid($ethaddr) {
-
- $ethbytes = split(':', $ethaddr);
-
- if (count($ethbytes) != 6)
- return FALSE;
-
- for ($i = 0; $i < 6; $i++) {
- $ethbyte = $ethbytes[$i];
- if (!ereg('^[0-9a-f][0-9a-f]$', $ethbyte))
- return FALSE;
- }
-
- return TRUE;
- }
-
- // write a simple eeprom configuration file
- function write_eeprom_cfg_file() {
-
- global $sernos, $nsernos, $bddb_cfgdir, $numerrs, $cfgerrs;
- global $date, $batch, $type_vals, $rev;
- global $sdram_vals, $sdram_nbits;
- global $flash_vals, $flash_nbits;
- global $zbt_vals, $zbt_nbits;
- global $xlxtyp_vals, $xlxspd_vals, $xlxtmp_vals, $xlxgrd_vals;
- global $cputyp, $cputyp_vals, $clk_vals;
- global $hstype, $hstype_vals, $hschin, $hschout;
-
- $numerrs = 0;
- $cfgerrs = array();
-
- for ($i = 0; $i < $nsernos; $i++) {
-
- $serno = sprintf("%010d", $sernos[$i]);
-
- $wfp = @fopen($bddb_cfgdir . "/$serno.cfg", "w");
- if (!$wfp) {
- $cfgerrs[$i] = 'file create fail';
- $numerrs++;
- continue;
- }
- set_file_buffer($wfp, 0);
-
- if (!fprintf($wfp, "serno=%d\n", $sernos[$i])) {
- $cfgerrs[$i] = 'cfg wr fail (serno)';
- fclose($wfp);
- $numerrs++;
- continue;
- }
-
- if (!fprintf($wfp, "date=%s\n", $date)) {
- $cfgerrs[$i] = 'cfg wr fail (date)';
- fclose($wfp);
- $numerrs++;
- continue;
- }
-
- if ($batch != '') {
- if (!fprintf($wfp, "batch=%s\n", $batch)) {
- $cfgerrs[$i] = 'cfg wr fail (batch)';
- fclose($wfp);
- $numerrs++;
- continue;
- }
- }
-
- $typei = enum_to_index("type", $type_vals);
- if (!fprintf($wfp, "type=%d\n", $typei)) {
- $cfgerrs[$i] = 'cfg wr fail (type)';
- fclose($wfp);
- $numerrs++;
- continue;
- }
-
- if (!fprintf($wfp, "rev=%d\n", $rev)) {
- $cfgerrs[$i] = 'cfg wr fail (rev)';
- fclose($wfp);
- $numerrs++;
- continue;
- }
-
- $s = gather_enum_multi_write("sdram", 4,
- $sdram_vals, $sdram_nbits);
- if ($s != '') {
- $b = fprintf($wfp, "sdram=%s\n", $s);
- if (!$b) {
- $cfgerrs[$i] = 'cfg wr fail (sdram)';
- fclose($wfp);
- $numerrs++;
- continue;
- }
- }
-
- $s = gather_enum_multi_write("flash", 4,
- $flash_vals, $flash_nbits);
- if ($s != '') {
- $b = fprintf($wfp, "flash=%s\n", $s);
- if (!$b) {
- $cfgerrs[$i] = 'cfg wr fail (flash)';
- fclose($wfp);
- $numerrs++;
- continue;
- }
- }
-
- $s = gather_enum_multi_write("zbt", 16,
- $zbt_vals, $zbt_nbits);
- if ($s != '') {
- $b = fprintf($wfp, "zbt=%s\n", $s);
- if (!$b) {
- $cfgerrs[$i] = 'cfg wr fail (zbt)';
- fclose($wfp);
- $numerrs++;
- continue;
- }
- }
-
- $s = gather_enum_multi_write("xlxtyp", 4, $xlxtyp_vals);
- if ($s != '') {
- $b = fprintf($wfp, "xlxtyp=%s\n", $s);
- if (!$b) {
- $cfgerrs[$i] = 'cfg wr fail (xlxtyp)';
- fclose($wfp);
- $numerrs++;
- continue;
- }
- }
-
- $s = gather_enum_multi_write("xlxspd", 4, $xlxspd_vals);
- if ($s != '') {
- $b = fprintf($wfp, "xlxspd=%s\n", $s);
- if (!$b) {
- $cfgerrs[$i] = 'cfg wr fail (xlxspd)';
- fclose($wfp);
- $numerrs++;
- continue;
- }
- }
-
- $s = gather_enum_multi_write("xlxtmp", 4, $xlxtmp_vals);
- if ($s != '') {
- $b = fprintf($wfp, "xlxtmp=%s\n", $s);
- if (!$b) {
- $cfgerrs[$i] = 'cfg wr fail (xlxtmp)';
- fclose($wfp);
- $numerrs++;
- continue;
- }
- }
-
- $s = gather_enum_multi_write("xlxgrd", 4, $xlxgrd_vals);
- if ($s != '') {
- $b = fprintf($wfp, "xlxgrd=%s\n", $s);
- if (!$b) {
- $cfgerrs[$i] = 'cfg wr fail (xlxgrd)';
- fclose($wfp);
- $numerrs++;
- continue;
- }
- }
-
- if ($cputyp != '') {
- $cputypi = enum_to_index("cputyp",$cputyp_vals);
- $cpuspdi = enum_to_index("cpuspd", $clk_vals);
- $busspdi = enum_to_index("busspd", $clk_vals);
- $cpmspdi = enum_to_index("cpmspd", $clk_vals);
- $b = fprintf($wfp, "cputyp=%d\ncpuspd=%d\n" .
- "busspd=%d\ncpmspd=%d\n",
- $cputypi, $cpuspdi, $busspdi, $cpmspdi);
- if (!$b) {
- $cfgerrs[$i] = 'cfg wr fail (cputyp)';
- fclose($wfp);
- $numerrs++;
- continue;
- }
- }
-
- if ($hstype != '') {
- $hstypei = enum_to_index("hstype",$hstype_vals);
- $b = fprintf($wfp, "hstype=%d\n" .
- "hschin=%s\nhschout=%s\n",
- $hstypei, $hschin, $hschout);
- if (!$b) {
- $cfgerrs[$i] = 'cfg wr fail (hstype)';
- fclose($wfp);
- $numerrs++;
- continue;
- }
- }
-
- if (!fclose($wfp)) {
- $cfgerrs[$i] = 'file cls fail';
- $numerrs++;
- }
- }
-
- return $numerrs;
- }
-?>
+++ /dev/null
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
- // (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@csiro.au>
- // CSIRO Manufacturing Science and Technology, Preston Lab
-
- // dodelete page (hymod_bddb / boards)
-
- require("defs.php");
-
- pg_head("$bddb_label - Delete Board Results");
-
- if (!isset($_REQUEST['serno']))
- die("the board serial number was not specified");
- $serno=intval($_REQUEST['serno']);
-
- mysql_query("delete from boards where serno=$serno");
-
- if(mysql_errno()) {
- $errstr = mysql_error();
- echo "\t<font size=+4>\n";
- echo "\t\t<p>\n";
- echo "\t\t\tThe following error was encountered:\n";
- echo "\t\t</p>\n";
- echo "\t\t<center>\n";
- printf("\t\t\t<b>%s</b>\n", $errstr);
- echo "\t\t</center>\n";
- echo "\t</font>\n";
- }
- else {
- echo "\t<font size=+2>\n";
- echo "\t\t<p>\n";
- echo "\t\t\tThe board with serial number <b>$serno</b> was"
- . " successfully deleted\n";
- mysql_query("delete from log where serno=$serno");
- if (mysql_errno()) {
- $errstr = mysql_error();
- echo "\t\t\t<font size=+4>\n";
- echo "\t\t\t\t<p>\n";
- echo "\t\t\t\t\tBut the following error occurred " .
- "when deleting the log entries:\n";
- echo "\t\t\t\t</p>\n";
- echo "\t\t\t\t<center>\n";
- printf("\t\t\t\t\t<b>%s</b>\n", $errstr);
- echo "\t\t\t\t</center>\n";
- echo "\t\t\t</font>\n";
- }
- echo "\t\t</p>\n";
- echo "\t</font>\n";
- }
-?>
-<p>
-<table width="100%">
-<tr>
- <td align=center>
- <a href="browse.php">Back to Browse</a>
- </td>
- <td align=center>
- <a href="index.php">Back to Start</a>
- </td>
-</tr>
-</table>
-<?php
- pg_foot();
-?>
+++ /dev/null
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
- // (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@csiro.au>
- // CSIRO Manufacturing Science and Technology, Preston Lab
-
- // dodelete page (hymod_bddb / boards)
-
- require("defs.php");
-
- pg_head("$bddb_label - Delete Log Entry Results");
-
- if (!isset($_REQUEST['serno']))
- die("the board serial number was not specified");
- $serno=intval($_REQUEST['serno']);
-
- if (!isset($_REQUEST['logno']) || $_REQUEST['logno'] == 0)
- die("the log entry number not specified!");
- $logno=$_REQUEST['logno'];
-
- mysql_query("delete from log where serno=$serno and logno=$logno");
-
- if(mysql_errno()) {
- $errstr = mysql_error();
- echo "\t<font size=+4>\n";
- echo "\t\t<p>\n";
- echo "\t\t\tThe following error was encountered:\n";
- echo "\t\t</p>\n";
- echo "\t\t<center>\n";
- printf("\t\t\t<b>%s</b>\n", $errstr);
- echo "\t\t</center>\n";
- echo "\t</font>\n";
- }
- else {
- echo "\t<font size=+2>\n";
- echo "\t\t<p>\n";
- echo "\t\t\tThe log entry with log number <b>$logno</b>\n";
- echo "\t\t\tand serial number <b>$serno</b> ";
- echo "was successfully deleted\n";
- echo "\t\t</p>\n";
- echo "\t</font>\n";
- }
-?>
-<p>
-<table width="100%">
-<tr>
- <td align=center>
- <a href="brlog.php?serno=<?php echo "$serno"; ?>">Back to Log</a>
- </td>
- <td align=center>
- <a href="index.php">Back to Start</a>
- </td>
-</tr>
-</table>
-<?php
- pg_foot();
-?>
+++ /dev/null
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
- // (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@csiro.au>
- // CSIRO Manufacturing Science and Technology, Preston Lab
-
- // doedit page (hymod_bddb / boards)
-
- require("defs.php");
-
- pg_head("$bddb_label - Edit Board Results");
-
- if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '')
- die("the board serial number was not specified");
- $serno=intval($_REQUEST['serno']);
-
- $query="update boards set";
-
- if (isset($_REQUEST['ethaddr'])) {
- $ethaddr=$_REQUEST['ethaddr'];
- if (!eth_addr_is_valid($ethaddr))
- die("ethaddr is invalid ('$ethaddr')");
- $query.=" ethaddr='$ethaddr',";
- }
-
- if (isset($_REQUEST['date'])) {
- $date=$_REQUEST['date'];
- list($y, $m, $d) = split("-", $date);
- if (!checkdate($m, $d, $y) || $y < 1999)
- die("date is invalid (input '$date', " .
- "yyyy-mm-dd '$y-$m-$d')");
- $query.=" date='$date'";
- }
-
- if (isset($_REQUEST['batch'])) {
- $batch=$_REQUEST['batch'];
- if (strlen($batch) > 32)
- die("batch field too long (>32)");
- $query.=", batch='$batch'";
- }
-
- if (isset($_REQUEST['type'])) {
- $type=$_REQUEST['type'];
- if (!in_array($type, $type_vals))
- die("Invalid type ($type) specified");
- $query.=", type='$type'";
- }
-
- if (isset($_REQUEST['rev'])) {
- $rev=$_REQUEST['rev'];
- if (($rev = intval($rev)) <= 0 || $rev > 255)
- die("Revision number is invalid ($rev)");
- $query.=sprintf(", rev=%d", $rev);
- }
-
- if (isset($_REQUEST['location'])) {
- $location=$_REQUEST['location'];
- if (strlen($location) > 64)
- die("location field too long (>64)");
- $query.=", location='$location'";
- }
-
- if (isset($_REQUEST['comments']))
- $comments=$_REQUEST['comments'];
- $query.=", comments='" . rawurlencode($comments) . "'";
-
- $query.=gather_enum_multi_query("sdram", 4);
-
- $query.=gather_enum_multi_query("flash", 4);
-
- $query.=gather_enum_multi_query("zbt", 16);
-
- $query.=gather_enum_multi_query("xlxtyp", 4);
- $nxlx = count_enum_multi("xlxtyp", 4);
-
- $query.=gather_enum_multi_query("xlxspd", 4);
- if (count_enum_multi("xlxspd", 4) != $nxlx)
- die("number of xilinx speeds not same as number of types");
-
- $query.=gather_enum_multi_query("xlxtmp", 4);
- if (count_enum_multi("xlxtmp", 4) != $nxlx)
- die("number of xilinx temps. not same as number of types");
-
- $query.=gather_enum_multi_query("xlxgrd", 4);
- if (count_enum_multi("xlxgrd", 4) != $nxlx)
- die("number of xilinx grades not same as number of types");
-
- if (isset($_REQUEST['cputyp'])) {
- $cputyp=$_REQUEST['cputyp'];
- $query.=", cputyp='$cputyp'";
- if (!isset($_REQUEST['cpuspd']) || $_REQUEST['cpuspd'] == '')
- die("must specify cpu speed if cpu type is defined");
- $cpuspd=$_REQUEST['cpuspd'];
- $query.=", cpuspd='$cpuspd'";
- if (!isset($_REQUEST['cpmspd']) || $_REQUEST['cpmspd'] == '')
- die("must specify cpm speed if cpu type is defined");
- $cpmspd=$_REQUEST['cpmspd'];
- $query.=", cpmspd='$cpmspd'";
- if (!isset($_REQUEST['busspd']) || $_REQUEST['busspd'] == '')
- die("must specify bus speed if cpu type is defined");
- $busspd=$_REQUEST['busspd'];
- $query.=", busspd='$busspd'";
- }
- else {
- if (isset($_REQUEST['cpuspd']))
- die("can't specify cpu speed if there is no cpu");
- if (isset($_REQUEST['cpmspd']))
- die("can't specify cpm speed if there is no cpu");
- if (isset($_REQUEST['busspd']))
- die("can't specify bus speed if there is no cpu");
- }
-
- if (isset($_REQUEST['hschin'])) {
- $hschin=$_REQUEST['hschin'];
- if (($hschin = intval($hschin)) < 0 || $hschin > 4)
- die("Invalid number of hs input chans ($hschin)");
- }
- else
- $hschin = 0;
- if (isset($_REQUEST['hschout'])) {
- $hschout=$_REQUEST['hschout'];
- if (($hschout = intval($hschout)) < 0 || $hschout > 4)
- die("Invalid number of hs output chans ($hschout)");
- }
- else
- $hschout = 0;
- if (isset($_REQUEST['hstype'])) {
- $hstype=$_REQUEST['hstype'];
- $query.=", hstype='$hstype'";
- }
- else {
- if ($_REQUEST['hschin'] != 0)
- die("number of high-speed input channels must be zero"
- . " if high-speed chip is not present");
- if ($_REQUEST['hschout'] != 0)
- die("number of high-speed output channels must be zero"
- . " if high-speed chip is not present");
- }
- $query.=", hschin='$hschin'";
- $query.=", hschout='$hschout'";
-
- $query.=" where serno=$serno";
-
- mysql_query($query);
- if(mysql_errno()) {
- $errstr = mysql_error();
- echo "\t<font size=+4>\n";
- echo "\t\t<p>\n";
- echo "\t\t\tThe following error was encountered:\n";
- echo "\t\t</p>\n";
- echo "\t\t<center>\n";
- printf("\t\t\t<b>%s</b>\n", $errstr);
- echo "\t\t</center>\n";
- echo "\t</font>\n";
- }
- else {
- $sernos = array($serno);
- $nsernos = 1;
-
- write_eeprom_cfg_file();
-
- echo "\t<font size=+2>\n";
- echo "\t\t<p>\n";
- echo "\t\t\tThe board with serial number <b>$serno</b> was"
- . " successfully updated";
- if ($numerrs > 0) {
- $errstr = $cfgerrs[0];
- echo "<br>\n\t\t\t";
- echo "(but the cfg file update failed: $errstr)";
- }
- echo "\n";
- echo "\t\t</p>\n";
- echo "\t</font>\n";
- }
-
-?>
-<p>
-<table align=center width="100%">
-<tr>
- <td align=center><a href="browse.php">Back to Browse</a></td>
- <td align=center><a href="index.php">Back to Start</a></td>
-</tr>
-</table>
-<?php
- pg_foot();
-?>
+++ /dev/null
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
- // (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@csiro.au>
- // CSIRO Manufacturing Science and Technology, Preston Lab
-
- // doedit page (hymod_bddb / boards)
-
- require("defs.php");
-
- pg_head("$bddb_label - Edit Log Entry Results");
-
- if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '')
- die("the board serial number was not specified");
- $serno=intval($_REQUEST['serno']);
-
- if (!isset($_REQUEST['logno']) || $_REQUEST['logno'] == '')
- die("log number not specified!");
- $logno=intval($_REQUEST['logno']);
-
- $query="update log set";
-
- if (isset($_REQUEST['date'])) {
- $date=$_REQUEST['date'];
- list($y, $m, $d) = split("-", $date);
- if (!checkdate($m, $d, $y) || $y < 1999)
- die("date is invalid (input '$date', " .
- "yyyy-mm-dd '$y-$m-$d')");
- $query.=" date='$date'";
- }
-
- if (isset($_REQUEST['who'])) {
- $who=$_REQUEST['who'];
- $query.=", who='" . $who . "'";
- }
-
- if (isset($_REQUEST['details'])) {
- $details=$_REQUEST['details'];
- $query.=", details='" . rawurlencode($details) . "'";
- }
-
- $query.=" where serno=$serno and logno=$logno";
-
- mysql_query($query);
- if(mysql_errno()) {
- $errstr = mysql_error();
- echo "\t<font size=+4>\n";
- echo "\t\t<p>\n";
- echo "\t\t\tThe following error was encountered:\n";
- echo "\t\t</p>\n";
- echo "\t\t<center>\n";
- printf("\t\t\t<b>%s</b>\n", $errstr);
- echo "\t\t</center>\n";
- echo "\t</font>\n";
- }
- else {
- echo "\t<font size=+2>\n";
- echo "\t\t<p>\n";
- echo "\t\t\tThe log entry with log number <b>$logno</b> and\n";
- echo "\t\t\tserial number <b>$serno</b> ";
- echo "was successfully updated\n";
- echo "\t\t</p>\n";
- echo "\t</font>\n";
- }
-
-?>
-<p>
-<table align=center width="100%">
-<tr>
- <td align=center><a href="brlog.php?serno=<?php echo "$serno"; ?>">Back to Log</a></td>
- <td align=center><a href="index.php">Back to Start</a></td>
-</tr>
-</table>
-<?php
- pg_foot();
-?>
+++ /dev/null
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
- // (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@csiro.au>
- // CSIRO Manufacturing Science and Technology, Preston Lab
-
- // doedit page (hymod_bddb / boards)
-
- require("defs.php");
-
- pg_head("$bddb_label - Board Registration Results");
-
- if (isset($_REQUEST['serno'])) {
- $serno=$_REQUEST['serno'];
- die("serial number must not be set ($serno) when Creating!");
- }
-
- $query="update boards set";
-
- list($y, $m, $d) = split("-", $date);
- if (!checkdate($m, $d, $y) || $y < 1999)
- die("date is invalid (input '$date', yyyy-mm-dd '$y-$m-$d')");
- $query.=" date='$date'";
-
- if ($batch != '') {
- if (strlen($batch) > 32)
- die("batch field too long (>32)");
- $query.=", batch='$batch'";
- }
-
- if (!in_array($type, $type_vals))
- die("Invalid type ($type) specified");
- $query.=", type='$type'";
-
- if (($rev = intval($rev)) <= 0 || $rev > 255)
- die("Revision number is invalid ($rev)");
- $query.=sprintf(", rev=%d", $rev);
-
- $query.=gather_enum_multi_query("sdram", 4);
-
- $query.=gather_enum_multi_query("flash", 4);
-
- $query.=gather_enum_multi_query("zbt", 16);
-
- $query.=gather_enum_multi_query("xlxtyp", 4);
- $nxlx = count_enum_multi("xlxtyp", 4);
-
- $query.=gather_enum_multi_query("xlxspd", 4);
- if (count_enum_multi("xlxspd", 4) != $nxlx)
- die("number of xilinx speeds not same as number of types");
-
- $query.=gather_enum_multi_query("xlxtmp", 4);
- if (count_enum_multi("xlxtmp", 4) != $nxlx)
- die("number of xilinx temps. not same as number of types");
-
- $query.=gather_enum_multi_query("xlxgrd", 4);
- if (count_enum_multi("xlxgrd", 4) != $nxlx)
- die("number of xilinx grades not same as number of types");
-
- if ($cputyp == '') {
- if ($cpuspd != '')
- die("can't specify cpu speed if there is no cpu");
- if ($cpmspd != '')
- die("can't specify cpm speed if there is no cpu");
- if ($busspd != '')
- die("can't specify bus speed if there is no cpu");
- }
- else {
- $query.=", cputyp='$cputyp'";
- if ($cpuspd == '')
- die("must specify cpu speed if cpu type is defined");
- $query.=", cpuspd='$cpuspd'";
- if ($cpmspd == '')
- die("must specify cpm speed if cpu type is defined");
- $query.=", cpmspd='$cpmspd'";
- if ($busspd == '')
- die("must specify bus speed if cpu type is defined");
- $query.=", busspd='$busspd'";
- }
-
- if (($hschin = intval($hschin)) < 0 || $hschin > 4)
- die("Invalid number of hs input chans ($hschin)");
- if (($hschout = intval($hschout)) < 0 || $hschout > 4)
- die("Invalid number of hs output chans ($hschout)");
- if ($hstype == '') {
- if ($hschin != 0)
- die("number of high-speed input channels must be zero"
- . " if high-speed chip is not present");
- if ($hschout != 0)
- die("number of high-speed output channels must be zero"
- . " if high-speed chip is not present");
- }
- else
- $query.=", hstype='$hstype'";
- $query.=", hschin='$hschin'";
- $query.=", hschout='$hschout'";
-
- // echo "final query = '$query'<br>\n";
-
- $quant = intval($quant);
- if ($quant <= 0) $quant = 1;
-
- $sernos = array();
- if ($geneths)
- $ethaddrs = array();
-
- $sqlerr = '';
-
- while ($quant-- > 0) {
-
- mysql_query("insert into boards (serno) values (null)");
- if (mysql_errno()) {
- $sqlerr = mysql_error();
- break;
- }
-
- $serno = mysql_insert_id();
- if (!$serno) {
- $sqlerr = "couldn't allocate new serial number";
- break;
- }
-
- mysql_query($query . " where serno=$serno");
- if (mysql_errno()) {
- $sqlerr = mysql_error();
- break;
- }
-
- array_push($sernos, $serno);
-
- if ($geneths) {
-
- $ethaddr = gen_eth_addr($serno);
-
- mysql_query("update boards set ethaddr='$ethaddr'" .
- " where serno=$serno");
- if (mysql_errno()) {
- $sqlerr = mysql_error();
-
- array_push($ethaddrs,
- "<font color=#ff0000><b>" .
- "db save fail" .
- "</b></font>");
- break;
- }
-
- array_push($ethaddrs, $ethaddr);
- }
- }
-
- $nsernos = count($sernos);
-
- if ($nsernos > 0) {
-
- write_eeprom_cfg_file();
-
- echo "<font size=+2>\n";
- echo "\t<p>\n";
- echo "\t\tThe following board serial numbers were"
- . " successfully allocated";
- if ($numerrs > 0)
- echo " (but with $numerrs cfg file error" .
- ($numerrs > 1 ? "s" : "") . ")";
- echo ":\n";
- echo "\t</p>\n";
-
- echo "</font>\n";
-
- echo "<table align=center width=\"100%\">\n";
- echo "<tr>\n";
- echo "\t<th>Serial Number</th>\n";
- if ($numerrs > 0)
- echo "\t<th>Cfg File Errs</th>\n";
- if ($geneths)
- echo "\t<th>Ethernet Address</th>\n";
- echo "</tr>\n";
-
- for ($i = 0; $i < $nsernos; $i++) {
-
- $serno = sprintf("%010d", $sernos[$i]);
-
- echo "<tr>\n";
-
- echo "\t<td align=center><font size=+2>" .
- "<b>$serno</b></font></td>\n";
-
- if ($numerrs > 0) {
- if (($errstr = $cfgerrs[$i]) == '')
- $errstr = ' ';
- echo "\t<td align=center>" .
- "<font size=+2 color=#ff0000><b>" .
- $errstr .
- "</b></font></td>\n";
- }
-
- if ($geneths) {
- echo "\t<td align=center>" .
- "<font size=+2 color=#00ff00><b>" .
- $ethaddrs[$i] .
- "</b></font></td>\n";
- }
-
- echo "</tr>\n";
- }
-
- echo "</table>\n";
- }
-
- if ($sqlerr != '') {
- echo "\t<font size=+4>\n";
- echo "\t\t<p>\n";
- echo "\t\t\tThe following SQL error was encountered:\n";
- echo "\t\t</p>\n";
- echo "\t\t<center>\n";
- printf("\t\t\t<b>%s</b>\n", $sqlerr);
- echo "\t\t</center>\n";
- echo "\t</font>\n";
- }
-
-?>
-<p>
-<table align=center width="100%">
-<tr>
- <td align=center><a href="browse.php">Go to Browse</a></td>
- <td align=center><a href="index.php">Back to Start</a></td>
-</tr>
-</table>
-<?php
- pg_foot();
-?>
+++ /dev/null
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
- // (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@csiro.au>
- // CSIRO Manufacturing Science and Technology, Preston Lab
-
- // doedit page (hymod_bddb / boards)
-
- require("defs.php");
-
- pg_head("$bddb_label - Add Log Entry Results");
-
- if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '')
- die("serial number not specified!");
- $serno=intval($_REQUEST['serno']);
-
- if (isset($_REQUEST['logno'])) {
- $logno=$_REQUEST['logno'];
- die("log number must not be set ($logno) when Creating!");
- }
-
- $query="update log set serno=$serno";
-
- list($y, $m, $d) = split("-", $date);
- if (!checkdate($m, $d, $y) || $y < 1999)
- die("date is invalid (input '$date', yyyy-mm-dd '$y-$m-$d')");
- $query.=", date='$date'";
-
- if (isset($_REQUEST['who'])) {
- $who=$_REQUEST['who'];
- $query.=", who='" . $who . "'";
- }
-
- if (isset($_REQUEST['details'])) {
- $details=$_REQUEST['details'];
- $query.=", details='" . rawurlencode($details) . "'";
- }
-
- // echo "final query = '$query'<br>\n";
-
- $sqlerr = '';
-
- mysql_query("insert into log (logno) values (null)");
- if (mysql_errno())
- $sqlerr = mysql_error();
- else {
- $logno = mysql_insert_id();
- if (!$logno)
- $sqlerr = "couldn't allocate new serial number";
- else {
- mysql_query($query . " where logno=$logno");
- if (mysql_errno())
- $sqlerr = mysql_error();
- }
- }
-
- if ($sqlerr == '') {
- echo "<font size=+2>\n";
- echo "\t<p>\n";
- echo "\t\tA log entry with log number '$logno' was " .
- "added to the board with serial number '$serno'\n";
- echo "\t</p>\n";
- echo "</font>\n";
- }
- else {
- echo "\t<font size=+4>\n";
- echo "\t\t<p>\n";
- echo "\t\t\tThe following SQL error was encountered:\n";
- echo "\t\t</p>\n";
- echo "\t\t<center>\n";
- printf("\t\t\t<b>%s</b>\n", $sqlerr);
- echo "\t\t</center>\n";
- echo "\t</font>\n";
- }
-
-?>
-<p></p>
-<table width="100%">
-<tr>
- <td align=center><a href="brlog.php?serno=<?php echo "$serno"; ?>">Go to Browse</a></td>
- <td align=center><a href="index.php">Back to Start</a></td>
-</tr>
-</table>
-<?php
- pg_foot();
-?>
+++ /dev/null
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
- // (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@csiro.au>
- // CSIRO Manufacturing Science and Technology, Preston Lab
-
- // edit page (hymod_bddb / boards)
-
- require("defs.php");
-
- pg_head("$bddb_label - Edit Board Registration");
-
- if ($serno == 0)
- die("serial number not specified or invalid!");
-
- $pserno = sprintf("%010d", $serno);
-
- echo "<center><b><font size=+2>";
- echo "Board Serial Number: $pserno";
- echo "</font></b></center>\n";
-
-?>
-<p>
-<form action=doedit.php method=POST>
-<?php
- echo "<input type=hidden name=serno value=$serno>\n";
-
- $r=mysql_query("select * from boards where serno=$serno");
- $row=mysql_fetch_array($r);
- if(!$row) die("no record of serial number '$serno' in database");
-
- begin_table(5);
-
- // ethaddr char(17)
- print_field("ethaddr", $row, 17);
-
- // date date
- print_field("date", $row);
-
- // batch char(32)
- print_field("batch", $row, 32);
-
- // type enum('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY')
- print_enum("type", $row, $type_vals);
-
- // rev tinyint(3) unsigned zerofill
- print_field("rev", $row, 3, 'rev_filter');
-
- // location char(64)
- print_field("location", $row, 64);
-
- // comments text
- print_field_multiline("comments", $row, 60, 10, 'text_filter');
-
- // sdram[0-3] enum('32M','64M','128M','256M')
- print_enum_multi("sdram", $row, $sdram_vals, 4, array());
-
- // flash[0-3] enum('4M','8M','16M','32M','64M')
- print_enum_multi("flash", $row, $flash_vals, 4, array());
-
- // zbt[0-f] enum('512K','1M','2M','4M')
- print_enum_multi("zbt", $row, $zbt_vals, 16, array());
-
- // xlxtyp[0-3] enum('XCV300E','XCV400E','XCV600E')
- print_enum_multi("xlxtyp", $row, $xlxtyp_vals, 4, array(), 1);
-
- // xlxspd[0-3] enum('6','7','8')
- print_enum_multi("xlxspd", $row, $xlxspd_vals, 4, array(), 1);
-
- // xlxtmp[0-3] enum('COM','IND')
- print_enum_multi("xlxtmp", $row, $xlxtmp_vals, 4, array(), 1);
-
- // xlxgrd[0-3] enum('NORMAL','ENGSAMP')
- print_enum_multi("xlxgrd", $row, $xlxgrd_vals, 4, array(), 1);
-
- // cputyp enum('MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)')
- print_enum("cputyp", $row, $cputyp_vals);
-
- // cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ')
- print_enum_select("cpuspd", $row, $clk_vals);
-
- // cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ')
- print_enum_select("cpmspd", $row, $clk_vals);
-
- // busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ')
- print_enum_select("busspd", $row, $clk_vals);
-
- // hstype enum('AMCC-S2064A')
- print_enum("hstype", $row, $hstype_vals);
-
- // hschin enum('0','1','2','3','4')
- print_enum("hschin", $row, $hschin_vals);
-
- // hschout enum('0','1','2','3','4')
- print_enum("hschout", $row, $hschout_vals);
-
- end_table();
-
- echo "<p>\n";
- echo "<center><b>";
- echo "<font color=#ff0000>WARNING: NO UNDO ON DELETE!</font>";
- echo "<br></br>\n";
- echo "<tt>[ <a href=\"dodelete.php?serno=$serno\">delete</a> ]</tt>";
- echo "</b></center>\n";
- echo "</p>\n";
-?>
-<p>
-<table align=center width="100%">
-<tr>
- <td align=center>
- <input type=submit value=Edit>
- </td>
- <td>
-
- </td>
- <td align=center>
- <input type=reset value=Reset>
- </td>
- <td>
-
- </td>
- <td align=center>
- <a href="index.php">Back to Start</a>
- </td>
-</tr>
-</table>
-</p>
-</form>
-<?php
- pg_foot();
-?>
+++ /dev/null
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
- // (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@csiro.au>
- // CSIRO Manufacturing Science and Technology, Preston Lab
-
- // edit page (hymod_bddb / boards)
-
- require("defs.php");
-
- pg_head("$bddb_label - Edit Board Log Entry");
-
- if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '')
- die("serial number not specified!");
- $serno=intval($_REQUEST['serno']);
-
- if (!isset($_REQUEST['logno']) || $_REQUEST['logno'] == '')
- die("log number not specified!");
- $logno=intval($_REQUEST['logno']);
-
- $pserno = sprintf("%010d", $serno);
- $plogno = sprintf("%010d", $logno);
-
- echo "<center><b><font size=+2>";
- echo "Board Serial Number: $pserno, Log Number: $plogno";
- echo "</font></b></center>\n";
-
-?>
-<p>
-<form action=doedlog.php method=POST>
-<?php
- echo "<input type=hidden name=serno value=$serno>\n";
- echo "<input type=hidden name=logno value=$logno>\n";
-
- $r=mysql_query("select * from log where serno=$serno and logno=$logno");
- $row=mysql_fetch_array($r);
- if(!$row)
- die("no record of log entry with serial number '$serno' " .
- "and log number '$logno' in database");
-
- begin_table(3);
-
- // date date
- print_field("date", $row);
-
- // who char(20)
- print_field("who", $row);
-
- // details text
- print_field_multiline("details", $row, 60, 10, 'text_filter');
-
- end_table();
-
- echo "<p>\n";
- echo "<center><b>";
- echo "<font color=#ff0000>WARNING: NO UNDO ON DELETE!</font>";
- echo "<br></br>\n";
- echo "<tt>[ <a href=\"dodellog.php?serno=$serno&logno=$logno\">delete</a> ]</tt>";
- echo "</b></center>\n";
- echo "</p>\n";
-?>
-<p>
-<table align=center width="100%">
-<tr>
- <td align=center>
- <input type=submit value=Edit>
- </td>
- <td>
-
- </td>
- <td align=center>
- <input type=reset value=Reset>
- </td>
- <td>
-
- </td>
- <td align=center>
- <a href="index.php">Back to Start</a>
- </td>
-</tr>
-</table>
-</p>
-</form>
-<?php
- pg_foot();
-?>
+++ /dev/null
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
- // (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@csiro.au>
- // CSIRO Manufacturing Science and Technology, Preston Lab
-
- $serno=isset($_REQUEST['serno'])?$_REQUEST['serno']:'';
-
- $submit=isset($_REQUEST['submit'])?$_REQUEST['submit']:"[NOT SET]";
-
- switch ($submit) {
-
- case "New":
- require("new.php");
- break;
-
- case "Edit":
- require("edit.php");
- break;
-
- case "Browse":
- require("browse.php");
- break;
-
- case "Log":
- require("brlog.php");
- break;
-
- default:
- require("badsubmit.php");
- break;
- }
-?>
+++ /dev/null
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
- // (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@csiro.au>
- // CSIRO Manufacturing Science and Technology, Preston Lab
-
- require("defs.php");
- pg_head("$bddb_label");
-?>
-<font size="+4">
- <form action=execute.php method=POST>
- <table width="100%" cellspacing=10 cellpadding=10>
- <tr>
- <td align=center>
- <input type=submit name=submit value="New"></input>
- </td>
- <td align=center>
- <input type=submit name=submit value="Edit"></input>
- </td>
- <td align=center>
- <input type=submit name=submit value="Browse"></input>
- </td>
- <td align=center>
- <input type=submit name=submit value="Log"></input>
- </td>
- </tr>
- <tr>
- <td align=center colspan=4>
- <b>Serial Number:</b>
- <input type=text name=serno size=10 maxsize=10 value=""></input>
- </td>
- </tr>
- </table>
- </form>
-</font>
-<?php
- pg_foot();
-?>
+++ /dev/null
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
- // (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@csiro.au>
- // CSIRO Manufacturing Science and Technology, Preston Lab
-
- // edit page (hymod_bddb / boards)
-
- require("defs.php");
-
- pg_head("$bddb_label - New Board Registration");
-?>
-<form action=donew.php method=POST>
-<p></p>
-<?php
- $serno=intval($serno);
- // if a serial number was supplied, fetch the record
- // and use its contents as defaults
- if ($serno != 0) {
- $r=mysql_query("select * from boards where serno=$serno");
- $row=mysql_fetch_array($r);
- if(!$row)die("no record of serial number '$serno' in database");
- }
- else
- $row = array();
-
- begin_table(5);
-
- // date date
- print_field("date", array('date' => date("Y-m-d")));
-
- // batch char(32)
- print_field("batch", $row, 32);
-
- // type enum('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY')
- print_enum("type", $row, $type_vals, 0);
-
- // rev tinyint(3) unsigned zerofill
- print_field("rev", $row, 3, 'rev_filter');
-
- // sdram[0-3] enum('32M','64M','128M','256M')
- print_enum_multi("sdram", $row, $sdram_vals, 4, array(2));
-
- // flash[0-3] enum('4M','8M','16M','32M','64M')
- print_enum_multi("flash", $row, $flash_vals, 4, array(2));
-
- // zbt[0-f] enum('512K','1M','2M','4M')
- print_enum_multi("zbt", $row, $zbt_vals, 16, array(2, 2));
-
- // xlxtyp[0-3] enum('XCV300E','XCV400E','XCV600E')
- print_enum_multi("xlxtyp", $row, $xlxtyp_vals, 4, array(1), 1);
-
- // xlxspd[0-3] enum('6','7','8')
- print_enum_multi("xlxspd", $row, $xlxspd_vals, 4, array(1), 1);
-
- // xlxtmp[0-3] enum('COM','IND')
- print_enum_multi("xlxtmp", $row, $xlxtmp_vals, 4, array(1), 1);
-
- // xlxgrd[0-3] enum('NORMAL','ENGSAMP')
- print_enum_multi("xlxgrd", $row, $xlxgrd_vals, 4, array(1), 1);
-
- // cputyp enum('MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)')
- print_enum("cputyp", $row, $cputyp_vals, 1);
-
- // cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ')
- print_enum_select("cpuspd", $row, $clk_vals, 4);
-
- // cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ')
- print_enum_select("cpmspd", $row, $clk_vals, 4);
-
- // busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ')
- print_enum_select("busspd", $row, $clk_vals, 2);
-
- // hstype enum('AMCC-S2064A')
- print_enum("hstype", $row, $hstype_vals, 1);
-
- // hschin enum('0','1','2','3','4')
- print_enum("hschin", $row, $hschin_vals, 4);
-
- // hschout enum('0','1','2','3','4')
- print_enum("hschout", $row, $hschout_vals, 4);
-
- end_table();
-?>
-<p></p>
-<table width="100%">
-<tr>
- <td align=center colspan=3>
- Allocate
- <input type=text name=quant size=2 maxlength=2 value=" 1">
- board serial number(s)
- </td>
-</tr>
-<tr>
- <td align=center colspan=3>
- <input type=checkbox name=geneths checked>
- Generate Ethernet Address(es)
- </td>
-</tr>
-<tr>
- <td colspan=3>
-
- </td>
-</tr>
-<tr>
- <td align=center>
- <input type=submit value="Register Board">
- </td>
- <td>
-
- </td>
- <td align=center>
- <input type=reset value="Reset Form Contents">
- </td>
-</tr>
-</table>
-</form>
-<?php
- pg_foot();
-?>
+++ /dev/null
-<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
-<?php
- // (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@csiro.au>
- // CSIRO Manufacturing Science and Technology, Preston Lab
-
- // edit page (hymod_bddb / boards)
-
- require("defs.php");
-
- pg_head("$bddb_label - New Log Entry");
-
- if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '')
- die("serial number not specified or invalid!");
- $serno=intval($_REQUEST['serno']);
-
- if (isset($_REQUEST['logno'])) {
- $logno=$_REQUEST['logno'];
- die("log number must not be specified when adding! ($logno)");
- }
-?>
-<form action=donewlog.php method=POST>
-<p></p>
-<?php
- echo "<input type=hidden name=serno value=$serno>\n";
-
- begin_table(3);
-
- // date date
- print_field("date", array('date' => date("Y-m-d")));
-
- // who char(20)
- print_field("who", array());
-
- // details text
- print_field_multiline("details", array(), 60, 10, 'text_filter');
-
- end_table();
-?>
-<p></p>
-<table width="100%">
-<tr>
- <td align=center>
- <input type=submit value="Add Log Entry">
- </td>
- <td align=center>
- <input type=reset value="Reset Form Contents">
- </td>
-</tr>
-</table>
-</form>
-<?php
- pg_foot();
-?>
#endif
static inline ulong getenvsize (void)
{
- ulong rc = CUR_ENVSIZE - sizeof(long);
+ ulong rc = CUR_ENVSIZE - sizeof(uint32_t);
if (HaveRedundEnv)
rc -= sizeof (char);
*
* The remaining fraction of a block bytes would not be loaded!
*/
- *header_size_ptr = ROUND(sbuf->st_size, 4096);
+ *header_size_ptr = ROUND((sbuf->st_size + imximage_ivt_offset), 4096);
if (csf_ptr && imximage_csf_size) {
*csf_ptr = params->ep - imximage_init_loadsize +
*/
#include "imagetool.h"
+#include <limits.h>
#include <image.h>
#include <stdint.h>
#include "kwbimage.h"
main_hdr = image;
/* Fill in the main header */
- main_hdr->blocksize = payloadsz + sizeof(uint32_t);
+ main_hdr->blocksize = payloadsz + sizeof(uint32_t) - headersz;
main_hdr->srcaddr = headersz;
main_hdr->ext = has_ext;
main_hdr->destaddr = params->addr;
ret = stat(binarye->binary.file, &s);
if (ret < 0) {
- char *cwd = get_current_dir_name();
+ char cwd[PATH_MAX];
+ char *dir = cwd;
+
+ memset(cwd, 0, sizeof(cwd));
+ if (!getcwd(cwd, sizeof(cwd))) {
+ dir = "current working directory";
+ perror("getcwd() failed");
+ }
+
fprintf(stderr,
"Didn't find the file '%s' in '%s' which is mandatory to generate the image\n"
"This file generally contains the DDR3 training code, and should be extracted from an existing bootable\n"
"image for your board. See 'kwbimage -x' to extract it from an existing image.\n",
- binarye->binary.file, cwd);
- free(cwd);
+ binarye->binary.file, dir);
return 0;
}
}
version = image_get_version();
- /* Fallback to version 0 is no version is provided in the cfg file */
- if (version == -1)
- version = 0;
-
- if (version == 0)
+ switch (version) {
+ /*
+ * Fallback to version 0 if no version is provided in the
+ * cfg file
+ */
+ case -1:
+ case 0:
image = image_create_v0(&headersz, params, sbuf->st_size);
- else if (version == 1)
+ break;
+
+ case 1:
image = image_create_v1(&headersz, params, sbuf->st_size);
+ break;
+
+ default:
+ fprintf(stderr, "Unsupported version %d\n", version);
+ free(image_cfg);
+ exit(EXIT_FAILURE);
+ }
if (!image) {
fprintf(stderr, "Could not create image\n");
printf("Image Type: MVEBU Boot from %s Image\n",
image_boot_mode_name(mhdr->blockid));
- printf("Data Size: ");
printf("Image version:%d\n", image_version((void *)ptr));
+ printf("Data Size: ");
genimg_print_size(mhdr->blocksize - sizeof(uint32_t));
printf("Load Address: %08x\n", mhdr->destaddr);
printf("Entry Point: %08x\n", mhdr->execaddr);
main_hdr = (void *)ptr;
checksum = image_checksum8(ptr,
- sizeof(struct main_hdr_v0));
+ sizeof(struct main_hdr_v0)
+ - sizeof(uint8_t));
if (checksum != main_hdr->checksum)
return -FDT_ERR_BADSTRUCTURE;
if (image_version((void *)ptr) == 0) {
ext_hdr = (void *)ptr + sizeof(struct main_hdr_v0);
checksum = image_checksum8(ext_hdr,
- sizeof(struct ext_hdr_v0));
+ sizeof(struct ext_hdr_v0)
+ - sizeof(uint8_t));
if (checksum != ext_hdr->checksum)
return -FDT_ERR_BADSTRUCTURE;
}
"\t\tkey1=value1\n"
"\t\tkey2=value2\n"
"\t\t...\n"
+ "\tEmpty lines are skipped, and lines with a # in the first\n"
+ "\tcolumn are treated as comments (also skipped).\n"
"\t-r : the environment has multiple copies in flash\n"
"\t-b : the target is big endian (default is little endian)\n"
"\t-p <byte> : fill the image with <byte> bytes instead of 0xff bytes\n"
/* Replace newlines separating variables with \0 */
for (fp = 0, ep = 0 ; fp < filesize ; fp++) {
if (filebuf[fp] == '\n') {
- if (ep == 0) {
+ if (fp == 0 || filebuf[fp-1] == '\n') {
/*
- * Newlines at the beginning of the file ?
- * Ignore them.
+ * Skip empty lines.
*/
continue;
} else if (filebuf[fp-1] == '\\') {
/* End of a variable */
envptr[ep++] = '\0';
}
+ } else if ((fp == 0 || filebuf[fp-1] == '\n') && filebuf[fp] == '#') {
+ /* Comment, skip the line. */
+ while (++fp < filesize && filebuf[fp] != '\n')
+ continue;
} else {
envptr[ep++] = filebuf[fp];
}
static void build_header(uint8_t *buf, uint8_t version, uint8_t flags,
uint16_t length_bytes)
{
- header.validation = htole32(VALIDATION_WORD);
+ header.validation = cpu_to_le32(VALIDATION_WORD);
header.version = version;
header.flags = flags;
- header.length_u32 = htole16(length_bytes/4);
+ header.length_u32 = cpu_to_le16(length_bytes/4);
header.zero = 0;
- header.checksum = htole16(hdr_checksum(&header));
+ header.checksum = cpu_to_le16(hdr_checksum(&header));
memcpy(buf, &header, sizeof(header));
}
{
memcpy(&header, buf, sizeof(header));
- if (le32toh(header.validation) != VALIDATION_WORD)
+ if (le32_to_cpu(header.validation) != VALIDATION_WORD)
return -1;
- if (le16toh(header.checksum) != hdr_checksum(&header))
+ if (le16_to_cpu(header.checksum) != hdr_checksum(&header))
return -1;
- return le16toh(header.length_u32) * 4;
+ return le16_to_cpu(header.length_u32) * 4;
}
/* Sign the buffer and return the signed buffer size */
/* Calculate and apply the CRC */
calc_crc = ~pbl_crc32(0, (char *)buf, len);
- *((uint32_t *)(buf + len)) = htole32(calc_crc);
+ *((uint32_t *)(buf + len)) = cpu_to_le32(calc_crc);
if (!pad_64k)
return len + 4;
calc_crc = ~pbl_crc32(0, (const char *)buf, len);
- buf_crc = le32toh(*((uint32_t *)(buf + len)));
+ buf_crc = le32_to_cpu(*((uint32_t *)(buf + len)));
if (buf_crc != calc_crc) {
fprintf(stderr, "CRC32 does not match (%08x != %08x)\n",
projects / karo-tx-uboot.git / commitdiff