select MMC
select SUPPORT_EMMC_BOOT
-config TX6UL
+config BOARD_TX6UL
bool
- select SOC_MX6UL
select SYS_I2C
select SYS_I2C_SOFT
select SYS_SDRAM_BUS_WIDTH_16
+ help
+ Common settings for TX6UL with i.MX6UL and i.MX6ULL.
+ Selected by TARGET_TX6UL_EMMC or TARGET_TX6UL_NAND.
config TX6QP
bool
config TARGET_TX6UL_NAND
bool "TXUL (i.MX6UL) modules with NAND flash (TXUL-5010)"
- select TX6UL
+ select BOARD_TX6UL
config TARGET_TX6UL_EMMC
bool "TXUL (i.MX6UL) modules with eMMC (TXUL-5011)"
- select TX6UL
+ select BOARD_TX6UL
select TX6_EMMC
config TARGET_TX6QP_EMMC
endchoice
+if BOARD_TX6UL
+
+choice
+ prompt "TX6UL SOC variant"
+
+config TX6UL
+ bool "i.MX6UL"
+ select SOC_MX6UL
+
+config TX6ULL
+ bool "i.MX6ULL"
+ select SOC_MX6ULL
+
+endchoice
+
+endif
+
choice
prompt "U-Boot image variant"
default TX6_UBOOT
LDSCRIPT := $(BOARDDIR)/u-boot.lds
obj-y += pmic.o
-ifeq ($(CONFIG_SOC_MX6UL),y)
+ifeq ($(CONFIG_BOARD_TX6UL),y)
obj-y += tx6ul_ll_init.o tx6ul.o
else
obj-y += lowlevel_init.o tx6qdl.o
# stack is allocated below CONFIG_SYS_TEXT_BASE
-ifeq ($(CONFIG_SOC_MX6SX)$(CONFIG_SOC_MX6SL)$(CONFIG_SOC_MX6UL),)
+ifeq ($(CONFIG_SOC_MX6SX)$(CONFIG_SOC_MX6SL)$(CONFIG_BOARD_TX6UL),)
CONFIG_SYS_TEXT_BASE := 0x100ff000
else
CONFIG_SYS_TEXT_BASE := 0x800ff000
cpu_str = "Q";
else if (is_cpu_type(MXC_CPU_MX6UL))
cpu_str = "UL";
+ else if (is_cpu_type(MXC_CPU_MX6ULL))
+ cpu_str = "ULL";
printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
cpu_str,
static inline u8 tx6ul_mem_suffix(void)
{
-#ifdef CONFIG_TX6_NAND
- return CONFIG_SYS_SDRAM_CHIP_SIZE / 1024 * 2 + '0';
-#else
- return '1';
-#endif
+ return '0' + CONFIG_SYS_SDRAM_CHIP_SIZE / 1024 * 2 +
+ IS_ENABLED(CONFIG_TX6_EMMC);
}
#ifdef CONFIG_RN5T567
{
int ret;
u32 cpurev = get_cpu_rev();
+ char f = '?';
- debug("%s@%d: \n", __func__, __LINE__);
+ if (is_cpu_type(MXC_CPU_MX6UL))
+ f = ((cpurev & 0xf0) > 0x10) ? '5' : '0';
+ else if (is_cpu_type(MXC_CPU_MX6ULL))
+ f = '8';
- printf("Board: Ka-Ro TXUL-%c01%c\n",
- ((cpurev &0xff) > 0x10) ? '5' : '0',
- tx6ul_mem_suffix());
+ debug("%s@%d: cpurev=%08x\n", __func__, __LINE__, cpurev);
+
+ printf("Board: Ka-Ro TXUL-%c01%c\n", f, tx6ul_mem_suffix());
get_hab_status();
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
+ PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
return 0;
}
printf("Failed to request stk5_gpios: %d\n", ret);
return;
}
+
imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
if (getenv_yesno("jtag_enable") != 0) {
/* true if unset or set to one of: 'yYtT1' */
imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads, ARRAY_SIZE(stk5_jtag_pads));
}
+
debug("%s@%d: \n", __func__, __LINE__);
}
MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, CCGR(2)) /* default: 0xcfc03f0f APBH-DMA */
// MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, CCGR()) /* default: 0xfcfc0000 */
// MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR()) /* default: 0x0c3ff033 */
+#ifdef CONFIG_SOC_MX6ULL
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, CCGR(6)) /* default: 0xcfc03f0f ENET */
+#else
MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, CCGR(2)) /* default: 0xffff3300 ENET */
+#endif
#ifdef CONFIG_TX6_NAND
MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4,
CCGR(15) | CCGR(14) | CCGR(13) | CCGR(12)) /* default: 0x0000f3ff GPMI BCH */
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_SOC_MX6UL=y
+CONFIG_BOARD_TX6UL=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6UL_NAND=y
CONFIG_TX6_UBOOT=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_SOC_MX6UL=y
+CONFIG_BOARD_TX6UL=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6UL_NAND=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_SOC_MX6UL=y
+CONFIG_BOARD_TX6UL=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6UL_NAND=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_SOC_MX6UL=y
+CONFIG_BOARD_TX6UL=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6UL_NAND=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_SOC_MX6UL=y
+CONFIG_TX6UL=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6UL_EMMC=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_SOC_MX6UL=y
+CONFIG_BOARD_TX6UL=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6UL_EMMC=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_SOC_MX6UL=y
+CONFIG_BOARD_TX6UL=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6UL_EMMC=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SECURE_BOOT"
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_SOC_MX6UL=y
+CONFIG_BOARD_TX6UL=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6UL_EMMC=y
CONFIG_TX6_UBOOT=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_SOC_MX6UL=y
+CONFIG_BOARD_TX6UL=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6UL_NAND=y
CONFIG_TX6_UBOOT=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_SOC_MX6UL=y
+CONFIG_BOARD_TX6UL=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6UL_NAND=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_SOC_MX6UL=y
+CONFIG_BOARD_TX6UL=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6UL_NAND=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_SOC_MX6UL=y
+CONFIG_BOARD_TX6UL=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6UL_NAND=y
CONFIG_TX6_UBOOT=y
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TX6ULL=y
+CONFIG_TARGET_TX6=y
+CONFIG_TARGET_TX6UL_EMMC=y
+CONFIG_TX6_UBOOT=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FEC_MXC=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_LCD=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6UL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=1024
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TX6ULL=y
+CONFIG_TARGET_TX6=y
+CONFIG_TARGET_TX6UL_EMMC=y
+CONFIG_TX6_UBOOT_MFG=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FEC_MXC=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6UL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=1024
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TX6ULL=y
+CONFIG_TARGET_TX6=y
+CONFIG_TARGET_TX6UL_EMMC=y
+CONFIG_TX6_UBOOT_NOENV=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FEC_MXC=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6UL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=1024
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SECURE_BOOT"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TX6ULL=y
+CONFIG_TARGET_TX6=y
+CONFIG_TARGET_TX6UL_EMMC=y
+CONFIG_TX6_UBOOT=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FEC_MXC=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_LCD=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6UL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=1024
#ifndef __CONFIG_H
#define __CONFIG_H
-#ifndef CONFIG_SOC_MX6UL
+#ifndef CONFIG_BOARD_TX6UL
#define CONFIG_ARM_ERRATA_743622
#define CONFIG_ARM_ERRATA_751472
#define CONFIG_ARM_ERRATA_794072
#ifdef CONFIG_LCD
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
-#ifndef CONFIG_SOC_MX6UL
+#ifndef CONFIG_BOARD_TX6UL
#define CONFIG_VIDEO_IPUV3
#define CONFIG_IPUV3_CLK (CONFIG_SYS_SDRAM_CLK * 1000000 / 2)
#else
#define CONFIG_VIDEO_MXS
#define MXS_LCDIF_BASE 0x021c8000UL
-#endif /* CONFIG_SOC_MX6UL */
+#endif /* CONFIG_BOARD_TX6UL */
#define CONFIG_LCD_LOGO
#define LCD_BPP LCD_COLOR32
#define CONFIG_CMD_BMP
* Memory configuration options
*/
#define CONFIG_NR_DRAM_BANKS 0x1 /* # of SDRAM banks */
+#ifndef CONFIG_BOARD_TX6UL
+/* Base address of SDRAM bank 1 */
+#define PHYS_SDRAM_1 0x10000000
+#else
+#define PHYS_SDRAM_1 0x80000000
+#endif
+
#ifndef CONFIG_SOC_MX6UL
-#define PHYS_SDRAM_1 0x10000000 /* Base address of bank 1 */
#define CONFIG_SYS_MPU_CLK 792
#else
-#define PHYS_SDRAM_1 0x80000000 /* Base address of bank 1 */
#define CONFIG_SYS_MPU_CLK 528
#endif
+
#ifndef CONFIG_SYS_SDRAM_BUS_WIDTH
#if defined(CONFIG_SYS_SDRAM_BUS_WIDTH_32)
#define CONFIG_SYS_SDRAM_BUS_WIDTH 32
#define _AC(x,s) (x##s)
#endif
#define UL(x) _AC(x,UL)
-#define PHYS_SDRAM_1_SIZE (UL(CONFIG_SYS_SDRAM_CHIP_SIZE) * SZ_1M \
- / 32 * CONFIG_SYS_SDRAM_BUS_WIDTH)
+#define PHYS_SDRAM_1_SIZE (UL(CONFIG_SYS_SDRAM_CHIP_SIZE) * \
+ SZ_1M / 32 * \
+ CONFIG_SYS_SDRAM_BUS_WIDTH)
#if PHYS_SDRAM_1_SIZE > SZ_1G
#define FDT_HIGH_STR "fdt_high=ffffffff\0"
#else
#elif defined(CONFIG_SOC_MX6DL)
#elif defined(CONFIG_SOC_MX6S)
#elif defined(CONFIG_SOC_MX6UL)
+#elif defined(CONFIG_SOC_MX6ULL)
#else
#error Unsupported i.MX6 processor variant
#endif
#else
#define CONFIG_BOOTCOMMAND "setenv bootcmd '" DEFAULT_BOOTCMD "';" \
"env import " xstr(CONFIG_BOOTCMD_MFG_LOADADDR) ";run bootcmd_mfg"
-#if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6UL))
+#if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6SL) || \
+ defined(CONFIG_BOARD_TX6UL))
#define CONFIG_BOOTCMD_MFG_LOADADDR 80500000
#else
#define CONFIG_BOOTCMD_MFG_LOADADDR 10500000
#endif
#define CONFIG_DELAY_ENVIRONMENT
#endif /* CONFIG_TX6_UBOOT_MFG */
-#if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6UL))
+#if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6SL) || \
+ defined(CONFIG_BOARD_TX6UL))
#define CONFIG_LOADADDR 82000000
#define CONFIG_FDTADDR 81000000
#else
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0"
#else
+
#define CONFIG_SYS_CPU_CLK_STR xstr(CONFIG_SYS_MPU_CLK)
#define CONFIG_EXTRA_ENV_SETTINGS \
/* This is required for the FEC driver to work with cache enabled */
#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
-#ifndef CONFIG_SOC_MX6UL
+#ifndef CONFIG_BOARD_TX6UL
#define CONFIG_FEC_MXC_PHYADDR 0
#define IMX_FEC_BASE ENET_BASE_ADDR
#else
#error Unsupported TX6 module revision
#endif
#else /* CONFIG_TX6_REV */
-#ifdef CONFIG_SOC_MX6UL
+#ifdef CONFIG_BOARD_TX6UL
#ifdef CONFIG_SYS_I2C_SOFT
/* NOENV U-Boot is used for initial bootstrap.
* Since the TAMPER_PIN_DISABLE fuses have to be programmed
#define CONFIG_SOFT_I2C_GPIO_SDA IMX_GPIO_NR(5, 1)
#define CONFIG_SOFT_I2C_READ_REPEATED_START
#endif /* CONFIG_SYS_I2C_SOFT */
-#else /* !CONFIG_SOC_MX6UL */
+#else /* !CONFIG_BOARD_TX6UL */
/* autodetect which PMIC is present to derive TX6_REV */
#define CONFIG_LTC3676 /* TX6_REV == 1 */
-#endif /* CONFIG_SOC_MX6UL */
+#endif /* CONFIG_BOARD_TX6UL */
#define CONFIG_RN5T567 /* TX6_REV == 3 */
#endif /* CONFIG_TX6_REV */