rockchip: Bring in RK3288 device tree file includes and bindings

Bring in required device tree files from Linux. Since mainline Linux is
somewhat behind, use the files from the Chromium tree. We can re-sync once
further code is acccepted upstream.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/dts/rk3288-thermal.dtsi b/arch/arm/dts/rk3288-thermal.dtsi
new file mode 100644 (file)
index 0000000..59482c1
--- /dev/null
+++ b/arch/arm/dts/rk3288-thermal.dtsi
@@ -0,0 +1,88 @@
+/*
+ * Device Tree Source for RK3288 SoC thermal
+ *
+ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+reserve_thermal: reserve_thermal {
+       polling-delay-passive = <1000>; /* milliseconds */
+       polling-delay = <5000>; /* milliseconds */
+
+                       /* sensor       ID */
+       thermal-sensors = <&tsadc       0>;
+
+};
+
+cpu_thermal: cpu_thermal {
+       polling-delay-passive = <100>; /* milliseconds */
+       polling-delay = <5000>; /* milliseconds */
+
+                       /* sensor       ID */
+       thermal-sensors = <&tsadc       1>;
+       linux,hwmon;
+
+       trips {
+               cpu_alert0: cpu_alert0 {
+                       temperature = <70000>; /* millicelsius */
+                       hysteresis = <2000>; /* millicelsius */
+                       type = "passive";
+               };
+               cpu_alert1: cpu_alert1 {
+                       temperature = <75000>; /* millicelsius */
+                       hysteresis = <2000>; /* millicelsius */
+                       type = "passive";
+               };
+               cpu_crit: cpu_crit {
+                       temperature = <100000>; /* millicelsius */
+                       hysteresis = <2000>; /* millicelsius */
+                       type = "critical";
+               };
+       };
+
+       cooling-maps {
+               map0 {
+                       trip = <&cpu_alert0>;
+                       cooling-device =
+                               <&cpu0 THERMAL_NO_LIMIT 6>;
+               };
+               map1 {
+                       trip = <&cpu_alert1>;
+                       cooling-device =
+                               <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+               };
+       };
+};
+
+gpu_thermal: gpu_thermal {
+       polling-delay-passive = <100>; /* milliseconds */
+       polling-delay = <5000>; /* milliseconds */
+
+                       /* sensor       ID */
+       thermal-sensors = <&tsadc       2>;
+       linux,hwmon;
+
+       trips {
+               gpu_alert0: gpu_alert0 {
+                       temperature = <80000>; /* millicelsius */
+                       hysteresis = <2000>; /* millicelsius */
+                       type = "passive";
+               };
+               gpu_crit: gpu_crit {
+                       temperature = <100000>; /* millicelsius */
+                       hysteresis = <2000>; /* millicelsius */
+                       type = "critical";
+               };
+       };
+
+       cooling-maps {
+               map0 {
+                       trip = <&gpu_alert0>;
+                       cooling-device =
+                               <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+               };
+       };
+};

diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
new file mode 100644 (file)
index 0000000..6b5145c
--- /dev/null
+++ b/arch/arm/dts/rk3288.dtsi
@@ -0,0 +1,1458 @@
+/*
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/clock/rk3288-cru.h>
+#include <dt-bindings/power-domain/rk3288.h>
+#include <dt-bindings/thermal/thermal.h>
+#include "skeleton.dtsi"
+
+/ {
+       compatible = "rockchip,rk3288";
+
+       interrupt-parent = <&gic>;
+       aliases {
+               i2c0 = &i2c0;
+               i2c1 = &i2c1;
+               i2c2 = &i2c2;
+               i2c3 = &i2c3;
+               i2c4 = &i2c4;
+               i2c5 = &i2c5;
+               mmc0 = &emmc;
+               mmc1 = &sdmmc;
+               mmc2 = &sdio0;
+               mmc3 = &sdio1;
+               mshc0 = &emmc;
+               mshc1 = &sdmmc;
+               mshc2 = &sdio0;
+               mshc3 = &sdio1;
+               serial0 = &uart0;
+               serial1 = &uart1;
+               serial2 = &uart2;
+               serial3 = &uart3;
+               serial4 = &uart4;
+               spi0 = &spi0;
+               spi1 = &spi1;
+               spi2 = &spi2;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               enable-method = "rockchip,rk3066-smp";
+               rockchip,pmu = <&pmu>;
+
+               cpu0: cpu@500 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a12";
+                       reg = <0x500>;
+                       operating-points = <
+                               /* KHz    uV */
+                               1800000 1400000
+                               1704000 1350000
+                               1608000 1300000
+                               1512000 1250000
+                               1416000 1200000
+                               1200000 1100000
+                               1008000 1050000
+                                816000 1000000
+                                696000  950000
+                                600000  900000
+                                408000  900000
+                                216000  900000
+                                126000  900000
+                       >;
+                       #cooling-cells = <2>; /* min followed by max */
+                       clock-latency = <40000>;
+                       clocks = <&cru ARMCLK>;
+                       resets = <&cru SRST_CORE0>;
+               };
+               cpu@501 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a12";
+                       reg = <0x501>;
+                       resets = <&cru SRST_CORE1>;
+               };
+               cpu@502 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a12";
+                       reg = <0x502>;
+                       resets = <&cru SRST_CORE2>;
+               };
+               cpu@503 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a12";
+                       reg = <0x503>;
+                       resets = <&cru SRST_CORE3>;
+               };
+       };
+
+       amba {
+               compatible = "arm,amba-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               dmac_peri: dma-controller@ff250000 {
+                       compatible = "arm,pl330", "arm,primecell";
+                       broken-no-flushp;
+                       reg = <0xff250000 0x4000>;
+                       interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                       #dma-cells = <1>;
+                       clocks = <&cru ACLK_DMAC2>;
+                       clock-names = "apb_pclk";
+               };
+
+               dmac_bus_ns: dma-controller@ff600000 {
+                       compatible = "arm,pl330", "arm,primecell";
+                       broken-no-flushp;
+                       reg = <0xff600000 0x4000>;
+                       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+                       #dma-cells = <1>;
+                       clocks = <&cru ACLK_DMAC1>;
+                       clock-names = "apb_pclk";
+                       status = "disabled";
+               };
+
+               dmac_bus_s: dma-controller@ffb20000 {
+                       compatible = "arm,pl330", "arm,primecell";
+                       broken-no-flushp;
+                       reg = <0xffb20000 0x4000>;
+                       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+                       #dma-cells = <1>;
+                       clocks = <&cru ACLK_DMAC1>;
+                       clock-names = "apb_pclk";
+               };
+       };
+
+       xin24m: oscillator {
+               compatible = "fixed-clock";
+               clock-frequency = <24000000>;
+               clock-output-names = "xin24m";
+               #clock-cells = <0>;
+       };
+
+       timer {
+               arm,use-physical-timer;
+               compatible = "arm,armv7-timer";
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+               clock-frequency = <24000000>;
+               always-on;
+       };
+
+       display-subsystem {
+               compatible = "rockchip,display-subsystem";
+               ports = <&vopl_out>, <&vopb_out>;
+       };
+
+       sdmmc: dwmmc@ff0c0000 {
+               compatible = "rockchip,rk3288-dw-mshc";
+               clock-freq-min-max = <400000 150000000>;
+               clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+                        <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+               clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+               fifo-depth = <0x100>;
+               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+               reg = <0xff0c0000 0x4000>;
+               status = "disabled";
+       };
+
+       sdio0: dwmmc@ff0d0000 {
+               compatible = "rockchip,rk3288-dw-mshc";
+               clock-freq-min-max = <400000 150000000>;
+               clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
+                        <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
+               clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+               fifo-depth = <0x100>;
+               interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+               reg = <0xff0d0000 0x4000>;
+               status = "disabled";
+       };
+
+       sdio1: dwmmc@ff0e0000 {
+               compatible = "rockchip,rk3288-dw-mshc";
+               clock-freq-min-max = <400000 150000000>;
+               clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
+                        <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
+               clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+               fifo-depth = <0x100>;
+               interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+               reg = <0xff0e0000 0x4000>;
+               status = "disabled";
+       };
+
+       emmc: dwmmc@ff0f0000 {
+               compatible = "rockchip,rk3288-dw-mshc";
+               clock-freq-min-max = <400000 150000000>;
+               clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
+                        <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+               clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+               fifo-depth = <0x100>;
+               interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+               reg = <0xff0f0000 0x4000>;
+               status = "disabled";
+       };
+
+       saradc: saradc@ff100000 {
+               compatible = "rockchip,saradc";
+               reg = <0xff100000 0x100>;
+               interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+               #io-channel-cells = <1>;
+               clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+               clock-names = "saradc", "apb_pclk";
+               status = "disabled";
+       };
+
+       spi0: spi@ff110000 {
+               compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
+               clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
+               clock-names = "spiclk", "apb_pclk";
+               dmas = <&dmac_peri 11>, <&dmac_peri 12>;
+               dma-names = "tx", "rx";
+               interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
+               reg = <0xff110000 0x1000>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       spi1: spi@ff120000 {
+               compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
+               clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
+               clock-names = "spiclk", "apb_pclk";
+               dmas = <&dmac_peri 13>, <&dmac_peri 14>;
+               dma-names = "tx", "rx";
+               interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
+               reg = <0xff120000 0x1000>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       spi2: spi@ff130000 {
+               compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
+               clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
+               clock-names = "spiclk", "apb_pclk";
+               dmas = <&dmac_peri 15>, <&dmac_peri 16>;
+               dma-names = "tx", "rx";
+               interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
+               reg = <0xff130000 0x1000>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       i2c1: i2c@ff140000 {
+               compatible = "rockchip,rk3288-i2c";
+               reg = <0xff140000 0x1000>;
+               interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "i2c";
+               clocks = <&cru PCLK_I2C1>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&i2c1_xfer>;
+               status = "disabled";
+       };
+
+       i2c3: i2c@ff150000 {
+               compatible = "rockchip,rk3288-i2c";
+               reg = <0xff150000 0x1000>;
+               interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "i2c";
+               clocks = <&cru PCLK_I2C3>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&i2c3_xfer>;
+               status = "disabled";
+       };
+
+       i2c4: i2c@ff160000 {
+               compatible = "rockchip,rk3288-i2c";
+               reg = <0xff160000 0x1000>;
+               interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "i2c";
+               clocks = <&cru PCLK_I2C4>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&i2c4_xfer>;
+               status = "disabled";
+       };
+
+       i2c5: i2c@ff170000 {
+               compatible = "rockchip,rk3288-i2c";
+               reg = <0xff170000 0x1000>;
+               interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "i2c";
+               clocks = <&cru PCLK_I2C5>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&i2c5_xfer>;
+               status = "disabled";
+       };
+       uart0: serial@ff180000 {
+               compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
+               reg = <0xff180000 0x100>;
+               interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+               reg-shift = <2>;
+               reg-io-width = <4>;
+               clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+               clock-names = "baudclk", "apb_pclk";
+               pinctrl-names = "default";
+               pinctrl-0 = <&uart0_xfer>;
+               status = "disabled";
+       };
+
+       uart1: serial@ff190000 {
+               compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
+               reg = <0xff190000 0x100>;
+               interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+               reg-shift = <2>;
+               reg-io-width = <4>;
+               clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+               clock-names = "baudclk", "apb_pclk";
+               pinctrl-names = "default";
+               pinctrl-0 = <&uart1_xfer>;
+               status = "disabled";
+       };
+
+       uart2: serial@ff690000 {
+               compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
+               reg = <0xff690000 0x100>;
+               interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+               reg-shift = <2>;
+               reg-io-width = <4>;
+               clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+               clock-names = "baudclk", "apb_pclk";
+               pinctrl-names = "default";
+               pinctrl-0 = <&uart2_xfer>;
+               status = "disabled";
+       };
+       uart3: serial@ff1b0000 {
+               compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
+               reg = <0xff1b0000 0x100>;
+               interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+               reg-shift = <2>;
+               reg-io-width = <4>;
+               clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+               clock-names = "baudclk", "apb_pclk";
+               pinctrl-names = "default";
+               pinctrl-0 = <&uart3_xfer>;
+               status = "disabled";
+       };
+
+       uart4: serial@ff1c0000 {
+               compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
+               reg = <0xff1c0000 0x100>;
+               interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+               reg-shift = <2>;
+               reg-io-width = <4>;
+               clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+               clock-names = "baudclk", "apb_pclk";
+               pinctrl-names = "default";
+               pinctrl-0 = <&uart4_xfer>;
+               status = "disabled";
+       };
+       thermal: thermal-zones {
+               #include "rk3288-thermal.dtsi"
+       };
+
+       tsadc: tsadc@ff280000 {
+               compatible = "rockchip,rk3288-tsadc";
+               reg = <0xff280000 0x100>;
+               interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
+               clock-names = "tsadc", "apb_pclk";
+               resets = <&cru SRST_TSADC>;
+               reset-names = "tsadc-apb";
+               pinctrl-names = "otp_out";
+               pinctrl-0 = <&otp_out>;
+               #thermal-sensor-cells = <1>;
+               hw-shut-temp = <125000>;
+               status = "disabled";
+       };
+
+       gmac: ethernet@ff290000 {
+               compatible = "rockchip,rk3288-gmac";
+               reg = <0xff290000 0x10000>;
+               interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "macirq";
+               rockchip,grf = <&grf>;
+               clocks = <&cru SCLK_MAC>,
+                       <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
+                       <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
+                       <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
+               clock-names = "stmmaceth",
+                       "mac_clk_rx", "mac_clk_tx",
+                       "clk_mac_ref", "clk_mac_refout",
+                       "aclk_mac", "pclk_mac";
+       };
+
+       usb_host0_ehci: usb@ff500000 {
+               compatible = "generic-ehci";
+               reg = <0xff500000 0x100>;
+               interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru HCLK_USBHOST0>;
+               clock-names = "usbhost";
+               phys = <&usbphy1>;
+               phy-names = "usb";
+               status = "disabled";
+       };
+
+       /* NOTE: ohci@ff520000 doesn't actually work on hardware */
+
+       usb_host1: usb@ff540000 {
+               compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
+                               "snps,dwc2";
+               reg = <0xff540000 0x40000>;
+               interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru HCLK_USBHOST1>;
+               clock-names = "otg";
+               phys = <&usbphy2>;
+               phy-names = "usb2-phy";
+               status = "disabled";
+       };
+
+       usb_otg: usb@ff580000 {
+               compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
+                               "snps,dwc2";
+               reg = <0xff580000 0x40000>;
+               interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru HCLK_OTG0>;
+               clock-names = "otg";
+               phys = <&usbphy0>;
+               phy-names = "usb2-phy";
+               status = "disabled";
+       };
+
+       usb_hsic: usb@ff5c0000 {
+               compatible = "generic-ehci";
+               reg = <0xff5c0000 0x100>;
+               interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru HCLK_HSIC>;
+               clock-names = "usbhost";
+               status = "disabled";
+       };
+
+       dmc: dmc@ff610000 {
+               compatible = "rockchip,rk3288-dmc", "syscon";
+               rockchip,cru = <&cru>;
+               rockchip,grf = <&grf>;
+               rockchip,pmu = <&pmu>;
+               rockchip,sgrf = <&sgrf>;
+               rockchip,noc = <&noc>;
+               reg = <0xff610000 0x3fc
+                      0xff620000 0x294
+                      0xff630000 0x3fc
+                      0xff640000 0x294>;
+               rockchip,sram = <&ddr_sram>;
+               clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
+                        <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
+                        <&cru ARMCLK>;
+               clock-names = "pclk_ddrupctl0", "pclk_publ0",
+                             "pclk_ddrupctl1", "pclk_publ1",
+                             "arm_clk";
+       };
+
+       i2c0: i2c@ff650000 {
+               compatible = "rockchip,rk3288-i2c";
+               reg = <0xff650000 0x1000>;
+               interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "i2c";
+               clocks = <&cru PCLK_I2C0>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&i2c0_xfer>;
+               status = "disabled";
+       };
+
+       i2c2: i2c@ff660000 {
+               compatible = "rockchip,rk3288-i2c";
+               reg = <0xff660000 0x1000>;
+               interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "i2c";
+               clocks = <&cru PCLK_I2C2>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&i2c2_xfer>;
+               status = "disabled";
+       };
+
+       pwm0: pwm@ff680000 {
+               compatible = "rockchip,rk3288-pwm";
+               reg = <0xff680000 0x10>;
+               #pwm-cells = <3>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pwm0_pin>;
+               clocks = <&cru PCLK_PWM>;
+               clock-names = "pwm";
+               rockchip,grf = <&grf>;
+               status = "disabled";
+       };
+
+       pwm1: pwm@ff680010 {
+               compatible = "rockchip,rk3288-pwm";
+               reg = <0xff680010 0x10>;
+               #pwm-cells = <3>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pwm1_pin>;
+               clocks = <&cru PCLK_PWM>;
+               clock-names = "pwm";
+               rockchip,grf = <&grf>;
+               status = "disabled";
+       };
+
+       pwm2: pwm@ff680020 {
+               compatible = "rockchip,rk3288-pwm";
+               reg = <0xff680020 0x10>;
+               #pwm-cells = <3>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pwm2_pin>;
+               clocks = <&cru PCLK_PWM>;
+               clock-names = "pwm";
+               rockchip,grf = <&grf>;
+               status = "disabled";
+       };
+
+       pwm3: pwm@ff680030 {
+               compatible = "rockchip,rk3288-pwm";
+               reg = <0xff680030 0x10>;
+               #pwm-cells = <2>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pwm3_pin>;
+               clocks = <&cru PCLK_PWM>;
+               clock-names = "pwm";
+               rockchip,grf = <&grf>;
+               status = "disabled";
+       };
+
+       bus_intmem@ff700000 {
+               compatible = "mmio-sram";
+               reg = <0xff700000 0x18000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0xff700000 0x18000>;
+               smp-sram@0 {
+                       compatible = "rockchip,rk3066-smp-sram";
+                       reg = <0x00 0x10>;
+               };
+               ddr_sram: ddr-sram@1000 {
+                       compatible = "rockchip,rk3288-ddr-sram";
+                       reg = <0x1000 0x4000>;
+               };
+       };
+
+       sram@ff720000 {
+               compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
+               reg = <0xff720000 0x1000>;
+       };
+
+       pmu: power-management@ff730000 {
+               compatible = "rockchip,rk3288-pmu", "syscon";
+               reg = <0xff730000 0x100>;
+       };
+
+       sgrf: syscon@ff740000 {
+               compatible = "rockchip,rk3288-sgrf", "syscon";
+               reg = <0xff740000 0x1000>;
+       };
+
+       cru: clock-controller@ff760000 {
+               compatible = "rockchip,rk3288-cru";
+               reg = <0xff760000 0x1000>;
+               rockchip,grf = <&grf>;
+               #clock-cells = <1>;
+               #reset-cells = <1>;
+               assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
+                                 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
+                                 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
+                                 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
+                                 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
+                                 <&cru PCLK_PERI>;
+               assigned-clock-rates = <0>, <0>,
+                                      <594000000>, <400000000>,
+                                      <500000000>, <300000000>,
+                                      <150000000>, <75000000>,
+                                      <300000000>, <150000000>,
+                                      <75000000>;
+               assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
+       };
+
+       grf: syscon@ff770000 {
+               compatible = "rockchip,rk3288-grf", "syscon";
+               reg = <0xff770000 0x1000>;
+       };
+
+       wdt: watchdog@ff800000 {
+               compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
+               reg = <0xff800000 0x100>;
+               clocks = <&cru PCLK_WDT>;
+               interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+       };
+
+       i2s: i2s@ff890000 {
+               compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
+               reg = <0xff890000 0x10000>;
+               interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
+               dma-names = "tx", "rx";
+               clock-names = "i2s_hclk", "i2s_clk";
+               clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&i2s0_bus>;
+               status = "disabled";
+       };
+
+       vopb: vop@ff930000 {
+               compatible = "rockchip,rk3288-vop";
+               reg = <0xff930000 0x19c>;
+               interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
+               clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+               resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
+               reset-names = "axi", "ahb", "dclk";
+               iommus = <&vopb_mmu>;
+               power-domains = <&power RK3288_PD_VIO>;
+               status = "disabled";
+               vopb_out: port {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       vopb_out_edp: endpoint@0 {
+                               reg = <0>;
+                               remote-endpoint = <&edp_in_vopb>;
+                       };
+                       vopb_out_hdmi: endpoint@1 {
+                               reg = <1>;
+                               remote-endpoint = <&hdmi_in_vopb>;
+                       };
+               };
+       };
+
+       vopb_mmu: iommu@ff930300 {
+               compatible = "rockchip,iommu";
+               reg = <0xff930300 0x100>;
+               interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "vopb_mmu";
+               power-domains = <&power RK3288_PD_VIO>;
+               #iommu-cells = <0>;
+               status = "disabled";
+       };
+
+       vopl: vop@ff940000 {
+               compatible = "rockchip,rk3288-vop";
+               reg = <0xff940000 0x19c>;
+               interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
+               clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+               resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
+               reset-names = "axi", "ahb", "dclk";
+               iommus = <&vopl_mmu>;
+               power-domains = <&power RK3288_PD_VIO>;
+               status = "disabled";
+               vopl_out: port {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       vopl_out_edp: endpoint@0 {
+                               reg = <0>;
+                               remote-endpoint = <&edp_in_vopl>;
+                       };
+                       vopl_out_hdmi: endpoint@1 {
+                               reg = <1>;
+                               remote-endpoint = <&hdmi_in_vopl>;
+                       };
+
+               };
+       };
+
+       vopl_mmu: iommu@ff940300 {
+               compatible = "rockchip,iommu";
+               reg = <0xff940300 0x100>;
+               interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "vopl_mmu";
+               power-domains = <&power RK3288_PD_VIO>;
+               #iommu-cells = <0>;
+               status = "disabled";
+       };
+
+       edp: edp@ff970000 {
+               compatible = "rockchip,rk3288-edp";
+               reg = <0xff970000 0x4000>;
+               interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
+               rockchip,grf = <&grf>;
+               clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
+               resets = <&cru 111>;
+               reset-names = "edp";
+               power-domains = <&power RK3288_PD_VIO>;
+               status = "disabled";
+               ports {
+                       edp_in: port {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               edp_in_vopb: endpoint@0 {
+                                       reg = <0>;
+                                       remote-endpoint = <&vopb_out_edp>;
+                               };
+                               edp_in_vopl: endpoint@1 {
+                                       reg = <1>;
+                                       remote-endpoint = <&vopl_out_edp>;
+                               };
+                       };
+               };
+       };
+
+       hdmi: hdmi@ff980000 {
+               compatible = "rockchip,rk3288-dw-hdmi";
+               reg = <0xff980000 0x20000>;
+               reg-io-width = <4>;
+               ddc-i2c-bus = <&i2c5>;
+               rockchip,grf = <&grf>;
+               interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
+               clock-names = "iahb", "isfr";
+               status = "disabled";
+               ports {
+                       hdmi_in: port {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               hdmi_in_vopb: endpoint@0 {
+                                       reg = <0>;
+                                       remote-endpoint = <&vopb_out_hdmi>;
+                               };
+                               hdmi_in_vopl: endpoint@1 {
+                                       reg = <1>;
+                                       remote-endpoint = <&vopl_out_hdmi>;
+                               };
+                       };
+               };
+       };
+
+       hdmi_audio: hdmi_audio {
+               compatible = "rockchip,rk3288-hdmi-audio";
+               i2s-controller = <&i2s>;
+               status = "disable";
+       };
+
+       vpu: video-codec@ff9a0000 {
+               compatible = "rockchip,rk3288-vpu";
+               reg = <0xff9a0000 0x800>;
+               interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "vepu", "vdpu";
+               clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+               clock-names = "aclk_vcodec", "hclk_vcodec";
+               power-domains = <&power RK3288_PD_VIDEO>;
+               iommus = <&vpu_mmu>;
+       };
+
+       vpu_mmu: iommu@ff9a0800 {
+               compatible = "rockchip,iommu";
+               reg = <0xff9a0800 0x100>;
+               interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "vpu_mmu";
+               power-domains = <&power RK3288_PD_VIDEO>;
+               #iommu-cells = <0>;
+       };
+
+       gpu: gpu@ffa30000 {
+               compatible = "arm,malit764",
+                            "arm,malit76x",
+                            "arm,malit7xx",
+                            "arm,mali-midgard";
+               reg = <0xffa30000 0x10000>;
+               interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "JOB", "MMU", "GPU";
+               clocks = <&cru ACLK_GPU>;
+               clock-names = "aclk_gpu";
+               operating-points = <
+                       /* KHz uV */
+                       100000 950000
+                       200000 950000
+                       300000 1000000
+                       400000 1100000
+                       /* 500000 1200000 - See crosbug.com/p/33857 */
+                       600000 1250000
+               >;
+               power-domains = <&power RK3288_PD_GPU>;
+               status = "disabled";
+       };
+
+       noc: syscon@ffac0000 {
+               compatible = "rockchip,rk3288-noc", "syscon";
+               reg = <0xffac0000 0x2000>;
+       };
+
+       efuse: efuse@ffb40000 {
+               compatible = "rockchip,rk3288-efuse";
+               reg = <0xffb40000 0x10000>;
+               status = "disabled";
+       };
+
+       gic: interrupt-controller@ffc01000 {
+               compatible = "arm,gic-400";
+               interrupt-controller;
+               #interrupt-cells = <3>;
+               #address-cells = <0>;
+
+               reg = <0xffc01000 0x1000>,
+                     <0xffc02000 0x1000>,
+                     <0xffc04000 0x2000>,
+                     <0xffc06000 0x2000>;
+               interrupts = <GIC_PPI 9 0xf04>;
+       };
+
+       cpuidle: cpuidle {
+               compatible = "rockchip,rk3288-cpuidle";
+       };
+
+       usbphy: phy {
+               compatible = "rockchip,rk3288-usb-phy";
+               rockchip,grf = <&grf>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+
+               usbphy0: usb-phy0 {
+                       #phy-cells = <0>;
+                       reg = <0x320>;
+                       clocks = <&cru SCLK_OTGPHY0>;
+                       clock-names = "phyclk";
+               };
+
+               usbphy1: usb-phy1 {
+                       #phy-cells = <0>;
+                       reg = <0x334>;
+                       clocks = <&cru SCLK_OTGPHY1>;
+                       clock-names = "phyclk";
+               };
+
+               usbphy2: usb-phy2 {
+                       #phy-cells = <0>;
+                       reg = <0x348>;
+                       clocks = <&cru SCLK_OTGPHY2>;
+                       clock-names = "phyclk";
+               };
+       };
+
+       pinctrl: pinctrl {
+               compatible = "rockchip,rk3288-pinctrl";
+               rockchip,grf = <&grf>;
+               rockchip,pmu = <&pmu>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               gpio0: gpio0@ff750000 {
+                       compatible = "rockchip,gpio-bank";
+                       reg =   <0xff750000 0x100>;
+                       interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cru PCLK_GPIO0>;
+
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpio1: gpio1@ff780000 {
+                       compatible = "rockchip,gpio-bank";
+                       reg = <0xff780000 0x100>;
+                       interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cru PCLK_GPIO1>;
+
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpio2: gpio2@ff790000 {
+                       compatible = "rockchip,gpio-bank";
+                       reg = <0xff790000 0x100>;
+                       interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cru PCLK_GPIO2>;
+
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpio3: gpio3@ff7a0000 {
+                       compatible = "rockchip,gpio-bank";
+                       reg = <0xff7a0000 0x100>;
+                       interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cru PCLK_GPIO3>;
+
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpio4: gpio4@ff7b0000 {
+                       compatible = "rockchip,gpio-bank";
+                       reg = <0xff7b0000 0x100>;
+                       interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cru PCLK_GPIO4>;
+
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpio5: gpio5@ff7c0000 {
+                       compatible = "rockchip,gpio-bank";
+                       reg = <0xff7c0000 0x100>;
+                       interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cru PCLK_GPIO5>;
+
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpio6: gpio6@ff7d0000 {
+                       compatible = "rockchip,gpio-bank";
+                       reg = <0xff7d0000 0x100>;
+                       interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cru PCLK_GPIO6>;
+
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpio7: gpio7@ff7e0000 {
+                       compatible = "rockchip,gpio-bank";
+                       reg = <0xff7e0000 0x100>;
+                       interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cru PCLK_GPIO7>;
+
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpio8: gpio8@ff7f0000 {
+                       compatible = "rockchip,gpio-bank";
+                       reg = <0xff7f0000 0x100>;
+                       interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cru PCLK_GPIO8>;
+
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               pcfg_pull_up: pcfg-pull-up {
+                       bias-pull-up;
+               };
+
+               pcfg_pull_down: pcfg-pull-down {
+                       bias-pull-down;
+               };
+
+               pcfg_pull_none: pcfg-pull-none {
+                       bias-disable;
+               };
+
+               pcfg_pull_none_12ma: pcfg-pull-none-12ma {
+                       bias-disable;
+                       drive-strength = <12>;
+               };
+
+               sleep {
+                       global_pwroff: global-pwroff {
+                               rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+
+                       ddrio_pwroff: ddrio-pwroff {
+                               rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+
+                       ddr0_retention: ddr0-retention {
+                               rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+
+                       ddr1_retention: ddr1-retention {
+                               rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+               };
+
+               i2c0 {
+                       i2c0_xfer: i2c0-xfer {
+                               rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
+                                               <0 16 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               i2c1 {
+                       i2c1_xfer: i2c1-xfer {
+                               rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
+                                               <8 5 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               i2c2 {
+                       i2c2_xfer: i2c2-xfer {
+                               rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
+                                               <6 10 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               i2c3 {
+                       i2c3_xfer: i2c3-xfer {
+                               rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
+                                               <2 17 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               i2c4 {
+                       i2c4_xfer: i2c4-xfer {
+                               rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
+                                               <7 18 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               i2c5 {
+                       i2c5_xfer: i2c5-xfer {
+                               rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
+                                               <7 20 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               i2s0 {
+                       i2s0_bus: i2s0-bus {
+                               rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
+                                               <6 1 RK_FUNC_1 &pcfg_pull_none>,
+                                               <6 2 RK_FUNC_1 &pcfg_pull_none>,
+                                               <6 3 RK_FUNC_1 &pcfg_pull_none>,
+                                               <6 4 RK_FUNC_1 &pcfg_pull_none>,
+                                               <6 8 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               sdmmc {
+                       sdmmc_clk: sdmmc-clk {
+                               rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+
+                       sdmmc_cmd: sdmmc-cmd {
+                               rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+
+                       sdmmc_cd: sdmcc-cd {
+                               rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+
+                       sdmmc_bus1: sdmmc-bus1 {
+                               rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+
+                       sdmmc_bus4: sdmmc-bus4 {
+                               rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
+                                               <6 17 RK_FUNC_1 &pcfg_pull_up>,
+                                               <6 18 RK_FUNC_1 &pcfg_pull_up>,
+                                               <6 19 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+               };
+
+               sdio0 {
+                       sdio0_bus1: sdio0-bus1 {
+                               rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+
+                       sdio0_bus4: sdio0-bus4 {
+                               rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
+                                               <4 21 RK_FUNC_1 &pcfg_pull_up>,
+                                               <4 22 RK_FUNC_1 &pcfg_pull_up>,
+                                               <4 23 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+
+                       sdio0_cmd: sdio0-cmd {
+                               rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+
+                       sdio0_clk: sdio0-clk {
+                               rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+
+                       sdio0_cd: sdio0-cd {
+                               rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+
+                       sdio0_wp: sdio0-wp {
+                               rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+
+                       sdio0_pwr: sdio0-pwr {
+                               rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+
+                       sdio0_bkpwr: sdio0-bkpwr {
+                               rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+
+                       sdio0_int: sdio0-int {
+                               rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+               };
+
+               sdio1 {
+                       sdio1_bus1: sdio1-bus1 {
+                               rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>;
+                       };
+
+                       sdio1_bus4: sdio1-bus4 {
+                               rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
+                                               <3 25 RK_FUNC_4 &pcfg_pull_up>,
+                                               <3 26 RK_FUNC_4 &pcfg_pull_up>,
+                                               <3 27 RK_FUNC_4 &pcfg_pull_up>;
+                       };
+
+                       sdio1_cd: sdio1-cd {
+                               rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>;
+                       };
+
+                       sdio1_wp: sdio1-wp {
+                               rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>;
+                       };
+
+                       sdio1_bkpwr: sdio1-bkpwr {
+                               rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>;
+                       };
+
+                       sdio1_int: sdio1-int {
+                               rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>;
+                       };
+
+                       sdio1_cmd: sdio1-cmd {
+                               rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
+                       };
+
+                       sdio1_clk: sdio1-clk {
+                               rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
+                       };
+
+                       sdio1_pwr: sdio1-pwr {
+                               rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
+                       };
+               };
+
+               emmc {
+                       emmc_clk: emmc-clk {
+                               rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+
+                       emmc_cmd: emmc-cmd {
+                               rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+
+                       emmc_pwr: emmc-pwr {
+                               rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+
+                       emmc_bus1: emmc-bus1 {
+                               rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+
+                       emmc_bus4: emmc-bus4 {
+                               rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
+                                               <3 1 RK_FUNC_2 &pcfg_pull_up>,
+                                               <3 2 RK_FUNC_2 &pcfg_pull_up>,
+                                               <3 3 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+
+                       emmc_bus8: emmc-bus8 {
+                               rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
+                                               <3 1 RK_FUNC_2 &pcfg_pull_up>,
+                                               <3 2 RK_FUNC_2 &pcfg_pull_up>,
+                                               <3 3 RK_FUNC_2 &pcfg_pull_up>,
+                                               <3 4 RK_FUNC_2 &pcfg_pull_up>,
+                                               <3 5 RK_FUNC_2 &pcfg_pull_up>,
+                                               <3 6 RK_FUNC_2 &pcfg_pull_up>,
+                                               <3 7 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+               };
+
+               spi0 {
+                       spi0_clk: spi0-clk {
+                               rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+                       spi0_cs0: spi0-cs0 {
+                               rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+                       spi0_tx: spi0-tx {
+                               rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+                       spi0_rx: spi0-rx {
+                               rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+                       spi0_cs1: spi0-cs1 {
+                               rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+               };
+               spi1 {
+                       spi1_clk: spi1-clk {
+                               rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi1_cs0: spi1-cs0 {
+                               rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi1_rx: spi1-rx {
+                               rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi1_tx: spi1-tx {
+                               rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+               };
+
+               spi2 {
+                       spi2_cs1: spi2-cs1 {
+                               rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+                       spi2_clk: spi2-clk {
+                               rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+                       spi2_cs0: spi2-cs0 {
+                               rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+                       spi2_rx: spi2-rx {
+                               rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+                       spi2_tx: spi2-tx {
+                               rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+               };
+
+               uart0 {
+                       uart0_xfer: uart0-xfer {
+                               rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
+                                               <4 17 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+
+                       uart0_cts: uart0-cts {
+                               rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+
+                       uart0_rts: uart0-rts {
+                               rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               uart1 {
+                       uart1_xfer: uart1-xfer {
+                               rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
+                                               <5 9 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+
+                       uart1_cts: uart1-cts {
+                               rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+
+                       uart1_rts: uart1-rts {
+                               rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               uart2 {
+                       uart2_xfer: uart2-xfer {
+                               rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
+                                               <7 23 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+                       /* no rts / cts for uart2 */
+               };
+
+               uart3 {
+                       uart3_xfer: uart3-xfer {
+                               rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
+                                               <7 8 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+
+                       uart3_cts: uart3-cts {
+                               rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+
+                       uart3_rts: uart3-rts {
+                               rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               uart4 {
+                       uart4_xfer: uart4-xfer {
+                               rockchip,pins = <5 12 3 &pcfg_pull_up>,
+                                               <5 13 3 &pcfg_pull_none>;
+                       };
+
+                       uart4_cts: uart4-cts {
+                               rockchip,pins = <5 14 3 &pcfg_pull_none>;
+                       };
+
+                       uart4_rts: uart4-rts {
+                               rockchip,pins = <5 15 3 &pcfg_pull_none>;
+                       };
+               };
+
+               tsadc {
+                       otp_out: otp-out {
+                               rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               pwm0 {
+                       pwm0_pin: pwm0-pin {
+                               rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               pwm1 {
+                       pwm1_pin: pwm1-pin {
+                               rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               pwm2 {
+                       pwm2_pin: pwm2-pin {
+                               rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>;
+                       };
+               };
+
+               pwm3 {
+                       pwm3_pin: pwm3-pin {
+                               rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>;
+                       };
+               };
+
+               gmac {
+                       rgmii_pins: rgmii-pins {
+                               rockchip,pins = <3 30 3 &pcfg_pull_none>,
+                                               <3 31 3 &pcfg_pull_none>,
+                                               <3 26 3 &pcfg_pull_none>,
+                                               <3 27 3 &pcfg_pull_none>,
+                                               <3 28 3 &pcfg_pull_none_12ma>,
+                                               <3 29 3 &pcfg_pull_none_12ma>,
+                                               <3 24 3 &pcfg_pull_none_12ma>,
+                                               <3 25 3 &pcfg_pull_none_12ma>,
+                                               <4 0 3 &pcfg_pull_none>,
+                                               <4 5 3 &pcfg_pull_none>,
+                                               <4 6 3 &pcfg_pull_none>,
+                                               <4 9 3 &pcfg_pull_none_12ma>,
+                                               <4 4 3 &pcfg_pull_none_12ma>,
+                                               <4 1 3 &pcfg_pull_none>,
+                                               <4 3 3 &pcfg_pull_none>;
+                       };
+
+                       rmii_pins: rmii-pins {
+                               rockchip,pins = <3 30 3 &pcfg_pull_none>,
+                                               <3 31 3 &pcfg_pull_none>,
+                                               <3 28 3 &pcfg_pull_none>,
+                                               <3 29 3 &pcfg_pull_none>,
+                                               <4 0 3 &pcfg_pull_none>,
+                                               <4 5 3 &pcfg_pull_none>,
+                                               <4 4 3 &pcfg_pull_none>,
+                                               <4 1 3 &pcfg_pull_none>,
+                                               <4 2 3 &pcfg_pull_none>,
+                                               <4 3 3 &pcfg_pull_none>;
+                       };
+               };
+       };
+
+       power: power-controller {
+               compatible = "rockchip,rk3288-power-controller";
+               #power-domain-cells = <1>;
+               rockchip,pmu = <&pmu>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               pd_gpu {
+                       reg = <RK3288_PD_GPU>;
+                       clocks = <&cru ACLK_GPU>;
+               };
+
+               pd_hevc {
+                       reg = <RK3288_PD_HEVC>;
+                       clocks = <&cru ACLK_HEVC>,
+                                <&cru SCLK_HEVC_CABAC>,
+                                <&cru SCLK_HEVC_CORE>,
+                                <&cru HCLK_HEVC>;
+               };
+
+               pd_vio {
+                       reg = <RK3288_PD_VIO>;
+                       clocks = <&cru ACLK_IEP>,
+                                <&cru ACLK_ISP>,
+                                <&cru ACLK_RGA>,
+                                <&cru ACLK_VIP>,
+                                <&cru ACLK_VOP0>,
+                                <&cru ACLK_VOP1>,
+                                <&cru DCLK_VOP0>,
+                                <&cru DCLK_VOP1>,
+                                <&cru HCLK_IEP>,
+                                <&cru HCLK_ISP>,
+                                <&cru HCLK_RGA>,
+                                <&cru HCLK_VIP>,
+                                <&cru HCLK_VOP0>,
+                                <&cru HCLK_VOP1>,
+                                <&cru PCLK_EDP_CTRL>,
+                                <&cru PCLK_HDMI_CTRL>,
+                                <&cru PCLK_LVDS_PHY>,
+                                <&cru PCLK_MIPI_CSI>,
+                                <&cru PCLK_MIPI_DSI0>,
+                                <&cru PCLK_MIPI_DSI1>,
+                                <&cru SCLK_EDP_24M>,
+                                <&cru SCLK_EDP>,
+                                <&cru SCLK_HDMI_CEC>,
+                                <&cru SCLK_HDMI_HDCP>,
+                                <&cru SCLK_ISP_JPE>,
+                                <&cru SCLK_ISP>,
+                                <&cru SCLK_RGA>;
+               };
+
+               pd_video {
+                       reg = <RK3288_PD_VIDEO>;
+                       clocks = <&cru ACLK_VCODEC>,
+                                <&cru HCLK_VCODEC>;
+               };
+       };
+};

diff --git a/doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt b/doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt
new file mode 100644 (file)
index 0000000..0c2bf5e
--- /dev/null
+++ b/doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt
@@ -0,0 +1,61 @@
+* Rockchip RK3188/RK3066 Clock and Reset Unit
+
+The RK3188/RK3066 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
+                       "rockchip,rk3066a-cru"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+  If missing pll rates are not changable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
+dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
+Similar macros exist for the reset sources in these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "xin32k" - rtc clock - optional,
+ - "xin27m" - 27mhz crystal input on rk3066 - optional,
+ - "ext_hsadc" - external HSADC clock - optional,
+ - "ext_cif0" - external camera clock - optional,
+ - "ext_rmii" - external RMII clock - optional,
+ - "ext_jtag" - externalJTAG clock - optional
+
+Example: Clock controller node:
+
+       cru: cru@20000000 {
+               compatible = "rockchip,rk3188-cru";
+               reg = <0x20000000 0x1000>;
+               rockchip,grf = <&grf>;
+
+               #clock-cells = <1>;
+               #reset-cells = <1>;
+       };
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller:
+
+       uart0: serial@10124000 {
+               compatible = "snps,dw-apb-uart";
+               reg = <0x10124000 0x400>;
+               interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+               reg-shift = <2>;
+               reg-io-width = <1>;
+               clocks = <&cru SCLK_UART0>;
+       };

diff --git a/doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt b/doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt
new file mode 100644 (file)
index 0000000..c9fbb76
--- /dev/null
+++ b/doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt
@@ -0,0 +1,61 @@
+* Rockchip RK3288 Clock and Reset Unit
+
+The RK3288 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: should be "rockchip,rk3288-cru"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+  If missing pll rates are not changable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "xin32k" - rtc clock - optional,
+ - "ext_i2s" - external I2S clock - optional,
+ - "ext_hsadc" - external HSADC clock - optional,
+ - "ext_edp_24m" - external display port clock - optional,
+ - "ext_vip" - external VIP clock - optional,
+ - "ext_isp" - external ISP clock - optional,
+ - "ext_jtag" - external JTAG clock - optional
+
+Example: Clock controller node:
+
+       cru: cru@20000000 {
+               compatible = "rockchip,rk3188-cru";
+               reg = <0x20000000 0x1000>;
+               rockchip,grf = <&grf>;
+
+               #clock-cells = <1>;
+               #reset-cells = <1>;
+       };
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller:
+
+       uart0: serial@10124000 {
+               compatible = "snps,dw-apb-uart";
+               reg = <0x10124000 0x400>;
+               interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+               reg-shift = <2>;
+               reg-io-width = <1>;
+               clocks = <&cru SCLK_UART0>;
+       };

diff --git a/doc/device-tree-bindings/clock/rockchip,rk3288-dmc.txt b/doc/device-tree-bindings/clock/rockchip,rk3288-dmc.txt
new file mode 100644 (file)
index 0000000..2ca9db7
--- /dev/null
+++ b/doc/device-tree-bindings/clock/rockchip,rk3288-dmc.txt
@@ -0,0 +1,155 @@
+Rockchip Dynamic Memory Controller Driver
+Required properties:
+- compatible: "rockchip,rk3288-dmc", "syscon"
+- rockchip,cru: this driver should access cru regs, so need get cru here
+- rockchip,grf: this driver should access grf regs, so need get grf here
+- rockchip,pmu: this driver should access pmu regs, so need get pmu here
+- rockchip,sgrf: this driver should access sgrf regs, so need get sgrf here
+- rockchip,noc: this driver should access noc regs, so need get noc here
+- reg: dynamic ram protocol controller(PCTL) address and phy controller(PHYCTL) address
+- clock: must include clock specifiers corresponding to entries in the clock-names property.
+- clock-output-names: from common clock binding to override the default output clock name
+    Must contain
+      pclk_ddrupctl0: support clock for access protocol controller registers of channel 0
+      pclk_publ0: support clock for access phy controller registers of channel 0
+      pclk_ddrupctl1: support clock for access protocol controller registers of channel 1
+      pclk_publ1: support clock for access phy controller registers of channel 1
+      arm_clk: for get arm frequency
+-logic-supply: this driver should adjust VDD_LOGIC according to dmc frequency, so need get logic-supply here
+-timings:
+    Must contain
+      rockchip,odt-disable-freq: if ddr clock frequency low than odt-disable-freq,this driver should disable DDR ODT
+      rockchip,dll-disable-freq: if ddr clock frequency low than dll-disable-freq,this driver should disable DDR DLL
+      rockchip,sr-enable-freq: if ddr clock frequency high than sr-enable-freq,this driver should enable the automatic self refresh function
+      rockchip,pd-enable-freq: if ddr clock frequency high than pd-enable-freq,this driver should enable the automatic power down function
+      rockchip,auto-self-refresh-cnt: Self Refresh idle period. Memories are placed into Self-Refresh mode if the NIF is idle in Access state for auto-self-refresh-cnt * 32 * n_clk cycles.The automatic self refresh function is disabled when auto-self-refresh-cnt=0.
+      rockchip,auto-power-down-cnt: Power-down idle period. Memories are placed into power-down mode if the NIF is idle for auto-power-down-cnt n_clk cycles.The automatic power down function is disabled when auto-power-down-cnt=0.
+      rockchip,ddr-speed-bin: DDR3 type,AC timing parameters from the memory data-sheet
+        0.DDR3_800D (5-5-5)
+        1.DDR3_800E (6-6-6)
+        2.DDR3_1066E (6-6-6)
+        3.DDR3_1066F (7-7-7)
+        4.DDR3_1066G (8-8-8)
+        5.DDR3_1333F (7-7-7)
+        6.DDR3_1333G (8-8-8)
+        7.DDR3_1333H (9-9-9)
+        8.DDR3_1333J (10-10-10)
+        9.DDR3_1600G (8-8-8)
+        10.DDR3_1600H (9-9-9)
+        11.DDR3_1600J (10-10-10)
+        12.DDR3_1600K (11-11-11)
+        13.DDR3_1866J (10-10-10)
+        14.DDR3_1866K (11-11-11)
+        15.DDR3_1866L (12-12-12)
+        16.DDR3_1866M (13-13-13)
+        17.DDR3_2133K (11-11-11)
+        18.DDR3_2133L (12-12-12)
+        19.DDR3_2133M (13-13-13)
+        20.DDR3_2133N (14-14-14)
+        21.DDR3_DEFAULT
+      rockchip,trcd: tRCD,AC timing parameters from the memory data-sheet
+      rockchip,trp: tRP,AC timing parameters from the memory data-sheet
+-rockchip,num-channels: number of SDRAM channels (1 or 2)
+-rockchip,pctl-timing: parameters for the SDRAM setup, in this order:
+       togcnt1u
+       tinit
+       trsth
+       togcnt100n
+       trefi
+       tmrd
+       trfc
+       trp
+       trtw
+       tal
+       tcl
+       tcwl
+       tras
+       trc
+       trcd
+       trrd
+       trtp
+       twr
+       twtr
+       texsr
+       txp
+       txpdll
+       tzqcs
+       tzqcsi
+       tdqs
+       tcksre
+       tcksrx
+       tcke
+       tmod
+       trstl
+       tzqcl
+       tmrr
+       tckesr
+       tdpd
+-rockchip,phy-timing: PHY timing information in this order:
+       dtpr0
+       dtpr1
+       dtpr2
+       mr0..mr3
+-rockchip,sdram-channel: SDRAM channel information, each 8 bits. Both channels
+will be set up the same. The parameters are in this order:
+       rank
+       col
+       bk
+       bw
+       dbw
+       row_3_4
+       cs0_row
+       cs1_row
+- rockchip,sdram-params: SDRAM base parameters, in this order:
+       NOC timing      - value for ddrtiming register
+       NOC activate    - value for activate register
+       ddrconf         - value for ddrconf register
+       DDR frequency in MHz
+       DRAM type (3=DDR3, 6=LPDDR3)
+       stride          - stride value for soc_con2 register
+       odt             - 1 to enable DDR ODT, 0 to disable
+
+Example:
+       dmc: dmc@ff610000 {
+               compatible = "rockchip,rk3288-dmc", "syscon";
+               rockchip,cru = <&cru>;
+               rockchip,grf = <&grf>;
+               rockchip,pmu = <&pmu>;
+               rockchip,sgrf = <&sgrf>;
+               rockchip,noc = <&noc>;
+               reg = <0xff610000 0x3fc
+                      0xff620000 0x294
+                      0xff630000 0x3fc
+                      0xff640000 0x294>;
+               clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
+                        <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
+                        <&cru ARMCLK>;
+               clock-names = "pclk_ddrupctl0", "pclk_publ0",
+                             "pclk_ddrupctl1", "pclk_publ1",
+                             "arm_clk";
+       };
+
+       &dmc {
+               logic-supply = <&vdd_logic>;
+               timings {
+                       rockchip,odt-disable-freq = <333000000>;
+                       rockchip,dll-disable-freq = <333000000>;
+                       rockchip,sr-enable-freq = <333000000>;
+                       rockchip,pd-enable-freq = <666000000>;
+                       rockchip,auto-self-refresh-cnt = <0>;
+                       rockchip,auto-power-down-cnt = <64>;
+                       rockchip,ddr-speed-bin = <21>;
+                       rockchip,trcd = <10>;
+                       rockchip,trp = <10>;
+               };
+               rockchip,num-channels = <2>;
+               rockchip,pctl-timing = <0x29a 0x1f4 0xc8 0x42 0x4e 0x4 0xea 0xa
+                       0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
+                       0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
+                       0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
+                       0x5 0x0>;
+               rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
+                       0xa60 0x40 0x10 0x0>;
+               rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf>;
+               rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
+       };

diff --git a/doc/device-tree-bindings/clock/rockchip.txt b/doc/device-tree-bindings/clock/rockchip.txt
new file mode 100644 (file)
index 0000000..22f6769
--- /dev/null
+++ b/doc/device-tree-bindings/clock/rockchip.txt
@@ -0,0 +1,77 @@
+Device Tree Clock bindings for arch-rockchip
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+== Gate clocks ==
+
+These bindings are deprecated!
+Please use the soc specific CRU bindings instead.
+
+The gate registers form a continuos block which makes the dt node
+structure a matter of taste, as either all gates can be put into
+one gate clock spanning all registers or they can be divided into
+the 10 individual gates containing 16 clocks each.
+The code supports both approaches.
+
+Required properties:
+- compatible : "rockchip,rk2928-gate-clk"
+- reg : shall be the control register address(es) for the clock.
+- #clock-cells : from common clock binding; shall be set to 1
+- clock-output-names : the corresponding gate names that the clock controls
+- clocks : should contain the parent clock for each individual gate,
+  therefore the number of clocks elements should match the number of
+  clock-output-names
+
+Example using multiple gate clocks:
+
+               clk_gates0: gate-clk@200000d0 {
+                       compatible = "rockchip,rk2928-gate-clk";
+                       reg = <0x200000d0 0x4>;
+                       clocks = <&dummy>, <&dummy>,
+                                <&dummy>, <&dummy>,
+                                <&dummy>, <&dummy>,
+                                <&dummy>, <&dummy>,
+                                <&dummy>, <&dummy>,
+                                <&dummy>, <&dummy>,
+                                <&dummy>, <&dummy>,
+                                <&dummy>, <&dummy>;
+
+                       clock-output-names =
+                               "gate_core_periph", "gate_cpu_gpll",
+                               "gate_ddrphy", "gate_aclk_cpu",
+                               "gate_hclk_cpu", "gate_pclk_cpu",
+                               "gate_atclk_cpu", "gate_i2s0",
+                               "gate_i2s0_frac", "gate_i2s1",
+                               "gate_i2s1_frac", "gate_i2s2",
+                               "gate_i2s2_frac", "gate_spdif",
+                               "gate_spdif_frac", "gate_testclk";
+
+                       #clock-cells = <1>;
+               };
+
+               clk_gates1: gate-clk@200000d4 {
+                       compatible = "rockchip,rk2928-gate-clk";
+                       reg = <0x200000d4 0x4>;
+                       clocks = <&xin24m>, <&xin24m>,
+                                <&xin24m>, <&dummy>,
+                                <&dummy>, <&xin24m>,
+                                <&xin24m>, <&dummy>,
+                                <&xin24m>, <&dummy>,
+                                <&xin24m>, <&dummy>,
+                                <&xin24m>, <&dummy>,
+                                <&xin24m>, <&dummy>;
+
+                       clock-output-names =
+                               "gate_timer0", "gate_timer1",
+                               "gate_timer2", "gate_jtag",
+                               "gate_aclk_lcdc1_src", "gate_otgphy0",
+                               "gate_otgphy1", "gate_ddr_gpll",
+                               "gate_uart0", "gate_frac_uart0",
+                               "gate_uart1", "gate_frac_uart1",
+                               "gate_uart2", "gate_frac_uart2",
+                               "gate_uart3", "gate_frac_uart3";
+
+                       #clock-cells = <1>;
+               };

diff --git a/doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt b/doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt
new file mode 100644 (file)
index 0000000..388b213
--- /dev/null
+++ b/doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt
@@ -0,0 +1,157 @@
+* Rockchip Pinmux Controller
+
+The Rockchip Pinmux Controller, enables the IC
+to share one PAD to several functional blocks. The sharing is done by
+multiplexing the PAD input/output signals. For each PAD there are several
+muxing options with option 0 being the use as a GPIO.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The Rockchip pin configuration node is a node of a group of pins which can be
+used for a specific device or function. This node represents both mux and
+config of the pins in that group. The 'pins' selects the function mode(also
+named pin mode) this pin can work on and the 'config' configures various pad
+settings such as pull-up, etc.
+
+The pins are grouped into up to 5 individual pin banks which need to be
+defined as gpio sub-nodes of the pinmux controller.
+
+Required properties for iomux controller:
+  - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
+                      "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
+                      "rockchip,rk3288-pinctrl"
+  - rockchip,grf: phandle referencing a syscon providing the
+        "general register files"
+
+Optional properties for iomux controller:
+  - rockchip,pmu: phandle referencing a syscon providing the pmu registers
+        as some SoCs carry parts of the iomux controller registers there.
+        Required for at least rk3188 and rk3288.
+
+Deprecated properties for iomux controller:
+  - reg: first element is the general register space of the iomux controller
+        It should be large enough to contain also separate pull registers.
+        second element is the separate pull register space of the rk3188.
+        Use rockchip,grf and rockchip,pmu described above instead.
+
+Required properties for gpio sub nodes:
+  - compatible: "rockchip,gpio-bank"
+  - reg: register of the gpio bank (different than the iomux registerset)
+  - interrupts: base interrupt of the gpio bank in the interrupt controller
+  - clocks: clock that drives this bank
+  - gpio-controller: identifies the node as a gpio controller and pin bank.
+  - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
+    binding is used, the amount of cells must be specified as 2. See generic
+    GPIO binding documentation for description of particular cells.
+  - interrupt-controller: identifies the controller node as interrupt-parent.
+  - #interrupt-cells: the value of this property should be 2 and the interrupt
+    cells should use the standard two-cell scheme described in
+    bindings/interrupt-controller/interrupts.txt
+
+Deprecated properties for gpio sub nodes:
+  - compatible: "rockchip,rk3188-gpio-bank0"
+  - reg: second element: separate pull register for rk3188 bank0, use
+        rockchip,pmu described above instead
+
+Required properties for pin configuration node:
+  - rockchip,pins: 3 integers array, represents a group of pins mux and config
+    setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
+    The MUX 0 means gpio and MUX 1 to N mean the specific device function.
+    The phandle of a node containing the generic pinconfig options
+    to use, as described in pinctrl-bindings.txt in this directory.
+
+Examples:
+
+#include <dt-bindings/pinctrl/rockchip.h>
+
+...
+
+pinctrl@20008000 {
+       compatible = "rockchip,rk3066a-pinctrl";
+       rockchip,grf = <&grf>;
+
+       #address-cells = <1>;
+       #size-cells = <1>;
+       ranges;
+
+       gpio0: gpio0@20034000 {
+               compatible = "rockchip,gpio-bank";
+               reg = <0x20034000 0x100>;
+               interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&clk_gates8 9>;
+
+               gpio-controller;
+               #gpio-cells = <2>;
+
+               interrupt-controller;
+               #interrupt-cells = <2>;
+       };
+
+       ...
+
+       pcfg_pull_default: pcfg_pull_default {
+               bias-pull-pin-default
+       };
+
+       uart2 {
+               uart2_xfer: uart2-xfer {
+                       rockchip,pins = <RK_GPIO1 8 1 &pcfg_pull_default>,
+                                       <RK_GPIO1 9 1 &pcfg_pull_default>;
+               };
+       };
+};
+
+uart2: serial@20064000 {
+       compatible = "snps,dw-apb-uart";
+       reg = <0x20064000 0x400>;
+       interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+       reg-shift = <2>;
+       reg-io-width = <1>;
+       clocks = <&mux_uart2>;
+       status = "okay";
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart2_xfer>;
+};
+
+Example for rk3188:
+
+       pinctrl@20008000 {
+               compatible = "rockchip,rk3188-pinctrl";
+               rockchip,grf = <&grf>;
+               rockchip,pmu = <&pmu>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               gpio0: gpio0@0x2000a000 {
+                       compatible = "rockchip,rk3188-gpio-bank0";
+                       reg = <0x2000a000 0x100>;
+                       interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk_gates8 9>;
+
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               gpio1: gpio1@0x2003c000 {
+                       compatible = "rockchip,gpio-bank";
+                       reg = <0x2003c000 0x100>;
+                       interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk_gates8 10>;
+
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
+               ...
+
+       };

diff --git a/doc/device-tree-bindings/thermal/rockchip-thermal.txt b/doc/device-tree-bindings/thermal/rockchip-thermal.txt
new file mode 100644 (file)
index 0000000..ef802de
--- /dev/null
+++ b/doc/device-tree-bindings/thermal/rockchip-thermal.txt
@@ -0,0 +1,68 @@
+* Temperature Sensor ADC (TSADC) on rockchip SoCs
+
+Required properties:
+- compatible : "rockchip,rk3288-tsadc"
+- reg : physical base address of the controller and length of memory mapped
+       region.
+- interrupts : The interrupt number to the cpu. The interrupt specifier format
+              depends on the interrupt controller.
+- clocks : Must contain an entry for each entry in clock-names.
+- clock-names : Shall be "tsadc" for the converter-clock, and "apb_pclk" for
+               the peripheral clock.
+- resets : Must contain an entry for each entry in reset-names.
+          See ../reset/reset.txt for details.
+- reset-names : Must include the name "tsadc-apb".
+- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description.
+- rockchip,hw-tshut-temp : The hardware-controlled shutdown temperature value.
+- rockchip,hw-tshut-mode : The hardware-controlled shutdown mode 0:CRU 1:GPIO.
+- rockchip,hw-tshut-polarity : The hardware-controlled active polarity 0:LOW
+                              1:HIGH.
+
+Exiample:
+tsadc: tsadc@ff280000 {
+       compatible = "rockchip,rk3288-tsadc";
+       reg = <0xff280000 0x100>;
+       interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+       clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
+       clock-names = "tsadc", "apb_pclk";
+       resets = <&cru SRST_TSADC>;
+       reset-names = "tsadc-apb";
+       pinctrl-names = "default";
+       pinctrl-0 = <&otp_out>;
+       #thermal-sensor-cells = <1>;
+       rockchip,hw-tshut-temp = <95000>;
+       rockchip,hw-tshut-mode = <0>;
+       rockchip,hw-tshut-polarity = <0>;
+};
+
+Example: referring to thermal sensors:
+thermal-zones {
+       cpu_thermal: cpu_thermal {
+               polling-delay-passive = <1000>; /* milliseconds */
+               polling-delay = <5000>; /* milliseconds */
+
+               /* sensor       ID */
+               thermal-sensors = <&tsadc       1>;
+
+               trips {
+                       cpu_alert0: cpu_alert {
+                               temperature = <70000>; /* millicelsius */
+                               hysteresis = <2000>; /* millicelsius */
+                               type = "passive";
+                       };
+                       cpu_crit: cpu_crit {
+                               temperature = <90000>; /* millicelsius */
+                               hysteresis = <2000>; /* millicelsius */
+                               type = "critical";
+                       };
+               };
+
+               cooling-maps {
+                       map0 {
+                               trip = <&cpu_alert0>;
+                               cooling-device =
+                                   <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                       };
+               };
+       };
+};

diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
new file mode 100644 (file)
index 0000000..216eee5
--- /dev/null
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -0,0 +1,370 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/* core clocks */
+#define PLL_APLL               1
+#define PLL_DPLL               2
+#define PLL_CPLL               3
+#define PLL_GPLL               4
+#define PLL_NPLL               5
+#define ARMCLK                 6
+
+/* sclk gates (special clocks) */
+#define SCLK_GPU               64
+#define SCLK_SPI0              65
+#define SCLK_SPI1              66
+#define SCLK_SPI2              67
+#define SCLK_SDMMC             68
+#define SCLK_SDIO0             69
+#define SCLK_SDIO1             70
+#define SCLK_EMMC              71
+#define SCLK_TSADC             72
+#define SCLK_SARADC            73
+#define SCLK_PS2C              74
+#define SCLK_NANDC0            75
+#define SCLK_NANDC1            76
+#define SCLK_UART0             77
+#define SCLK_UART1             78
+#define SCLK_UART2             79
+#define SCLK_UART3             80
+#define SCLK_UART4             81
+#define SCLK_I2S0              82
+#define SCLK_SPDIF             83
+#define SCLK_SPDIF8CH          84
+#define SCLK_TIMER0            85
+#define SCLK_TIMER1            86
+#define SCLK_TIMER2            87
+#define SCLK_TIMER3            88
+#define SCLK_TIMER4            89
+#define SCLK_TIMER5            90
+#define SCLK_TIMER6            91
+#define SCLK_HSADC             92
+#define SCLK_OTGPHY0           93
+#define SCLK_OTGPHY1           94
+#define SCLK_OTGPHY2           95
+#define SCLK_OTG_ADP           96
+#define SCLK_HSICPHY480M       97
+#define SCLK_HSICPHY12M                98
+#define SCLK_MACREF            99
+#define SCLK_LCDC_PWM0         100
+#define SCLK_LCDC_PWM1         101
+#define SCLK_MAC_RX            102
+#define SCLK_MAC_TX            103
+#define SCLK_EDP_24M           104
+#define SCLK_EDP               105
+#define SCLK_RGA               106
+#define SCLK_ISP               107
+#define SCLK_ISP_JPE           108
+#define SCLK_HDMI_HDCP         109
+#define SCLK_HDMI_CEC          110
+#define SCLK_HEVC_CABAC                111
+#define SCLK_HEVC_CORE         112
+#define SCLK_I2S0_OUT          113
+#define SCLK_SDMMC_DRV         114
+#define SCLK_SDIO0_DRV         115
+#define SCLK_SDIO1_DRV         116
+#define SCLK_EMMC_DRV          117
+#define SCLK_SDMMC_SAMPLE      118
+#define SCLK_SDIO0_SAMPLE      119
+#define SCLK_SDIO1_SAMPLE      120
+#define SCLK_EMMC_SAMPLE       121
+#define SCLK_USBPHY480M_SRC    122
+#define SCLK_PVTM_CORE         123
+#define SCLK_PVTM_GPU          124
+
+#define SCLK_MAC               151
+#define SCLK_MACREF_OUT                152
+
+#define DCLK_VOP0              190
+#define DCLK_VOP1              191
+
+/* aclk gates */
+#define ACLK_GPU               192
+#define ACLK_DMAC1             193
+#define ACLK_DMAC2             194
+#define ACLK_MMU               195
+#define ACLK_GMAC              196
+#define ACLK_VOP0              197
+#define ACLK_VOP1              198
+#define ACLK_CRYPTO            199
+#define ACLK_RGA               200
+#define ACLK_RGA_NIU           201
+#define ACLK_IEP               202
+#define ACLK_VIO0_NIU          203
+#define ACLK_VIP               204
+#define ACLK_ISP               205
+#define ACLK_VIO1_NIU          206
+#define ACLK_HEVC              207
+#define ACLK_VCODEC            208
+#define ACLK_CPU               209
+#define ACLK_PERI              210
+
+/* pclk gates */
+#define PCLK_GPIO0             320
+#define PCLK_GPIO1             321
+#define PCLK_GPIO2             322
+#define PCLK_GPIO3             323
+#define PCLK_GPIO4             324
+#define PCLK_GPIO5             325
+#define PCLK_GPIO6             326
+#define PCLK_GPIO7             327
+#define PCLK_GPIO8             328
+#define PCLK_GRF               329
+#define PCLK_SGRF              330
+#define PCLK_PMU               331
+#define PCLK_I2C0              332
+#define PCLK_I2C1              333
+#define PCLK_I2C2              334
+#define PCLK_I2C3              335
+#define PCLK_I2C4              336
+#define PCLK_I2C5              337
+#define PCLK_SPI0              338
+#define PCLK_SPI1              339
+#define PCLK_SPI2              340
+#define PCLK_UART0             341
+#define PCLK_UART1             342
+#define PCLK_UART2             343
+#define PCLK_UART3             344
+#define PCLK_UART4             345
+#define PCLK_TSADC             346
+#define PCLK_SARADC            347
+#define PCLK_SIM               348
+#define PCLK_GMAC              349
+#define PCLK_PWM               350
+#define PCLK_RKPWM             351
+#define PCLK_PS2C              352
+#define PCLK_TIMER             353
+#define PCLK_TZPC              354
+#define PCLK_EDP_CTRL          355
+#define PCLK_MIPI_DSI0         356
+#define PCLK_MIPI_DSI1         357
+#define PCLK_MIPI_CSI          358
+#define PCLK_LVDS_PHY          359
+#define PCLK_HDMI_CTRL         360
+#define PCLK_VIO2_H2P          361
+#define PCLK_CPU               362
+#define PCLK_PERI              363
+#define PCLK_DDRUPCTL0         364
+#define PCLK_PUBL0             365
+#define PCLK_DDRUPCTL1         366
+#define PCLK_PUBL1             367
+#define PCLK_WDT               368
+
+/* hclk gates */
+#define HCLK_GPS               448
+#define HCLK_OTG0              449
+#define HCLK_USBHOST0          450
+#define HCLK_USBHOST1          451
+#define HCLK_HSIC              452
+#define HCLK_NANDC0            453
+#define HCLK_NANDC1            454
+#define HCLK_TSP               455
+#define HCLK_SDMMC             456
+#define HCLK_SDIO0             457
+#define HCLK_SDIO1             458
+#define HCLK_EMMC              459
+#define HCLK_HSADC             460
+#define HCLK_CRYPTO            461
+#define HCLK_I2S0              462
+#define HCLK_SPDIF             463
+#define HCLK_SPDIF8CH          464
+#define HCLK_VOP0              465
+#define HCLK_VOP1              466
+#define HCLK_ROM               467
+#define HCLK_IEP               468
+#define HCLK_ISP               469
+#define HCLK_RGA               470
+#define HCLK_VIO_AHB_ARBI      471
+#define HCLK_VIO_NIU           472
+#define HCLK_VIP               473
+#define HCLK_VIO2_H2P          474
+#define HCLK_HEVC              475
+#define HCLK_VCODEC            476
+#define HCLK_CPU               477
+#define HCLK_PERI              478
+
+#define CLK_NR_CLKS            (HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0             0
+#define SRST_CORE1             1
+#define SRST_CORE2             2
+#define SRST_CORE3             3
+#define SRST_CORE0_PO          4
+#define SRST_CORE1_PO          5
+#define SRST_CORE2_PO          6
+#define SRST_CORE3_PO          7
+#define SRST_PDCORE_STRSYS     8
+#define SRST_PDBUS_STRSYS      9
+#define SRST_L2C               10
+#define SRST_TOPDBG            11
+#define SRST_CORE0_DBG         12
+#define SRST_CORE1_DBG         13
+#define SRST_CORE2_DBG         14
+#define SRST_CORE3_DBG         15
+
+#define SRST_PDBUG_AHB_ARBITOR 16
+#define SRST_EFUSE256          17
+#define SRST_DMAC1             18
+#define SRST_INTMEM            19
+#define SRST_ROM               20
+#define SRST_SPDIF8CH          21
+#define SRST_TIMER             22
+#define SRST_I2S0              23
+#define SRST_SPDIF             24
+#define SRST_TIMER0            25
+#define SRST_TIMER1            26
+#define SRST_TIMER2            27
+#define SRST_TIMER3            28
+#define SRST_TIMER4            29
+#define SRST_TIMER5            30
+#define SRST_EFUSE             31
+
+#define SRST_GPIO0             32
+#define SRST_GPIO1             33
+#define SRST_GPIO2             34
+#define SRST_GPIO3             35
+#define SRST_GPIO4             36
+#define SRST_GPIO5             37
+#define SRST_GPIO6             38
+#define SRST_GPIO7             39
+#define SRST_GPIO8             40
+#define SRST_I2C0              42
+#define SRST_I2C1              43
+#define SRST_I2C2              44
+#define SRST_I2C3              45
+#define SRST_I2C4              46
+#define SRST_I2C5              47
+
+#define SRST_DWPWM             48
+#define SRST_MMC_PERI          49
+#define SRST_PERIPH_MMU                50
+#define SRST_DAP               51
+#define SRST_DAP_SYS           52
+#define SRST_TPIU              53
+#define SRST_PMU_APB           54
+#define SRST_GRF               55
+#define SRST_PMU               56
+#define SRST_PERIPH_AXI                57
+#define SRST_PERIPH_AHB                58
+#define SRST_PERIPH_APB                59
+#define SRST_PERIPH_NIU                60
+#define SRST_PDPERI_AHB_ARBI   61
+#define SRST_EMEM              62
+#define SRST_USB_PERI          63
+
+#define SRST_DMAC2             64
+#define SRST_MAC               66
+#define SRST_GPS               67
+#define SRST_RKPWM             69
+#define SRST_CCP               71
+#define SRST_USBHOST0          72
+#define SRST_HSIC              73
+#define SRST_HSIC_AUX          74
+#define SRST_HSIC_PHY          75
+#define SRST_HSADC             76
+#define SRST_NANDC0            77
+#define SRST_NANDC1            78
+
+#define SRST_TZPC              80
+#define SRST_SPI0              83
+#define SRST_SPI1              84
+#define SRST_SPI2              85
+#define SRST_SARADC            87
+#define SRST_PDALIVE_NIU       88
+#define SRST_PDPMU_INTMEM      89
+#define SRST_PDPMU_NIU         90
+#define SRST_SGRF              91
+
+#define SRST_VIO_ARBI          96
+#define SRST_RGA_NIU           97
+#define SRST_VIO0_NIU_AXI      98
+#define SRST_VIO_NIU_AHB       99
+#define SRST_LCDC0_AXI         100
+#define SRST_LCDC0_AHB         101
+#define SRST_LCDC0_DCLK                102
+#define SRST_VIO1_NIU_AXI      103
+#define SRST_VIP               104
+#define SRST_RGA_CORE          105
+#define SRST_IEP_AXI           106
+#define SRST_IEP_AHB           107
+#define SRST_RGA_AXI           108
+#define SRST_RGA_AHB           109
+#define SRST_ISP               110
+#define SRST_EDP               111
+
+#define SRST_VCODEC_AXI                112
+#define SRST_VCODEC_AHB                113
+#define SRST_VIO_H2P           114
+#define SRST_MIPIDSI0          115
+#define SRST_MIPIDSI1          116
+#define SRST_MIPICSI           117
+#define SRST_LVDS_PHY          118
+#define SRST_LVDS_CON          119
+#define SRST_GPU               120
+#define SRST_HDMI              121
+#define SRST_CORE_PVTM         124
+#define SRST_GPU_PVTM          125
+
+#define SRST_MMC0              128
+#define SRST_SDIO0             129
+#define SRST_SDIO1             130
+#define SRST_EMMC              131
+#define SRST_USBOTG_AHB                132
+#define SRST_USBOTG_PHY                133
+#define SRST_USBOTG_CON                134
+#define SRST_USBHOST0_AHB      135
+#define SRST_USBHOST0_PHY      136
+#define SRST_USBHOST0_CON      137
+#define SRST_USBHOST1_AHB      138
+#define SRST_USBHOST1_PHY      139
+#define SRST_USBHOST1_CON      140
+#define SRST_USB_ADP           141
+#define SRST_ACC_EFUSE         142
+
+#define SRST_CORESIGHT         144
+#define SRST_PD_CORE_AHB_NOC   145
+#define SRST_PD_CORE_APB_NOC   146
+#define SRST_PD_CORE_MP_AXI    147
+#define SRST_GIC               148
+#define SRST_LCDC_PWM0         149
+#define SRST_LCDC_PWM1         150
+#define SRST_VIO0_H2P_BRG      151
+#define SRST_VIO1_H2P_BRG      152
+#define SRST_RGA_H2P_BRG       153
+#define SRST_HEVC              154
+#define SRST_TSADC             159
+
+#define SRST_DDRPHY0           160
+#define SRST_DDRPHY0_APB       161
+#define SRST_DDRCTRL0          162
+#define SRST_DDRCTRL0_APB      163
+#define SRST_DDRPHY0_CTRL      164
+#define SRST_DDRPHY1           165
+#define SRST_DDRPHY1_APB       166
+#define SRST_DDRCTRL1          167
+#define SRST_DDRCTRL1_APB      168
+#define SRST_DDRPHY1_CTRL      169
+#define SRST_DDRMSCH0          170
+#define SRST_DDRMSCH1          171
+#define SRST_CRYPTO            174
+#define SRST_C2C_HOST          175
+
+#define SRST_LCDC1_AXI         176
+#define SRST_LCDC1_AHB         177
+#define SRST_LCDC1_DCLK                178
+#define SRST_UART0             179
+#define SRST_UART1             180
+#define SRST_UART2             181
+#define SRST_UART3             182
+#define SRST_UART4             183
+#define SRST_SIMC              186
+#define SRST_PS2C              187
+#define SRST_TSP               188
+#define SRST_TSP_CLKIN0                189
+#define SRST_TSP_CLKIN1                190
+#define SRST_TSP_27M           191

diff --git a/include/dt-bindings/clock/rockchip,rk808.h b/include/dt-bindings/clock/rockchip,rk808.h
new file mode 100644 (file)
index 0000000..1a87343
--- /dev/null
+++ b/include/dt-bindings/clock/rockchip,rk808.h
@@ -0,0 +1,11 @@
+/*
+ * This header provides constants clk index RK808 pmic clkout
+ */
+#ifndef _CLK_ROCKCHIP_RK808
+#define _CLK_ROCKCHIP_RK808
+
+/* CLOCKOUT index */
+#define RK808_CLKOUT0          0
+#define RK808_CLKOUT1          1
+
+#endif

diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h
new file mode 100644 (file)
index 0000000..56887e1
--- /dev/null
+++ b/include/dt-bindings/pinctrl/rockchip.h
@@ -0,0 +1,26 @@
+/*
+ * Header providing constants for Rockchip pinctrl bindings.
+ *
+ * Copyright (c) 2013 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_H__
+#define __DT_BINDINGS_ROCKCHIP_PINCTRL_H__
+
+#define RK_GPIO0       0
+#define RK_GPIO1       1
+#define RK_GPIO2       2
+#define RK_GPIO3       3
+#define RK_GPIO4       4
+#define RK_GPIO6       6
+
+#define RK_FUNC_GPIO   0
+#define RK_FUNC_1      1
+#define RK_FUNC_2      2
+#define RK_FUNC_3      3
+#define RK_FUNC_4      4
+
+#endif

diff --git a/include/dt-bindings/power-domain/rk3288.h b/include/dt-bindings/power-domain/rk3288.h
new file mode 100644 (file)
index 0000000..ca68c11
--- /dev/null
+++ b/include/dt-bindings/power-domain/rk3288.h
@@ -0,0 +1,11 @@
+#ifndef __DT_BINDINGS_POWER_DOMAIN_RK3288_H__
+#define __DT_BINDINGS_POWER_DOMAIN_RK3288_H__
+
+/* RK3288 power domain index */
+#define RK3288_PD_GPU          0
+#define RK3288_PD_VIO          1
+#define RK3288_PD_VIDEO        2
+#define RK3288_PD_HEVC         3
+#define RK3288_PD_PERI         4
+
+#endif