]> git.karo-electronics.de Git - karo-tx-uboot.git/commitdiff
Merge branch 'master' of git://git.denx.de/u-boot
authorStefano Babic <sbabic@denx.de>
Tue, 30 Dec 2014 12:04:09 +0000 (13:04 +0100)
committerStefano Babic <sbabic@denx.de>
Tue, 30 Dec 2014 12:04:38 +0000 (13:04 +0100)
Signed-off-by: Stefano Babic <sbabic@denx.de>
arch/arm/cpu/armv7/mx6/clock.c
board/freescale/mx51evk/mx51evk.c
board/freescale/mx6qarm2/mx6qarm2.c
board/freescale/mx6sabresd/mx6sabresd.c
board/gateworks/gw_ventana/gw_ventana_spl.c
board/olimex/mx23_olinuxino/mx23_olinuxino.c
board/olimex/mx23_olinuxino/spl_boot.c
include/configs/mx6qarm2.h
include/configs/mx6sabresd.h
include/configs/ot1200.h

index 93a02adcec4d843e68196903f891cccaddb566ab..b6983e60d7363fa03752ffd7b821b60e8dd917c1 100644 (file)
@@ -746,10 +746,11 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
        case MXC_SATA_CLK:
                return get_ahb_clk();
        default:
+               printf("Unsupported MXC CLK: %d\n", clk);
                break;
        }
 
-       return -1;
+       return 0;
 }
 
 /*
index f1e5eb433a3b9ec4f3ec195e5d26462f6b8c4d11..c7c21f392bbbdd78b9acb44651ef6b4083ce750a 100644 (file)
@@ -112,7 +112,7 @@ static void setup_iomux_spi(void)
 #ifdef CONFIG_USB_EHCI_MX5
 #define MX51EVK_USBH1_HUB_RST  IMX_GPIO_NR(1, 7)
 #define MX51EVK_USBH1_STP      IMX_GPIO_NR(1, 27)
-#define MX51EVK_USB_CLK_EN_B   IMX_GPIO_NR(2, 2)
+#define MX51EVK_USB_CLK_EN_B   IMX_GPIO_NR(2, 1)
 #define MX51EVK_USB_PHY_RESET  IMX_GPIO_NR(2, 5)
 
 static void setup_usb_h1(void)
index 3a5b26dde747a318e648816d4b6b183541700e5b..98ccdb785b3498fa15406f628e84cbbd1da859aa 100644 (file)
@@ -16,6 +16,7 @@
 #include <fsl_esdhc.h>
 #include <miiphy.h>
 #include <netdev.h>
+#include <usb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -213,6 +214,43 @@ int board_eth_init(bd_t *bis)
        return 0;
 }
 
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET   0x800
+#define UCTRL_PWR_POL          (1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+       MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+       MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_usb(void)
+{
+       imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+                                        ARRAY_SIZE(usb_otg_pads));
+
+       /*
+        * set daisy chain for otg_pin_id on 6q.
+        * for 6dl, this bit is reserved
+        */
+       imx_iomux_set_gpr_register(1, 13, 1, 1);
+}
+
+int board_ehci_hcd_init(int port)
+{
+       u32 *usbnc_usb_ctrl;
+
+       if (port > 0)
+               return -EINVAL;
+
+       usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+                                port * 4);
+
+       setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+       return 0;
+}
+#endif
+
 int board_early_init_f(void)
 {
        setup_iomux_uart();
@@ -226,6 +264,10 @@ int board_init(void)
        /* address of boot parameters */
        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+#ifdef CONFIG_USB_EHCI_MX6
+       setup_usb();
+#endif
+
        return 0;
 }
 
index ac3757f074425a1403d0d2e4f8d7405bb39b05c9..2f7198d3bfdfc0b438ec185973d62dcb3dc45156 100644 (file)
@@ -29,6 +29,7 @@
 #include <power/pfuze100_pmic.h>
 #include "../common/pfuze.h"
 #include <asm/arch/mx6-ddr.h>
+#include <usb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -537,6 +538,69 @@ int board_eth_init(bd_t *bis)
        return cpu_eth_init(bis);
 }
 
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET   0x800
+#define UCTRL_PWR_POL          (1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+       MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+       MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usb_hc1_pads[] = {
+       MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_usb(void)
+{
+       imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+                                        ARRAY_SIZE(usb_otg_pads));
+
+       /*
+        * set daisy chain for otg_pin_id on 6q.
+        * for 6dl, this bit is reserved
+        */
+       imx_iomux_set_gpr_register(1, 13, 1, 0);
+
+       imx_iomux_v3_setup_multiple_pads(usb_hc1_pads,
+                                        ARRAY_SIZE(usb_hc1_pads));
+}
+
+int board_ehci_hcd_init(int port)
+{
+       u32 *usbnc_usb_ctrl;
+
+       if (port > 1)
+               return -EINVAL;
+
+       usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+                                port * 4);
+
+       setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+       return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+       switch (port) {
+       case 0:
+               break;
+       case 1:
+               if (on)
+                       gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
+               else
+                       gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
+               break;
+       default:
+               printf("MXC USB port %d not yet supported\n", port);
+               return -EINVAL;
+       }
+
+       return 0;
+}
+#endif
+
 int board_early_init_f(void)
 {
        setup_iomux_uart();
@@ -557,6 +621,10 @@ int board_init(void)
 #endif
        setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 
+#ifdef CONFIG_USB_EHCI_MX6
+       setup_usb();
+#endif
+
        return 0;
 }
 
index d6a584745bd168edc8e57a8cadd869c3a9351dd6..97128127fbe741f2393faeba06d1c4ff40a23238 100644 (file)
@@ -401,7 +401,7 @@ static void ccgr_init(void)
        writel(0x0030FC03, &ccm->CCGR1);
        writel(0x0FFFC000, &ccm->CCGR2);
        writel(0x3FF00000, &ccm->CCGR3);
-       writel(0x00FFF300, &ccm->CCGR4);
+       writel(0xFFFFF300, &ccm->CCGR4);        /* enable NAND/GPMI/BCH clks */
        writel(0x0F0000C3, &ccm->CCGR5);
        writel(0x000003FF, &ccm->CCGR6);
 }
index 313ab20e26ea734e5e2fa76c7c0aae9af1faa21d..65cbbf15b73194ec15311c288f17e7c23cf3dbc4 100644 (file)
@@ -78,33 +78,3 @@ int board_init(void)
 
        return 0;
 }
-
-/* Fine-tune the DRAM configuration. */
-void mxs_adjust_memory_params(uint32_t *dram_vals)
-{
-       /* Enable Auto Precharge. */
-       dram_vals[3] |= 1 << 8;
-       /* Enable Fast Writes. */
-       dram_vals[5] |= 1 << 8;
-       /* tEMRS = 3*tCK */
-       dram_vals[10] &= ~(0x3 << 8);
-       dram_vals[10] |= (0x3 << 8);
-       /* CASLAT = 3*tCK */
-       dram_vals[11] &= ~(0x3 << 0);
-       dram_vals[11] |= (0x3 << 0);
-       /* tCKE = 1*tCK */
-       dram_vals[12] &= ~(0x7 << 0);
-       dram_vals[12] |= (0x1 << 0);
-       /* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */
-       dram_vals[13] &= ~((0xf << 16) | (0xf << 24) | (0xf << 0));
-       dram_vals[13] |= (0x6 << 16) | (0x6 << 24) | (0x2 << 0);
-       /* tDAL = 6*tCK */
-       dram_vals[15] &= ~(0xf << 16);
-       dram_vals[15] |= (0x6 << 16);
-       /* tREF = 1040*tCK */
-       dram_vals[26] &= ~0xffff;
-       dram_vals[26] |= 0x0410;
-       /* tRAS_MAX = 9334*tCK */
-       dram_vals[32] &= ~0xffff;
-       dram_vals[32] |= 0x2475;
-}
index 5272dfa4e676dbb5e2296f45df6494458083929d..de3b0e4c8b0d9153324539a0c5436af8ebcc6e3a 100644 (file)
@@ -89,3 +89,33 @@ void board_init_ll(const uint32_t arg, const uint32_t *resptr)
 {
        mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
 }
+
+/* Fine-tune the DRAM configuration. */
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+       /* Enable Auto Precharge. */
+       dram_vals[3] |= 1 << 8;
+       /* Enable Fast Writes. */
+       dram_vals[5] |= 1 << 8;
+       /* tEMRS = 3*tCK */
+       dram_vals[10] &= ~(0x3 << 8);
+       dram_vals[10] |= (0x3 << 8);
+       /* CASLAT = 3*tCK */
+       dram_vals[11] &= ~(0x3 << 0);
+       dram_vals[11] |= (0x3 << 0);
+       /* tCKE = 1*tCK */
+       dram_vals[12] &= ~(0x7 << 0);
+       dram_vals[12] |= (0x1 << 0);
+       /* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */
+       dram_vals[13] &= ~((0xf << 16) | (0xf << 24) | (0xf << 0));
+       dram_vals[13] |= (0x6 << 16) | (0x6 << 24) | (0x2 << 0);
+       /* tDAL = 6*tCK */
+       dram_vals[15] &= ~(0xf << 16);
+       dram_vals[15] |= (0x6 << 16);
+       /* tREF = 1040*tCK */
+       dram_vals[26] &= ~0xffff;
+       dram_vals[26] |= 0x0410;
+       /* tRAS_MAX = 9334*tCK */
+       dram_vals[32] &= ~0xffff;
+       dram_vals[32] |= 0x2475;
+}
index 6e01fa0435a09087ee57bd54b611a6fb6dece922..76cfef123cd13d5adc5f2b51579eb5023980c3c4 100644 (file)
 #define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ
 
+/* USB Configs */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC          (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS           0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT        1
+#endif
+
 #endif                         /* __CONFIG_H */
index a346542130d69fa33daf9b484b3221a6c08d7bd5..99d9d4d7cfbf5a5c54de344f7fec4ec84c92fa89 100644 (file)
 #define CONFIG_POWER_PFUZE100
 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
 
+/* USB Configs */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC          (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS           0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT        1 /* Enabled USB controller number */
+#endif
+
 #endif                         /* __MX6QSABRESD_CONFIG_H */
index 9512b1e15055411ff8904f61b6e620475c779a56..255c933baa4be2a2440e831f7fdbe97ee32627bd 100644 (file)
@@ -85,6 +85,7 @@
 
 /* USB Configs */
 #define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
 #define CONFIG_MXC_USB_PORTSC   (PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_CMD_EXT4
 #define CONFIG_DOS_PARTITION
 #define CONFIG_CMD_FS_GENERIC
+#define CONFIG_LIB_UUID
+#define CONFIG_CMD_FS_UUID
 
 #define CONFIG_BOOTP_SERVERIP
 #define CONFIG_BOOTP_BOOTFILE