+++ /dev/null
-/*
- * (C) Copyright 2005
- * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#include <libfdt_env.h>
-#include <fdt_support.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */
- /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */
- /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
- /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
- /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
- /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
- /* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */
-#if defined(CONFIG_SYS_I2C_SOFT)
- /* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */
- /* PA23 */ { 1, 0, 0, 1, 1, 1 }, /* I2C_SCL2 */
-#else /* normal I/O port pins */
- /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */
- /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */
-#endif
- /* PA22 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DCD */
- /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
- /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
- /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
- /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
- /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
- /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */
- /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
- /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
- /* PA13 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_RTS */
- /* PA12 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_CTS */
- /* PA11 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_DTR */
- /* PA10 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DSR */
- /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
- /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
- /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
- /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
- /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
- /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
- /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
- /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
- /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
- /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
- /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
- /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
- /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
- /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
- /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CLSN */
- /* PC28 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_OUT */
- /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
- /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_IN */
- /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
- /* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
- /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
- /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
- /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
- /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
- /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
- /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
- /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */
- /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */
- /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
- /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
- /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
- /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
- /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
- /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 1, 0, 0, 0, 0 }, /* SCC3_RX */
- /* PD24 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_TX */
- /* PD23 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_RTS */
- /* PD22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC4_RXD */
- /* PD21 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_TXD */
- /* PD20 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_RTS */
- /* PD19 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_SEL */
- /* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_CLK */
- /* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MOSI */
- /* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MISO */
-#if defined(CONFIG_HARD_I2C)
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA1 */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL1 */
-#else /* normal I/O port pins */
- /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* PD15 */
- /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* PD14 */
-#endif
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
- /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
- /* PD7 */ { 1, 0, 0, 1, 0, 1 }, /* MII_MDIO */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-/* ------------------------------------------------------------------------- */
-
-/* Check Board Identity:
- */
-int checkboard (void)
-{
- puts ("Board: IDS 8247\n");
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
- *
- * This routine performs standard 8260 initialization sequence
- * and calculates the available memory size. It may be called
- * several times to try different SDRAM configurations on both
- * 60x and local buses.
- */
-static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
- ulong orx, volatile uchar * base)
-{
- volatile uchar c = 0xff;
- volatile uint *sdmr_ptr;
- volatile uint *orx_ptr;
- ulong maxsize, size;
- int i;
-
- /* We must be able to test a location outsize the maximum legal size
- * to find out THAT we are outside; but this address still has to be
- * mapped by the controller. That means, that the initial mapping has
- * to be (at least) twice as large as the maximum expected size.
- */
- maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
-
- sdmr_ptr = &memctl->memc_psdmr;
- orx_ptr = &memctl->memc_or2;
-
- *orx_ptr = orx;
-
- /*
- * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
- *
- * "At system reset, initialization software must set up the
- * programmable parameters in the memory controller banks registers
- * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
- * system software should execute the following initialization sequence
- * for each SDRAM device.
- *
- * 1. Issue a PRECHARGE-ALL-BANKS command
- * 2. Issue eight CBR REFRESH commands
- * 3. Issue a MODE-SET command to initialize the mode register
- *
- * The initial commands are executed by setting P/LSDMR[OP] and
- * accessing the SDRAM with a single-byte transaction."
- *
- * The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
- */
-
- *sdmr_ptr = sdmr | PSDMR_OP_PREA;
- *base = c;
-
- *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
- *base = c;
-
- *sdmr_ptr = sdmr | PSDMR_OP_MRW;
- *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
-
- *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
- *base = c;
-
- size = get_ram_size((long *)base, maxsize);
- *orx_ptr = orx | ~(size - 1);
-
- return (size);
-}
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
-
- long psize;
-
- psize = 16 * 1024 * 1024;
-
- memctl->memc_psrt = CONFIG_SYS_PSRT;
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-#ifndef CONFIG_SYS_RAMBOOT
- /* 60x SDRAM setup:
- */
- psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR2,
- (uchar *) CONFIG_SYS_SDRAM_BASE);
-#endif /* CONFIG_SYS_RAMBOOT */
-
- icache_enable ();
-
- return (psize);
-}
-
-int misc_init_r (void)
-{
- gd->bd->bi_flashstart = 0xff800000;
- return 0;
-}
-
-#if defined(CONFIG_CMD_NAND)
-#include <nand.h>
-#include <linux/mtd/mtd.h>
-#include <asm/io.h>
-
-static u8 hwctl;
-
-static void ids_nand_hwctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- if ( ctrl & NAND_CLE ) {
- hwctl |= 0x1;
- writeb(0x00, (this->IO_ADDR_W + 0x0a));
- } else {
- hwctl &= ~0x1;
- writeb(0x00, (this->IO_ADDR_W + 0x08));
- }
- if ( ctrl & NAND_ALE ) {
- hwctl |= 0x2;
- writeb(0x00, (this->IO_ADDR_W + 0x09));
- } else {
- hwctl &= ~0x2;
- writeb(0x00, (this->IO_ADDR_W + 0x08));
- }
- if ( (ctrl & NAND_NCE) != NAND_NCE)
- writeb(0x00, (this->IO_ADDR_W + 0x0c));
- else
- writeb(0x00, (this->IO_ADDR_W + 0x08));
- }
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-
-}
-
-static u_char ids_nand_read_byte(struct mtd_info *mtd)
-{
- struct nand_chip *this = mtd->priv;
-
- return readb(this->IO_ADDR_R);
-}
-
-static void ids_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
- struct nand_chip *nand = mtd->priv;
- int i;
-
- for (i = 0; i < len; i++) {
- if (hwctl & 0x1)
- writeb(buf[i], (nand->IO_ADDR_W + 0x02));
- else if (hwctl & 0x2)
- writeb(buf[i], (nand->IO_ADDR_W + 0x01));
- else
- writeb(buf[i], nand->IO_ADDR_W);
- }
-}
-
-static void ids_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
-{
- struct nand_chip *this = mtd->priv;
- int i;
-
- for (i = 0; i < len; i++) {
- buf[i] = readb(this->IO_ADDR_R);
- }
-}
-
-static int ids_nand_dev_ready(struct mtd_info *mtd)
-{
- /* constant delay (see also tR in the datasheet) */
- udelay(12);
- return 1;
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
- nand->ecc.mode = NAND_ECC_SOFT;
-
- /* Reference hardware control function */
- nand->cmd_ctrl = ids_nand_hwctrl;
- nand->read_byte = ids_nand_read_byte;
- nand->write_buf = ids_nand_write_buf;
- nand->read_buf = ids_nand_read_buf;
- nand->dev_ready = ids_nand_dev_ready;
- nand->chip_delay = 12;
-
- return 0;
-}
-
-#endif /* CONFIG_CMD_NAND */
-
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-void ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup( blob, bd);
-}
-#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8272_FAMILY 1
-#define CONFIG_IDS8247 1
-#define CPU_ID_STR "MPC8247"
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_BOOTCOUNT_LIMIT
-
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw " \
- "console=ttyS0,115200\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "rootpath=/opt/eldk/ppc_82xx\0" \
- "bootfile=/tftpboot/IDS8247/uImage\0" \
- "kernel_addr=ff800000\0" \
- "ramdisk_addr=ffa00000\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#define CONFIG_MISC_INIT_R 1
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 400000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
-/*
- * Software (bit-bang) I2C driver configuration
- */
-
-#define I2C_PORT 0 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00000080)
-#define I2C_TRISTATE (iop->pdir &= ~0x00000080)
-#define I2C_READ ((iop->pdat & 0x00000080) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000080; \
- else iop->pdat &= ~0x00000080
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000100; \
- else iop->pdat &= ~0x00000100
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-
-#if 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-#define CONFIG_I2C_X
-#endif
-
-/*
- * select serial console configuration
- * use the extern UART for the console
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-
-#define CONFIG_SYS_NS16550_CLK 14745600
-
-#define CONFIG_SYS_UART_BASE 0xE0000000
-#define CONFIG_SYS_UART_SIZE 0x10000
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0x8000)
-
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_TBCLK (bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000"
-
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
-#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
-#undef CONFIG_ETHER_NONE /* define if ether on something else */
-#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
-#define CONFIG_ETHER_ON_FCC1
-#define FCC_ENET
-
-/*
- * - Rx-CLK is CLK10
- * - Tx-CLK is CLK9
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9)
-# define CONFIG_SYS_CPMFCR_RAMTYPE 0
-# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#define CONFIG_8260_CLKIN 66666666 /* in Hz */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#define CONFIG_RTC_PCF8563
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_FLASH_BANKS_LIST { 0xFF800000 }
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ids8247/config.mk
- * The main FLASH is whichever is connected to *CS0.
- */
-#define CONFIG_SYS_FLASH0_BASE 0xFFF00000
-#define CONFIG_SYS_FLASH0_SIZE 8
-
-/* Flash bank size (for preliminary settings)
- */
-#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-/* Environment in flash */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x60000)
-#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#if defined(CONFIG_CMD_NAND)
-
-#define CONFIG_SYS_NAND0_BASE 0xE1000000
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-
-#endif /* CONFIG_CMD_NAND */
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000)
-
-/* no slaves so just fill with zeros */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- *
- * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-
-#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
-#define CONFIG_SYS_HID0_FINAL 0
-#define CONFIG_SYS_HID2 0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR 0
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration 4-25
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_BCR 0
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 4-31
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01)
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control 9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR (0x00000028 | SCCR_DFBRG01)
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration 13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR 0
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus Machine PortSz Device
- * ---- --- ------- ------ ------
- * 0 60x GPCM 16 bit FLASH
- * 1 60x GPCM 8 bit NAND
- * 2 60x SDRAM 32 bit SDRAM
- * 3 60x GPCM 8 bit UART
- *
- */
-
-#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
-
-/* Minimum mask to separate preliminary
- * address ranges for CS[0:2]
- */
-#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (32<<20) /* less than 32 MB */
-
-#define CONFIG_SYS_MPTPR 0x6600
-
-/*-----------------------------------------------------------------------------
- * Address for Mode Register Set (MRS) command
- *-----------------------------------------------------------------------------
- */
-#define CONFIG_SYS_MRS_OFFS 0x00000110
-
-
-/* Bank 0 - FLASH
- */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
- ORxG_SCY_6_CLK )
-
-#if defined(CONFIG_CMD_NAND)
-/* Bank 1 - NAND Flash
-*/
-#define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND0_BASE
-#define CONFIG_SYS_NAND_SIZE 0x8000
-
-#define CONFIG_SYS_OR_TIMING_NAND 0x000036
-
-#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )
-#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | CONFIG_SYS_OR_TIMING_NAND )
-#endif
-
-/* Bank 2 - 60x bus SDRAM
- */
-#define CONFIG_SYS_PSRT 0x20
-#define CONFIG_SYS_LSRT 0x20
-
-#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
- BRx_PS_32 |\
- BRx_MS_SDRAM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2
-
-
-/* SDRAM initialization values
-*/
-#define CONFIG_SYS_OR2 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI0_A9 |\
- ORxS_NUMR_12)
-
-#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\
- PSDMR_BSMA_A15_A17 |\
- PSDMR_SDA10_PBI0_A10 |\
- PSDMR_RFRC_5_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_BL |\
- PSDMR_LDOTOPRE_2C |\
- PSDMR_WRC_3C |\
- PSDMR_CL_3)
-
-/* Bank 3 - UART
-*/
-
-#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )
-#define CONFIG_SYS_OR3_PRELIM (((-CONFIG_SYS_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX )
-
-#endif /* __CONFIG_H */
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