SYM_PREFIX = _
+LDR_FLAGS += -J
LDR_FLAGS += --bmode $(subst BFIN_BOOT_,,$(CONFIG_BFIN_BOOT_MODE))
LDR_FLAGS += --use-vmas
ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
OUTPUT_ARCH(bfin)
-/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
MEMORY
{
ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
- l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
- l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+ l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
}
ENTRY(_start)
/*
- * U-boot - stamp.c STAMP board specific routines
+ * U-boot - main board file
*
- * Copyright (c) 2005-2007 Analog Devices Inc.
+ * Copyright (c) 2005-2008 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
DECLARE_GLOBAL_DATA_PTR;
-#define STATUS_LED_OFF 0
-#define STATUS_LED_ON 1
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
-#else
-# define SHOW_BOOT_PROGRESS(arg)
-#endif
-
int checkboard(void)
{
printf("Board: ADI BF533 Stamp board\n");
}
#endif
-void stamp_led_set(int LED1, int LED2, int LED3)
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+
+#define STATUS_LED_OFF 0
+#define STATUS_LED_ON 1
+
+static void stamp_led_set(int LED1, int LED2, int LED3)
{
- *pFIO_INEN &= ~(PF2 | PF3 | PF4);
- *pFIO_DIR |= (PF2 | PF3 | PF4);
+ bfin_write_FIO_INEN(bfin_read_FIO_INEN() & ~(PF2 | PF3 | PF4));
+ bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (PF2 | PF3 | PF4));
if (LED1 == STATUS_LED_OFF)
*pFIO_FLAG_S = PF2;
break;
}
}
+#endif
+
+#ifdef CONFIG_STATUS_LED
+#include <status_led.h>
+
+static void set_led(int pf, int state)
+{
+ switch (state) {
+ case STATUS_LED_OFF: bfin_write_FIO_FLAG_S(pf); break;
+ case STATUS_LED_BLINKING: bfin_write_FIO_FLAG_T(pf); break;
+ case STATUS_LED_ON: bfin_write_FIO_FLAG_C(pf); break;
+ }
+}
+
+static void set_leds(led_id_t mask, int state)
+{
+ if (mask & 0x1) set_led(PF2, state);
+ if (mask & 0x2) set_led(PF3, state);
+ if (mask & 0x4) set_led(PF4, state);
+}
+
+void __led_init(led_id_t mask, int state)
+{
+ bfin_write_FIO_INEN(bfin_read_FIO_INEN() & ~(PF2 | PF3 | PF4));
+ bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (PF2 | PF3 | PF4));
+}
+
+void __led_set(led_id_t mask, int state)
+{
+ set_leds(mask, state);
+}
+
+void __led_toggle(led_id_t mask)
+{
+ set_leds(mask, STATUS_LED_BLINKING);
+}
+
+#endif
OUTPUT_ARCH(bfin)
-/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
MEMORY
{
ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
- l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
- l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+ l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
}
ENTRY(_start)
LIB = $(obj)lib$(BOARD).a
-COBJS-y := $(BOARD).o post-memory.o cmd_bf537led.o
+COBJS-y := $(BOARD).o cmd_bf537led.o
COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o
COBJS-$(CONFIG_CMD_NAND) += nand.o
+COBJS-$(CONFIG_POST) += post.o post-memory.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
/*
- * U-boot - BF537.c
+ * U-boot - main board file
*
- * Copyright (c) 2005-2007 Analog Devices Inc.
+ * Copyright (c) 2005-2008 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#include <config.h>
#include <command.h>
#include <asm/blackfin.h>
-#include <asm/io.h>
+#include <asm/net.h>
#include <net.h>
#include <asm/mach-common/bits/bootrom.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
-#define POST_WORD_ADDR 0xFF903FFC
-
int checkboard(void)
{
printf("Board: ADI BF537 stamp board\n");
return gd->bd->bi_memsize;
}
+void board_reset(void)
+{
+ /* workaround for weak pull ups on ssel */
+ if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
+ bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~PF10);
+ bfin_write_PORTFIO_SET(PF10);
+ udelay(1);
+ }
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+#ifdef CONFIG_SYS_NO_FLASH
+# define USE_MAC_IN_FLASH 0
+#else
+# define USE_MAC_IN_FLASH 1
+#endif
+ bool valid_mac = false;
+
+ if (USE_MAC_IN_FLASH) {
+ /* we cram the MAC in the last flash sector */
+ uchar *board_mac_addr = (uchar *)0x203F0000;
+ if (is_valid_ether_addr(board_mac_addr)) {
+ memcpy(mac_addr, board_mac_addr, 6);
+ valid_mac = true;
+ }
+ }
+
+ if (!valid_mac) {
+ puts("Warning: Generating 'random' MAC address\n");
+ bfin_gen_rand_mac(mac_addr);
+ }
+
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return bfin_EMAC_initialize(bis);
+}
+#endif
+
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
int misc_init_r(void)
{
-#if defined(CONFIG_CMD_NET)
- char nid[32];
- unsigned char *pMACaddr = (unsigned char *)0x203F0000;
+#ifdef CONFIG_BFIN_MAC
+ uchar enetaddr[6];
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ board_init_enetaddr(enetaddr);
+#endif
- /* The 0xFF check here is to make sure we don't use the address
- * in flash if it's simply been erased (aka all 0xFF values) */
- if (getenv("ethaddr") == NULL && is_valid_ether_addr(pMACaddr)) {
- sprintf(nid, "%02x:%02x:%02x:%02x:%02x:%02x",
- pMACaddr[0], pMACaddr[1],
- pMACaddr[2], pMACaddr[3], pMACaddr[4], pMACaddr[5]);
- setenv("ethaddr", nid);
- }
+#ifndef CONFIG_SYS_NO_FLASH
+ /* we use the last sector for the MAC address / POST LDR */
+ extern flash_info_t flash_info[];
+ flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, &flash_info[0]);
#endif
#if defined(CONFIG_BFIN_IDE)
return 0;
}
#endif /* CONFIG_MISC_INIT_R */
-
-#if defined(CONFIG_BFIN_MAC)
-
-int board_eth_init(bd_t *bis)
-{
- return bfin_EMAC_initialize(bis);
-}
-#endif
-
-#ifdef CONFIG_POST
-/* Using sw10-PF5 as the hotkey */
-int post_hotkeys_pressed(void)
-{
- int delay = 3;
- int i;
- unsigned short value;
-
- *pPORTF_FER &= ~PF5;
- *pPORTFIO_DIR &= ~PF5;
- *pPORTFIO_INEN |= PF5;
-
- printf("########Press SW10 to enter Memory POST########: %2d ", delay);
- while (delay--) {
- for (i = 0; i < 100; i++) {
- value = *pPORTFIO & PF5;
- if (value != 0) {
- break;
- }
- udelay(10000);
- }
- printf("\b\b\b%2d ", delay);
- }
- printf("\b\b\b 0");
- printf("\n");
- if (value == 0)
- return 0;
- else {
- printf("Hotkey has been pressed, Enter POST . . . . . .\n");
- return 1;
- }
-}
-#endif
-
-#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
-void post_word_store(ulong a)
-{
- volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
- *save_addr = a;
-}
-
-ulong post_word_load(void)
-{
- volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
- return *save_addr;
-}
-#endif
-
-#ifdef CONFIG_POST
-int uart_post_test(int flags)
-{
- return 0;
-}
-
-#define BLOCK_SIZE 0x10000
-#define VERIFY_ADDR 0x2000000
-extern int erase_block_flash(int);
-extern int write_data(long lStart, long lCount, uchar * pnData);
-int flash_post_test(int flags)
-{
- unsigned short *pbuf, *temp;
- int offset, n, i;
- int value = 0;
- int result = 0;
- printf("\n");
- pbuf = (unsigned short *)VERIFY_ADDR;
- temp = pbuf;
- for (n = FLASH_START_POST_BLOCK; n < FLASH_END_POST_BLOCK; n++) {
- offset = (n - 7) * BLOCK_SIZE;
- printf("--------Erase block:%2d..", n);
- erase_block_flash(n);
- printf("OK\r");
- printf("--------Program block:%2d...", n);
- write_data(CONFIG_SYS_FLASH_BASE + offset, BLOCK_SIZE, pbuf);
- printf("OK\r");
- printf("--------Verify block:%2d...", n);
- for (i = 0; i < BLOCK_SIZE; i += 2) {
- if (*(unsigned short *)(CONFIG_SYS_FLASH_BASE + offset + i) !=
- *temp++) {
- value = 1;
- result = 1;
- }
- }
- if (value)
- printf("failed\n");
- else
- printf("OK %3d%%\r",
- (int)(
- (n + 1 -
- FLASH_START_POST_BLOCK) *
- 100 / (FLASH_END_POST_BLOCK -
- FLASH_START_POST_BLOCK)));
-
- temp = pbuf;
- value = 0;
- }
- printf("\n");
- if (result)
- return -1;
- else
- return 0;
-}
-
-/****************************************************
- * LED1 ---- PF6 LED2 ---- PF7 *
- * LED3 ---- PF8 LED4 ---- PF9 *
- * LED5 ---- PF10 LED6 ---- PF11 *
- ****************************************************/
-int led_post_test(int flags)
-{
- *pPORTF_FER &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
- *pPORTFIO_DIR |= PF6 | PF7 | PF8 | PF9 | PF10 | PF11;
- *pPORTFIO_INEN &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
- *pPORTFIO &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
- udelay(1000000);
- printf("LED1 on");
- *pPORTFIO |= PF6;
- udelay(1000000);
- printf("\b\b\b\b\b\b\b");
- printf("LED2 on");
- *pPORTFIO |= PF7;
- udelay(1000000);
- printf("\b\b\b\b\b\b\b");
- printf("LED3 on");
- *pPORTFIO |= PF8;
- udelay(1000000);
- printf("\b\b\b\b\b\b\b");
- printf("LED4 on");
- *pPORTFIO |= PF9;
- udelay(1000000);
- printf("\b\b\b\b\b\b\b");
- printf("LED5 on");
- *pPORTFIO |= PF10;
- udelay(1000000);
- printf("\b\b\b\b\b\b\b");
- printf("lED6 on");
- *pPORTFIO |= PF11;
- printf("\b\b\b\b\b\b\b ");
- return 0;
-}
-
-/************************************************
- * SW10 ---- PF5 SW11 ---- PF4 *
- * SW12 ---- PF3 SW13 ---- PF2 *
- ************************************************/
-int button_post_test(int flags)
-{
- int i, delay = 5;
- unsigned short value = 0;
- int result = 0;
-
- *pPORTF_FER &= ~(PF5 | PF4 | PF3 | PF2);
- *pPORTFIO_DIR &= ~(PF5 | PF4 | PF3 | PF2);
- *pPORTFIO_INEN |= (PF5 | PF4 | PF3 | PF2);
-
- printf("\n--------Press SW10: %2d ", delay);
- while (delay--) {
- for (i = 0; i < 100; i++) {
- value = *pPORTFIO & PF5;
- if (value != 0) {
- break;
- }
- udelay(10000);
- }
- printf("\b\b\b%2d ", delay);
- }
- if (value != 0)
- printf("\b\bOK");
- else {
- result = -1;
- printf("\b\bfailed");
- }
-
- delay = 5;
- printf("\n--------Press SW11: %2d ", delay);
- while (delay--) {
- for (i = 0; i < 100; i++) {
- value = *pPORTFIO & PF4;
- if (value != 0) {
- break;
- }
- udelay(10000);
- }
- printf("\b\b\b%2d ", delay);
- }
- if (value != 0)
- printf("\b\bOK");
- else {
- result = -1;
- printf("\b\bfailed");
- }
-
- delay = 5;
- printf("\n--------Press SW12: %2d ", delay);
- while (delay--) {
- for (i = 0; i < 100; i++) {
- value = *pPORTFIO & PF3;
- if (value != 0) {
- break;
- }
- udelay(10000);
- }
- printf("\b\b\b%2d ", delay);
- }
- if (value != 0)
- printf("\b\bOK");
- else {
- result = -1;
- printf("\b\bfailed");
- }
-
- delay = 5;
- printf("\n--------Press SW13: %2d ", delay);
- while (delay--) {
- for (i = 0; i < 100; i++) {
- value = *pPORTFIO & PF2;
- if (value != 0) {
- break;
- }
- udelay(10000);
- }
- printf("\b\b\b%2d ", delay);
- }
- if (value != 0)
- printf("\b\bOK");
- else {
- result = -1;
- printf("\b\bfailed");
- }
- printf("\n");
- return result;
-}
-#endif
#include <common.h>
#include <asm/io.h>
-#ifdef CONFIG_POST
-
#include <post.h>
#include <watchdog.h>
}
#endif /* CONFIG_POST & CONFIG_SYS_POST_MEMORY */
-#endif /* CONFIG_POST */
--- /dev/null
+/*
+ * BF537-STAMP POST code
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <asm/blackfin.h>
+
+#define POST_WORD_ADDR 0xFF903FFC
+
+/* Using sw10-PF5 as the hotkey */
+int post_hotkeys_pressed(void)
+{
+ int delay = 3;
+ int i;
+ unsigned short value;
+
+ *pPORTF_FER &= ~PF5;
+ *pPORTFIO_DIR &= ~PF5;
+ *pPORTFIO_INEN |= PF5;
+
+ printf("########Press SW10 to enter Memory POST########: %2d ", delay);
+ while (delay--) {
+ for (i = 0; i < 100; i++) {
+ value = *pPORTFIO & PF5;
+ if (value != 0) {
+ break;
+ }
+ udelay(10000);
+ }
+ printf("\b\b\b%2d ", delay);
+ }
+ printf("\b\b\b 0");
+ printf("\n");
+ if (value == 0)
+ return 0;
+ else {
+ printf("Hotkey has been pressed, Enter POST . . . . . .\n");
+ return 1;
+ }
+}
+
+void post_word_store(ulong a)
+{
+ volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
+ *save_addr = a;
+}
+
+ulong post_word_load(void)
+{
+ volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
+ return *save_addr;
+}
+
+int uart_post_test(int flags)
+{
+ return 0;
+}
+
+#define BLOCK_SIZE 0x10000
+#define VERIFY_ADDR 0x2000000
+extern int erase_block_flash(int);
+extern int write_data(long lStart, long lCount, uchar * pnData);
+int flash_post_test(int flags)
+{
+ unsigned short *pbuf, *temp;
+ int offset, n, i;
+ int value = 0;
+ int result = 0;
+ printf("\n");
+ pbuf = (unsigned short *)VERIFY_ADDR;
+ temp = pbuf;
+ for (n = FLASH_START_POST_BLOCK; n < FLASH_END_POST_BLOCK; n++) {
+ offset = (n - 7) * BLOCK_SIZE;
+ printf("--------Erase block:%2d..", n);
+ erase_block_flash(n);
+ printf("OK\r");
+ printf("--------Program block:%2d...", n);
+ write_data(CONFIG_SYS_FLASH_BASE + offset, BLOCK_SIZE, pbuf);
+ printf("OK\r");
+ printf("--------Verify block:%2d...", n);
+ for (i = 0; i < BLOCK_SIZE; i += 2) {
+ if (*(unsigned short *)(CONFIG_SYS_FLASH_BASE + offset + i) !=
+ *temp++) {
+ value = 1;
+ result = 1;
+ }
+ }
+ if (value)
+ printf("failed\n");
+ else
+ printf("OK %3d%%\r",
+ (int)(
+ (n + 1 -
+ FLASH_START_POST_BLOCK) *
+ 100 / (FLASH_END_POST_BLOCK -
+ FLASH_START_POST_BLOCK)));
+
+ temp = pbuf;
+ value = 0;
+ }
+ printf("\n");
+ if (result)
+ return -1;
+ else
+ return 0;
+}
+
+/****************************************************
+ * LED1 ---- PF6 LED2 ---- PF7 *
+ * LED3 ---- PF8 LED4 ---- PF9 *
+ * LED5 ---- PF10 LED6 ---- PF11 *
+ ****************************************************/
+int led_post_test(int flags)
+{
+ *pPORTF_FER &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
+ *pPORTFIO_DIR |= PF6 | PF7 | PF8 | PF9 | PF10 | PF11;
+ *pPORTFIO_INEN &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
+ *pPORTFIO &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
+ udelay(1000000);
+ printf("LED1 on");
+ *pPORTFIO |= PF6;
+ udelay(1000000);
+ printf("\b\b\b\b\b\b\b");
+ printf("LED2 on");
+ *pPORTFIO |= PF7;
+ udelay(1000000);
+ printf("\b\b\b\b\b\b\b");
+ printf("LED3 on");
+ *pPORTFIO |= PF8;
+ udelay(1000000);
+ printf("\b\b\b\b\b\b\b");
+ printf("LED4 on");
+ *pPORTFIO |= PF9;
+ udelay(1000000);
+ printf("\b\b\b\b\b\b\b");
+ printf("LED5 on");
+ *pPORTFIO |= PF10;
+ udelay(1000000);
+ printf("\b\b\b\b\b\b\b");
+ printf("lED6 on");
+ *pPORTFIO |= PF11;
+ printf("\b\b\b\b\b\b\b ");
+ return 0;
+}
+
+/************************************************
+ * SW10 ---- PF5 SW11 ---- PF4 *
+ * SW12 ---- PF3 SW13 ---- PF2 *
+ ************************************************/
+int button_post_test(int flags)
+{
+ int i, delay = 5;
+ unsigned short value = 0;
+ int result = 0;
+
+ *pPORTF_FER &= ~(PF5 | PF4 | PF3 | PF2);
+ *pPORTFIO_DIR &= ~(PF5 | PF4 | PF3 | PF2);
+ *pPORTFIO_INEN |= (PF5 | PF4 | PF3 | PF2);
+
+ printf("\n--------Press SW10: %2d ", delay);
+ while (delay--) {
+ for (i = 0; i < 100; i++) {
+ value = *pPORTFIO & PF5;
+ if (value != 0) {
+ break;
+ }
+ udelay(10000);
+ }
+ printf("\b\b\b%2d ", delay);
+ }
+ if (value != 0)
+ printf("\b\bOK");
+ else {
+ result = -1;
+ printf("\b\bfailed");
+ }
+
+ delay = 5;
+ printf("\n--------Press SW11: %2d ", delay);
+ while (delay--) {
+ for (i = 0; i < 100; i++) {
+ value = *pPORTFIO & PF4;
+ if (value != 0) {
+ break;
+ }
+ udelay(10000);
+ }
+ printf("\b\b\b%2d ", delay);
+ }
+ if (value != 0)
+ printf("\b\bOK");
+ else {
+ result = -1;
+ printf("\b\bfailed");
+ }
+
+ delay = 5;
+ printf("\n--------Press SW12: %2d ", delay);
+ while (delay--) {
+ for (i = 0; i < 100; i++) {
+ value = *pPORTFIO & PF3;
+ if (value != 0) {
+ break;
+ }
+ udelay(10000);
+ }
+ printf("\b\b\b%2d ", delay);
+ }
+ if (value != 0)
+ printf("\b\bOK");
+ else {
+ result = -1;
+ printf("\b\bfailed");
+ }
+
+ delay = 5;
+ printf("\n--------Press SW13: %2d ", delay);
+ while (delay--) {
+ for (i = 0; i < 100; i++) {
+ value = *pPORTFIO & PF2;
+ if (value != 0) {
+ break;
+ }
+ udelay(10000);
+ }
+ printf("\b\b\b%2d ", delay);
+ }
+ if (value != 0)
+ printf("\b\bOK");
+ else {
+ result = -1;
+ printf("\b\bfailed");
+ }
+ printf("\n");
+ return result;
+}
#include <malloc.h>
#include <asm/io.h>
#include <asm/mach-common/bits/spi.h>
+#include <asm/mach-common/bits/dma.h>
/* Forcibly phase out these */
#ifdef CONFIG_SPI_FLASH_NUM_SECTORS
struct flash_info {
char *name;
uint16_t id;
+ uint16_t ext_id;
unsigned sector_size;
unsigned num_sectors;
};
/* SPI Speeds: 50 MHz / 33 MHz */
static struct flash_info flash_spansion_serial_flash[] = {
- { "S25FL016", 0x0215, 64 * 1024, 32 },
- { "S25FL032", 0x0216, 64 * 1024, 64 },
- { "S25FL064", 0x0217, 64 * 1024, 128 },
- { "S25FL0128", 0x0218, 256 * 1024, 64 },
- { NULL, 0, 0, 0 }
+ { "S25FL016", 0x0215, 0, 64 * 1024, 32 },
+ { "S25FL032", 0x0216, 0, 64 * 1024, 64 },
+ { "S25FL064", 0x0217, 0, 64 * 1024, 128 },
+ { "S25FL128-00", 0x2018, 0x0301, 64 * 1024, 256 }, /* Package marking FL128PIF */
+ { "S25FL128-01", 0x2018, 0x0300, 128 * 1024, 64 }, /* Package marking FL128PIFL */
+ { NULL, 0, 0, 0, 0 }
};
/* SPI Speeds: 50 MHz / 20 MHz */
static struct flash_info flash_st_serial_flash[] = {
- { "m25p05", 0x2010, 32 * 1024, 2 },
- { "m25p10", 0x2011, 32 * 1024, 4 },
- { "m25p20", 0x2012, 64 * 1024, 4 },
- { "m25p40", 0x2013, 64 * 1024, 8 },
- { "m25p16", 0x2015, 64 * 1024, 32 },
- { "m25p32", 0x2016, 64 * 1024, 64 },
- { "m25p64", 0x2017, 64 * 1024, 128 },
- { "m25p128", 0x2018, 256 * 1024, 64 },
- { NULL, 0, 0, 0 }
+ { "m25p05", 0x2010, 0, 32 * 1024, 2 },
+ { "m25p10", 0x2011, 0, 32 * 1024, 4 },
+ { "m25p20", 0x2012, 0, 64 * 1024, 4 },
+ { "m25p40", 0x2013, 0, 64 * 1024, 8 },
+ { "m25p80", 0x20FF, 0, 64 * 1024, 16 },
+ { "m25p16", 0x2015, 0, 64 * 1024, 32 },
+ { "m25p32", 0x2016, 0, 64 * 1024, 64 },
+ { "m25p64", 0x2017, 0, 64 * 1024, 128 },
+ { "m25p128", 0x2018, 0, 256 * 1024, 64 },
+ { NULL, 0, 0, 0, 0 }
+};
+
+/* SPI Speeds: 20 MHz / 40 MHz */
+static struct flash_info flash_sst_serial_flash[] = {
+ { "SST25WF512", 0x2501, 0, 4 * 1024, 128 },
+ { "SST25WF010", 0x2502, 0, 4 * 1024, 256 },
+ { "SST25WF020", 0x2503, 0, 4 * 1024, 512 },
+ { "SST25WF040", 0x2504, 0, 4 * 1024, 1024 },
+ { NULL, 0, 0, 0, 0 }
};
/* SPI Speeds: 66 MHz / 33 MHz */
static struct flash_info flash_atmel_dataflash[] = {
- { "AT45DB011x", 0x0c, 264, 512 },
- { "AT45DB021x", 0x14, 264, 1025 },
- { "AT45DB041x", 0x1c, 264, 2048 },
- { "AT45DB081x", 0x24, 264, 4096 },
- { "AT45DB161x", 0x2c, 528, 4096 },
- { "AT45DB321x", 0x34, 528, 8192 },
- { "AT45DB642x", 0x3c, 1056, 8192 },
- { NULL, 0, 0, 0 }
+ { "AT45DB011x", 0x0c, 0, 264, 512 },
+ { "AT45DB021x", 0x14, 0, 264, 1025 },
+ { "AT45DB041x", 0x1c, 0, 264, 2048 },
+ { "AT45DB081x", 0x24, 0, 264, 4096 },
+ { "AT45DB161x", 0x2c, 0, 528, 4096 },
+ { "AT45DB321x", 0x34, 0, 528, 8192 },
+ { "AT45DB642x", 0x3c, 0, 1056, 8192 },
+ { NULL, 0, 0, 0, 0 }
};
/* SPI Speed: 50 MHz / 25 MHz or 40 MHz / 20 MHz */
static struct flash_info flash_winbond_serial_flash[] = {
- { "W25X10", 0x3011, 16 * 256, 32 },
- { "W25X20", 0x3012, 16 * 256, 64 },
- { "W25X40", 0x3013, 16 * 256, 128 },
- { "W25X80", 0x3014, 16 * 256, 256 },
- { "W25P80", 0x2014, 256 * 256, 16 },
- { "W25P16", 0x2015, 256 * 256, 32 },
- { NULL, 0, 0, 0 }
+ { "W25X10", 0x3011, 0, 16 * 256, 32 },
+ { "W25X20", 0x3012, 0, 16 * 256, 64 },
+ { "W25X40", 0x3013, 0, 16 * 256, 128 },
+ { "W25X80", 0x3014, 0, 16 * 256, 256 },
+ { "W25P80", 0x2014, 0, 256 * 256, 16 },
+ { "W25P16", 0x2015, 0, 256 * 256, 32 },
+ { NULL, 0, 0, 0, 0 }
};
struct flash_ops {
.status = 0x05,
};
+static struct flash_ops flash_sst_ops = {
+ .read = OP_READ,
+ .write = 0x02,
+ .erase = 0x20,
+ .status = 0x05,
+};
+
static struct flash_ops flash_atmel_ops = {
.read = OP_READ,
.write = 0x82,
struct manufacturer_info *manufacturer;
struct flash_info *flash;
struct flash_ops *ops;
- uint8_t manufacturer_id, device_id1, device_id2;
+ uint8_t manufacturer_id, device_id1, device_id2, device_extid1, device_extid2;
unsigned int write_length;
unsigned long sector_size, num_sectors;
} flash;
enum {
JED_MANU_SPANSION = 0x01,
JED_MANU_ST = 0x20,
+ JED_MANU_SST = 0xBF,
JED_MANU_ATMEL = 0x1F,
JED_MANU_WINBOND = 0xEF,
};
.flashes = flash_st_serial_flash,
.ops = &flash_st_ops,
},
+ {
+ .name = "SST",
+ .id = JED_MANU_SST,
+ .flashes = flash_sst_serial_flash,
+ .ops = &flash_sst_ops,
+ },
{
.name = "Atmel",
.id = JED_MANU_ATMEL,
},
};
-#define TIMEOUT 5000 /* timeout of 5 seconds */
+#define TIMEOUT 5000 /* timeout of 5 seconds */
/* If part has multiple SPI flashes, assume SPI0 as that is
* the one we can boot off of ...
/* [#3541] This delay appears to be necessary, but not sure
* exactly why as the history behind it is non-existant.
*/
+ *pSPI_CTL = 0;
udelay(CONFIG_CCLK_HZ / 25000000);
/* enable SPI pins: SSEL, MOSI, MISO, SCK */
#endif
/* initate communication upon write of TDBR */
- *pSPI_CTL = (SPE|MSTR|CPHA|CPOL|0x01);
+ *pSPI_CTL = (SPE | MSTR | CPHA | CPOL | TDBR_CORE);
*pSPI_BAUD = CONFIG_SPI_BAUD;
}
static void SPI_DEINIT(void)
{
- /* put SPI settings back to reset state */
- *pSPI_CTL = 0x0400;
+ *pSPI_CTL = 0;
*pSPI_BAUD = 0;
SSYNC();
}
switch (flash.manufacturer_id) {
case JED_MANU_SPANSION:
case JED_MANU_ST:
+ case JED_MANU_SST:
case JED_MANU_WINBOND:
if (!(read_status_register() & 0x01))
return 0;
return -1;
}
+static int enable_writing(void)
+{
+ ulong start;
+
+ if (flash.manufacturer_id == JED_MANU_ATMEL)
+ return 0;
+
+ /* A write enable instruction must previously have been executed */
+ SPI_ON();
+ spi_write_read_byte(0x06);
+ SPI_OFF();
+
+ /* The status register will be polled to check the write enable latch "WREN" */
+ start = get_timer(0);
+ while (get_timer(0) - start < TIMEOUT) {
+ if (read_status_register() & 0x02)
+ return 0;
+
+ if (ctrlc()) {
+ puts("\nAbort\n");
+ return -1;
+ }
+ }
+
+ puts("Timeout\n");
+ return -1;
+}
+
+static void write_status_register(uint8_t val)
+{
+ if (flash.manufacturer_id != JED_MANU_SST)
+ hang();
+
+ if (enable_writing())
+ return;
+
+ /* send instruction to write status register */
+ SPI_ON();
+ spi_write_read_byte(0x01);
+ /* and clear it! */
+ spi_write_read_byte(val);
+ SPI_OFF();
+}
+
/* Request and read the manufacturer and device id of parts which
* are compatible with the JEDEC standard (JEP106) and use that to
* setup other operating conditions.
*/
static int spi_detect_part(void)
{
- uint16_t dev_id;
+ uint16_t dev_id, dev_extid;
size_t i;
static char called_init;
if (called_init)
return 0;
+#ifdef CONFIG_SPI_FLASH_M25P80
+ flash.manufacturer_id = JED_MANU_ST;
+ flash.device_id1 = 0x20;
+ flash.device_id2 = 0xFF;
+#else
SPI_ON();
/* Send the request for the part identification */
/* Now read in the second device id byte */
flash.device_id2 = spi_write_read_byte(0);
+ /* Read extended device ids */
+ flash.device_extid1 = spi_write_read_byte(0);
+ flash.device_extid2 = spi_write_read_byte(0);
+
SPI_OFF();
+#endif
dev_id = (flash.device_id1 << 8) | flash.device_id2;
+ dev_extid = (flash.device_extid1 << 8) | flash.device_extid2;
for (i = 0; i < ARRAY_SIZE(flash_manufacturers); ++i) {
if (flash.manufacturer_id == flash_manufacturers[i].id)
switch (flash.manufacturer_id) {
case JED_MANU_SPANSION:
case JED_MANU_ST:
+ case JED_MANU_SST:
case JED_MANU_WINBOND:
for (i = 0; flash.manufacturer->flashes[i].name; ++i) {
- if (dev_id == flash.manufacturer->flashes[i].id)
+ if (dev_id == flash.manufacturer->flashes[i].id &&
+ (flash.manufacturer->flashes[i].ext_id == 0 ||
+ flash.manufacturer->flashes[i].ext_id == dev_extid))
break;
}
if (!flash.manufacturer->flashes[i].name)
flash.flash = &flash.manufacturer->flashes[i];
flash.sector_size = flash.flash->sector_size;
flash.num_sectors = flash.flash->num_sectors;
- flash.write_length = 256;
+
+ if (flash.manufacturer_id == JED_MANU_SST)
+ flash.write_length = 1; /* pwnt :( */
+ else
+ flash.write_length = 256;
break;
case JED_MANU_ATMEL: {
}
}
+ /* the SST parts power up with software protection enabled by default */
+ if (flash.manufacturer_id == JED_MANU_SST)
+ write_status_register(0);
+
called_init = 1;
return 0;
* int pnData - pointer to store value read from flash
* long lCount - number of elements to read
*/
+#ifdef CONFIG_SPI_READFLASH_NODMA
static int read_flash(unsigned long address, long count, uchar *buffer)
{
- size_t i;
+ size_t i, j;
/* Send the read command to SPI device */
SPI_ON();
/* After the SPI device address has been placed on the MOSI pin the data can be */
/* received on the MISO pin. */
+ j = flash.sector_size << 1;
for (i = 1; i <= count; ++i) {
*buffer++ = spi_write_read_byte(0);
- if (i % flash.sector_size == 0)
+ if (!j--) {
puts(".");
+ j = flash.sector_size;
+ }
}
SPI_OFF();
return 0;
}
+#else
-static int enable_writing(void)
+#ifdef __ADSPBF54x__
+#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA4_IRQ_STATUS
+#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA4_IRQ_STATUS
+#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA4_CURR_DESC_PTR
+#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA4_CONFIG
+#elif defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__) || \
+ defined(__ADSPBF538__) || defined(__ADSPBF539__)
+#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA5_IRQ_STATUS
+#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA5_IRQ_STATUS
+#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA5_CURR_DESC_PTR
+#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA5_CONFIG
+#elif defined(__ADSPBF561__)
+#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA16_IRQ_STATUS
+#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA16_IRQ_STATUS
+#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA16_CURR_DESC_PTR
+#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA16_CONFIG
+#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) || \
+ defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
+#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA7_IRQ_STATUS
+#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA7_IRQ_STATUS
+#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA7_CURR_DESC_PTR
+#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA7_CONFIG
+#else
+#error "Please provide SPI DMA channel defines"
+#endif
+
+struct dmadesc_array {
+ unsigned long start_addr;
+ unsigned short cfg;
+ unsigned short x_count;
+ short x_modify;
+ unsigned short y_count;
+ short y_modify;
+} __attribute__((packed));
+
+/*
+ * Read a value from flash for verify purpose
+ * Inputs: unsigned long ulStart - holds the SPI start address
+ * int pnData - pointer to store value read from flash
+ * long lCount - number of elements to read
+ */
+
+static int read_flash(unsigned long address, long count, uchar *buffer)
{
- ulong start;
+ unsigned int ndsize;
+ struct dmadesc_array dma[2];
+ /* Send the read command to SPI device */
- if (flash.manufacturer_id == JED_MANU_ATMEL)
+ if (!count)
return 0;
- /* A write enable instruction must previously have been executed */
+ dma[0].start_addr = (unsigned long)buffer;
+ dma[0].x_modify = 1;
+ if (count <= 65536) {
+ blackfin_dcache_flush_invalidate_range(buffer, buffer + count);
+ ndsize = NDSIZE_5;
+ dma[0].cfg = NDSIZE_0 | WNR | WDSIZE_8 | FLOW_STOP | DMAEN | DI_EN;
+ dma[0].x_count = count;
+ } else {
+ blackfin_dcache_flush_invalidate_range(buffer, buffer + 65536 - 1);
+ ndsize = NDSIZE_7;
+ dma[0].cfg = NDSIZE_5 | WNR | WDSIZE_8 | FLOW_ARRAY | DMAEN | DMA2D;
+ dma[0].x_count = 0; /* 2^16 */
+ dma[0].y_count = count >> 16; /* count / 2^16 */
+ dma[0].y_modify = 1;
+ dma[1].start_addr = (unsigned long)(buffer + (count & ~0xFFFF));
+ dma[1].cfg = NDSIZE_0 | WNR | WDSIZE_8 | FLOW_STOP | DMAEN | DI_EN;
+ dma[1].x_count = count & 0xFFFF; /* count % 2^16 */
+ dma[1].x_modify = 1;
+ }
+
+ bfin_write_DMA_SPI_CONFIG(0);
+ bfin_write_DMA_SPI_IRQ_STATUS(DMA_DONE | DMA_ERR);
+ bfin_write_DMA_SPI_CURR_DESC_PTR(dma);
+
SPI_ON();
- spi_write_read_byte(0x06);
+
+ spi_write_read_byte(flash.ops->read);
+ transmit_address(address);
+
+#ifndef CONFIG_SPI_FLASH_SLOW_READ
+ /* Send dummy byte when doing SPI fast reads */
+ spi_write_read_byte(0);
+#endif
+
+ bfin_write_DMA_SPI_CONFIG(ndsize | FLOW_ARRAY | DMAEN);
+ *pSPI_CTL = (MSTR | CPHA | CPOL | RDBR_DMA | SPE | SZ);
+ SSYNC();
+
+ /*
+ * We already invalidated the first 64k,
+ * now while we just wait invalidate the remaining part.
+ * Its not likely that the DMA is going to overtake
+ */
+ if (count > 65536)
+ blackfin_dcache_flush_invalidate_range(buffer + 65536,
+ buffer + count);
+
+ while (!(bfin_read_DMA_SPI_IRQ_STATUS() & DMA_DONE))
+ if (ctrlc())
+ break;
+
SPI_OFF();
- /* The status register will be polled to check the write enable latch "WREN" */
- start = get_timer(0);
- while (get_timer(0) - start < TIMEOUT) {
- if (read_status_register() & 0x02)
- return 0;
+ *pSPI_CTL = 0;
- if (ctrlc()) {
- puts("\nAbort\n");
- return -1;
- }
- }
+ bfin_write_DMA_SPI_CONFIG(0);
- puts("Timeout\n");
- return -1;
+ *pSPI_CTL = (SPE | MSTR | CPHA | CPOL | TDBR_CORE);
+
+ return 0;
}
+#endif
static long address_to_sector(unsigned long address)
{
OUTPUT_ARCH(bfin)
-/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
MEMORY
{
ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
- l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
- l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+ l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
}
ENTRY(_start)
OUTPUT_ARCH(bfin)
-/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
MEMORY
{
ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
- l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
- l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+ l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
}
ENTRY(_start)
eieio();
}
-static int dev_ready(void)
+static int dev_ready(int chip_nr)
{
if (in_be32(&im->qepio.ioport[4].pdat) & 0x00002000) {
debug("nand ready\n");
.upm_cmd_offset = 8,
.upm_addr_offset = 16,
.dev_ready = dev_ready,
- .wait_pattern = 1,
+ .wait_flags = FSL_UPM_WAIT_RUN_PATTERN,
.chip_delay = 50,
};
MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
/* dummy access to perform write */
- out_8 ((void __iomem *)CONFIG_SYS_NAND0_BASE, 0);
+ out_8 ((void __iomem *)CONFIG_SYS_NAND_BASE, 0);
clrbits_be32(&lbc->mbmr, MxMR_OP_WARR);
}
.width = 8,
.upm_cmd_offset = 0x08,
.upm_addr_offset = 0x10,
+ .upm_mar_chip_offset = CONFIG_SYS_NAND_CS_DIST,
+ .chip_offset = CONFIG_SYS_NAND_CS_DIST,
.chip_delay = NAND_BIG_DELAY_US,
+ .wait_flags = FSL_UPM_WAIT_RUN_PATTERN | FSL_UPM_WAIT_WRITE_BUFFER,
};
void board_nand_select_device (struct nand_chip *nand, int chip)
}
#endif
+static void nand_print_info(int idx)
+{
+ nand_info_t *nand = &nand_info[idx];
+ struct nand_chip *chip = nand->priv;
+ printf("Device %d: ", idx);
+ if (chip->numchips > 1)
+ printf("%dx ", chip->numchips);
+ printf("%s, sector size %u KiB\n",
+ nand->name, nand->erasesize >> 10);
+}
+
int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
int i, dev, ret = 0;
putc('\n');
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) {
if (nand_info[i].name)
- printf("Device %d: %s, sector size %u KiB\n",
- i, nand_info[i].name,
- nand_info[i].erasesize >> 10);
+ nand_print_info(i);
}
return 0;
}
if (strcmp(cmd, "device") == 0) {
if (argc < 3) {
+ putc('\n');
if ((nand_curr_device < 0) ||
(nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE))
- puts("\nno devices available\n");
+ puts("no devices available\n");
else
- printf("\nDevice %d: %s\n", nand_curr_device,
- nand_info[nand_curr_device].name);
+ nand_print_info(nand_curr_device);
return 0;
}
dev = (int)simple_strtoul(argv[2], NULL, 10);
__attribute__ ((__noreturn__))
void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
{
- /* Build a NOP slide over the LDR jump block. Whee! */
- serial_early_puts("NOP Slide\n");
- char nops[0xC];
- memset(nops, 0x00, sizeof(nops));
- extern char _stext_l1;
- memcpy(&_stext_l1 - sizeof(nops), nops, sizeof(nops));
-
if (!loaded_from_ldr) {
/* Relocate sections into L1 if the LDR didn't do it -- don't
* check length because the linker script does the size
* checking at build time.
*/
+ extern char _stext_l1;
serial_early_puts("L1 Relocate\n");
extern char _stext_l1, _etext_l1, _stext_l1_lma;
memcpy(&_stext_l1, &_stext_l1_lma, (&_etext_l1 - &_stext_l1));
#include <config.h>
#include <asm/blackfin.h>
#include <asm/mach-common/bits/bootrom.h>
+#include <asm/mach-common/bits/core.h>
#include <asm/mach-common/bits/ebiu.h>
#include <asm/mach-common/bits/pll.h>
#include <asm/mach-common/bits/uart.h>
# define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
#endif
+/* some parts do not have an on-chip voltage regulator */
+#if defined(__ADSPBF51x__)
+# define CONFIG_HAS_VR 0
+# undef CONFIG_VR_CTL_VAL
+# define CONFIG_VR_CTL_VAL 0
+#else
+# define CONFIG_HAS_VR 1
+#endif
+
+#ifndef EBIU_RSTCTL
+/* Blackfin with SDRAM */
+#ifndef CONFIG_EBIU_SDBCTL_VAL
+# if CONFIG_MEM_SIZE == 16
+# define CONFIG_EBSZ_VAL EBSZ_16
+# elif CONFIG_MEM_SIZE == 32
+# define CONFIG_EBSZ_VAL EBSZ_32
+# elif CONFIG_MEM_SIZE == 64
+# define CONFIG_EBSZ_VAL EBSZ_64
+# elif CONFIG_MEM_SIZE == 128
+# define CONFIG_EBSZ_VAL EBSZ_128
+# elif CONFIG_MEM_SIZE == 256
+# define CONFIG_EBSZ_VAL EBSZ_256
+# elif CONFIG_MEM_SIZE == 512
+# define CONFIG_EBSZ_VAL EBSZ_512
+# else
+# error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_SIZE
+# endif
+# if CONFIG_MEM_ADD_WDTH == 8
+# define CONFIG_EBCAW_VAL EBCAW_8
+# elif CONFIG_MEM_ADD_WDTH == 9
+# define CONFIG_EBCAW_VAL EBCAW_9
+# elif CONFIG_MEM_ADD_WDTH == 10
+# define CONFIG_EBCAW_VAL EBCAW_10
+# elif CONFIG_MEM_ADD_WDTH == 11
+# define CONFIG_EBCAW_VAL EBCAW_11
+# else
+# error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_ADD_WDTH
+# endif
+# define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE)
+#endif
+#endif
+
BOOTROM_CALLED_FUNC_ATTR
void initcode(ADI_BOOT_DATA *bootstruct)
{
divB = serial_early_get_div();
}
+ serial_putc('A');
+
#ifdef CONFIG_HW_WATCHDOG
# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
# define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
}
#endif
- serial_putc('S');
+ serial_putc('B');
+
+ /* If external memory is enabled, put it into self refresh first. */
+ bool put_into_srfs = false;
+#ifdef EBIU_RSTCTL
+ if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
+ bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ);
+ put_into_srfs = true;
+ }
+#else
+ if (bfin_read_EBIU_SDBCTL() & EBE) {
+ bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
+ put_into_srfs = true;
+ }
+#endif
+
+ serial_putc('C');
/* Blackfin bootroms use the SPI slow read opcode instead of the SPI
* fast read, so we need to slow down the SPI clock a lot more during
bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
}
- serial_putc('B');
+ serial_putc('D');
- /* Disable all peripheral wakeups except for the PLL event. */
-#ifdef SIC_IWR0
- bfin_write_SIC_IWR0(1);
- bfin_write_SIC_IWR1(0);
-# ifdef SIC_IWR2
- bfin_write_SIC_IWR2(0);
-# endif
-#elif defined(SICA_IWR0)
- bfin_write_SICA_IWR0(1);
- bfin_write_SICA_IWR1(0);
+ /* If we're entering self refresh, make sure it has happened. */
+ if (put_into_srfs)
+#ifdef EBIU_RSTCTL
+ while (!(bfin_read_EBIU_RSTCTL() & SRACK))
#else
- bfin_write_SIC_IWR(1);
+ while (!(bfin_read_EBIU_SDSTAT() & SDSRA))
#endif
+ continue;
+
+ serial_putc('E');
/* With newer bootroms, we use the helper function to set up
* the memory controller. Older bootroms lacks such helpers
* so we do it ourselves.
*/
-#define BOOTROM_CAPS_SYSCONTROL 0
- if (BOOTROM_CAPS_SYSCONTROL) {
- serial_putc('S');
+ uint16_t vr_ctl = bfin_read_VR_CTL();
+ if (!ANOMALY_05000386) {
+ serial_putc('F');
ADI_SYSCTRL_VALUES memory_settings;
- memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
+ uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT;
+ if (CONFIG_HAS_VR) {
+ actions |= SYSCTRL_VRCTL;
+ if (CONFIG_VR_CTL_VAL & FREQ_MASK)
+ actions |= SYSCTRL_INTVOLTAGE;
+ else
+ actions |= SYSCTRL_EXTVOLTAGE;
+ memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
+ } else
+ actions |= SYSCTRL_EXTVOLTAGE;
memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
- syscontrol(SYSCTRL_WRITE | SYSCTRL_VRCTL | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT |
- (CONFIG_VR_CTL_VAL & FREQ_MASK ? SYSCTRL_INTVOLTAGE : SYSCTRL_EXTVOLTAGE), &memory_settings, NULL);
+#if ANOMALY_05000432
+ bfin_write_SIC_IWR1(0);
+#endif
+ bfrom_SysControl(actions, &memory_settings, NULL);
+#if ANOMALY_05000432
+ bfin_write_SIC_IWR1(-1);
+#endif
} else {
- serial_putc('L');
+ serial_putc('G');
+
+ /* Disable all peripheral wakeups except for the PLL event. */
+#ifdef SIC_IWR0
+ bfin_write_SIC_IWR0(1);
+ bfin_write_SIC_IWR1(0);
+# ifdef SIC_IWR2
+ bfin_write_SIC_IWR2(0);
+# endif
+#elif defined(SICA_IWR0)
+ bfin_write_SICA_IWR0(1);
+ bfin_write_SICA_IWR1(0);
+#else
+ bfin_write_SIC_IWR(1);
+#endif
+
+ serial_putc('H');
bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
- serial_putc('A');
+ serial_putc('I');
/* Only reprogram when needed to avoid triggering unnecessary
* PLL relock sequences.
*/
- if (bfin_read_VR_CTL() != CONFIG_VR_CTL_VAL) {
+ if (vr_ctl != CONFIG_VR_CTL_VAL) {
serial_putc('!');
bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
asm("idle;");
}
- serial_putc('C');
+ serial_putc('J');
bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
asm("idle;");
}
+
+ serial_putc('L');
+
+ /* Restore all peripheral wakeups. */
+#ifdef SIC_IWR0
+ bfin_write_SIC_IWR0(-1);
+ bfin_write_SIC_IWR1(-1);
+# ifdef SIC_IWR2
+ bfin_write_SIC_IWR2(-1);
+# endif
+#elif defined(SICA_IWR0)
+ bfin_write_SICA_IWR0(-1);
+ bfin_write_SICA_IWR1(-1);
+#else
+ bfin_write_SIC_IWR(-1);
+#endif
}
+ serial_putc('M');
+
/* Since we've changed the SCLK above, we may need to update
* the UART divisors (UART baud rates are based on SCLK).
* Do the division by hand as there are no native instructions
serial_early_put_div(quotient - ANOMALY_05000230);
}
- serial_putc('F');
+ serial_putc('N');
- /* Program the async banks controller. */
- bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
- bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
- bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
+ /* Program the external memory controller before we come out of
+ * self-refresh. This only works with our SDRAM controller.
+ */
+#ifndef EBIU_RSTCTL
+ bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
+ bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
+ bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
+#endif
-#ifdef EBIU_MODE
- /* Not all parts have these additional MMRs. */
- bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
- bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
- bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
+ serial_putc('O');
+
+ /* Now that we've reprogrammed, take things out of self refresh. */
+ if (put_into_srfs)
+#ifdef EBIU_RSTCTL
+ bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
+#else
+ bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS));
#endif
- serial_putc('I');
+ serial_putc('P');
- /* Program the external memory controller. */
+ /* Our DDR controller sucks and cannot be programmed while in
+ * self-refresh. So we have to pull it out before programming.
+ */
#ifdef EBIU_RSTCTL
bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
/* default is disable, so don't need to force this */
bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
# endif
-#else
- bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
- bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
- bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
+# ifdef CONFIG_EBIU_DDRQUE_VAL
+ bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | CONFIG_EBIU_DDRQUE_VAL);
+# endif
#endif
- serial_putc('N');
+ serial_putc('Q');
- /* Restore all peripheral wakeups. */
-#ifdef SIC_IWR0
- bfin_write_SIC_IWR0(-1);
- bfin_write_SIC_IWR1(-1);
-# ifdef SIC_IWR2
- bfin_write_SIC_IWR2(-1);
-# endif
-#elif defined(SICA_IWR0)
- bfin_write_SICA_IWR0(-1);
- bfin_write_SICA_IWR1(-1);
-#else
- bfin_write_SIC_IWR(-1);
+ /* Are we coming out of hibernate (suspend to memory) ?
+ * The memory layout is:
+ * 0x0: hibernate magic for anomaly 307 (0xDEADBEEF)
+ * 0x4: return address
+ * 0x8: stack pointer
+ *
+ * SCKELOW is unreliable on older parts (anomaly 307)
+ */
+ if (ANOMALY_05000307 || vr_ctl & 0x8000) {
+ uint32_t *hibernate_magic = 0;
+ __builtin_bfin_ssync(); /* make sure memory controller is done */
+ if (hibernate_magic[0] == 0xDEADBEEF) {
+ serial_putc('R');
+ bfin_write_EVT15(hibernate_magic[1]);
+ bfin_write_IMASK(EVT_IVG15);
+ __asm__ __volatile__ (
+ /* load reti early to avoid anomaly 281 */
+ "reti = %0;"
+ /* clear hibernate magic */
+ "[%0] = %1;"
+ /* load stack pointer */
+ "SP = [%0 + 8];"
+ /* lower ourselves from reset ivg to ivg15 */
+ "raise 15;"
+ "rti;"
+ :
+ : "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */)
+ );
+ }
+ }
+
+ serial_putc('S');
+
+ /* Program the async banks controller. */
+ bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
+ bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
+ bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
+
+#ifdef EBIU_MODE
+ /* Not all parts have these additional MMRs. */
+ bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
+ bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
+ bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
#endif
+ serial_putc('T');
+
+ /* tell the bootrom where our entry point is */
+ if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
+ bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE);
+
serial_putc('>');
serial_putc('\n');
jtag_send(s, strlen(s));
}
-static int jtag_tstc(void)
+static size_t inbound_len, leftovers_len;
+
+/* Lower layers want to know when jtag has data */
+static int jtag_tstc_dbg(void)
{
return (bfin_read_DBGSTAT() & 0x2);
}
+/* Higher layers want to know when any data is available */
+static int jtag_tstc(void)
+{
+ return jtag_tstc_dbg() || leftovers_len;
+}
+
/* Receive a buffer. The format is:
* [32bit length][actual data]
*/
-static size_t inbound_len;
-static int leftovers_len;
static uint32_t leftovers;
static int jtag_getc(void)
{
}
/* wait for new data ! */
- while (!jtag_tstc())
+ while (!jtag_tstc_dbg())
continue;
__asm__("%0 = emudat;" : "=d"(emudat));
* the core reset.
*/
__attribute__ ((__l1_text__, __noreturn__))
-void bfin_reset(void)
+static void bfin_reset(void)
{
/* Wait for completion of "system" events such as cache line
* line fills so that we avoid infinite stalls later on as
/* Save RETX so we can pass it while booting Linux */
r7 = RETX;
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
- /* In bypass mode, we don't have an LDR with an init block
- * so we need to explicitly call it ourselves. This will
- * reprogram our clocks and setup our async banks.
- */
- /* XXX: we should DMA this into L1, put external memory into
- * self refresh, and then jump there ...
+ /* Figure out where we are currently executing so that we can decide
+ * how to best reprogram and relocate things. We'll pass below:
+ * R4: load address of _start
+ * R5: current (not load) address of _start
*/
+ serial_early_puts("Find ourselves");
+
call _get_pc;
- r3 = 0x0;
- r3.h = 0x2000;
- cc = r0 < r3 (iu);
- if cc jump .Lproc_initialized;
+.Loffset:
+ r1.l = .Loffset;
+ r1.h = .Loffset;
+ r4.l = _start;
+ r4.h = _start;
+ r3 = r1 - r4;
+ r5 = r0 - r3;
+
+ /* Inform upper layers if we had to do the relocation ourselves.
+ * This allows us to detect whether we were loaded by 'go 0x1000'
+ * or by the bootrom from an LDR. "R6" is "loaded_from_ldr".
+ */
+ r6 = 1 (x);
+ cc = r4 == r5;
+ if cc jump .Lnorelocate;
+ r6 = 0 (x);
+ /* In bypass mode, we don't have an LDR with an init block
+ * so we need to explicitly call it ourselves. This will
+ * reprogram our clocks, memory, and setup our async banks.
+ */
serial_early_puts("Program Clocks");
+ /* if we're executing >=0x20000000, then we dont need to dma */
+ r3 = 0x0;
+ r3.h = 0x2000;
+ cc = r5 < r3 (iu);
+ if cc jump .Ldma_and_reprogram;
call _initcode;
+ jump .Lprogrammed;
+
+ /* we're sitting in external memory, so dma into L1 and reprogram */
+.Ldma_and_reprogram:
+ r0.l = LO(L1_INST_SRAM);
+ r0.h = HI(L1_INST_SRAM);
+ r1.l = __initcode_start;
+ r1.h = __initcode_start;
+ r2.l = __initcode_end;
+ r2.h = __initcode_end;
+ r2 = r2 - r1; /* convert r2 into length of initcode */
+ r1 = r1 - r4; /* convert r1 from load address of initcode ... */
+ r1 = r1 + r5; /* ... to current (not load) address of initcode */
+ p3 = r0;
+ call _dma_memcpy_nocache;
+ call (p3);
/* Since we reprogrammed SCLK, we need to update the serial divisor */
+.Lprogrammed:
serial_early_set_baud
-.Lproc_initialized:
-#endif
-
- /* Inform upper layers if we had to do the relocation ourselves.
- * This allows us to detect whether we were loaded by 'go 0x1000'
- * or by the bootrom from an LDR. "r6" is "loaded_from_ldr".
- */
- r6 = 1 (x);
-
/* Relocate from wherever we are (FLASH/RAM/etc...) to the hardcoded
* monitor location in the end of RAM. We know that memcpy() only
* uses registers, so it is safe to call here. Note that this only
* it yet (see "lower to 15" below).
*/
serial_early_puts("Relocate");
- call _get_pc;
-.Loffset:
- r2.l = .Loffset;
- r2.h = .Loffset;
- r3.l = _start;
- r3.h = _start;
- r2 = r2 - r3;
- r1 = r0 - r2;
- cc = r1 == r3;
- if cc jump .Lnorelocate;
- r6 = 0 (x);
-
- r0 = r3;
+ r0 = r4;
+ r1 = r5;
r2.l = LO(CONFIG_SYS_MONITOR_LEN);
r2.h = HI(CONFIG_SYS_MONITOR_LEN);
call _memcpy_ASM;
while (*sym) {
sym_addr = simple_strtoul(sym, &esym, 16);
- sym = esym + 1;
+ sym = esym;
if (sym_addr > addr)
break;
*caddr = sym_addr;
if (gd->flags & GD_FLG_RELOC) {
fdr = divider;
} else {
- printf("%ld kHz, ", best_speed / 1000);
+ if (gd->have_console)
+ printf("%ld kHz, ", best_speed / 1000);
return divider;
}
}
xaddr[3] = addr & 0xFF;
if (wait_for_bb()) {
- printf("i2c_read: bus is busy\n");
+ if (gd->have_console)
+ printf("i2c_read: bus is busy\n");
goto Done;
}
mpc_reg_out(®s->mcr, I2C_STA, I2C_STA);
if (do_address(chip, 0)) {
- printf("i2c_read: failed to address chip\n");
+ if (gd->have_console)
+ printf("i2c_read: failed to address chip\n");
goto Done;
}
if (send_bytes(chip, &xaddr[4-alen], alen)) {
- printf("i2c_read: send_bytes failed\n");
+ if (gd->have_console)
+ printf("i2c_read: send_bytes failed\n");
goto Done;
}
mpc_reg_out(®s->mcr, I2C_RSTA, I2C_RSTA);
if (do_address(chip, 1)) {
- printf("i2c_read: failed to address chip\n");
+ if (gd->have_console)
+ printf("i2c_read: failed to address chip\n");
goto Done;
}
if (receive_bytes(chip, (char *)buf, len)) {
- printf("i2c_read: receive_bytes failed\n");
+ if (gd->have_console)
+ printf("i2c_read: receive_bytes failed\n");
goto Done;
}
xaddr[3] = addr & 0xFF;
if (wait_for_bb()) {
- printf("i2c_write: bus is busy\n");
+ if (gd->have_console)
+ printf("i2c_write: bus is busy\n");
goto Done;
}
mpc_reg_out(®s->mcr, I2C_STA, I2C_STA);
if (do_address(chip, 0)) {
- printf("i2c_write: failed to address chip\n");
+ if (gd->have_console)
+ printf("i2c_write: failed to address chip\n");
goto Done;
}
if (send_bytes(chip, &xaddr[4-alen], alen)) {
- printf("i2c_write: send_bytes failed\n");
+ if (gd->have_console)
+ printf("i2c_write: send_bytes failed\n");
goto Done;
}
if (send_bytes(chip, (char *)buf, len)) {
- printf("i2c_write: send_bytes failed\n");
+ if (gd->have_console)
+ printf("i2c_write: send_bytes failed\n");
goto Done;
}
eieio();
}
-static void fsl_upm_run_pattern(struct fsl_upm *upm, int width, u32 cmd)
+static void fsl_upm_run_pattern(struct fsl_upm *upm, int width,
+ void __iomem *io_addr, u32 mar)
{
- out_be32(upm->mar, cmd << (32 - width));
+ out_be32(upm->mar, mar);
switch (width) {
case 8:
- out_8(upm->io_addr, 0x0);
+ out_8(io_addr, 0x0);
break;
case 16:
- out_be16(upm->io_addr, 0x0);
+ out_be16(io_addr, 0x0);
break;
case 32:
- out_be32(upm->io_addr, 0x0);
+ out_be32(io_addr, 0x0);
break;
}
}
+static void fun_wait(struct fsl_upm_nand *fun)
+{
+ if (fun->dev_ready) {
+ while (!fun->dev_ready(fun->chip_nr))
+ debug("unexpected busy state\n");
+ } else {
+ /*
+ * If the R/B pin is not connected, like on the TQM8548,
+ * a short delay is necessary.
+ */
+ udelay(1);
+ }
+}
+
+#if CONFIG_SYS_NAND_MAX_CHIPS > 1
+static void fun_select_chip(struct mtd_info *mtd, int chip_nr)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct fsl_upm_nand *fun = chip->priv;
+
+ if (chip_nr >= 0) {
+ fun->chip_nr = chip_nr;
+ chip->IO_ADDR_R = chip->IO_ADDR_W =
+ fun->upm.io_addr + fun->chip_offset * chip_nr;
+ } else if (chip_nr == -1) {
+ chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
+ }
+}
+#endif
+
static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *chip = mtd->priv;
struct fsl_upm_nand *fun = chip->priv;
+ void __iomem *io_addr;
+ u32 mar;
if (!(ctrl & fun->last_ctrl)) {
fsl_upm_end_pattern(&fun->upm);
fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
}
- fsl_upm_run_pattern(&fun->upm, fun->width, cmd);
+ mar = cmd << (32 - fun->width);
+ io_addr = fun->upm.io_addr;
+#if CONFIG_SYS_NAND_MAX_CHIPS > 1
+ if (fun->chip_nr > 0) {
+ io_addr += fun->chip_offset * fun->chip_nr;
+ if (fun->upm_mar_chip_offset)
+ mar |= fun->upm_mar_chip_offset * fun->chip_nr;
+ }
+#endif
+ fsl_upm_run_pattern(&fun->upm, fun->width, io_addr, mar);
/*
- * Some boards/chips needs this. At least on MPC8360E-RDK we
- * need it. Probably weird chip, because I don't see any need
- * for this on MPC8555E + Samsung K9F1G08U0A. Usually here are
- * 0-2 unexpected busy states per block read.
+ * Some boards/chips needs this. At least the MPC8360E-RDK and
+ * TQM8548 need it. Probably weird chip, because I don't see
+ * any need for this on MPC8555E + Samsung K9F1G08U0A. Usually
+ * here are 0-2 unexpected busy states per block read.
*/
- if (fun->wait_pattern) {
- while (!fun->dev_ready())
- debug("unexpected busy state\n");
- }
+ if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
+ fun_wait(fun);
}
static u8 nand_read_byte(struct mtd_info *mtd)
{
int i;
struct nand_chip *chip = mtd->priv;
+ struct fsl_upm_nand *fun = chip->priv;
- for (i = 0; i < len; i++)
+ for (i = 0; i < len; i++) {
out_8(chip->IO_ADDR_W, buf[i]);
+ if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE)
+ fun_wait(fun);
+ }
+
+ if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER)
+ fun_wait(fun);
}
static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
struct nand_chip *chip = mtd->priv;
struct fsl_upm_nand *fun = chip->priv;
- return fun->dev_ready();
+ return fun->dev_ready(fun->chip_nr);
}
int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
chip->chip_delay = fun->chip_delay;
chip->ecc.mode = NAND_ECC_SOFT;
chip->cmd_ctrl = fun_cmd_ctrl;
+#if CONFIG_SYS_NAND_MAX_CHIPS > 1
+ chip->select_chip = fun_select_chip;
+#endif
chip->read_byte = nand_read_byte;
chip->read_buf = nand_read_buf;
chip->write_buf = nand_write_buf;
static void nand_init_chip(struct mtd_info *mtd, struct nand_chip *nand,
ulong base_addr)
{
+ int maxchips = CONFIG_SYS_NAND_MAX_CHIPS;
+
+ if (maxchips < 1)
+ maxchips = 1;
mtd->priv = nand;
nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
if (board_nand_init(nand) == 0) {
- if (nand_scan(mtd, 1) == 0) {
+ if (nand_scan(mtd, maxchips) == 0) {
if (!mtd->name)
mtd->name = (char *)default_nand_name;
else
type->id != chip->read_byte(mtd))
break;
}
+#ifdef DEBUG
if (i > 1)
printk(KERN_INFO "%d NAND chips detected\n", i);
+#endif
/* Store the number of chips and calc total size for mtd */
chip->numchips = i;
#elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__)
u16 mux = bfin_read_PORT_MUX();
u16 f_fer = bfin_read_PORTF_FER();
- u16 j_fer = bfin_read_PORTJ_FER();
/* set SCK/MISO/MOSI */
f_fer |= PF11 | PF12 | PF13;
switch (slave->cs) {
case 1: f_fer |= PF10; break;
- case 2: mux |= PJSE; j_fer |= PJ11; break;
- case 3: mux |= PJSE; j_fer |= PJ10; break;
+ case 2: mux |= PJSE; break;
+ case 3: mux |= PJSE; break;
case 4: mux |= PFS4E; f_fer |= PF6; break;
case 5: mux |= PFS5E; f_fer |= PF5; break;
case 6: mux |= PFS6E; f_fer |= PF4; break;
- case 7: mux |= PJCE_SPI; j_fer |= PJ5; break;
+ case 7: mux |= PJCE_SPI; break;
}
bfin_write_PORT_MUX(mux);
bfin_write_PORTF_FER(f_fer);
- bfin_write_PORTJ_FER(j_fer);
#elif defined(__ADSPBF54x__)
#define DO_MUX(port, pin) \
mux = ((mux & ~PORT_x_MUX_##pin##_MASK) | PORT_x_MUX_##pin##_FUNC_1); \
#define MK_STR(x) XMK_STR(x)
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-/* Configurable Blackfin-specific monitor commands */
-#define CONFIG_SYS_BFIN_CMD_BOOTLDR 0x01
-#define CONFIG_SYS_BFIN_CMD_CPLBINFO 0x02
-#define CONFIG_SYS_BFIN_CMD_OTP 0x04
-#define CONFIG_SYS_BFIN_CMD_CACHE_DUMP 0x08
-
/* Bootmode defines -- your config needs to select this via CONFIG_BFIN_BOOT_MODE.
* Depending on your cpu, some of these may not be valid, check your HRM.
* The actual values here are meaningless as long as they're unique.
#ifndef __BFIN_CDEF_ADSP_EDN_BF52x_extended__
#define __BFIN_CDEF_ADSP_EDN_BF52x_extended__
-#define pSIC_RVECT ((uint32_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */
-#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
+#define pSIC_RVECT ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */
+#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
+#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val)
#define pSIC_IMASK0 ((uint32_t volatile *)SIC_IMASK0) /* Interrupt Mask Register */
#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */
#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */
#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
* File: include/asm-blackfin/mach-bf527/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
- * Copyright (C) 2004-2008 Analog Devices Inc.
+ * Copyright (C) 2004-2009 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
#define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0)
+#define ANOMALY_05000278 (0)
#define ANOMALY_05000285 (0)
+#define ANOMALY_05000305 (0)
#define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000312 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000363 (0)
#define ANOMALY_05000412 (0)
+#define ANOMALY_05000447 (0)
+#define ANOMALY_05000448 (0)
#endif
#define PORT_x_MUX_7_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
#define PORT_x_MUX_7_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
-/* Port F Masks */
-#define PF0 0x0001
-#define PF1 0x0002
-#define PF2 0x0004
-#define PF3 0x0008
-#define PF4 0x0010
-#define PF5 0x0020
-#define PF6 0x0040
-#define PF7 0x0080
-#define PF8 0x0100
-#define PF9 0x0200
-#define PF10 0x0400
-#define PF11 0x0800
-#define PF12 0x1000
-#define PF13 0x2000
-#define PF14 0x4000
-#define PF15 0x8000
-
-/* Port G Masks */
-#define PG0 0x0001
-#define PG1 0x0002
-#define PG2 0x0004
-#define PG3 0x0008
-#define PG4 0x0010
-#define PG5 0x0020
-#define PG6 0x0040
-#define PG7 0x0080
-#define PG8 0x0100
-#define PG9 0x0200
-#define PG10 0x0400
-#define PG11 0x0800
-#define PG12 0x1000
-#define PG13 0x2000
-#define PG14 0x4000
-#define PG15 0x8000
-
-/* Port H Masks */
-#define PH0 0x0001
-#define PH1 0x0002
-#define PH2 0x0004
-#define PH3 0x0008
-#define PH4 0x0010
-#define PH5 0x0020
-#define PH6 0x0040
-#define PH7 0x0080
-#define PH8 0x0100
-#define PH9 0x0200
-#define PH10 0x0400
-#define PH11 0x0800
-#define PH12 0x1000
-#define PH13 0x2000
-#define PH14 0x4000
-#define PH15 0x8000
-
-/* Port J Masks */
-#define PJ0 0x0001
-#define PJ1 0x0002
-#define PJ2 0x0004
-#define PJ3 0x0008
-#define PJ4 0x0010
-#define PJ5 0x0020
-#define PJ6 0x0040
-#define PJ7 0x0080
-#define PJ8 0x0100
-#define PJ9 0x0200
-#define PJ10 0x0400
-#define PJ11 0x0800
-#define PJ12 0x1000
-#define PJ13 0x2000
-#define PJ14 0x4000
-#define PJ15 0x8000
+#include "../mach-common/bits/ports-f.h"
+#include "../mach-common/bits/ports-g.h"
+#include "../mach-common/bits/ports-h.h"
+#include "../mach-common/bits/ports-j.h"
#endif
* File: include/asm-blackfin/mach-bf533/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
- * Copyright (C) 2004-2008 Analog Devices Inc.
+ * Copyright (C) 2004-2009 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
-/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
+/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */
#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000353 (1)
+#define ANOMALY_05000380 (0)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
+#define ANOMALY_05000447 (0)
+#define ANOMALY_05000448 (0)
#endif
#ifndef __BFIN_PERIPHERAL_PORT__
#define __BFIN_PERIPHERAL_PORT__
-/* Port F Masks */
-#define PF0 0x0001
-#define PF1 0x0002
-#define PF2 0x0004
-#define PF3 0x0008
-#define PF4 0x0010
-#define PF5 0x0020
-#define PF6 0x0040
-#define PF7 0x0080
-#define PF8 0x0100
-#define PF9 0x0200
-#define PF10 0x0400
-#define PF11 0x0800
-#define PF12 0x1000
-#define PF13 0x2000
-#define PF14 0x4000
-#define PF15 0x8000
+#include "../mach-common/bits/ports-f.h"
#endif
#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration Register */
#define bfin_read_SYSCR() bfin_read16(SYSCR)
#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define pSIC_RVECT ((uint32_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */
-#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
+#define pSIC_RVECT ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */
+#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
+#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val)
#define pSIC_IMASK ((uint32_t volatile *)SIC_IMASK) /* Interrupt Mask Register */
#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val)
#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */
#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */
#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
* File: include/asm-blackfin/mach-bf537/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
- * Copyright (C) 2004-2008 Analog Devices Inc.
+ * Copyright (C) 2004-2009 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
#define ANOMALY_05000301 (1)
/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
-/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
+/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
/* SCKELOW Bit Does Not Maintain State Through Hibernate */
#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000353 (1)
#define ANOMALY_05000363 (0)
+#define ANOMALY_05000380 (0)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
+#define ANOMALY_05000447 (0)
+#define ANOMALY_05000448 (0)
#endif
#define PGRE 0x0400
#define PGTE 0x0800
-/* Port F Masks */
-#define PF0 0x0001
-#define PF1 0x0002
-#define PF2 0x0004
-#define PF3 0x0008
-#define PF4 0x0010
-#define PF5 0x0020
-#define PF6 0x0040
-#define PF7 0x0080
-#define PF8 0x0100
-#define PF9 0x0200
-#define PF10 0x0400
-#define PF11 0x0800
-#define PF12 0x1000
-#define PF13 0x2000
-#define PF14 0x4000
-#define PF15 0x8000
-
-/* Port G Masks */
-#define PG0 0x0001
-#define PG1 0x0002
-#define PG2 0x0004
-#define PG3 0x0008
-#define PG4 0x0010
-#define PG5 0x0020
-#define PG6 0x0040
-#define PG7 0x0080
-#define PG8 0x0100
-#define PG9 0x0200
-#define PG10 0x0400
-#define PG11 0x0800
-#define PG12 0x1000
-#define PG13 0x2000
-#define PG14 0x4000
-#define PG15 0x8000
-
-/* Port H Masks */
-#define PH0 0x0001
-#define PH1 0x0002
-#define PH2 0x0004
-#define PH3 0x0008
-#define PH4 0x0010
-#define PH5 0x0020
-#define PH6 0x0040
-#define PH7 0x0080
-#define PH8 0x0100
-#define PH9 0x0200
-#define PH10 0x0400
-#define PH11 0x0800
-#define PH12 0x1000
-#define PH13 0x2000
-#define PH14 0x4000
-#define PH15 0x8000
+#include "../mach-common/bits/ports-f.h"
+#include "../mach-common/bits/ports-g.h"
+#include "../mach-common/bits/ports-h.h"
#endif
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
#define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
-#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX)
#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
#define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
#define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
-#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX)
#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
#define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
#define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
-#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX)
#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
#define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
#define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
-#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX)
#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
#define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */
#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
#define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
-#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX)
#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
#define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
#define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
-#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX)
#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
#define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */
#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
#define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
-#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX)
#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
#define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
#define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
-#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX)
#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
#define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */
#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
#define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
-#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX)
#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
#define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
#define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
-#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX)
#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
#define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
* File: include/asm-blackfin/mach-bf548/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
- * Copyright (C) 2004-2008 Analog Devices Inc.
+ * Copyright (C) 2004-2009 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
/* This file shoule be up to date with:
- * - Revision G, 08/07/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
+ * - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
-/* Mobile DDR Operation Not Functional */
-#define ANOMALY_05000377 (1)
/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
/* Software System Reset Corrupts PLL_LOCKCNT Register */
#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
+/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
+#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
+/* OTP Write Accesses Not Supported */
+#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
+/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
+#define ANOMALY_05000446 (1)
+/* UART IrDA Receiver Fails on Extended Bit Pulses */
+#define ANOMALY_05000447 (1)
+/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
+#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
+/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
+#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
+/* USB DMA Mode 1 Short Packet Data Corruption */
+#define ANOMALY_05000450 (1
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000125 (0)
#define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0)
+#define ANOMALY_05000278 (0)
+#define ANOMALY_05000305 (0)
#define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000363 (0)
+#define ANOMALY_05000380 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
#define PORT_x_MUX_15_FUNC_3 (PORT_x_MUX_FUNC_3 << 30)
#define PORT_x_MUX_15_FUNC_4 (PORT_x_MUX_FUNC_4 << 30)
-/* Port A Masks */
-#define PA0 0x0001
-#define PA1 0x0002
-#define PA2 0x0004
-#define PA3 0x0008
-#define PA4 0x0010
-#define PA5 0x0020
-#define PA6 0x0040
-#define PA7 0x0080
-#define PA8 0x0100
-#define PA9 0x0200
-#define PA10 0x0400
-#define PA11 0x0800
-#define PA12 0x1000
-#define PA13 0x2000
-#define PA14 0x4000
-#define PA15 0x8000
-
-/* Port B Masks */
-#define PB0 0x0001
-#define PB1 0x0002
-#define PB2 0x0004
-#define PB3 0x0008
-#define PB4 0x0010
-#define PB5 0x0020
-#define PB6 0x0040
-#define PB7 0x0080
-#define PB8 0x0100
-#define PB9 0x0200
-#define PB10 0x0400
-#define PB11 0x0800
-#define PB12 0x1000
-#define PB13 0x2000
-#define PB14 0x4000
-#define PB15 0x8000
-
-/* Port C Masks */
-#define PC0 0x0001
-#define PC1 0x0002
-#define PC2 0x0004
-#define PC3 0x0008
-#define PC4 0x0010
-#define PC5 0x0020
-#define PC6 0x0040
-#define PC7 0x0080
-#define PC8 0x0100
-#define PC9 0x0200
-#define PC10 0x0400
-#define PC11 0x0800
-#define PC12 0x1000
-#define PC13 0x2000
-#define PC14 0x4000
-#define PC15 0x8000
-
-/* Port F Masks */
-#define PD0 0x0001
-#define PD1 0x0002
-#define PD2 0x0004
-#define PD3 0x0008
-#define PD4 0x0010
-#define PD5 0x0020
-#define PD6 0x0040
-#define PD7 0x0080
-#define PD8 0x0100
-#define PD9 0x0200
-#define PD10 0x0400
-#define PD11 0x0800
-#define PD12 0x1000
-#define PD13 0x2000
-#define PD14 0x4000
-#define PD15 0x8000
-
-/* Port F Masks */
-#define PE0 0x0001
-#define PE1 0x0002
-#define PE2 0x0004
-#define PE3 0x0008
-#define PE4 0x0010
-#define PE5 0x0020
-#define PE6 0x0040
-#define PE7 0x0080
-#define PE8 0x0100
-#define PE9 0x0200
-#define PE10 0x0400
-#define PE11 0x0800
-#define PE12 0x1000
-#define PE13 0x2000
-#define PE14 0x4000
-#define PE15 0x8000
-
-/* Port F Masks */
-#define PF0 0x0001
-#define PF1 0x0002
-#define PF2 0x0004
-#define PF3 0x0008
-#define PF4 0x0010
-#define PF5 0x0020
-#define PF6 0x0040
-#define PF7 0x0080
-#define PF8 0x0100
-#define PF9 0x0200
-#define PF10 0x0400
-#define PF11 0x0800
-#define PF12 0x1000
-#define PF13 0x2000
-#define PF14 0x4000
-#define PF15 0x8000
-
-/* Port G Masks */
-#define PG0 0x0001
-#define PG1 0x0002
-#define PG2 0x0004
-#define PG3 0x0008
-#define PG4 0x0010
-#define PG5 0x0020
-#define PG6 0x0040
-#define PG7 0x0080
-#define PG8 0x0100
-#define PG9 0x0200
-#define PG10 0x0400
-#define PG11 0x0800
-#define PG12 0x1000
-#define PG13 0x2000
-#define PG14 0x4000
-#define PG15 0x8000
-
-/* Port H Masks */
-#define PH0 0x0001
-#define PH1 0x0002
-#define PH2 0x0004
-#define PH3 0x0008
-#define PH4 0x0010
-#define PH5 0x0020
-#define PH6 0x0040
-#define PH7 0x0080
-#define PH8 0x0100
-#define PH9 0x0200
-#define PH10 0x0400
-#define PH11 0x0800
-#define PH12 0x1000
-#define PH13 0x2000
-#define PH14 0x4000
-#define PH15 0x8000
-
-/* Port I Masks */
-#define PI0 0x0001
-#define PI1 0x0002
-#define PI2 0x0004
-#define PI3 0x0008
-#define PI4 0x0010
-#define PI5 0x0020
-#define PI6 0x0040
-#define PI7 0x0080
-#define PI8 0x0100
-#define PI9 0x0200
-#define PI10 0x0400
-#define PI11 0x0800
-#define PI12 0x1000
-#define PI13 0x2000
-#define PI14 0x4000
-#define PI15 0x8000
-
-/* Port I Masks */
-#define PJ0 0x0001
-#define PJ1 0x0002
-#define PJ2 0x0004
-#define PJ3 0x0008
-#define PJ4 0x0010
-#define PJ5 0x0020
-#define PJ6 0x0040
-#define PJ7 0x0080
-#define PJ8 0x0100
-#define PJ9 0x0200
-#define PJ10 0x0400
-#define PJ11 0x0800
-#define PJ12 0x1000
-#define PJ13 0x2000
-#define PJ14 0x4000
-#define PJ15 0x8000
+#include "../mach-common/bits/ports-a.h"
+#include "../mach-common/bits/ports-b.h"
+#include "../mach-common/bits/ports-c.h"
+#include "../mach-common/bits/ports-d.h"
+#include "../mach-common/bits/ports-e.h"
+#include "../mach-common/bits/ports-f.h"
+#include "../mach-common/bits/ports-g.h"
+#include "../mach-common/bits/ports-h.h"
+#include "../mach-common/bits/ports-i.h"
+#include "../mach-common/bits/ports-j.h"
#endif
#define pSICA_SWRST ((uint16_t volatile *)SICA_SWRST)
#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST)
#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST, val)
-#define pSICA_SYSCR ((uint32_t volatile *)SICA_SYSCR)
-#define bfin_read_SICA_SYSCR() bfin_read32(SICA_SYSCR)
-#define bfin_write_SICA_SYSCR(val) bfin_write32(SICA_SYSCR, val)
+#define pSICA_SYSCR ((uint16_t volatile *)SICA_SYSCR)
+#define bfin_read_SICA_SYSCR() bfin_read16(SICA_SYSCR)
+#define bfin_write_SICA_SYSCR(val) bfin_write16(SICA_SYSCR, val)
#define pSICA_RVECT ((uint16_t volatile *)SICA_RVECT)
#define bfin_read_SICA_RVECT() bfin_read16(SICA_RVECT)
#define bfin_write_SICA_RVECT(val) bfin_write16(SICA_RVECT, val)
#define pSICB_SWRST ((uint16_t volatile *)SICB_SWRST)
#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST)
#define bfin_write_SICB_SWRST(val) bfin_write16(SICB_SWRST, val)
-#define pSICB_SYSCR ((uint32_t volatile *)SICB_SYSCR)
-#define bfin_read_SICB_SYSCR() bfin_read32(SICB_SYSCR)
-#define bfin_write_SICB_SYSCR(val) bfin_write32(SICB_SYSCR, val)
+#define pSICB_SYSCR ((uint16_t volatile *)SICB_SYSCR)
+#define bfin_read_SICB_SYSCR() bfin_read16(SICB_SYSCR)
+#define bfin_write_SICB_SYSCR(val) bfin_write16(SICB_SYSCR, val)
#define pSICB_RVECT ((uint16_t volatile *)SICB_RVECT)
#define bfin_read_SICB_RVECT() bfin_read16(SICB_RVECT)
#define bfin_write_SICB_RVECT(val) bfin_write16(SICB_RVECT, val)
* File: include/asm-blackfin/mach-bf561/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
- * Copyright (C) 2004-2008 Analog Devices Inc.
+ * Copyright (C) 2004-2009 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
#define ANOMALY_05000301 (1)
/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
#define ANOMALY_05000302 (1)
-/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
+/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
/* SCKELOW Bit Does Not Maintain State Through Hibernate */
#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
#define ANOMALY_05000273 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000353 (1)
+#define ANOMALY_05000380 (0)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
+#define ANOMALY_05000447 (0)
+#define ANOMALY_05000448 (0)
#endif
#define bfin_write_WDOG_CNT(val) bfin_write_WDOGA_CNT(val)
#define bfin_write_WDOG_CTL(val) bfin_write_WDOGA_CTL(val)
#define bfin_write_WDOG_STAT(val) bfin_write_WDOGA_STAT(val)
+
+#include "ports.h"
--- /dev/null
+/*
+ * Port Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT__
+#define __BFIN_PERIPHERAL_PORT__
+
+#include "../mach-common/bits/ports-f.h"
+
+/* The non-standard PF16+ */
+#define PF16 (1 << 0)
+#define PF17 (1 << 1)
+#define PF18 (1 << 2)
+#define PF19 (1 << 3)
+#define PF20 (1 << 4)
+#define PF21 (1 << 5)
+#define PF22 (1 << 6)
+#define PF23 (1 << 7)
+#define PF24 (1 << 8)
+#define PF25 (1 << 9)
+#define PF26 (1 << 10)
+#define PF27 (1 << 11)
+#define PF28 (1 << 12)
+#define PF29 (1 << 13)
+#define PF30 (1 << 14)
+#define PF31 (1 << 15)
+#define PF32 (1 << 0)
+#define PF33 (1 << 1)
+#define PF34 (1 << 2)
+#define PF35 (1 << 3)
+#define PF36 (1 << 4)
+#define PF37 (1 << 5)
+#define PF38 (1 << 6)
+#define PF39 (1 << 7)
+#define PF40 (1 << 8)
+#define PF41 (1 << 9)
+#define PF42 (1 << 10)
+#define PF43 (1 << 11)
+#define PF44 (1 << 12)
+#define PF45 (1 << 13)
+#define PF46 (1 << 14)
+#define PF47 (1 << 15)
+
+#endif
#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1)
#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX)
#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register (16-bit) */
#define bfin_read_SWRST() bfin_read16(SWRST)
#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define pSYSCR ((uint32_t volatile *)SYSCR) /* System Configuration register */
-#define bfin_read_SYSCR() bfin_read32(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write32(SYSCR, val)
+#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */
+#define bfin_read_SYSCR() bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
#define pEVT_OVERRIDE ((uint32_t volatile *)EVT_OVERRIDE)
#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE)
#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE, val)
#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */
#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */
#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
/* SESR argument structure. Expected to reside at 0xFF900018. */
typedef struct SESR_args {
- unsigned short usFlags; /* security firmware flags */
- unsigned short usIRQMask; /* interrupt mask */
- unsigned long ulMessageSize; /* message length in bytes */
- unsigned long ulSFEntryPoint; /* entry point of secure function */
- unsigned long ulMessagePtr; /* pointer to the buffer containing */
- /* the digital signature and message */
- unsigned long ulReserved1; /* reserved */
- unsigned long ulReserved2; /* reserved */
+ unsigned short usFlags; /* security firmware flags */
+ unsigned short usIRQMask; /* interrupt mask */
+ unsigned long ulMessageSize; /* message length in bytes */
+ unsigned long ulSFEntryPoint; /* entry point of secure function */
+ unsigned long ulMessagePtr; /* pointer to the buffer containing
+ the digital signature and message */
+ unsigned long ulReserved1; /* reserved */
+ unsigned long ulReserved2; /* reserved */
} tSESR_args;
/* Secure Entry Service Routine */
-void (* const sesr)(void) = (void *)_BOOTROM_SESR;
+static void (* const sesr)(void) = (void *)_BOOTROM_SESR;
#endif
-/* SESR flags argument bitfields */
-#define SESR_FLAGS_STAY_AT_NMI 0x0000
-#define SESR_FLAGS_DROP_BELOW_NMI 0x0001
-#define SESR_FLAGS_NO_SF_DMA 0x0000
-#define SESR_FLAGS_DMA_SF_TO_RUN_DEST 0x0002
-#define SESR_FLAGS_USE_ADI_PUB_KEY 0x0000
-#define SESR_FLAGS_USE_CUST_PUB_KEY 0x0100
+/* SESR flags argument bitfields */
+#define SESR_FLAGS_STAY_AT_NMI 0x0000
+#define SESR_FLAGS_DROP_BELOW_NMI 0x0001
+#define SESR_FLAGS_NO_SF_DMA 0x0000
+#define SESR_FLAGS_DMA_SF_TO_RUN_DEST 0x0002
+#define SESR_FLAGS_USE_ADI_PUB_KEY 0x0000
+#define SESR_FLAGS_USE_CUST_PUB_KEY 0x0100
/* Bit masks for SECURE_SYSSWT */
-#define EMUDABL 0x00000001 /* Emulation Disable */
-#define RSTDABL 0x00000002 /* Reset Disable */
-#define L1IDABL 0x0000001c /* L1 Instruction Memory Disable */
-#define L1DADABL 0x000000e0 /* L1 Data Bank A Memory Disable */
-#define L1DBDABL 0x00000700 /* L1 Data Bank B Memory Disable */
-#define DMA0OVR 0x00000800 /* DMA0 Memory Access Override */
-#define DMA1OVR 0x00001000 /* DMA1 Memory Access Override */
-#define EMUOVR 0x00004000 /* Emulation Override */
-#define OTPSEN 0x00008000 /* OTP Secrets Enable */
-#define L2DABL 0x00070000 /* L2 Memory Disable */
+#define EMUDABL 0x00000001 /* Emulation Disable */
+#define RSTDABL 0x00000002 /* Reset Disable */
+#define L1IDABL 0x0000001c /* L1 Instruction Memory Disable */
+#define L1DADABL 0x000000e0 /* L1 Data Bank A Memory Disable */
+#define L1DBDABL 0x00000700 /* L1 Data Bank B Memory Disable */
+#define DMA0OVR 0x00000800 /* DMA0 Memory Access Override */
+#define DMA1OVR 0x00001000 /* DMA1 Memory Access Override */
+#define EMUOVR 0x00004000 /* Emulation Override */
+#define OTPSEN 0x00008000 /* OTP Secrets Enable */
+#define L2DABL 0x00070000 /* L2 Memory Disable */
/* Bit masks for SECURE_CONTROL */
-#define SECURE0 0x0001 /* SECURE 0 */
-#define SECURE1 0x0002 /* SECURE 1 */
-#define SECURE2 0x0004 /* SECURE 2 */
-#define SECURE3 0x0008 /* SECURE 3 */
+#define SECURE0 0x0001 /* SECURE 0 */
+#define SECURE1 0x0002 /* SECURE 1 */
+#define SECURE2 0x0004 /* SECURE 2 */
+#define SECURE3 0x0008 /* SECURE 3 */
/* Bit masks for SECURE_STATUS */
-#define SECMODE 0x0003 /* Secured Mode Control State */
-#define NMI 0x0004 /* Non Maskable Interrupt */
-#define AFVALID 0x0008 /* Authentication Firmware Valid */
-#define AFEXIT 0x0010 /* Authentication Firmware Exit */
-#define SECSTAT 0x00e0 /* Secure Status */
+#define SECMODE 0x0003 /* Secured Mode Control State */
+#define NMI 0x0004 /* Non Maskable Interrupt */
+#define AFVALID 0x0008 /* Authentication Firmware Valid */
+#define AFEXIT 0x0010 /* Authentication Firmware Exit */
+#define SECSTAT 0x00e0 /* Secure Status */
#endif
--- /dev/null
+/*
+ * Port A Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_A__
+#define __BFIN_PERIPHERAL_PORT_A__
+
+#define PA0 (1 << 0)
+#define PA1 (1 << 1)
+#define PA2 (1 << 2)
+#define PA3 (1 << 3)
+#define PA4 (1 << 4)
+#define PA5 (1 << 5)
+#define PA6 (1 << 6)
+#define PA7 (1 << 7)
+#define PA8 (1 << 8)
+#define PA9 (1 << 9)
+#define PA10 (1 << 10)
+#define PA11 (1 << 11)
+#define PA12 (1 << 12)
+#define PA13 (1 << 13)
+#define PA14 (1 << 14)
+#define PA15 (1 << 15)
+
+#endif
--- /dev/null
+/*
+ * Port B Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_B__
+#define __BFIN_PERIPHERAL_PORT_B__
+
+#define PB0 (1 << 0)
+#define PB1 (1 << 1)
+#define PB2 (1 << 2)
+#define PB3 (1 << 3)
+#define PB4 (1 << 4)
+#define PB5 (1 << 5)
+#define PB6 (1 << 6)
+#define PB7 (1 << 7)
+#define PB8 (1 << 8)
+#define PB9 (1 << 9)
+#define PB10 (1 << 10)
+#define PB11 (1 << 11)
+#define PB12 (1 << 12)
+#define PB13 (1 << 13)
+#define PB14 (1 << 14)
+#define PB15 (1 << 15)
+
+#endif
--- /dev/null
+/*
+ * Port C Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_C__
+#define __BFIN_PERIPHERAL_PORT_C__
+
+#define PC0 (1 << 0)
+#define PC1 (1 << 1)
+#define PC2 (1 << 2)
+#define PC3 (1 << 3)
+#define PC4 (1 << 4)
+#define PC5 (1 << 5)
+#define PC6 (1 << 6)
+#define PC7 (1 << 7)
+#define PC8 (1 << 8)
+#define PC9 (1 << 9)
+#define PC10 (1 << 10)
+#define PC11 (1 << 11)
+#define PC12 (1 << 12)
+#define PC13 (1 << 13)
+#define PC14 (1 << 14)
+#define PC15 (1 << 15)
+
+#endif
--- /dev/null
+/*
+ * Port D Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_D__
+#define __BFIN_PERIPHERAL_PORT_D__
+
+#define PD0 (1 << 0)
+#define PD1 (1 << 1)
+#define PD2 (1 << 2)
+#define PD3 (1 << 3)
+#define PD4 (1 << 4)
+#define PD5 (1 << 5)
+#define PD6 (1 << 6)
+#define PD7 (1 << 7)
+#define PD8 (1 << 8)
+#define PD9 (1 << 9)
+#define PD10 (1 << 10)
+#define PD11 (1 << 11)
+#define PD12 (1 << 12)
+#define PD13 (1 << 13)
+#define PD14 (1 << 14)
+#define PD15 (1 << 15)
+
+#endif
--- /dev/null
+/*
+ * Port E Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_E__
+#define __BFIN_PERIPHERAL_PORT_E__
+
+#define PE0 (1 << 0)
+#define PE1 (1 << 1)
+#define PE2 (1 << 2)
+#define PE3 (1 << 3)
+#define PE4 (1 << 4)
+#define PE5 (1 << 5)
+#define PE6 (1 << 6)
+#define PE7 (1 << 7)
+#define PE8 (1 << 8)
+#define PE9 (1 << 9)
+#define PE10 (1 << 10)
+#define PE11 (1 << 11)
+#define PE12 (1 << 12)
+#define PE13 (1 << 13)
+#define PE14 (1 << 14)
+#define PE15 (1 << 15)
+
+#endif
--- /dev/null
+/*
+ * Port F Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_F__
+#define __BFIN_PERIPHERAL_PORT_F__
+
+#define PF0 (1 << 0)
+#define PF1 (1 << 1)
+#define PF2 (1 << 2)
+#define PF3 (1 << 3)
+#define PF4 (1 << 4)
+#define PF5 (1 << 5)
+#define PF6 (1 << 6)
+#define PF7 (1 << 7)
+#define PF8 (1 << 8)
+#define PF9 (1 << 9)
+#define PF10 (1 << 10)
+#define PF11 (1 << 11)
+#define PF12 (1 << 12)
+#define PF13 (1 << 13)
+#define PF14 (1 << 14)
+#define PF15 (1 << 15)
+
+#endif
--- /dev/null
+/*
+ * Port G Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_G__
+#define __BFIN_PERIPHERAL_PORT_G__
+
+#define PG0 (1 << 0)
+#define PG1 (1 << 1)
+#define PG2 (1 << 2)
+#define PG3 (1 << 3)
+#define PG4 (1 << 4)
+#define PG5 (1 << 5)
+#define PG6 (1 << 6)
+#define PG7 (1 << 7)
+#define PG8 (1 << 8)
+#define PG9 (1 << 9)
+#define PG10 (1 << 10)
+#define PG11 (1 << 11)
+#define PG12 (1 << 12)
+#define PG13 (1 << 13)
+#define PG14 (1 << 14)
+#define PG15 (1 << 15)
+
+#endif
--- /dev/null
+/*
+ * Port H Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_H__
+#define __BFIN_PERIPHERAL_PORT_H__
+
+#define PH0 (1 << 0)
+#define PH1 (1 << 1)
+#define PH2 (1 << 2)
+#define PH3 (1 << 3)
+#define PH4 (1 << 4)
+#define PH5 (1 << 5)
+#define PH6 (1 << 6)
+#define PH7 (1 << 7)
+#define PH8 (1 << 8)
+#define PH9 (1 << 9)
+#define PH10 (1 << 10)
+#define PH11 (1 << 11)
+#define PH12 (1 << 12)
+#define PH13 (1 << 13)
+#define PH14 (1 << 14)
+#define PH15 (1 << 15)
+
+#endif
--- /dev/null
+/*
+ * Port I Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_I__
+#define __BFIN_PERIPHERAL_PORT_I__
+
+#define PI0 (1 << 0)
+#define PI1 (1 << 1)
+#define PI2 (1 << 2)
+#define PI3 (1 << 3)
+#define PI4 (1 << 4)
+#define PI5 (1 << 5)
+#define PI6 (1 << 6)
+#define PI7 (1 << 7)
+#define PI8 (1 << 8)
+#define PI9 (1 << 9)
+#define PI10 (1 << 10)
+#define PI11 (1 << 11)
+#define PI12 (1 << 12)
+#define PI13 (1 << 13)
+#define PI14 (1 << 14)
+#define PI15 (1 << 15)
+
+#endif
--- /dev/null
+/*
+ * Port J Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_J__
+#define __BFIN_PERIPHERAL_PORT_J__
+
+#define PJ0 (1 << 0)
+#define PJ1 (1 << 1)
+#define PJ2 (1 << 2)
+#define PJ3 (1 << 3)
+#define PJ4 (1 << 4)
+#define PJ5 (1 << 5)
+#define PJ6 (1 << 6)
+#define PJ7 (1 << 7)
+#define PJ8 (1 << 8)
+#define PJ9 (1 << 9)
+#define PJ10 (1 << 10)
+#define PJ11 (1 << 11)
+#define PJ12 (1 << 12)
+#define PJ13 (1 << 13)
+#define PJ14 (1 << 14)
+#define PJ15 (1 << 15)
+
+#endif
--- /dev/null
+/*
+ * net.h - misc Blackfin network helpers
+ *
+ * Copyright (c) 2008-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ASM_BFIN_RAND_MAC__
+#define __ASM_BFIN_RAND_MAC__
+
+/* If the board does not have a real MAC assigned to it, then generate a
+ * locally administrated pseudo-random one based on CYCLES and compile date.
+ */
+static inline void bfin_gen_rand_mac(uchar *mac_addr)
+{
+ /* make something up */
+ const char s[] = __DATE__;
+ size_t i;
+ u32 cycles;
+ for (i = 0; i < 6; ++i) {
+ asm("%0 = CYCLES;" : "=r" (cycles));
+ mac_addr[i] = cycles ^ s[i];
+ }
+ mac_addr[0] = (mac_addr[0] | 0x02) & ~0x01; /* make it local unicast */
+}
+
+#endif
#define CONFIG_SYS_NAND_CS_DIST 0x200
#define CONFIG_SYS_NAND_SIZE 0x8000
-#define CONFIG_SYS_NAND0_BASE (CONFIG_SYS_CCSRBAR + 0x03010000)
-#define CONFIG_SYS_NAND1_BASE (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST)
-#define CONFIG_SYS_NAND2_BASE (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST)
-#define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
-
-#if (CONFIG_SYS_MAX_NAND_DEVICE == 1)
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
-#elif (CONFIG_SYS_MAX_NAND_DEVICE == 2)
-#define CONFIG_SYS_NAND_QUIET_TEST 1
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
- CONFIG_SYS_NAND1_BASE, \
-}
-#elif (CONFIG_SYS_MAX_NAND_DEVICE == 4)
-#define CONFIG_SYS_NAND_QUIET_TEST 1
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
- CONFIG_SYS_NAND1_BASE, \
- CONFIG_SYS_NAND2_BASE, \
- CONFIG_SYS_NAND3_BASE, \
-}
-#endif
+#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_CCSRBAR + 0x03010000)
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define CONFIG_SYS_NAND_MAX_CHIPS 2 /* Number of chips per device */
/* CS3 for NAND Flash */
-#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_NAND0_BASE & BR_BA) | BR_PS_8 | \
- BR_MS_UPMB | BR_V)
+#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_NAND_BASE & BR_BA) | \
+ BR_PS_8 | BR_MS_UPMB | BR_V)
#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | OR_UPM_BI)
-#define NAND_BIG_DELAY_US 25 /* max tR for Samsung devices */
+#define NAND_BIG_DELAY_US 25 /* max tR for Samsung devices */
#endif /* CONFIG_NAND */
#endif
#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
#define CONFIG_SYS_HID2 HID2_HBE
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
* U-boot - Configuration file for BF533 EZKIT board
*/
-#ifndef __CONFIG_EZKIT533_H__
-#define __CONFIG_EZKIT533_H__
+#ifndef __CONFIG_BF533_EZKIT_H__
+#define __CONFIG_BF533_EZKIT_H__
#include <asm/blackfin-config-pre.h>
-#define CONFIG_BAUDRATE 57600
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_SYS_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU bf533-0.3
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-#define CONFIG_SYS_LONGHELP 1
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_LOADADDR 0x01000000 /* default load address */
-#define CONFIG_BOOTCOMMAND "tftp $(loadaddr) linux"
-/* #define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" */
-#define CONFIG_DRIVER_SMC91111 1
-#define CONFIG_SMC91111_BASE 0x20310300
+/*
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 27000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
+#define CONFIG_VCO_MULT 22
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 5
-#if 0
-#define CONFIG_MII
-#define CONFIG_SYS_DISCOVER_PHY
-#endif
-#define CONFIG_RTC_BFIN 1
-#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
-
-#define CONFIG_PANIC_HANG 1
-
-#define CONFIG_BFIN_CPU bf533-0.3
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
-/* This sets the default state of the cache on U-Boot's boot */
-#define CONFIG_ICACHE_ON
-#define CONFIG_DCACHE_ON
-
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 27000000
-/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
-/* 1=CLKIN/2 */
-#define CONFIG_CLKIN_HALF 0
-/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
-/* 1=bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
-/* Values can range from 1-64 */
-#define CONFIG_VCO_MULT 22
-/* CONFIG_CCLK_DIV controls what the core clock divider is */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
-/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
-/* Values can range from 2-65535 */
-/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
-#define CONFIG_SPI_BAUD 2
-#define CONFIG_SPI_BAUD_INITBLOCK 4
-
-#if ( CONFIG_CLKIN_HALF == 0 )
-#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_SIZE 32
+/* Early EZKITs had 32megs, but later have 64megs */
+#if (CONFIG_MEM_SIZE == 64)
+# define CONFIG_MEM_ADD_WDTH 10
#else
-#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
+# define CONFIG_MEM_ADD_WDTH 9
#endif
-#if (CONFIG_PLL_BYPASS == 0)
-#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
-#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
-#else
-#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
-#endif
+#define CONFIG_EBIU_SDRRC_VAL 0x398
+#define CONFIG_EBIU_SDGCTL_VAL 0x91118d
-#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */
-#define CONFIG_MEM_MT48LC16M16A2TG_75 1
+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-#define CONFIG_LOADS_ECHO 1
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
/*
- * BOOTP options
+ * Network Settings
*/
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
+#define ADI_CMDS_NETWORK 1
+#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_SMC91111_BASE 0x20310300
+#define SMC91111_EEPROM_INIT() \
+ do { \
+ *pFIO_DIR |= PF1; \
+ *pFIO_FLAG_S = PF1; \
+ SSYNC(); \
+ } while (0)
+#define CONFIG_HOSTNAME bf533-ezkit
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
/*
- * Command line configuration.
+ * Flash Settings
*/
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_DATE
-
-
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off console=ttyBF0,57600"
-
-#define CONFIG_SYS_PROMPT "bfin> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 1024 * 1024) /* 1 ... 31 MB in DRAM */
-#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 10 ms ticks */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024)
#define CONFIG_SYS_FLASH_BASE 0x20000000
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
-#define CONFIG_SYS_GBL_DATA_SIZE 0x4000
-#define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4)
-
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_FLASH0_BASE 0x20000000
-#define CONFIG_SYS_FLASH1_BASE 0x20200000
-#define CONFIG_SYS_FLASH2_BASE 0x20280000
-#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 40 /* max number of sectors on one chip */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_SYS_MAX_FLASH_BANKS 3
+#define CONFIG_SYS_MAX_FLASH_SECT 40
+#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR 0x20020000
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
-
-/* JFFS Partition offset set */
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-/* 512k reserved for u-boot */
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
-
-
-/*
- * Stack sizes
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-
-#define POLL_MODE 1
+#define CONFIG_ENV_SECT_SIZE 0x10000
#define FLASH_TOT_SECT 40
-#define FLASH_SIZE 0x220000
-#define CONFIG_SYS_FLASH_SIZE 0x220000
-/*
- * Initialize PSD4256 registers for using I2C
- */
-#define CONFIG_MISC_INIT_R
/*
- * I2C settings
+ * I2C Settings
* By default PF1 is used as SDA and PF0 as SCL on the Stamp board
*/
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PF_SCL PF0
-#define PF_SDA PF1
-
-#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;")
-#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
-#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
-#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
-#define I2C_SDA(bit) if(bit) { \
- *pFIO_FLAG_S = PF_SDA; \
- asm("ssync;"); \
- } \
- else { \
- *pFIO_FLAG_C = PF_SDA; \
- asm("ssync;"); \
- }
-#define I2C_SCL(bit) if(bit) { \
- *pFIO_FLAG_S = PF_SCL; \
- asm("ssync;"); \
- } \
- else { \
- *pFIO_FLAG_C = PF_SCL; \
- asm("ssync;"); \
- }
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+#define CONFIG_SOFT_I2C
+#ifdef CONFIG_SOFT_I2C
+#define PF_SCL PF0
+#define PF_SDA PF1
+#define I2C_INIT \
+ do { \
+ *pFIO_DIR |= PF_SCL; \
+ SSYNC(); \
+ } while (0)
+#define I2C_ACTIVE \
+ do { \
+ *pFIO_DIR |= PF_SDA; \
+ *pFIO_INEN &= ~PF_SDA; \
+ SSYNC(); \
+ } while (0)
+#define I2C_TRISTATE \
+ do { \
+ *pFIO_DIR &= ~PF_SDA; \
+ *pFIO_INEN |= PF_SDA; \
+ SSYNC(); \
+ } while (0)
+#define I2C_READ ((*pFIO_FLAG_D & PF_SDA) != 0)
+#define I2C_SDA(bit) \
+ do { \
+ if (bit) \
+ *pFIO_FLAG_S = PF_SDA; \
+ else \
+ *pFIO_FLAG_C = PF_SDA; \
+ SSYNC(); \
+ } while (0)
+#define I2C_SCL(bit) \
+ do { \
+ if (bit) \
+ *pFIO_FLAG_S = PF_SCL; \
+ else \
+ *pFIO_FLAG_C = PF_SCL; \
+ SSYNC(); \
+ } while (0)
+#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
#define CONFIG_SYS_I2C_SPEED 50000
#define CONFIG_SYS_I2C_SLAVE 0
+#endif
-#define CONFIG_SYS_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
-#define CONFIG_EBIU_SDRRC_VAL 0x398
-#define CONFIG_EBIU_SDGCTL_VAL 0x91118d
-#define CONFIG_EBIU_SDBCTL_VAL 0x13
+/*
+ * Misc Settings
+ */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE 0
+
-#define CONFIG_EBIU_AMGCTL_VAL 0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
#include <asm/blackfin-config-post.h>
* U-boot - Configuration file for BF533 STAMP board
*/
-#ifndef __CONFIG_STAMP_H__
-#define __CONFIG_STAMP_H__
+#ifndef __CONFIG_BF533_STAMP_H__
+#define __CONFIG_BF533_STAMP_H__
#include <asm/blackfin-config-pre.h>
-#define CONFIG_RTC_BFIN 1
-
-#define CONFIG_PANIC_HANG 1
-
-#define CONFIG_BFIN_CPU bf533-0.3
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
-/* This sets the default state of the cache on U-Boot's boot */
-#define CONFIG_ICACHE_ON
-#define CONFIG_DCACHE_ON
/*
- * Board settings
+ * Processor Settings
*/
-#define CONFIG_DRIVER_SMC91111 1
-#define CONFIG_SMC91111_BASE 0x20300300
-
-/* FLASH/ETHERNET uses the same address range */
-#define SHARED_RESOURCES 1
+#define CONFIG_BFIN_CPU bf533-0.3
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-/* Is I2C bit-banged? */
-#define CONFIG_SOFT_I2C 1
/*
- * Software (bit-bang) I2C driver configuration
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
-#define PF_SCL PF3
-#define PF_SDA PF2
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 11059200
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
+#define CONFIG_VCO_MULT 45
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 5
-/*
- * Video splash screen support
- */
-#define CONFIG_VIDEO 0
/*
- * Clock settings
+ * Memory Settings
*/
+#define CONFIG_MEM_ADD_WDTH 11
+#define CONFIG_MEM_SIZE 128
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 11059200
-/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
-/* 1=CLKIN/2 */
-#define CONFIG_CLKIN_HALF 0
-/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
-/* 1=bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
-/* Values can range from 1-64 */
-#define CONFIG_VCO_MULT 36
-/* CONFIG_CCLK_DIV controls what the core clock divider is */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
-/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
-/* Values can range from 2-65535 */
-/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
-#define CONFIG_SPI_BAUD 2
-#define CONFIG_SPI_BAUD_INITBLOCK 4
-
-/*
- * Network settings
- */
+#define CONFIG_EBIU_SDRRC_VAL 0x268
+#define CONFIG_EBIU_SDGCTL_VAL 0x911109
-#if (CONFIG_DRIVER_SMC91111)
-#if 0
-#define CONFIG_MII
-#endif
+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
+#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
-/* network support */
-#define CONFIG_IPADDR 192.168.0.15
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_GATEWAYIP 192.168.0.1
-#define CONFIG_SERVERIP 192.168.0.2
-#define CONFIG_HOSTNAME STAMP
-#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
-/* To remove hardcoding and enable MAC storage in EEPROM */
-/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
-#endif /* CONFIG_DRIVER_SMC91111 */
/*
- * Flash settings
+ * Network Settings
*/
+#define ADI_CMDS_NETWORK 1
+#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_SMC91111_BASE 0x20300300
+#define SMC91111_EEPROM_INIT() \
+ do { \
+ *pFIO_DIR |= PF1; \
+ *pFIO_FLAG_S = PF1; \
+ SSYNC(); \
+ } while (0)
+#define CONFIG_HOSTNAME bf533-stamp
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET
-
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
-
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_ENV_OFFSET 0x4000
-#define CONFIG_ENV_HEADER (CONFIG_ENV_OFFSET + 0x12A) /* 0x12A is the length of LDR file header */
-#else
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR 0x20004000
-#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
-#endif
-
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
-#define ENV_IS_EMBEDDED
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */
-#define CONFIG_SYS_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
-
-/* JFFS Partition offset set */
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-/* 512k reserved for u-boot */
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
-
-/*
- * following timeouts shall be used once the
- * Flash real protection is enabled
- */
-#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
-
-/*
- * SDRAM settings & memory map
- */
-
-#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */
-#define CONFIG_MEM_MT48LC64M4A2FB_7E 1
-
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-#define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 *1024)
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MAX_RAM_SIZE - 0x80000 - 1)
-#define CONFIG_LOADADDR 0x01000000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_GBL_DATA_SIZE 0x4000 /* Reserve 16k for Global Data */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - 0x40000)
-#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
-#define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4)
-
-/* Check to make sure everything fits in SDRAM */
-#if ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE)
- #error Memory Map does not fit into configuration
-#endif
-
-#if ( CONFIG_CLKIN_HALF == 0 )
-#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
-#else
-#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
-#endif
-
-#if (CONFIG_PLL_BYPASS == 0)
-#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
-#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
-#else
-#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
-#endif
/*
- * Command settings
+ * Flash Settings
*/
-
-#define CONFIG_SYS_LONGHELP 1
-#define CONFIG_CMDLINE_EDITING 1
-
-#define CONFIG_SYS_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */
-
-/* configuration lookup from the BOOTP/DHCP server, */
-/* but not try to load any image using TFTP */
-
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
-#define CONFIG_BOOTCOMMAND "run ramboot"
-
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
-
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
- "$(rootpath) console=ttyBF0,57600\0" \
- "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
- "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
- "ramboot=tftpboot $(loadaddr) linux; " \
- "run ramargs;run addip;bootelf\0" \
- "nfsboot=tftpboot $(loadaddr) linux; " \
- "run nfsargs;run addip;bootelf\0" \
- "flashboot=bootm 0x20100000\0" \
- "update=tftpboot $(loadaddr) u-boot.bin; " \
- "protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \
- "cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
- ""
-
-#ifdef CONFIG_SOFT_I2C
-#if (!CONFIG_SOFT_I2C)
-#undef CONFIG_SOFT_I2C
-#endif
-#endif
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 67
/*
- * BOOTP options
+ * SPI Settings
*/
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ 30000000
+#define CONFIG_SF_DEFAULT_HZ 30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_WINBOND
/*
- * Command line configuration.
+ * Env Storage Settings
*/
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_DATE
-
-#if (CONFIG_DRIVER_SMC91111)
-#define CONFIG_CMD_PING
-#endif
-
-#if (CONFIG_SOFT_I2C)
-#define CONFIG_CMD_I2C
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET 0x4000
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OFFSET 0x4000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x2000
#endif
-
-#define CONFIG_CMD_DHCP
-
-
-/*
- * Console settings
- */
-
-#define CONFIG_BAUDRATE 57600
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_SYS_PROMPT "bfin> " /* Monitor Command Prompt */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#define ENV_IS_EMBEDDED
#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define ENV_IS_EMBEDDED_CUSTOM
#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_LOADS_ECHO 1
/*
- * I2C settings
+ * I2C Settings
* By default PF2 is used as SDA and PF3 as SCL on the Stamp board
*/
-#if (CONFIG_SOFT_I2C)
-
-#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;")
-#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
-#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
-#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
-#define I2C_SDA(bit) if(bit) { \
- *pFIO_FLAG_S = PF_SDA; \
- asm("ssync;"); \
- } \
- else { \
- *pFIO_FLAG_C = PF_SDA; \
- asm("ssync;"); \
- }
-#define I2C_SCL(bit) if(bit) { \
- *pFIO_FLAG_S = PF_SCL; \
- asm("ssync;"); \
- } \
- else { \
- *pFIO_FLAG_C = PF_SCL; \
- asm("ssync;"); \
- }
+#define CONFIG_SOFT_I2C
+#ifdef CONFIG_SOFT_I2C
+#define PF_SCL PF3
+#define PF_SDA PF2
+#define I2C_INIT \
+ do { \
+ *pFIO_DIR |= PF_SCL; \
+ SSYNC(); \
+ } while (0)
+#define I2C_ACTIVE \
+ do { \
+ *pFIO_DIR |= PF_SDA; \
+ *pFIO_INEN &= ~PF_SDA; \
+ SSYNC(); \
+ } while (0)
+#define I2C_TRISTATE \
+ do { \
+ *pFIO_DIR &= ~PF_SDA; \
+ *pFIO_INEN |= PF_SDA; \
+ SSYNC(); \
+ } while (0)
+#define I2C_READ ((*pFIO_FLAG_D & PF_SDA) != 0)
+#define I2C_SDA(bit) \
+ do { \
+ if (bit) \
+ *pFIO_FLAG_S = PF_SDA; \
+ else \
+ *pFIO_FLAG_C = PF_SDA; \
+ SSYNC(); \
+ } while (0)
+#define I2C_SCL(bit) \
+ do { \
+ if (bit) \
+ *pFIO_FLAG_S = PF_SCL; \
+ else \
+ *pFIO_FLAG_C = PF_SCL; \
+ SSYNC(); \
+ } while (0)
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
#define CONFIG_SYS_I2C_SPEED 50000
#define CONFIG_SYS_I2C_SLAVE 0
-#endif /* CONFIG_SOFT_I2C */
+#endif
+
/*
- * Compact Flash settings
+ * Compact Flash / IDE / ATA Settings
*/
/* Enabled below option for CF support */
-/* #define CONFIG_STAMP_CF 1 */
-
-#if defined(CONFIG_STAMP_CF) && defined(CONFIG_CMD_IDE)
-
-#define CONFIG_MISC_INIT_R 1
+/* #define CONFIG_STAMP_CF */
+#if defined(CONFIG_STAMP_CF)
+#define CONFIG_MISC_INIT_R
#define CONFIG_DOS_PARTITION 1
-/*
- * IDE/ATA stuff
- */
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
#undef CONFIG_IDE_LED /* no led for ide supported */
#undef CONFIG_IDE_RESET /* no reset for ide supported */
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS 1
+#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
#define CONFIG_SYS_ATA_BASE_ADDR 0x20200000
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */
+#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
+#define CONFIG_SYS_ATA_ALT_OFFSET 0x0007 /* alternate registers */
#define CONFIG_SYS_ATA_STRIDE 2
+
+#undef CONFIG_EBIU_AMBCTL1_VAL
+#define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2
#endif
+
/*
- * Miscellaneous configurable options
+ * Misc Settings
*/
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE 0
-#define CONFIG_SYS_HZ 1000 /* 1ms time tick */
-
-#define CONFIG_SYS_BOOTM_LEN 0x4000000/* Large Image Length, set to 64 Meg */
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
+/* FLASH/ETHERNET uses the same async bank */
+#define SHARED_RESOURCES 1
-#define CONFIG_SPI
+/* define to enable boot progress via leds */
+/* #define CONFIG_SHOW_BOOT_PROGRESS */
-#ifdef CONFIG_VIDEO
-#if (CONFIG_VIDEO)
-#define CONFIG_SPLASH_SCREEN 1
-#define CONFIG_SILENT_CONSOLE 1
-#else
-#undef CONFIG_VIDEO
+/* define to enable run status via led */
+/* #define CONFIG_STATUS_LED */
+#ifdef CONFIG_STATUS_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+#ifndef __ASSEMBLY__
+typedef unsigned int led_id_t;
+void __led_init(led_id_t mask, int state);
+void __led_set(led_id_t mask, int state);
+void __led_toggle(led_id_t mask);
#endif
+/* use LED1 to indicate booting/alive */
+#define STATUS_LED_BOOT 0
+#define STATUS_LED_BIT 1
+#define STATUS_LED_STATE STATUS_LED_ON
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
+/* use LED2 to indicate crash */
+#define STATUS_LED_CRASH 1
+#define STATUS_LED_BIT1 2
+#define STATUS_LED_STATE1 STATUS_LED_ON
+#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
#endif
-/*
- * FLASH organization and environment definitions
- */
+/* define to enable splash screen support */
+/* #define CONFIG_VIDEO */
-#define CONFIG_EBIU_SDRRC_VAL 0x268
-#define CONFIG_EBIU_SDGCTL_VAL 0x911109
-#define CONFIG_EBIU_SDBCTL_VAL 0x37
-#define CONFIG_EBIU_AMGCTL_VAL 0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
-#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
-#define CF_CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
#include <asm/blackfin-config-post.h>
* U-boot - Configuration file for BF537 STAMP board
*/
-#ifndef __CONFIG_BF537_H__
-#define __CONFIG_BF537_H__
+#ifndef __CONFIG_BF537_STAMP_H__
+#define __CONFIG_BF537_STAMP_H__
#include <asm/blackfin-config-pre.h>
-#define CONFIG_SYS_LONGHELP 1
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_BAUDRATE 57600
-/* Set default serial console for bf537 */
-#define CONFIG_UART_CONSOLE 0
-#define CONFIG_BOOTDELAY 5
-/* define CONFIG_BF537_STAMP_LEDCMD to enable LED command*/
-/*#define CONFIG_BF537_STAMP_LEDCMD 1*/
-
-#define CONFIG_PANIC_HANG 1
-#define CONFIG_BFIN_CPU bf537-0.2
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
-#define CONFIG_BFIN_MAC
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU bf537-0.2
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-/* This sets the default state of the cache on U-Boot's boot */
-#define CONFIG_ICACHE_ON
-#define CONFIG_DCACHE_ON
-/* Define if want to do post memory test */
-#undef CONFIG_POST_TEST
-
-#define CONFIG_RTC_BFIN 1
-#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
-
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 25000000
-/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
-/* 1=CLKIN/2 */
-#define CONFIG_CLKIN_HALF 0
-/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
-/* 1=bypass PLL*/
-#define CONFIG_PLL_BYPASS 0
-/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
-/* Values can range from 1-64 */
+/*
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 20
-/* CONFIG_CCLK_DIV controls what the core clock divider is */
-/* Values can be 1, 2, 4, or 8 ONLY */
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
-/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
-/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
-/* Values can range from 2-65535 */
-/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
-#define CONFIG_SPI_BAUD 2
-#define CONFIG_SPI_BAUD_INITBLOCK 4
-
-#if ( CONFIG_CLKIN_HALF == 0 )
-#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
-#else
-#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
-#endif
-
-#if (CONFIG_PLL_BYPASS == 0)
-#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
-#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
-#else
-#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
-#endif
-
-#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */
-#define CONFIG_MEM_MT48LC32M8A2_75 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 4
-#define CONFIG_LOADS_ECHO 1
/*
- * rarpb, bootp or dhcp commands will perform only a
- * configuration lookup from the BOOTP/DHCP server
- * but not try to load any image using TFTP
+ * Memory Settings
*/
-#define CONFIG_SYS_AUTOLOAD "no"
+#define CONFIG_MEM_ADD_WDTH 10
+#define CONFIG_MEM_SIZE 64
+
+#define CONFIG_EBIU_SDRRC_VAL 0x306
+#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
+
+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
+
/*
* Network Settings
*/
-/* network support */
-#ifdef CONFIG_BFIN_MAC
-#define CONFIG_IPADDR 192.168.0.15
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_GATEWAYIP 192.168.0.1
-#define CONFIG_SERVERIP 192.168.0.2
-#define CONFIG_HOSTNAME BF537
+#ifndef __ADSPBF534__
+#define ADI_CMDS_NETWORK 1
+#define CONFIG_BFIN_MAC
+#define CONFIG_NETCONSOLE 1
+#define CONFIG_NET_MULTI 1
#endif
-
-#define CONFIG_ROOTPATH /romfs
+#define CONFIG_HOSTNAME bf537-stamp
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-/* This is the routine that copies the MAC in Flash to the 'ethaddr' setting */
-
-#define CONFIG_SYS_LONGHELP 1
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
-#define CONFIG_BOOTCOMMAND "run ramboot"
-
-#if defined(CONFIG_POST_TEST)
-/* POST support */
-#define CONFIG_POST ( CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_UART | \
- CONFIG_SYS_POST_FLASH | \
- CONFIG_SYS_POST_ETHER | \
- CONFIG_SYS_POST_LED | \
- CONFIG_SYS_POST_BUTTON)
-#else
-#undef CONFIG_POST
-#endif
-#ifdef CONFIG_POST
-#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
-#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
-#endif
-
-/* CF-CARD IDE-HDD Support */
-
-/* #define CONFIG_BFIN_TRUE_IDE */ /* Add CF flash card support */
-/* #define CONFIG_BFIN_CF_IDE */ /* Add CF flash card support */
-/* #define CONFIG_BFIN_HDD_IDE */ /* Add IDE Disk Drive (HDD) support */
-
-#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)
-# define CONFIG_BFIN_IDE 1
-#endif
-
-/*#define CONFIG_BF537_NAND */ /* Add nand flash support */
-
-#define CONFIG_NETCONSOLE 1
-#define CONFIG_NET_MULTI 1
/*
- * BOOTP options
+ * Flash Settings
*/
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
+#define CONFIG_SYS_MAX_FLASH_SECT 71
/*
- * Command line configuration.
+ * SPI Settings
*/
-#include <config_cmd_default.h>
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ 30000000
+#define CONFIG_SF_DEFAULT_HZ 30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_WINBOND
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_DATE
-#ifndef CONFIG_BFIN_MAC
-#undef CONFIG_CMD_NET
+/*
+ * Env Storage Settings
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET 0x4000
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x2000
#else
-#define CONFIG_CMD_PING
-#endif
-
-#if defined(CONFIG_BFIN_CF_IDE) \
- || defined(CONFIG_BFIN_HDD_IDE) \
- || defined(CONFIG_BFIN_TRUE_IDE)
-#define CONFIG_CMD_IDE
-#endif
-
-#define CONFIG_CMD_DHCP
-
-#if defined(CONFIG_POST)
-#define CONFIG_CMD_DIAG
-#endif
-
-#ifdef CONFIG_BF537_NAND
-#define CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OFFSET 0x4000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x2000
#endif
-
-
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
-#define CONFIG_LOADADDR 0x1000000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):eth0:off\0" \
- "ramboot=tftpboot $(loadaddr) linux;" \
- "run ramargs;run addip;bootelf\0" \
- "nfsboot=tftpboot $(loadaddr) linux;" \
- "run nfsargs;run addip;bootelf\0" \
- "flashboot=bootm 0x20100000\0" \
- "update=tftpboot $(loadaddr) u-boot.bin;" \
- "protect off 0x20000000 0x2007FFFF;" \
- "erase 0x20000000 0x2007FFFF;cp.b 0x1000000 0x20000000 $(filesize)\0" \
- ""
-
-#define CONFIG_SYS_PROMPT "bfin> " /* Monitor Command Prompt */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#define ENV_IS_EMBEDDED
#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define ENV_IS_EMBEDDED_CUSTOM
#endif
-#define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024*1024)
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_MEMTEST_START 0x0 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 1024*1024) /* 1 ... 63 MB in DRAM */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 10 ms ticks */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 71 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
-#define CONFIG_SYS_GBL_DATA_SIZE 0x4000
-#define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4)
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_ENV_OFFSET 0x4000
-#define CONFIG_ENV_HEADER (CONFIG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
-#else
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR 0x20004000
-#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
-#endif
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
-#define ENV_IS_EMBEDDED
-
-/* JFFS Partition offset set */
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-/* 512k reserved for u-boot */
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_SYS_I2C_SLAVE 0
-#define CONFIG_SPI
/*
- * Stack sizes
+ * SPI_MMC Settings
*/
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#define CONFIG_MMC
+#define CONFIG_BFIN_SPI_MMC
-#define POLL_MODE 1
-#define FLASH_TOT_SECT 71
-#define FLASH_SIZE 0x400000
-#define CONFIG_SYS_FLASH_SIZE 0x400000
/*
- * Board NAND Infomation
+ * NAND Settings
*/
+/* #define CONFIG_BF537_NAND */
+#ifdef CONFIG_BF537_NAND
+# define CONFIG_CMD_NAND
+#endif
#define CONFIG_SYS_NAND_ADDR 0x20212000
#define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND_ADDR
#define NAND_MAX_FLOORS 1
#define BFIN_NAND_READY PF3
-#define NAND_WAIT_READY(nand) \
- do { \
- int timeout = 0; \
- while(!(*pPORTFIO & PF3)) \
- if (timeout++ > 100000) \
- break; \
+#define NAND_WAIT_READY(nand) \
+ do { \
+ int timeout = 0; \
+ while (!(*pPORTFIO & PF3)) \
+ if (timeout++ > 100000) \
+ break; \
} while (0)
-#define BFIN_NAND_CLE (1<<2) /* A2 -> Command Enable */
-#define BFIN_NAND_ALE (1<<1) /* A1 -> Address Enable */
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
-/*
- * Initialize PSD4256 registers for using I2C
- */
-#define CONFIG_MISC_INIT_R
+#define BFIN_NAND_CLE (1 << 2) /* A2 -> Command Enable */
+#define BFIN_NAND_ALE (1 << 1) /* A1 -> Address Enable */
+#define WRITE_NAND_COMMAND(d, adr) bfin_write8(adr | BFIN_NAND_CLE, d)
+#define WRITE_NAND_ADDRESS(d, adr) bfin_write8(adr | BFIN_NAND_ALE, d)
+#define WRITE_NAND(d, adr) bfin_write8(adr, d)
+#define READ_NAND(adr) bfin_read8(adr)
-#define CONFIG_SYS_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
/*
- * I2C settings
+ * CF-CARD IDE-HDD Support
*/
-#define CONFIG_HARD_I2C 1
-#define CONFIG_BFIN_TWI_I2C 1
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0
-
-#define CONFIG_EBIU_SDRRC_VAL 0x306
-#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
-#define CONFIG_EBIU_SDBCTL_VAL 0x25
-
-#define CONFIG_EBIU_AMGCTL_VAL 0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-
-/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
-/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
-#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
- ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
-#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \
- B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
-*/
+/* #define CONFIG_BFIN_TRUE_IDE */ /* Add CF flash card support */
+/* #define CONFIG_BFIN_CF_IDE */ /* Add CF flash card support */
+/* #define CONFIG_BFIN_HDD_IDE */ /* Add IDE Disk Drive (HDD) support */
-#define AMGCTLVAL 0xFF
-#define AMBCTL0VAL 0x7BB07BB0
-#define AMBCTL1VAL 0xFFC27BB0
+#if defined(CONFIG_BFIN_CF_IDE) || \
+ defined(CONFIG_BFIN_HDD_IDE) || \
+ defined(CONFIG_BFIN_TRUE_IDE)
+# define CONFIG_BFIN_IDE 1
+# define CONFIG_CMD_IDE
+#endif
#if defined(CONFIG_BFIN_IDE)
#undef CONFIG_IDE_LED /* no led for ide supported */
#undef CONFIG_IDE_RESET /* no reset for ide supported */
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS 1
+#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
-#undef AMBCTL1VAL
-#define AMBCTL1VAL 0xFFC3FFC3
+#undef CONFIG_EBIU_AMBCTL1_VAL
+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3
#define CONFIG_CF_ATASEL_DIS 0x20311800
#define CONFIG_CF_ATASEL_ENA 0x20311802
*/
#define CONFIG_SYS_ATA_BASE_ADDR 0x2031C000
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
+#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
+#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.Ax */
-#endif /* CONFIG_BFIN_TRUE_IDE */
-#if defined(CONFIG_BFIN_CF_IDE) /* USE CompactFlash Storage Card in the common memory space */
+#elif defined(CONFIG_BFIN_CF_IDE)
#define CONFIG_SYS_ATA_BASE_ADDR 0x20211800
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x000E /* Offset for alternate registers */
+#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* normal register accesses */
+#define CONFIG_SYS_ATA_ALT_OFFSET 0x000E /* alternate registers */
#define CONFIG_SYS_ATA_STRIDE 1 /* CF.A0 --> Blackfin.Ax */
-#endif /* CONFIG_BFIN_CF_IDE */
-#if defined(CONFIG_BFIN_HDD_IDE) /* USE TRUE IDE */
+#elif defined(CONFIG_BFIN_HDD_IDE)
#define CONFIG_SYS_ATA_BASE_ADDR 0x20314000
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
+#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
+#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
-
#undef CONFIG_SCLK_DIV
#define CONFIG_SCLK_DIV 8
-#endif /* CONFIG_BFIN_HDD_IDE */
+#endif
+
+#endif
-#endif /*CONFIG_BFIN_IDE */
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE 0
+
+/* #define CONFIG_BF537_STAMP_LEDCMD 1 */
+
+/* Define if want to do post memory test */
+#undef CONFIG_POST
+#ifdef CONFIG_POST
+#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
+#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
+#endif
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
#include <asm/blackfin-config-post.h>
* U-boot - Configuration file for BF561 EZKIT board
*/
-#ifndef __CONFIG_EZKIT561_H__
-#define __CONFIG_EZKIT561_H__
+#ifndef __CONFIG_BF561_EZKIT_H__
+#define __CONFIG_BF561_EZKIT_H__
#include <asm/blackfin-config-pre.h>
-#define CONFIG_SYS_LONGHELP 1
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_BAUDRATE 57600
-/* Set default serial console for bf537 */
-#define CONFIG_UART_CONSOLE 0
-#define CONFIG_EZKIT561 1
-#define CONFIG_BOOTDELAY 5
-
-#define CONFIG_PANIC_HANG 1
-
-#define CONFIG_BFIN_CPU bf561-0.3
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
-/* This sets the default state of the cache on U-Boot's boot */
-#define CONFIG_ICACHE_ON
-#define CONFIG_DCACHE_ON
/*
- * Board settings
+ * Processor Settings
*/
-#define CONFIG_DRIVER_SMC91111 1
-#define CONFIG_SMC91111_BASE 0x2C010300
-#define CONFIG_ASYNC_EBIU_BASE CONFIG_SMC91111_BASE & ~(4*1024*1024)
-#define CONFIG_SMC_USE_32_BIT 1
-#define CONFIG_MISC_INIT_R 1
-
-/*
- * Clock settings
- */
-
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 30000000
-/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
-/* 1=CLKIN/2 */
-#define CONFIG_CLKIN_HALF 0
-/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
-/* 1=bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* CONFIG_VCO_MULT controls what the multiplier of the PLL is */
-/* Values can range from 1-64 */
-#define CONFIG_VCO_MULT 20
-/* CONFIG_CCLK_DIV controls what the core clock divider is */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
-/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
-/* Values can range from 2-65535 */
-/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
-#define CONFIG_SPI_BAUD 2
-#define CONFIG_SPI_BAUD_INITBLOCK 4
+#define CONFIG_BFIN_CPU bf561-0.3
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-/*
- * Network settings
- */
-#if (CONFIG_DRIVER_SMC91111)
-#define CONFIG_IPADDR 192.168.0.15
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_GATEWAYIP 192.168.0.1
-#define CONFIG_SERVERIP 192.168.0.2
-#define CONFIG_HOSTNAME ezkit561
-#define CONFIG_ROOTPATH /arm-cross-build/BF561/uClinux-dist/romfs
-#endif /* CONFIG_DRIVER_SMC91111 */
/*
- * Flash settings
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 30000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
+#define CONFIG_VCO_MULT 20
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 6
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max number of sectors on one chip */
-#define CONFIG_ENV_ADDR 0x20020000
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
-/* JFFS Partition offset set */
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-/* 512k reserved for u-boot */
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 8
/*
- * SDRAM settings & memory map
+ * Memory Settings
*/
+#define CONFIG_MEM_ADD_WDTH 9
+#define CONFIG_MEM_SIZE 64
-#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */
-#define CONFIG_MEM_MT48LC16M16A2TG_75 1
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024)
-
-#define CONFIG_SYS_MEMTEST_START 0x0 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 1024*1024) /* 1 ... 63 MB in DRAM */
+#define CONFIG_EBIU_SDRRC_VAL 0x306
+#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
-#define CONFIG_LOADADDR 0x01000000 /* default load address */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_EBIU_AMGCTL_VAL 0x3F
+#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 0x4000
-#define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4)
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-
-#if ( CONFIG_CLKIN_HALF == 0 )
-#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
-#else
-#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
-#endif
-
-#if (CONFIG_PLL_BYPASS == 0)
-#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
-#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
-#else
-#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
-#endif
/*
- * Command settings
+ * Network Settings
*/
+#define ADI_CMDS_NETWORK 1
+#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_SMC91111_BASE 0x2C010300
+#define CONFIG_SMC_USE_32_BIT 1
+#define CONFIG_HOSTNAME bf561-ezkit
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-#define CONFIG_SYS_AUTOLOAD "no" /* rarpb, bootp, dhcp commands will */
- /* only perform a configuration */
- /* lookup from the BOOTP/DHCP server */
- /* but not try to load any image */
- /* using TFTP */
-#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, */
- /* currently its disabled */
-#define CONFIG_BOOTCOMMAND "run ramboot"
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
-
-#if (CONFIG_DRIVER_SMC91111)
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
- "$(rootpath) console=ttyBF0,57600\0" \
- "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
- "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
- "ramboot=tftpboot $(loadaddr) linux; " \
- "run ramargs; run addip; bootelf\0" \
- "nfsboot=tftpboot $(loadaddr) linux; " \
- "run nfsargs; run addip; bootelf\0" \
- "update=tftpboot $(loadaddr) u-boot.bin; " \
- "protect off 0x20000000 0x2003FFFF; " \
- "erase 0x20000000 0x2003FFFF; " \
- "cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
- ""
-#else
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
- "flashboot=bootm 0x20100000\0" \
- ""
-#endif
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
/*
- * Command line configuration.
+ * Flash Settings
*/
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_JFFS2
-
-#if defined(CONFIG_DRIVER_SMC91111)
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 135
+/* The BF561-EZKIT uses a top boot flash */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR 0x20004000
+#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#define ENV_IS_EMBEDDED
+#else
+#define ENV_IS_EMBEDDED_CUSTOM
#endif
+
/*
- * Console settings
+ * I2C Settings
*/
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_SYS_PROMPT "bfin> " /* Monitor Command Prompt */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SOFT_I2C
+#ifdef CONFIG_SOFT_I2C
+#define PF_SCL PF0
+#define PF_SDA PF1
+#define I2C_INIT \
+ do { \
+ *pFIO0_DIR |= PF_SCL; \
+ SSYNC(); \
+ } while (0)
+#define I2C_ACTIVE \
+ do { \
+ *pFIO0_DIR |= PF_SDA; \
+ *pFIO0_INEN &= ~PF_SDA; \
+ SSYNC(); \
+ } while (0)
+#define I2C_TRISTATE \
+ do { \
+ *pFIO0_DIR &= ~PF_SDA; \
+ *pFIO0_INEN |= PF_SDA; \
+ SSYNC(); \
+ } while (0)
+#define I2C_READ ((*pFIO0_FLAG_D & PF_SDA) != 0)
+#define I2C_SDA(bit) \
+ do { \
+ if (bit) \
+ *pFIO0_FLAG_S = PF_SDA; \
+ else \
+ *pFIO0_FLAG_C = PF_SDA; \
+ SSYNC(); \
+ } while (0)
+#define I2C_SCL(bit) \
+ do { \
+ if (bit) \
+ *pFIO0_FLAG_S = PF_SCL; \
+ else \
+ *pFIO0_FLAG_C = PF_SCL; \
+ SSYNC(); \
+ } while (0)
+#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_SYS_I2C_SLAVE 0
#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_LOADS_ECHO 1
/*
- * Miscellaneous configurable options
+ * Misc Settings
*/
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 10 ms ticks */
-#define CONFIG_SYS_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
+#define CONFIG_UART_CONSOLE 0
+
/*
- * FLASH organization and environment definitions
+ * Pull in common ADI header for remaining command/environment setup
*/
-#define CONFIG_EBIU_SDRRC_VAL 0x306
-#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
-#define CONFIG_EBIU_SDBCTL_VAL 0x15
-
-#define CONFIG_EBIU_AMGCTL_VAL 0x3F
-#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
+#include <configs/bfin_adi_common.h>
#include <asm/blackfin-config-post.h>
--- /dev/null
+/*
+ * U-Boot - Common settings for Analog Devices boards
+ */
+
+#ifndef __CONFIG_BFIN_ADI_COMMON_H__
+#define __CONFIG_BFIN_ADI_COMMON_H__
+
+/*
+ * Command Settings
+ */
+#ifndef _CONFIG_CMD_DEFAULT_H
+# include <config_cmd_default.h>
+# if ADI_CMDS_NETWORK
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+# ifdef CONFIG_BFIN_MAC
+# define CONFIG_CMD_MII
+# endif
+# else
+# undef CONFIG_CMD_BOOTD
+# undef CONFIG_CMD_NET
+# undef CONFIG_CMD_NFS
+# endif
+# ifdef CONFIG_LIBATA
+# define CONFIG_CMD_FAT
+# define CONFIG_CMD_SATA
+# define CONFIG_DOS_PARTITION
+# endif
+# ifdef CONFIG_MMC
+# define CONFIG_CMD_FAT
+# define CONFIG_CMD_MMC
+# define CONFIG_DOS_PARTITION
+# endif
+# ifdef CONFIG_USB
+# define CONFIG_CMD_EXT2
+# define CONFIG_CMD_FAT
+# define CONFIG_CMD_USB
+# define CONFIG_CMD_USB_STORAGE
+# define CONFIG_DOS_PARTITION
+# endif
+# ifdef CONFIG_POST
+# define CONFIG_CMD_DIAG
+# endif
+# ifdef CONFIG_RTC_BFIN
+# define CONFIG_CMD_DATE
+# endif
+# ifdef CONFIG_SPI
+# define CONFIG_CMD_EEPROM
+# endif
+# if defined(CONFIG_BFIN_SPI) || defined(CONFIG_SOFT_SPI)
+# define CONFIG_CMD_SPI
+# endif
+# ifdef CONFIG_SPI_FLASH
+# define CONFIG_CMD_SF
+# endif
+# if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+# define CONFIG_CMD_I2C
+# endif
+# ifdef CONFIG_SYS_NO_FLASH
+# undef CONFIG_CMD_FLASH
+# undef CONFIG_CMD_IMLS
+# else
+# define CONFIG_CMD_JFFS2
+# endif
+# define CONFIG_CMD_BOOTLDR
+# define CONFIG_CMD_CACHE
+# define CONFIG_CMD_CPLBINFO
+# define CONFIG_CMD_ELF
+# define CONFIG_ELF_SIMPLE_LOAD
+# define CONFIG_CMD_REGINFO
+# define CONFIG_CMD_STRINGS
+# if defined(__ADSPBF51x__) || defined(__ADSPBF52x__) || defined(__ADSPBF54x__)
+# define CONFIG_CMD_OTP
+# endif
+#endif
+
+/*
+ * Console Settings
+ */
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_AUTO_COMPLETE 1
+#define CONFIG_LOADS_ECHO 1
+#define CONFIG_JTAG_CONSOLE
+#ifndef CONFIG_BAUDRATE
+# define CONFIG_BAUDRATE 57600
+#endif
+
+/*
+ * Debug Settings
+ */
+#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_DEBUG_DUMP 1
+#define CONFIG_DEBUG_DUMP_SYMS 1
+#define CONFIG_PANIC_HANG 1
+
+/*
+ * Env Settings
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
+# define CONFIG_BOOTDELAY -1
+#else
+# define CONFIG_BOOTDELAY 5
+#endif
+#define CONFIG_BOOTCOMMAND "run ramboot"
+#ifdef CONFIG_VIDEO
+# define CONFIG_BOOTARGS_VIDEO "console=tty0 "
+#else
+# define CONFIG_BOOTARGS_VIDEO ""
+#endif
+#define CONFIG_BOOTARGS \
+ "root=/dev/mtdblock0 rw " \
+ "clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \
+ "earlyprintk=" \
+ "serial," \
+ "uart" MK_STR(CONFIG_UART_CONSOLE) "," \
+ MK_STR(CONFIG_BAUDRATE) " " \
+ CONFIG_BOOTARGS_VIDEO \
+ "console=ttyBF0," MK_STR(CONFIG_BAUDRATE)
+
+#if defined(CONFIG_CMD_NET)
+# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+# define UBOOT_ENV_FILE "u-boot.bin"
+# else
+# define UBOOT_ENV_FILE "u-boot.ldr"
+# endif
+# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+# ifdef CONFIG_SPI
+# define UBOOT_ENV_UPDATE \
+ "eeprom write $(loadaddr) 0x0 $(filesize)"
+# else
+# define UBOOT_ENV_UPDATE \
+ "sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \
+ "sf erase 0 0x40000;" \
+ "sf write $(loadaddr) 0 $(filesize)"
+# endif
+# elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
+# define UBOOT_ENV_UPDATE \
+ "nand unlock 0 0x40000;" \
+ "nand erase 0 0x40000;" \
+ "nand write $(loadaddr) 0 0x40000"
+# else
+# define UBOOT_ENV_UPDATE \
+ "protect off 0x20000000 0x2003FFFF;" \
+ "erase 0x20000000 0x2003FFFF;" \
+ "cp.b $(loadaddr) 0x20000000 $(filesize)"
+# endif
+# define NETWORK_ENV_SETTINGS \
+ "ubootfile=" UBOOT_ENV_FILE "\0" \
+ "update=" \
+ "tftp $(loadaddr) $(ubootfile);" \
+ UBOOT_ENV_UPDATE \
+ "\0" \
+ "addip=set bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \
+ "$(hostname):eth0:off" \
+ "\0" \
+ "ramargs=set bootargs " CONFIG_BOOTARGS "\0" \
+ "ramboot=" \
+ "tftp $(loadaddr) uImage;" \
+ "run ramargs;" \
+ "run addip;" \
+ "bootm" \
+ "\0" \
+ "nfsargs=set bootargs " \
+ "root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3" \
+ "\0" \
+ "nfsboot=" \
+ "tftp $(loadaddr) vmImage;" \
+ "run nfsargs;" \
+ "run addip;" \
+ "bootm" \
+ "\0"
+#else
+# define NETWORK_ENV_SETTINGS
+#endif
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ NETWORK_ENV_SETTINGS \
+ "flashboot=bootm 0x20100000\0"
+
+/*
+ * Network Settings
+ */
+#ifdef CONFIG_CMD_NET
+# define CONFIG_IPADDR 192.168.0.15
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_GATEWAYIP 192.168.0.1
+# define CONFIG_SERVERIP 192.168.0.2
+# define CONFIG_ROOTPATH /romfs
+# ifdef CONFIG_CMD_DHCP
+# ifndef CONFIG_SYS_AUTOLOAD
+# define CONFIG_SYS_AUTOLOAD "no"
+# endif
+# endif
+# define CONFIG_NET_RETRY_COUNT 20
+#endif
+
+#endif
#include <linux/mtd/nand.h>
+#define FSL_UPM_WAIT_RUN_PATTERN 0x1
+#define FSL_UPM_WAIT_WRITE_BYTE 0x2
+#define FSL_UPM_WAIT_WRITE_BUFFER 0x4
+
struct fsl_upm {
void __iomem *mdr;
void __iomem *mxmr;
int width;
int upm_cmd_offset;
int upm_addr_offset;
- int wait_pattern;
- int (*dev_ready)(void);
+ int upm_mar_chip_offset;
+ int wait_flags;
+ int (*dev_ready)(int chip_nr);
int chip_delay;
+ int chip_offset;
+ int chip_nr;
/* no need to fill */
int last_ctrl;
board_init_r((gd_t *) gd, 0x20000010);
}
+static void board_net_init_r(bd_t *bd)
+{
+#ifdef CONFIG_CMD_NET
+ uchar enetaddr[6];
+ char *s;
+
+ if ((s = getenv("bootfile")) != NULL)
+ copy_filename(BootFile, s, sizeof(BootFile));
+
+ bd->bi_ip_addr = getenv_IPaddr("ipaddr");
+
+ printf("Net: ");
+ eth_initialize(gd->bd);
+
+ eth_getenv_enetaddr("ethaddr", enetaddr);
+ printf("MAC: %pM\n", enetaddr);
+#endif
+}
+
void board_init_r(gd_t * id, ulong dest_addr)
{
extern void malloc_bin_reloc(void);
#if !defined(CONFIG_SYS_NO_FLASH)
/* Initialize the flash and protect u-boot by default */
extern flash_info_t flash_info[];
- ulong size = flash_init();
puts("Flash: ");
+ ulong size = flash_init();
print_size(size, "\n");
flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_FLASH_BASE,
CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - 1,
/* Initialize from environment */
if ((s = getenv("loadaddr")) != NULL)
load_addr = simple_strtoul(s, NULL, 16);
-#ifdef CONFIG_CMD_NET
- if ((s = getenv("bootfile")) != NULL)
- copy_filename(BootFile, s, sizeof(BootFile));
-#endif
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
misc_init_r();
#endif
-#ifdef CONFIG_CMD_NET
- /* IP Address */
- bd->bi_ip_addr = getenv_IPaddr("ipaddr");
- printf("Net: ");
- eth_initialize(gd->bd);
-#endif
+ board_net_init_r(bd);
display_global_data();
blackfin_dcache_flush_range(start_addr, end_addr);
}
+#ifdef CONFIG_DCACHE_WB
+static void flushinv_all_dcache(void)
+{
+ u32 way, bank, subbank, set;
+ u32 status, addr;
+ u32 dmem_ctl = bfin_read_DMEM_CONTROL();
+
+ for (bank = 0; bank < 2; ++bank) {
+ if (!(dmem_ctl & (1 << (DMC1_P - bank))))
+ continue;
+
+ for (way = 0; way < 2; ++way)
+ for (subbank = 0; subbank < 4; ++subbank)
+ for (set = 0; set < 64; ++set) {
+
+ bfin_write_DTEST_COMMAND(
+ way << 26 |
+ bank << 23 |
+ subbank << 16 |
+ set << 5
+ );
+ CSYNC();
+ status = bfin_read_DTEST_DATA0();
+
+ /* only worry about valid/dirty entries */
+ if ((status & 0x3) != 0x3)
+ continue;
+
+ /* construct the address using the tag */
+ addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
+
+ /* flush it */
+ __asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr));
+ }
+ }
+}
+#endif
+
void icache_enable(void)
{
bfin_write_IMEM_CONTROL(IMC | ENICPLB);
void dcache_disable(void)
{
+#ifdef CONFIG_DCACHE_WB
+ bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() & ~(ENDCPLB));
+ flushinv_all_dcache();
+#endif
bfin_write_DMEM_CONTROL(0);
SSYNC();
}
#include "onenand_ipl.h"
-#ifdef CONFIG_SYS_PRINTF
-int print_info(void)
-{
- printf(XLOADER_VERSION);
-
- return 0;
-}
-#endif
-
typedef int (init_fnc_t)(void);
-init_fnc_t *init_sequence[] = {
- board_init, /* basic board dependent setup */
-#ifdef CONFIG_SYS_PRINTF
- serial_init, /* serial communications setup */
- print_info,
-#endif
- NULL,
-};
-
void start_oneboot(void)
{
- init_fnc_t **init_fnc_ptr;
uchar *buf;
- for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
- if ((*init_fnc_ptr)() != 0)
- hang();
- }
-
buf = (uchar *) CONFIG_SYS_LOAD_ADDR;
- if (!onenand_read_block0(buf))
- buf += ONENAND_BLOCK_SIZE;
-
- if (buf == (uchar *)CONFIG_SYS_LOAD_ADDR)
- hang();
+ onenand_read_block0(buf);
- /* go run U-Boot and never return */
- printf("Starting OS Bootloader...\n");
((init_fnc_t *)CONFIG_SYS_LOAD_ADDR)();
/* should never come here */
void hang(void)
{
- /* if board_hang() returns, hange here */
- printf("X-Loader hangs\n");
- for (;;);
+ for (;;);
}
#include <linux/mtd/onenand_regs.h>
-#define ONENAND_BLOCK_SIZE 2048
-
-#ifndef CONFIG_SYS_PRINTF
-#define printf(format, args...)
-#endif
-
#define onenand_readw(a) readw(a)
#define onenand_writew(v, a) writew(v, a)
projects / karo-tx-uboot.git / commitdiff