]> git.karo-electronics.de Git - linux-beck.git/commitdiff
Add support for Beck-IPC SC145 module and DB150 eval kit
authorOle Reinhardt <ole.reinhardt@kernelconcepts.de>
Thu, 9 Mar 2017 15:21:00 +0000 (16:21 +0100)
committerOle Reinhardt <ole.reinhardt@kernelconcepts.de>
Mon, 13 Mar 2017 16:13:31 +0000 (17:13 +0100)
arch/arm/boot/dts/Makefile
arch/arm/boot/dts/imx6ul-sc145-db150.dts [new file with mode: 0644]
arch/arm/boot/dts/imx6ul-sc145-h01.dtsi [new file with mode: 0644]
arch/arm/boot/dts/imx6ul-sc145-h02.dtsi [new file with mode: 0644]
arch/arm/boot/dts/imx6ul-sc145.dtsi [new file with mode: 0644]
arch/arm/configs/beck-db150_defconfig [new file with mode: 0644]

index 7037201c5e3a7dd232b087fd7d7daa36bf3878ad..40510b448efb823997a03bd1f3852596e11b8504 100644 (file)
@@ -423,7 +423,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
        imx6ul-pico-hobbit.dtb \
        imx6ul-tx6ul-0010.dtb \
        imx6ul-tx6ul-0011.dtb \
-       imx6ul-tx6ul-mainboard.dtb
+       imx6ul-tx6ul-mainboard.dtb \
+       imx6ul-sc145-db150.dtb
 dtb-$(CONFIG_SOC_IMX7D) += \
        imx7d-cl-som-imx7.dtb \
        imx7d-colibri-eval-v3.dtb \
diff --git a/arch/arm/boot/dts/imx6ul-sc145-db150.dts b/arch/arm/boot/dts/imx6ul-sc145-db150.dts
new file mode 100644 (file)
index 0000000..7a3b69d
--- /dev/null
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2016 Beck IPC GmbH
+ * Copyright (C) 2017 Kernel Concepts GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* Device tree for SC145-H02 on DB150-H01 */
+
+/dts-v1/;
+#include "imx6ul.dtsi"
+#include "imx6ul-sc145-h02.dtsi"
+
+/ {
+    model = "Beck IPC@CHIP SC145, DB150 Baseboard";
+    compatible = "beck,imx6ul-sc145", "fsl,imx6ul";
+
+    chosen {
+        stdout-path = &uart1;
+    };
+};
+
+
+&fec2 {
+    status = "okay";
+};
+
+&can2 {
+    status = "okay";
+};
+
+&uart5 {
+    status = "okay";
+};
+
+&usdhc2 {
+    status = "disabled";
+};
+
+&i2c4 {
+    status = "disabled";
+};
diff --git a/arch/arm/boot/dts/imx6ul-sc145-h01.dtsi b/arch/arm/boot/dts/imx6ul-sc145-h01.dtsi
new file mode 100644 (file)
index 0000000..400204a
--- /dev/null
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2016 Beck IPC GmbH
+ * Copyright (C) 2017 Kernel Concepts GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* Device tree for SC145 H00/H01 */
+
+#include "imx6ul-sc145.dtsi"
+
+&fec1 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_enet1>;
+    phy-mode = "rmii";
+    phy-handle = <&ethphy0>;
+    phy-supply = <&reg_vref_3v3>;
+    bus-no = <0>;
+    status = "okay";
+};
+
+&fec2 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_enet2>;
+    phy-mode = "rmii";
+    phy-handle = <&ethphy1>;
+    phy-supply = <&reg_vref_3v3>;
+    bus-no = <1>;
+    status = "disabled";
+
+    mdio {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        ethphy0: ethernet-phy@0 {
+            compatible = "ethernet-phy-ieee802.3-c22";
+            reg = <0>;
+        };
+
+        ethphy1: ethernet-phy@1 {
+            compatible = "ethernet-phy-ieee802.3-c22";
+            reg = <1>;
+        };
+    };
+};
diff --git a/arch/arm/boot/dts/imx6ul-sc145-h02.dtsi b/arch/arm/boot/dts/imx6ul-sc145-h02.dtsi
new file mode 100644 (file)
index 0000000..107ccc3
--- /dev/null
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2016 Beck IPC GmbH
+ * Copyright (C) 2017 Kernel Concepts GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* Device tree for SC145 H02 */
+
+#include "imx6ul-sc145.dtsi"
+
+&fec1 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_enet1>;
+    phy-mode = "rmii";
+    phy-handle = <&ethphy1>;
+    phy-supply = <&reg_vref_3v3>;
+    bus-no = <0>;
+    status = "okay";
+};
+
+&fec2 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_enet2>;
+    phy-mode = "rmii";
+    phy-handle = <&ethphy2>;
+    phy-supply = <&reg_vref_3v3>;
+    bus-no = <1>;
+    status = "okay";
+
+    mdio {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        ethphy1: ethernet-phy@1 {
+            compatible = "ethernet-phy-ieee802.3-c22";
+            reg = <1>;
+        };
+
+        ethphy2: ethernet-phy@2 {
+            compatible = "ethernet-phy-ieee802.3-c22";
+            reg = <2>;
+        };
+    };
+};
diff --git a/arch/arm/boot/dts/imx6ul-sc145.dtsi b/arch/arm/boot/dts/imx6ul-sc145.dtsi
new file mode 100644 (file)
index 0000000..51ac6ee
--- /dev/null
@@ -0,0 +1,584 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2016 Beck IPC GmbH
+ * Copyright (C) 2017 Kernel Concepts GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+    memory {
+        reg = <0x80000000 0x8000000>;
+    };
+
+    regulators {
+        compatible = "simple-bus";
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        reg_sd1_vmmc: regulator@1 {
+            compatible = "regulator-fixed";
+            regulator-name = "VSD_3V3";
+            regulator-min-microvolt = <3300000>;
+            regulator-max-microvolt = <3300000>;
+            gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+            enable-active-high;
+        };
+
+        reg_vref_3v3: regulator@2 {
+            compatible = "regulator-fixed";
+            regulator-name = "vref-3v3";
+            regulator-min-microvolt = <3300000>;
+            regulator-max-microvolt = <3300000>;
+        };
+
+        reg_vref_5v: regulator@3 {
+            compatible = "regulator-fixed";
+            regulator-name = "vref-5v";
+            regulator-min-microvolt = <5000000>;
+            regulator-max-microvolt = <5000000>;
+        };
+    };
+};
+
+&cpu0 {
+    arm-supply = <&reg_arm>;
+    soc-supply = <&reg_soc>;
+};
+
+&clks {
+    assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+    assigned-clock-rates = <786432000>;
+};
+
+&wdog1 {
+    fsl,ext-reset-output = <1>;
+};
+
+&ecspi1 {
+    fsl,spi-num-chipselects = <1>;
+    cs-gpios = <0>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_ecspi1>;
+    status = "okay";
+
+    spidev0: spidev@0 {
+        compatible = "spidev";
+        reg = <0>;
+        spi-max-frequency = <60000000>;
+    };
+};
+
+&ecspi2 {
+    fsl,spi-num-chipselects = <1>;
+    cs-gpios = <0>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_ecspi2>;
+    status = "disabled";
+
+    spidev1: spidev@1 {
+        compatible = "spidev";
+        spi-max-frequency = <0>;
+        reg = <0>;
+    };
+};
+
+&ecspi3 {
+    fsl,spi-num-chipselects = <1>;
+    cs-gpios = <0>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_ecspi3>;
+    status = "disabled";
+
+    spidev2: spidev@2 {
+                compatible = "spidev";
+                spi-max-frequency = <0>;
+                reg = <0>;
+            };
+};
+
+&ecspi4 {
+    fsl,spi-num-chipselects = <1>;
+    cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_ecspi4>;
+    status = "okay";
+
+    fram0: fram@0 {
+        compatible = "atmel,at25", "cypress,fm25cl64b";
+        spi-max-frequency = <20000000>;
+        reg = <0>;
+        pagesize = <8192>;
+        size = <8192>;
+        address-width = <16>;
+    };
+};
+
+&can1 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_flexcan1>;
+    xceiver-supply = <&reg_vref_3v3>;
+    status = "okay";
+};
+
+&can2 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_flexcan2>;
+    xceiver-supply = <&reg_vref_3v3>;
+    status = "disabled";
+};
+
+&gpc {
+    fsl,cpu_pupscr_sw2iso = <0x1>;
+    fsl,cpu_pupscr_sw = <0x0>;
+    fsl,cpu_pdnscr_iso2sw = <0x1>;
+    fsl,cpu_pdnscr_iso = <0x1>;
+    fsl,wdog-reset = <1>; /* watchdog select of reset source */
+    fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
+};
+
+&pwm1 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_pwm1>;
+    bus-no = <0>;
+    status = "okay";
+};
+
+&pwm5 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_pwm5>;
+    bus-no = <4>;
+    status = "disabled";
+};
+
+&pwm7 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_pwm7>;
+    bus-no = <6>;
+    status = "disabled";
+};
+
+&pwm8 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_pwm8>;
+    bus-no = <7>;
+    status = "disabled";
+};
+
+&adc1 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_adc1>;
+    vref-supply = <&reg_vref_3v3>;
+    num-channels = <10>;
+    status = "okay";
+};
+
+&uart1 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_uart1>;
+    fsl,uart-has-rtscts;
+    status = "okay";
+};
+
+&uart2 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_uart2>;
+    status = "disabled";
+};
+
+&uart3 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_uart3>;
+    fsl,uart-has-rtscts;
+    status = "disabled";
+};
+
+&uart4 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_uart4>;
+    status = "disabled";
+};
+
+&uart5 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_uart5>;
+    fsl,uart-has-rtscts;
+    status = "disabled";
+};
+
+&uart6 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_uart6>;
+    fsl,uart-has-rtscts;
+    status = "disabled";
+};
+
+&usbotg1 {
+    vbus-supply = <&reg_vref_5v>;
+    dr_mode = "otg";
+    srp-disable;
+    hnp-disable;
+    adp-disable;
+    disable-over-current;
+    status = "okay";
+};
+
+&usbotg2 {
+    vbus-supply = <&reg_vref_5v>;
+    dr_mode = "host";
+    disable-over-current;
+    status = "okay";
+};
+
+&usdhc1 {
+    pinctrl-names = "default", "state_100mhz", "state_200mhz";
+    pinctrl-0 = <&pinctrl_usdhc1_default>;
+    pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+    pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+    cd-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
+    wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+    keep-power-in-suspend;
+    wakeup-source;
+    vmmc-supply = <&reg_sd1_vmmc>;
+    no-1-8-v;
+    status = "okay";
+};
+
+&usdhc2 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_usdhc2_default>;
+    no-1-8-v;
+    non-removable;
+    keep-power-in-suspend;
+    wakeup-source;
+    status = "disabled";
+};
+
+&i2c1 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_i2c1>;
+    sda-gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>;
+    scl-gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
+    status = "disabled";
+};
+
+&i2c2 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_i2c2>;
+    sda-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
+    scl-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
+    status = "disabled";
+};
+
+&i2c4 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_i2c4>;
+    sda-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
+    scl-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
+    status = "disabled";
+};
+
+&qspi {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_qspi>;
+    status = "okay";
+    ddrsmp=<0>;
+
+    flash0: n25q512ax3@0 {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "micron,n25q512ax3";
+        spi-max-frequency = <29000000>;
+        spi-nor,ddr-quad-read-dummy = <6>;
+        reg = <0>;
+    };
+};
+
+&iomuxc {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_hog>;
+
+    pinctrl_hog: hoggrp {
+        fsl,pins = <
+            MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x130a0 /* PFAIL_IN */
+            MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY    0x008b0 /* Watchdog Reset */
+        >;
+    };
+
+    /* ETH0 */
+    pinctrl_enet1: enet1grp {
+        fsl,pins = <
+            MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
+            MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
+            MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+            MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+            MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
+            MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+            MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+            MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
+        >;
+    };
+
+    /* ETH1 */
+    pinctrl_enet2: enet2grp {
+        fsl,pins = <
+            MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
+            MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
+            MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
+            MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
+            MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+            MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+            MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
+            MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+            MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+            MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
+        >;
+    };
+
+    /* SPI1 */
+    pinctrl_ecspi1: ecspi1grp {
+        fsl,pins = <
+            MX6UL_PAD_CSI_DATA07__ECSPI1_MISO    0x1b020
+            MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI    0x1b020
+            MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK    0x1b020
+        >;
+    };
+
+    /* SPI2 */
+    pinctrl_ecspi2: ecspi2grp {
+        fsl,pins = <
+            MX6UL_PAD_CSI_DATA03__ECSPI2_MISO    0x1b020
+            MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI    0x1b020
+            MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK    0x1b020
+        >;
+    };
+
+    /* SPI3 */
+    pinctrl_ecspi3: ecspi3grp {
+        fsl,pins = <
+            MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO   0x1b020
+            MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI   0x1b020
+            MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x1b020
+        >;
+    };
+
+    /* SPI4 */
+    pinctrl_ecspi4: ecspi4grp {
+        fsl,pins = <
+            MX6UL_PAD_NAND_DATA06__ECSPI4_MISO   0x1b020
+            MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI   0x1b020
+            MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK   0x1b020
+            MX6UL_PAD_NAND_DATA07__GPIO4_IO09    0x1b020
+        >;
+    };
+
+    /* CAN1 */
+    pinctrl_flexcan1: flexcan1grp {
+        fsl,pins = <
+            MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX   0x1b020
+            MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX   0x1b020
+        >;
+    };
+
+    /* CAN2 */
+    pinctrl_flexcan2: flexcan2grp {
+        fsl,pins = <
+            MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX   0x1b020
+            MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX   0x1b020
+        >;
+    };
+
+    /* PWM1 */
+    pinctrl_pwm1_default: pwm1grp_default {
+        fsl,pins = <>;
+    };
+
+    pinctrl_pwm1: pwm1grp {
+        fsl,pins = <
+            MX6UL_PAD_GPIO1_IO08__PWM1_OUT       0x110b0
+        >;
+    };
+
+    /* PWM5 */
+    pinctrl_pwm5: pwm5grp {
+        fsl,pins = <
+            MX6UL_PAD_LCD_DATA18__PWM5_OUT       0x110b0
+        >;
+    };
+
+    /* PWM7 */
+    pinctrl_pwm7: pwm7grp {
+        fsl,pins = <
+            MX6UL_PAD_CSI_VSYNC__PWM7_OUT        0x110b0
+        >;
+    };
+
+    /* PWM8 */
+    pinctrl_pwm8: pwm8grp {
+        fsl,pins = <
+            MX6UL_PAD_CSI_HSYNC__PWM8_OUT        0x110b0
+        >;
+    };
+
+    /* ADC1: AIN3 */
+    pinctrl_adc1: adc1grp {
+        fsl,pins = <
+            MX6UL_PAD_GPIO1_IO03__GPIO1_IO03     0xb0
+        >;
+    };
+
+    /* UART1 */
+    pinctrl_uart1: uart1grp {
+        fsl,pins = <
+            MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x1b0b1
+            MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x1b0b1
+            MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS    0x1b0b1
+            MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS    0x1b0b1
+        >;
+    };
+
+    /* UART2 */
+    pinctrl_uart2: uart2grp {
+        fsl,pins = <
+            MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
+            MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
+        >;
+    };
+
+    /* UART3 */
+    pinctrl_uart3: uart3grp {
+        fsl,pins = <
+            MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX   0x1b0b1
+            MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX   0x1b0b1
+            MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS    0x1b0b1
+            MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS    0x1b0b1
+        >;
+    };
+
+    /* UART4 */
+    pinctrl_uart4: uart4grp {
+        fsl,pins = <
+            MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX   0x1b0b1
+            MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX   0x1b0b1
+        >;
+    };
+
+    /* UART5 */
+    pinctrl_uart5: uart5grp {
+        fsl,pins = <
+            MX6UL_PAD_CSI_DATA00__UART5_DCE_TX      0x1b0b1
+            MX6UL_PAD_CSI_DATA01__UART5_DCE_RX      0x1b0b1
+            MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS     0x1b0b1
+            MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS     0x1b0b1
+        >;
+    };
+
+    /* UART6 */
+    pinctrl_uart6: uart6grp {
+        fsl,pins = <
+            MX6UL_PAD_CSI_MCLK__UART6_DCE_TX        0x1b0b1
+            MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX      0x1b0b1
+            MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS      0x1b0b1
+            MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS      0x1b0b1
+        >;
+    };
+
+    /* SDIO1 / SDHC card */
+    pinctrl_usdhc1_default: usdhc1grp_default {
+        fsl,pins = <
+            MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
+            MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10071
+            MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
+            MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
+            MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
+            MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
+            MX6UL_PAD_CSI_DATA05__GPIO4_IO26        0x17059 /* SD1 CD */
+            MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
+            MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x13059 /* SD1 WP */
+        >;
+    };
+
+    pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+        fsl,pins = <
+            MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x170b9
+            MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x100b9
+            MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x170b9
+            MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x170b9
+            MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x170b9
+            MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x170b9
+            MX6UL_PAD_CSI_DATA05__GPIO4_IO26        0x17059 /* SD1 CD */
+            MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
+            MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x13059 /* SD1 WP */
+        >;
+    };
+
+    pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+        fsl,pins = <
+            MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x170f9
+            MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x100f9
+            MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x170f9
+            MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x170f9
+            MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x170f9
+            MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x170f9
+            MX6UL_PAD_CSI_DATA05__GPIO4_IO26        0x17059 /* SD1 CD */
+            MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
+            MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x13059 /* SD1 WP */
+        >;
+    };
+
+    /* SDIO2 / WLAN etc. */
+    pinctrl_usdhc2_default: usdhc2grp_default {
+        fsl,pins = <
+            MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
+            MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
+            MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+            MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+            MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+            MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+            MX6UL_PAD_NAND_ALE__USDHC2_RESET_B  0x17059
+        >;
+    };
+
+    /* I2C1 */
+    pinctrl_i2c1: i2c1grp {
+        fsl,pins = <
+            MX6UL_PAD_CSI_PIXCLK__I2C1_SCL    0x4001b8b0
+            MX6UL_PAD_CSI_MCLK__I2C1_SDA      0x4001b8b0
+        >;
+    };
+
+
+    /* I2C2 */
+    pinctrl_i2c2: i2c2grp {
+        fsl,pins = <
+            MX6UL_PAD_CSI_HSYNC__I2C2_SCL     0x4001b8b0
+            MX6UL_PAD_CSI_VSYNC__I2C2_SDA     0x4001b8b0
+        >;
+    };
+
+    /* I2C4 */
+    pinctrl_i2c4: i2c4grp {
+        fsl,pins = <
+            MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001b8b0
+            MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001b8b0
+        >;
+    };
+
+    /* QSPI */
+    pinctrl_qspi: qspigrp {
+        fsl,pins = <
+            MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK      0x70a1
+            MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
+            MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01   0x70a1
+            MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02   0x70a1
+            MX6UL_PAD_NAND_CLE__QSPI_A_DATA03     0x70a1
+            MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B      0x70a1
+        >;
+    };
+};
diff --git a/arch/arm/configs/beck-db150_defconfig b/arch/arm/configs/beck-db150_defconfig
new file mode 100644 (file)
index 0000000..8df91f8
--- /dev/null
@@ -0,0 +1,308 @@
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+# CONFIG_FHANDLE is not set
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_RELAY=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_ARCH_MXC=y
+CONFIG_SOC_IMX6UL=y
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+CONFIG_VMSPLIT_2G=y
+CONFIG_PREEMPT=y
+CONFIG_HZ_1000=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+# CONFIG_HIGHPTE is not set
+CONFIG_CMA=y
+CONFIG_FORCE_MAX_ZONEORDER=14
+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_ARM_IMX6Q_CPUFREQ=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_TEST_SUSPEND=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_FIB_TRIE_STATS=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_NET_IPIP=y
+CONFIG_NET_IPVTI=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_RAW=y
+CONFIG_VLAN_8021Q=y
+CONFIG_LLC2=y
+CONFIG_CAN=y
+CONFIG_CAN_FLEXCAN=y
+CONFIG_CAN_M_CAN=y
+CONFIG_CFG80211=m
+CONFIG_CFG80211_WEXT=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+CONFIG_DMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=32
+CONFIG_IMX_WEIM=y
+CONFIG_CONNECTOR=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_DATAFLASH=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_SST25L=y
+CONFIG_MTD_SPI_NOR=y
+# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
+CONFIG_SPI_FSL_QUADSPI=y
+CONFIG_MTD_UBI=y
+CONFIG_OF_OVERLAY=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=65536
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
+CONFIG_SCSI=y
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+CONFIG_TUN=y
+# CONFIG_NET_VENDOR_AMAZON is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_HISILICON is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_RENESAS is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_TLK106L_PHY=y
+CONFIG_MICREL_PHY=y
+CONFIG_PPP=y
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_ASYNC=y
+CONFIG_PPP_SYNC_TTY=y
+# CONFIG_USB_NET_DRIVERS is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_LEDS is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_I2C=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_IMX=y
+CONFIG_SPI=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_IMX=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_CPU_THERMAL=y
+CONFIG_IMX_THERMAL=y
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_WATCHDOG_SYSFS=y
+CONFIG_IMX2_WDT=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_ANATOP=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_HID=m
+# CONFIG_USB_HID is not set
+CONFIG_USB=y
+CONFIG_USB_OTG=y
+CONFIG_USB_OTG_WHITELIST=y
+CONFIG_USB_OTG_FSM=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_MXC=y
+CONFIG_USB_HCD_TEST_MODE=y
+CONFIG_USB_ACM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_CP210X=y
+CONFIG_USB_SERIAL_FTDI_SIO=y
+CONFIG_USB_SERIAL_PL2303=y
+CONFIG_USB_SERIAL_OPTION=y
+CONFIG_USB_EHSET_TEST_FIXTURE=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_MXS_PHY=y
+CONFIG_USB_GADGET=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ESDHC=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_DRV_MXC=y
+CONFIG_RTC_DRV_SNVS=y
+CONFIG_DMADEVICES=y
+CONFIG_IMX_SDMA=y
+CONFIG_STAGING=y
+CONFIG_STAGING_MEDIA=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_IIO=y
+CONFIG_VF610_ADC=y
+CONFIG_PWM=y
+CONFIG_PWM_IMX=y
+CONFIG_NVMEM_IMX_OCOTP=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_ENCRYPTION=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_NTFS_RW=y
+CONFIG_TMPFS=y
+CONFIG_UBIFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_FTRACE is not set
+CONFIG_CORESIGHT=y
+CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
+CONFIG_CORESIGHT_SINK_TPIU=y
+CONFIG_CORESIGHT_SINK_ETBV10=y
+CONFIG_CORESIGHT_SOURCE_ETM3X=y
+CONFIG_SECURITYFS=y
+CONFIG_CRYPTO_USER=y
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_CMAC=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+CONFIG_CRYPTO_RMD128=y
+CONFIG_CRYPTO_RMD160=y
+CONFIG_CRYPTO_RMD256=y
+CONFIG_CRYPTO_RMD320=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_TGR192=y
+CONFIG_CRYPTO_WP512=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=y
+CONFIG_CRYPTO_CAMELLIA=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_DEV_FSL_CAAM=y
+CONFIG_ARM_CRYPTO=y
+CONFIG_CRYPTO_SHA1_ARM=y
+CONFIG_CRYPTO_SHA256_ARM=y
+CONFIG_CRYPTO_SHA512_ARM=y
+CONFIG_CRYPTO_AES_ARM=y
+CONFIG_CRC_T10DIF=y