arch/arm/kernel/perf_event.c

   1 #undef DEBUG
   2
   3 /*
   4  * ARM performance counter support.
   5  *
   6  * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
   7  *
   8  * ARMv7 support: Jean Pihet <jpihet@mvista.com>
   9  * 2010 (c) MontaVista Software, LLC.
  10  *
  11  * This code is based on the sparc64 perf event code, which is in turn based
  12  * on the x86 code. Callchain code is based on the ARM OProfile backtrace
  13  * code.
  14  */
  15 #define pr_fmt(fmt) "hw perfevents: " fmt
  16
  17 #include <linux/interrupt.h>
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/perf_event.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/uaccess.h>
  24
  25 #include <asm/cputype.h>
  26 #include <asm/irq.h>
  27 #include <asm/irq_regs.h>
  28 #include <asm/pmu.h>
  29 #include <asm/stacktrace.h>
  30
  31 static struct platform_device *pmu_device;
  32
  33 /*
  34  * Hardware lock to serialize accesses to PMU registers. Needed for the
  35  * read/modify/write sequences.
  36  */
  37 DEFINE_SPINLOCK(pmu_lock);
  38
  39 /*
  40  * ARMv6 supports a maximum of 3 events, starting from index 1. If we add
  41  * another platform that supports more, we need to increase this to be the
  42  * largest of all platforms.
  43  *
  44  * ARMv7 supports up to 32 events:
  45  *  cycle counter CCNT + 31 events counters CNT0..30.
  46  *  Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
  47  */
  48 #define ARMPMU_MAX_HWEVENTS             33
  49
  50 /* The events for a given CPU. */
  51 struct cpu_hw_events {
  52         /*
  53          * The events that are active on the CPU for the given index. Index 0
  54          * is reserved.
  55          */
  56         struct perf_event       *events[ARMPMU_MAX_HWEVENTS];
  57
  58         /*
  59          * A 1 bit for an index indicates that the counter is being used for
  60          * an event. A 0 means that the counter can be used.
  61          */
  62         unsigned long           used_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
  63
  64         /*
  65          * A 1 bit for an index indicates that the counter is actively being
  66          * used.
  67          */
  68         unsigned long           active_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
  69 };
  70 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
  71
  72 /* PMU names. */
  73 static const char *arm_pmu_names[] = {
  74         [ARM_PERF_PMU_ID_XSCALE1] = "xscale1",
  75         [ARM_PERF_PMU_ID_XSCALE2] = "xscale2",
  76         [ARM_PERF_PMU_ID_V6]      = "v6",
  77         [ARM_PERF_PMU_ID_V6MP]    = "v6mpcore",
  78         [ARM_PERF_PMU_ID_CA8]     = "ARMv7 Cortex-A8",
  79         [ARM_PERF_PMU_ID_CA9]     = "ARMv7 Cortex-A9",
  80 };
  81
  82 struct arm_pmu {
  83         enum arm_perf_pmu_ids id;
  84         irqreturn_t     (*handle_irq)(int irq_num, void *dev);
  85         void            (*enable)(struct hw_perf_event *evt, int idx);
  86         void            (*disable)(struct hw_perf_event *evt, int idx);
  87         int             (*event_map)(int evt);
  88         u64             (*raw_event)(u64);
  89         int             (*get_event_idx)(struct cpu_hw_events *cpuc,
  90                                          struct hw_perf_event *hwc);
  91         u32             (*read_counter)(int idx);
  92         void            (*write_counter)(int idx, u32 val);
  93         void            (*start)(void);
  94         void            (*stop)(void);
  95         int             num_events;
  96         u64             max_period;
  97 };
  98
  99 /* Set at runtime when we know what CPU type we are. */
 100 static const struct arm_pmu *armpmu;
 101
 102 enum arm_perf_pmu_ids
 103 armpmu_get_pmu_id(void)
 104 {
 105         int id = -ENODEV;
 106
 107         if (armpmu != NULL)
 108                 id = armpmu->id;
 109
 110         return id;
 111 }
 112 EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
 113
 114 int
 115 armpmu_get_max_events(void)
 116 {
 117         int max_events = 0;
 118
 119         if (armpmu != NULL)
 120                 max_events = armpmu->num_events;
 121
 122         return max_events;
 123 }
 124 EXPORT_SYMBOL_GPL(armpmu_get_max_events);
 125
 126 #define HW_OP_UNSUPPORTED               0xFFFF
 127
 128 #define C(_x) \
 129         PERF_COUNT_HW_CACHE_##_x
 130
 131 #define CACHE_OP_UNSUPPORTED            0xFFFF
 132
 133 static unsigned armpmu_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 134                                      [PERF_COUNT_HW_CACHE_OP_MAX]
 135                                      [PERF_COUNT_HW_CACHE_RESULT_MAX];
 136
 137 static int
 138 armpmu_map_cache_event(u64 config)
 139 {
 140         unsigned int cache_type, cache_op, cache_result, ret;
 141
 142         cache_type = (config >>  0) & 0xff;
 143         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 144                 return -EINVAL;
 145
 146         cache_op = (config >>  8) & 0xff;
 147         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 148                 return -EINVAL;
 149
 150         cache_result = (config >> 16) & 0xff;
 151         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 152                 return -EINVAL;
 153
 154         ret = (int)armpmu_perf_cache_map[cache_type][cache_op][cache_result];
 155
 156         if (ret == CACHE_OP_UNSUPPORTED)
 157                 return -ENOENT;
 158
 159         return ret;
 160 }
 161
 162 static int
 163 armpmu_event_set_period(struct perf_event *event,
 164                         struct hw_perf_event *hwc,
 165                         int idx)
 166 {
 167         s64 left = local64_read(&hwc->period_left);
 168         s64 period = hwc->sample_period;
 169         int ret = 0;
 170
 171         if (unlikely(left <= -period)) {
 172                 left = period;
 173                 local64_set(&hwc->period_left, left);
 174                 hwc->last_period = period;
 175                 ret = 1;
 176         }
 177
 178         if (unlikely(left <= 0)) {
 179                 left += period;
 180                 local64_set(&hwc->period_left, left);
 181                 hwc->last_period = period;
 182                 ret = 1;
 183         }
 184
 185         if (left > (s64)armpmu->max_period)
 186                 left = armpmu->max_period;
 187
 188         local64_set(&hwc->prev_count, (u64)-left);
 189
 190         armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
 191
 192         perf_event_update_userpage(event);
 193
 194         return ret;
 195 }
 196
 197 static u64
 198 armpmu_event_update(struct perf_event *event,
 199                     struct hw_perf_event *hwc,
 200                     int idx)
 201 {
 202         int shift = 64 - 32;
 203         s64 prev_raw_count, new_raw_count;
 204         u64 delta;
 205
 206 again:
 207         prev_raw_count = local64_read(&hwc->prev_count);
 208         new_raw_count = armpmu->read_counter(idx);
 209
 210         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 211                              new_raw_count) != prev_raw_count)
 212                 goto again;
 213
 214         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 215         delta >>= shift;
 216
 217         local64_add(delta, &event->count);
 218         local64_sub(delta, &hwc->period_left);
 219
 220         return new_raw_count;
 221 }
 222
 223 static void
 224 armpmu_disable(struct perf_event *event)
 225 {
 226         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 227         struct hw_perf_event *hwc = &event->hw;
 228         int idx = hwc->idx;
 229
 230         WARN_ON(idx < 0);
 231
 232         clear_bit(idx, cpuc->active_mask);
 233         armpmu->disable(hwc, idx);
 234
 235         barrier();
 236
 237         armpmu_event_update(event, hwc, idx);
 238         cpuc->events[idx] = NULL;
 239         clear_bit(idx, cpuc->used_mask);
 240
 241         perf_event_update_userpage(event);
 242 }
 243
 244 static void
 245 armpmu_read(struct perf_event *event)
 246 {
 247         struct hw_perf_event *hwc = &event->hw;
 248
 249         /* Don't read disabled counters! */
 250         if (hwc->idx < 0)
 251                 return;
 252
 253         armpmu_event_update(event, hwc, hwc->idx);
 254 }
 255
 256 static void
 257 armpmu_unthrottle(struct perf_event *event)
 258 {
 259         struct hw_perf_event *hwc = &event->hw;
 260
 261         /*
 262          * Set the period again. Some counters can't be stopped, so when we
 263          * were throttled we simply disabled the IRQ source and the counter
 264          * may have been left counting. If we don't do this step then we may
 265          * get an interrupt too soon or *way* too late if the overflow has
 266          * happened since disabling.
 267          */
 268         armpmu_event_set_period(event, hwc, hwc->idx);
 269         armpmu->enable(hwc, hwc->idx);
 270 }
 271
 272 static int
 273 armpmu_enable(struct perf_event *event)
 274 {
 275         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 276         struct hw_perf_event *hwc = &event->hw;
 277         int idx;
 278         int err = 0;
 279
 280         /* If we don't have a space for the counter then finish early. */
 281         idx = armpmu->get_event_idx(cpuc, hwc);
 282         if (idx < 0) {
 283                 err = idx;
 284                 goto out;
 285         }
 286
 287         /*
 288          * If there is an event in the counter we are going to use then make
 289          * sure it is disabled.
 290          */
 291         event->hw.idx = idx;
 292         armpmu->disable(hwc, idx);
 293         cpuc->events[idx] = event;
 294         set_bit(idx, cpuc->active_mask);
 295
 296         /* Set the period for the event. */
 297         armpmu_event_set_period(event, hwc, idx);
 298
 299         /* Enable the event. */
 300         armpmu->enable(hwc, idx);
 301
 302         /* Propagate our changes to the userspace mapping. */
 303         perf_event_update_userpage(event);
 304
 305 out:
 306         return err;
 307 }
 308
 309 static struct pmu pmu;
 310
 311 static int
 312 validate_event(struct cpu_hw_events *cpuc,
 313                struct perf_event *event)
 314 {
 315         struct hw_perf_event fake_event = event->hw;
 316
 317         if (event->pmu && event->pmu != &pmu)
 318                 return 0;
 319
 320         return armpmu->get_event_idx(cpuc, &fake_event) >= 0;
 321 }
 322
 323 static int
 324 validate_group(struct perf_event *event)
 325 {
 326         struct perf_event *sibling, *leader = event->group_leader;
 327         struct cpu_hw_events fake_pmu;
 328
 329         memset(&fake_pmu, 0, sizeof(fake_pmu));
 330
 331         if (!validate_event(&fake_pmu, leader))
 332                 return -ENOSPC;
 333
 334         list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
 335                 if (!validate_event(&fake_pmu, sibling))
 336                         return -ENOSPC;
 337         }
 338
 339         if (!validate_event(&fake_pmu, event))
 340                 return -ENOSPC;
 341
 342         return 0;
 343 }
 344
 345 static int
 346 armpmu_reserve_hardware(void)
 347 {
 348         int i, err = -ENODEV, irq;
 349
 350         pmu_device = reserve_pmu(ARM_PMU_DEVICE_CPU);
 351         if (IS_ERR(pmu_device)) {
 352                 pr_warning("unable to reserve pmu\n");
 353                 return PTR_ERR(pmu_device);
 354         }
 355
 356         init_pmu(ARM_PMU_DEVICE_CPU);
 357
 358         if (pmu_device->num_resources < 1) {
 359                 pr_err("no irqs for PMUs defined\n");
 360                 return -ENODEV;
 361         }
 362
 363         for (i = 0; i < pmu_device->num_resources; ++i) {
 364                 irq = platform_get_irq(pmu_device, i);
 365                 if (irq < 0)
 366                         continue;
 367
 368                 err = request_irq(irq, armpmu->handle_irq,
 369                                   IRQF_DISABLED | IRQF_NOBALANCING,
 370                                   "armpmu", NULL);
 371                 if (err) {
 372                         pr_warning("unable to request IRQ%d for ARM perf "
 373                                 "counters\n", irq);
 374                         break;
 375                 }
 376         }
 377
 378         if (err) {
 379                 for (i = i - 1; i >= 0; --i) {
 380                         irq = platform_get_irq(pmu_device, i);
 381                         if (irq >= 0)
 382                                 free_irq(irq, NULL);
 383                 }
 384                 release_pmu(pmu_device);
 385                 pmu_device = NULL;
 386         }
 387
 388         return err;
 389 }
 390
 391 static void
 392 armpmu_release_hardware(void)
 393 {
 394         int i, irq;
 395
 396         for (i = pmu_device->num_resources - 1; i >= 0; --i) {
 397                 irq = platform_get_irq(pmu_device, i);
 398                 if (irq >= 0)
 399                         free_irq(irq, NULL);
 400         }
 401         armpmu->stop();
 402
 403         release_pmu(pmu_device);
 404         pmu_device = NULL;
 405 }
 406
 407 static atomic_t active_events = ATOMIC_INIT(0);
 408 static DEFINE_MUTEX(pmu_reserve_mutex);
 409
 410 static void
 411 hw_perf_event_destroy(struct perf_event *event)
 412 {
 413         if (atomic_dec_and_mutex_lock(&active_events, &pmu_reserve_mutex)) {
 414                 armpmu_release_hardware();
 415                 mutex_unlock(&pmu_reserve_mutex);
 416         }
 417 }
 418
 419 static int
 420 __hw_perf_event_init(struct perf_event *event)
 421 {
 422         struct hw_perf_event *hwc = &event->hw;
 423         int mapping, err;
 424
 425         /* Decode the generic type into an ARM event identifier. */
 426         if (PERF_TYPE_HARDWARE == event->attr.type) {
 427                 mapping = armpmu->event_map(event->attr.config);
 428         } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
 429                 mapping = armpmu_map_cache_event(event->attr.config);
 430         } else if (PERF_TYPE_RAW == event->attr.type) {
 431                 mapping = armpmu->raw_event(event->attr.config);
 432         } else {
 433                 pr_debug("event type %x not supported\n", event->attr.type);
 434                 return -EOPNOTSUPP;
 435         }
 436
 437         if (mapping < 0) {
 438                 pr_debug("event %x:%llx not supported\n", event->attr.type,
 439                          event->attr.config);
 440                 return mapping;
 441         }
 442
 443         /*
 444          * Check whether we need to exclude the counter from certain modes.
 445          * The ARM performance counters are on all of the time so if someone
 446          * has asked us for some excludes then we have to fail.
 447          */
 448         if (event->attr.exclude_kernel || event->attr.exclude_user ||
 449             event->attr.exclude_hv || event->attr.exclude_idle) {
 450                 pr_debug("ARM performance counters do not support "
 451                          "mode exclusion\n");
 452                 return -EPERM;
 453         }
 454
 455         /*
 456          * We don't assign an index until we actually place the event onto
 457          * hardware. Use -1 to signify that we haven't decided where to put it
 458          * yet. For SMP systems, each core has it's own PMU so we can't do any
 459          * clever allocation or constraints checking at this point.
 460          */
 461         hwc->idx = -1;
 462
 463         /*
 464          * Store the event encoding into the config_base field. config and
 465          * event_base are unused as the only 2 things we need to know are
 466          * the event mapping and the counter to use. The counter to use is
 467          * also the indx and the config_base is the event type.
 468          */
 469         hwc->config_base            = (unsigned long)mapping;
 470         hwc->config                 = 0;
 471         hwc->event_base             = 0;
 472
 473         if (!hwc->sample_period) {
 474                 hwc->sample_period  = armpmu->max_period;
 475                 hwc->last_period    = hwc->sample_period;
 476                 local64_set(&hwc->period_left, hwc->sample_period);
 477         }
 478
 479         err = 0;
 480         if (event->group_leader != event) {
 481                 err = validate_group(event);
 482                 if (err)
 483                         return -EINVAL;
 484         }
 485
 486         return err;
 487 }
 488
 489 static int armpmu_event_init(struct perf_event *event)
 490 {
 491         int err = 0;
 492
 493         switch (event->attr.type) {
 494         case PERF_TYPE_RAW:
 495         case PERF_TYPE_HARDWARE:
 496         case PERF_TYPE_HW_CACHE:
 497                 break;
 498
 499         default:
 500                 return -ENOENT;
 501         }
 502
 503         if (!armpmu)
 504                 return -ENODEV;
 505
 506         event->destroy = hw_perf_event_destroy;
 507
 508         if (!atomic_inc_not_zero(&active_events)) {
 509                 if (atomic_read(&active_events) > perf_max_events) {
 510                         atomic_dec(&active_events);
 511                         return -ENOSPC;
 512                 }
 513
 514                 mutex_lock(&pmu_reserve_mutex);
 515                 if (atomic_read(&active_events) == 0) {
 516                         err = armpmu_reserve_hardware();
 517                 }
 518
 519                 if (!err)
 520                         atomic_inc(&active_events);
 521                 mutex_unlock(&pmu_reserve_mutex);
 522         }
 523
 524         if (err)
 525                 return err;
 526
 527         err = __hw_perf_event_init(event);
 528         if (err)
 529                 hw_perf_event_destroy(event);
 530
 531         return err;
 532 }
 533
 534 static struct pmu pmu = {
 535         .event_init = armpmu_event_init,
 536         .enable     = armpmu_enable,
 537         .disable    = armpmu_disable,
 538         .unthrottle = armpmu_unthrottle,
 539         .read       = armpmu_read,
 540 };
 541
 542 void
 543 hw_perf_enable(void)
 544 {
 545         /* Enable all of the perf events on hardware. */
 546         int idx;
 547         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 548
 549         if (!armpmu)
 550                 return;
 551
 552         for (idx = 0; idx <= armpmu->num_events; ++idx) {
 553                 struct perf_event *event = cpuc->events[idx];
 554
 555                 if (!event)
 556                         continue;
 557
 558                 armpmu->enable(&event->hw, idx);
 559         }
 560
 561         armpmu->start();
 562 }
 563
 564 void
 565 hw_perf_disable(void)
 566 {
 567         if (armpmu)
 568                 armpmu->stop();
 569 }
 570
 571 /*
 572  * ARMv6 Performance counter handling code.
 573  *
 574  * ARMv6 has 2 configurable performance counters and a single cycle counter.
 575  * They all share a single reset bit but can be written to zero so we can use
 576  * that for a reset.
 577  *
 578  * The counters can't be individually enabled or disabled so when we remove
 579  * one event and replace it with another we could get spurious counts from the
 580  * wrong event. However, we can take advantage of the fact that the
 581  * performance counters can export events to the event bus, and the event bus
 582  * itself can be monitored. This requires that we *don't* export the events to
 583  * the event bus. The procedure for disabling a configurable counter is:
 584  *      - change the counter to count the ETMEXTOUT[0] signal (0x20). This
 585  *        effectively stops the counter from counting.
 586  *      - disable the counter's interrupt generation (each counter has it's
 587  *        own interrupt enable bit).
 588  * Once stopped, the counter value can be written as 0 to reset.
 589  *
 590  * To enable a counter:
 591  *      - enable the counter's interrupt generation.
 592  *      - set the new event type.
 593  *
 594  * Note: the dedicated cycle counter only counts cycles and can't be
 595  * enabled/disabled independently of the others. When we want to disable the
 596  * cycle counter, we have to just disable the interrupt reporting and start
 597  * ignoring that counter. When re-enabling, we have to reset the value and
 598  * enable the interrupt.
 599  */
 600
 601 enum armv6_perf_types {
 602         ARMV6_PERFCTR_ICACHE_MISS           = 0x0,
 603         ARMV6_PERFCTR_IBUF_STALL            = 0x1,
 604         ARMV6_PERFCTR_DDEP_STALL            = 0x2,
 605         ARMV6_PERFCTR_ITLB_MISS             = 0x3,
 606         ARMV6_PERFCTR_DTLB_MISS             = 0x4,
 607         ARMV6_PERFCTR_BR_EXEC               = 0x5,
 608         ARMV6_PERFCTR_BR_MISPREDICT         = 0x6,
 609         ARMV6_PERFCTR_INSTR_EXEC            = 0x7,
 610         ARMV6_PERFCTR_DCACHE_HIT            = 0x9,
 611         ARMV6_PERFCTR_DCACHE_ACCESS         = 0xA,
 612         ARMV6_PERFCTR_DCACHE_MISS           = 0xB,
 613         ARMV6_PERFCTR_DCACHE_WBACK          = 0xC,
 614         ARMV6_PERFCTR_SW_PC_CHANGE          = 0xD,
 615         ARMV6_PERFCTR_MAIN_TLB_MISS         = 0xF,
 616         ARMV6_PERFCTR_EXPL_D_ACCESS         = 0x10,
 617         ARMV6_PERFCTR_LSU_FULL_STALL        = 0x11,
 618         ARMV6_PERFCTR_WBUF_DRAINED          = 0x12,
 619         ARMV6_PERFCTR_CPU_CYCLES            = 0xFF,
 620         ARMV6_PERFCTR_NOP                   = 0x20,
 621 };
 622
 623 enum armv6_counters {
 624         ARMV6_CYCLE_COUNTER = 1,
 625         ARMV6_COUNTER0,
 626         ARMV6_COUNTER1,
 627 };
 628
 629 /*
 630  * The hardware events that we support. We do support cache operations but
 631  * we have harvard caches and no way to combine instruction and data
 632  * accesses/misses in hardware.
 633  */
 634 static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = {
 635         [PERF_COUNT_HW_CPU_CYCLES]          = ARMV6_PERFCTR_CPU_CYCLES,
 636         [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV6_PERFCTR_INSTR_EXEC,
 637         [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
 638         [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
 639         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC,
 640         [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV6_PERFCTR_BR_MISPREDICT,
 641         [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
 642 };
 643
 644 static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 645                                           [PERF_COUNT_HW_CACHE_OP_MAX]
 646                                           [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 647         [C(L1D)] = {
 648                 /*
 649                  * The performance counters don't differentiate between read
 650                  * and write accesses/misses so this isn't strictly correct,
 651                  * but it's the best we can do. Writes and reads get
 652                  * combined.
 653                  */
 654                 [C(OP_READ)] = {
 655                         [C(RESULT_ACCESS)]      = ARMV6_PERFCTR_DCACHE_ACCESS,
 656                         [C(RESULT_MISS)]        = ARMV6_PERFCTR_DCACHE_MISS,
 657                 },
 658                 [C(OP_WRITE)] = {
 659                         [C(RESULT_ACCESS)]      = ARMV6_PERFCTR_DCACHE_ACCESS,
 660                         [C(RESULT_MISS)]        = ARMV6_PERFCTR_DCACHE_MISS,
 661                 },
 662                 [C(OP_PREFETCH)] = {
 663                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 664                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 665                 },
 666         },
 667         [C(L1I)] = {
 668                 [C(OP_READ)] = {
 669                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 670                         [C(RESULT_MISS)]        = ARMV6_PERFCTR_ICACHE_MISS,
 671                 },
 672                 [C(OP_WRITE)] = {
 673                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 674                         [C(RESULT_MISS)]        = ARMV6_PERFCTR_ICACHE_MISS,
 675                 },
 676                 [C(OP_PREFETCH)] = {
 677                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 678                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 679                 },
 680         },
 681         [C(LL)] = {
 682                 [C(OP_READ)] = {
 683                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 684                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 685                 },
 686                 [C(OP_WRITE)] = {
 687                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 688                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 689                 },
 690                 [C(OP_PREFETCH)] = {
 691                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 692                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 693                 },
 694         },
 695         [C(DTLB)] = {
 696                 /*
 697                  * The ARM performance counters can count micro DTLB misses,
 698                  * micro ITLB misses and main TLB misses. There isn't an event
 699                  * for TLB misses, so use the micro misses here and if users
 700                  * want the main TLB misses they can use a raw counter.
 701                  */
 702                 [C(OP_READ)] = {
 703                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 704                         [C(RESULT_MISS)]        = ARMV6_PERFCTR_DTLB_MISS,
 705                 },
 706                 [C(OP_WRITE)] = {
 707                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 708                         [C(RESULT_MISS)]        = ARMV6_PERFCTR_DTLB_MISS,
 709                 },
 710                 [C(OP_PREFETCH)] = {
 711                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 712                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 713                 },
 714         },
 715         [C(ITLB)] = {
 716                 [C(OP_READ)] = {
 717                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 718                         [C(RESULT_MISS)]        = ARMV6_PERFCTR_ITLB_MISS,
 719                 },
 720                 [C(OP_WRITE)] = {
 721                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 722                         [C(RESULT_MISS)]        = ARMV6_PERFCTR_ITLB_MISS,
 723                 },
 724                 [C(OP_PREFETCH)] = {
 725                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 726                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 727                 },
 728         },
 729         [C(BPU)] = {
 730                 [C(OP_READ)] = {
 731                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 732                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 733                 },
 734                 [C(OP_WRITE)] = {
 735                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 736                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 737                 },
 738                 [C(OP_PREFETCH)] = {
 739                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
 740                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
 741                 },
 742         },
 743 };
 744
 745 enum armv6mpcore_perf_types {
 746         ARMV6MPCORE_PERFCTR_ICACHE_MISS     = 0x0,
 747         ARMV6MPCORE_PERFCTR_IBUF_STALL      = 0x1,
 748         ARMV6MPCORE_PERFCTR_DDEP_STALL      = 0x2,
 749         ARMV6MPCORE_PERFCTR_ITLB_MISS       = 0x3,
 750         ARMV6MPCORE_PERFCTR_DTLB_MISS       = 0x4,
 751         ARMV6MPCORE_PERFCTR_BR_EXEC         = 0x5,
 752         ARMV6MPCORE_PERFCTR_BR_NOTPREDICT   = 0x6,
 753         ARMV6MPCORE_PERFCTR_BR_MISPREDICT   = 0x7,
 754         ARMV6MPCORE_PERFCTR_INSTR_EXEC      = 0x8,
 755         ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS = 0xA,
 756         ARMV6MPCORE_PERFCTR_DCACHE_RDMISS   = 0xB,
 757         ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS = 0xC,
 758         ARMV6MPCORE_PERFCTR_DCACHE_WRMISS   = 0xD,
 759         ARMV6MPCORE_PERFCTR_DCACHE_EVICTION = 0xE,
 760         ARMV6MPCORE_PERFCTR_SW_PC_CHANGE    = 0xF,
 761         ARMV6MPCORE_PERFCTR_MAIN_TLB_MISS   = 0x10,
 762         ARMV6MPCORE_PERFCTR_EXPL_MEM_ACCESS = 0x11,
 763         ARMV6MPCORE_PERFCTR_LSU_FULL_STALL  = 0x12,
 764         ARMV6MPCORE_PERFCTR_WBUF_DRAINED    = 0x13,
 765         ARMV6MPCORE_PERFCTR_CPU_CYCLES      = 0xFF,
 766 };
 767
 768 /*
 769  * The hardware events that we support. We do support cache operations but
 770  * we have harvard caches and no way to combine instruction and data
 771  * accesses/misses in hardware.
 772  */
 773 static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
 774         [PERF_COUNT_HW_CPU_CYCLES]          = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
 775         [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
 776         [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
 777         [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
 778         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC,
 779         [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
 780         [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
 781 };
 782
 783 static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 784                                         [PERF_COUNT_HW_CACHE_OP_MAX]
 785                                         [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 786         [C(L1D)] = {
 787                 [C(OP_READ)] = {
 788                         [C(RESULT_ACCESS)]  =
 789                                 ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS,
 790                         [C(RESULT_MISS)]    =
 791                                 ARMV6MPCORE_PERFCTR_DCACHE_RDMISS,
 792                 },
 793                 [C(OP_WRITE)] = {
 794                         [C(RESULT_ACCESS)]  =
 795                                 ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS,
 796                         [C(RESULT_MISS)]    =
 797                                 ARMV6MPCORE_PERFCTR_DCACHE_WRMISS,
 798                 },
 799                 [C(OP_PREFETCH)] = {
 800                         [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
 801                         [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
 802                 },
 803         },
 804         [C(L1I)] = {
 805                 [C(OP_READ)] = {
 806                         [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
 807                         [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
 808                 },
 809                 [C(OP_WRITE)] = {
 810                         [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
 811                         [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
 812                 },
 813                 [C(OP_PREFETCH)] = {
 814                         [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
 815                         [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
 816                 },
 817         },
 818         [C(LL)] = {
 819                 [C(OP_READ)] = {
 820                         [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
 821                         [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
 822                 },
 823                 [C(OP_WRITE)] = {
 824                         [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
 825                         [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
 826                 },
 827                 [C(OP_PREFETCH)] = {
 828                         [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
 829                         [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
 830                 },
 831         },
 832         [C(DTLB)] = {
 833                 /*
 834                  * The ARM performance counters can count micro DTLB misses,
 835                  * micro ITLB misses and main TLB misses. There isn't an event
 836                  * for TLB misses, so use the micro misses here and if users
 837                  * want the main TLB misses they can use a raw counter.
 838                  */
 839                 [C(OP_READ)] = {
 840                         [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
 841                         [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_DTLB_MISS,
 842                 },
 843                 [C(OP_WRITE)] = {
 844                         [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
 845                         [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_DTLB_MISS,
 846                 },
 847                 [C(OP_PREFETCH)] = {
 848                         [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
 849                         [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
 850                 },
 851         },
 852         [C(ITLB)] = {
 853                 [C(OP_READ)] = {
 854                         [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
 855                         [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ITLB_MISS,
 856                 },
 857                 [C(OP_WRITE)] = {
 858                         [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
 859                         [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ITLB_MISS,
 860                 },
 861                 [C(OP_PREFETCH)] = {
 862                         [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
 863                         [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
 864                 },
 865         },
 866         [C(BPU)] = {
 867                 [C(OP_READ)] = {
 868                         [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
 869                         [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
 870                 },
 871                 [C(OP_WRITE)] = {
 872                         [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
 873                         [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
 874                 },
 875                 [C(OP_PREFETCH)] = {
 876                         [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
 877                         [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
 878                 },
 879         },
 880 };
 881
 882 static inline unsigned long
 883 armv6_pmcr_read(void)
 884 {
 885         u32 val;
 886         asm volatile("mrc   p15, 0, %0, c15, c12, 0" : "=r"(val));
 887         return val;
 888 }
 889
 890 static inline void
 891 armv6_pmcr_write(unsigned long val)
 892 {
 893         asm volatile("mcr   p15, 0, %0, c15, c12, 0" : : "r"(val));
 894 }
 895
 896 #define ARMV6_PMCR_ENABLE               (1 << 0)
 897 #define ARMV6_PMCR_CTR01_RESET          (1 << 1)
 898 #define ARMV6_PMCR_CCOUNT_RESET         (1 << 2)
 899 #define ARMV6_PMCR_CCOUNT_DIV           (1 << 3)
 900 #define ARMV6_PMCR_COUNT0_IEN           (1 << 4)
 901 #define ARMV6_PMCR_COUNT1_IEN           (1 << 5)
 902 #define ARMV6_PMCR_CCOUNT_IEN           (1 << 6)
 903 #define ARMV6_PMCR_COUNT0_OVERFLOW      (1 << 8)
 904 #define ARMV6_PMCR_COUNT1_OVERFLOW      (1 << 9)
 905 #define ARMV6_PMCR_CCOUNT_OVERFLOW      (1 << 10)
 906 #define ARMV6_PMCR_EVT_COUNT0_SHIFT     20
 907 #define ARMV6_PMCR_EVT_COUNT0_MASK      (0xFF << ARMV6_PMCR_EVT_COUNT0_SHIFT)
 908 #define ARMV6_PMCR_EVT_COUNT1_SHIFT     12
 909 #define ARMV6_PMCR_EVT_COUNT1_MASK      (0xFF << ARMV6_PMCR_EVT_COUNT1_SHIFT)
 910
 911 #define ARMV6_PMCR_OVERFLOWED_MASK \
 912         (ARMV6_PMCR_COUNT0_OVERFLOW | ARMV6_PMCR_COUNT1_OVERFLOW | \
 913          ARMV6_PMCR_CCOUNT_OVERFLOW)
 914
 915 static inline int
 916 armv6_pmcr_has_overflowed(unsigned long pmcr)
 917 {
 918         return (pmcr & ARMV6_PMCR_OVERFLOWED_MASK);
 919 }
 920
 921 static inline int
 922 armv6_pmcr_counter_has_overflowed(unsigned long pmcr,
 923                                   enum armv6_counters counter)
 924 {
 925         int ret = 0;
 926
 927         if (ARMV6_CYCLE_COUNTER == counter)
 928                 ret = pmcr & ARMV6_PMCR_CCOUNT_OVERFLOW;
 929         else if (ARMV6_COUNTER0 == counter)
 930                 ret = pmcr & ARMV6_PMCR_COUNT0_OVERFLOW;
 931         else if (ARMV6_COUNTER1 == counter)
 932                 ret = pmcr & ARMV6_PMCR_COUNT1_OVERFLOW;
 933         else
 934                 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
 935
 936         return ret;
 937 }
 938
 939 static inline u32
 940 armv6pmu_read_counter(int counter)
 941 {
 942         unsigned long value = 0;
 943
 944         if (ARMV6_CYCLE_COUNTER == counter)
 945                 asm volatile("mrc   p15, 0, %0, c15, c12, 1" : "=r"(value));
 946         else if (ARMV6_COUNTER0 == counter)
 947                 asm volatile("mrc   p15, 0, %0, c15, c12, 2" : "=r"(value));
 948         else if (ARMV6_COUNTER1 == counter)
 949                 asm volatile("mrc   p15, 0, %0, c15, c12, 3" : "=r"(value));
 950         else
 951                 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
 952
 953         return value;
 954 }
 955
 956 static inline void
 957 armv6pmu_write_counter(int counter,
 958                        u32 value)
 959 {
 960         if (ARMV6_CYCLE_COUNTER == counter)
 961                 asm volatile("mcr   p15, 0, %0, c15, c12, 1" : : "r"(value));
 962         else if (ARMV6_COUNTER0 == counter)
 963                 asm volatile("mcr   p15, 0, %0, c15, c12, 2" : : "r"(value));
 964         else if (ARMV6_COUNTER1 == counter)
 965                 asm volatile("mcr   p15, 0, %0, c15, c12, 3" : : "r"(value));
 966         else
 967                 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
 968 }
 969
 970 void
 971 armv6pmu_enable_event(struct hw_perf_event *hwc,
 972                       int idx)
 973 {
 974         unsigned long val, mask, evt, flags;
 975
 976         if (ARMV6_CYCLE_COUNTER == idx) {
 977                 mask    = 0;
 978                 evt     = ARMV6_PMCR_CCOUNT_IEN;
 979         } else if (ARMV6_COUNTER0 == idx) {
 980                 mask    = ARMV6_PMCR_EVT_COUNT0_MASK;
 981                 evt     = (hwc->config_base << ARMV6_PMCR_EVT_COUNT0_SHIFT) |
 982                           ARMV6_PMCR_COUNT0_IEN;
 983         } else if (ARMV6_COUNTER1 == idx) {
 984                 mask    = ARMV6_PMCR_EVT_COUNT1_MASK;
 985                 evt     = (hwc->config_base << ARMV6_PMCR_EVT_COUNT1_SHIFT) |
 986                           ARMV6_PMCR_COUNT1_IEN;
 987         } else {
 988                 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
 989                 return;
 990         }
 991
 992         /*
 993          * Mask out the current event and set the counter to count the event
 994          * that we're interested in.
 995          */
 996         spin_lock_irqsave(&pmu_lock, flags);
 997         val = armv6_pmcr_read();
 998         val &= ~mask;
 999         val |= evt;
1000         armv6_pmcr_write(val);
1001         spin_unlock_irqrestore(&pmu_lock, flags);
1002 }
1003
1004 static irqreturn_t
1005 armv6pmu_handle_irq(int irq_num,
1006                     void *dev)
1007 {
1008         unsigned long pmcr = armv6_pmcr_read();
1009         struct perf_sample_data data;
1010         struct cpu_hw_events *cpuc;
1011         struct pt_regs *regs;
1012         int idx;
1013
1014         if (!armv6_pmcr_has_overflowed(pmcr))
1015                 return IRQ_NONE;
1016
1017         regs = get_irq_regs();
1018
1019         /*
1020          * The interrupts are cleared by writing the overflow flags back to
1021          * the control register. All of the other bits don't have any effect
1022          * if they are rewritten, so write the whole value back.
1023          */
1024         armv6_pmcr_write(pmcr);
1025
1026         perf_sample_data_init(&data, 0);
1027
1028         cpuc = &__get_cpu_var(cpu_hw_events);
1029         for (idx = 0; idx <= armpmu->num_events; ++idx) {
1030                 struct perf_event *event = cpuc->events[idx];
1031                 struct hw_perf_event *hwc;
1032
1033                 if (!test_bit(idx, cpuc->active_mask))
1034                         continue;
1035
1036                 /*
1037                  * We have a single interrupt for all counters. Check that
1038                  * each counter has overflowed before we process it.
1039                  */
1040                 if (!armv6_pmcr_counter_has_overflowed(pmcr, idx))
1041                         continue;
1042
1043                 hwc = &event->hw;
1044                 armpmu_event_update(event, hwc, idx);
1045                 data.period = event->hw.last_period;
1046                 if (!armpmu_event_set_period(event, hwc, idx))
1047                         continue;
1048
1049                 if (perf_event_overflow(event, 0, &data, regs))
1050                         armpmu->disable(hwc, idx);
1051         }
1052
1053         /*
1054          * Handle the pending perf events.
1055          *
1056          * Note: this call *must* be run with interrupts enabled. For
1057          * platforms that can have the PMU interrupts raised as a PMI, this
1058          * will not work.
1059          */
1060         perf_event_do_pending();
1061
1062         return IRQ_HANDLED;
1063 }
1064
1065 static void
1066 armv6pmu_start(void)
1067 {
1068         unsigned long flags, val;
1069
1070         spin_lock_irqsave(&pmu_lock, flags);
1071         val = armv6_pmcr_read();
1072         val |= ARMV6_PMCR_ENABLE;
1073         armv6_pmcr_write(val);
1074         spin_unlock_irqrestore(&pmu_lock, flags);
1075 }
1076
1077 void
1078 armv6pmu_stop(void)
1079 {
1080         unsigned long flags, val;
1081
1082         spin_lock_irqsave(&pmu_lock, flags);
1083         val = armv6_pmcr_read();
1084         val &= ~ARMV6_PMCR_ENABLE;
1085         armv6_pmcr_write(val);
1086         spin_unlock_irqrestore(&pmu_lock, flags);
1087 }
1088
1089 static inline int
1090 armv6pmu_event_map(int config)
1091 {
1092         int mapping = armv6_perf_map[config];
1093         if (HW_OP_UNSUPPORTED == mapping)
1094                 mapping = -EOPNOTSUPP;
1095         return mapping;
1096 }
1097
1098 static inline int
1099 armv6mpcore_pmu_event_map(int config)
1100 {
1101         int mapping = armv6mpcore_perf_map[config];
1102         if (HW_OP_UNSUPPORTED == mapping)
1103                 mapping = -EOPNOTSUPP;
1104         return mapping;
1105 }
1106
1107 static u64
1108 armv6pmu_raw_event(u64 config)
1109 {
1110         return config & 0xff;
1111 }
1112
1113 static int
1114 armv6pmu_get_event_idx(struct cpu_hw_events *cpuc,
1115                        struct hw_perf_event *event)
1116 {
1117         /* Always place a cycle counter into the cycle counter. */
1118         if (ARMV6_PERFCTR_CPU_CYCLES == event->config_base) {
1119                 if (test_and_set_bit(ARMV6_CYCLE_COUNTER, cpuc->used_mask))
1120                         return -EAGAIN;
1121
1122                 return ARMV6_CYCLE_COUNTER;
1123         } else {
1124                 /*
1125                  * For anything other than a cycle counter, try and use
1126                  * counter0 and counter1.
1127                  */
1128                 if (!test_and_set_bit(ARMV6_COUNTER1, cpuc->used_mask)) {
1129                         return ARMV6_COUNTER1;
1130                 }
1131
1132                 if (!test_and_set_bit(ARMV6_COUNTER0, cpuc->used_mask)) {
1133                         return ARMV6_COUNTER0;
1134                 }
1135
1136                 /* The counters are all in use. */
1137                 return -EAGAIN;
1138         }
1139 }
1140
1141 static void
1142 armv6pmu_disable_event(struct hw_perf_event *hwc,
1143                        int idx)
1144 {
1145         unsigned long val, mask, evt, flags;
1146
1147         if (ARMV6_CYCLE_COUNTER == idx) {
1148                 mask    = ARMV6_PMCR_CCOUNT_IEN;
1149                 evt     = 0;
1150         } else if (ARMV6_COUNTER0 == idx) {
1151                 mask    = ARMV6_PMCR_COUNT0_IEN | ARMV6_PMCR_EVT_COUNT0_MASK;
1152                 evt     = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT0_SHIFT;
1153         } else if (ARMV6_COUNTER1 == idx) {
1154                 mask    = ARMV6_PMCR_COUNT1_IEN | ARMV6_PMCR_EVT_COUNT1_MASK;
1155                 evt     = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT1_SHIFT;
1156         } else {
1157                 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
1158                 return;
1159         }
1160
1161         /*
1162          * Mask out the current event and set the counter to count the number
1163          * of ETM bus signal assertion cycles. The external reporting should
1164          * be disabled and so this should never increment.
1165          */
1166         spin_lock_irqsave(&pmu_lock, flags);
1167         val = armv6_pmcr_read();
1168         val &= ~mask;
1169         val |= evt;
1170         armv6_pmcr_write(val);
1171         spin_unlock_irqrestore(&pmu_lock, flags);
1172 }
1173
1174 static void
1175 armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
1176                               int idx)
1177 {
1178         unsigned long val, mask, flags, evt = 0;
1179
1180         if (ARMV6_CYCLE_COUNTER == idx) {
1181                 mask    = ARMV6_PMCR_CCOUNT_IEN;
1182         } else if (ARMV6_COUNTER0 == idx) {
1183                 mask    = ARMV6_PMCR_COUNT0_IEN;
1184         } else if (ARMV6_COUNTER1 == idx) {
1185                 mask    = ARMV6_PMCR_COUNT1_IEN;
1186         } else {
1187                 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
1188                 return;
1189         }
1190
1191         /*
1192          * Unlike UP ARMv6, we don't have a way of stopping the counters. We
1193          * simply disable the interrupt reporting.
1194          */
1195         spin_lock_irqsave(&pmu_lock, flags);
1196         val = armv6_pmcr_read();
1197         val &= ~mask;
1198         val |= evt;
1199         armv6_pmcr_write(val);
1200         spin_unlock_irqrestore(&pmu_lock, flags);
1201 }
1202
1203 static const struct arm_pmu armv6pmu = {
1204         .id                     = ARM_PERF_PMU_ID_V6,
1205         .handle_irq             = armv6pmu_handle_irq,
1206         .enable                 = armv6pmu_enable_event,
1207         .disable                = armv6pmu_disable_event,
1208         .event_map              = armv6pmu_event_map,
1209         .raw_event              = armv6pmu_raw_event,
1210         .read_counter           = armv6pmu_read_counter,
1211         .write_counter          = armv6pmu_write_counter,
1212         .get_event_idx          = armv6pmu_get_event_idx,
1213         .start                  = armv6pmu_start,
1214         .stop                   = armv6pmu_stop,
1215         .num_events             = 3,
1216         .max_period             = (1LLU << 32) - 1,
1217 };
1218
1219 /*
1220  * ARMv6mpcore is almost identical to single core ARMv6 with the exception
1221  * that some of the events have different enumerations and that there is no
1222  * *hack* to stop the programmable counters. To stop the counters we simply
1223  * disable the interrupt reporting and update the event. When unthrottling we
1224  * reset the period and enable the interrupt reporting.
1225  */
1226 static const struct arm_pmu armv6mpcore_pmu = {
1227         .id                     = ARM_PERF_PMU_ID_V6MP,
1228         .handle_irq             = armv6pmu_handle_irq,
1229         .enable                 = armv6pmu_enable_event,
1230         .disable                = armv6mpcore_pmu_disable_event,
1231         .event_map              = armv6mpcore_pmu_event_map,
1232         .raw_event              = armv6pmu_raw_event,
1233         .read_counter           = armv6pmu_read_counter,
1234         .write_counter          = armv6pmu_write_counter,
1235         .get_event_idx          = armv6pmu_get_event_idx,
1236         .start                  = armv6pmu_start,
1237         .stop                   = armv6pmu_stop,
1238         .num_events             = 3,
1239         .max_period             = (1LLU << 32) - 1,
1240 };
1241
1242 /*
1243  * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code.
1244  *
1245  * Copied from ARMv6 code, with the low level code inspired
1246  *  by the ARMv7 Oprofile code.
1247  *
1248  * Cortex-A8 has up to 4 configurable performance counters and
1249  *  a single cycle counter.
1250  * Cortex-A9 has up to 31 configurable performance counters and
1251  *  a single cycle counter.
1252  *
1253  * All counters can be enabled/disabled and IRQ masked separately. The cycle
1254  *  counter and all 4 performance counters together can be reset separately.
1255  */
1256
1257 /* Common ARMv7 event types */
1258 enum armv7_perf_types {
1259         ARMV7_PERFCTR_PMNC_SW_INCR              = 0x00,
1260         ARMV7_PERFCTR_IFETCH_MISS               = 0x01,
1261         ARMV7_PERFCTR_ITLB_MISS                 = 0x02,
1262         ARMV7_PERFCTR_DCACHE_REFILL             = 0x03,
1263         ARMV7_PERFCTR_DCACHE_ACCESS             = 0x04,
1264         ARMV7_PERFCTR_DTLB_REFILL               = 0x05,
1265         ARMV7_PERFCTR_DREAD                     = 0x06,
1266         ARMV7_PERFCTR_DWRITE                    = 0x07,
1267
1268         ARMV7_PERFCTR_EXC_TAKEN                 = 0x09,
1269         ARMV7_PERFCTR_EXC_EXECUTED              = 0x0A,
1270         ARMV7_PERFCTR_CID_WRITE                 = 0x0B,
1271         /* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
1272          * It counts:
1273          *  - all branch instructions,
1274          *  - instructions that explicitly write the PC,
1275          *  - exception generating instructions.
1276          */
1277         ARMV7_PERFCTR_PC_WRITE                  = 0x0C,
1278         ARMV7_PERFCTR_PC_IMM_BRANCH             = 0x0D,
1279         ARMV7_PERFCTR_UNALIGNED_ACCESS          = 0x0F,
1280         ARMV7_PERFCTR_PC_BRANCH_MIS_PRED        = 0x10,
1281         ARMV7_PERFCTR_CLOCK_CYCLES              = 0x11,
1282
1283         ARMV7_PERFCTR_PC_BRANCH_MIS_USED        = 0x12,
1284
1285         ARMV7_PERFCTR_CPU_CYCLES                = 0xFF
1286 };
1287
1288 /* ARMv7 Cortex-A8 specific event types */
1289 enum armv7_a8_perf_types {
1290         ARMV7_PERFCTR_INSTR_EXECUTED            = 0x08,
1291
1292         ARMV7_PERFCTR_PC_PROC_RETURN            = 0x0E,
1293
1294         ARMV7_PERFCTR_WRITE_BUFFER_FULL         = 0x40,
1295         ARMV7_PERFCTR_L2_STORE_MERGED           = 0x41,
1296         ARMV7_PERFCTR_L2_STORE_BUFF             = 0x42,
1297         ARMV7_PERFCTR_L2_ACCESS                 = 0x43,
1298         ARMV7_PERFCTR_L2_CACH_MISS              = 0x44,
1299         ARMV7_PERFCTR_AXI_READ_CYCLES           = 0x45,
1300         ARMV7_PERFCTR_AXI_WRITE_CYCLES          = 0x46,
1301         ARMV7_PERFCTR_MEMORY_REPLAY             = 0x47,
1302         ARMV7_PERFCTR_UNALIGNED_ACCESS_REPLAY   = 0x48,
1303         ARMV7_PERFCTR_L1_DATA_MISS              = 0x49,
1304         ARMV7_PERFCTR_L1_INST_MISS              = 0x4A,
1305         ARMV7_PERFCTR_L1_DATA_COLORING          = 0x4B,
1306         ARMV7_PERFCTR_L1_NEON_DATA              = 0x4C,
1307         ARMV7_PERFCTR_L1_NEON_CACH_DATA         = 0x4D,
1308         ARMV7_PERFCTR_L2_NEON                   = 0x4E,
1309         ARMV7_PERFCTR_L2_NEON_HIT               = 0x4F,
1310         ARMV7_PERFCTR_L1_INST                   = 0x50,
1311         ARMV7_PERFCTR_PC_RETURN_MIS_PRED        = 0x51,
1312         ARMV7_PERFCTR_PC_BRANCH_FAILED          = 0x52,
1313         ARMV7_PERFCTR_PC_BRANCH_TAKEN           = 0x53,
1314         ARMV7_PERFCTR_PC_BRANCH_EXECUTED        = 0x54,
1315         ARMV7_PERFCTR_OP_EXECUTED               = 0x55,
1316         ARMV7_PERFCTR_CYCLES_INST_STALL         = 0x56,
1317         ARMV7_PERFCTR_CYCLES_INST               = 0x57,
1318         ARMV7_PERFCTR_CYCLES_NEON_DATA_STALL    = 0x58,
1319         ARMV7_PERFCTR_CYCLES_NEON_INST_STALL    = 0x59,
1320         ARMV7_PERFCTR_NEON_CYCLES               = 0x5A,
1321
1322         ARMV7_PERFCTR_PMU0_EVENTS               = 0x70,
1323         ARMV7_PERFCTR_PMU1_EVENTS               = 0x71,
1324         ARMV7_PERFCTR_PMU_EVENTS                = 0x72,
1325 };
1326
1327 /* ARMv7 Cortex-A9 specific event types */
1328 enum armv7_a9_perf_types {
1329         ARMV7_PERFCTR_JAVA_HW_BYTECODE_EXEC     = 0x40,
1330         ARMV7_PERFCTR_JAVA_SW_BYTECODE_EXEC     = 0x41,
1331         ARMV7_PERFCTR_JAZELLE_BRANCH_EXEC       = 0x42,
1332
1333         ARMV7_PERFCTR_COHERENT_LINE_MISS        = 0x50,
1334         ARMV7_PERFCTR_COHERENT_LINE_HIT         = 0x51,
1335
1336         ARMV7_PERFCTR_ICACHE_DEP_STALL_CYCLES   = 0x60,
1337         ARMV7_PERFCTR_DCACHE_DEP_STALL_CYCLES   = 0x61,
1338         ARMV7_PERFCTR_TLB_MISS_DEP_STALL_CYCLES = 0x62,
1339         ARMV7_PERFCTR_STREX_EXECUTED_PASSED     = 0x63,
1340         ARMV7_PERFCTR_STREX_EXECUTED_FAILED     = 0x64,
1341         ARMV7_PERFCTR_DATA_EVICTION             = 0x65,
1342         ARMV7_PERFCTR_ISSUE_STAGE_NO_INST       = 0x66,
1343         ARMV7_PERFCTR_ISSUE_STAGE_EMPTY         = 0x67,
1344         ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE  = 0x68,
1345
1346         ARMV7_PERFCTR_PREDICTABLE_FUNCT_RETURNS = 0x6E,
1347
1348         ARMV7_PERFCTR_MAIN_UNIT_EXECUTED_INST   = 0x70,
1349         ARMV7_PERFCTR_SECOND_UNIT_EXECUTED_INST = 0x71,
1350         ARMV7_PERFCTR_LD_ST_UNIT_EXECUTED_INST  = 0x72,
1351         ARMV7_PERFCTR_FP_EXECUTED_INST          = 0x73,
1352         ARMV7_PERFCTR_NEON_EXECUTED_INST        = 0x74,
1353
1354         ARMV7_PERFCTR_PLD_FULL_DEP_STALL_CYCLES = 0x80,
1355         ARMV7_PERFCTR_DATA_WR_DEP_STALL_CYCLES  = 0x81,
1356         ARMV7_PERFCTR_ITLB_MISS_DEP_STALL_CYCLES        = 0x82,
1357         ARMV7_PERFCTR_DTLB_MISS_DEP_STALL_CYCLES        = 0x83,
1358         ARMV7_PERFCTR_MICRO_ITLB_MISS_DEP_STALL_CYCLES  = 0x84,
1359         ARMV7_PERFCTR_MICRO_DTLB_MISS_DEP_STALL_CYCLES  = 0x85,
1360         ARMV7_PERFCTR_DMB_DEP_STALL_CYCLES      = 0x86,
1361
1362         ARMV7_PERFCTR_INTGR_CLK_ENABLED_CYCLES  = 0x8A,
1363         ARMV7_PERFCTR_DATA_ENGINE_CLK_EN_CYCLES = 0x8B,
1364
1365         ARMV7_PERFCTR_ISB_INST                  = 0x90,
1366         ARMV7_PERFCTR_DSB_INST                  = 0x91,
1367         ARMV7_PERFCTR_DMB_INST                  = 0x92,
1368         ARMV7_PERFCTR_EXT_INTERRUPTS            = 0x93,
1369
1370         ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_COMPLETED     = 0xA0,
1371         ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_SKIPPED       = 0xA1,
1372         ARMV7_PERFCTR_PLE_FIFO_FLUSH            = 0xA2,
1373         ARMV7_PERFCTR_PLE_RQST_COMPLETED        = 0xA3,
1374         ARMV7_PERFCTR_PLE_FIFO_OVERFLOW         = 0xA4,
1375         ARMV7_PERFCTR_PLE_RQST_PROG             = 0xA5
1376 };
1377
1378 /*
1379  * Cortex-A8 HW events mapping
1380  *
1381  * The hardware events that we support. We do support cache operations but
1382  * we have harvard caches and no way to combine instruction and data
1383  * accesses/misses in hardware.
1384  */
1385 static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = {
1386         [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
1387         [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV7_PERFCTR_INSTR_EXECUTED,
1388         [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
1389         [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
1390         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
1391         [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1392         [PERF_COUNT_HW_BUS_CYCLES]          = ARMV7_PERFCTR_CLOCK_CYCLES,
1393 };
1394
1395 static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
1396                                           [PERF_COUNT_HW_CACHE_OP_MAX]
1397                                           [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1398         [C(L1D)] = {
1399                 /*
1400                  * The performance counters don't differentiate between read
1401                  * and write accesses/misses so this isn't strictly correct,
1402                  * but it's the best we can do. Writes and reads get
1403                  * combined.
1404                  */
1405                 [C(OP_READ)] = {
1406                         [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
1407                         [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
1408                 },
1409                 [C(OP_WRITE)] = {
1410                         [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
1411                         [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
1412                 },
1413                 [C(OP_PREFETCH)] = {
1414                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
1415                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
1416                 },
1417         },
1418         [C(L1I)] = {
1419                 [C(OP_READ)] = {
1420                         [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_INST,
1421                         [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_INST_MISS,
1422                 },
1423                 [C(OP_WRITE)] = {
1424                         [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_INST,
1425                         [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_INST_MISS,
1426                 },
1427                 [C(OP_PREFETCH)] = {
1428                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
1429                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
1430                 },
1431         },
1432         [C(LL)] = {
1433                 [C(OP_READ)] = {
1434                         [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L2_ACCESS,
1435                         [C(RESULT_MISS)]        = ARMV7_PERFCTR_L2_CACH_MISS,
1436                 },
1437                 [C(OP_WRITE)] = {
1438                         [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L2_ACCESS,
1439                         [C(RESULT_MISS)]        = ARMV7_PERFCTR_L2_CACH_MISS,
1440                 },
1441                 [C(OP_PREFETCH)] = {
1442                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
1443                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
1444                 },
1445         },
1446         [C(DTLB)] = {
1447                 /*
1448                  * Only ITLB misses and DTLB refills are supported.
1449                  * If users want the DTLB refills misses a raw counter
1450                  * must be used.
1451                  */
1452                 [C(OP_READ)] = {
1453                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
1454                         [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
1455                 },
1456                 [C(OP_WRITE)] = {
1457                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
1458                         [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
1459                 },
1460                 [C(OP_PREFETCH)] = {
1461                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
1462                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
1463                 },
1464         },
1465         [C(ITLB)] = {
1466                 [C(OP_READ)] = {
1467                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
1468                         [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
1469                 },
1470                 [C(OP_WRITE)] = {
1471                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
1472                         [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
1473                 },
1474                 [C(OP_PREFETCH)] = {
1475                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
1476                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
1477                 },
1478         },
1479         [C(BPU)] = {
1480                 [C(OP_READ)] = {
1481                         [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
1482                         [C(RESULT_MISS)]
1483                                         = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1484                 },
1485                 [C(OP_WRITE)] = {
1486                         [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
1487                         [C(RESULT_MISS)]
1488                                         = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1489                 },
1490                 [C(OP_PREFETCH)] = {
1491                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
1492                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
1493                 },
1494         },
1495 };
1496
1497 /*
1498  * Cortex-A9 HW events mapping
1499  */
1500 static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
1501         [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
1502         [PERF_COUNT_HW_INSTRUCTIONS]        =
1503                                         ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE,
1504         [PERF_COUNT_HW_CACHE_REFERENCES]    = ARMV7_PERFCTR_COHERENT_LINE_HIT,
1505         [PERF_COUNT_HW_CACHE_MISSES]        = ARMV7_PERFCTR_COHERENT_LINE_MISS,
1506         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
1507         [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1508         [PERF_COUNT_HW_BUS_CYCLES]          = ARMV7_PERFCTR_CLOCK_CYCLES,
1509 };
1510
1511 static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
1512                                           [PERF_COUNT_HW_CACHE_OP_MAX]
1513                                           [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1514         [C(L1D)] = {
1515                 /*
1516                  * The performance counters don't differentiate between read
1517                  * and write accesses/misses so this isn't strictly correct,
1518                  * but it's the best we can do. Writes and reads get
1519                  * combined.
1520                  */
1521                 [C(OP_READ)] = {
1522                         [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
1523                         [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
1524                 },
1525                 [C(OP_WRITE)] = {
1526                         [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
1527                         [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
1528                 },
1529                 [C(OP_PREFETCH)] = {
1530                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
1531                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
1532                 },
1533         },
1534         [C(L1I)] = {
1535                 [C(OP_READ)] = {
1536                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
1537                         [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
1538                 },
1539                 [C(OP_WRITE)] = {
1540                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
1541                         [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
1542                 },
1543                 [C(OP_PREFETCH)] = {
1544                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
1545                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
1546                 },
1547         },
1548         [C(LL)] = {
1549                 [C(OP_READ)] = {
1550                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
1551                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
1552                 },
1553                 [C(OP_WRITE)] = {
1554                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
1555                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
1556                 },
1557                 [C(OP_PREFETCH)] = {
1558                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
1559                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
1560                 },
1561         },
1562         [C(DTLB)] = {
1563                 /*
1564                  * Only ITLB misses and DTLB refills are supported.
1565                  * If users want the DTLB refills misses a raw counter
1566                  * must be used.
1567                  */
1568                 [C(OP_READ)] = {
1569                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
1570                         [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
1571                 },
1572                 [C(OP_WRITE)] = {
1573                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
1574                         [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
1575                 },
1576                 [C(OP_PREFETCH)] = {
1577                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
1578                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
1579                 },
1580         },
1581         [C(ITLB)] = {
1582                 [C(OP_READ)] = {
1583                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
1584                         [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
1585                 },
1586                 [C(OP_WRITE)] = {
1587                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
1588                         [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
1589                 },
1590                 [C(OP_PREFETCH)] = {
1591                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
1592                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
1593                 },
1594         },
1595         [C(BPU)] = {
1596                 [C(OP_READ)] = {
1597                         [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
1598                         [C(RESULT_MISS)]
1599                                         = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1600                 },
1601                 [C(OP_WRITE)] = {
1602                         [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
1603                         [C(RESULT_MISS)]
1604                                         = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1605                 },
1606                 [C(OP_PREFETCH)] = {
1607                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
1608                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
1609                 },
1610         },
1611 };
1612
1613 /*
1614  * Perf Events counters
1615  */
1616 enum armv7_counters {
1617         ARMV7_CYCLE_COUNTER             = 1,    /* Cycle counter */
1618         ARMV7_COUNTER0                  = 2,    /* First event counter */
1619 };
1620
1621 /*
1622  * The cycle counter is ARMV7_CYCLE_COUNTER.
1623  * The first event counter is ARMV7_COUNTER0.
1624  * The last event counter is (ARMV7_COUNTER0 + armpmu->num_events - 1).
1625  */
1626 #define ARMV7_COUNTER_LAST      (ARMV7_COUNTER0 + armpmu->num_events - 1)
1627
1628 /*
1629  * ARMv7 low level PMNC access
1630  */
1631
1632 /*
1633  * Per-CPU PMNC: config reg
1634  */
1635 #define ARMV7_PMNC_E            (1 << 0) /* Enable all counters */
1636 #define ARMV7_PMNC_P            (1 << 1) /* Reset all counters */
1637 #define ARMV7_PMNC_C            (1 << 2) /* Cycle counter reset */
1638 #define ARMV7_PMNC_D            (1 << 3) /* CCNT counts every 64th cpu cycle */
1639 #define ARMV7_PMNC_X            (1 << 4) /* Export to ETM */
1640 #define ARMV7_PMNC_DP           (1 << 5) /* Disable CCNT if non-invasive debug*/
1641 #define ARMV7_PMNC_N_SHIFT      11       /* Number of counters supported */
1642 #define ARMV7_PMNC_N_MASK       0x1f
1643 #define ARMV7_PMNC_MASK         0x3f     /* Mask for writable bits */
1644
1645 /*
1646  * Available counters
1647  */
1648 #define ARMV7_CNT0              0       /* First event counter */
1649 #define ARMV7_CCNT              31      /* Cycle counter */
1650
1651 /* Perf Event to low level counters mapping */
1652 #define ARMV7_EVENT_CNT_TO_CNTx (ARMV7_COUNTER0 - ARMV7_CNT0)
1653
1654 /*
1655  * CNTENS: counters enable reg
1656  */
1657 #define ARMV7_CNTENS_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
1658 #define ARMV7_CNTENS_C          (1 << ARMV7_CCNT)
1659
1660 /*
1661  * CNTENC: counters disable reg
1662  */
1663 #define ARMV7_CNTENC_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
1664 #define ARMV7_CNTENC_C          (1 << ARMV7_CCNT)
1665
1666 /*
1667  * INTENS: counters overflow interrupt enable reg
1668  */
1669 #define ARMV7_INTENS_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
1670 #define ARMV7_INTENS_C          (1 << ARMV7_CCNT)
1671
1672 /*
1673  * INTENC: counters overflow interrupt disable reg
1674  */
1675 #define ARMV7_INTENC_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
1676 #define ARMV7_INTENC_C          (1 << ARMV7_CCNT)
1677
1678 /*
1679  * EVTSEL: Event selection reg
1680  */
1681 #define ARMV7_EVTSEL_MASK       0xff            /* Mask for writable bits */
1682
1683 /*
1684  * SELECT: Counter selection reg
1685  */
1686 #define ARMV7_SELECT_MASK       0x1f            /* Mask for writable bits */
1687
1688 /*
1689  * FLAG: counters overflow flag status reg
1690  */
1691 #define ARMV7_FLAG_P(idx)       (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
1692 #define ARMV7_FLAG_C            (1 << ARMV7_CCNT)
1693 #define ARMV7_FLAG_MASK         0xffffffff      /* Mask for writable bits */
1694 #define ARMV7_OVERFLOWED_MASK   ARMV7_FLAG_MASK
1695
1696 static inline unsigned long armv7_pmnc_read(void)
1697 {
1698         u32 val;
1699         asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val));
1700         return val;
1701 }
1702
1703 static inline void armv7_pmnc_write(unsigned long val)
1704 {
1705         val &= ARMV7_PMNC_MASK;
1706         asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val));
1707 }
1708
1709 static inline int armv7_pmnc_has_overflowed(unsigned long pmnc)
1710 {
1711         return pmnc & ARMV7_OVERFLOWED_MASK;
1712 }
1713
1714 static inline int armv7_pmnc_counter_has_overflowed(unsigned long pmnc,
1715                                         enum armv7_counters counter)
1716 {
1717         int ret;
1718
1719         if (counter == ARMV7_CYCLE_COUNTER)
1720                 ret = pmnc & ARMV7_FLAG_C;
1721         else if ((counter >= ARMV7_COUNTER0) && (counter <= ARMV7_COUNTER_LAST))
1722                 ret = pmnc & ARMV7_FLAG_P(counter);
1723         else
1724                 pr_err("CPU%u checking wrong counter %d overflow status\n",
1725                         smp_processor_id(), counter);
1726
1727         return ret;
1728 }
1729
1730 static inline int armv7_pmnc_select_counter(unsigned int idx)
1731 {
1732         u32 val;
1733
1734         if ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST)) {
1735                 pr_err("CPU%u selecting wrong PMNC counter"
1736                         " %d\n", smp_processor_id(), idx);
1737                 return -1;
1738         }
1739
1740         val = (idx - ARMV7_EVENT_CNT_TO_CNTx) & ARMV7_SELECT_MASK;
1741         asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val));
1742
1743         return idx;
1744 }
1745
1746 static inline u32 armv7pmu_read_counter(int idx)
1747 {
1748         unsigned long value = 0;
1749
1750         if (idx == ARMV7_CYCLE_COUNTER)
1751                 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value));
1752         else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
1753                 if (armv7_pmnc_select_counter(idx) == idx)
1754                         asm volatile("mrc p15, 0, %0, c9, c13, 2"
1755                                      : "=r" (value));
1756         } else
1757                 pr_err("CPU%u reading wrong counter %d\n",
1758                         smp_processor_id(), idx);
1759
1760         return value;
1761 }
1762
1763 static inline void armv7pmu_write_counter(int idx, u32 value)
1764 {
1765         if (idx == ARMV7_CYCLE_COUNTER)
1766                 asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value));
1767         else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
1768                 if (armv7_pmnc_select_counter(idx) == idx)
1769                         asm volatile("mcr p15, 0, %0, c9, c13, 2"
1770                                      : : "r" (value));
1771         } else
1772                 pr_err("CPU%u writing wrong counter %d\n",
1773                         smp_processor_id(), idx);
1774 }
1775
1776 static inline void armv7_pmnc_write_evtsel(unsigned int idx, u32 val)
1777 {
1778         if (armv7_pmnc_select_counter(idx) == idx) {
1779                 val &= ARMV7_EVTSEL_MASK;
1780                 asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
1781         }
1782 }
1783
1784 static inline u32 armv7_pmnc_enable_counter(unsigned int idx)
1785 {
1786         u32 val;
1787
1788         if ((idx != ARMV7_CYCLE_COUNTER) &&
1789             ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
1790                 pr_err("CPU%u enabling wrong PMNC counter"
1791                         " %d\n", smp_processor_id(), idx);
1792                 return -1;
1793         }
1794
1795         if (idx == ARMV7_CYCLE_COUNTER)
1796                 val = ARMV7_CNTENS_C;
1797         else
1798                 val = ARMV7_CNTENS_P(idx);
1799
1800         asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
1801
1802         return idx;
1803 }
1804
1805 static inline u32 armv7_pmnc_disable_counter(unsigned int idx)
1806 {
1807         u32 val;
1808
1809
1810         if ((idx != ARMV7_CYCLE_COUNTER) &&
1811             ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
1812                 pr_err("CPU%u disabling wrong PMNC counter"
1813                         " %d\n", smp_processor_id(), idx);
1814                 return -1;
1815         }
1816
1817         if (idx == ARMV7_CYCLE_COUNTER)
1818                 val = ARMV7_CNTENC_C;
1819         else
1820                 val = ARMV7_CNTENC_P(idx);
1821
1822         asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val));
1823
1824         return idx;
1825 }
1826
1827 static inline u32 armv7_pmnc_enable_intens(unsigned int idx)
1828 {
1829         u32 val;
1830
1831         if ((idx != ARMV7_CYCLE_COUNTER) &&
1832             ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
1833                 pr_err("CPU%u enabling wrong PMNC counter"
1834                         " interrupt enable %d\n", smp_processor_id(), idx);
1835                 return -1;
1836         }
1837
1838         if (idx == ARMV7_CYCLE_COUNTER)
1839                 val = ARMV7_INTENS_C;
1840         else
1841                 val = ARMV7_INTENS_P(idx);
1842
1843         asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val));
1844
1845         return idx;
1846 }
1847
1848 static inline u32 armv7_pmnc_disable_intens(unsigned int idx)
1849 {
1850         u32 val;
1851
1852         if ((idx != ARMV7_CYCLE_COUNTER) &&
1853             ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
1854                 pr_err("CPU%u disabling wrong PMNC counter"
1855                         " interrupt enable %d\n", smp_processor_id(), idx);
1856                 return -1;
1857         }
1858
1859         if (idx == ARMV7_CYCLE_COUNTER)
1860                 val = ARMV7_INTENC_C;
1861         else
1862                 val = ARMV7_INTENC_P(idx);
1863
1864         asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (val));
1865
1866         return idx;
1867 }
1868
1869 static inline u32 armv7_pmnc_getreset_flags(void)
1870 {
1871         u32 val;
1872
1873         /* Read */
1874         asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
1875
1876         /* Write to clear flags */
1877         val &= ARMV7_FLAG_MASK;
1878         asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val));
1879
1880         return val;
1881 }
1882
1883 #ifdef DEBUG
1884 static void armv7_pmnc_dump_regs(void)
1885 {
1886         u32 val;
1887         unsigned int cnt;
1888
1889         printk(KERN_INFO "PMNC registers dump:\n");
1890
1891         asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
1892         printk(KERN_INFO "PMNC  =0x%08x\n", val);
1893
1894         asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));
1895         printk(KERN_INFO "CNTENS=0x%08x\n", val);
1896
1897         asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val));
1898         printk(KERN_INFO "INTENS=0x%08x\n", val);
1899
1900         asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
1901         printk(KERN_INFO "FLAGS =0x%08x\n", val);
1902
1903         asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val));
1904         printk(KERN_INFO "SELECT=0x%08x\n", val);
1905
1906         asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
1907         printk(KERN_INFO "CCNT  =0x%08x\n", val);
1908
1909         for (cnt = ARMV7_COUNTER0; cnt < ARMV7_COUNTER_LAST; cnt++) {
1910                 armv7_pmnc_select_counter(cnt);
1911                 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
1912                 printk(KERN_INFO "CNT[%d] count =0x%08x\n",
1913                         cnt-ARMV7_EVENT_CNT_TO_CNTx, val);
1914                 asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val));
1915                 printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n",
1916                         cnt-ARMV7_EVENT_CNT_TO_CNTx, val);
1917         }
1918 }
1919 #endif
1920
1921 void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
1922 {
1923         unsigned long flags;
1924
1925         /*
1926          * Enable counter and interrupt, and set the counter to count
1927          * the event that we're interested in.
1928          */
1929         spin_lock_irqsave(&pmu_lock, flags);
1930
1931         /*
1932          * Disable counter
1933          */
1934         armv7_pmnc_disable_counter(idx);
1935
1936         /*
1937          * Set event (if destined for PMNx counters)
1938          * We don't need to set the event if it's a cycle count
1939          */
1940         if (idx != ARMV7_CYCLE_COUNTER)
1941                 armv7_pmnc_write_evtsel(idx, hwc->config_base);
1942
1943         /*
1944          * Enable interrupt for this counter
1945          */
1946         armv7_pmnc_enable_intens(idx);
1947
1948         /*
1949          * Enable counter
1950          */
1951         armv7_pmnc_enable_counter(idx);
1952
1953         spin_unlock_irqrestore(&pmu_lock, flags);
1954 }
1955
1956 static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx)
1957 {
1958         unsigned long flags;
1959
1960         /*
1961          * Disable counter and interrupt
1962          */
1963         spin_lock_irqsave(&pmu_lock, flags);
1964
1965         /*
1966          * Disable counter
1967          */
1968         armv7_pmnc_disable_counter(idx);
1969
1970         /*
1971          * Disable interrupt for this counter
1972          */
1973         armv7_pmnc_disable_intens(idx);
1974
1975         spin_unlock_irqrestore(&pmu_lock, flags);
1976 }
1977
1978 static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
1979 {
1980         unsigned long pmnc;
1981         struct perf_sample_data data;
1982         struct cpu_hw_events *cpuc;
1983         struct pt_regs *regs;
1984         int idx;
1985
1986         /*
1987          * Get and reset the IRQ flags
1988          */
1989         pmnc = armv7_pmnc_getreset_flags();
1990
1991         /*
1992          * Did an overflow occur?
1993          */
1994         if (!armv7_pmnc_has_overflowed(pmnc))
1995                 return IRQ_NONE;
1996
1997         /*
1998          * Handle the counter(s) overflow(s)
1999          */
2000         regs = get_irq_regs();
2001
2002         perf_sample_data_init(&data, 0);
2003
2004         cpuc = &__get_cpu_var(cpu_hw_events);
2005         for (idx = 0; idx <= armpmu->num_events; ++idx) {
2006                 struct perf_event *event = cpuc->events[idx];
2007                 struct hw_perf_event *hwc;
2008
2009                 if (!test_bit(idx, cpuc->active_mask))
2010                         continue;
2011
2012                 /*
2013                  * We have a single interrupt for all counters. Check that
2014                  * each counter has overflowed before we process it.
2015                  */
2016                 if (!armv7_pmnc_counter_has_overflowed(pmnc, idx))
2017                         continue;
2018
2019                 hwc = &event->hw;
2020                 armpmu_event_update(event, hwc, idx);
2021                 data.period = event->hw.last_period;
2022                 if (!armpmu_event_set_period(event, hwc, idx))
2023                         continue;
2024
2025                 if (perf_event_overflow(event, 0, &data, regs))
2026                         armpmu->disable(hwc, idx);
2027         }
2028
2029         /*
2030          * Handle the pending perf events.
2031          *
2032          * Note: this call *must* be run with interrupts enabled. For
2033          * platforms that can have the PMU interrupts raised as a PMI, this
2034          * will not work.
2035          */
2036         perf_event_do_pending();
2037
2038         return IRQ_HANDLED;
2039 }
2040
2041 static void armv7pmu_start(void)
2042 {
2043         unsigned long flags;
2044
2045         spin_lock_irqsave(&pmu_lock, flags);
2046         /* Enable all counters */
2047         armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E);
2048         spin_unlock_irqrestore(&pmu_lock, flags);
2049 }
2050
2051 static void armv7pmu_stop(void)
2052 {
2053         unsigned long flags;
2054
2055         spin_lock_irqsave(&pmu_lock, flags);
2056         /* Disable all counters */
2057         armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E);
2058         spin_unlock_irqrestore(&pmu_lock, flags);
2059 }
2060
2061 static inline int armv7_a8_pmu_event_map(int config)
2062 {
2063         int mapping = armv7_a8_perf_map[config];
2064         if (HW_OP_UNSUPPORTED == mapping)
2065                 mapping = -EOPNOTSUPP;
2066         return mapping;
2067 }
2068
2069 static inline int armv7_a9_pmu_event_map(int config)
2070 {
2071         int mapping = armv7_a9_perf_map[config];
2072         if (HW_OP_UNSUPPORTED == mapping)
2073                 mapping = -EOPNOTSUPP;
2074         return mapping;
2075 }
2076
2077 static u64 armv7pmu_raw_event(u64 config)
2078 {
2079         return config & 0xff;
2080 }
2081
2082 static int armv7pmu_get_event_idx(struct cpu_hw_events *cpuc,
2083                                   struct hw_perf_event *event)
2084 {
2085         int idx;
2086
2087         /* Always place a cycle counter into the cycle counter. */
2088         if (event->config_base == ARMV7_PERFCTR_CPU_CYCLES) {
2089                 if (test_and_set_bit(ARMV7_CYCLE_COUNTER, cpuc->used_mask))
2090                         return -EAGAIN;
2091
2092                 return ARMV7_CYCLE_COUNTER;
2093         } else {
2094                 /*
2095                  * For anything other than a cycle counter, try and use
2096                  * the events counters
2097                  */
2098                 for (idx = ARMV7_COUNTER0; idx <= armpmu->num_events; ++idx) {
2099                         if (!test_and_set_bit(idx, cpuc->used_mask))
2100                                 return idx;
2101                 }
2102
2103                 /* The counters are all in use. */
2104                 return -EAGAIN;
2105         }
2106 }
2107
2108 static struct arm_pmu armv7pmu = {
2109         .handle_irq             = armv7pmu_handle_irq,
2110         .enable                 = armv7pmu_enable_event,
2111         .disable                = armv7pmu_disable_event,
2112         .raw_event              = armv7pmu_raw_event,
2113         .read_counter           = armv7pmu_read_counter,
2114         .write_counter          = armv7pmu_write_counter,
2115         .get_event_idx          = armv7pmu_get_event_idx,
2116         .start                  = armv7pmu_start,
2117         .stop                   = armv7pmu_stop,
2118         .max_period             = (1LLU << 32) - 1,
2119 };
2120
2121 static u32 __init armv7_reset_read_pmnc(void)
2122 {
2123         u32 nb_cnt;
2124
2125         /* Initialize & Reset PMNC: C and P bits */
2126         armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C);
2127
2128         /* Read the nb of CNTx counters supported from PMNC */
2129         nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK;
2130
2131         /* Add the CPU cycles counter and return */
2132         return nb_cnt + 1;
2133 }
2134
2135 /*
2136  * ARMv5 [xscale] Performance counter handling code.
2137  *
2138  * Based on xscale OProfile code.
2139  *
2140  * There are two variants of the xscale PMU that we support:
2141  *      - xscale1pmu: 2 event counters and a cycle counter
2142  *      - xscale2pmu: 4 event counters and a cycle counter
2143  * The two variants share event definitions, but have different
2144  * PMU structures.
2145  */
2146
2147 enum xscale_perf_types {
2148         XSCALE_PERFCTR_ICACHE_MISS              = 0x00,
2149         XSCALE_PERFCTR_ICACHE_NO_DELIVER        = 0x01,
2150         XSCALE_PERFCTR_DATA_STALL               = 0x02,
2151         XSCALE_PERFCTR_ITLB_MISS                = 0x03,
2152         XSCALE_PERFCTR_DTLB_MISS                = 0x04,
2153         XSCALE_PERFCTR_BRANCH                   = 0x05,
2154         XSCALE_PERFCTR_BRANCH_MISS              = 0x06,
2155         XSCALE_PERFCTR_INSTRUCTION              = 0x07,
2156         XSCALE_PERFCTR_DCACHE_FULL_STALL        = 0x08,
2157         XSCALE_PERFCTR_DCACHE_FULL_STALL_CONTIG = 0x09,
2158         XSCALE_PERFCTR_DCACHE_ACCESS            = 0x0A,
2159         XSCALE_PERFCTR_DCACHE_MISS              = 0x0B,
2160         XSCALE_PERFCTR_DCACHE_WRITE_BACK        = 0x0C,
2161         XSCALE_PERFCTR_PC_CHANGED               = 0x0D,
2162         XSCALE_PERFCTR_BCU_REQUEST              = 0x10,
2163         XSCALE_PERFCTR_BCU_FULL                 = 0x11,
2164         XSCALE_PERFCTR_BCU_DRAIN                = 0x12,
2165         XSCALE_PERFCTR_BCU_ECC_NO_ELOG          = 0x14,
2166         XSCALE_PERFCTR_BCU_1_BIT_ERR            = 0x15,
2167         XSCALE_PERFCTR_RMW                      = 0x16,
2168         /* XSCALE_PERFCTR_CCNT is not hardware defined */
2169         XSCALE_PERFCTR_CCNT                     = 0xFE,
2170         XSCALE_PERFCTR_UNUSED                   = 0xFF,
2171 };
2172
2173 enum xscale_counters {
2174         XSCALE_CYCLE_COUNTER    = 1,
2175         XSCALE_COUNTER0,
2176         XSCALE_COUNTER1,
2177         XSCALE_COUNTER2,
2178         XSCALE_COUNTER3,
2179 };
2180
2181 static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = {
2182         [PERF_COUNT_HW_CPU_CYCLES]          = XSCALE_PERFCTR_CCNT,
2183         [PERF_COUNT_HW_INSTRUCTIONS]        = XSCALE_PERFCTR_INSTRUCTION,
2184         [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
2185         [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
2186         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH,
2187         [PERF_COUNT_HW_BRANCH_MISSES]       = XSCALE_PERFCTR_BRANCH_MISS,
2188         [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
2189 };
2190
2191 static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
2192                                            [PERF_COUNT_HW_CACHE_OP_MAX]
2193                                            [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2194         [C(L1D)] = {
2195                 [C(OP_READ)] = {
2196                         [C(RESULT_ACCESS)]      = XSCALE_PERFCTR_DCACHE_ACCESS,
2197                         [C(RESULT_MISS)]        = XSCALE_PERFCTR_DCACHE_MISS,
2198                 },
2199                 [C(OP_WRITE)] = {
2200                         [C(RESULT_ACCESS)]      = XSCALE_PERFCTR_DCACHE_ACCESS,
2201                         [C(RESULT_MISS)]        = XSCALE_PERFCTR_DCACHE_MISS,
2202                 },
2203                 [C(OP_PREFETCH)] = {
2204                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
2205                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
2206                 },
2207         },
2208         [C(L1I)] = {
2209                 [C(OP_READ)] = {
2210                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
2211                         [C(RESULT_MISS)]        = XSCALE_PERFCTR_ICACHE_MISS,
2212                 },
2213                 [C(OP_WRITE)] = {
2214                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
2215                         [C(RESULT_MISS)]        = XSCALE_PERFCTR_ICACHE_MISS,
2216                 },
2217                 [C(OP_PREFETCH)] = {
2218                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
2219                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
2220                 },
2221         },
2222         [C(LL)] = {
2223                 [C(OP_READ)] = {
2224                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
2225                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
2226                 },
2227                 [C(OP_WRITE)] = {
2228                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
2229                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
2230                 },
2231                 [C(OP_PREFETCH)] = {
2232                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
2233                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
2234                 },
2235         },
2236         [C(DTLB)] = {
2237                 [C(OP_READ)] = {
2238                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
2239                         [C(RESULT_MISS)]        = XSCALE_PERFCTR_DTLB_MISS,
2240                 },
2241                 [C(OP_WRITE)] = {
2242                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
2243                         [C(RESULT_MISS)]        = XSCALE_PERFCTR_DTLB_MISS,
2244                 },
2245                 [C(OP_PREFETCH)] = {
2246                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
2247                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
2248                 },
2249         },
2250         [C(ITLB)] = {
2251                 [C(OP_READ)] = {
2252                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
2253                         [C(RESULT_MISS)]        = XSCALE_PERFCTR_ITLB_MISS,
2254                 },
2255                 [C(OP_WRITE)] = {
2256                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
2257                         [C(RESULT_MISS)]        = XSCALE_PERFCTR_ITLB_MISS,
2258                 },
2259                 [C(OP_PREFETCH)] = {
2260                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
2261                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
2262                 },
2263         },
2264         [C(BPU)] = {
2265                 [C(OP_READ)] = {
2266                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
2267                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
2268                 },
2269                 [C(OP_WRITE)] = {
2270                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
2271                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
2272                 },
2273                 [C(OP_PREFETCH)] = {
2274                         [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
2275                         [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
2276                 },
2277         },
2278 };
2279
2280 #define XSCALE_PMU_ENABLE       0x001
2281 #define XSCALE_PMN_RESET        0x002
2282 #define XSCALE_CCNT_RESET       0x004
2283 #define XSCALE_PMU_RESET        (CCNT_RESET | PMN_RESET)
2284 #define XSCALE_PMU_CNT64        0x008
2285
2286 static inline int
2287 xscalepmu_event_map(int config)
2288 {
2289         int mapping = xscale_perf_map[config];
2290         if (HW_OP_UNSUPPORTED == mapping)
2291                 mapping = -EOPNOTSUPP;
2292         return mapping;
2293 }
2294
2295 static u64
2296 xscalepmu_raw_event(u64 config)
2297 {
2298         return config & 0xff;
2299 }
2300
2301 #define XSCALE1_OVERFLOWED_MASK 0x700
2302 #define XSCALE1_CCOUNT_OVERFLOW 0x400
2303 #define XSCALE1_COUNT0_OVERFLOW 0x100
2304 #define XSCALE1_COUNT1_OVERFLOW 0x200
2305 #define XSCALE1_CCOUNT_INT_EN   0x040
2306 #define XSCALE1_COUNT0_INT_EN   0x010
2307 #define XSCALE1_COUNT1_INT_EN   0x020
2308 #define XSCALE1_COUNT0_EVT_SHFT 12
2309 #define XSCALE1_COUNT0_EVT_MASK (0xff << XSCALE1_COUNT0_EVT_SHFT)
2310 #define XSCALE1_COUNT1_EVT_SHFT 20
2311 #define XSCALE1_COUNT1_EVT_MASK (0xff << XSCALE1_COUNT1_EVT_SHFT)
2312
2313 static inline u32
2314 xscale1pmu_read_pmnc(void)
2315 {
2316         u32 val;
2317         asm volatile("mrc p14, 0, %0, c0, c0, 0" : "=r" (val));
2318         return val;
2319 }
2320
2321 static inline void
2322 xscale1pmu_write_pmnc(u32 val)
2323 {
2324         /* upper 4bits and 7, 11 are write-as-0 */
2325         val &= 0xffff77f;
2326         asm volatile("mcr p14, 0, %0, c0, c0, 0" : : "r" (val));
2327 }
2328
2329 static inline int
2330 xscale1_pmnc_counter_has_overflowed(unsigned long pmnc,
2331                                         enum xscale_counters counter)
2332 {
2333         int ret = 0;
2334
2335         switch (counter) {
2336         case XSCALE_CYCLE_COUNTER:
2337                 ret = pmnc & XSCALE1_CCOUNT_OVERFLOW;
2338                 break;
2339         case XSCALE_COUNTER0:
2340                 ret = pmnc & XSCALE1_COUNT0_OVERFLOW;
2341                 break;
2342         case XSCALE_COUNTER1:
2343                 ret = pmnc & XSCALE1_COUNT1_OVERFLOW;
2344                 break;
2345         default:
2346                 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
2347         }
2348
2349         return ret;
2350 }
2351
2352 static irqreturn_t
2353 xscale1pmu_handle_irq(int irq_num, void *dev)
2354 {
2355         unsigned long pmnc;
2356         struct perf_sample_data data;
2357         struct cpu_hw_events *cpuc;
2358         struct pt_regs *regs;
2359         int idx;
2360
2361         /*
2362          * NOTE: there's an A stepping erratum that states if an overflow
2363          *       bit already exists and another occurs, the previous
2364          *       Overflow bit gets cleared. There's no workaround.
2365          *       Fixed in B stepping or later.
2366          */
2367         pmnc = xscale1pmu_read_pmnc();
2368
2369         /*
2370          * Write the value back to clear the overflow flags. Overflow
2371          * flags remain in pmnc for use below. We also disable the PMU
2372          * while we process the interrupt.
2373          */
2374         xscale1pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE);
2375
2376         if (!(pmnc & XSCALE1_OVERFLOWED_MASK))
2377                 return IRQ_NONE;
2378
2379         regs = get_irq_regs();
2380
2381         perf_sample_data_init(&data, 0);
2382
2383         cpuc = &__get_cpu_var(cpu_hw_events);
2384         for (idx = 0; idx <= armpmu->num_events; ++idx) {
2385                 struct perf_event *event = cpuc->events[idx];
2386                 struct hw_perf_event *hwc;
2387
2388                 if (!test_bit(idx, cpuc->active_mask))
2389                         continue;
2390
2391                 if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx))
2392                         continue;
2393
2394                 hwc = &event->hw;
2395                 armpmu_event_update(event, hwc, idx);
2396                 data.period = event->hw.last_period;
2397                 if (!armpmu_event_set_period(event, hwc, idx))
2398                         continue;
2399
2400                 if (perf_event_overflow(event, 0, &data, regs))
2401                         armpmu->disable(hwc, idx);
2402         }
2403
2404         perf_event_do_pending();
2405
2406         /*
2407          * Re-enable the PMU.
2408          */
2409         pmnc = xscale1pmu_read_pmnc() | XSCALE_PMU_ENABLE;
2410         xscale1pmu_write_pmnc(pmnc);
2411
2412         return IRQ_HANDLED;
2413 }
2414
2415 static void
2416 xscale1pmu_enable_event(struct hw_perf_event *hwc, int idx)
2417 {
2418         unsigned long val, mask, evt, flags;
2419
2420         switch (idx) {
2421         case XSCALE_CYCLE_COUNTER:
2422                 mask = 0;
2423                 evt = XSCALE1_CCOUNT_INT_EN;
2424                 break;
2425         case XSCALE_COUNTER0:
2426                 mask = XSCALE1_COUNT0_EVT_MASK;
2427                 evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) |
2428                         XSCALE1_COUNT0_INT_EN;
2429                 break;
2430         case XSCALE_COUNTER1:
2431                 mask = XSCALE1_COUNT1_EVT_MASK;
2432                 evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) |
2433                         XSCALE1_COUNT1_INT_EN;
2434                 break;
2435         default:
2436                 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
2437                 return;
2438         }
2439
2440         spin_lock_irqsave(&pmu_lock, flags);
2441         val = xscale1pmu_read_pmnc();
2442         val &= ~mask;
2443         val |= evt;
2444         xscale1pmu_write_pmnc(val);
2445         spin_unlock_irqrestore(&pmu_lock, flags);
2446 }
2447
2448 static void
2449 xscale1pmu_disable_event(struct hw_perf_event *hwc, int idx)
2450 {
2451         unsigned long val, mask, evt, flags;
2452
2453         switch (idx) {
2454         case XSCALE_CYCLE_COUNTER:
2455                 mask = XSCALE1_CCOUNT_INT_EN;
2456                 evt = 0;
2457                 break;
2458         case XSCALE_COUNTER0:
2459                 mask = XSCALE1_COUNT0_INT_EN | XSCALE1_COUNT0_EVT_MASK;
2460                 evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT0_EVT_SHFT;
2461                 break;
2462         case XSCALE_COUNTER1:
2463                 mask = XSCALE1_COUNT1_INT_EN | XSCALE1_COUNT1_EVT_MASK;
2464                 evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT1_EVT_SHFT;
2465                 break;
2466         default:
2467                 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
2468                 return;
2469         }
2470
2471         spin_lock_irqsave(&pmu_lock, flags);
2472         val = xscale1pmu_read_pmnc();
2473         val &= ~mask;
2474         val |= evt;
2475         xscale1pmu_write_pmnc(val);
2476         spin_unlock_irqrestore(&pmu_lock, flags);
2477 }
2478
2479 static int
2480 xscale1pmu_get_event_idx(struct cpu_hw_events *cpuc,
2481                         struct hw_perf_event *event)
2482 {
2483         if (XSCALE_PERFCTR_CCNT == event->config_base) {
2484                 if (test_and_set_bit(XSCALE_CYCLE_COUNTER, cpuc->used_mask))
2485                         return -EAGAIN;
2486
2487                 return XSCALE_CYCLE_COUNTER;
2488         } else {
2489                 if (!test_and_set_bit(XSCALE_COUNTER1, cpuc->used_mask)) {
2490                         return XSCALE_COUNTER1;
2491                 }
2492
2493                 if (!test_and_set_bit(XSCALE_COUNTER0, cpuc->used_mask)) {
2494                         return XSCALE_COUNTER0;
2495                 }
2496
2497                 return -EAGAIN;
2498         }
2499 }
2500
2501 static void
2502 xscale1pmu_start(void)
2503 {
2504         unsigned long flags, val;
2505
2506         spin_lock_irqsave(&pmu_lock, flags);
2507         val = xscale1pmu_read_pmnc();
2508         val |= XSCALE_PMU_ENABLE;
2509         xscale1pmu_write_pmnc(val);
2510         spin_unlock_irqrestore(&pmu_lock, flags);
2511 }
2512
2513 static void
2514 xscale1pmu_stop(void)
2515 {
2516         unsigned long flags, val;
2517
2518         spin_lock_irqsave(&pmu_lock, flags);
2519         val = xscale1pmu_read_pmnc();
2520         val &= ~XSCALE_PMU_ENABLE;
2521         xscale1pmu_write_pmnc(val);
2522         spin_unlock_irqrestore(&pmu_lock, flags);
2523 }
2524
2525 static inline u32
2526 xscale1pmu_read_counter(int counter)
2527 {
2528         u32 val = 0;
2529
2530         switch (counter) {
2531         case XSCALE_CYCLE_COUNTER:
2532                 asm volatile("mrc p14, 0, %0, c1, c0, 0" : "=r" (val));
2533                 break;
2534         case XSCALE_COUNTER0:
2535                 asm volatile("mrc p14, 0, %0, c2, c0, 0" : "=r" (val));
2536                 break;
2537         case XSCALE_COUNTER1:
2538                 asm volatile("mrc p14, 0, %0, c3, c0, 0" : "=r" (val));
2539                 break;
2540         }
2541
2542         return val;
2543 }
2544
2545 static inline void
2546 xscale1pmu_write_counter(int counter, u32 val)
2547 {
2548         switch (counter) {
2549         case XSCALE_CYCLE_COUNTER:
2550                 asm volatile("mcr p14, 0, %0, c1, c0, 0" : : "r" (val));
2551                 break;
2552         case XSCALE_COUNTER0:
2553                 asm volatile("mcr p14, 0, %0, c2, c0, 0" : : "r" (val));
2554                 break;
2555         case XSCALE_COUNTER1:
2556                 asm volatile("mcr p14, 0, %0, c3, c0, 0" : : "r" (val));
2557                 break;
2558         }
2559 }
2560
2561 static const struct arm_pmu xscale1pmu = {
2562         .id             = ARM_PERF_PMU_ID_XSCALE1,
2563         .handle_irq     = xscale1pmu_handle_irq,
2564         .enable         = xscale1pmu_enable_event,
2565         .disable        = xscale1pmu_disable_event,
2566         .event_map      = xscalepmu_event_map,
2567         .raw_event      = xscalepmu_raw_event,
2568         .read_counter   = xscale1pmu_read_counter,
2569         .write_counter  = xscale1pmu_write_counter,
2570         .get_event_idx  = xscale1pmu_get_event_idx,
2571         .start          = xscale1pmu_start,
2572         .stop           = xscale1pmu_stop,
2573         .num_events     = 3,
2574         .max_period     = (1LLU << 32) - 1,
2575 };
2576
2577 #define XSCALE2_OVERFLOWED_MASK 0x01f
2578 #define XSCALE2_CCOUNT_OVERFLOW 0x001
2579 #define XSCALE2_COUNT0_OVERFLOW 0x002
2580 #define XSCALE2_COUNT1_OVERFLOW 0x004
2581 #define XSCALE2_COUNT2_OVERFLOW 0x008
2582 #define XSCALE2_COUNT3_OVERFLOW 0x010
2583 #define XSCALE2_CCOUNT_INT_EN   0x001
2584 #define XSCALE2_COUNT0_INT_EN   0x002
2585 #define XSCALE2_COUNT1_INT_EN   0x004
2586 #define XSCALE2_COUNT2_INT_EN   0x008
2587 #define XSCALE2_COUNT3_INT_EN   0x010
2588 #define XSCALE2_COUNT0_EVT_SHFT 0
2589 #define XSCALE2_COUNT0_EVT_MASK (0xff << XSCALE2_COUNT0_EVT_SHFT)
2590 #define XSCALE2_COUNT1_EVT_SHFT 8
2591 #define XSCALE2_COUNT1_EVT_MASK (0xff << XSCALE2_COUNT1_EVT_SHFT)
2592 #define XSCALE2_COUNT2_EVT_SHFT 16
2593 #define XSCALE2_COUNT2_EVT_MASK (0xff << XSCALE2_COUNT2_EVT_SHFT)
2594 #define XSCALE2_COUNT3_EVT_SHFT 24
2595 #define XSCALE2_COUNT3_EVT_MASK (0xff << XSCALE2_COUNT3_EVT_SHFT)
2596
2597 static inline u32
2598 xscale2pmu_read_pmnc(void)
2599 {
2600         u32 val;
2601         asm volatile("mrc p14, 0, %0, c0, c1, 0" : "=r" (val));
2602         /* bits 1-2 and 4-23 are read-unpredictable */
2603         return val & 0xff000009;
2604 }
2605
2606 static inline void
2607 xscale2pmu_write_pmnc(u32 val)
2608 {
2609         /* bits 4-23 are write-as-0, 24-31 are write ignored */
2610         val &= 0xf;
2611         asm volatile("mcr p14, 0, %0, c0, c1, 0" : : "r" (val));
2612 }
2613
2614 static inline u32
2615 xscale2pmu_read_overflow_flags(void)
2616 {
2617         u32 val;
2618         asm volatile("mrc p14, 0, %0, c5, c1, 0" : "=r" (val));
2619         return val;
2620 }
2621
2622 static inline void
2623 xscale2pmu_write_overflow_flags(u32 val)
2624 {
2625         asm volatile("mcr p14, 0, %0, c5, c1, 0" : : "r" (val));
2626 }
2627
2628 static inline u32
2629 xscale2pmu_read_event_select(void)
2630 {
2631         u32 val;
2632         asm volatile("mrc p14, 0, %0, c8, c1, 0" : "=r" (val));
2633         return val;
2634 }
2635
2636 static inline void
2637 xscale2pmu_write_event_select(u32 val)
2638 {
2639         asm volatile("mcr p14, 0, %0, c8, c1, 0" : : "r"(val));
2640 }
2641
2642 static inline u32
2643 xscale2pmu_read_int_enable(void)
2644 {
2645         u32 val;
2646         asm volatile("mrc p14, 0, %0, c4, c1, 0" : "=r" (val));
2647         return val;
2648 }
2649
2650 static void
2651 xscale2pmu_write_int_enable(u32 val)
2652 {
2653         asm volatile("mcr p14, 0, %0, c4, c1, 0" : : "r" (val));
2654 }
2655
2656 static inline int
2657 xscale2_pmnc_counter_has_overflowed(unsigned long of_flags,
2658                                         enum xscale_counters counter)
2659 {
2660         int ret = 0;
2661
2662         switch (counter) {
2663         case XSCALE_CYCLE_COUNTER:
2664                 ret = of_flags & XSCALE2_CCOUNT_OVERFLOW;
2665                 break;
2666         case XSCALE_COUNTER0:
2667                 ret = of_flags & XSCALE2_COUNT0_OVERFLOW;
2668                 break;
2669         case XSCALE_COUNTER1:
2670                 ret = of_flags & XSCALE2_COUNT1_OVERFLOW;
2671                 break;
2672         case XSCALE_COUNTER2:
2673                 ret = of_flags & XSCALE2_COUNT2_OVERFLOW;
2674                 break;
2675         case XSCALE_COUNTER3:
2676                 ret = of_flags & XSCALE2_COUNT3_OVERFLOW;
2677                 break;
2678         default:
2679                 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
2680         }
2681
2682         return ret;
2683 }
2684
2685 static irqreturn_t
2686 xscale2pmu_handle_irq(int irq_num, void *dev)
2687 {
2688         unsigned long pmnc, of_flags;
2689         struct perf_sample_data data;
2690         struct cpu_hw_events *cpuc;
2691         struct pt_regs *regs;
2692         int idx;
2693
2694         /* Disable the PMU. */
2695         pmnc = xscale2pmu_read_pmnc();
2696         xscale2pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE);
2697
2698         /* Check the overflow flag register. */
2699         of_flags = xscale2pmu_read_overflow_flags();
2700         if (!(of_flags & XSCALE2_OVERFLOWED_MASK))
2701                 return IRQ_NONE;
2702
2703         /* Clear the overflow bits. */
2704         xscale2pmu_write_overflow_flags(of_flags);
2705
2706         regs = get_irq_regs();
2707
2708         perf_sample_data_init(&data, 0);
2709
2710         cpuc = &__get_cpu_var(cpu_hw_events);
2711         for (idx = 0; idx <= armpmu->num_events; ++idx) {
2712                 struct perf_event *event = cpuc->events[idx];
2713                 struct hw_perf_event *hwc;
2714
2715                 if (!test_bit(idx, cpuc->active_mask))
2716                         continue;
2717
2718                 if (!xscale2_pmnc_counter_has_overflowed(pmnc, idx))
2719                         continue;
2720
2721                 hwc = &event->hw;
2722                 armpmu_event_update(event, hwc, idx);
2723                 data.period = event->hw.last_period;
2724                 if (!armpmu_event_set_period(event, hwc, idx))
2725                         continue;
2726
2727                 if (perf_event_overflow(event, 0, &data, regs))
2728                         armpmu->disable(hwc, idx);
2729         }
2730
2731         perf_event_do_pending();
2732
2733         /*
2734          * Re-enable the PMU.
2735          */
2736         pmnc = xscale2pmu_read_pmnc() | XSCALE_PMU_ENABLE;
2737         xscale2pmu_write_pmnc(pmnc);
2738
2739         return IRQ_HANDLED;
2740 }
2741
2742 static void
2743 xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx)
2744 {
2745         unsigned long flags, ien, evtsel;
2746
2747         ien = xscale2pmu_read_int_enable();
2748         evtsel = xscale2pmu_read_event_select();
2749
2750         switch (idx) {
2751         case XSCALE_CYCLE_COUNTER:
2752                 ien |= XSCALE2_CCOUNT_INT_EN;
2753                 break;
2754         case XSCALE_COUNTER0:
2755                 ien |= XSCALE2_COUNT0_INT_EN;
2756                 evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
2757                 evtsel |= hwc->config_base << XSCALE2_COUNT0_EVT_SHFT;
2758                 break;
2759         case XSCALE_COUNTER1:
2760                 ien |= XSCALE2_COUNT1_INT_EN;
2761                 evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
2762                 evtsel |= hwc->config_base << XSCALE2_COUNT1_EVT_SHFT;
2763                 break;
2764         case XSCALE_COUNTER2:
2765                 ien |= XSCALE2_COUNT2_INT_EN;
2766                 evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
2767                 evtsel |= hwc->config_base << XSCALE2_COUNT2_EVT_SHFT;
2768                 break;
2769         case XSCALE_COUNTER3:
2770                 ien |= XSCALE2_COUNT3_INT_EN;
2771                 evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
2772                 evtsel |= hwc->config_base << XSCALE2_COUNT3_EVT_SHFT;
2773                 break;
2774         default:
2775                 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
2776                 return;
2777         }
2778
2779         spin_lock_irqsave(&pmu_lock, flags);
2780         xscale2pmu_write_event_select(evtsel);
2781         xscale2pmu_write_int_enable(ien);
2782         spin_unlock_irqrestore(&pmu_lock, flags);
2783 }
2784
2785 static void
2786 xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
2787 {
2788         unsigned long flags, ien, evtsel;
2789
2790         ien = xscale2pmu_read_int_enable();
2791         evtsel = xscale2pmu_read_event_select();
2792
2793         switch (idx) {
2794         case XSCALE_CYCLE_COUNTER:
2795                 ien &= ~XSCALE2_CCOUNT_INT_EN;
2796                 break;
2797         case XSCALE_COUNTER0:
2798                 ien &= ~XSCALE2_COUNT0_INT_EN;
2799                 evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
2800                 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT0_EVT_SHFT;
2801                 break;
2802         case XSCALE_COUNTER1:
2803                 ien &= ~XSCALE2_COUNT1_INT_EN;
2804                 evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
2805                 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT1_EVT_SHFT;
2806                 break;
2807         case XSCALE_COUNTER2:
2808                 ien &= ~XSCALE2_COUNT2_INT_EN;
2809                 evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
2810                 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT2_EVT_SHFT;
2811                 break;
2812         case XSCALE_COUNTER3:
2813                 ien &= ~XSCALE2_COUNT3_INT_EN;
2814                 evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
2815                 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT3_EVT_SHFT;
2816                 break;
2817         default:
2818                 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
2819                 return;
2820         }
2821
2822         spin_lock_irqsave(&pmu_lock, flags);
2823         xscale2pmu_write_event_select(evtsel);
2824         xscale2pmu_write_int_enable(ien);
2825         spin_unlock_irqrestore(&pmu_lock, flags);
2826 }
2827
2828 static int
2829 xscale2pmu_get_event_idx(struct cpu_hw_events *cpuc,
2830                         struct hw_perf_event *event)
2831 {
2832         int idx = xscale1pmu_get_event_idx(cpuc, event);
2833         if (idx >= 0)
2834                 goto out;
2835
2836         if (!test_and_set_bit(XSCALE_COUNTER3, cpuc->used_mask))
2837                 idx = XSCALE_COUNTER3;
2838         else if (!test_and_set_bit(XSCALE_COUNTER2, cpuc->used_mask))
2839                 idx = XSCALE_COUNTER2;
2840 out:
2841         return idx;
2842 }
2843
2844 static void
2845 xscale2pmu_start(void)
2846 {
2847         unsigned long flags, val;
2848
2849         spin_lock_irqsave(&pmu_lock, flags);
2850         val = xscale2pmu_read_pmnc() & ~XSCALE_PMU_CNT64;
2851         val |= XSCALE_PMU_ENABLE;
2852         xscale2pmu_write_pmnc(val);
2853         spin_unlock_irqrestore(&pmu_lock, flags);
2854 }
2855
2856 static void
2857 xscale2pmu_stop(void)
2858 {
2859         unsigned long flags, val;
2860
2861         spin_lock_irqsave(&pmu_lock, flags);
2862         val = xscale2pmu_read_pmnc();
2863         val &= ~XSCALE_PMU_ENABLE;
2864         xscale2pmu_write_pmnc(val);
2865         spin_unlock_irqrestore(&pmu_lock, flags);
2866 }
2867
2868 static inline u32
2869 xscale2pmu_read_counter(int counter)
2870 {
2871         u32 val = 0;
2872
2873         switch (counter) {
2874         case XSCALE_CYCLE_COUNTER:
2875                 asm volatile("mrc p14, 0, %0, c1, c1, 0" : "=r" (val));
2876                 break;
2877         case XSCALE_COUNTER0:
2878                 asm volatile("mrc p14, 0, %0, c0, c2, 0" : "=r" (val));
2879                 break;
2880         case XSCALE_COUNTER1:
2881                 asm volatile("mrc p14, 0, %0, c1, c2, 0" : "=r" (val));
2882                 break;
2883         case XSCALE_COUNTER2:
2884                 asm volatile("mrc p14, 0, %0, c2, c2, 0" : "=r" (val));
2885                 break;
2886         case XSCALE_COUNTER3:
2887                 asm volatile("mrc p14, 0, %0, c3, c2, 0" : "=r" (val));
2888                 break;
2889         }
2890
2891         return val;
2892 }
2893
2894 static inline void
2895 xscale2pmu_write_counter(int counter, u32 val)
2896 {
2897         switch (counter) {
2898         case XSCALE_CYCLE_COUNTER:
2899                 asm volatile("mcr p14, 0, %0, c1, c1, 0" : : "r" (val));
2900                 break;
2901         case XSCALE_COUNTER0:
2902                 asm volatile("mcr p14, 0, %0, c0, c2, 0" : : "r" (val));
2903                 break;
2904         case XSCALE_COUNTER1:
2905                 asm volatile("mcr p14, 0, %0, c1, c2, 0" : : "r" (val));
2906                 break;
2907         case XSCALE_COUNTER2:
2908                 asm volatile("mcr p14, 0, %0, c2, c2, 0" : : "r" (val));
2909                 break;
2910         case XSCALE_COUNTER3:
2911                 asm volatile("mcr p14, 0, %0, c3, c2, 0" : : "r" (val));
2912                 break;
2913         }
2914 }
2915
2916 static const struct arm_pmu xscale2pmu = {
2917         .id             = ARM_PERF_PMU_ID_XSCALE2,
2918         .handle_irq     = xscale2pmu_handle_irq,
2919         .enable         = xscale2pmu_enable_event,
2920         .disable        = xscale2pmu_disable_event,
2921         .event_map      = xscalepmu_event_map,
2922         .raw_event      = xscalepmu_raw_event,
2923         .read_counter   = xscale2pmu_read_counter,
2924         .write_counter  = xscale2pmu_write_counter,
2925         .get_event_idx  = xscale2pmu_get_event_idx,
2926         .start          = xscale2pmu_start,
2927         .stop           = xscale2pmu_stop,
2928         .num_events     = 5,
2929         .max_period     = (1LLU << 32) - 1,
2930 };
2931
2932 static int __init
2933 init_hw_perf_events(void)
2934 {
2935         unsigned long cpuid = read_cpuid_id();
2936         unsigned long implementor = (cpuid & 0xFF000000) >> 24;
2937         unsigned long part_number = (cpuid & 0xFFF0);
2938
2939         /* ARM Ltd CPUs. */
2940         if (0x41 == implementor) {
2941                 switch (part_number) {
2942                 case 0xB360:    /* ARM1136 */
2943                 case 0xB560:    /* ARM1156 */
2944                 case 0xB760:    /* ARM1176 */
2945                         armpmu = &armv6pmu;
2946                         memcpy(armpmu_perf_cache_map, armv6_perf_cache_map,
2947                                         sizeof(armv6_perf_cache_map));
2948                         perf_max_events = armv6pmu.num_events;
2949                         break;
2950                 case 0xB020:    /* ARM11mpcore */
2951                         armpmu = &armv6mpcore_pmu;
2952                         memcpy(armpmu_perf_cache_map,
2953                                armv6mpcore_perf_cache_map,
2954                                sizeof(armv6mpcore_perf_cache_map));
2955                         perf_max_events = armv6mpcore_pmu.num_events;
2956                         break;
2957                 case 0xC080:    /* Cortex-A8 */
2958                         armv7pmu.id = ARM_PERF_PMU_ID_CA8;
2959                         memcpy(armpmu_perf_cache_map, armv7_a8_perf_cache_map,
2960                                 sizeof(armv7_a8_perf_cache_map));
2961                         armv7pmu.event_map = armv7_a8_pmu_event_map;
2962                         armpmu = &armv7pmu;
2963
2964                         /* Reset PMNC and read the nb of CNTx counters
2965                             supported */
2966                         armv7pmu.num_events = armv7_reset_read_pmnc();
2967                         perf_max_events = armv7pmu.num_events;
2968                         break;
2969                 case 0xC090:    /* Cortex-A9 */
2970                         armv7pmu.id = ARM_PERF_PMU_ID_CA9;
2971                         memcpy(armpmu_perf_cache_map, armv7_a9_perf_cache_map,
2972                                 sizeof(armv7_a9_perf_cache_map));
2973                         armv7pmu.event_map = armv7_a9_pmu_event_map;
2974                         armpmu = &armv7pmu;
2975
2976                         /* Reset PMNC and read the nb of CNTx counters
2977                             supported */
2978                         armv7pmu.num_events = armv7_reset_read_pmnc();
2979                         perf_max_events = armv7pmu.num_events;
2980                         break;
2981                 }
2982         /* Intel CPUs [xscale]. */
2983         } else if (0x69 == implementor) {
2984                 part_number = (cpuid >> 13) & 0x7;
2985                 switch (part_number) {
2986                 case 1:
2987                         armpmu = &xscale1pmu;
2988                         memcpy(armpmu_perf_cache_map, xscale_perf_cache_map,
2989                                         sizeof(xscale_perf_cache_map));
2990                         perf_max_events = xscale1pmu.num_events;
2991                         break;
2992                 case 2:
2993                         armpmu = &xscale2pmu;
2994                         memcpy(armpmu_perf_cache_map, xscale_perf_cache_map,
2995                                         sizeof(xscale_perf_cache_map));
2996                         perf_max_events = xscale2pmu.num_events;
2997                         break;
2998                 }
2999         }
3000
3001         if (armpmu) {
3002                 pr_info("enabled with %s PMU driver, %d counters available\n",
3003                                 arm_pmu_names[armpmu->id], armpmu->num_events);
3004         } else {
3005                 pr_info("no hardware support available\n");
3006                 perf_max_events = -1;
3007         }
3008
3009         perf_pmu_register(&pmu);
3010
3011         return 0;
3012 }
3013 arch_initcall(init_hw_perf_events);
3014
3015 /*
3016  * Callchain handling code.
3017  */
3018
3019 /*
3020  * The registers we're interested in are at the end of the variable
3021  * length saved register structure. The fp points at the end of this
3022  * structure so the address of this struct is:
3023  * (struct frame_tail *)(xxx->fp)-1
3024  *
3025  * This code has been adapted from the ARM OProfile support.
3026  */
3027 struct frame_tail {
3028         struct frame_tail   *fp;
3029         unsigned long       sp;
3030         unsigned long       lr;
3031 } __attribute__((packed));
3032
3033 /*
3034  * Get the return address for a single stackframe and return a pointer to the
3035  * next frame tail.
3036  */
3037 static struct frame_tail *
3038 user_backtrace(struct frame_tail *tail,
3039                struct perf_callchain_entry *entry)
3040 {
3041         struct frame_tail buftail;
3042
3043         /* Also check accessibility of one struct frame_tail beyond */
3044         if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
3045                 return NULL;
3046         if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
3047                 return NULL;
3048
3049         perf_callchain_store(entry, buftail.lr);
3050
3051         /*
3052          * Frame pointers should strictly progress back up the stack
3053          * (towards higher addresses).
3054          */
3055         if (tail >= buftail.fp)
3056                 return NULL;
3057
3058         return buftail.fp - 1;
3059 }
3060
3061 void
3062 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
3063 {
3064         struct frame_tail *tail;
3065
3066
3067         tail = (struct frame_tail *)regs->ARM_fp - 1;
3068
3069         while (tail && !((unsigned long)tail & 0x3))
3070                 tail = user_backtrace(tail, entry);
3071 }
3072
3073 /*
3074  * Gets called by walk_stackframe() for every stackframe. This will be called
3075  * whist unwinding the stackframe and is like a subroutine return so we use
3076  * the PC.
3077  */
3078 static int
3079 callchain_trace(struct stackframe *fr,
3080                 void *data)
3081 {
3082         struct perf_callchain_entry *entry = data;
3083         perf_callchain_store(entry, fr->pc);
3084         return 0;
3085 }
3086
3087 void
3088 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
3089 {
3090         struct stackframe fr;
3091
3092         fr.fp = regs->ARM_fp;
3093         fr.sp = regs->ARM_sp;
3094         fr.lr = regs->ARM_lr;
3095         fr.pc = regs->ARM_pc;
3096         walk_stackframe(&fr, callchain_trace, entry);
3097 }