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- add Cogent CSB1725 board support (along with RDStor, will be split later)
[mv-sheeva.git] / arch / arm / mach-mv78xx0 / include / mach / bridge-regs.h
1 /*
2  * arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
3  *
4  * This file is licensed under the terms of the GNU General Public
5  * License version 2.  This program is licensed "as is" without any
6  * warranty of any kind, whether express or implied.
7  */
8
9 #ifndef __ASM_ARCH_BRIDGE_REGS_H
10 #define __ASM_ARCH_BRIDGE_REGS_H
11
12 #include <mach/mv78xx0.h>
13
14 #define CPU_CONTROL             (BRIDGE_VIRT_BASE | 0x0104)
15 #define L2_WRITETHROUGH         0x00020000
16
17 #define RSTOUTn_MASK            (BRIDGE_VIRT_BASE | 0x0108)
18 #define WDT_RESET_OUT_EN        0x00000002
19 #define SOFT_RESET_OUT_EN       0x00000004
20
21 #define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
22 #define SOFT_RESET              0x00000001
23
24 #define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE | 0x0110)
25 #define BRIDGE_MASK             (BRIDGE_VIRT_BASE | 0x0114)
26 #define BRIDGE_INT_TIMER0       0x0002
27 #define BRIDGE_INT_TIMER1       0x0004
28 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
29 #define WDT_INT_REQ             0x0008
30
31 #define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
32 #define IRQ_CAUSE_ERR_OFF       0x0000
33 #define IRQ_CAUSE_LOW_OFF       0x0004
34 #define IRQ_CAUSE_HIGH_OFF      0x0008
35 #define IRQ_MASK_ERR_OFF        0x000c
36 #define IRQ_MASK_LOW_OFF        0x0010
37 #define IRQ_MASK_HIGH_OFF       0x0014
38
39 #define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0300)
40
41 #endif