arch/arm/mach-s5pv310/cpu.c

   1 /* linux/arch/arm/mach-s5pv310/cpu.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9 */
  10
  11 #include <linux/sched.h>
  12 #include <linux/sysdev.h>
  13
  14 #include <asm/mach/map.h>
  15 #include <asm/mach/irq.h>
  16
  17 #include <asm/proc-fns.h>
  18 #include <asm/hardware/cache-l2x0.h>
  19
  20 #include <plat/cpu.h>
  21 #include <plat/clock.h>
  22 #include <plat/s5pv310.h>
  23 #include <plat/sdhci.h>
  24
  25 #include <mach/regs-irq.h>
  26
  27 void __iomem *gic_cpu_base_addr;
  28
  29 extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
  30                          unsigned int irq_start);
  31 extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
  32
  33 /* Initial IO mappings */
  34 static struct map_desc s5pv310_iodesc[] __initdata = {
  35         {
  36                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
  37                 .pfn            = __phys_to_pfn(S5PV310_PA_SYSRAM),
  38                 .length         = SZ_4K,
  39                 .type           = MT_DEVICE,
  40         }, {
  41                 .virtual        = (unsigned long)S5P_VA_CMU,
  42                 .pfn            = __phys_to_pfn(S5PV310_PA_CMU),
  43                 .length         = SZ_128K,
  44                 .type           = MT_DEVICE,
  45         }, {
  46                 .virtual        = (unsigned long)S5P_VA_PMU,
  47                 .pfn            = __phys_to_pfn(S5PV310_PA_PMU),
  48                 .length         = SZ_64K,
  49                 .type           = MT_DEVICE,
  50         }, {
  51                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
  52                 .pfn            = __phys_to_pfn(S5PV310_PA_COMBINER),
  53                 .length         = SZ_4K,
  54                 .type           = MT_DEVICE,
  55         }, {
  56                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
  57                 .pfn            = __phys_to_pfn(S5PV310_PA_COREPERI),
  58                 .length         = SZ_8K,
  59                 .type           = MT_DEVICE,
  60         }, {
  61                 .virtual        = (unsigned long)S5P_VA_L2CC,
  62                 .pfn            = __phys_to_pfn(S5PV310_PA_L2CC),
  63                 .length         = SZ_4K,
  64                 .type           = MT_DEVICE,
  65         }, {
  66                 .virtual        = (unsigned long)S5P_VA_GPIO1,
  67                 .pfn            = __phys_to_pfn(S5PV310_PA_GPIO1),
  68                 .length         = SZ_4K,
  69                 .type           = MT_DEVICE,
  70         }, {
  71                 .virtual        = (unsigned long)S5P_VA_GPIO2,
  72                 .pfn            = __phys_to_pfn(S5PV310_PA_GPIO2),
  73                 .length         = SZ_4K,
  74                 .type           = MT_DEVICE,
  75         }, {
  76                 .virtual        = (unsigned long)S5P_VA_GPIO3,
  77                 .pfn            = __phys_to_pfn(S5PV310_PA_GPIO3),
  78                 .length         = SZ_256,
  79                 .type           = MT_DEVICE,
  80         }, {
  81                 .virtual        = (unsigned long)S5P_VA_DMC0,
  82                 .pfn            = __phys_to_pfn(S5PV310_PA_DMC0),
  83                 .length         = SZ_4K,
  84                 .type           = MT_DEVICE,
  85         }, {
  86                 .virtual        = (unsigned long)S3C_VA_UART,
  87                 .pfn            = __phys_to_pfn(S3C_PA_UART),
  88                 .length         = SZ_512K,
  89                 .type           = MT_DEVICE,
  90         }, {
  91                 .virtual        = (unsigned long)S5P_VA_SROMC,
  92                 .pfn            = __phys_to_pfn(S5PV310_PA_SROMC),
  93                 .length         = SZ_4K,
  94                 .type           = MT_DEVICE,
  95         },
  96 };
  97
  98 static void s5pv310_idle(void)
  99 {
 100         if (!need_resched())
 101                 cpu_do_idle();
 102
 103         local_irq_enable();
 104 }
 105
 106 /* s5pv310_map_io
 107  *
 108  * register the standard cpu IO areas
 109 */
 110 void __init s5pv310_map_io(void)
 111 {
 112         iotable_init(s5pv310_iodesc, ARRAY_SIZE(s5pv310_iodesc));
 113
 114         /* initialize device information early */
 115         s5pv310_default_sdhci0();
 116         s5pv310_default_sdhci1();
 117         s5pv310_default_sdhci2();
 118         s5pv310_default_sdhci3();
 119 }
 120
 121 void __init s5pv310_init_clocks(int xtal)
 122 {
 123         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 124
 125         s3c24xx_register_baseclocks(xtal);
 126         s5p_register_clocks(xtal);
 127         s5pv310_register_clocks();
 128         s5pv310_setup_clocks();
 129 }
 130
 131 void __init s5pv310_init_irq(void)
 132 {
 133         int irq;
 134
 135         gic_cpu_base_addr = S5P_VA_GIC_CPU;
 136         gic_dist_init(0, S5P_VA_GIC_DIST, IRQ_LOCALTIMER);
 137         gic_cpu_init(0, S5P_VA_GIC_CPU);
 138
 139         for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
 140
 141                 /*
 142                  * From SPI(0) to SPI(39) and SPI(51), SPI(53) are
 143                  * connected to the interrupt combiner. These irqs
 144                  * should be initialized to support cascade interrupt.
 145                  */
 146                 if ((irq >= 40) && !(irq == 51) && !(irq == 53))
 147                         continue;
 148
 149                 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
 150                                 COMBINER_IRQ(irq, 0));
 151                 combiner_cascade_irq(irq, IRQ_SPI(irq));
 152         }
 153
 154         /* The parameters of s5p_init_irq() are for VIC init.
 155          * Theses parameters should be NULL and 0 because S5PV310
 156          * uses GIC instead of VIC.
 157          */
 158         s5p_init_irq(NULL, 0);
 159 }
 160
 161 struct sysdev_class s5pv310_sysclass = {
 162         .name   = "s5pv310-core",
 163 };
 164
 165 static struct sys_device s5pv310_sysdev = {
 166         .cls    = &s5pv310_sysclass,
 167 };
 168
 169 static int __init s5pv310_core_init(void)
 170 {
 171         return sysdev_class_register(&s5pv310_sysclass);
 172 }
 173
 174 core_initcall(s5pv310_core_init);
 175
 176 #ifdef CONFIG_CACHE_L2X0
 177 static int __init s5pv310_l2x0_cache_init(void)
 178 {
 179         /* TAG, Data Latency Control: 2cycle */
 180         __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 181         __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 182
 183         /* L2X0 Prefetch Control */
 184         __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 185
 186         /* L2X0 Power Control */
 187         __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
 188                      S5P_VA_L2CC + L2X0_POWER_CTRL);
 189
 190         l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
 191
 192         return 0;
 193 }
 194
 195 early_initcall(s5pv310_l2x0_cache_init);
 196 #endif
 197
 198 int __init s5pv310_init(void)
 199 {
 200         printk(KERN_INFO "S5PV310: Initializing architecture\n");
 201
 202         /* set idle function */
 203         pm_idle = s5pv310_idle;
 204
 205         return sysdev_register(&s5pv310_sysdev);
 206 }