arch/m32r/platforms/m32700ut/setup.c

   1 /*
   2  *  linux/arch/m32r/platforms/m32700ut/setup.c
   3  *
   4  *  Setup routines for Renesas M32700UT Board
   5  *
   6  *  Copyright (c) 2002-2005  Hiroyuki Kondo, Hirokazu Takata,
   7  *                           Hitoshi Yamamoto, Takeo Takahashi
   8  *
   9  *  This file is subject to the terms and conditions of the GNU General
  10  *  Public License.  See the file "COPYING" in the main directory of this
  11  *  archive for more details.
  12  */
  13
  14 #include <linux/irq.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/platform_device.h>
  18
  19 #include <asm/system.h>
  20 #include <asm/m32r.h>
  21 #include <asm/io.h>
  22
  23 /*
  24  * M32700 Interrupt Control Unit (Level 1)
  25  */
  26 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
  27
  28 icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
  29
  30 static void disable_m32700ut_irq(unsigned int irq)
  31 {
  32         unsigned long port, data;
  33
  34         port = irq2port(irq);
  35         data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
  36         outl(data, port);
  37 }
  38
  39 static void enable_m32700ut_irq(unsigned int irq)
  40 {
  41         unsigned long port, data;
  42
  43         port = irq2port(irq);
  44         data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
  45         outl(data, port);
  46 }
  47
  48 static void mask_m32700ut(struct irq_data *data)
  49 {
  50         disable_m32700ut_irq(data->irq);
  51 }
  52
  53 static void unmask_m32700ut(struct irq_data *data)
  54 {
  55         enable_m32700ut_irq(data->irq);
  56 }
  57
  58 static void shutdown_m32700ut(struct irq_data *data)
  59 {
  60         unsigned long port;
  61
  62         port = irq2port(data->irq);
  63         outl(M32R_ICUCR_ILEVEL7, port);
  64 }
  65
  66 static struct irq_chip m32700ut_irq_type =
  67 {
  68         .name           = "M32700UT-IRQ",
  69         .irq_shutdown   = shutdown_m32700ut,
  70         .irq_mask       = mask_m32700ut,
  71         .irq_unmask     = unmask_m32700ut
  72 };
  73
  74 /*
  75  * Interrupt Control Unit of PLD on M32700UT (Level 2)
  76  */
  77 #define irq2pldirq(x)           ((x) - M32700UT_PLD_IRQ_BASE)
  78 #define pldirq2port(x)          (unsigned long)((int)PLD_ICUCR1 + \
  79                                  (((x) - 1) * sizeof(unsigned short)))
  80
  81 typedef struct {
  82         unsigned short icucr;  /* ICU Control Register */
  83 } pld_icu_data_t;
  84
  85 static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
  86
  87 static void disable_m32700ut_pld_irq(unsigned int irq)
  88 {
  89         unsigned long port, data;
  90         unsigned int pldirq;
  91
  92         pldirq = irq2pldirq(irq);
  93 //      disable_m32700ut_irq(M32R_IRQ_INT1);
  94         port = pldirq2port(pldirq);
  95         data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
  96         outw(data, port);
  97 }
  98
  99 static void enable_m32700ut_pld_irq(unsigned int irq)
 100 {
 101         unsigned long port, data;
 102         unsigned int pldirq;
 103
 104         pldirq = irq2pldirq(irq);
 105 //      enable_m32700ut_irq(M32R_IRQ_INT1);
 106         port = pldirq2port(pldirq);
 107         data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
 108         outw(data, port);
 109 }
 110
 111 static void mask_and_ack_m32700ut_pld(unsigned int irq)
 112 {
 113         disable_m32700ut_pld_irq(irq);
 114 //      mask_and_ack_m32700ut(M32R_IRQ_INT1);
 115 }
 116
 117 static void end_m32700ut_pld_irq(unsigned int irq)
 118 {
 119         enable_m32700ut_pld_irq(irq);
 120         enable_m32700ut_irq(M32R_IRQ_INT1);
 121 }
 122
 123 static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
 124 {
 125         enable_m32700ut_pld_irq(irq);
 126         return (0);
 127 }
 128
 129 static void shutdown_m32700ut_pld_irq(unsigned int irq)
 130 {
 131         unsigned long port;
 132         unsigned int pldirq;
 133
 134         pldirq = irq2pldirq(irq);
 135 //      shutdown_m32700ut_irq(M32R_IRQ_INT1);
 136         port = pldirq2port(pldirq);
 137         outw(PLD_ICUCR_ILEVEL7, port);
 138 }
 139
 140 static struct irq_chip m32700ut_pld_irq_type =
 141 {
 142         .name = "M32700UT-PLD-IRQ",
 143         .startup = startup_m32700ut_pld_irq,
 144         .shutdown = shutdown_m32700ut_pld_irq,
 145         .enable = enable_m32700ut_pld_irq,
 146         .disable = disable_m32700ut_pld_irq,
 147         .ack = mask_and_ack_m32700ut_pld,
 148         .end = end_m32700ut_pld_irq
 149 };
 150
 151 /*
 152  * Interrupt Control Unit of PLD on M32700UT-LAN (Level 2)
 153  */
 154 #define irq2lanpldirq(x)        ((x) - M32700UT_LAN_PLD_IRQ_BASE)
 155 #define lanpldirq2port(x)       (unsigned long)((int)M32700UT_LAN_ICUCR1 + \
 156                                  (((x) - 1) * sizeof(unsigned short)))
 157
 158 static pld_icu_data_t lanpld_icu_data[M32700UT_NUM_LAN_PLD_IRQ];
 159
 160 static void disable_m32700ut_lanpld_irq(unsigned int irq)
 161 {
 162         unsigned long port, data;
 163         unsigned int pldirq;
 164
 165         pldirq = irq2lanpldirq(irq);
 166         port = lanpldirq2port(pldirq);
 167         data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
 168         outw(data, port);
 169 }
 170
 171 static void enable_m32700ut_lanpld_irq(unsigned int irq)
 172 {
 173         unsigned long port, data;
 174         unsigned int pldirq;
 175
 176         pldirq = irq2lanpldirq(irq);
 177         port = lanpldirq2port(pldirq);
 178         data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
 179         outw(data, port);
 180 }
 181
 182 static void mask_and_ack_m32700ut_lanpld(unsigned int irq)
 183 {
 184         disable_m32700ut_lanpld_irq(irq);
 185 }
 186
 187 static void end_m32700ut_lanpld_irq(unsigned int irq)
 188 {
 189         enable_m32700ut_lanpld_irq(irq);
 190         enable_m32700ut_irq(M32R_IRQ_INT0);
 191 }
 192
 193 static unsigned int startup_m32700ut_lanpld_irq(unsigned int irq)
 194 {
 195         enable_m32700ut_lanpld_irq(irq);
 196         return (0);
 197 }
 198
 199 static void shutdown_m32700ut_lanpld_irq(unsigned int irq)
 200 {
 201         unsigned long port;
 202         unsigned int pldirq;
 203
 204         pldirq = irq2lanpldirq(irq);
 205         port = lanpldirq2port(pldirq);
 206         outw(PLD_ICUCR_ILEVEL7, port);
 207 }
 208
 209 static struct irq_chip m32700ut_lanpld_irq_type =
 210 {
 211         .name = "M32700UT-PLD-LAN-IRQ",
 212         .startup = startup_m32700ut_lanpld_irq,
 213         .shutdown = shutdown_m32700ut_lanpld_irq,
 214         .enable = enable_m32700ut_lanpld_irq,
 215         .disable = disable_m32700ut_lanpld_irq,
 216         .ack = mask_and_ack_m32700ut_lanpld,
 217         .end = end_m32700ut_lanpld_irq
 218 };
 219
 220 /*
 221  * Interrupt Control Unit of PLD on M32700UT-LCD (Level 2)
 222  */
 223 #define irq2lcdpldirq(x)        ((x) - M32700UT_LCD_PLD_IRQ_BASE)
 224 #define lcdpldirq2port(x)       (unsigned long)((int)M32700UT_LCD_ICUCR1 + \
 225                                  (((x) - 1) * sizeof(unsigned short)))
 226
 227 static pld_icu_data_t lcdpld_icu_data[M32700UT_NUM_LCD_PLD_IRQ];
 228
 229 static void disable_m32700ut_lcdpld_irq(unsigned int irq)
 230 {
 231         unsigned long port, data;
 232         unsigned int pldirq;
 233
 234         pldirq = irq2lcdpldirq(irq);
 235         port = lcdpldirq2port(pldirq);
 236         data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
 237         outw(data, port);
 238 }
 239
 240 static void enable_m32700ut_lcdpld_irq(unsigned int irq)
 241 {
 242         unsigned long port, data;
 243         unsigned int pldirq;
 244
 245         pldirq = irq2lcdpldirq(irq);
 246         port = lcdpldirq2port(pldirq);
 247         data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
 248         outw(data, port);
 249 }
 250
 251 static void mask_and_ack_m32700ut_lcdpld(unsigned int irq)
 252 {
 253         disable_m32700ut_lcdpld_irq(irq);
 254 }
 255
 256 static void end_m32700ut_lcdpld_irq(unsigned int irq)
 257 {
 258         enable_m32700ut_lcdpld_irq(irq);
 259         enable_m32700ut_irq(M32R_IRQ_INT2);
 260 }
 261
 262 static unsigned int startup_m32700ut_lcdpld_irq(unsigned int irq)
 263 {
 264         enable_m32700ut_lcdpld_irq(irq);
 265         return (0);
 266 }
 267
 268 static void shutdown_m32700ut_lcdpld_irq(unsigned int irq)
 269 {
 270         unsigned long port;
 271         unsigned int pldirq;
 272
 273         pldirq = irq2lcdpldirq(irq);
 274         port = lcdpldirq2port(pldirq);
 275         outw(PLD_ICUCR_ILEVEL7, port);
 276 }
 277
 278 static struct irq_chip m32700ut_lcdpld_irq_type =
 279 {
 280         .name = "M32700UT-PLD-LCD-IRQ",
 281         .startup = startup_m32700ut_lcdpld_irq,
 282         .shutdown = shutdown_m32700ut_lcdpld_irq,
 283         .enable = enable_m32700ut_lcdpld_irq,
 284         .disable = disable_m32700ut_lcdpld_irq,
 285         .ack = mask_and_ack_m32700ut_lcdpld,
 286         .end = end_m32700ut_lcdpld_irq
 287 };
 288
 289 void __init init_IRQ(void)
 290 {
 291 #if defined(CONFIG_SMC91X)
 292         /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
 293         set_irq_chip(M32700UT_LAN_IRQ_LAN, &m32700ut_lanpld_irq_type);
 294         lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;   /* "H" edge sense */
 295         disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
 296 #endif  /* CONFIG_SMC91X */
 297
 298         /* MFT2 : system timer */
 299         set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type,
 300                                  handle_level_irq);
 301         icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
 302         disable_m32700ut_irq(M32R_IRQ_MFT2);
 303
 304         /* SIO0 : receive */
 305         set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type,
 306                                  handle_level_irq);
 307         icu_data[M32R_IRQ_SIO0_R].icucr = 0;
 308         disable_m32700ut_irq(M32R_IRQ_SIO0_R);
 309
 310         /* SIO0 : send */
 311         set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type,
 312                                  handle_level_irq);
 313         icu_data[M32R_IRQ_SIO0_S].icucr = 0;
 314         disable_m32700ut_irq(M32R_IRQ_SIO0_S);
 315
 316         /* SIO1 : receive */
 317         set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type,
 318                                  handle_level_irq);
 319         icu_data[M32R_IRQ_SIO1_R].icucr = 0;
 320         disable_m32700ut_irq(M32R_IRQ_SIO1_R);
 321
 322         /* SIO1 : send */
 323         set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type,
 324                                  handle_level_irq);
 325         icu_data[M32R_IRQ_SIO1_S].icucr = 0;
 326         disable_m32700ut_irq(M32R_IRQ_SIO1_S);
 327
 328         /* DMA1 : */
 329         set_irq_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type,
 330                                  handle_level_irq);
 331         icu_data[M32R_IRQ_DMA1].icucr = 0;
 332         disable_m32700ut_irq(M32R_IRQ_DMA1);
 333
 334 #ifdef CONFIG_SERIAL_M32R_PLDSIO
 335         /* INT#1: SIO0 Receive on PLD */
 336         set_irq_chip(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type);
 337         pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
 338         disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
 339
 340         /* INT#1: SIO0 Send on PLD */
 341         set_irq_chip(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type);
 342         pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
 343         disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
 344 #endif  /* CONFIG_SERIAL_M32R_PLDSIO */
 345
 346         /* INT#1: CFC IREQ on PLD */
 347         set_irq_chip(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type);
 348         pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;       /* 'L' level sense */
 349         disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
 350
 351         /* INT#1: CFC Insert on PLD */
 352         set_irq_chip(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type);
 353         pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00;   /* 'L' edge sense */
 354         disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
 355
 356         /* INT#1: CFC Eject on PLD */
 357         set_irq_chip(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type);
 358         pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;    /* 'H' edge sense */
 359         disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
 360
 361         /*
 362          * INT0# is used for LAN, DIO
 363          * We enable it here.
 364          */
 365         icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
 366         enable_m32700ut_irq(M32R_IRQ_INT0);
 367
 368         /*
 369          * INT1# is used for UART, MMC, CF Controller in FPGA.
 370          * We enable it here.
 371          */
 372         icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
 373         enable_m32700ut_irq(M32R_IRQ_INT1);
 374
 375 #if defined(CONFIG_USB)
 376         outw(USBCR_OTGS, USBCR);        /* USBCR: non-OTG */
 377         set_irq_chip(M32700UT_LCD_IRQ_USB_INT1, &m32700ut_lcdpld_irq_type);
 378
 379         lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;      /* "L" level sense */
 380         disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
 381 #endif
 382         /*
 383          * INT2# is used for BAT, USB, AUDIO
 384          * We enable it here.
 385          */
 386         icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
 387         enable_m32700ut_irq(M32R_IRQ_INT2);
 388
 389 #if defined(CONFIG_VIDEO_M32R_AR)
 390         /*
 391          * INT3# is used for AR
 392          */
 393         set_irq_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type,
 394                                  handle_level_irq);
 395         icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
 396         disable_m32700ut_irq(M32R_IRQ_INT3);
 397 #endif  /* CONFIG_VIDEO_M32R_AR */
 398 }
 399
 400 #if defined(CONFIG_SMC91X)
 401
 402 #define LAN_IOSTART     0x300
 403 #define LAN_IOEND       0x320
 404 static struct resource smc91x_resources[] = {
 405         [0] = {
 406                 .start  = (LAN_IOSTART),
 407                 .end    = (LAN_IOEND),
 408                 .flags  = IORESOURCE_MEM,
 409         },
 410         [1] = {
 411                 .start  = M32700UT_LAN_IRQ_LAN,
 412                 .end    = M32700UT_LAN_IRQ_LAN,
 413                 .flags  = IORESOURCE_IRQ,
 414         }
 415 };
 416
 417 static struct platform_device smc91x_device = {
 418         .name           = "smc91x",
 419         .id             = 0,
 420         .num_resources  = ARRAY_SIZE(smc91x_resources),
 421         .resource       = smc91x_resources,
 422 };
 423 #endif
 424
 425 #if defined(CONFIG_FB_S1D13XXX)
 426
 427 #include <video/s1d13xxxfb.h>
 428 #include <asm/s1d13806.h>
 429
 430 static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
 431         .initregs               = s1d13xxxfb_initregs,
 432         .initregssize           = ARRAY_SIZE(s1d13xxxfb_initregs),
 433         .platform_init_video    = NULL,
 434 #ifdef CONFIG_PM
 435         .platform_suspend_video = NULL,
 436         .platform_resume_video  = NULL,
 437 #endif
 438 };
 439
 440 static struct resource s1d13xxxfb_resources[] = {
 441         [0] = {
 442                 .start  = 0x10600000UL,
 443                 .end    = 0x1073FFFFUL,
 444                 .flags  = IORESOURCE_MEM,
 445         },
 446         [1] = {
 447                 .start  = 0x10400000UL,
 448                 .end    = 0x104001FFUL,
 449                 .flags  = IORESOURCE_MEM,
 450         }
 451 };
 452
 453 static struct platform_device s1d13xxxfb_device = {
 454         .name           = S1D_DEVICENAME,
 455         .id             = 0,
 456         .dev            = {
 457                 .platform_data  = &s1d13xxxfb_data,
 458         },
 459         .num_resources  = ARRAY_SIZE(s1d13xxxfb_resources),
 460         .resource       = s1d13xxxfb_resources,
 461 };
 462 #endif
 463
 464 static int __init platform_init(void)
 465 {
 466 #if defined(CONFIG_SMC91X)
 467         platform_device_register(&smc91x_device);
 468 #endif
 469 #if defined(CONFIG_FB_S1D13XXX)
 470         platform_device_register(&s1d13xxxfb_device);
 471 #endif
 472         return 0;
 473 }
 474 arch_initcall(platform_init);