2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2004-2009 Cavium Networks
7 * Copyright (C) 2008 Wind River Systems
10 #include <linux/init.h>
11 #include <linux/irq.h>
12 #include <linux/i2c.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
17 #include <asm/octeon/octeon.h>
18 #include <asm/octeon/cvmx-rnm-defs.h>
20 static struct octeon_cf_data octeon_cf_data;
22 static int __init octeon_cf_device_init(void)
24 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
25 unsigned long base_ptr, region_base, region_size;
26 struct platform_device *pd;
27 struct resource cf_resources[3];
28 unsigned int num_resources;
32 /* Setup octeon-cf platform device if present. */
34 if (octeon_bootinfo->major_version == 1
35 && octeon_bootinfo->minor_version >= 1) {
36 if (octeon_bootinfo->compact_flash_common_base_addr)
38 octeon_bootinfo->compact_flash_common_base_addr;
40 base_ptr = 0x1d000800;
46 /* Find CS0 region. */
47 for (i = 0; i < 8; i++) {
48 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i));
49 region_base = mio_boot_reg_cfg.s.base << 16;
50 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
51 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
52 && base_ptr < region_base + region_size)
56 /* i and i + 1 are CS0 and CS1, both must be less than 8. */
59 octeon_cf_data.base_region = i;
60 octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width;
61 octeon_cf_data.base_region_bias = base_ptr - region_base;
62 memset(cf_resources, 0, sizeof(cf_resources));
64 cf_resources[num_resources].flags = IORESOURCE_MEM;
65 cf_resources[num_resources].start = region_base;
66 cf_resources[num_resources].end = region_base + region_size - 1;
70 if (!(base_ptr & 0xfffful)) {
72 * Boot loader signals availability of DMA (true_ide
73 * mode) by setting low order bits of base_ptr to
77 /* Asume that CS1 immediately follows. */
78 mio_boot_reg_cfg.u64 =
79 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1));
80 region_base = mio_boot_reg_cfg.s.base << 16;
81 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
82 if (!mio_boot_reg_cfg.s.en)
85 cf_resources[num_resources].flags = IORESOURCE_MEM;
86 cf_resources[num_resources].start = region_base;
87 cf_resources[num_resources].end = region_base + region_size - 1;
90 octeon_cf_data.dma_engine = 0;
91 cf_resources[num_resources].flags = IORESOURCE_IRQ;
92 cf_resources[num_resources].start = OCTEON_IRQ_BOOTDMA;
93 cf_resources[num_resources].end = OCTEON_IRQ_BOOTDMA;
96 octeon_cf_data.dma_engine = -1;
99 pd = platform_device_alloc("pata_octeon_cf", -1);
104 pd->dev.platform_data = &octeon_cf_data;
106 ret = platform_device_add_resources(pd, cf_resources, num_resources);
110 ret = platform_device_add(pd);
116 platform_device_put(pd);
120 device_initcall(octeon_cf_device_init);
122 /* Octeon Random Number Generator. */
123 static int __init octeon_rng_device_init(void)
125 struct platform_device *pd;
128 struct resource rng_resources[] = {
130 .flags = IORESOURCE_MEM,
131 .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
132 .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
134 .flags = IORESOURCE_MEM,
135 .start = cvmx_build_io_address(8, 0),
136 .end = cvmx_build_io_address(8, 0) + 0x7
140 pd = platform_device_alloc("octeon_rng", -1);
146 ret = platform_device_add_resources(pd, rng_resources,
147 ARRAY_SIZE(rng_resources));
151 ret = platform_device_add(pd);
157 platform_device_put(pd);
162 device_initcall(octeon_rng_device_init);
164 static struct i2c_board_info __initdata octeon_i2c_devices[] = {
166 I2C_BOARD_INFO("ds1337", 0x68),
170 static int __init octeon_i2c_devices_init(void)
172 return i2c_register_board_info(0, octeon_i2c_devices,
173 ARRAY_SIZE(octeon_i2c_devices));
175 arch_initcall(octeon_i2c_devices_init);
177 #define OCTEON_I2C_IO_BASE 0x1180000001000ull
178 #define OCTEON_I2C_IO_UNIT_OFFSET 0x200
180 static struct octeon_i2c_data octeon_i2c_data[2];
182 static int __init octeon_i2c_device_init(void)
184 struct platform_device *pd;
188 struct resource i2c_resources[] = {
190 .flags = IORESOURCE_MEM,
192 .flags = IORESOURCE_IRQ,
196 if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
201 for (port = 0; port < num_ports; port++) {
202 octeon_i2c_data[port].sys_freq = octeon_get_clock_rate();
203 /*FIXME: should be examined. At the moment is set for 100Khz */
204 octeon_i2c_data[port].i2c_freq = 100000;
206 pd = platform_device_alloc("i2c-octeon", port);
212 pd->dev.platform_data = octeon_i2c_data + port;
214 i2c_resources[0].start =
215 OCTEON_I2C_IO_BASE + (port * OCTEON_I2C_IO_UNIT_OFFSET);
216 i2c_resources[0].end = i2c_resources[0].start + 0x1f;
219 i2c_resources[1].start = OCTEON_IRQ_TWSI;
220 i2c_resources[1].end = OCTEON_IRQ_TWSI;
223 i2c_resources[1].start = OCTEON_IRQ_TWSI2;
224 i2c_resources[1].end = OCTEON_IRQ_TWSI2;
230 ret = platform_device_add_resources(pd,
232 ARRAY_SIZE(i2c_resources));
236 ret = platform_device_add(pd);
242 platform_device_put(pd);
246 device_initcall(octeon_i2c_device_init);
248 /* Octeon SMI/MDIO interface. */
249 static int __init octeon_mdiobus_device_init(void)
251 struct platform_device *pd;
254 if (octeon_is_simulation())
255 return 0; /* No mdio in the simulator. */
257 /* The bus number is the platform_device id. */
258 pd = platform_device_alloc("mdio-octeon", 0);
264 ret = platform_device_add(pd);
270 platform_device_put(pd);
276 device_initcall(octeon_mdiobus_device_init);
278 /* Octeon mgmt port Ethernet interface. */
279 static int __init octeon_mgmt_device_init(void)
281 struct platform_device *pd;
285 struct resource mgmt_port_resource = {
286 .flags = IORESOURCE_IRQ,
291 if (!OCTEON_IS_MODEL(OCTEON_CN56XX) && !OCTEON_IS_MODEL(OCTEON_CN52XX))
294 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
299 for (port = 0; port < num_ports; port++) {
300 pd = platform_device_alloc("octeon_mgmt", port);
305 /* No DMA restrictions */
306 pd->dev.coherent_dma_mask = DMA_BIT_MASK(64);
307 pd->dev.dma_mask = &pd->dev.coherent_dma_mask;
311 mgmt_port_resource.start = OCTEON_IRQ_MII0;
314 mgmt_port_resource.start = OCTEON_IRQ_MII1;
319 mgmt_port_resource.end = mgmt_port_resource.start;
321 ret = platform_device_add_resources(pd, &mgmt_port_resource, 1);
326 ret = platform_device_add(pd);
332 platform_device_put(pd);
338 device_initcall(octeon_mgmt_device_init);
340 MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
341 MODULE_LICENSE("GPL");
342 MODULE_DESCRIPTION("Platform driver for Octeon SOC");