arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/highmem.h>
  26 #include <linux/cpu.h>
  27 #include <linux/bitops.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/compat.h>
  33
  34 #if 0
  35 #undef wrmsrl
  36 #define wrmsrl(msr, val)                                        \
  37 do {                                                            \
  38         trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
  39                         (unsigned long)(val));                  \
  40         native_write_msr((msr), (u32)((u64)(val)),              \
  41                         (u32)((u64)(val) >> 32));               \
  42 } while (0)
  43 #endif
  44
  45 /*
  46  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
  47  */
  48 static unsigned long
  49 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
  50 {
  51         unsigned long offset, addr = (unsigned long)from;
  52         int type = in_nmi() ? KM_NMI : KM_IRQ0;
  53         unsigned long size, len = 0;
  54         struct page *page;
  55         void *map;
  56         int ret;
  57
  58         do {
  59                 ret = __get_user_pages_fast(addr, 1, 0, &page);
  60                 if (!ret)
  61                         break;
  62
  63                 offset = addr & (PAGE_SIZE - 1);
  64                 size = min(PAGE_SIZE - offset, n - len);
  65
  66                 map = kmap_atomic(page, type);
  67                 memcpy(to, map+offset, size);
  68                 kunmap_atomic(map, type);
  69                 put_page(page);
  70
  71                 len  += size;
  72                 to   += size;
  73                 addr += size;
  74
  75         } while (len < n);
  76
  77         return len;
  78 }
  79
  80 struct event_constraint {
  81         union {
  82                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  83                 u64             idxmsk64;
  84         };
  85         u64     code;
  86         u64     cmask;
  87         int     weight;
  88 };
  89
  90 struct amd_nb {
  91         int nb_id;  /* NorthBridge id */
  92         int refcnt; /* reference count */
  93         struct perf_event *owners[X86_PMC_IDX_MAX];
  94         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
  95 };
  96
  97 #define MAX_LBR_ENTRIES         16
  98
  99 struct cpu_hw_events {
 100         /*
 101          * Generic x86 PMC bits
 102          */
 103         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
 104         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 105         int                     enabled;
 106
 107         int                     n_events;
 108         int                     n_added;
 109         int                     n_txn;
 110         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
 111         u64                     tags[X86_PMC_IDX_MAX];
 112         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
 113
 114         unsigned int            group_flag;
 115
 116         /*
 117          * Intel DebugStore bits
 118          */
 119         struct debug_store      *ds;
 120         u64                     pebs_enabled;
 121
 122         /*
 123          * Intel LBR bits
 124          */
 125         int                             lbr_users;
 126         void                            *lbr_context;
 127         struct perf_branch_stack        lbr_stack;
 128         struct perf_branch_entry        lbr_entries[MAX_LBR_ENTRIES];
 129
 130         /*
 131          * AMD specific bits
 132          */
 133         struct amd_nb           *amd_nb;
 134 };
 135
 136 #define __EVENT_CONSTRAINT(c, n, m, w) {\
 137         { .idxmsk64 = (n) },            \
 138         .code = (c),                    \
 139         .cmask = (m),                   \
 140         .weight = (w),                  \
 141 }
 142
 143 #define EVENT_CONSTRAINT(c, n, m)       \
 144         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
 145
 146 /*
 147  * Constraint on the Event code.
 148  */
 149 #define INTEL_EVENT_CONSTRAINT(c, n)    \
 150         EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
 151
 152 /*
 153  * Constraint on the Event code + UMask + fixed-mask
 154  *
 155  * filter mask to validate fixed counter events.
 156  * the following filters disqualify for fixed counters:
 157  *  - inv
 158  *  - edge
 159  *  - cnt-mask
 160  *  The other filters are supported by fixed counters.
 161  *  The any-thread option is supported starting with v3.
 162  */
 163 #define FIXED_EVENT_CONSTRAINT(c, n)    \
 164         EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
 165
 166 /*
 167  * Constraint on the Event code + UMask
 168  */
 169 #define PEBS_EVENT_CONSTRAINT(c, n)     \
 170         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
 171
 172 #define EVENT_CONSTRAINT_END            \
 173         EVENT_CONSTRAINT(0, 0, 0)
 174
 175 #define for_each_event_constraint(e, c) \
 176         for ((e) = (c); (e)->weight; (e)++)
 177
 178 union perf_capabilities {
 179         struct {
 180                 u64     lbr_format    : 6;
 181                 u64     pebs_trap     : 1;
 182                 u64     pebs_arch_reg : 1;
 183                 u64     pebs_format   : 4;
 184                 u64     smm_freeze    : 1;
 185         };
 186         u64     capabilities;
 187 };
 188
 189 /*
 190  * struct x86_pmu - generic x86 pmu
 191  */
 192 struct x86_pmu {
 193         /*
 194          * Generic x86 PMC bits
 195          */
 196         const char      *name;
 197         int             version;
 198         int             (*handle_irq)(struct pt_regs *);
 199         void            (*disable_all)(void);
 200         void            (*enable_all)(int added);
 201         void            (*enable)(struct perf_event *);
 202         void            (*disable)(struct perf_event *);
 203         int             (*hw_config)(struct perf_event *event);
 204         int             (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
 205         unsigned        eventsel;
 206         unsigned        perfctr;
 207         u64             (*event_map)(int);
 208         int             max_events;
 209         int             num_counters;
 210         int             num_counters_fixed;
 211         int             cntval_bits;
 212         u64             cntval_mask;
 213         int             apic;
 214         u64             max_period;
 215         struct event_constraint *
 216                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
 217                                                  struct perf_event *event);
 218
 219         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
 220                                                  struct perf_event *event);
 221         struct event_constraint *event_constraints;
 222         void            (*quirks)(void);
 223         int             perfctr_second_write;
 224
 225         int             (*cpu_prepare)(int cpu);
 226         void            (*cpu_starting)(int cpu);
 227         void            (*cpu_dying)(int cpu);
 228         void            (*cpu_dead)(int cpu);
 229
 230         /*
 231          * Intel Arch Perfmon v2+
 232          */
 233         u64                     intel_ctrl;
 234         union perf_capabilities intel_cap;
 235
 236         /*
 237          * Intel DebugStore bits
 238          */
 239         int             bts, pebs;
 240         int             pebs_record_size;
 241         void            (*drain_pebs)(struct pt_regs *regs);
 242         struct event_constraint *pebs_constraints;
 243
 244         /*
 245          * Intel LBR
 246          */
 247         unsigned long   lbr_tos, lbr_from, lbr_to; /* MSR base regs       */
 248         int             lbr_nr;                    /* hardware stack size */
 249 };
 250
 251 static struct x86_pmu x86_pmu __read_mostly;
 252
 253 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
 254         .enabled = 1,
 255 };
 256
 257 static int x86_perf_event_set_period(struct perf_event *event);
 258
 259 /*
 260  * Generalized hw caching related hw_event table, filled
 261  * in on a per model basis. A value of 0 means
 262  * 'not supported', -1 means 'hw_event makes no sense on
 263  * this CPU', any other value means the raw hw_event
 264  * ID.
 265  */
 266
 267 #define C(x) PERF_COUNT_HW_CACHE_##x
 268
 269 static u64 __read_mostly hw_cache_event_ids
 270                                 [PERF_COUNT_HW_CACHE_MAX]
 271                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 272                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 273
 274 /*
 275  * Propagate event elapsed time into the generic event.
 276  * Can only be executed on the CPU where the event is active.
 277  * Returns the delta events processed.
 278  */
 279 static u64
 280 x86_perf_event_update(struct perf_event *event)
 281 {
 282         struct hw_perf_event *hwc = &event->hw;
 283         int shift = 64 - x86_pmu.cntval_bits;
 284         u64 prev_raw_count, new_raw_count;
 285         int idx = hwc->idx;
 286         s64 delta;
 287
 288         if (idx == X86_PMC_IDX_FIXED_BTS)
 289                 return 0;
 290
 291         /*
 292          * Careful: an NMI might modify the previous event value.
 293          *
 294          * Our tactic to handle this is to first atomically read and
 295          * exchange a new raw count - then add that new-prev delta
 296          * count to the generic event atomically:
 297          */
 298 again:
 299         prev_raw_count = local64_read(&hwc->prev_count);
 300         rdmsrl(hwc->event_base + idx, new_raw_count);
 301
 302         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 303                                         new_raw_count) != prev_raw_count)
 304                 goto again;
 305
 306         /*
 307          * Now we have the new raw value and have updated the prev
 308          * timestamp already. We can now calculate the elapsed delta
 309          * (event-)time and add that to the generic event.
 310          *
 311          * Careful, not all hw sign-extends above the physical width
 312          * of the count.
 313          */
 314         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 315         delta >>= shift;
 316
 317         local64_add(delta, &event->count);
 318         local64_sub(delta, &hwc->period_left);
 319
 320         return new_raw_count;
 321 }
 322
 323 static atomic_t active_events;
 324 static DEFINE_MUTEX(pmc_reserve_mutex);
 325
 326 #ifdef CONFIG_X86_LOCAL_APIC
 327
 328 static bool reserve_pmc_hardware(void)
 329 {
 330         int i;
 331
 332         if (nmi_watchdog == NMI_LOCAL_APIC)
 333                 disable_lapic_nmi_watchdog();
 334
 335         for (i = 0; i < x86_pmu.num_counters; i++) {
 336                 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
 337                         goto perfctr_fail;
 338         }
 339
 340         for (i = 0; i < x86_pmu.num_counters; i++) {
 341                 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
 342                         goto eventsel_fail;
 343         }
 344
 345         return true;
 346
 347 eventsel_fail:
 348         for (i--; i >= 0; i--)
 349                 release_evntsel_nmi(x86_pmu.eventsel + i);
 350
 351         i = x86_pmu.num_counters;
 352
 353 perfctr_fail:
 354         for (i--; i >= 0; i--)
 355                 release_perfctr_nmi(x86_pmu.perfctr + i);
 356
 357         if (nmi_watchdog == NMI_LOCAL_APIC)
 358                 enable_lapic_nmi_watchdog();
 359
 360         return false;
 361 }
 362
 363 static void release_pmc_hardware(void)
 364 {
 365         int i;
 366
 367         for (i = 0; i < x86_pmu.num_counters; i++) {
 368                 release_perfctr_nmi(x86_pmu.perfctr + i);
 369                 release_evntsel_nmi(x86_pmu.eventsel + i);
 370         }
 371
 372         if (nmi_watchdog == NMI_LOCAL_APIC)
 373                 enable_lapic_nmi_watchdog();
 374 }
 375
 376 #else
 377
 378 static bool reserve_pmc_hardware(void) { return true; }
 379 static void release_pmc_hardware(void) {}
 380
 381 #endif
 382
 383 static int reserve_ds_buffers(void);
 384 static void release_ds_buffers(void);
 385
 386 static void hw_perf_event_destroy(struct perf_event *event)
 387 {
 388         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 389                 release_pmc_hardware();
 390                 release_ds_buffers();
 391                 mutex_unlock(&pmc_reserve_mutex);
 392         }
 393 }
 394
 395 static inline int x86_pmu_initialized(void)
 396 {
 397         return x86_pmu.handle_irq != NULL;
 398 }
 399
 400 static inline int
 401 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
 402 {
 403         unsigned int cache_type, cache_op, cache_result;
 404         u64 config, val;
 405
 406         config = attr->config;
 407
 408         cache_type = (config >>  0) & 0xff;
 409         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 410                 return -EINVAL;
 411
 412         cache_op = (config >>  8) & 0xff;
 413         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 414                 return -EINVAL;
 415
 416         cache_result = (config >> 16) & 0xff;
 417         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 418                 return -EINVAL;
 419
 420         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 421
 422         if (val == 0)
 423                 return -ENOENT;
 424
 425         if (val == -1)
 426                 return -EINVAL;
 427
 428         hwc->config |= val;
 429
 430         return 0;
 431 }
 432
 433 static int x86_setup_perfctr(struct perf_event *event)
 434 {
 435         struct perf_event_attr *attr = &event->attr;
 436         struct hw_perf_event *hwc = &event->hw;
 437         u64 config;
 438
 439         if (!hwc->sample_period) {
 440                 hwc->sample_period = x86_pmu.max_period;
 441                 hwc->last_period = hwc->sample_period;
 442                 local64_set(&hwc->period_left, hwc->sample_period);
 443         } else {
 444                 /*
 445                  * If we have a PMU initialized but no APIC
 446                  * interrupts, we cannot sample hardware
 447                  * events (user-space has to fall back and
 448                  * sample via a hrtimer based software event):
 449                  */
 450                 if (!x86_pmu.apic)
 451                         return -EOPNOTSUPP;
 452         }
 453
 454         if (attr->type == PERF_TYPE_RAW)
 455                 return 0;
 456
 457         if (attr->type == PERF_TYPE_HW_CACHE)
 458                 return set_ext_hw_attr(hwc, attr);
 459
 460         if (attr->config >= x86_pmu.max_events)
 461                 return -EINVAL;
 462
 463         /*
 464          * The generic map:
 465          */
 466         config = x86_pmu.event_map(attr->config);
 467
 468         if (config == 0)
 469                 return -ENOENT;
 470
 471         if (config == -1LL)
 472                 return -EINVAL;
 473
 474         /*
 475          * Branch tracing:
 476          */
 477         if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
 478             (hwc->sample_period == 1)) {
 479                 /* BTS is not supported by this architecture. */
 480                 if (!x86_pmu.bts)
 481                         return -EOPNOTSUPP;
 482
 483                 /* BTS is currently only allowed for user-mode. */
 484                 if (!attr->exclude_kernel)
 485                         return -EOPNOTSUPP;
 486         }
 487
 488         hwc->config |= config;
 489
 490         return 0;
 491 }
 492
 493 static int x86_pmu_hw_config(struct perf_event *event)
 494 {
 495         if (event->attr.precise_ip) {
 496                 int precise = 0;
 497
 498                 /* Support for constant skid */
 499                 if (x86_pmu.pebs)
 500                         precise++;
 501
 502                 /* Support for IP fixup */
 503                 if (x86_pmu.lbr_nr)
 504                         precise++;
 505
 506                 if (event->attr.precise_ip > precise)
 507                         return -EOPNOTSUPP;
 508         }
 509
 510         /*
 511          * Generate PMC IRQs:
 512          * (keep 'enabled' bit clear for now)
 513          */
 514         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 515
 516         /*
 517          * Count user and OS events unless requested not to
 518          */
 519         if (!event->attr.exclude_user)
 520                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 521         if (!event->attr.exclude_kernel)
 522                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 523
 524         if (event->attr.type == PERF_TYPE_RAW)
 525                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 526
 527         return x86_setup_perfctr(event);
 528 }
 529
 530 /*
 531  * Setup the hardware configuration for a given attr_type
 532  */
 533 static int __x86_pmu_event_init(struct perf_event *event)
 534 {
 535         int err;
 536
 537         if (!x86_pmu_initialized())
 538                 return -ENODEV;
 539
 540         err = 0;
 541         if (!atomic_inc_not_zero(&active_events)) {
 542                 mutex_lock(&pmc_reserve_mutex);
 543                 if (atomic_read(&active_events) == 0) {
 544                         if (!reserve_pmc_hardware())
 545                                 err = -EBUSY;
 546                         else {
 547                                 err = reserve_ds_buffers();
 548                                 if (err)
 549                                         release_pmc_hardware();
 550                         }
 551                 }
 552                 if (!err)
 553                         atomic_inc(&active_events);
 554                 mutex_unlock(&pmc_reserve_mutex);
 555         }
 556         if (err)
 557                 return err;
 558
 559         event->destroy = hw_perf_event_destroy;
 560
 561         event->hw.idx = -1;
 562         event->hw.last_cpu = -1;
 563         event->hw.last_tag = ~0ULL;
 564
 565         return x86_pmu.hw_config(event);
 566 }
 567
 568 static void x86_pmu_disable_all(void)
 569 {
 570         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 571         int idx;
 572
 573         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 574                 u64 val;
 575
 576                 if (!test_bit(idx, cpuc->active_mask))
 577                         continue;
 578                 rdmsrl(x86_pmu.eventsel + idx, val);
 579                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 580                         continue;
 581                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 582                 wrmsrl(x86_pmu.eventsel + idx, val);
 583         }
 584 }
 585
 586 static void x86_pmu_disable(struct pmu *pmu)
 587 {
 588         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 589
 590         if (!x86_pmu_initialized())
 591                 return;
 592
 593         if (!cpuc->enabled)
 594                 return;
 595
 596         cpuc->n_added = 0;
 597         cpuc->enabled = 0;
 598         barrier();
 599
 600         x86_pmu.disable_all();
 601 }
 602
 603 static void x86_pmu_enable_all(int added)
 604 {
 605         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 606         int idx;
 607
 608         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 609                 struct perf_event *event = cpuc->events[idx];
 610                 u64 val;
 611
 612                 if (!test_bit(idx, cpuc->active_mask))
 613                         continue;
 614
 615                 val = event->hw.config;
 616                 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
 617                 wrmsrl(x86_pmu.eventsel + idx, val);
 618         }
 619 }
 620
 621 static struct pmu pmu;
 622
 623 static inline int is_x86_event(struct perf_event *event)
 624 {
 625         return event->pmu == &pmu;
 626 }
 627
 628 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 629 {
 630         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
 631         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 632         int i, j, w, wmax, num = 0;
 633         struct hw_perf_event *hwc;
 634
 635         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 636
 637         for (i = 0; i < n; i++) {
 638                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 639                 constraints[i] = c;
 640         }
 641
 642         /*
 643          * fastpath, try to reuse previous register
 644          */
 645         for (i = 0; i < n; i++) {
 646                 hwc = &cpuc->event_list[i]->hw;
 647                 c = constraints[i];
 648
 649                 /* never assigned */
 650                 if (hwc->idx == -1)
 651                         break;
 652
 653                 /* constraint still honored */
 654                 if (!test_bit(hwc->idx, c->idxmsk))
 655                         break;
 656
 657                 /* not already used */
 658                 if (test_bit(hwc->idx, used_mask))
 659                         break;
 660
 661                 __set_bit(hwc->idx, used_mask);
 662                 if (assign)
 663                         assign[i] = hwc->idx;
 664         }
 665         if (i == n)
 666                 goto done;
 667
 668         /*
 669          * begin slow path
 670          */
 671
 672         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 673
 674         /*
 675          * weight = number of possible counters
 676          *
 677          * 1    = most constrained, only works on one counter
 678          * wmax = least constrained, works on any counter
 679          *
 680          * assign events to counters starting with most
 681          * constrained events.
 682          */
 683         wmax = x86_pmu.num_counters;
 684
 685         /*
 686          * when fixed event counters are present,
 687          * wmax is incremented by 1 to account
 688          * for one more choice
 689          */
 690         if (x86_pmu.num_counters_fixed)
 691                 wmax++;
 692
 693         for (w = 1, num = n; num && w <= wmax; w++) {
 694                 /* for each event */
 695                 for (i = 0; num && i < n; i++) {
 696                         c = constraints[i];
 697                         hwc = &cpuc->event_list[i]->hw;
 698
 699                         if (c->weight != w)
 700                                 continue;
 701
 702                         for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
 703                                 if (!test_bit(j, used_mask))
 704                                         break;
 705                         }
 706
 707                         if (j == X86_PMC_IDX_MAX)
 708                                 break;
 709
 710                         __set_bit(j, used_mask);
 711
 712                         if (assign)
 713                                 assign[i] = j;
 714                         num--;
 715                 }
 716         }
 717 done:
 718         /*
 719          * scheduling failed or is just a simulation,
 720          * free resources if necessary
 721          */
 722         if (!assign || num) {
 723                 for (i = 0; i < n; i++) {
 724                         if (x86_pmu.put_event_constraints)
 725                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
 726                 }
 727         }
 728         return num ? -ENOSPC : 0;
 729 }
 730
 731 /*
 732  * dogrp: true if must collect siblings events (group)
 733  * returns total number of events and error code
 734  */
 735 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 736 {
 737         struct perf_event *event;
 738         int n, max_count;
 739
 740         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 741
 742         /* current number of events already accepted */
 743         n = cpuc->n_events;
 744
 745         if (is_x86_event(leader)) {
 746                 if (n >= max_count)
 747                         return -ENOSPC;
 748                 cpuc->event_list[n] = leader;
 749                 n++;
 750         }
 751         if (!dogrp)
 752                 return n;
 753
 754         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 755                 if (!is_x86_event(event) ||
 756                     event->state <= PERF_EVENT_STATE_OFF)
 757                         continue;
 758
 759                 if (n >= max_count)
 760                         return -ENOSPC;
 761
 762                 cpuc->event_list[n] = event;
 763                 n++;
 764         }
 765         return n;
 766 }
 767
 768 static inline void x86_assign_hw_event(struct perf_event *event,
 769                                 struct cpu_hw_events *cpuc, int i)
 770 {
 771         struct hw_perf_event *hwc = &event->hw;
 772
 773         hwc->idx = cpuc->assign[i];
 774         hwc->last_cpu = smp_processor_id();
 775         hwc->last_tag = ++cpuc->tags[i];
 776
 777         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
 778                 hwc->config_base = 0;
 779                 hwc->event_base = 0;
 780         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
 781                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 782                 /*
 783                  * We set it so that event_base + idx in wrmsr/rdmsr maps to
 784                  * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
 785                  */
 786                 hwc->event_base =
 787                         MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
 788         } else {
 789                 hwc->config_base = x86_pmu.eventsel;
 790                 hwc->event_base  = x86_pmu.perfctr;
 791         }
 792 }
 793
 794 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 795                                         struct cpu_hw_events *cpuc,
 796                                         int i)
 797 {
 798         return hwc->idx == cpuc->assign[i] &&
 799                 hwc->last_cpu == smp_processor_id() &&
 800                 hwc->last_tag == cpuc->tags[i];
 801 }
 802
 803 static void x86_pmu_start(struct perf_event *event, int flags);
 804 static void x86_pmu_stop(struct perf_event *event, int flags);
 805
 806 static void x86_pmu_enable(struct pmu *pmu)
 807 {
 808         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 809         struct perf_event *event;
 810         struct hw_perf_event *hwc;
 811         int i, added = cpuc->n_added;
 812
 813         if (!x86_pmu_initialized())
 814                 return;
 815
 816         if (cpuc->enabled)
 817                 return;
 818
 819         if (cpuc->n_added) {
 820                 int n_running = cpuc->n_events - cpuc->n_added;
 821                 /*
 822                  * apply assignment obtained either from
 823                  * hw_perf_group_sched_in() or x86_pmu_enable()
 824                  *
 825                  * step1: save events moving to new counters
 826                  * step2: reprogram moved events into new counters
 827                  */
 828                 for (i = 0; i < n_running; i++) {
 829                         event = cpuc->event_list[i];
 830                         hwc = &event->hw;
 831
 832                         /*
 833                          * we can avoid reprogramming counter if:
 834                          * - assigned same counter as last time
 835                          * - running on same CPU as last time
 836                          * - no other event has used the counter since
 837                          */
 838                         if (hwc->idx == -1 ||
 839                             match_prev_assignment(hwc, cpuc, i))
 840                                 continue;
 841
 842                         /*
 843                          * Ensure we don't accidentally enable a stopped
 844                          * counter simply because we rescheduled.
 845                          */
 846                         if (hwc->state & PERF_HES_STOPPED)
 847                                 hwc->state |= PERF_HES_ARCH;
 848
 849                         x86_pmu_stop(event, PERF_EF_UPDATE);
 850                 }
 851
 852                 for (i = 0; i < cpuc->n_events; i++) {
 853                         event = cpuc->event_list[i];
 854                         hwc = &event->hw;
 855
 856                         if (!match_prev_assignment(hwc, cpuc, i))
 857                                 x86_assign_hw_event(event, cpuc, i);
 858                         else if (i < n_running)
 859                                 continue;
 860
 861                         if (hwc->state & PERF_HES_ARCH)
 862                                 continue;
 863
 864                         x86_pmu_start(event, PERF_EF_RELOAD);
 865                 }
 866                 cpuc->n_added = 0;
 867                 perf_events_lapic_init();
 868         }
 869
 870         cpuc->enabled = 1;
 871         barrier();
 872
 873         x86_pmu.enable_all(added);
 874 }
 875
 876 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
 877                                           u64 enable_mask)
 878 {
 879         wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask);
 880 }
 881
 882 static inline void x86_pmu_disable_event(struct perf_event *event)
 883 {
 884         struct hw_perf_event *hwc = &event->hw;
 885
 886         wrmsrl(hwc->config_base + hwc->idx, hwc->config);
 887 }
 888
 889 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 890
 891 /*
 892  * Set the next IRQ period, based on the hwc->period_left value.
 893  * To be called with the event disabled in hw:
 894  */
 895 static int
 896 x86_perf_event_set_period(struct perf_event *event)
 897 {
 898         struct hw_perf_event *hwc = &event->hw;
 899         s64 left = local64_read(&hwc->period_left);
 900         s64 period = hwc->sample_period;
 901         int ret = 0, idx = hwc->idx;
 902
 903         if (idx == X86_PMC_IDX_FIXED_BTS)
 904                 return 0;
 905
 906         /*
 907          * If we are way outside a reasonable range then just skip forward:
 908          */
 909         if (unlikely(left <= -period)) {
 910                 left = period;
 911                 local64_set(&hwc->period_left, left);
 912                 hwc->last_period = period;
 913                 ret = 1;
 914         }
 915
 916         if (unlikely(left <= 0)) {
 917                 left += period;
 918                 local64_set(&hwc->period_left, left);
 919                 hwc->last_period = period;
 920                 ret = 1;
 921         }
 922         /*
 923          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
 924          */
 925         if (unlikely(left < 2))
 926                 left = 2;
 927
 928         if (left > x86_pmu.max_period)
 929                 left = x86_pmu.max_period;
 930
 931         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 932
 933         /*
 934          * The hw event starts counting from this event offset,
 935          * mark it to be able to extra future deltas:
 936          */
 937         local64_set(&hwc->prev_count, (u64)-left);
 938
 939         wrmsrl(hwc->event_base + idx, (u64)(-left) & x86_pmu.cntval_mask);
 940
 941         /*
 942          * Due to erratum on certan cpu we need
 943          * a second write to be sure the register
 944          * is updated properly
 945          */
 946         if (x86_pmu.perfctr_second_write) {
 947                 wrmsrl(hwc->event_base + idx,
 948                         (u64)(-left) & x86_pmu.cntval_mask);
 949         }
 950
 951         perf_event_update_userpage(event);
 952
 953         return ret;
 954 }
 955
 956 static void x86_pmu_enable_event(struct perf_event *event)
 957 {
 958         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 959         if (cpuc->enabled)
 960                 __x86_pmu_enable_event(&event->hw,
 961                                        ARCH_PERFMON_EVENTSEL_ENABLE);
 962 }
 963
 964 /*
 965  * Add a single event to the PMU.
 966  *
 967  * The event is added to the group of enabled events
 968  * but only if it can be scehduled with existing events.
 969  */
 970 static int x86_pmu_add(struct perf_event *event, int flags)
 971 {
 972         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 973         struct hw_perf_event *hwc;
 974         int assign[X86_PMC_IDX_MAX];
 975         int n, n0, ret;
 976
 977         hwc = &event->hw;
 978
 979         perf_pmu_disable(event->pmu);
 980         n0 = cpuc->n_events;
 981         ret = n = collect_events(cpuc, event, false);
 982         if (ret < 0)
 983                 goto out;
 984
 985         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
 986         if (!(flags & PERF_EF_START))
 987                 hwc->state |= PERF_HES_ARCH;
 988
 989         /*
 990          * If group events scheduling transaction was started,
 991          * skip the schedulability test here, it will be peformed
 992          * at commit time (->commit_txn) as a whole
 993          */
 994         if (cpuc->group_flag & PERF_EVENT_TXN)
 995                 goto done_collect;
 996
 997         ret = x86_pmu.schedule_events(cpuc, n, assign);
 998         if (ret)
 999                 goto out;
1000         /*
1001          * copy new assignment, now we know it is possible
1002          * will be used by hw_perf_enable()
1003          */
1004         memcpy(cpuc->assign, assign, n*sizeof(int));
1005
1006 done_collect:
1007         cpuc->n_events = n;
1008         cpuc->n_added += n - n0;
1009         cpuc->n_txn += n - n0;
1010
1011         ret = 0;
1012 out:
1013         perf_pmu_enable(event->pmu);
1014         return ret;
1015 }
1016
1017 static void x86_pmu_start(struct perf_event *event, int flags)
1018 {
1019         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1020         int idx = event->hw.idx;
1021
1022         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1023                 return;
1024
1025         if (WARN_ON_ONCE(idx == -1))
1026                 return;
1027
1028         if (flags & PERF_EF_RELOAD) {
1029                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1030                 x86_perf_event_set_period(event);
1031         }
1032
1033         event->hw.state = 0;
1034
1035         cpuc->events[idx] = event;
1036         __set_bit(idx, cpuc->active_mask);
1037         x86_pmu.enable(event);
1038         perf_event_update_userpage(event);
1039 }
1040
1041 void perf_event_print_debug(void)
1042 {
1043         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1044         u64 pebs;
1045         struct cpu_hw_events *cpuc;
1046         unsigned long flags;
1047         int cpu, idx;
1048
1049         if (!x86_pmu.num_counters)
1050                 return;
1051
1052         local_irq_save(flags);
1053
1054         cpu = smp_processor_id();
1055         cpuc = &per_cpu(cpu_hw_events, cpu);
1056
1057         if (x86_pmu.version >= 2) {
1058                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1059                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1060                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1061                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1062                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1063
1064                 pr_info("\n");
1065                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1066                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1067                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1068                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1069                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1070         }
1071         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1072
1073         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1074                 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1075                 rdmsrl(x86_pmu.perfctr  + idx, pmc_count);
1076
1077                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1078
1079                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1080                         cpu, idx, pmc_ctrl);
1081                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1082                         cpu, idx, pmc_count);
1083                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1084                         cpu, idx, prev_left);
1085         }
1086         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1087                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1088
1089                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1090                         cpu, idx, pmc_count);
1091         }
1092         local_irq_restore(flags);
1093 }
1094
1095 static void x86_pmu_stop(struct perf_event *event, int flags)
1096 {
1097         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1098         struct hw_perf_event *hwc = &event->hw;
1099
1100         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1101                 x86_pmu.disable(event);
1102                 cpuc->events[hwc->idx] = NULL;
1103                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1104                 hwc->state |= PERF_HES_STOPPED;
1105         }
1106
1107         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1108                 /*
1109                  * Drain the remaining delta count out of a event
1110                  * that we are disabling:
1111                  */
1112                 x86_perf_event_update(event);
1113                 hwc->state |= PERF_HES_UPTODATE;
1114         }
1115 }
1116
1117 static void x86_pmu_del(struct perf_event *event, int flags)
1118 {
1119         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1120         int i;
1121
1122         /*
1123          * If we're called during a txn, we don't need to do anything.
1124          * The events never got scheduled and ->cancel_txn will truncate
1125          * the event_list.
1126          */
1127         if (cpuc->group_flag & PERF_EVENT_TXN)
1128                 return;
1129
1130         x86_pmu_stop(event, PERF_EF_UPDATE);
1131
1132         for (i = 0; i < cpuc->n_events; i++) {
1133                 if (event == cpuc->event_list[i]) {
1134
1135                         if (x86_pmu.put_event_constraints)
1136                                 x86_pmu.put_event_constraints(cpuc, event);
1137
1138                         while (++i < cpuc->n_events)
1139                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1140
1141                         --cpuc->n_events;
1142                         break;
1143                 }
1144         }
1145         perf_event_update_userpage(event);
1146 }
1147
1148 static int x86_pmu_handle_irq(struct pt_regs *regs)
1149 {
1150         struct perf_sample_data data;
1151         struct cpu_hw_events *cpuc;
1152         struct perf_event *event;
1153         struct hw_perf_event *hwc;
1154         int idx, handled = 0;
1155         u64 val;
1156
1157         perf_sample_data_init(&data, 0);
1158
1159         cpuc = &__get_cpu_var(cpu_hw_events);
1160
1161         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1162                 if (!test_bit(idx, cpuc->active_mask))
1163                         continue;
1164
1165                 event = cpuc->events[idx];
1166                 hwc = &event->hw;
1167
1168                 val = x86_perf_event_update(event);
1169                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1170                         continue;
1171
1172                 /*
1173                  * event overflow
1174                  */
1175                 handled++;
1176                 data.period     = event->hw.last_period;
1177
1178                 if (!x86_perf_event_set_period(event))
1179                         continue;
1180
1181                 if (perf_event_overflow(event, 1, &data, regs))
1182                         x86_pmu_stop(event, 0);
1183         }
1184
1185         if (handled)
1186                 inc_irq_stat(apic_perf_irqs);
1187
1188         return handled;
1189 }
1190
1191 void smp_perf_pending_interrupt(struct pt_regs *regs)
1192 {
1193         irq_enter();
1194         ack_APIC_irq();
1195         inc_irq_stat(apic_pending_irqs);
1196         perf_event_do_pending();
1197         irq_exit();
1198 }
1199
1200 void set_perf_event_pending(void)
1201 {
1202 #ifdef CONFIG_X86_LOCAL_APIC
1203         if (!x86_pmu.apic || !x86_pmu_initialized())
1204                 return;
1205
1206         apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1207 #endif
1208 }
1209
1210 void perf_events_lapic_init(void)
1211 {
1212         if (!x86_pmu.apic || !x86_pmu_initialized())
1213                 return;
1214
1215         /*
1216          * Always use NMI for PMU
1217          */
1218         apic_write(APIC_LVTPC, APIC_DM_NMI);
1219 }
1220
1221 struct pmu_nmi_state {
1222         unsigned int    marked;
1223         int             handled;
1224 };
1225
1226 static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi);
1227
1228 static int __kprobes
1229 perf_event_nmi_handler(struct notifier_block *self,
1230                          unsigned long cmd, void *__args)
1231 {
1232         struct die_args *args = __args;
1233         unsigned int this_nmi;
1234         int handled;
1235
1236         if (!atomic_read(&active_events))
1237                 return NOTIFY_DONE;
1238
1239         switch (cmd) {
1240         case DIE_NMI:
1241         case DIE_NMI_IPI:
1242                 break;
1243         case DIE_NMIUNKNOWN:
1244                 this_nmi = percpu_read(irq_stat.__nmi_count);
1245                 if (this_nmi != __get_cpu_var(pmu_nmi).marked)
1246                         /* let the kernel handle the unknown nmi */
1247                         return NOTIFY_DONE;
1248                 /*
1249                  * This one is a PMU back-to-back nmi. Two events
1250                  * trigger 'simultaneously' raising two back-to-back
1251                  * NMIs. If the first NMI handles both, the latter
1252                  * will be empty and daze the CPU. So, we drop it to
1253                  * avoid false-positive 'unknown nmi' messages.
1254                  */
1255                 return NOTIFY_STOP;
1256         default:
1257                 return NOTIFY_DONE;
1258         }
1259
1260         apic_write(APIC_LVTPC, APIC_DM_NMI);
1261
1262         handled = x86_pmu.handle_irq(args->regs);
1263         if (!handled)
1264                 return NOTIFY_DONE;
1265
1266         this_nmi = percpu_read(irq_stat.__nmi_count);
1267         if ((handled > 1) ||
1268                 /* the next nmi could be a back-to-back nmi */
1269             ((__get_cpu_var(pmu_nmi).marked == this_nmi) &&
1270              (__get_cpu_var(pmu_nmi).handled > 1))) {
1271                 /*
1272                  * We could have two subsequent back-to-back nmis: The
1273                  * first handles more than one counter, the 2nd
1274                  * handles only one counter and the 3rd handles no
1275                  * counter.
1276                  *
1277                  * This is the 2nd nmi because the previous was
1278                  * handling more than one counter. We will mark the
1279                  * next (3rd) and then drop it if unhandled.
1280                  */
1281                 __get_cpu_var(pmu_nmi).marked   = this_nmi + 1;
1282                 __get_cpu_var(pmu_nmi).handled  = handled;
1283         }
1284
1285         return NOTIFY_STOP;
1286 }
1287
1288 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1289         .notifier_call          = perf_event_nmi_handler,
1290         .next                   = NULL,
1291         .priority               = 1
1292 };
1293
1294 static struct event_constraint unconstrained;
1295 static struct event_constraint emptyconstraint;
1296
1297 static struct event_constraint *
1298 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1299 {
1300         struct event_constraint *c;
1301
1302         if (x86_pmu.event_constraints) {
1303                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1304                         if ((event->hw.config & c->cmask) == c->code)
1305                                 return c;
1306                 }
1307         }
1308
1309         return &unconstrained;
1310 }
1311
1312 #include "perf_event_amd.c"
1313 #include "perf_event_p6.c"
1314 #include "perf_event_p4.c"
1315 #include "perf_event_intel_lbr.c"
1316 #include "perf_event_intel_ds.c"
1317 #include "perf_event_intel.c"
1318
1319 static int __cpuinit
1320 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1321 {
1322         unsigned int cpu = (long)hcpu;
1323         int ret = NOTIFY_OK;
1324
1325         switch (action & ~CPU_TASKS_FROZEN) {
1326         case CPU_UP_PREPARE:
1327                 if (x86_pmu.cpu_prepare)
1328                         ret = x86_pmu.cpu_prepare(cpu);
1329                 break;
1330
1331         case CPU_STARTING:
1332                 if (x86_pmu.cpu_starting)
1333                         x86_pmu.cpu_starting(cpu);
1334                 break;
1335
1336         case CPU_DYING:
1337                 if (x86_pmu.cpu_dying)
1338                         x86_pmu.cpu_dying(cpu);
1339                 break;
1340
1341         case CPU_UP_CANCELED:
1342         case CPU_DEAD:
1343                 if (x86_pmu.cpu_dead)
1344                         x86_pmu.cpu_dead(cpu);
1345                 break;
1346
1347         default:
1348                 break;
1349         }
1350
1351         return ret;
1352 }
1353
1354 static void __init pmu_check_apic(void)
1355 {
1356         if (cpu_has_apic)
1357                 return;
1358
1359         x86_pmu.apic = 0;
1360         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1361         pr_info("no hardware sampling interrupt available.\n");
1362 }
1363
1364 void __init init_hw_perf_events(void)
1365 {
1366         struct event_constraint *c;
1367         int err;
1368
1369         pr_info("Performance Events: ");
1370
1371         switch (boot_cpu_data.x86_vendor) {
1372         case X86_VENDOR_INTEL:
1373                 err = intel_pmu_init();
1374                 break;
1375         case X86_VENDOR_AMD:
1376                 err = amd_pmu_init();
1377                 break;
1378         default:
1379                 return;
1380         }
1381         if (err != 0) {
1382                 pr_cont("no PMU driver, software events only.\n");
1383                 return;
1384         }
1385
1386         pmu_check_apic();
1387
1388         pr_cont("%s PMU driver.\n", x86_pmu.name);
1389
1390         if (x86_pmu.quirks)
1391                 x86_pmu.quirks();
1392
1393         if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1394                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1395                      x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1396                 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1397         }
1398         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1399         perf_max_events = x86_pmu.num_counters;
1400
1401         if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1402                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1403                      x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1404                 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1405         }
1406
1407         x86_pmu.intel_ctrl |=
1408                 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1409
1410         perf_events_lapic_init();
1411         register_die_notifier(&perf_event_nmi_notifier);
1412
1413         unconstrained = (struct event_constraint)
1414                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1415                                    0, x86_pmu.num_counters);
1416
1417         if (x86_pmu.event_constraints) {
1418                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1419                         if (c->cmask != X86_RAW_EVENT_MASK)
1420                                 continue;
1421
1422                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1423                         c->weight += x86_pmu.num_counters;
1424                 }
1425         }
1426
1427         pr_info("... version:                %d\n",     x86_pmu.version);
1428         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1429         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1430         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1431         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1432         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1433         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1434
1435         perf_pmu_register(&pmu);
1436         perf_cpu_notifier(x86_pmu_notifier);
1437 }
1438
1439 static inline void x86_pmu_read(struct perf_event *event)
1440 {
1441         x86_perf_event_update(event);
1442 }
1443
1444 /*
1445  * Start group events scheduling transaction
1446  * Set the flag to make pmu::enable() not perform the
1447  * schedulability test, it will be performed at commit time
1448  */
1449 static void x86_pmu_start_txn(struct pmu *pmu)
1450 {
1451         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1452
1453         perf_pmu_disable(pmu);
1454         cpuc->group_flag |= PERF_EVENT_TXN;
1455         cpuc->n_txn = 0;
1456 }
1457
1458 /*
1459  * Stop group events scheduling transaction
1460  * Clear the flag and pmu::enable() will perform the
1461  * schedulability test.
1462  */
1463 static void x86_pmu_cancel_txn(struct pmu *pmu)
1464 {
1465         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1466
1467         cpuc->group_flag &= ~PERF_EVENT_TXN;
1468         /*
1469          * Truncate the collected events.
1470          */
1471         cpuc->n_added -= cpuc->n_txn;
1472         cpuc->n_events -= cpuc->n_txn;
1473         perf_pmu_enable(pmu);
1474 }
1475
1476 /*
1477  * Commit group events scheduling transaction
1478  * Perform the group schedulability test as a whole
1479  * Return 0 if success
1480  */
1481 static int x86_pmu_commit_txn(struct pmu *pmu)
1482 {
1483         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1484         int assign[X86_PMC_IDX_MAX];
1485         int n, ret;
1486
1487         n = cpuc->n_events;
1488
1489         if (!x86_pmu_initialized())
1490                 return -EAGAIN;
1491
1492         ret = x86_pmu.schedule_events(cpuc, n, assign);
1493         if (ret)
1494                 return ret;
1495
1496         /*
1497          * copy new assignment, now we know it is possible
1498          * will be used by hw_perf_enable()
1499          */
1500         memcpy(cpuc->assign, assign, n*sizeof(int));
1501
1502         cpuc->group_flag &= ~PERF_EVENT_TXN;
1503         perf_pmu_enable(pmu);
1504         return 0;
1505 }
1506
1507 /*
1508  * validate that we can schedule this event
1509  */
1510 static int validate_event(struct perf_event *event)
1511 {
1512         struct cpu_hw_events *fake_cpuc;
1513         struct event_constraint *c;
1514         int ret = 0;
1515
1516         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1517         if (!fake_cpuc)
1518                 return -ENOMEM;
1519
1520         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1521
1522         if (!c || !c->weight)
1523                 ret = -ENOSPC;
1524
1525         if (x86_pmu.put_event_constraints)
1526                 x86_pmu.put_event_constraints(fake_cpuc, event);
1527
1528         kfree(fake_cpuc);
1529
1530         return ret;
1531 }
1532
1533 /*
1534  * validate a single event group
1535  *
1536  * validation include:
1537  *      - check events are compatible which each other
1538  *      - events do not compete for the same counter
1539  *      - number of events <= number of counters
1540  *
1541  * validation ensures the group can be loaded onto the
1542  * PMU if it was the only group available.
1543  */
1544 static int validate_group(struct perf_event *event)
1545 {
1546         struct perf_event *leader = event->group_leader;
1547         struct cpu_hw_events *fake_cpuc;
1548         int ret, n;
1549
1550         ret = -ENOMEM;
1551         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1552         if (!fake_cpuc)
1553                 goto out;
1554
1555         /*
1556          * the event is not yet connected with its
1557          * siblings therefore we must first collect
1558          * existing siblings, then add the new event
1559          * before we can simulate the scheduling
1560          */
1561         ret = -ENOSPC;
1562         n = collect_events(fake_cpuc, leader, true);
1563         if (n < 0)
1564                 goto out_free;
1565
1566         fake_cpuc->n_events = n;
1567         n = collect_events(fake_cpuc, event, false);
1568         if (n < 0)
1569                 goto out_free;
1570
1571         fake_cpuc->n_events = n;
1572
1573         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1574
1575 out_free:
1576         kfree(fake_cpuc);
1577 out:
1578         return ret;
1579 }
1580
1581 int x86_pmu_event_init(struct perf_event *event)
1582 {
1583         struct pmu *tmp;
1584         int err;
1585
1586         switch (event->attr.type) {
1587         case PERF_TYPE_RAW:
1588         case PERF_TYPE_HARDWARE:
1589         case PERF_TYPE_HW_CACHE:
1590                 break;
1591
1592         default:
1593                 return -ENOENT;
1594         }
1595
1596         err = __x86_pmu_event_init(event);
1597         if (!err) {
1598                 /*
1599                  * we temporarily connect event to its pmu
1600                  * such that validate_group() can classify
1601                  * it as an x86 event using is_x86_event()
1602                  */
1603                 tmp = event->pmu;
1604                 event->pmu = &pmu;
1605
1606                 if (event->group_leader != event)
1607                         err = validate_group(event);
1608                 else
1609                         err = validate_event(event);
1610
1611                 event->pmu = tmp;
1612         }
1613         if (err) {
1614                 if (event->destroy)
1615                         event->destroy(event);
1616         }
1617
1618         return err;
1619 }
1620
1621 static struct pmu pmu = {
1622         .pmu_enable     = x86_pmu_enable,
1623         .pmu_disable    = x86_pmu_disable,
1624
1625         .event_init     = x86_pmu_event_init,
1626
1627         .add            = x86_pmu_add,
1628         .del            = x86_pmu_del,
1629         .start          = x86_pmu_start,
1630         .stop           = x86_pmu_stop,
1631         .read           = x86_pmu_read,
1632
1633         .start_txn      = x86_pmu_start_txn,
1634         .cancel_txn     = x86_pmu_cancel_txn,
1635         .commit_txn     = x86_pmu_commit_txn,
1636 };
1637
1638 /*
1639  * callchain support
1640  */
1641
1642 static void
1643 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1644 {
1645         /* Ignore warnings */
1646 }
1647
1648 static void backtrace_warning(void *data, char *msg)
1649 {
1650         /* Ignore warnings */
1651 }
1652
1653 static int backtrace_stack(void *data, char *name)
1654 {
1655         return 0;
1656 }
1657
1658 static void backtrace_address(void *data, unsigned long addr, int reliable)
1659 {
1660         struct perf_callchain_entry *entry = data;
1661
1662         perf_callchain_store(entry, addr);
1663 }
1664
1665 static const struct stacktrace_ops backtrace_ops = {
1666         .warning                = backtrace_warning,
1667         .warning_symbol         = backtrace_warning_symbol,
1668         .stack                  = backtrace_stack,
1669         .address                = backtrace_address,
1670         .walk_stack             = print_context_stack_bp,
1671 };
1672
1673 void
1674 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1675 {
1676         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1677                 /* TODO: We don't support guest os callchain now */
1678                 return;
1679         }
1680
1681         perf_callchain_store(entry, regs->ip);
1682
1683         dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
1684 }
1685
1686 #ifdef CONFIG_COMPAT
1687 static inline int
1688 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1689 {
1690         /* 32-bit process in 64-bit kernel. */
1691         struct stack_frame_ia32 frame;
1692         const void __user *fp;
1693
1694         if (!test_thread_flag(TIF_IA32))
1695                 return 0;
1696
1697         fp = compat_ptr(regs->bp);
1698         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1699                 unsigned long bytes;
1700                 frame.next_frame     = 0;
1701                 frame.return_address = 0;
1702
1703                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1704                 if (bytes != sizeof(frame))
1705                         break;
1706
1707                 if (fp < compat_ptr(regs->sp))
1708                         break;
1709
1710                 perf_callchain_store(entry, frame.return_address);
1711                 fp = compat_ptr(frame.next_frame);
1712         }
1713         return 1;
1714 }
1715 #else
1716 static inline int
1717 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1718 {
1719     return 0;
1720 }
1721 #endif
1722
1723 void
1724 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1725 {
1726         struct stack_frame frame;
1727         const void __user *fp;
1728
1729         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1730                 /* TODO: We don't support guest os callchain now */
1731                 return;
1732         }
1733
1734         fp = (void __user *)regs->bp;
1735
1736         perf_callchain_store(entry, regs->ip);
1737
1738         if (perf_callchain_user32(regs, entry))
1739                 return;
1740
1741         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1742                 unsigned long bytes;
1743                 frame.next_frame             = NULL;
1744                 frame.return_address = 0;
1745
1746                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1747                 if (bytes != sizeof(frame))
1748                         break;
1749
1750                 if ((unsigned long)fp < regs->sp)
1751                         break;
1752
1753                 perf_callchain_store(entry, frame.return_address);
1754                 fp = frame.next_frame;
1755         }
1756 }
1757
1758 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1759 {
1760         unsigned long ip;
1761
1762         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1763                 ip = perf_guest_cbs->get_guest_ip();
1764         else
1765                 ip = instruction_pointer(regs);
1766
1767         return ip;
1768 }
1769
1770 unsigned long perf_misc_flags(struct pt_regs *regs)
1771 {
1772         int misc = 0;
1773
1774         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1775                 if (perf_guest_cbs->is_user_mode())
1776                         misc |= PERF_RECORD_MISC_GUEST_USER;
1777                 else
1778                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1779         } else {
1780                 if (user_mode(regs))
1781                         misc |= PERF_RECORD_MISC_USER;
1782                 else
1783                         misc |= PERF_RECORD_MISC_KERNEL;
1784         }
1785
1786         if (regs->flags & PERF_EFLAGS_EXACT)
1787                 misc |= PERF_RECORD_MISC_EXACT_IP;
1788
1789         return misc;
1790 }