arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/highmem.h>
  26 #include <linux/cpu.h>
  27 #include <linux/bitops.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/compat.h>
  33
  34 #if 0
  35 #undef wrmsrl
  36 #define wrmsrl(msr, val)                                        \
  37 do {                                                            \
  38         trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
  39                         (unsigned long)(val));                  \
  40         native_write_msr((msr), (u32)((u64)(val)),              \
  41                         (u32)((u64)(val) >> 32));               \
  42 } while (0)
  43 #endif
  44
  45 /*
  46  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
  47  */
  48 static unsigned long
  49 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
  50 {
  51         unsigned long offset, addr = (unsigned long)from;
  52         int type = in_nmi() ? KM_NMI : KM_IRQ0;
  53         unsigned long size, len = 0;
  54         struct page *page;
  55         void *map;
  56         int ret;
  57
  58         do {
  59                 ret = __get_user_pages_fast(addr, 1, 0, &page);
  60                 if (!ret)
  61                         break;
  62
  63                 offset = addr & (PAGE_SIZE - 1);
  64                 size = min(PAGE_SIZE - offset, n - len);
  65
  66                 map = kmap_atomic(page, type);
  67                 memcpy(to, map+offset, size);
  68                 kunmap_atomic(map, type);
  69                 put_page(page);
  70
  71                 len  += size;
  72                 to   += size;
  73                 addr += size;
  74
  75         } while (len < n);
  76
  77         return len;
  78 }
  79
  80 struct event_constraint {
  81         union {
  82                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  83                 u64             idxmsk64;
  84         };
  85         u64     code;
  86         u64     cmask;
  87         int     weight;
  88 };
  89
  90 struct amd_nb {
  91         int nb_id;  /* NorthBridge id */
  92         int refcnt; /* reference count */
  93         struct perf_event *owners[X86_PMC_IDX_MAX];
  94         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
  95 };
  96
  97 #define MAX_LBR_ENTRIES         16
  98
  99 struct cpu_hw_events {
 100         /*
 101          * Generic x86 PMC bits
 102          */
 103         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
 104         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 105         unsigned long           running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 106         int                     enabled;
 107
 108         int                     n_events;
 109         int                     n_added;
 110         int                     n_txn;
 111         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
 112         u64                     tags[X86_PMC_IDX_MAX];
 113         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
 114
 115         unsigned int            group_flag;
 116
 117         /*
 118          * Intel DebugStore bits
 119          */
 120         struct debug_store      *ds;
 121         u64                     pebs_enabled;
 122
 123         /*
 124          * Intel LBR bits
 125          */
 126         int                             lbr_users;
 127         void                            *lbr_context;
 128         struct perf_branch_stack        lbr_stack;
 129         struct perf_branch_entry        lbr_entries[MAX_LBR_ENTRIES];
 130
 131         /*
 132          * AMD specific bits
 133          */
 134         struct amd_nb           *amd_nb;
 135 };
 136
 137 #define __EVENT_CONSTRAINT(c, n, m, w) {\
 138         { .idxmsk64 = (n) },            \
 139         .code = (c),                    \
 140         .cmask = (m),                   \
 141         .weight = (w),                  \
 142 }
 143
 144 #define EVENT_CONSTRAINT(c, n, m)       \
 145         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
 146
 147 /*
 148  * Constraint on the Event code.
 149  */
 150 #define INTEL_EVENT_CONSTRAINT(c, n)    \
 151         EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
 152
 153 /*
 154  * Constraint on the Event code + UMask + fixed-mask
 155  *
 156  * filter mask to validate fixed counter events.
 157  * the following filters disqualify for fixed counters:
 158  *  - inv
 159  *  - edge
 160  *  - cnt-mask
 161  *  The other filters are supported by fixed counters.
 162  *  The any-thread option is supported starting with v3.
 163  */
 164 #define FIXED_EVENT_CONSTRAINT(c, n)    \
 165         EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
 166
 167 /*
 168  * Constraint on the Event code + UMask
 169  */
 170 #define PEBS_EVENT_CONSTRAINT(c, n)     \
 171         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
 172
 173 #define EVENT_CONSTRAINT_END            \
 174         EVENT_CONSTRAINT(0, 0, 0)
 175
 176 #define for_each_event_constraint(e, c) \
 177         for ((e) = (c); (e)->weight; (e)++)
 178
 179 union perf_capabilities {
 180         struct {
 181                 u64     lbr_format    : 6;
 182                 u64     pebs_trap     : 1;
 183                 u64     pebs_arch_reg : 1;
 184                 u64     pebs_format   : 4;
 185                 u64     smm_freeze    : 1;
 186         };
 187         u64     capabilities;
 188 };
 189
 190 /*
 191  * struct x86_pmu - generic x86 pmu
 192  */
 193 struct x86_pmu {
 194         /*
 195          * Generic x86 PMC bits
 196          */
 197         const char      *name;
 198         int             version;
 199         int             (*handle_irq)(struct pt_regs *);
 200         void            (*disable_all)(void);
 201         void            (*enable_all)(int added);
 202         void            (*enable)(struct perf_event *);
 203         void            (*disable)(struct perf_event *);
 204         int             (*hw_config)(struct perf_event *event);
 205         int             (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
 206         unsigned        eventsel;
 207         unsigned        perfctr;
 208         u64             (*event_map)(int);
 209         int             max_events;
 210         int             num_counters;
 211         int             num_counters_fixed;
 212         int             cntval_bits;
 213         u64             cntval_mask;
 214         int             apic;
 215         u64             max_period;
 216         struct event_constraint *
 217                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
 218                                                  struct perf_event *event);
 219
 220         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
 221                                                  struct perf_event *event);
 222         struct event_constraint *event_constraints;
 223         void            (*quirks)(void);
 224         int             perfctr_second_write;
 225
 226         int             (*cpu_prepare)(int cpu);
 227         void            (*cpu_starting)(int cpu);
 228         void            (*cpu_dying)(int cpu);
 229         void            (*cpu_dead)(int cpu);
 230
 231         /*
 232          * Intel Arch Perfmon v2+
 233          */
 234         u64                     intel_ctrl;
 235         union perf_capabilities intel_cap;
 236
 237         /*
 238          * Intel DebugStore bits
 239          */
 240         int             bts, pebs;
 241         int             pebs_record_size;
 242         void            (*drain_pebs)(struct pt_regs *regs);
 243         struct event_constraint *pebs_constraints;
 244
 245         /*
 246          * Intel LBR
 247          */
 248         unsigned long   lbr_tos, lbr_from, lbr_to; /* MSR base regs       */
 249         int             lbr_nr;                    /* hardware stack size */
 250 };
 251
 252 static struct x86_pmu x86_pmu __read_mostly;
 253
 254 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
 255         .enabled = 1,
 256 };
 257
 258 static int x86_perf_event_set_period(struct perf_event *event);
 259
 260 /*
 261  * Generalized hw caching related hw_event table, filled
 262  * in on a per model basis. A value of 0 means
 263  * 'not supported', -1 means 'hw_event makes no sense on
 264  * this CPU', any other value means the raw hw_event
 265  * ID.
 266  */
 267
 268 #define C(x) PERF_COUNT_HW_CACHE_##x
 269
 270 static u64 __read_mostly hw_cache_event_ids
 271                                 [PERF_COUNT_HW_CACHE_MAX]
 272                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 273                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 274
 275 /*
 276  * Propagate event elapsed time into the generic event.
 277  * Can only be executed on the CPU where the event is active.
 278  * Returns the delta events processed.
 279  */
 280 static u64
 281 x86_perf_event_update(struct perf_event *event)
 282 {
 283         struct hw_perf_event *hwc = &event->hw;
 284         int shift = 64 - x86_pmu.cntval_bits;
 285         u64 prev_raw_count, new_raw_count;
 286         int idx = hwc->idx;
 287         s64 delta;
 288
 289         if (idx == X86_PMC_IDX_FIXED_BTS)
 290                 return 0;
 291
 292         /*
 293          * Careful: an NMI might modify the previous event value.
 294          *
 295          * Our tactic to handle this is to first atomically read and
 296          * exchange a new raw count - then add that new-prev delta
 297          * count to the generic event atomically:
 298          */
 299 again:
 300         prev_raw_count = local64_read(&hwc->prev_count);
 301         rdmsrl(hwc->event_base + idx, new_raw_count);
 302
 303         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 304                                         new_raw_count) != prev_raw_count)
 305                 goto again;
 306
 307         /*
 308          * Now we have the new raw value and have updated the prev
 309          * timestamp already. We can now calculate the elapsed delta
 310          * (event-)time and add that to the generic event.
 311          *
 312          * Careful, not all hw sign-extends above the physical width
 313          * of the count.
 314          */
 315         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 316         delta >>= shift;
 317
 318         local64_add(delta, &event->count);
 319         local64_sub(delta, &hwc->period_left);
 320
 321         return new_raw_count;
 322 }
 323
 324 static atomic_t active_events;
 325 static DEFINE_MUTEX(pmc_reserve_mutex);
 326
 327 #ifdef CONFIG_X86_LOCAL_APIC
 328
 329 static bool reserve_pmc_hardware(void)
 330 {
 331         int i;
 332
 333         if (nmi_watchdog == NMI_LOCAL_APIC)
 334                 disable_lapic_nmi_watchdog();
 335
 336         for (i = 0; i < x86_pmu.num_counters; i++) {
 337                 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
 338                         goto perfctr_fail;
 339         }
 340
 341         for (i = 0; i < x86_pmu.num_counters; i++) {
 342                 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
 343                         goto eventsel_fail;
 344         }
 345
 346         return true;
 347
 348 eventsel_fail:
 349         for (i--; i >= 0; i--)
 350                 release_evntsel_nmi(x86_pmu.eventsel + i);
 351
 352         i = x86_pmu.num_counters;
 353
 354 perfctr_fail:
 355         for (i--; i >= 0; i--)
 356                 release_perfctr_nmi(x86_pmu.perfctr + i);
 357
 358         if (nmi_watchdog == NMI_LOCAL_APIC)
 359                 enable_lapic_nmi_watchdog();
 360
 361         return false;
 362 }
 363
 364 static void release_pmc_hardware(void)
 365 {
 366         int i;
 367
 368         for (i = 0; i < x86_pmu.num_counters; i++) {
 369                 release_perfctr_nmi(x86_pmu.perfctr + i);
 370                 release_evntsel_nmi(x86_pmu.eventsel + i);
 371         }
 372
 373         if (nmi_watchdog == NMI_LOCAL_APIC)
 374                 enable_lapic_nmi_watchdog();
 375 }
 376
 377 #else
 378
 379 static bool reserve_pmc_hardware(void) { return true; }
 380 static void release_pmc_hardware(void) {}
 381
 382 #endif
 383
 384 static int reserve_ds_buffers(void);
 385 static void release_ds_buffers(void);
 386
 387 static void hw_perf_event_destroy(struct perf_event *event)
 388 {
 389         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 390                 release_pmc_hardware();
 391                 release_ds_buffers();
 392                 mutex_unlock(&pmc_reserve_mutex);
 393         }
 394 }
 395
 396 static inline int x86_pmu_initialized(void)
 397 {
 398         return x86_pmu.handle_irq != NULL;
 399 }
 400
 401 static inline int
 402 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
 403 {
 404         unsigned int cache_type, cache_op, cache_result;
 405         u64 config, val;
 406
 407         config = attr->config;
 408
 409         cache_type = (config >>  0) & 0xff;
 410         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 411                 return -EINVAL;
 412
 413         cache_op = (config >>  8) & 0xff;
 414         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 415                 return -EINVAL;
 416
 417         cache_result = (config >> 16) & 0xff;
 418         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 419                 return -EINVAL;
 420
 421         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 422
 423         if (val == 0)
 424                 return -ENOENT;
 425
 426         if (val == -1)
 427                 return -EINVAL;
 428
 429         hwc->config |= val;
 430
 431         return 0;
 432 }
 433
 434 static int x86_setup_perfctr(struct perf_event *event)
 435 {
 436         struct perf_event_attr *attr = &event->attr;
 437         struct hw_perf_event *hwc = &event->hw;
 438         u64 config;
 439
 440         if (!hwc->sample_period) {
 441                 hwc->sample_period = x86_pmu.max_period;
 442                 hwc->last_period = hwc->sample_period;
 443                 local64_set(&hwc->period_left, hwc->sample_period);
 444         } else {
 445                 /*
 446                  * If we have a PMU initialized but no APIC
 447                  * interrupts, we cannot sample hardware
 448                  * events (user-space has to fall back and
 449                  * sample via a hrtimer based software event):
 450                  */
 451                 if (!x86_pmu.apic)
 452                         return -EOPNOTSUPP;
 453         }
 454
 455         if (attr->type == PERF_TYPE_RAW)
 456                 return 0;
 457
 458         if (attr->type == PERF_TYPE_HW_CACHE)
 459                 return set_ext_hw_attr(hwc, attr);
 460
 461         if (attr->config >= x86_pmu.max_events)
 462                 return -EINVAL;
 463
 464         /*
 465          * The generic map:
 466          */
 467         config = x86_pmu.event_map(attr->config);
 468
 469         if (config == 0)
 470                 return -ENOENT;
 471
 472         if (config == -1LL)
 473                 return -EINVAL;
 474
 475         /*
 476          * Branch tracing:
 477          */
 478         if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
 479             (hwc->sample_period == 1)) {
 480                 /* BTS is not supported by this architecture. */
 481                 if (!x86_pmu.bts)
 482                         return -EOPNOTSUPP;
 483
 484                 /* BTS is currently only allowed for user-mode. */
 485                 if (!attr->exclude_kernel)
 486                         return -EOPNOTSUPP;
 487         }
 488
 489         hwc->config |= config;
 490
 491         return 0;
 492 }
 493
 494 static int x86_pmu_hw_config(struct perf_event *event)
 495 {
 496         if (event->attr.precise_ip) {
 497                 int precise = 0;
 498
 499                 /* Support for constant skid */
 500                 if (x86_pmu.pebs)
 501                         precise++;
 502
 503                 /* Support for IP fixup */
 504                 if (x86_pmu.lbr_nr)
 505                         precise++;
 506
 507                 if (event->attr.precise_ip > precise)
 508                         return -EOPNOTSUPP;
 509         }
 510
 511         /*
 512          * Generate PMC IRQs:
 513          * (keep 'enabled' bit clear for now)
 514          */
 515         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 516
 517         /*
 518          * Count user and OS events unless requested not to
 519          */
 520         if (!event->attr.exclude_user)
 521                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 522         if (!event->attr.exclude_kernel)
 523                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 524
 525         if (event->attr.type == PERF_TYPE_RAW)
 526                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 527
 528         return x86_setup_perfctr(event);
 529 }
 530
 531 /*
 532  * Setup the hardware configuration for a given attr_type
 533  */
 534 static int __x86_pmu_event_init(struct perf_event *event)
 535 {
 536         int err;
 537
 538         if (!x86_pmu_initialized())
 539                 return -ENODEV;
 540
 541         err = 0;
 542         if (!atomic_inc_not_zero(&active_events)) {
 543                 mutex_lock(&pmc_reserve_mutex);
 544                 if (atomic_read(&active_events) == 0) {
 545                         if (!reserve_pmc_hardware())
 546                                 err = -EBUSY;
 547                         else {
 548                                 err = reserve_ds_buffers();
 549                                 if (err)
 550                                         release_pmc_hardware();
 551                         }
 552                 }
 553                 if (!err)
 554                         atomic_inc(&active_events);
 555                 mutex_unlock(&pmc_reserve_mutex);
 556         }
 557         if (err)
 558                 return err;
 559
 560         event->destroy = hw_perf_event_destroy;
 561
 562         event->hw.idx = -1;
 563         event->hw.last_cpu = -1;
 564         event->hw.last_tag = ~0ULL;
 565
 566         return x86_pmu.hw_config(event);
 567 }
 568
 569 static void x86_pmu_disable_all(void)
 570 {
 571         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 572         int idx;
 573
 574         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 575                 u64 val;
 576
 577                 if (!test_bit(idx, cpuc->active_mask))
 578                         continue;
 579                 rdmsrl(x86_pmu.eventsel + idx, val);
 580                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 581                         continue;
 582                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 583                 wrmsrl(x86_pmu.eventsel + idx, val);
 584         }
 585 }
 586
 587 static void x86_pmu_disable(struct pmu *pmu)
 588 {
 589         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 590
 591         if (!x86_pmu_initialized())
 592                 return;
 593
 594         if (!cpuc->enabled)
 595                 return;
 596
 597         cpuc->n_added = 0;
 598         cpuc->enabled = 0;
 599         barrier();
 600
 601         x86_pmu.disable_all();
 602 }
 603
 604 static void x86_pmu_enable_all(int added)
 605 {
 606         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 607         int idx;
 608
 609         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 610                 struct perf_event *event = cpuc->events[idx];
 611                 u64 val;
 612
 613                 if (!test_bit(idx, cpuc->active_mask))
 614                         continue;
 615
 616                 val = event->hw.config;
 617                 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
 618                 wrmsrl(x86_pmu.eventsel + idx, val);
 619         }
 620 }
 621
 622 static struct pmu pmu;
 623
 624 static inline int is_x86_event(struct perf_event *event)
 625 {
 626         return event->pmu == &pmu;
 627 }
 628
 629 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 630 {
 631         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
 632         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 633         int i, j, w, wmax, num = 0;
 634         struct hw_perf_event *hwc;
 635
 636         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 637
 638         for (i = 0; i < n; i++) {
 639                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 640                 constraints[i] = c;
 641         }
 642
 643         /*
 644          * fastpath, try to reuse previous register
 645          */
 646         for (i = 0; i < n; i++) {
 647                 hwc = &cpuc->event_list[i]->hw;
 648                 c = constraints[i];
 649
 650                 /* never assigned */
 651                 if (hwc->idx == -1)
 652                         break;
 653
 654                 /* constraint still honored */
 655                 if (!test_bit(hwc->idx, c->idxmsk))
 656                         break;
 657
 658                 /* not already used */
 659                 if (test_bit(hwc->idx, used_mask))
 660                         break;
 661
 662                 __set_bit(hwc->idx, used_mask);
 663                 if (assign)
 664                         assign[i] = hwc->idx;
 665         }
 666         if (i == n)
 667                 goto done;
 668
 669         /*
 670          * begin slow path
 671          */
 672
 673         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 674
 675         /*
 676          * weight = number of possible counters
 677          *
 678          * 1    = most constrained, only works on one counter
 679          * wmax = least constrained, works on any counter
 680          *
 681          * assign events to counters starting with most
 682          * constrained events.
 683          */
 684         wmax = x86_pmu.num_counters;
 685
 686         /*
 687          * when fixed event counters are present,
 688          * wmax is incremented by 1 to account
 689          * for one more choice
 690          */
 691         if (x86_pmu.num_counters_fixed)
 692                 wmax++;
 693
 694         for (w = 1, num = n; num && w <= wmax; w++) {
 695                 /* for each event */
 696                 for (i = 0; num && i < n; i++) {
 697                         c = constraints[i];
 698                         hwc = &cpuc->event_list[i]->hw;
 699
 700                         if (c->weight != w)
 701                                 continue;
 702
 703                         for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
 704                                 if (!test_bit(j, used_mask))
 705                                         break;
 706                         }
 707
 708                         if (j == X86_PMC_IDX_MAX)
 709                                 break;
 710
 711                         __set_bit(j, used_mask);
 712
 713                         if (assign)
 714                                 assign[i] = j;
 715                         num--;
 716                 }
 717         }
 718 done:
 719         /*
 720          * scheduling failed or is just a simulation,
 721          * free resources if necessary
 722          */
 723         if (!assign || num) {
 724                 for (i = 0; i < n; i++) {
 725                         if (x86_pmu.put_event_constraints)
 726                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
 727                 }
 728         }
 729         return num ? -ENOSPC : 0;
 730 }
 731
 732 /*
 733  * dogrp: true if must collect siblings events (group)
 734  * returns total number of events and error code
 735  */
 736 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 737 {
 738         struct perf_event *event;
 739         int n, max_count;
 740
 741         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 742
 743         /* current number of events already accepted */
 744         n = cpuc->n_events;
 745
 746         if (is_x86_event(leader)) {
 747                 if (n >= max_count)
 748                         return -ENOSPC;
 749                 cpuc->event_list[n] = leader;
 750                 n++;
 751         }
 752         if (!dogrp)
 753                 return n;
 754
 755         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 756                 if (!is_x86_event(event) ||
 757                     event->state <= PERF_EVENT_STATE_OFF)
 758                         continue;
 759
 760                 if (n >= max_count)
 761                         return -ENOSPC;
 762
 763                 cpuc->event_list[n] = event;
 764                 n++;
 765         }
 766         return n;
 767 }
 768
 769 static inline void x86_assign_hw_event(struct perf_event *event,
 770                                 struct cpu_hw_events *cpuc, int i)
 771 {
 772         struct hw_perf_event *hwc = &event->hw;
 773
 774         hwc->idx = cpuc->assign[i];
 775         hwc->last_cpu = smp_processor_id();
 776         hwc->last_tag = ++cpuc->tags[i];
 777
 778         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
 779                 hwc->config_base = 0;
 780                 hwc->event_base = 0;
 781         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
 782                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 783                 /*
 784                  * We set it so that event_base + idx in wrmsr/rdmsr maps to
 785                  * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
 786                  */
 787                 hwc->event_base =
 788                         MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
 789         } else {
 790                 hwc->config_base = x86_pmu.eventsel;
 791                 hwc->event_base  = x86_pmu.perfctr;
 792         }
 793 }
 794
 795 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 796                                         struct cpu_hw_events *cpuc,
 797                                         int i)
 798 {
 799         return hwc->idx == cpuc->assign[i] &&
 800                 hwc->last_cpu == smp_processor_id() &&
 801                 hwc->last_tag == cpuc->tags[i];
 802 }
 803
 804 static void x86_pmu_start(struct perf_event *event, int flags);
 805 static void x86_pmu_stop(struct perf_event *event, int flags);
 806
 807 static void x86_pmu_enable(struct pmu *pmu)
 808 {
 809         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 810         struct perf_event *event;
 811         struct hw_perf_event *hwc;
 812         int i, added = cpuc->n_added;
 813
 814         if (!x86_pmu_initialized())
 815                 return;
 816
 817         if (cpuc->enabled)
 818                 return;
 819
 820         if (cpuc->n_added) {
 821                 int n_running = cpuc->n_events - cpuc->n_added;
 822                 /*
 823                  * apply assignment obtained either from
 824                  * hw_perf_group_sched_in() or x86_pmu_enable()
 825                  *
 826                  * step1: save events moving to new counters
 827                  * step2: reprogram moved events into new counters
 828                  */
 829                 for (i = 0; i < n_running; i++) {
 830                         event = cpuc->event_list[i];
 831                         hwc = &event->hw;
 832
 833                         /*
 834                          * we can avoid reprogramming counter if:
 835                          * - assigned same counter as last time
 836                          * - running on same CPU as last time
 837                          * - no other event has used the counter since
 838                          */
 839                         if (hwc->idx == -1 ||
 840                             match_prev_assignment(hwc, cpuc, i))
 841                                 continue;
 842
 843                         /*
 844                          * Ensure we don't accidentally enable a stopped
 845                          * counter simply because we rescheduled.
 846                          */
 847                         if (hwc->state & PERF_HES_STOPPED)
 848                                 hwc->state |= PERF_HES_ARCH;
 849
 850                         x86_pmu_stop(event, PERF_EF_UPDATE);
 851                 }
 852
 853                 for (i = 0; i < cpuc->n_events; i++) {
 854                         event = cpuc->event_list[i];
 855                         hwc = &event->hw;
 856
 857                         if (!match_prev_assignment(hwc, cpuc, i))
 858                                 x86_assign_hw_event(event, cpuc, i);
 859                         else if (i < n_running)
 860                                 continue;
 861
 862                         if (hwc->state & PERF_HES_ARCH)
 863                                 continue;
 864
 865                         x86_pmu_start(event, PERF_EF_RELOAD);
 866                 }
 867                 cpuc->n_added = 0;
 868                 perf_events_lapic_init();
 869         }
 870
 871         cpuc->enabled = 1;
 872         barrier();
 873
 874         x86_pmu.enable_all(added);
 875 }
 876
 877 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
 878                                           u64 enable_mask)
 879 {
 880         wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask);
 881 }
 882
 883 static inline void x86_pmu_disable_event(struct perf_event *event)
 884 {
 885         struct hw_perf_event *hwc = &event->hw;
 886
 887         wrmsrl(hwc->config_base + hwc->idx, hwc->config);
 888 }
 889
 890 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 891
 892 /*
 893  * Set the next IRQ period, based on the hwc->period_left value.
 894  * To be called with the event disabled in hw:
 895  */
 896 static int
 897 x86_perf_event_set_period(struct perf_event *event)
 898 {
 899         struct hw_perf_event *hwc = &event->hw;
 900         s64 left = local64_read(&hwc->period_left);
 901         s64 period = hwc->sample_period;
 902         int ret = 0, idx = hwc->idx;
 903
 904         if (idx == X86_PMC_IDX_FIXED_BTS)
 905                 return 0;
 906
 907         /*
 908          * If we are way outside a reasonable range then just skip forward:
 909          */
 910         if (unlikely(left <= -period)) {
 911                 left = period;
 912                 local64_set(&hwc->period_left, left);
 913                 hwc->last_period = period;
 914                 ret = 1;
 915         }
 916
 917         if (unlikely(left <= 0)) {
 918                 left += period;
 919                 local64_set(&hwc->period_left, left);
 920                 hwc->last_period = period;
 921                 ret = 1;
 922         }
 923         /*
 924          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
 925          */
 926         if (unlikely(left < 2))
 927                 left = 2;
 928
 929         if (left > x86_pmu.max_period)
 930                 left = x86_pmu.max_period;
 931
 932         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 933
 934         /*
 935          * The hw event starts counting from this event offset,
 936          * mark it to be able to extra future deltas:
 937          */
 938         local64_set(&hwc->prev_count, (u64)-left);
 939
 940         wrmsrl(hwc->event_base + idx, (u64)(-left) & x86_pmu.cntval_mask);
 941
 942         /*
 943          * Due to erratum on certan cpu we need
 944          * a second write to be sure the register
 945          * is updated properly
 946          */
 947         if (x86_pmu.perfctr_second_write) {
 948                 wrmsrl(hwc->event_base + idx,
 949                         (u64)(-left) & x86_pmu.cntval_mask);
 950         }
 951
 952         perf_event_update_userpage(event);
 953
 954         return ret;
 955 }
 956
 957 static void x86_pmu_enable_event(struct perf_event *event)
 958 {
 959         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 960         if (cpuc->enabled)
 961                 __x86_pmu_enable_event(&event->hw,
 962                                        ARCH_PERFMON_EVENTSEL_ENABLE);
 963 }
 964
 965 /*
 966  * Add a single event to the PMU.
 967  *
 968  * The event is added to the group of enabled events
 969  * but only if it can be scehduled with existing events.
 970  */
 971 static int x86_pmu_add(struct perf_event *event, int flags)
 972 {
 973         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 974         struct hw_perf_event *hwc;
 975         int assign[X86_PMC_IDX_MAX];
 976         int n, n0, ret;
 977
 978         hwc = &event->hw;
 979
 980         perf_pmu_disable(event->pmu);
 981         n0 = cpuc->n_events;
 982         ret = n = collect_events(cpuc, event, false);
 983         if (ret < 0)
 984                 goto out;
 985
 986         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
 987         if (!(flags & PERF_EF_START))
 988                 hwc->state |= PERF_HES_ARCH;
 989
 990         /*
 991          * If group events scheduling transaction was started,
 992          * skip the schedulability test here, it will be peformed
 993          * at commit time (->commit_txn) as a whole
 994          */
 995         if (cpuc->group_flag & PERF_EVENT_TXN)
 996                 goto done_collect;
 997
 998         ret = x86_pmu.schedule_events(cpuc, n, assign);
 999         if (ret)
1000                 goto out;
1001         /*
1002          * copy new assignment, now we know it is possible
1003          * will be used by hw_perf_enable()
1004          */
1005         memcpy(cpuc->assign, assign, n*sizeof(int));
1006
1007 done_collect:
1008         cpuc->n_events = n;
1009         cpuc->n_added += n - n0;
1010         cpuc->n_txn += n - n0;
1011
1012         ret = 0;
1013 out:
1014         perf_pmu_enable(event->pmu);
1015         return ret;
1016 }
1017
1018 static void x86_pmu_start(struct perf_event *event, int flags)
1019 {
1020         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1021         int idx = event->hw.idx;
1022
1023         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1024                 return;
1025
1026         if (WARN_ON_ONCE(idx == -1))
1027                 return;
1028
1029         if (flags & PERF_EF_RELOAD) {
1030                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1031                 x86_perf_event_set_period(event);
1032         }
1033
1034         event->hw.state = 0;
1035
1036         cpuc->events[idx] = event;
1037         __set_bit(idx, cpuc->active_mask);
1038         __set_bit(idx, cpuc->running);
1039         x86_pmu.enable(event);
1040         perf_event_update_userpage(event);
1041 }
1042
1043 void perf_event_print_debug(void)
1044 {
1045         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1046         u64 pebs;
1047         struct cpu_hw_events *cpuc;
1048         unsigned long flags;
1049         int cpu, idx;
1050
1051         if (!x86_pmu.num_counters)
1052                 return;
1053
1054         local_irq_save(flags);
1055
1056         cpu = smp_processor_id();
1057         cpuc = &per_cpu(cpu_hw_events, cpu);
1058
1059         if (x86_pmu.version >= 2) {
1060                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1061                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1062                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1063                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1064                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1065
1066                 pr_info("\n");
1067                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1068                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1069                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1070                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1071                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1072         }
1073         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1074
1075         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1076                 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1077                 rdmsrl(x86_pmu.perfctr  + idx, pmc_count);
1078
1079                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1080
1081                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1082                         cpu, idx, pmc_ctrl);
1083                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1084                         cpu, idx, pmc_count);
1085                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1086                         cpu, idx, prev_left);
1087         }
1088         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1089                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1090
1091                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1092                         cpu, idx, pmc_count);
1093         }
1094         local_irq_restore(flags);
1095 }
1096
1097 static void x86_pmu_stop(struct perf_event *event, int flags)
1098 {
1099         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1100         struct hw_perf_event *hwc = &event->hw;
1101
1102         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1103                 x86_pmu.disable(event);
1104                 cpuc->events[hwc->idx] = NULL;
1105                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1106                 hwc->state |= PERF_HES_STOPPED;
1107         }
1108
1109         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1110                 /*
1111                  * Drain the remaining delta count out of a event
1112                  * that we are disabling:
1113                  */
1114                 x86_perf_event_update(event);
1115                 hwc->state |= PERF_HES_UPTODATE;
1116         }
1117 }
1118
1119 static void x86_pmu_del(struct perf_event *event, int flags)
1120 {
1121         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1122         int i;
1123
1124         /*
1125          * If we're called during a txn, we don't need to do anything.
1126          * The events never got scheduled and ->cancel_txn will truncate
1127          * the event_list.
1128          */
1129         if (cpuc->group_flag & PERF_EVENT_TXN)
1130                 return;
1131
1132         x86_pmu_stop(event, PERF_EF_UPDATE);
1133
1134         for (i = 0; i < cpuc->n_events; i++) {
1135                 if (event == cpuc->event_list[i]) {
1136
1137                         if (x86_pmu.put_event_constraints)
1138                                 x86_pmu.put_event_constraints(cpuc, event);
1139
1140                         while (++i < cpuc->n_events)
1141                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1142
1143                         --cpuc->n_events;
1144                         break;
1145                 }
1146         }
1147         perf_event_update_userpage(event);
1148 }
1149
1150 static int x86_pmu_handle_irq(struct pt_regs *regs)
1151 {
1152         struct perf_sample_data data;
1153         struct cpu_hw_events *cpuc;
1154         struct perf_event *event;
1155         int idx, handled = 0;
1156         u64 val;
1157
1158         perf_sample_data_init(&data, 0);
1159
1160         cpuc = &__get_cpu_var(cpu_hw_events);
1161
1162         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1163                 if (!test_bit(idx, cpuc->active_mask)) {
1164                         /*
1165                          * Though we deactivated the counter some cpus
1166                          * might still deliver spurious interrupts still
1167                          * in flight. Catch them:
1168                          */
1169                         if (__test_and_clear_bit(idx, cpuc->running))
1170                                 handled++;
1171                         continue;
1172                 }
1173
1174                 event = cpuc->events[idx];
1175
1176                 val = x86_perf_event_update(event);
1177                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1178                         continue;
1179
1180                 /*
1181                  * event overflow
1182                  */
1183                 handled++;
1184                 data.period     = event->hw.last_period;
1185
1186                 if (!x86_perf_event_set_period(event))
1187                         continue;
1188
1189                 if (perf_event_overflow(event, 1, &data, regs))
1190                         x86_pmu_stop(event, 0);
1191         }
1192
1193         if (handled)
1194                 inc_irq_stat(apic_perf_irqs);
1195
1196         return handled;
1197 }
1198
1199 void smp_perf_pending_interrupt(struct pt_regs *regs)
1200 {
1201         irq_enter();
1202         ack_APIC_irq();
1203         inc_irq_stat(apic_pending_irqs);
1204         perf_event_do_pending();
1205         irq_exit();
1206 }
1207
1208 void set_perf_event_pending(void)
1209 {
1210 #ifdef CONFIG_X86_LOCAL_APIC
1211         if (!x86_pmu.apic || !x86_pmu_initialized())
1212                 return;
1213
1214         apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1215 #endif
1216 }
1217
1218 void perf_events_lapic_init(void)
1219 {
1220         if (!x86_pmu.apic || !x86_pmu_initialized())
1221                 return;
1222
1223         /*
1224          * Always use NMI for PMU
1225          */
1226         apic_write(APIC_LVTPC, APIC_DM_NMI);
1227 }
1228
1229 struct pmu_nmi_state {
1230         unsigned int    marked;
1231         int             handled;
1232 };
1233
1234 static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi);
1235
1236 static int __kprobes
1237 perf_event_nmi_handler(struct notifier_block *self,
1238                          unsigned long cmd, void *__args)
1239 {
1240         struct die_args *args = __args;
1241         unsigned int this_nmi;
1242         int handled;
1243
1244         if (!atomic_read(&active_events))
1245                 return NOTIFY_DONE;
1246
1247         switch (cmd) {
1248         case DIE_NMI:
1249         case DIE_NMI_IPI:
1250                 break;
1251         case DIE_NMIUNKNOWN:
1252                 this_nmi = percpu_read(irq_stat.__nmi_count);
1253                 if (this_nmi != __get_cpu_var(pmu_nmi).marked)
1254                         /* let the kernel handle the unknown nmi */
1255                         return NOTIFY_DONE;
1256                 /*
1257                  * This one is a PMU back-to-back nmi. Two events
1258                  * trigger 'simultaneously' raising two back-to-back
1259                  * NMIs. If the first NMI handles both, the latter
1260                  * will be empty and daze the CPU. So, we drop it to
1261                  * avoid false-positive 'unknown nmi' messages.
1262                  */
1263                 return NOTIFY_STOP;
1264         default:
1265                 return NOTIFY_DONE;
1266         }
1267
1268         apic_write(APIC_LVTPC, APIC_DM_NMI);
1269
1270         handled = x86_pmu.handle_irq(args->regs);
1271         if (!handled)
1272                 return NOTIFY_DONE;
1273
1274         this_nmi = percpu_read(irq_stat.__nmi_count);
1275         if ((handled > 1) ||
1276                 /* the next nmi could be a back-to-back nmi */
1277             ((__get_cpu_var(pmu_nmi).marked == this_nmi) &&
1278              (__get_cpu_var(pmu_nmi).handled > 1))) {
1279                 /*
1280                  * We could have two subsequent back-to-back nmis: The
1281                  * first handles more than one counter, the 2nd
1282                  * handles only one counter and the 3rd handles no
1283                  * counter.
1284                  *
1285                  * This is the 2nd nmi because the previous was
1286                  * handling more than one counter. We will mark the
1287                  * next (3rd) and then drop it if unhandled.
1288                  */
1289                 __get_cpu_var(pmu_nmi).marked   = this_nmi + 1;
1290                 __get_cpu_var(pmu_nmi).handled  = handled;
1291         }
1292
1293         return NOTIFY_STOP;
1294 }
1295
1296 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1297         .notifier_call          = perf_event_nmi_handler,
1298         .next                   = NULL,
1299         .priority               = 1
1300 };
1301
1302 static struct event_constraint unconstrained;
1303 static struct event_constraint emptyconstraint;
1304
1305 static struct event_constraint *
1306 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1307 {
1308         struct event_constraint *c;
1309
1310         if (x86_pmu.event_constraints) {
1311                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1312                         if ((event->hw.config & c->cmask) == c->code)
1313                                 return c;
1314                 }
1315         }
1316
1317         return &unconstrained;
1318 }
1319
1320 #include "perf_event_amd.c"
1321 #include "perf_event_p6.c"
1322 #include "perf_event_p4.c"
1323 #include "perf_event_intel_lbr.c"
1324 #include "perf_event_intel_ds.c"
1325 #include "perf_event_intel.c"
1326
1327 static int __cpuinit
1328 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1329 {
1330         unsigned int cpu = (long)hcpu;
1331         int ret = NOTIFY_OK;
1332
1333         switch (action & ~CPU_TASKS_FROZEN) {
1334         case CPU_UP_PREPARE:
1335                 if (x86_pmu.cpu_prepare)
1336                         ret = x86_pmu.cpu_prepare(cpu);
1337                 break;
1338
1339         case CPU_STARTING:
1340                 if (x86_pmu.cpu_starting)
1341                         x86_pmu.cpu_starting(cpu);
1342                 break;
1343
1344         case CPU_DYING:
1345                 if (x86_pmu.cpu_dying)
1346                         x86_pmu.cpu_dying(cpu);
1347                 break;
1348
1349         case CPU_UP_CANCELED:
1350         case CPU_DEAD:
1351                 if (x86_pmu.cpu_dead)
1352                         x86_pmu.cpu_dead(cpu);
1353                 break;
1354
1355         default:
1356                 break;
1357         }
1358
1359         return ret;
1360 }
1361
1362 static void __init pmu_check_apic(void)
1363 {
1364         if (cpu_has_apic)
1365                 return;
1366
1367         x86_pmu.apic = 0;
1368         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1369         pr_info("no hardware sampling interrupt available.\n");
1370 }
1371
1372 void __init init_hw_perf_events(void)
1373 {
1374         struct event_constraint *c;
1375         int err;
1376
1377         pr_info("Performance Events: ");
1378
1379         switch (boot_cpu_data.x86_vendor) {
1380         case X86_VENDOR_INTEL:
1381                 err = intel_pmu_init();
1382                 break;
1383         case X86_VENDOR_AMD:
1384                 err = amd_pmu_init();
1385                 break;
1386         default:
1387                 return;
1388         }
1389         if (err != 0) {
1390                 pr_cont("no PMU driver, software events only.\n");
1391                 return;
1392         }
1393
1394         pmu_check_apic();
1395
1396         pr_cont("%s PMU driver.\n", x86_pmu.name);
1397
1398         if (x86_pmu.quirks)
1399                 x86_pmu.quirks();
1400
1401         if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1402                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1403                      x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1404                 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1405         }
1406         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1407
1408         if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1409                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1410                      x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1411                 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1412         }
1413
1414         x86_pmu.intel_ctrl |=
1415                 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1416
1417         perf_events_lapic_init();
1418         register_die_notifier(&perf_event_nmi_notifier);
1419
1420         unconstrained = (struct event_constraint)
1421                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1422                                    0, x86_pmu.num_counters);
1423
1424         if (x86_pmu.event_constraints) {
1425                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1426                         if (c->cmask != X86_RAW_EVENT_MASK)
1427                                 continue;
1428
1429                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1430                         c->weight += x86_pmu.num_counters;
1431                 }
1432         }
1433
1434         pr_info("... version:                %d\n",     x86_pmu.version);
1435         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1436         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1437         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1438         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1439         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1440         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1441
1442         perf_pmu_register(&pmu);
1443         perf_cpu_notifier(x86_pmu_notifier);
1444 }
1445
1446 static inline void x86_pmu_read(struct perf_event *event)
1447 {
1448         x86_perf_event_update(event);
1449 }
1450
1451 /*
1452  * Start group events scheduling transaction
1453  * Set the flag to make pmu::enable() not perform the
1454  * schedulability test, it will be performed at commit time
1455  */
1456 static void x86_pmu_start_txn(struct pmu *pmu)
1457 {
1458         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1459
1460         perf_pmu_disable(pmu);
1461         cpuc->group_flag |= PERF_EVENT_TXN;
1462         cpuc->n_txn = 0;
1463 }
1464
1465 /*
1466  * Stop group events scheduling transaction
1467  * Clear the flag and pmu::enable() will perform the
1468  * schedulability test.
1469  */
1470 static void x86_pmu_cancel_txn(struct pmu *pmu)
1471 {
1472         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1473
1474         cpuc->group_flag &= ~PERF_EVENT_TXN;
1475         /*
1476          * Truncate the collected events.
1477          */
1478         cpuc->n_added -= cpuc->n_txn;
1479         cpuc->n_events -= cpuc->n_txn;
1480         perf_pmu_enable(pmu);
1481 }
1482
1483 /*
1484  * Commit group events scheduling transaction
1485  * Perform the group schedulability test as a whole
1486  * Return 0 if success
1487  */
1488 static int x86_pmu_commit_txn(struct pmu *pmu)
1489 {
1490         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1491         int assign[X86_PMC_IDX_MAX];
1492         int n, ret;
1493
1494         n = cpuc->n_events;
1495
1496         if (!x86_pmu_initialized())
1497                 return -EAGAIN;
1498
1499         ret = x86_pmu.schedule_events(cpuc, n, assign);
1500         if (ret)
1501                 return ret;
1502
1503         /*
1504          * copy new assignment, now we know it is possible
1505          * will be used by hw_perf_enable()
1506          */
1507         memcpy(cpuc->assign, assign, n*sizeof(int));
1508
1509         cpuc->group_flag &= ~PERF_EVENT_TXN;
1510         perf_pmu_enable(pmu);
1511         return 0;
1512 }
1513
1514 /*
1515  * validate that we can schedule this event
1516  */
1517 static int validate_event(struct perf_event *event)
1518 {
1519         struct cpu_hw_events *fake_cpuc;
1520         struct event_constraint *c;
1521         int ret = 0;
1522
1523         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1524         if (!fake_cpuc)
1525                 return -ENOMEM;
1526
1527         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1528
1529         if (!c || !c->weight)
1530                 ret = -ENOSPC;
1531
1532         if (x86_pmu.put_event_constraints)
1533                 x86_pmu.put_event_constraints(fake_cpuc, event);
1534
1535         kfree(fake_cpuc);
1536
1537         return ret;
1538 }
1539
1540 /*
1541  * validate a single event group
1542  *
1543  * validation include:
1544  *      - check events are compatible which each other
1545  *      - events do not compete for the same counter
1546  *      - number of events <= number of counters
1547  *
1548  * validation ensures the group can be loaded onto the
1549  * PMU if it was the only group available.
1550  */
1551 static int validate_group(struct perf_event *event)
1552 {
1553         struct perf_event *leader = event->group_leader;
1554         struct cpu_hw_events *fake_cpuc;
1555         int ret, n;
1556
1557         ret = -ENOMEM;
1558         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1559         if (!fake_cpuc)
1560                 goto out;
1561
1562         /*
1563          * the event is not yet connected with its
1564          * siblings therefore we must first collect
1565          * existing siblings, then add the new event
1566          * before we can simulate the scheduling
1567          */
1568         ret = -ENOSPC;
1569         n = collect_events(fake_cpuc, leader, true);
1570         if (n < 0)
1571                 goto out_free;
1572
1573         fake_cpuc->n_events = n;
1574         n = collect_events(fake_cpuc, event, false);
1575         if (n < 0)
1576                 goto out_free;
1577
1578         fake_cpuc->n_events = n;
1579
1580         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1581
1582 out_free:
1583         kfree(fake_cpuc);
1584 out:
1585         return ret;
1586 }
1587
1588 int x86_pmu_event_init(struct perf_event *event)
1589 {
1590         struct pmu *tmp;
1591         int err;
1592
1593         switch (event->attr.type) {
1594         case PERF_TYPE_RAW:
1595         case PERF_TYPE_HARDWARE:
1596         case PERF_TYPE_HW_CACHE:
1597                 break;
1598
1599         default:
1600                 return -ENOENT;
1601         }
1602
1603         err = __x86_pmu_event_init(event);
1604         if (!err) {
1605                 /*
1606                  * we temporarily connect event to its pmu
1607                  * such that validate_group() can classify
1608                  * it as an x86 event using is_x86_event()
1609                  */
1610                 tmp = event->pmu;
1611                 event->pmu = &pmu;
1612
1613                 if (event->group_leader != event)
1614                         err = validate_group(event);
1615                 else
1616                         err = validate_event(event);
1617
1618                 event->pmu = tmp;
1619         }
1620         if (err) {
1621                 if (event->destroy)
1622                         event->destroy(event);
1623         }
1624
1625         return err;
1626 }
1627
1628 static struct pmu pmu = {
1629         .pmu_enable     = x86_pmu_enable,
1630         .pmu_disable    = x86_pmu_disable,
1631
1632         .event_init     = x86_pmu_event_init,
1633
1634         .add            = x86_pmu_add,
1635         .del            = x86_pmu_del,
1636         .start          = x86_pmu_start,
1637         .stop           = x86_pmu_stop,
1638         .read           = x86_pmu_read,
1639
1640         .start_txn      = x86_pmu_start_txn,
1641         .cancel_txn     = x86_pmu_cancel_txn,
1642         .commit_txn     = x86_pmu_commit_txn,
1643 };
1644
1645 /*
1646  * callchain support
1647  */
1648
1649 static void
1650 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1651 {
1652         /* Ignore warnings */
1653 }
1654
1655 static void backtrace_warning(void *data, char *msg)
1656 {
1657         /* Ignore warnings */
1658 }
1659
1660 static int backtrace_stack(void *data, char *name)
1661 {
1662         return 0;
1663 }
1664
1665 static void backtrace_address(void *data, unsigned long addr, int reliable)
1666 {
1667         struct perf_callchain_entry *entry = data;
1668
1669         perf_callchain_store(entry, addr);
1670 }
1671
1672 static const struct stacktrace_ops backtrace_ops = {
1673         .warning                = backtrace_warning,
1674         .warning_symbol         = backtrace_warning_symbol,
1675         .stack                  = backtrace_stack,
1676         .address                = backtrace_address,
1677         .walk_stack             = print_context_stack_bp,
1678 };
1679
1680 void
1681 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1682 {
1683         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1684                 /* TODO: We don't support guest os callchain now */
1685                 return;
1686         }
1687
1688         perf_callchain_store(entry, regs->ip);
1689
1690         dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
1691 }
1692
1693 #ifdef CONFIG_COMPAT
1694 static inline int
1695 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1696 {
1697         /* 32-bit process in 64-bit kernel. */
1698         struct stack_frame_ia32 frame;
1699         const void __user *fp;
1700
1701         if (!test_thread_flag(TIF_IA32))
1702                 return 0;
1703
1704         fp = compat_ptr(regs->bp);
1705         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1706                 unsigned long bytes;
1707                 frame.next_frame     = 0;
1708                 frame.return_address = 0;
1709
1710                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1711                 if (bytes != sizeof(frame))
1712                         break;
1713
1714                 if (fp < compat_ptr(regs->sp))
1715                         break;
1716
1717                 perf_callchain_store(entry, frame.return_address);
1718                 fp = compat_ptr(frame.next_frame);
1719         }
1720         return 1;
1721 }
1722 #else
1723 static inline int
1724 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1725 {
1726     return 0;
1727 }
1728 #endif
1729
1730 void
1731 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1732 {
1733         struct stack_frame frame;
1734         const void __user *fp;
1735
1736         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1737                 /* TODO: We don't support guest os callchain now */
1738                 return;
1739         }
1740
1741         fp = (void __user *)regs->bp;
1742
1743         perf_callchain_store(entry, regs->ip);
1744
1745         if (perf_callchain_user32(regs, entry))
1746                 return;
1747
1748         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1749                 unsigned long bytes;
1750                 frame.next_frame             = NULL;
1751                 frame.return_address = 0;
1752
1753                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1754                 if (bytes != sizeof(frame))
1755                         break;
1756
1757                 if ((unsigned long)fp < regs->sp)
1758                         break;
1759
1760                 perf_callchain_store(entry, frame.return_address);
1761                 fp = frame.next_frame;
1762         }
1763 }
1764
1765 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1766 {
1767         unsigned long ip;
1768
1769         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1770                 ip = perf_guest_cbs->get_guest_ip();
1771         else
1772                 ip = instruction_pointer(regs);
1773
1774         return ip;
1775 }
1776
1777 unsigned long perf_misc_flags(struct pt_regs *regs)
1778 {
1779         int misc = 0;
1780
1781         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1782                 if (perf_guest_cbs->is_user_mode())
1783                         misc |= PERF_RECORD_MISC_GUEST_USER;
1784                 else
1785                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1786         } else {
1787                 if (user_mode(regs))
1788                         misc |= PERF_RECORD_MISC_USER;
1789                 else
1790                         misc |= PERF_RECORD_MISC_KERNEL;
1791         }
1792
1793         if (regs->flags & PERF_EFLAGS_EXACT)
1794                 misc |= PERF_RECORD_MISC_EXACT_IP;
1795
1796         return misc;
1797 }