1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include <linux/sysrq.h>
30 #include <linux/slab.h>
35 #include "i915_trace.h"
36 #include "intel_drv.h"
38 #define MAX_NOPID ((u32)~0)
41 * Interrupts that are always left unmasked.
43 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
44 * we leave them always unmasked in IMR and then control enabling them through
47 #define I915_INTERRUPT_ENABLE_FIX \
48 (I915_ASLE_INTERRUPT | \
49 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
50 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
51 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
52 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
53 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
55 /** Interrupts that we mask and unmask at runtime. */
56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
59 PIPE_VBLANK_INTERRUPT_STATUS)
61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
62 PIPE_VBLANK_INTERRUPT_ENABLE)
64 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
65 DRM_I915_VBLANK_PIPE_B)
67 /* For display hotplug interrupt */
69 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
71 if ((dev_priv->irq_mask & mask) != 0) {
72 dev_priv->irq_mask &= ~mask;
73 I915_WRITE(DEIMR, dev_priv->irq_mask);
79 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
81 if ((dev_priv->irq_mask & mask) != mask) {
82 dev_priv->irq_mask |= mask;
83 I915_WRITE(DEIMR, dev_priv->irq_mask);
89 i915_pipestat(int pipe)
99 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
101 if ((dev_priv->pipestat[pipe] & mask) != mask) {
102 u32 reg = i915_pipestat(pipe);
104 dev_priv->pipestat[pipe] |= mask;
105 /* Enable the interrupt, clear any pending status */
106 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
112 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
114 if ((dev_priv->pipestat[pipe] & mask) != 0) {
115 u32 reg = i915_pipestat(pipe);
117 dev_priv->pipestat[pipe] &= ~mask;
118 I915_WRITE(reg, dev_priv->pipestat[pipe]);
124 * intel_enable_asle - enable ASLE interrupt for OpRegion
126 void intel_enable_asle(struct drm_device *dev)
128 drm_i915_private_t *dev_priv = dev->dev_private;
129 unsigned long irqflags;
131 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
133 if (HAS_PCH_SPLIT(dev))
134 ironlake_enable_display_irq(dev_priv, DE_GSE);
136 i915_enable_pipestat(dev_priv, 1,
137 PIPE_LEGACY_BLC_EVENT_ENABLE);
138 if (INTEL_INFO(dev)->gen >= 4)
139 i915_enable_pipestat(dev_priv, 0,
140 PIPE_LEGACY_BLC_EVENT_ENABLE);
143 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
147 * i915_pipe_enabled - check if a pipe is enabled
149 * @pipe: pipe to check
151 * Reading certain registers when the pipe is disabled can hang the chip.
152 * Use this routine to make sure the PLL is running and the pipe is active
153 * before reading such registers if unsure.
156 i915_pipe_enabled(struct drm_device *dev, int pipe)
158 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
159 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
162 /* Called from drm generic code, passed a 'crtc', which
163 * we use as a pipe index
165 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
167 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
168 unsigned long high_frame;
169 unsigned long low_frame;
170 u32 high1, high2, low;
172 if (!i915_pipe_enabled(dev, pipe)) {
173 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
178 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
179 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
182 * High & low register fields aren't synchronized, so make sure
183 * we get a low value that's stable across two reads of the high
187 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
188 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
189 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
190 } while (high1 != high2);
192 high1 >>= PIPE_FRAME_HIGH_SHIFT;
193 low >>= PIPE_FRAME_LOW_SHIFT;
194 return (high1 << 8) | low;
197 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
199 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
200 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
202 if (!i915_pipe_enabled(dev, pipe)) {
203 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
208 return I915_READ(reg);
211 int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
212 int *vpos, int *hpos)
214 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
215 u32 vbl = 0, position = 0;
216 int vbl_start, vbl_end, htotal, vtotal;
220 if (!i915_pipe_enabled(dev, pipe)) {
221 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
227 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
229 if (INTEL_INFO(dev)->gen >= 4) {
230 /* No obvious pixelcount register. Only query vertical
231 * scanout position from Display scan line register.
233 position = I915_READ(PIPEDSL(pipe));
235 /* Decode into vertical scanout position. Don't have
236 * horizontal scanout position.
238 *vpos = position & 0x1fff;
241 /* Have access to pixelcount since start of frame.
242 * We can split this into vertical and horizontal
245 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
247 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
248 *vpos = position / htotal;
249 *hpos = position - (*vpos * htotal);
252 /* Query vblank area. */
253 vbl = I915_READ(VBLANK(pipe));
255 /* Test position against vblank region. */
256 vbl_start = vbl & 0x1fff;
257 vbl_end = (vbl >> 16) & 0x1fff;
259 if ((*vpos < vbl_start) || (*vpos > vbl_end))
262 /* Inside "upper part" of vblank area? Apply corrective offset: */
263 if (in_vbl && (*vpos >= vbl_start))
264 *vpos = *vpos - vtotal;
266 /* Readouts valid? */
268 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
272 ret |= DRM_SCANOUTPOS_INVBL;
277 int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
279 struct timeval *vblank_time,
282 struct drm_i915_private *dev_priv = dev->dev_private;
283 struct drm_crtc *crtc;
285 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
286 DRM_ERROR("Invalid crtc %d\n", pipe);
290 /* Get drm_crtc to timestamp: */
291 crtc = intel_get_crtc_for_pipe(dev, pipe);
293 DRM_ERROR("Invalid crtc %d\n", pipe);
297 if (!crtc->enabled) {
298 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
302 /* Helper routine in DRM core does all the work: */
303 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
309 * Handle hotplug events outside the interrupt handler proper.
311 static void i915_hotplug_work_func(struct work_struct *work)
313 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
315 struct drm_device *dev = dev_priv->dev;
316 struct drm_mode_config *mode_config = &dev->mode_config;
317 struct intel_encoder *encoder;
319 DRM_DEBUG_KMS("running encoder hotplug functions\n");
321 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
322 if (encoder->hot_plug)
323 encoder->hot_plug(encoder);
325 /* Just fire off a uevent and let userspace tell us what to do */
326 drm_helper_hpd_irq_event(dev);
329 static void i915_handle_rps_change(struct drm_device *dev)
331 drm_i915_private_t *dev_priv = dev->dev_private;
332 u32 busy_up, busy_down, max_avg, min_avg;
333 u8 new_delay = dev_priv->cur_delay;
335 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
336 busy_up = I915_READ(RCPREVBSYTUPAVG);
337 busy_down = I915_READ(RCPREVBSYTDNAVG);
338 max_avg = I915_READ(RCBMAXAVG);
339 min_avg = I915_READ(RCBMINAVG);
341 /* Handle RCS change request from hw */
342 if (busy_up > max_avg) {
343 if (dev_priv->cur_delay != dev_priv->max_delay)
344 new_delay = dev_priv->cur_delay - 1;
345 if (new_delay < dev_priv->max_delay)
346 new_delay = dev_priv->max_delay;
347 } else if (busy_down < min_avg) {
348 if (dev_priv->cur_delay != dev_priv->min_delay)
349 new_delay = dev_priv->cur_delay + 1;
350 if (new_delay > dev_priv->min_delay)
351 new_delay = dev_priv->min_delay;
354 if (ironlake_set_drps(dev, new_delay))
355 dev_priv->cur_delay = new_delay;
360 static void notify_ring(struct drm_device *dev,
361 struct intel_ring_buffer *ring)
363 struct drm_i915_private *dev_priv = dev->dev_private;
366 if (ring->obj == NULL)
369 seqno = ring->get_seqno(ring);
370 trace_i915_gem_request_complete(dev, seqno);
372 ring->irq_seqno = seqno;
373 wake_up_all(&ring->irq_queue);
375 dev_priv->hangcheck_count = 0;
376 mod_timer(&dev_priv->hangcheck_timer,
377 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
380 static void gen6_pm_irq_handler(struct drm_device *dev)
382 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
383 u8 new_delay = dev_priv->cur_delay;
386 pm_iir = I915_READ(GEN6_PMIIR);
390 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
391 if (dev_priv->cur_delay != dev_priv->max_delay)
392 new_delay = dev_priv->cur_delay + 1;
393 if (new_delay > dev_priv->max_delay)
394 new_delay = dev_priv->max_delay;
395 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
396 if (dev_priv->cur_delay != dev_priv->min_delay)
397 new_delay = dev_priv->cur_delay - 1;
398 if (new_delay < dev_priv->min_delay) {
399 new_delay = dev_priv->min_delay;
400 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
401 I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
402 ((new_delay << 16) & 0x3f0000));
404 /* Make sure we continue to get down interrupts
405 * until we hit the minimum frequency */
406 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
407 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
412 gen6_set_rps(dev, new_delay);
413 dev_priv->cur_delay = new_delay;
415 I915_WRITE(GEN6_PMIIR, pm_iir);
418 static void pch_irq_handler(struct drm_device *dev)
420 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
423 pch_iir = I915_READ(SDEIIR);
425 if (pch_iir & SDE_AUDIO_POWER_MASK)
426 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
427 (pch_iir & SDE_AUDIO_POWER_MASK) >>
428 SDE_AUDIO_POWER_SHIFT);
430 if (pch_iir & SDE_GMBUS)
431 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
433 if (pch_iir & SDE_AUDIO_HDCP_MASK)
434 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
436 if (pch_iir & SDE_AUDIO_TRANS_MASK)
437 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
439 if (pch_iir & SDE_POISON)
440 DRM_ERROR("PCH poison interrupt\n");
442 if (pch_iir & SDE_FDI_MASK) {
445 fdia = I915_READ(FDI_RXA_IIR);
446 fdib = I915_READ(FDI_RXB_IIR);
447 DRM_DEBUG_DRIVER("PCH FDI RX interrupt; FDI RXA IIR: 0x%08x, FDI RXB IIR: 0x%08x\n", fdia, fdib);
450 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
451 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
453 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
454 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
456 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
457 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
458 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
459 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
462 static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
464 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
466 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
468 struct drm_i915_master_private *master_priv;
469 u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
472 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
474 /* disable master interrupt before clearing iir */
475 de_ier = I915_READ(DEIER);
476 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
479 de_iir = I915_READ(DEIIR);
480 gt_iir = I915_READ(GTIIR);
481 pch_iir = I915_READ(SDEIIR);
482 pm_iir = I915_READ(GEN6_PMIIR);
484 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
485 (!IS_GEN6(dev) || pm_iir == 0))
488 if (HAS_PCH_CPT(dev))
489 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
491 hotplug_mask = SDE_HOTPLUG_MASK;
495 if (dev->primary->master) {
496 master_priv = dev->primary->master->driver_priv;
497 if (master_priv->sarea_priv)
498 master_priv->sarea_priv->last_dispatch =
499 READ_BREADCRUMB(dev_priv);
502 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
503 notify_ring(dev, &dev_priv->ring[RCS]);
504 if (gt_iir & bsd_usr_interrupt)
505 notify_ring(dev, &dev_priv->ring[VCS]);
506 if (gt_iir & GT_BLT_USER_INTERRUPT)
507 notify_ring(dev, &dev_priv->ring[BCS]);
510 intel_opregion_gse_intr(dev);
512 if (de_iir & DE_PLANEA_FLIP_DONE) {
513 intel_prepare_page_flip(dev, 0);
514 intel_finish_page_flip_plane(dev, 0);
517 if (de_iir & DE_PLANEB_FLIP_DONE) {
518 intel_prepare_page_flip(dev, 1);
519 intel_finish_page_flip_plane(dev, 1);
522 if (de_iir & DE_PIPEA_VBLANK)
523 drm_handle_vblank(dev, 0);
525 if (de_iir & DE_PIPEB_VBLANK)
526 drm_handle_vblank(dev, 1);
528 /* check event from PCH */
529 if (de_iir & DE_PCH_EVENT) {
530 if (pch_iir & hotplug_mask)
531 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
532 pch_irq_handler(dev);
535 if (de_iir & DE_PCU_EVENT) {
536 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
537 i915_handle_rps_change(dev);
541 gen6_pm_irq_handler(dev);
543 /* should clear PCH hotplug event before clear CPU irq */
544 I915_WRITE(SDEIIR, pch_iir);
545 I915_WRITE(GTIIR, gt_iir);
546 I915_WRITE(DEIIR, de_iir);
549 I915_WRITE(DEIER, de_ier);
556 * i915_error_work_func - do process context error handling work
559 * Fire an error uevent so userspace can see that a hang or error
562 static void i915_error_work_func(struct work_struct *work)
564 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
566 struct drm_device *dev = dev_priv->dev;
567 char *error_event[] = { "ERROR=1", NULL };
568 char *reset_event[] = { "RESET=1", NULL };
569 char *reset_done_event[] = { "ERROR=0", NULL };
571 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
573 if (atomic_read(&dev_priv->mm.wedged)) {
574 DRM_DEBUG_DRIVER("resetting chip\n");
575 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
576 if (!i915_reset(dev, GRDOM_RENDER)) {
577 atomic_set(&dev_priv->mm.wedged, 0);
578 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
580 complete_all(&dev_priv->error_completion);
584 #ifdef CONFIG_DEBUG_FS
585 static struct drm_i915_error_object *
586 i915_error_object_create(struct drm_i915_private *dev_priv,
587 struct drm_i915_gem_object *src)
589 struct drm_i915_error_object *dst;
590 int page, page_count;
593 if (src == NULL || src->pages == NULL)
596 page_count = src->base.size / PAGE_SIZE;
598 dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
602 reloc_offset = src->gtt_offset;
603 for (page = 0; page < page_count; page++) {
608 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
612 local_irq_save(flags);
613 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
615 memcpy_fromio(d, s, PAGE_SIZE);
616 io_mapping_unmap_atomic(s);
617 local_irq_restore(flags);
619 dst->pages[page] = d;
621 reloc_offset += PAGE_SIZE;
623 dst->page_count = page_count;
624 dst->gtt_offset = src->gtt_offset;
630 kfree(dst->pages[page]);
636 i915_error_object_free(struct drm_i915_error_object *obj)
643 for (page = 0; page < obj->page_count; page++)
644 kfree(obj->pages[page]);
650 i915_error_state_free(struct drm_device *dev,
651 struct drm_i915_error_state *error)
653 i915_error_object_free(error->batchbuffer[0]);
654 i915_error_object_free(error->batchbuffer[1]);
655 i915_error_object_free(error->ringbuffer);
656 kfree(error->active_bo);
657 kfree(error->overlay);
661 static u32 capture_bo_list(struct drm_i915_error_buffer *err,
663 struct list_head *head)
665 struct drm_i915_gem_object *obj;
668 list_for_each_entry(obj, head, mm_list) {
669 err->size = obj->base.size;
670 err->name = obj->base.name;
671 err->seqno = obj->last_rendering_seqno;
672 err->gtt_offset = obj->gtt_offset;
673 err->read_domains = obj->base.read_domains;
674 err->write_domain = obj->base.write_domain;
675 err->fence_reg = obj->fence_reg;
677 if (obj->pin_count > 0)
679 if (obj->user_pin_count > 0)
681 err->tiling = obj->tiling_mode;
682 err->dirty = obj->dirty;
683 err->purgeable = obj->madv != I915_MADV_WILLNEED;
684 err->ring = obj->ring ? obj->ring->id : 0;
685 err->agp_type = obj->agp_type == AGP_USER_CACHED_MEMORY;
696 static void i915_gem_record_fences(struct drm_device *dev,
697 struct drm_i915_error_state *error)
699 struct drm_i915_private *dev_priv = dev->dev_private;
703 switch (INTEL_INFO(dev)->gen) {
705 for (i = 0; i < 16; i++)
706 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
710 for (i = 0; i < 16; i++)
711 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
714 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
715 for (i = 0; i < 8; i++)
716 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
718 for (i = 0; i < 8; i++)
719 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
725 static struct drm_i915_error_object *
726 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
727 struct intel_ring_buffer *ring)
729 struct drm_i915_gem_object *obj;
732 if (!ring->get_seqno)
735 seqno = ring->get_seqno(ring);
736 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
737 if (obj->ring != ring)
740 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
743 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
746 /* We need to copy these to an anonymous buffer as the simplest
747 * method to avoid being overwritten by userspace.
749 return i915_error_object_create(dev_priv, obj);
756 * i915_capture_error_state - capture an error record for later analysis
759 * Should be called when an error is detected (either a hang or an error
760 * interrupt) to capture error state from the time of the error. Fills
761 * out a structure which becomes available in debugfs for user level tools
764 static void i915_capture_error_state(struct drm_device *dev)
766 struct drm_i915_private *dev_priv = dev->dev_private;
767 struct drm_i915_gem_object *obj;
768 struct drm_i915_error_state *error;
772 spin_lock_irqsave(&dev_priv->error_lock, flags);
773 error = dev_priv->first_error;
774 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
778 error = kmalloc(sizeof(*error), GFP_ATOMIC);
780 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
784 DRM_DEBUG_DRIVER("generating error event\n");
786 error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]);
787 error->eir = I915_READ(EIR);
788 error->pgtbl_er = I915_READ(PGTBL_ER);
789 error->pipeastat = I915_READ(PIPEASTAT);
790 error->pipebstat = I915_READ(PIPEBSTAT);
791 error->instpm = I915_READ(INSTPM);
793 if (INTEL_INFO(dev)->gen >= 6) {
794 error->error = I915_READ(ERROR_GEN6);
796 error->bcs_acthd = I915_READ(BCS_ACTHD);
797 error->bcs_ipehr = I915_READ(BCS_IPEHR);
798 error->bcs_ipeir = I915_READ(BCS_IPEIR);
799 error->bcs_instdone = I915_READ(BCS_INSTDONE);
800 error->bcs_seqno = 0;
801 if (dev_priv->ring[BCS].get_seqno)
802 error->bcs_seqno = dev_priv->ring[BCS].get_seqno(&dev_priv->ring[BCS]);
804 error->vcs_acthd = I915_READ(VCS_ACTHD);
805 error->vcs_ipehr = I915_READ(VCS_IPEHR);
806 error->vcs_ipeir = I915_READ(VCS_IPEIR);
807 error->vcs_instdone = I915_READ(VCS_INSTDONE);
808 error->vcs_seqno = 0;
809 if (dev_priv->ring[VCS].get_seqno)
810 error->vcs_seqno = dev_priv->ring[VCS].get_seqno(&dev_priv->ring[VCS]);
812 if (INTEL_INFO(dev)->gen >= 4) {
813 error->ipeir = I915_READ(IPEIR_I965);
814 error->ipehr = I915_READ(IPEHR_I965);
815 error->instdone = I915_READ(INSTDONE_I965);
816 error->instps = I915_READ(INSTPS);
817 error->instdone1 = I915_READ(INSTDONE1);
818 error->acthd = I915_READ(ACTHD_I965);
819 error->bbaddr = I915_READ64(BB_ADDR);
821 error->ipeir = I915_READ(IPEIR);
822 error->ipehr = I915_READ(IPEHR);
823 error->instdone = I915_READ(INSTDONE);
824 error->acthd = I915_READ(ACTHD);
827 i915_gem_record_fences(dev, error);
829 /* Record the active batchbuffers */
830 for (i = 0; i < I915_NUM_RINGS; i++)
831 error->batchbuffer[i] =
832 i915_error_first_batchbuffer(dev_priv,
835 /* Record the ringbuffer */
836 error->ringbuffer = i915_error_object_create(dev_priv,
837 dev_priv->ring[RCS].obj);
839 /* Record buffers on the active and pinned lists. */
840 error->active_bo = NULL;
841 error->pinned_bo = NULL;
844 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
846 error->active_bo_count = i;
847 list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
849 error->pinned_bo_count = i - error->active_bo_count;
851 error->active_bo = NULL;
852 error->pinned_bo = NULL;
854 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
856 if (error->active_bo)
858 error->active_bo + error->active_bo_count;
861 if (error->active_bo)
862 error->active_bo_count =
863 capture_bo_list(error->active_bo,
864 error->active_bo_count,
865 &dev_priv->mm.active_list);
867 if (error->pinned_bo)
868 error->pinned_bo_count =
869 capture_bo_list(error->pinned_bo,
870 error->pinned_bo_count,
871 &dev_priv->mm.pinned_list);
873 do_gettimeofday(&error->time);
875 error->overlay = intel_overlay_capture_error_state(dev);
876 error->display = intel_display_capture_error_state(dev);
878 spin_lock_irqsave(&dev_priv->error_lock, flags);
879 if (dev_priv->first_error == NULL) {
880 dev_priv->first_error = error;
883 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
886 i915_error_state_free(dev, error);
889 void i915_destroy_error_state(struct drm_device *dev)
891 struct drm_i915_private *dev_priv = dev->dev_private;
892 struct drm_i915_error_state *error;
894 spin_lock(&dev_priv->error_lock);
895 error = dev_priv->first_error;
896 dev_priv->first_error = NULL;
897 spin_unlock(&dev_priv->error_lock);
900 i915_error_state_free(dev, error);
903 #define i915_capture_error_state(x)
906 static void i915_report_and_clear_eir(struct drm_device *dev)
908 struct drm_i915_private *dev_priv = dev->dev_private;
909 u32 eir = I915_READ(EIR);
914 printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
918 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
919 u32 ipeir = I915_READ(IPEIR_I965);
921 printk(KERN_ERR " IPEIR: 0x%08x\n",
922 I915_READ(IPEIR_I965));
923 printk(KERN_ERR " IPEHR: 0x%08x\n",
924 I915_READ(IPEHR_I965));
925 printk(KERN_ERR " INSTDONE: 0x%08x\n",
926 I915_READ(INSTDONE_I965));
927 printk(KERN_ERR " INSTPS: 0x%08x\n",
929 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
930 I915_READ(INSTDONE1));
931 printk(KERN_ERR " ACTHD: 0x%08x\n",
932 I915_READ(ACTHD_I965));
933 I915_WRITE(IPEIR_I965, ipeir);
934 POSTING_READ(IPEIR_I965);
936 if (eir & GM45_ERROR_PAGE_TABLE) {
937 u32 pgtbl_err = I915_READ(PGTBL_ER);
938 printk(KERN_ERR "page table error\n");
939 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
941 I915_WRITE(PGTBL_ER, pgtbl_err);
942 POSTING_READ(PGTBL_ER);
947 if (eir & I915_ERROR_PAGE_TABLE) {
948 u32 pgtbl_err = I915_READ(PGTBL_ER);
949 printk(KERN_ERR "page table error\n");
950 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
952 I915_WRITE(PGTBL_ER, pgtbl_err);
953 POSTING_READ(PGTBL_ER);
957 if (eir & I915_ERROR_MEMORY_REFRESH) {
958 u32 pipea_stats = I915_READ(PIPEASTAT);
959 u32 pipeb_stats = I915_READ(PIPEBSTAT);
961 printk(KERN_ERR "memory refresh error\n");
962 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
964 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
966 /* pipestat has already been acked */
968 if (eir & I915_ERROR_INSTRUCTION) {
969 printk(KERN_ERR "instruction error\n");
970 printk(KERN_ERR " INSTPM: 0x%08x\n",
972 if (INTEL_INFO(dev)->gen < 4) {
973 u32 ipeir = I915_READ(IPEIR);
975 printk(KERN_ERR " IPEIR: 0x%08x\n",
977 printk(KERN_ERR " IPEHR: 0x%08x\n",
979 printk(KERN_ERR " INSTDONE: 0x%08x\n",
980 I915_READ(INSTDONE));
981 printk(KERN_ERR " ACTHD: 0x%08x\n",
983 I915_WRITE(IPEIR, ipeir);
986 u32 ipeir = I915_READ(IPEIR_I965);
988 printk(KERN_ERR " IPEIR: 0x%08x\n",
989 I915_READ(IPEIR_I965));
990 printk(KERN_ERR " IPEHR: 0x%08x\n",
991 I915_READ(IPEHR_I965));
992 printk(KERN_ERR " INSTDONE: 0x%08x\n",
993 I915_READ(INSTDONE_I965));
994 printk(KERN_ERR " INSTPS: 0x%08x\n",
996 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
997 I915_READ(INSTDONE1));
998 printk(KERN_ERR " ACTHD: 0x%08x\n",
999 I915_READ(ACTHD_I965));
1000 I915_WRITE(IPEIR_I965, ipeir);
1001 POSTING_READ(IPEIR_I965);
1005 I915_WRITE(EIR, eir);
1007 eir = I915_READ(EIR);
1010 * some errors might have become stuck,
1013 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1014 I915_WRITE(EMR, I915_READ(EMR) | eir);
1015 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1020 * i915_handle_error - handle an error interrupt
1023 * Do some basic checking of regsiter state at error interrupt time and
1024 * dump it to the syslog. Also call i915_capture_error_state() to make
1025 * sure we get a record and make it available in debugfs. Fire a uevent
1026 * so userspace knows something bad happened (should trigger collection
1027 * of a ring dump etc.).
1029 void i915_handle_error(struct drm_device *dev, bool wedged)
1031 struct drm_i915_private *dev_priv = dev->dev_private;
1033 i915_capture_error_state(dev);
1034 i915_report_and_clear_eir(dev);
1037 INIT_COMPLETION(dev_priv->error_completion);
1038 atomic_set(&dev_priv->mm.wedged, 1);
1041 * Wakeup waiting processes so they don't hang
1043 wake_up_all(&dev_priv->ring[RCS].irq_queue);
1045 wake_up_all(&dev_priv->ring[VCS].irq_queue);
1047 wake_up_all(&dev_priv->ring[BCS].irq_queue);
1050 queue_work(dev_priv->wq, &dev_priv->error_work);
1053 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1055 drm_i915_private_t *dev_priv = dev->dev_private;
1056 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1058 struct drm_i915_gem_object *obj;
1059 struct intel_unpin_work *work;
1060 unsigned long flags;
1061 bool stall_detected;
1063 /* Ignore early vblank irqs */
1064 if (intel_crtc == NULL)
1067 spin_lock_irqsave(&dev->event_lock, flags);
1068 work = intel_crtc->unpin_work;
1070 if (work == NULL || work->pending || !work->enable_stall_check) {
1071 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1072 spin_unlock_irqrestore(&dev->event_lock, flags);
1076 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1077 obj = work->pending_flip_obj;
1078 if (INTEL_INFO(dev)->gen >= 4) {
1079 int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
1080 stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
1082 int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
1083 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1084 crtc->y * crtc->fb->pitch +
1085 crtc->x * crtc->fb->bits_per_pixel/8);
1088 spin_unlock_irqrestore(&dev->event_lock, flags);
1090 if (stall_detected) {
1091 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1092 intel_prepare_page_flip(dev, intel_crtc->plane);
1096 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1098 struct drm_device *dev = (struct drm_device *) arg;
1099 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1100 struct drm_i915_master_private *master_priv;
1102 u32 pipea_stats, pipeb_stats;
1105 unsigned long irqflags;
1109 atomic_inc(&dev_priv->irq_received);
1111 if (HAS_PCH_SPLIT(dev))
1112 return ironlake_irq_handler(dev);
1114 iir = I915_READ(IIR);
1116 if (INTEL_INFO(dev)->gen >= 4)
1117 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
1119 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
1122 irq_received = iir != 0;
1124 /* Can't rely on pipestat interrupt bit in iir as it might
1125 * have been cleared after the pipestat interrupt was received.
1126 * It doesn't set the bit in iir again, but it still produces
1127 * interrupts (for non-MSI).
1129 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1130 pipea_stats = I915_READ(PIPEASTAT);
1131 pipeb_stats = I915_READ(PIPEBSTAT);
1133 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
1134 i915_handle_error(dev, false);
1137 * Clear the PIPE(A|B)STAT regs before the IIR
1139 if (pipea_stats & 0x8000ffff) {
1140 if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS)
1141 DRM_DEBUG_DRIVER("pipe a underrun\n");
1142 I915_WRITE(PIPEASTAT, pipea_stats);
1146 if (pipeb_stats & 0x8000ffff) {
1147 if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS)
1148 DRM_DEBUG_DRIVER("pipe b underrun\n");
1149 I915_WRITE(PIPEBSTAT, pipeb_stats);
1152 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1159 /* Consume port. Then clear IIR or we'll miss events */
1160 if ((I915_HAS_HOTPLUG(dev)) &&
1161 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1162 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1164 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1166 if (hotplug_status & dev_priv->hotplug_supported_mask)
1167 queue_work(dev_priv->wq,
1168 &dev_priv->hotplug_work);
1170 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1171 I915_READ(PORT_HOTPLUG_STAT);
1174 I915_WRITE(IIR, iir);
1175 new_iir = I915_READ(IIR); /* Flush posted writes */
1177 if (dev->primary->master) {
1178 master_priv = dev->primary->master->driver_priv;
1179 if (master_priv->sarea_priv)
1180 master_priv->sarea_priv->last_dispatch =
1181 READ_BREADCRUMB(dev_priv);
1184 if (iir & I915_USER_INTERRUPT)
1185 notify_ring(dev, &dev_priv->ring[RCS]);
1186 if (iir & I915_BSD_USER_INTERRUPT)
1187 notify_ring(dev, &dev_priv->ring[VCS]);
1189 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1190 intel_prepare_page_flip(dev, 0);
1191 if (dev_priv->flip_pending_is_done)
1192 intel_finish_page_flip_plane(dev, 0);
1195 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1196 intel_prepare_page_flip(dev, 1);
1197 if (dev_priv->flip_pending_is_done)
1198 intel_finish_page_flip_plane(dev, 1);
1201 if (pipea_stats & vblank_status &&
1202 drm_handle_vblank(dev, 0)) {
1204 if (!dev_priv->flip_pending_is_done) {
1205 i915_pageflip_stall_check(dev, 0);
1206 intel_finish_page_flip(dev, 0);
1210 if (pipeb_stats & vblank_status &&
1211 drm_handle_vblank(dev, 1)) {
1213 if (!dev_priv->flip_pending_is_done) {
1214 i915_pageflip_stall_check(dev, 1);
1215 intel_finish_page_flip(dev, 1);
1219 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1220 (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1221 (iir & I915_ASLE_INTERRUPT))
1222 intel_opregion_asle_intr(dev);
1224 /* With MSI, interrupts are only generated when iir
1225 * transitions from zero to nonzero. If another bit got
1226 * set while we were handling the existing iir bits, then
1227 * we would never get another interrupt.
1229 * This is fine on non-MSI as well, as if we hit this path
1230 * we avoid exiting the interrupt handler only to generate
1233 * Note that for MSI this could cause a stray interrupt report
1234 * if an interrupt landed in the time between writing IIR and
1235 * the posting read. This should be rare enough to never
1236 * trigger the 99% of 100,000 interrupts test for disabling
1245 static int i915_emit_irq(struct drm_device * dev)
1247 drm_i915_private_t *dev_priv = dev->dev_private;
1248 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1250 i915_kernel_lost_context(dev);
1252 DRM_DEBUG_DRIVER("\n");
1254 dev_priv->counter++;
1255 if (dev_priv->counter > 0x7FFFFFFFUL)
1256 dev_priv->counter = 1;
1257 if (master_priv->sarea_priv)
1258 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1260 if (BEGIN_LP_RING(4) == 0) {
1261 OUT_RING(MI_STORE_DWORD_INDEX);
1262 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1263 OUT_RING(dev_priv->counter);
1264 OUT_RING(MI_USER_INTERRUPT);
1268 return dev_priv->counter;
1271 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1273 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1274 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1276 if (dev_priv->trace_irq_seqno == 0 &&
1277 ring->irq_get(ring))
1278 dev_priv->trace_irq_seqno = seqno;
1281 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1283 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1284 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1286 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1288 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1289 READ_BREADCRUMB(dev_priv));
1291 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1292 if (master_priv->sarea_priv)
1293 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1297 if (master_priv->sarea_priv)
1298 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1300 if (ring->irq_get(ring)) {
1301 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
1302 READ_BREADCRUMB(dev_priv) >= irq_nr);
1303 ring->irq_put(ring);
1304 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
1307 if (ret == -EBUSY) {
1308 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1309 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1315 /* Needs the lock as it touches the ring.
1317 int i915_irq_emit(struct drm_device *dev, void *data,
1318 struct drm_file *file_priv)
1320 drm_i915_private_t *dev_priv = dev->dev_private;
1321 drm_i915_irq_emit_t *emit = data;
1324 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
1325 DRM_ERROR("called with no initialization\n");
1329 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1331 mutex_lock(&dev->struct_mutex);
1332 result = i915_emit_irq(dev);
1333 mutex_unlock(&dev->struct_mutex);
1335 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1336 DRM_ERROR("copy_to_user\n");
1343 /* Doesn't need the hardware lock.
1345 int i915_irq_wait(struct drm_device *dev, void *data,
1346 struct drm_file *file_priv)
1348 drm_i915_private_t *dev_priv = dev->dev_private;
1349 drm_i915_irq_wait_t *irqwait = data;
1352 DRM_ERROR("called with no initialization\n");
1356 return i915_wait_irq(dev, irqwait->irq_seq);
1359 /* Called from drm generic code, passed 'crtc' which
1360 * we use as a pipe index
1362 int i915_enable_vblank(struct drm_device *dev, int pipe)
1364 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1365 unsigned long irqflags;
1367 if (!i915_pipe_enabled(dev, pipe))
1370 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1371 if (HAS_PCH_SPLIT(dev))
1372 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1373 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1374 else if (INTEL_INFO(dev)->gen >= 4)
1375 i915_enable_pipestat(dev_priv, pipe,
1376 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1378 i915_enable_pipestat(dev_priv, pipe,
1379 PIPE_VBLANK_INTERRUPT_ENABLE);
1380 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1384 /* Called from drm generic code, passed 'crtc' which
1385 * we use as a pipe index
1387 void i915_disable_vblank(struct drm_device *dev, int pipe)
1389 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1390 unsigned long irqflags;
1392 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1393 if (HAS_PCH_SPLIT(dev))
1394 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1395 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1397 i915_disable_pipestat(dev_priv, pipe,
1398 PIPE_VBLANK_INTERRUPT_ENABLE |
1399 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1400 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1403 void i915_enable_interrupt (struct drm_device *dev)
1405 struct drm_i915_private *dev_priv = dev->dev_private;
1407 if (!HAS_PCH_SPLIT(dev))
1408 intel_opregion_enable_asle(dev);
1409 dev_priv->irq_enabled = 1;
1413 /* Set the vblank monitor pipe
1415 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1416 struct drm_file *file_priv)
1418 drm_i915_private_t *dev_priv = dev->dev_private;
1421 DRM_ERROR("called with no initialization\n");
1428 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1429 struct drm_file *file_priv)
1431 drm_i915_private_t *dev_priv = dev->dev_private;
1432 drm_i915_vblank_pipe_t *pipe = data;
1435 DRM_ERROR("called with no initialization\n");
1439 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1445 * Schedule buffer swap at given vertical blank.
1447 int i915_vblank_swap(struct drm_device *dev, void *data,
1448 struct drm_file *file_priv)
1450 /* The delayed swap mechanism was fundamentally racy, and has been
1451 * removed. The model was that the client requested a delayed flip/swap
1452 * from the kernel, then waited for vblank before continuing to perform
1453 * rendering. The problem was that the kernel might wake the client
1454 * up before it dispatched the vblank swap (since the lock has to be
1455 * held while touching the ringbuffer), in which case the client would
1456 * clear and start the next frame before the swap occurred, and
1457 * flicker would occur in addition to likely missing the vblank.
1459 * In the absence of this ioctl, userland falls back to a correct path
1460 * of waiting for a vblank, then dispatching the swap on its own.
1461 * Context switching to userland and back is plenty fast enough for
1462 * meeting the requirements of vblank swapping.
1468 ring_last_seqno(struct intel_ring_buffer *ring)
1470 return list_entry(ring->request_list.prev,
1471 struct drm_i915_gem_request, list)->seqno;
1474 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1476 if (list_empty(&ring->request_list) ||
1477 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1478 /* Issue a wake-up to catch stuck h/w. */
1479 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
1480 DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1482 ring->waiting_seqno,
1483 ring->get_seqno(ring));
1484 wake_up_all(&ring->irq_queue);
1492 static bool kick_ring(struct intel_ring_buffer *ring)
1494 struct drm_device *dev = ring->dev;
1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496 u32 tmp = I915_READ_CTL(ring);
1497 if (tmp & RING_WAIT) {
1498 DRM_ERROR("Kicking stuck wait on %s\n",
1500 I915_WRITE_CTL(ring, tmp);
1504 (tmp & RING_WAIT_SEMAPHORE)) {
1505 DRM_ERROR("Kicking stuck semaphore on %s\n",
1507 I915_WRITE_CTL(ring, tmp);
1514 * This is called when the chip hasn't reported back with completed
1515 * batchbuffers in a long time. The first time this is called we simply record
1516 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1517 * again, we assume the chip is wedged and try to fix it.
1519 void i915_hangcheck_elapsed(unsigned long data)
1521 struct drm_device *dev = (struct drm_device *)data;
1522 drm_i915_private_t *dev_priv = dev->dev_private;
1523 uint32_t acthd, instdone, instdone1;
1526 /* If all work is done then ACTHD clearly hasn't advanced. */
1527 if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1528 i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1529 i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
1530 dev_priv->hangcheck_count = 0;
1536 if (INTEL_INFO(dev)->gen < 4) {
1537 acthd = I915_READ(ACTHD);
1538 instdone = I915_READ(INSTDONE);
1541 acthd = I915_READ(ACTHD_I965);
1542 instdone = I915_READ(INSTDONE_I965);
1543 instdone1 = I915_READ(INSTDONE1);
1546 if (dev_priv->last_acthd == acthd &&
1547 dev_priv->last_instdone == instdone &&
1548 dev_priv->last_instdone1 == instdone1) {
1549 if (dev_priv->hangcheck_count++ > 1) {
1550 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1552 if (!IS_GEN2(dev)) {
1553 /* Is the chip hanging on a WAIT_FOR_EVENT?
1554 * If so we can simply poke the RB_WAIT bit
1555 * and break the hang. This should work on
1556 * all but the second generation chipsets.
1559 if (kick_ring(&dev_priv->ring[RCS]))
1563 kick_ring(&dev_priv->ring[VCS]))
1567 kick_ring(&dev_priv->ring[BCS]))
1571 i915_handle_error(dev, true);
1575 dev_priv->hangcheck_count = 0;
1577 dev_priv->last_acthd = acthd;
1578 dev_priv->last_instdone = instdone;
1579 dev_priv->last_instdone1 = instdone1;
1583 /* Reset timer case chip hangs without another request being added */
1584 mod_timer(&dev_priv->hangcheck_timer,
1585 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1590 static void ironlake_irq_preinstall(struct drm_device *dev)
1592 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1594 I915_WRITE(HWSTAM, 0xeffe);
1596 /* XXX hotplug from PCH */
1598 I915_WRITE(DEIMR, 0xffffffff);
1599 I915_WRITE(DEIER, 0x0);
1600 POSTING_READ(DEIER);
1603 I915_WRITE(GTIMR, 0xffffffff);
1604 I915_WRITE(GTIER, 0x0);
1605 POSTING_READ(GTIER);
1607 /* south display irq */
1608 I915_WRITE(SDEIMR, 0xffffffff);
1609 I915_WRITE(SDEIER, 0x0);
1610 POSTING_READ(SDEIER);
1613 static int ironlake_irq_postinstall(struct drm_device *dev)
1615 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1616 /* enable kind of interrupts always enabled */
1617 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1618 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1622 dev_priv->irq_mask = ~display_mask;
1624 /* should always can generate irq */
1625 I915_WRITE(DEIIR, I915_READ(DEIIR));
1626 I915_WRITE(DEIMR, dev_priv->irq_mask);
1627 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1628 POSTING_READ(DEIER);
1630 dev_priv->gt_irq_mask = ~0;
1632 I915_WRITE(GTIIR, I915_READ(GTIIR));
1633 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1638 GT_GEN6_BSD_USER_INTERRUPT |
1639 GT_BLT_USER_INTERRUPT;
1644 GT_BSD_USER_INTERRUPT;
1645 I915_WRITE(GTIER, render_irqs);
1646 POSTING_READ(GTIER);
1648 if (HAS_PCH_CPT(dev)) {
1649 hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT |
1650 SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ;
1652 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1653 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1654 hotplug_mask |= SDE_AUX_MASK;
1657 dev_priv->pch_irq_mask = ~hotplug_mask;
1659 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1660 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1661 I915_WRITE(SDEIER, hotplug_mask);
1662 POSTING_READ(SDEIER);
1664 if (IS_IRONLAKE_M(dev)) {
1665 /* Clear & enable PCU event interrupts */
1666 I915_WRITE(DEIIR, DE_PCU_EVENT);
1667 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1668 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1674 void i915_driver_irq_preinstall(struct drm_device * dev)
1676 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1678 atomic_set(&dev_priv->irq_received, 0);
1680 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1681 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1683 if (HAS_PCH_SPLIT(dev)) {
1684 ironlake_irq_preinstall(dev);
1688 if (I915_HAS_HOTPLUG(dev)) {
1689 I915_WRITE(PORT_HOTPLUG_EN, 0);
1690 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1693 I915_WRITE(HWSTAM, 0xeffe);
1694 I915_WRITE(PIPEASTAT, 0);
1695 I915_WRITE(PIPEBSTAT, 0);
1696 I915_WRITE(IMR, 0xffffffff);
1697 I915_WRITE(IER, 0x0);
1702 * Must be called after intel_modeset_init or hotplug interrupts won't be
1703 * enabled correctly.
1705 int i915_driver_irq_postinstall(struct drm_device *dev)
1707 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1708 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1711 DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1713 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1715 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1717 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1719 if (HAS_PCH_SPLIT(dev))
1720 return ironlake_irq_postinstall(dev);
1722 /* Unmask the interrupts that we always want on. */
1723 dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
1725 dev_priv->pipestat[0] = 0;
1726 dev_priv->pipestat[1] = 0;
1728 if (I915_HAS_HOTPLUG(dev)) {
1729 /* Enable in IER... */
1730 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1731 /* and unmask in IMR */
1732 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
1736 * Enable some error detection, note the instruction error mask
1737 * bit is reserved, so we leave it masked.
1740 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1741 GM45_ERROR_MEM_PRIV |
1742 GM45_ERROR_CP_PRIV |
1743 I915_ERROR_MEMORY_REFRESH);
1745 error_mask = ~(I915_ERROR_PAGE_TABLE |
1746 I915_ERROR_MEMORY_REFRESH);
1748 I915_WRITE(EMR, error_mask);
1750 I915_WRITE(IMR, dev_priv->irq_mask);
1751 I915_WRITE(IER, enable_mask);
1754 if (I915_HAS_HOTPLUG(dev)) {
1755 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1757 /* Note HDMI and DP share bits */
1758 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1759 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1760 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1761 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1762 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1763 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1764 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1765 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1766 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1767 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1768 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1769 hotplug_en |= CRT_HOTPLUG_INT_EN;
1771 /* Programming the CRT detection parameters tends
1772 to generate a spurious hotplug event about three
1773 seconds later. So just do it once.
1776 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1777 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1780 /* Ignore TV since it's buggy */
1782 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1785 intel_opregion_enable_asle(dev);
1790 static void ironlake_irq_uninstall(struct drm_device *dev)
1792 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1793 I915_WRITE(HWSTAM, 0xffffffff);
1795 I915_WRITE(DEIMR, 0xffffffff);
1796 I915_WRITE(DEIER, 0x0);
1797 I915_WRITE(DEIIR, I915_READ(DEIIR));
1799 I915_WRITE(GTIMR, 0xffffffff);
1800 I915_WRITE(GTIER, 0x0);
1801 I915_WRITE(GTIIR, I915_READ(GTIIR));
1804 void i915_driver_irq_uninstall(struct drm_device * dev)
1806 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1811 dev_priv->vblank_pipe = 0;
1813 if (HAS_PCH_SPLIT(dev)) {
1814 ironlake_irq_uninstall(dev);
1818 if (I915_HAS_HOTPLUG(dev)) {
1819 I915_WRITE(PORT_HOTPLUG_EN, 0);
1820 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1823 I915_WRITE(HWSTAM, 0xffffffff);
1824 I915_WRITE(PIPEASTAT, 0);
1825 I915_WRITE(PIPEBSTAT, 0);
1826 I915_WRITE(IMR, 0xffffffff);
1827 I915_WRITE(IER, 0x0);
1829 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1830 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1831 I915_WRITE(IIR, I915_READ(IIR));