drivers/gpu/drm/radeon/evergreen_blit_kms.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *     Alex Deucher <alexander.deucher@amd.com>
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "radeon_drm.h"
  30 #include "radeon.h"
  31
  32 #include "evergreend.h"
  33 #include "evergreen_blit_shaders.h"
  34
  35 #define DI_PT_RECTLIST        0x11
  36 #define DI_INDEX_SIZE_16_BIT  0x0
  37 #define DI_SRC_SEL_AUTO_INDEX 0x2
  38
  39 #define FMT_8                 0x1
  40 #define FMT_5_6_5             0x8
  41 #define FMT_8_8_8_8           0x1a
  42 #define COLOR_8               0x1
  43 #define COLOR_5_6_5           0x8
  44 #define COLOR_8_8_8_8         0x1a
  45
  46 /* emits 17 */
  47 static void
  48 set_render_target(struct radeon_device *rdev, int format,
  49                   int w, int h, u64 gpu_addr)
  50 {
  51         u32 cb_color_info;
  52         int pitch, slice;
  53
  54         h = ALIGN(h, 8);
  55         if (h < 8)
  56                 h = 8;
  57
  58         cb_color_info = ((format << 2) | (1 << 24));
  59         pitch = (w / 8) - 1;
  60         slice = ((w * h) / 64) - 1;
  61
  62         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 15));
  63         radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2);
  64         radeon_ring_write(rdev, gpu_addr >> 8);
  65         radeon_ring_write(rdev, pitch);
  66         radeon_ring_write(rdev, slice);
  67         radeon_ring_write(rdev, 0);
  68         radeon_ring_write(rdev, cb_color_info);
  69         radeon_ring_write(rdev, (1 << 4));
  70         radeon_ring_write(rdev, (w - 1) | ((h - 1) << 16));
  71         radeon_ring_write(rdev, 0);
  72         radeon_ring_write(rdev, 0);
  73         radeon_ring_write(rdev, 0);
  74         radeon_ring_write(rdev, 0);
  75         radeon_ring_write(rdev, 0);
  76         radeon_ring_write(rdev, 0);
  77         radeon_ring_write(rdev, 0);
  78         radeon_ring_write(rdev, 0);
  79 }
  80
  81 /* emits 5dw */
  82 static void
  83 cp_set_surface_sync(struct radeon_device *rdev,
  84                     u32 sync_type, u32 size,
  85                     u64 mc_addr)
  86 {
  87         u32 cp_coher_size;
  88
  89         if (size == 0xffffffff)
  90                 cp_coher_size = 0xffffffff;
  91         else
  92                 cp_coher_size = ((size + 255) >> 8);
  93
  94         radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
  95         radeon_ring_write(rdev, sync_type);
  96         radeon_ring_write(rdev, cp_coher_size);
  97         radeon_ring_write(rdev, mc_addr >> 8);
  98         radeon_ring_write(rdev, 10); /* poll interval */
  99 }
 100
 101 /* emits 11dw + 1 surface sync = 16dw */
 102 static void
 103 set_shaders(struct radeon_device *rdev)
 104 {
 105         u64 gpu_addr;
 106
 107         /* VS */
 108         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
 109         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 3));
 110         radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2);
 111         radeon_ring_write(rdev, gpu_addr >> 8);
 112         radeon_ring_write(rdev, 2);
 113         radeon_ring_write(rdev, 0);
 114
 115         /* PS */
 116         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
 117         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 4));
 118         radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2);
 119         radeon_ring_write(rdev, gpu_addr >> 8);
 120         radeon_ring_write(rdev, 1);
 121         radeon_ring_write(rdev, 0);
 122         radeon_ring_write(rdev, 2);
 123
 124         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
 125         cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
 126 }
 127
 128 /* emits 10 + 1 sync (5) = 15 */
 129 static void
 130 set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
 131 {
 132         u32 sq_vtx_constant_word2, sq_vtx_constant_word3;
 133
 134         /* high addr, stride */
 135         sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8));
 136         /* xyzw swizzles */
 137         sq_vtx_constant_word3 = (0 << 3) | (1 << 6) | (2 << 9) | (3 << 12);
 138
 139         radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8));
 140         radeon_ring_write(rdev, 0x580);
 141         radeon_ring_write(rdev, gpu_addr & 0xffffffff);
 142         radeon_ring_write(rdev, 48 - 1); /* size */
 143         radeon_ring_write(rdev, sq_vtx_constant_word2);
 144         radeon_ring_write(rdev, sq_vtx_constant_word3);
 145         radeon_ring_write(rdev, 0);
 146         radeon_ring_write(rdev, 0);
 147         radeon_ring_write(rdev, 0);
 148         radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
 149
 150         if ((rdev->family == CHIP_CEDAR) ||
 151             (rdev->family == CHIP_PALM) ||
 152             (rdev->family == CHIP_CAICOS))
 153                 cp_set_surface_sync(rdev,
 154                                     PACKET3_TC_ACTION_ENA, 48, gpu_addr);
 155         else
 156                 cp_set_surface_sync(rdev,
 157                                     PACKET3_VC_ACTION_ENA, 48, gpu_addr);
 158
 159 }
 160
 161 /* emits 10 */
 162 static void
 163 set_tex_resource(struct radeon_device *rdev,
 164                  int format, int w, int h, int pitch,
 165                  u64 gpu_addr)
 166 {
 167         u32 sq_tex_resource_word0, sq_tex_resource_word1;
 168         u32 sq_tex_resource_word4, sq_tex_resource_word7;
 169
 170         if (h < 1)
 171                 h = 1;
 172
 173         sq_tex_resource_word0 = (1 << 0); /* 2D */
 174         sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 6) |
 175                                   ((w - 1) << 18));
 176         sq_tex_resource_word1 = ((h - 1) << 0);
 177         /* xyzw swizzles */
 178         sq_tex_resource_word4 = (0 << 16) | (1 << 19) | (2 << 22) | (3 << 25);
 179
 180         sq_tex_resource_word7 = format | (SQ_TEX_VTX_VALID_TEXTURE << 30);
 181
 182         radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8));
 183         radeon_ring_write(rdev, 0);
 184         radeon_ring_write(rdev, sq_tex_resource_word0);
 185         radeon_ring_write(rdev, sq_tex_resource_word1);
 186         radeon_ring_write(rdev, gpu_addr >> 8);
 187         radeon_ring_write(rdev, gpu_addr >> 8);
 188         radeon_ring_write(rdev, sq_tex_resource_word4);
 189         radeon_ring_write(rdev, 0);
 190         radeon_ring_write(rdev, 0);
 191         radeon_ring_write(rdev, sq_tex_resource_word7);
 192 }
 193
 194 /* emits 12 */
 195 static void
 196 set_scissors(struct radeon_device *rdev, int x1, int y1,
 197              int x2, int y2)
 198 {
 199         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 200         radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
 201         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
 202         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 203
 204         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 205         radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
 206         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
 207         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 208
 209         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 210         radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
 211         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
 212         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 213 }
 214
 215 /* emits 10 */
 216 static void
 217 draw_auto(struct radeon_device *rdev)
 218 {
 219         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 220         radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2);
 221         radeon_ring_write(rdev, DI_PT_RECTLIST);
 222
 223         radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));
 224         radeon_ring_write(rdev, DI_INDEX_SIZE_16_BIT);
 225
 226         radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));
 227         radeon_ring_write(rdev, 1);
 228
 229         radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
 230         radeon_ring_write(rdev, 3);
 231         radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
 232
 233 }
 234
 235 /* emits 30 */
 236 static void
 237 set_default_state(struct radeon_device *rdev)
 238 {
 239         u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3;
 240         u32 sq_thread_resource_mgmt, sq_thread_resource_mgmt_2;
 241         u32 sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3;
 242         int num_ps_gprs, num_vs_gprs, num_temp_gprs;
 243         int num_gs_gprs, num_es_gprs, num_hs_gprs, num_ls_gprs;
 244         int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
 245         int num_hs_threads, num_ls_threads;
 246         int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
 247         int num_hs_stack_entries, num_ls_stack_entries;
 248
 249         switch (rdev->family) {
 250         case CHIP_CEDAR:
 251         default:
 252                 num_ps_gprs = 93;
 253                 num_vs_gprs = 46;
 254                 num_temp_gprs = 4;
 255                 num_gs_gprs = 31;
 256                 num_es_gprs = 31;
 257                 num_hs_gprs = 23;
 258                 num_ls_gprs = 23;
 259                 num_ps_threads = 96;
 260                 num_vs_threads = 16;
 261                 num_gs_threads = 16;
 262                 num_es_threads = 16;
 263                 num_hs_threads = 16;
 264                 num_ls_threads = 16;
 265                 num_ps_stack_entries = 42;
 266                 num_vs_stack_entries = 42;
 267                 num_gs_stack_entries = 42;
 268                 num_es_stack_entries = 42;
 269                 num_hs_stack_entries = 42;
 270                 num_ls_stack_entries = 42;
 271                 break;
 272         case CHIP_REDWOOD:
 273                 num_ps_gprs = 93;
 274                 num_vs_gprs = 46;
 275                 num_temp_gprs = 4;
 276                 num_gs_gprs = 31;
 277                 num_es_gprs = 31;
 278                 num_hs_gprs = 23;
 279                 num_ls_gprs = 23;
 280                 num_ps_threads = 128;
 281                 num_vs_threads = 20;
 282                 num_gs_threads = 20;
 283                 num_es_threads = 20;
 284                 num_hs_threads = 20;
 285                 num_ls_threads = 20;
 286                 num_ps_stack_entries = 42;
 287                 num_vs_stack_entries = 42;
 288                 num_gs_stack_entries = 42;
 289                 num_es_stack_entries = 42;
 290                 num_hs_stack_entries = 42;
 291                 num_ls_stack_entries = 42;
 292                 break;
 293         case CHIP_JUNIPER:
 294                 num_ps_gprs = 93;
 295                 num_vs_gprs = 46;
 296                 num_temp_gprs = 4;
 297                 num_gs_gprs = 31;
 298                 num_es_gprs = 31;
 299                 num_hs_gprs = 23;
 300                 num_ls_gprs = 23;
 301                 num_ps_threads = 128;
 302                 num_vs_threads = 20;
 303                 num_gs_threads = 20;
 304                 num_es_threads = 20;
 305                 num_hs_threads = 20;
 306                 num_ls_threads = 20;
 307                 num_ps_stack_entries = 85;
 308                 num_vs_stack_entries = 85;
 309                 num_gs_stack_entries = 85;
 310                 num_es_stack_entries = 85;
 311                 num_hs_stack_entries = 85;
 312                 num_ls_stack_entries = 85;
 313                 break;
 314         case CHIP_CYPRESS:
 315         case CHIP_HEMLOCK:
 316                 num_ps_gprs = 93;
 317                 num_vs_gprs = 46;
 318                 num_temp_gprs = 4;
 319                 num_gs_gprs = 31;
 320                 num_es_gprs = 31;
 321                 num_hs_gprs = 23;
 322                 num_ls_gprs = 23;
 323                 num_ps_threads = 128;
 324                 num_vs_threads = 20;
 325                 num_gs_threads = 20;
 326                 num_es_threads = 20;
 327                 num_hs_threads = 20;
 328                 num_ls_threads = 20;
 329                 num_ps_stack_entries = 85;
 330                 num_vs_stack_entries = 85;
 331                 num_gs_stack_entries = 85;
 332                 num_es_stack_entries = 85;
 333                 num_hs_stack_entries = 85;
 334                 num_ls_stack_entries = 85;
 335                 break;
 336         case CHIP_PALM:
 337                 num_ps_gprs = 93;
 338                 num_vs_gprs = 46;
 339                 num_temp_gprs = 4;
 340                 num_gs_gprs = 31;
 341                 num_es_gprs = 31;
 342                 num_hs_gprs = 23;
 343                 num_ls_gprs = 23;
 344                 num_ps_threads = 96;
 345                 num_vs_threads = 16;
 346                 num_gs_threads = 16;
 347                 num_es_threads = 16;
 348                 num_hs_threads = 16;
 349                 num_ls_threads = 16;
 350                 num_ps_stack_entries = 42;
 351                 num_vs_stack_entries = 42;
 352                 num_gs_stack_entries = 42;
 353                 num_es_stack_entries = 42;
 354                 num_hs_stack_entries = 42;
 355                 num_ls_stack_entries = 42;
 356                 break;
 357         case CHIP_BARTS:
 358                 num_ps_gprs = 93;
 359                 num_vs_gprs = 46;
 360                 num_temp_gprs = 4;
 361                 num_gs_gprs = 31;
 362                 num_es_gprs = 31;
 363                 num_hs_gprs = 23;
 364                 num_ls_gprs = 23;
 365                 num_ps_threads = 128;
 366                 num_vs_threads = 20;
 367                 num_gs_threads = 20;
 368                 num_es_threads = 20;
 369                 num_hs_threads = 20;
 370                 num_ls_threads = 20;
 371                 num_ps_stack_entries = 85;
 372                 num_vs_stack_entries = 85;
 373                 num_gs_stack_entries = 85;
 374                 num_es_stack_entries = 85;
 375                 num_hs_stack_entries = 85;
 376                 num_ls_stack_entries = 85;
 377                 break;
 378         case CHIP_TURKS:
 379                 num_ps_gprs = 93;
 380                 num_vs_gprs = 46;
 381                 num_temp_gprs = 4;
 382                 num_gs_gprs = 31;
 383                 num_es_gprs = 31;
 384                 num_hs_gprs = 23;
 385                 num_ls_gprs = 23;
 386                 num_ps_threads = 128;
 387                 num_vs_threads = 20;
 388                 num_gs_threads = 20;
 389                 num_es_threads = 20;
 390                 num_hs_threads = 20;
 391                 num_ls_threads = 20;
 392                 num_ps_stack_entries = 42;
 393                 num_vs_stack_entries = 42;
 394                 num_gs_stack_entries = 42;
 395                 num_es_stack_entries = 42;
 396                 num_hs_stack_entries = 42;
 397                 num_ls_stack_entries = 42;
 398                 break;
 399         case CHIP_CAICOS:
 400                 num_ps_gprs = 93;
 401                 num_vs_gprs = 46;
 402                 num_temp_gprs = 4;
 403                 num_gs_gprs = 31;
 404                 num_es_gprs = 31;
 405                 num_hs_gprs = 23;
 406                 num_ls_gprs = 23;
 407                 num_ps_threads = 128;
 408                 num_vs_threads = 10;
 409                 num_gs_threads = 10;
 410                 num_es_threads = 10;
 411                 num_hs_threads = 10;
 412                 num_ls_threads = 10;
 413                 num_ps_stack_entries = 42;
 414                 num_vs_stack_entries = 42;
 415                 num_gs_stack_entries = 42;
 416                 num_es_stack_entries = 42;
 417                 num_hs_stack_entries = 42;
 418                 num_ls_stack_entries = 42;
 419                 break;
 420         }
 421
 422         if ((rdev->family == CHIP_CEDAR) ||
 423             (rdev->family == CHIP_PALM) ||
 424             (rdev->family == CHIP_CAICOS))
 425                 sq_config = 0;
 426         else
 427                 sq_config = VC_ENABLE;
 428
 429         sq_config |= (EXPORT_SRC_C |
 430                       CS_PRIO(0) |
 431                       LS_PRIO(0) |
 432                       HS_PRIO(0) |
 433                       PS_PRIO(0) |
 434                       VS_PRIO(1) |
 435                       GS_PRIO(2) |
 436                       ES_PRIO(3));
 437
 438         sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
 439                                   NUM_VS_GPRS(num_vs_gprs) |
 440                                   NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
 441         sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
 442                                   NUM_ES_GPRS(num_es_gprs));
 443         sq_gpr_resource_mgmt_3 = (NUM_HS_GPRS(num_hs_gprs) |
 444                                   NUM_LS_GPRS(num_ls_gprs));
 445         sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
 446                                    NUM_VS_THREADS(num_vs_threads) |
 447                                    NUM_GS_THREADS(num_gs_threads) |
 448                                    NUM_ES_THREADS(num_es_threads));
 449         sq_thread_resource_mgmt_2 = (NUM_HS_THREADS(num_hs_threads) |
 450                                      NUM_LS_THREADS(num_ls_threads));
 451         sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
 452                                     NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
 453         sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
 454                                     NUM_ES_STACK_ENTRIES(num_es_stack_entries));
 455         sq_stack_resource_mgmt_3 = (NUM_HS_STACK_ENTRIES(num_hs_stack_entries) |
 456                                     NUM_LS_STACK_ENTRIES(num_ls_stack_entries));
 457
 458         /* set clear context state */
 459         radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
 460         radeon_ring_write(rdev, 0);
 461
 462         /* disable dyn gprs */
 463         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 464         radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2);
 465         radeon_ring_write(rdev, 0);
 466
 467         /* SQ config */
 468         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11));
 469         radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2);
 470         radeon_ring_write(rdev, sq_config);
 471         radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
 472         radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
 473         radeon_ring_write(rdev, sq_gpr_resource_mgmt_3);
 474         radeon_ring_write(rdev, 0);
 475         radeon_ring_write(rdev, 0);
 476         radeon_ring_write(rdev, sq_thread_resource_mgmt);
 477         radeon_ring_write(rdev, sq_thread_resource_mgmt_2);
 478         radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
 479         radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
 480         radeon_ring_write(rdev, sq_stack_resource_mgmt_3);
 481
 482         /* CONTEXT_CONTROL */
 483         radeon_ring_write(rdev, 0xc0012800);
 484         radeon_ring_write(rdev, 0x80000000);
 485         radeon_ring_write(rdev, 0x80000000);
 486
 487         /* SQ_VTX_BASE_VTX_LOC */
 488         radeon_ring_write(rdev, 0xc0026f00);
 489         radeon_ring_write(rdev, 0x00000000);
 490         radeon_ring_write(rdev, 0x00000000);
 491         radeon_ring_write(rdev, 0x00000000);
 492
 493         /* SET_SAMPLER */
 494         radeon_ring_write(rdev, 0xc0036e00);
 495         radeon_ring_write(rdev, 0x00000000);
 496         radeon_ring_write(rdev, 0x00000012);
 497         radeon_ring_write(rdev, 0x00000000);
 498         radeon_ring_write(rdev, 0x00000000);
 499
 500 }
 501
 502 static inline uint32_t i2f(uint32_t input)
 503 {
 504         u32 result, i, exponent, fraction;
 505
 506         if ((input & 0x3fff) == 0)
 507                 result = 0; /* 0 is a special case */
 508         else {
 509                 exponent = 140; /* exponent biased by 127; */
 510                 fraction = (input & 0x3fff) << 10; /* cheat and only
 511                                                       handle numbers below 2^^15 */
 512                 for (i = 0; i < 14; i++) {
 513                         if (fraction & 0x800000)
 514                                 break;
 515                         else {
 516                                 fraction = fraction << 1; /* keep
 517                                                              shifting left until top bit = 1 */
 518                                 exponent = exponent - 1;
 519                         }
 520                 }
 521                 result = exponent << 23 | (fraction & 0x7fffff); /* mask
 522                                                                     off top bit; assumed 1 */
 523         }
 524         return result;
 525 }
 526
 527 int evergreen_blit_init(struct radeon_device *rdev)
 528 {
 529         u32 obj_size;
 530         int r;
 531         void *ptr;
 532
 533         /* pin copy shader into vram if already initialized */
 534         if (rdev->r600_blit.shader_obj)
 535                 goto done;
 536
 537         mutex_init(&rdev->r600_blit.mutex);
 538         rdev->r600_blit.state_offset = 0;
 539         rdev->r600_blit.state_len = 0;
 540         obj_size = 0;
 541
 542         rdev->r600_blit.vs_offset = obj_size;
 543         obj_size += evergreen_vs_size * 4;
 544         obj_size = ALIGN(obj_size, 256);
 545
 546         rdev->r600_blit.ps_offset = obj_size;
 547         obj_size += evergreen_ps_size * 4;
 548         obj_size = ALIGN(obj_size, 256);
 549
 550         r = radeon_bo_create(rdev, NULL, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
 551                                 &rdev->r600_blit.shader_obj);
 552         if (r) {
 553                 DRM_ERROR("evergreen failed to allocate shader\n");
 554                 return r;
 555         }
 556
 557         DRM_DEBUG("evergreen blit allocated bo %08x vs %08x ps %08x\n",
 558                   obj_size,
 559                   rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
 560
 561         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 562         if (unlikely(r != 0))
 563                 return r;
 564         r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
 565         if (r) {
 566                 DRM_ERROR("failed to map blit object %d\n", r);
 567                 return r;
 568         }
 569
 570         memcpy(ptr + rdev->r600_blit.vs_offset, evergreen_vs, evergreen_vs_size * 4);
 571         memcpy(ptr + rdev->r600_blit.ps_offset, evergreen_ps, evergreen_ps_size * 4);
 572         radeon_bo_kunmap(rdev->r600_blit.shader_obj);
 573         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 574
 575 done:
 576         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 577         if (unlikely(r != 0))
 578                 return r;
 579         r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
 580                           &rdev->r600_blit.shader_gpu_addr);
 581         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 582         if (r) {
 583                 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
 584                 return r;
 585         }
 586         rdev->mc.active_vram_size = rdev->mc.real_vram_size;
 587         return 0;
 588 }
 589
 590 void evergreen_blit_fini(struct radeon_device *rdev)
 591 {
 592         int r;
 593
 594         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
 595         if (rdev->r600_blit.shader_obj == NULL)
 596                 return;
 597         /* If we can't reserve the bo, unref should be enough to destroy
 598          * it when it becomes idle.
 599          */
 600         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 601         if (!r) {
 602                 radeon_bo_unpin(rdev->r600_blit.shader_obj);
 603                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 604         }
 605         radeon_bo_unref(&rdev->r600_blit.shader_obj);
 606 }
 607
 608 static int evergreen_vb_ib_get(struct radeon_device *rdev)
 609 {
 610         int r;
 611         r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib);
 612         if (r) {
 613                 DRM_ERROR("failed to get IB for vertex buffer\n");
 614                 return r;
 615         }
 616
 617         rdev->r600_blit.vb_total = 64*1024;
 618         rdev->r600_blit.vb_used = 0;
 619         return 0;
 620 }
 621
 622 static void evergreen_vb_ib_put(struct radeon_device *rdev)
 623 {
 624         radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence);
 625         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
 626 }
 627
 628 int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
 629 {
 630         int r;
 631         int ring_size, line_size;
 632         int max_size;
 633         /* loops of emits + fence emit possible */
 634         int dwords_per_loop = 74, num_loops;
 635
 636         r = evergreen_vb_ib_get(rdev);
 637         if (r)
 638                 return r;
 639
 640         /* 8 bpp vs 32 bpp for xfer unit */
 641         if (size_bytes & 3)
 642                 line_size = 8192;
 643         else
 644                 line_size = 8192 * 4;
 645
 646         max_size = 8192 * line_size;
 647
 648         /* major loops cover the max size transfer */
 649         num_loops = ((size_bytes + max_size) / max_size);
 650         /* minor loops cover the extra non aligned bits */
 651         num_loops += ((size_bytes % line_size) ? 1 : 0);
 652         /* calculate number of loops correctly */
 653         ring_size = num_loops * dwords_per_loop;
 654         /* set default  + shaders */
 655         ring_size += 46; /* shaders + def state */
 656         ring_size += 10; /* fence emit for VB IB */
 657         ring_size += 5; /* done copy */
 658         ring_size += 10; /* fence emit for done copy */
 659         r = radeon_ring_lock(rdev, ring_size);
 660         if (r)
 661                 return r;
 662
 663         set_default_state(rdev); /* 30 */
 664         set_shaders(rdev); /* 16 */
 665         return 0;
 666 }
 667
 668 void evergreen_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
 669 {
 670         int r;
 671
 672         if (rdev->r600_blit.vb_ib)
 673                 evergreen_vb_ib_put(rdev);
 674
 675         if (fence)
 676                 r = radeon_fence_emit(rdev, fence);
 677
 678         radeon_ring_unlock_commit(rdev);
 679 }
 680
 681 void evergreen_kms_blit_copy(struct radeon_device *rdev,
 682                              u64 src_gpu_addr, u64 dst_gpu_addr,
 683                              int size_bytes)
 684 {
 685         int max_bytes;
 686         u64 vb_gpu_addr;
 687         u32 *vb;
 688
 689         DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr,
 690                   size_bytes, rdev->r600_blit.vb_used);
 691         vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
 692         if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
 693                 max_bytes = 8192;
 694
 695                 while (size_bytes) {
 696                         int cur_size = size_bytes;
 697                         int src_x = src_gpu_addr & 255;
 698                         int dst_x = dst_gpu_addr & 255;
 699                         int h = 1;
 700                         src_gpu_addr = src_gpu_addr & ~255ULL;
 701                         dst_gpu_addr = dst_gpu_addr & ~255ULL;
 702
 703                         if (!src_x && !dst_x) {
 704                                 h = (cur_size / max_bytes);
 705                                 if (h > 8192)
 706                                         h = 8192;
 707                                 if (h == 0)
 708                                         h = 1;
 709                                 else
 710                                         cur_size = max_bytes;
 711                         } else {
 712                                 if (cur_size > max_bytes)
 713                                         cur_size = max_bytes;
 714                                 if (cur_size > (max_bytes - dst_x))
 715                                         cur_size = (max_bytes - dst_x);
 716                                 if (cur_size > (max_bytes - src_x))
 717                                         cur_size = (max_bytes - src_x);
 718                         }
 719
 720                         if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
 721                                 WARN_ON(1);
 722                         }
 723
 724                         vb[0] = i2f(dst_x);
 725                         vb[1] = 0;
 726                         vb[2] = i2f(src_x);
 727                         vb[3] = 0;
 728
 729                         vb[4] = i2f(dst_x);
 730                         vb[5] = i2f(h);
 731                         vb[6] = i2f(src_x);
 732                         vb[7] = i2f(h);
 733
 734                         vb[8] = i2f(dst_x + cur_size);
 735                         vb[9] = i2f(h);
 736                         vb[10] = i2f(src_x + cur_size);
 737                         vb[11] = i2f(h);
 738
 739                         /* src 10 */
 740                         set_tex_resource(rdev, FMT_8,
 741                                          src_x + cur_size, h, src_x + cur_size,
 742                                          src_gpu_addr);
 743
 744                         /* 5 */
 745                         cp_set_surface_sync(rdev,
 746                                             PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
 747
 748
 749                         /* dst 17 */
 750                         set_render_target(rdev, COLOR_8,
 751                                           dst_x + cur_size, h,
 752                                           dst_gpu_addr);
 753
 754                         /* scissors 12 */
 755                         set_scissors(rdev, dst_x, 0, dst_x + cur_size, h);
 756
 757                         /* 15 */
 758                         vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
 759                         set_vtx_resource(rdev, vb_gpu_addr);
 760
 761                         /* draw 10 */
 762                         draw_auto(rdev);
 763
 764                         /* 5 */
 765                         cp_set_surface_sync(rdev,
 766                                             PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
 767                                             cur_size * h, dst_gpu_addr);
 768
 769                         vb += 12;
 770                         rdev->r600_blit.vb_used += 12 * 4;
 771
 772                         src_gpu_addr += cur_size * h;
 773                         dst_gpu_addr += cur_size * h;
 774                         size_bytes -= cur_size * h;
 775                 }
 776         } else {
 777                 max_bytes = 8192 * 4;
 778
 779                 while (size_bytes) {
 780                         int cur_size = size_bytes;
 781                         int src_x = (src_gpu_addr & 255);
 782                         int dst_x = (dst_gpu_addr & 255);
 783                         int h = 1;
 784                         src_gpu_addr = src_gpu_addr & ~255ULL;
 785                         dst_gpu_addr = dst_gpu_addr & ~255ULL;
 786
 787                         if (!src_x && !dst_x) {
 788                                 h = (cur_size / max_bytes);
 789                                 if (h > 8192)
 790                                         h = 8192;
 791                                 if (h == 0)
 792                                         h = 1;
 793                                 else
 794                                         cur_size = max_bytes;
 795                         } else {
 796                                 if (cur_size > max_bytes)
 797                                         cur_size = max_bytes;
 798                                 if (cur_size > (max_bytes - dst_x))
 799                                         cur_size = (max_bytes - dst_x);
 800                                 if (cur_size > (max_bytes - src_x))
 801                                         cur_size = (max_bytes - src_x);
 802                         }
 803
 804                         if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
 805                                 WARN_ON(1);
 806                         }
 807
 808                         vb[0] = i2f(dst_x / 4);
 809                         vb[1] = 0;
 810                         vb[2] = i2f(src_x / 4);
 811                         vb[3] = 0;
 812
 813                         vb[4] = i2f(dst_x / 4);
 814                         vb[5] = i2f(h);
 815                         vb[6] = i2f(src_x / 4);
 816                         vb[7] = i2f(h);
 817
 818                         vb[8] = i2f((dst_x + cur_size) / 4);
 819                         vb[9] = i2f(h);
 820                         vb[10] = i2f((src_x + cur_size) / 4);
 821                         vb[11] = i2f(h);
 822
 823                         /* src 10 */
 824                         set_tex_resource(rdev, FMT_8_8_8_8,
 825                                          (src_x + cur_size) / 4,
 826                                          h, (src_x + cur_size) / 4,
 827                                          src_gpu_addr);
 828                         /* 5 */
 829                         cp_set_surface_sync(rdev,
 830                                             PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
 831
 832                         /* dst 17 */
 833                         set_render_target(rdev, COLOR_8_8_8_8,
 834                                           (dst_x + cur_size) / 4, h,
 835                                           dst_gpu_addr);
 836
 837                         /* scissors 12  */
 838                         set_scissors(rdev, (dst_x / 4), 0, (dst_x + cur_size / 4), h);
 839
 840                         /* Vertex buffer setup 15 */
 841                         vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
 842                         set_vtx_resource(rdev, vb_gpu_addr);
 843
 844                         /* draw 10 */
 845                         draw_auto(rdev);
 846
 847                         /* 5 */
 848                         cp_set_surface_sync(rdev,
 849                                             PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
 850                                             cur_size * h, dst_gpu_addr);
 851
 852                         /* 74 ring dwords per loop */
 853                         vb += 12;
 854                         rdev->r600_blit.vb_used += 12 * 4;
 855
 856                         src_gpu_addr += cur_size * h;
 857                         dst_gpu_addr += cur_size * h;
 858                         size_bytes -= cur_size * h;
 859                 }
 860         }
 861 }
 862