drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/platform_device.h>
  32 #include "drmP.h"
  33 #include "radeon_drm.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "radeon_mode.h"
  37 #include "r600d.h"
  38 #include "atom.h"
  39 #include "avivod.h"
  40
  41 #define PFP_UCODE_SIZE 576
  42 #define PM4_UCODE_SIZE 1792
  43 #define RLC_UCODE_SIZE 768
  44 #define R700_PFP_UCODE_SIZE 848
  45 #define R700_PM4_UCODE_SIZE 1360
  46 #define R700_RLC_UCODE_SIZE 1024
  47 #define EVERGREEN_PFP_UCODE_SIZE 1120
  48 #define EVERGREEN_PM4_UCODE_SIZE 1376
  49 #define EVERGREEN_RLC_UCODE_SIZE 768
  50
  51 /* Firmware Names */
  52 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  53 MODULE_FIRMWARE("radeon/R600_me.bin");
  54 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  55 MODULE_FIRMWARE("radeon/RV610_me.bin");
  56 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  57 MODULE_FIRMWARE("radeon/RV630_me.bin");
  58 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  59 MODULE_FIRMWARE("radeon/RV620_me.bin");
  60 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  61 MODULE_FIRMWARE("radeon/RV635_me.bin");
  62 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  63 MODULE_FIRMWARE("radeon/RV670_me.bin");
  64 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  65 MODULE_FIRMWARE("radeon/RS780_me.bin");
  66 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  67 MODULE_FIRMWARE("radeon/RV770_me.bin");
  68 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  69 MODULE_FIRMWARE("radeon/RV730_me.bin");
  70 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  71 MODULE_FIRMWARE("radeon/RV710_me.bin");
  72 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  73 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  74 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  75 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  76 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  77 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  78 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  79 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  80 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  81 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  82 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  83 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  84 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  85 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  86
  87 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  88
  89 /* r600,rv610,rv630,rv620,rv635,rv670 */
  90 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  91 void r600_gpu_init(struct radeon_device *rdev);
  92 void r600_fini(struct radeon_device *rdev);
  93 void r600_irq_disable(struct radeon_device *rdev);
  94
  95 /* get temperature in millidegrees */
  96 u32 rv6xx_get_temp(struct radeon_device *rdev)
  97 {
  98         u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
  99                 ASIC_T_SHIFT;
 100         u32 actual_temp = 0;
 101
 102         if ((temp >> 7) & 1)
 103                 actual_temp = 0;
 104         else
 105                 actual_temp = (temp >> 1) & 0xff;
 106
 107         return actual_temp * 1000;
 108 }
 109
 110 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
 111 {
 112         int i;
 113
 114         rdev->pm.dynpm_can_upclock = true;
 115         rdev->pm.dynpm_can_downclock = true;
 116
 117         /* power state array is low to high, default is first */
 118         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 119                 int min_power_state_index = 0;
 120
 121                 if (rdev->pm.num_power_states > 2)
 122                         min_power_state_index = 1;
 123
 124                 switch (rdev->pm.dynpm_planned_action) {
 125                 case DYNPM_ACTION_MINIMUM:
 126                         rdev->pm.requested_power_state_index = min_power_state_index;
 127                         rdev->pm.requested_clock_mode_index = 0;
 128                         rdev->pm.dynpm_can_downclock = false;
 129                         break;
 130                 case DYNPM_ACTION_DOWNCLOCK:
 131                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 132                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 133                                 rdev->pm.dynpm_can_downclock = false;
 134                         } else {
 135                                 if (rdev->pm.active_crtc_count > 1) {
 136                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 137                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 138                                                         continue;
 139                                                 else if (i >= rdev->pm.current_power_state_index) {
 140                                                         rdev->pm.requested_power_state_index =
 141                                                                 rdev->pm.current_power_state_index;
 142                                                         break;
 143                                                 } else {
 144                                                         rdev->pm.requested_power_state_index = i;
 145                                                         break;
 146                                                 }
 147                                         }
 148                                 } else {
 149                                         if (rdev->pm.current_power_state_index == 0)
 150                                                 rdev->pm.requested_power_state_index =
 151                                                         rdev->pm.num_power_states - 1;
 152                                         else
 153                                                 rdev->pm.requested_power_state_index =
 154                                                         rdev->pm.current_power_state_index - 1;
 155                                 }
 156                         }
 157                         rdev->pm.requested_clock_mode_index = 0;
 158                         /* don't use the power state if crtcs are active and no display flag is set */
 159                         if ((rdev->pm.active_crtc_count > 0) &&
 160                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 161                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 162                              RADEON_PM_MODE_NO_DISPLAY)) {
 163                                 rdev->pm.requested_power_state_index++;
 164                         }
 165                         break;
 166                 case DYNPM_ACTION_UPCLOCK:
 167                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 168                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 169                                 rdev->pm.dynpm_can_upclock = false;
 170                         } else {
 171                                 if (rdev->pm.active_crtc_count > 1) {
 172                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 173                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 174                                                         continue;
 175                                                 else if (i <= rdev->pm.current_power_state_index) {
 176                                                         rdev->pm.requested_power_state_index =
 177                                                                 rdev->pm.current_power_state_index;
 178                                                         break;
 179                                                 } else {
 180                                                         rdev->pm.requested_power_state_index = i;
 181                                                         break;
 182                                                 }
 183                                         }
 184                                 } else
 185                                         rdev->pm.requested_power_state_index =
 186                                                 rdev->pm.current_power_state_index + 1;
 187                         }
 188                         rdev->pm.requested_clock_mode_index = 0;
 189                         break;
 190                 case DYNPM_ACTION_DEFAULT:
 191                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 192                         rdev->pm.requested_clock_mode_index = 0;
 193                         rdev->pm.dynpm_can_upclock = false;
 194                         break;
 195                 case DYNPM_ACTION_NONE:
 196                 default:
 197                         DRM_ERROR("Requested mode for not defined action\n");
 198                         return;
 199                 }
 200         } else {
 201                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 202                 /* for now just select the first power state and switch between clock modes */
 203                 /* power state array is low to high, default is first (0) */
 204                 if (rdev->pm.active_crtc_count > 1) {
 205                         rdev->pm.requested_power_state_index = -1;
 206                         /* start at 1 as we don't want the default mode */
 207                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 208                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 209                                         continue;
 210                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 211                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 212                                         rdev->pm.requested_power_state_index = i;
 213                                         break;
 214                                 }
 215                         }
 216                         /* if nothing selected, grab the default state. */
 217                         if (rdev->pm.requested_power_state_index == -1)
 218                                 rdev->pm.requested_power_state_index = 0;
 219                 } else
 220                         rdev->pm.requested_power_state_index = 1;
 221
 222                 switch (rdev->pm.dynpm_planned_action) {
 223                 case DYNPM_ACTION_MINIMUM:
 224                         rdev->pm.requested_clock_mode_index = 0;
 225                         rdev->pm.dynpm_can_downclock = false;
 226                         break;
 227                 case DYNPM_ACTION_DOWNCLOCK:
 228                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 229                                 if (rdev->pm.current_clock_mode_index == 0) {
 230                                         rdev->pm.requested_clock_mode_index = 0;
 231                                         rdev->pm.dynpm_can_downclock = false;
 232                                 } else
 233                                         rdev->pm.requested_clock_mode_index =
 234                                                 rdev->pm.current_clock_mode_index - 1;
 235                         } else {
 236                                 rdev->pm.requested_clock_mode_index = 0;
 237                                 rdev->pm.dynpm_can_downclock = false;
 238                         }
 239                         /* don't use the power state if crtcs are active and no display flag is set */
 240                         if ((rdev->pm.active_crtc_count > 0) &&
 241                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 242                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 243                              RADEON_PM_MODE_NO_DISPLAY)) {
 244                                 rdev->pm.requested_clock_mode_index++;
 245                         }
 246                         break;
 247                 case DYNPM_ACTION_UPCLOCK:
 248                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 249                                 if (rdev->pm.current_clock_mode_index ==
 250                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 251                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 252                                         rdev->pm.dynpm_can_upclock = false;
 253                                 } else
 254                                         rdev->pm.requested_clock_mode_index =
 255                                                 rdev->pm.current_clock_mode_index + 1;
 256                         } else {
 257                                 rdev->pm.requested_clock_mode_index =
 258                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 259                                 rdev->pm.dynpm_can_upclock = false;
 260                         }
 261                         break;
 262                 case DYNPM_ACTION_DEFAULT:
 263                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 264                         rdev->pm.requested_clock_mode_index = 0;
 265                         rdev->pm.dynpm_can_upclock = false;
 266                         break;
 267                 case DYNPM_ACTION_NONE:
 268                 default:
 269                         DRM_ERROR("Requested mode for not defined action\n");
 270                         return;
 271                 }
 272         }
 273
 274         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 275                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 276                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 277                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 278                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 279                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 280                   pcie_lanes);
 281 }
 282
 283 static int r600_pm_get_type_index(struct radeon_device *rdev,
 284                                   enum radeon_pm_state_type ps_type,
 285                                   int instance)
 286 {
 287         int i;
 288         int found_instance = -1;
 289
 290         for (i = 0; i < rdev->pm.num_power_states; i++) {
 291                 if (rdev->pm.power_state[i].type == ps_type) {
 292                         found_instance++;
 293                         if (found_instance == instance)
 294                                 return i;
 295                 }
 296         }
 297         /* return default if no match */
 298         return rdev->pm.default_power_state_index;
 299 }
 300
 301 void rs780_pm_init_profile(struct radeon_device *rdev)
 302 {
 303         if (rdev->pm.num_power_states == 2) {
 304                 /* default */
 305                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 306                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 307                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 308                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 309                 /* low sh */
 310                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 311                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 312                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 313                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 314                 /* mid sh */
 315                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 316                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 317                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 318                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 319                 /* high sh */
 320                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 321                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 322                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 323                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 324                 /* low mh */
 325                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 326                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 327                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 328                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 329                 /* mid mh */
 330                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 331                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 332                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 333                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 334                 /* high mh */
 335                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 336                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 337                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 338                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 339         } else if (rdev->pm.num_power_states == 3) {
 340                 /* default */
 341                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 342                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 343                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 344                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 345                 /* low sh */
 346                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 347                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 348                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 349                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 350                 /* mid sh */
 351                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 352                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 353                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 354                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 355                 /* high sh */
 356                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 357                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 358                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 359                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 360                 /* low mh */
 361                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 362                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 363                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 364                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 365                 /* mid mh */
 366                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 367                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 368                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 369                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 370                 /* high mh */
 371                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 372                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 373                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 374                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 375         } else {
 376                 /* default */
 377                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 378                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 379                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 380                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 381                 /* low sh */
 382                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 383                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 384                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 385                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 386                 /* mid sh */
 387                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 388                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 389                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 390                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 391                 /* high sh */
 392                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 393                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 394                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 395                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 396                 /* low mh */
 397                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 398                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 399                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 400                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 401                 /* mid mh */
 402                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 403                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 404                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 405                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 406                 /* high mh */
 407                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 408                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 409                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 410                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 411         }
 412 }
 413
 414 void r600_pm_init_profile(struct radeon_device *rdev)
 415 {
 416         if (rdev->family == CHIP_R600) {
 417                 /* XXX */
 418                 /* default */
 419                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 420                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 421                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 422                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 423                 /* low sh */
 424                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 425                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 426                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 427                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 428                 /* mid sh */
 429                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 430                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 431                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 432                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 433                 /* high sh */
 434                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 435                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 436                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 437                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 438                 /* low mh */
 439                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 440                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 441                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 442                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 443                 /* mid mh */
 444                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 445                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 446                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 447                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 448                 /* high mh */
 449                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 450                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 451                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 452                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 453         } else {
 454                 if (rdev->pm.num_power_states < 4) {
 455                         /* default */
 456                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 457                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 458                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 459                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 460                         /* low sh */
 461                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 462                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 463                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 464                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 465                         /* mid sh */
 466                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 467                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 468                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 469                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 470                         /* high sh */
 471                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 472                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 473                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 474                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 475                         /* low mh */
 476                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 477                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 478                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 479                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 480                         /* low mh */
 481                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 482                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 483                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 484                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 485                         /* high mh */
 486                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 487                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 488                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 489                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 490                 } else {
 491                         /* default */
 492                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 493                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 494                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 495                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 496                         /* low sh */
 497                         if (rdev->flags & RADEON_IS_MOBILITY) {
 498                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 499                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 500                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 501                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 502                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 503                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 504                         } else {
 505                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 506                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 507                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 508                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 509                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 510                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 511                         }
 512                         /* mid sh */
 513                         if (rdev->flags & RADEON_IS_MOBILITY) {
 514                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 515                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 516                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 517                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 518                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 519                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 520                         } else {
 521                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 522                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 523                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 524                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 525                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 526                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 527                         }
 528                         /* high sh */
 529                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
 530                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 531                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
 532                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 533                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 534                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 535                         /* low mh */
 536                         if (rdev->flags & RADEON_IS_MOBILITY) {
 537                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 538                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 539                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 540                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 541                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 542                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 543                         } else {
 544                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 545                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 546                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 547                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 548                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 549                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 550                         }
 551                         /* mid mh */
 552                         if (rdev->flags & RADEON_IS_MOBILITY) {
 553                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 554                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 555                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 556                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 557                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 558                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 559                         } else {
 560                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 561                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 562                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 563                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 564                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 565                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 566                         }
 567                         /* high mh */
 568                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
 569                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 570                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
 571                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 572                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 573                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 574                 }
 575         }
 576 }
 577
 578 void r600_pm_misc(struct radeon_device *rdev)
 579 {
 580         int req_ps_idx = rdev->pm.requested_power_state_index;
 581         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 582         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 583         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 584
 585         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 586                 if (voltage->voltage != rdev->pm.current_vddc) {
 587                         radeon_atom_set_voltage(rdev, voltage->voltage);
 588                         rdev->pm.current_vddc = voltage->voltage;
 589                         DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
 590                 }
 591         }
 592 }
 593
 594 bool r600_gui_idle(struct radeon_device *rdev)
 595 {
 596         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 597                 return false;
 598         else
 599                 return true;
 600 }
 601
 602 /* hpd for digital panel detect/disconnect */
 603 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 604 {
 605         bool connected = false;
 606
 607         if (ASIC_IS_DCE3(rdev)) {
 608                 switch (hpd) {
 609                 case RADEON_HPD_1:
 610                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 611                                 connected = true;
 612                         break;
 613                 case RADEON_HPD_2:
 614                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 615                                 connected = true;
 616                         break;
 617                 case RADEON_HPD_3:
 618                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 619                                 connected = true;
 620                         break;
 621                 case RADEON_HPD_4:
 622                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 623                                 connected = true;
 624                         break;
 625                         /* DCE 3.2 */
 626                 case RADEON_HPD_5:
 627                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 628                                 connected = true;
 629                         break;
 630                 case RADEON_HPD_6:
 631                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 632                                 connected = true;
 633                         break;
 634                 default:
 635                         break;
 636                 }
 637         } else {
 638                 switch (hpd) {
 639                 case RADEON_HPD_1:
 640                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 641                                 connected = true;
 642                         break;
 643                 case RADEON_HPD_2:
 644                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 645                                 connected = true;
 646                         break;
 647                 case RADEON_HPD_3:
 648                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 649                                 connected = true;
 650                         break;
 651                 default:
 652                         break;
 653                 }
 654         }
 655         return connected;
 656 }
 657
 658 void r600_hpd_set_polarity(struct radeon_device *rdev,
 659                            enum radeon_hpd_id hpd)
 660 {
 661         u32 tmp;
 662         bool connected = r600_hpd_sense(rdev, hpd);
 663
 664         if (ASIC_IS_DCE3(rdev)) {
 665                 switch (hpd) {
 666                 case RADEON_HPD_1:
 667                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 668                         if (connected)
 669                                 tmp &= ~DC_HPDx_INT_POLARITY;
 670                         else
 671                                 tmp |= DC_HPDx_INT_POLARITY;
 672                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 673                         break;
 674                 case RADEON_HPD_2:
 675                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 676                         if (connected)
 677                                 tmp &= ~DC_HPDx_INT_POLARITY;
 678                         else
 679                                 tmp |= DC_HPDx_INT_POLARITY;
 680                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 681                         break;
 682                 case RADEON_HPD_3:
 683                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 684                         if (connected)
 685                                 tmp &= ~DC_HPDx_INT_POLARITY;
 686                         else
 687                                 tmp |= DC_HPDx_INT_POLARITY;
 688                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 689                         break;
 690                 case RADEON_HPD_4:
 691                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 692                         if (connected)
 693                                 tmp &= ~DC_HPDx_INT_POLARITY;
 694                         else
 695                                 tmp |= DC_HPDx_INT_POLARITY;
 696                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 697                         break;
 698                 case RADEON_HPD_5:
 699                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 700                         if (connected)
 701                                 tmp &= ~DC_HPDx_INT_POLARITY;
 702                         else
 703                                 tmp |= DC_HPDx_INT_POLARITY;
 704                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 705                         break;
 706                         /* DCE 3.2 */
 707                 case RADEON_HPD_6:
 708                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 709                         if (connected)
 710                                 tmp &= ~DC_HPDx_INT_POLARITY;
 711                         else
 712                                 tmp |= DC_HPDx_INT_POLARITY;
 713                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 714                         break;
 715                 default:
 716                         break;
 717                 }
 718         } else {
 719                 switch (hpd) {
 720                 case RADEON_HPD_1:
 721                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 722                         if (connected)
 723                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 724                         else
 725                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 726                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 727                         break;
 728                 case RADEON_HPD_2:
 729                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 730                         if (connected)
 731                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 732                         else
 733                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 734                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 735                         break;
 736                 case RADEON_HPD_3:
 737                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 738                         if (connected)
 739                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 740                         else
 741                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 742                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 743                         break;
 744                 default:
 745                         break;
 746                 }
 747         }
 748 }
 749
 750 void r600_hpd_init(struct radeon_device *rdev)
 751 {
 752         struct drm_device *dev = rdev->ddev;
 753         struct drm_connector *connector;
 754
 755         if (ASIC_IS_DCE3(rdev)) {
 756                 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 757                 if (ASIC_IS_DCE32(rdev))
 758                         tmp |= DC_HPDx_EN;
 759
 760                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 761                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 762                         switch (radeon_connector->hpd.hpd) {
 763                         case RADEON_HPD_1:
 764                                 WREG32(DC_HPD1_CONTROL, tmp);
 765                                 rdev->irq.hpd[0] = true;
 766                                 break;
 767                         case RADEON_HPD_2:
 768                                 WREG32(DC_HPD2_CONTROL, tmp);
 769                                 rdev->irq.hpd[1] = true;
 770                                 break;
 771                         case RADEON_HPD_3:
 772                                 WREG32(DC_HPD3_CONTROL, tmp);
 773                                 rdev->irq.hpd[2] = true;
 774                                 break;
 775                         case RADEON_HPD_4:
 776                                 WREG32(DC_HPD4_CONTROL, tmp);
 777                                 rdev->irq.hpd[3] = true;
 778                                 break;
 779                                 /* DCE 3.2 */
 780                         case RADEON_HPD_5:
 781                                 WREG32(DC_HPD5_CONTROL, tmp);
 782                                 rdev->irq.hpd[4] = true;
 783                                 break;
 784                         case RADEON_HPD_6:
 785                                 WREG32(DC_HPD6_CONTROL, tmp);
 786                                 rdev->irq.hpd[5] = true;
 787                                 break;
 788                         default:
 789                                 break;
 790                         }
 791                 }
 792         } else {
 793                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 794                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 795                         switch (radeon_connector->hpd.hpd) {
 796                         case RADEON_HPD_1:
 797                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 798                                 rdev->irq.hpd[0] = true;
 799                                 break;
 800                         case RADEON_HPD_2:
 801                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 802                                 rdev->irq.hpd[1] = true;
 803                                 break;
 804                         case RADEON_HPD_3:
 805                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 806                                 rdev->irq.hpd[2] = true;
 807                                 break;
 808                         default:
 809                                 break;
 810                         }
 811                 }
 812         }
 813         if (rdev->irq.installed)
 814                 r600_irq_set(rdev);
 815 }
 816
 817 void r600_hpd_fini(struct radeon_device *rdev)
 818 {
 819         struct drm_device *dev = rdev->ddev;
 820         struct drm_connector *connector;
 821
 822         if (ASIC_IS_DCE3(rdev)) {
 823                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 824                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 825                         switch (radeon_connector->hpd.hpd) {
 826                         case RADEON_HPD_1:
 827                                 WREG32(DC_HPD1_CONTROL, 0);
 828                                 rdev->irq.hpd[0] = false;
 829                                 break;
 830                         case RADEON_HPD_2:
 831                                 WREG32(DC_HPD2_CONTROL, 0);
 832                                 rdev->irq.hpd[1] = false;
 833                                 break;
 834                         case RADEON_HPD_3:
 835                                 WREG32(DC_HPD3_CONTROL, 0);
 836                                 rdev->irq.hpd[2] = false;
 837                                 break;
 838                         case RADEON_HPD_4:
 839                                 WREG32(DC_HPD4_CONTROL, 0);
 840                                 rdev->irq.hpd[3] = false;
 841                                 break;
 842                                 /* DCE 3.2 */
 843                         case RADEON_HPD_5:
 844                                 WREG32(DC_HPD5_CONTROL, 0);
 845                                 rdev->irq.hpd[4] = false;
 846                                 break;
 847                         case RADEON_HPD_6:
 848                                 WREG32(DC_HPD6_CONTROL, 0);
 849                                 rdev->irq.hpd[5] = false;
 850                                 break;
 851                         default:
 852                                 break;
 853                         }
 854                 }
 855         } else {
 856                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 857                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 858                         switch (radeon_connector->hpd.hpd) {
 859                         case RADEON_HPD_1:
 860                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 861                                 rdev->irq.hpd[0] = false;
 862                                 break;
 863                         case RADEON_HPD_2:
 864                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 865                                 rdev->irq.hpd[1] = false;
 866                                 break;
 867                         case RADEON_HPD_3:
 868                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 869                                 rdev->irq.hpd[2] = false;
 870                                 break;
 871                         default:
 872                                 break;
 873                         }
 874                 }
 875         }
 876 }
 877
 878 /*
 879  * R600 PCIE GART
 880  */
 881 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 882 {
 883         unsigned i;
 884         u32 tmp;
 885
 886         /* flush hdp cache so updates hit vram */
 887         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) {
 888                 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
 889                 u32 tmp;
 890
 891                 /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
 892                  * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
 893                  */
 894                 WREG32(HDP_DEBUG1, 0);
 895                 tmp = readl((void __iomem *)ptr);
 896         } else
 897                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 898
 899         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 900         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 901         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 902         for (i = 0; i < rdev->usec_timeout; i++) {
 903                 /* read MC_STATUS */
 904                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 905                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 906                 if (tmp == 2) {
 907                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 908                         return;
 909                 }
 910                 if (tmp) {
 911                         return;
 912                 }
 913                 udelay(1);
 914         }
 915 }
 916
 917 int r600_pcie_gart_init(struct radeon_device *rdev)
 918 {
 919         int r;
 920
 921         if (rdev->gart.table.vram.robj) {
 922                 WARN(1, "R600 PCIE GART already initialized.\n");
 923                 return 0;
 924         }
 925         /* Initialize common gart structure */
 926         r = radeon_gart_init(rdev);
 927         if (r)
 928                 return r;
 929         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 930         return radeon_gart_table_vram_alloc(rdev);
 931 }
 932
 933 int r600_pcie_gart_enable(struct radeon_device *rdev)
 934 {
 935         u32 tmp;
 936         int r, i;
 937
 938         if (rdev->gart.table.vram.robj == NULL) {
 939                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 940                 return -EINVAL;
 941         }
 942         r = radeon_gart_table_vram_pin(rdev);
 943         if (r)
 944                 return r;
 945         radeon_gart_restore(rdev);
 946
 947         /* Setup L2 cache */
 948         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 949                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 950                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 951         WREG32(VM_L2_CNTL2, 0);
 952         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 953         /* Setup TLB control */
 954         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 955                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 956                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 957                 ENABLE_WAIT_L2_QUERY;
 958         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 959         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 960         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 961         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 962         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 963         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 964         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 965         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 966         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 967         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 968         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 969         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 970         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 971         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 972         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 973         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 974         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 975         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 976                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 977         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 978                         (u32)(rdev->dummy_page.addr >> 12));
 979         for (i = 1; i < 7; i++)
 980                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 981
 982         r600_pcie_gart_tlb_flush(rdev);
 983         rdev->gart.ready = true;
 984         return 0;
 985 }
 986
 987 void r600_pcie_gart_disable(struct radeon_device *rdev)
 988 {
 989         u32 tmp;
 990         int i, r;
 991
 992         /* Disable all tables */
 993         for (i = 0; i < 7; i++)
 994                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 995
 996         /* Disable L2 cache */
 997         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 998                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 999         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1000         /* Setup L1 TLB control */
1001         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1002                 ENABLE_WAIT_L2_QUERY;
1003         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1004         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1005         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1006         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1007         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1008         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1009         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1010         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1011         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1012         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1013         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1014         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1015         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1016         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1017         if (rdev->gart.table.vram.robj) {
1018                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
1019                 if (likely(r == 0)) {
1020                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
1021                         radeon_bo_unpin(rdev->gart.table.vram.robj);
1022                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
1023                 }
1024         }
1025 }
1026
1027 void r600_pcie_gart_fini(struct radeon_device *rdev)
1028 {
1029         radeon_gart_fini(rdev);
1030         r600_pcie_gart_disable(rdev);
1031         radeon_gart_table_vram_free(rdev);
1032 }
1033
1034 void r600_agp_enable(struct radeon_device *rdev)
1035 {
1036         u32 tmp;
1037         int i;
1038
1039         /* Setup L2 cache */
1040         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1041                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1042                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1043         WREG32(VM_L2_CNTL2, 0);
1044         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1045         /* Setup TLB control */
1046         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1047                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1048                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1049                 ENABLE_WAIT_L2_QUERY;
1050         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1051         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1052         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1053         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1054         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1055         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1056         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1057         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1058         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1059         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1060         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1061         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1062         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1063         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1064         for (i = 0; i < 7; i++)
1065                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1066 }
1067
1068 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1069 {
1070         unsigned i;
1071         u32 tmp;
1072
1073         for (i = 0; i < rdev->usec_timeout; i++) {
1074                 /* read MC_STATUS */
1075                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1076                 if (!tmp)
1077                         return 0;
1078                 udelay(1);
1079         }
1080         return -1;
1081 }
1082
1083 static void r600_mc_program(struct radeon_device *rdev)
1084 {
1085         struct rv515_mc_save save;
1086         u32 tmp;
1087         int i, j;
1088
1089         /* Initialize HDP */
1090         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1091                 WREG32((0x2c14 + j), 0x00000000);
1092                 WREG32((0x2c18 + j), 0x00000000);
1093                 WREG32((0x2c1c + j), 0x00000000);
1094                 WREG32((0x2c20 + j), 0x00000000);
1095                 WREG32((0x2c24 + j), 0x00000000);
1096         }
1097         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1098
1099         rv515_mc_stop(rdev, &save);
1100         if (r600_mc_wait_for_idle(rdev)) {
1101                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1102         }
1103         /* Lockout access through VGA aperture (doesn't exist before R600) */
1104         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1105         /* Update configuration */
1106         if (rdev->flags & RADEON_IS_AGP) {
1107                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1108                         /* VRAM before AGP */
1109                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1110                                 rdev->mc.vram_start >> 12);
1111                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1112                                 rdev->mc.gtt_end >> 12);
1113                 } else {
1114                         /* VRAM after AGP */
1115                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1116                                 rdev->mc.gtt_start >> 12);
1117                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1118                                 rdev->mc.vram_end >> 12);
1119                 }
1120         } else {
1121                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1122                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1123         }
1124         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1125         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1126         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1127         WREG32(MC_VM_FB_LOCATION, tmp);
1128         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1129         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1130         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1131         if (rdev->flags & RADEON_IS_AGP) {
1132                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1133                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1134                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1135         } else {
1136                 WREG32(MC_VM_AGP_BASE, 0);
1137                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1138                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1139         }
1140         if (r600_mc_wait_for_idle(rdev)) {
1141                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1142         }
1143         rv515_mc_resume(rdev, &save);
1144         /* we need to own VRAM, so turn off the VGA renderer here
1145          * to stop it overwriting our objects */
1146         rv515_vga_render_disable(rdev);
1147 }
1148
1149 /**
1150  * r600_vram_gtt_location - try to find VRAM & GTT location
1151  * @rdev: radeon device structure holding all necessary informations
1152  * @mc: memory controller structure holding memory informations
1153  *
1154  * Function will place try to place VRAM at same place as in CPU (PCI)
1155  * address space as some GPU seems to have issue when we reprogram at
1156  * different address space.
1157  *
1158  * If there is not enough space to fit the unvisible VRAM after the
1159  * aperture then we limit the VRAM size to the aperture.
1160  *
1161  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1162  * them to be in one from GPU point of view so that we can program GPU to
1163  * catch access outside them (weird GPU policy see ??).
1164  *
1165  * This function will never fails, worst case are limiting VRAM or GTT.
1166  *
1167  * Note: GTT start, end, size should be initialized before calling this
1168  * function on AGP platform.
1169  */
1170 void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1171 {
1172         u64 size_bf, size_af;
1173
1174         if (mc->mc_vram_size > 0xE0000000) {
1175                 /* leave room for at least 512M GTT */
1176                 dev_warn(rdev->dev, "limiting VRAM\n");
1177                 mc->real_vram_size = 0xE0000000;
1178                 mc->mc_vram_size = 0xE0000000;
1179         }
1180         if (rdev->flags & RADEON_IS_AGP) {
1181                 size_bf = mc->gtt_start;
1182                 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1183                 if (size_bf > size_af) {
1184                         if (mc->mc_vram_size > size_bf) {
1185                                 dev_warn(rdev->dev, "limiting VRAM\n");
1186                                 mc->real_vram_size = size_bf;
1187                                 mc->mc_vram_size = size_bf;
1188                         }
1189                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1190                 } else {
1191                         if (mc->mc_vram_size > size_af) {
1192                                 dev_warn(rdev->dev, "limiting VRAM\n");
1193                                 mc->real_vram_size = size_af;
1194                                 mc->mc_vram_size = size_af;
1195                         }
1196                         mc->vram_start = mc->gtt_end;
1197                 }
1198                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1199                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1200                                 mc->mc_vram_size >> 20, mc->vram_start,
1201                                 mc->vram_end, mc->real_vram_size >> 20);
1202         } else {
1203                 u64 base = 0;
1204                 if (rdev->flags & RADEON_IS_IGP)
1205                         base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
1206                 radeon_vram_location(rdev, &rdev->mc, base);
1207                 rdev->mc.gtt_base_align = 0;
1208                 radeon_gtt_location(rdev, mc);
1209         }
1210 }
1211
1212 int r600_mc_init(struct radeon_device *rdev)
1213 {
1214         u32 tmp;
1215         int chansize, numchan;
1216
1217         /* Get VRAM informations */
1218         rdev->mc.vram_is_ddr = true;
1219         tmp = RREG32(RAMCFG);
1220         if (tmp & CHANSIZE_OVERRIDE) {
1221                 chansize = 16;
1222         } else if (tmp & CHANSIZE_MASK) {
1223                 chansize = 64;
1224         } else {
1225                 chansize = 32;
1226         }
1227         tmp = RREG32(CHMAP);
1228         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1229         case 0:
1230         default:
1231                 numchan = 1;
1232                 break;
1233         case 1:
1234                 numchan = 2;
1235                 break;
1236         case 2:
1237                 numchan = 4;
1238                 break;
1239         case 3:
1240                 numchan = 8;
1241                 break;
1242         }
1243         rdev->mc.vram_width = numchan * chansize;
1244         /* Could aper size report 0 ? */
1245         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1246         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1247         /* Setup GPU memory space */
1248         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1249         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1250         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1251         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1252         r600_vram_gtt_location(rdev, &rdev->mc);
1253
1254         if (rdev->flags & RADEON_IS_IGP) {
1255                 rs690_pm_info(rdev);
1256                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1257         }
1258         radeon_update_bandwidth_info(rdev);
1259         return 0;
1260 }
1261
1262 /* We doesn't check that the GPU really needs a reset we simply do the
1263  * reset, it's up to the caller to determine if the GPU needs one. We
1264  * might add an helper function to check that.
1265  */
1266 int r600_gpu_soft_reset(struct radeon_device *rdev)
1267 {
1268         struct rv515_mc_save save;
1269         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1270                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1271                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1272                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1273                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1274                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1275                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1276                                 S_008010_GUI_ACTIVE(1);
1277         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1278                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1279                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1280                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1281                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1282                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1283                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1284                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1285         u32 tmp;
1286
1287         dev_info(rdev->dev, "GPU softreset \n");
1288         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1289                 RREG32(R_008010_GRBM_STATUS));
1290         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1291                 RREG32(R_008014_GRBM_STATUS2));
1292         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1293                 RREG32(R_000E50_SRBM_STATUS));
1294         rv515_mc_stop(rdev, &save);
1295         if (r600_mc_wait_for_idle(rdev)) {
1296                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1297         }
1298         /* Disable CP parsing/prefetching */
1299         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1300         /* Check if any of the rendering block is busy and reset it */
1301         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1302             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1303                 tmp = S_008020_SOFT_RESET_CR(1) |
1304                         S_008020_SOFT_RESET_DB(1) |
1305                         S_008020_SOFT_RESET_CB(1) |
1306                         S_008020_SOFT_RESET_PA(1) |
1307                         S_008020_SOFT_RESET_SC(1) |
1308                         S_008020_SOFT_RESET_SMX(1) |
1309                         S_008020_SOFT_RESET_SPI(1) |
1310                         S_008020_SOFT_RESET_SX(1) |
1311                         S_008020_SOFT_RESET_SH(1) |
1312                         S_008020_SOFT_RESET_TC(1) |
1313                         S_008020_SOFT_RESET_TA(1) |
1314                         S_008020_SOFT_RESET_VC(1) |
1315                         S_008020_SOFT_RESET_VGT(1);
1316                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1317                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1318                 RREG32(R_008020_GRBM_SOFT_RESET);
1319                 mdelay(15);
1320                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1321         }
1322         /* Reset CP (we always reset CP) */
1323         tmp = S_008020_SOFT_RESET_CP(1);
1324         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1325         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1326         RREG32(R_008020_GRBM_SOFT_RESET);
1327         mdelay(15);
1328         WREG32(R_008020_GRBM_SOFT_RESET, 0);
1329         /* Wait a little for things to settle down */
1330         mdelay(1);
1331         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1332                 RREG32(R_008010_GRBM_STATUS));
1333         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1334                 RREG32(R_008014_GRBM_STATUS2));
1335         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1336                 RREG32(R_000E50_SRBM_STATUS));
1337         rv515_mc_resume(rdev, &save);
1338         return 0;
1339 }
1340
1341 bool r600_gpu_is_lockup(struct radeon_device *rdev)
1342 {
1343         u32 srbm_status;
1344         u32 grbm_status;
1345         u32 grbm_status2;
1346         int r;
1347
1348         srbm_status = RREG32(R_000E50_SRBM_STATUS);
1349         grbm_status = RREG32(R_008010_GRBM_STATUS);
1350         grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1351         if (!G_008010_GUI_ACTIVE(grbm_status)) {
1352                 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
1353                 return false;
1354         }
1355         /* force CP activities */
1356         r = radeon_ring_lock(rdev, 2);
1357         if (!r) {
1358                 /* PACKET2 NOP */
1359                 radeon_ring_write(rdev, 0x80000000);
1360                 radeon_ring_write(rdev, 0x80000000);
1361                 radeon_ring_unlock_commit(rdev);
1362         }
1363         rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1364         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
1365 }
1366
1367 int r600_asic_reset(struct radeon_device *rdev)
1368 {
1369         return r600_gpu_soft_reset(rdev);
1370 }
1371
1372 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1373                                              u32 num_backends,
1374                                              u32 backend_disable_mask)
1375 {
1376         u32 backend_map = 0;
1377         u32 enabled_backends_mask;
1378         u32 enabled_backends_count;
1379         u32 cur_pipe;
1380         u32 swizzle_pipe[R6XX_MAX_PIPES];
1381         u32 cur_backend;
1382         u32 i;
1383
1384         if (num_tile_pipes > R6XX_MAX_PIPES)
1385                 num_tile_pipes = R6XX_MAX_PIPES;
1386         if (num_tile_pipes < 1)
1387                 num_tile_pipes = 1;
1388         if (num_backends > R6XX_MAX_BACKENDS)
1389                 num_backends = R6XX_MAX_BACKENDS;
1390         if (num_backends < 1)
1391                 num_backends = 1;
1392
1393         enabled_backends_mask = 0;
1394         enabled_backends_count = 0;
1395         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1396                 if (((backend_disable_mask >> i) & 1) == 0) {
1397                         enabled_backends_mask |= (1 << i);
1398                         ++enabled_backends_count;
1399                 }
1400                 if (enabled_backends_count == num_backends)
1401                         break;
1402         }
1403
1404         if (enabled_backends_count == 0) {
1405                 enabled_backends_mask = 1;
1406                 enabled_backends_count = 1;
1407         }
1408
1409         if (enabled_backends_count != num_backends)
1410                 num_backends = enabled_backends_count;
1411
1412         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1413         switch (num_tile_pipes) {
1414         case 1:
1415                 swizzle_pipe[0] = 0;
1416                 break;
1417         case 2:
1418                 swizzle_pipe[0] = 0;
1419                 swizzle_pipe[1] = 1;
1420                 break;
1421         case 3:
1422                 swizzle_pipe[0] = 0;
1423                 swizzle_pipe[1] = 1;
1424                 swizzle_pipe[2] = 2;
1425                 break;
1426         case 4:
1427                 swizzle_pipe[0] = 0;
1428                 swizzle_pipe[1] = 1;
1429                 swizzle_pipe[2] = 2;
1430                 swizzle_pipe[3] = 3;
1431                 break;
1432         case 5:
1433                 swizzle_pipe[0] = 0;
1434                 swizzle_pipe[1] = 1;
1435                 swizzle_pipe[2] = 2;
1436                 swizzle_pipe[3] = 3;
1437                 swizzle_pipe[4] = 4;
1438                 break;
1439         case 6:
1440                 swizzle_pipe[0] = 0;
1441                 swizzle_pipe[1] = 2;
1442                 swizzle_pipe[2] = 4;
1443                 swizzle_pipe[3] = 5;
1444                 swizzle_pipe[4] = 1;
1445                 swizzle_pipe[5] = 3;
1446                 break;
1447         case 7:
1448                 swizzle_pipe[0] = 0;
1449                 swizzle_pipe[1] = 2;
1450                 swizzle_pipe[2] = 4;
1451                 swizzle_pipe[3] = 6;
1452                 swizzle_pipe[4] = 1;
1453                 swizzle_pipe[5] = 3;
1454                 swizzle_pipe[6] = 5;
1455                 break;
1456         case 8:
1457                 swizzle_pipe[0] = 0;
1458                 swizzle_pipe[1] = 2;
1459                 swizzle_pipe[2] = 4;
1460                 swizzle_pipe[3] = 6;
1461                 swizzle_pipe[4] = 1;
1462                 swizzle_pipe[5] = 3;
1463                 swizzle_pipe[6] = 5;
1464                 swizzle_pipe[7] = 7;
1465                 break;
1466         }
1467
1468         cur_backend = 0;
1469         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1470                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1471                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1472
1473                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1474
1475                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1476         }
1477
1478         return backend_map;
1479 }
1480
1481 int r600_count_pipe_bits(uint32_t val)
1482 {
1483         int i, ret = 0;
1484
1485         for (i = 0; i < 32; i++) {
1486                 ret += val & 1;
1487                 val >>= 1;
1488         }
1489         return ret;
1490 }
1491
1492 void r600_gpu_init(struct radeon_device *rdev)
1493 {
1494         u32 tiling_config;
1495         u32 ramcfg;
1496         u32 backend_map;
1497         u32 cc_rb_backend_disable;
1498         u32 cc_gc_shader_pipe_config;
1499         u32 tmp;
1500         int i, j;
1501         u32 sq_config;
1502         u32 sq_gpr_resource_mgmt_1 = 0;
1503         u32 sq_gpr_resource_mgmt_2 = 0;
1504         u32 sq_thread_resource_mgmt = 0;
1505         u32 sq_stack_resource_mgmt_1 = 0;
1506         u32 sq_stack_resource_mgmt_2 = 0;
1507
1508         /* FIXME: implement */
1509         switch (rdev->family) {
1510         case CHIP_R600:
1511                 rdev->config.r600.max_pipes = 4;
1512                 rdev->config.r600.max_tile_pipes = 8;
1513                 rdev->config.r600.max_simds = 4;
1514                 rdev->config.r600.max_backends = 4;
1515                 rdev->config.r600.max_gprs = 256;
1516                 rdev->config.r600.max_threads = 192;
1517                 rdev->config.r600.max_stack_entries = 256;
1518                 rdev->config.r600.max_hw_contexts = 8;
1519                 rdev->config.r600.max_gs_threads = 16;
1520                 rdev->config.r600.sx_max_export_size = 128;
1521                 rdev->config.r600.sx_max_export_pos_size = 16;
1522                 rdev->config.r600.sx_max_export_smx_size = 128;
1523                 rdev->config.r600.sq_num_cf_insts = 2;
1524                 break;
1525         case CHIP_RV630:
1526         case CHIP_RV635:
1527                 rdev->config.r600.max_pipes = 2;
1528                 rdev->config.r600.max_tile_pipes = 2;
1529                 rdev->config.r600.max_simds = 3;
1530                 rdev->config.r600.max_backends = 1;
1531                 rdev->config.r600.max_gprs = 128;
1532                 rdev->config.r600.max_threads = 192;
1533                 rdev->config.r600.max_stack_entries = 128;
1534                 rdev->config.r600.max_hw_contexts = 8;
1535                 rdev->config.r600.max_gs_threads = 4;
1536                 rdev->config.r600.sx_max_export_size = 128;
1537                 rdev->config.r600.sx_max_export_pos_size = 16;
1538                 rdev->config.r600.sx_max_export_smx_size = 128;
1539                 rdev->config.r600.sq_num_cf_insts = 2;
1540                 break;
1541         case CHIP_RV610:
1542         case CHIP_RV620:
1543         case CHIP_RS780:
1544         case CHIP_RS880:
1545                 rdev->config.r600.max_pipes = 1;
1546                 rdev->config.r600.max_tile_pipes = 1;
1547                 rdev->config.r600.max_simds = 2;
1548                 rdev->config.r600.max_backends = 1;
1549                 rdev->config.r600.max_gprs = 128;
1550                 rdev->config.r600.max_threads = 192;
1551                 rdev->config.r600.max_stack_entries = 128;
1552                 rdev->config.r600.max_hw_contexts = 4;
1553                 rdev->config.r600.max_gs_threads = 4;
1554                 rdev->config.r600.sx_max_export_size = 128;
1555                 rdev->config.r600.sx_max_export_pos_size = 16;
1556                 rdev->config.r600.sx_max_export_smx_size = 128;
1557                 rdev->config.r600.sq_num_cf_insts = 1;
1558                 break;
1559         case CHIP_RV670:
1560                 rdev->config.r600.max_pipes = 4;
1561                 rdev->config.r600.max_tile_pipes = 4;
1562                 rdev->config.r600.max_simds = 4;
1563                 rdev->config.r600.max_backends = 4;
1564                 rdev->config.r600.max_gprs = 192;
1565                 rdev->config.r600.max_threads = 192;
1566                 rdev->config.r600.max_stack_entries = 256;
1567                 rdev->config.r600.max_hw_contexts = 8;
1568                 rdev->config.r600.max_gs_threads = 16;
1569                 rdev->config.r600.sx_max_export_size = 128;
1570                 rdev->config.r600.sx_max_export_pos_size = 16;
1571                 rdev->config.r600.sx_max_export_smx_size = 128;
1572                 rdev->config.r600.sq_num_cf_insts = 2;
1573                 break;
1574         default:
1575                 break;
1576         }
1577
1578         /* Initialize HDP */
1579         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1580                 WREG32((0x2c14 + j), 0x00000000);
1581                 WREG32((0x2c18 + j), 0x00000000);
1582                 WREG32((0x2c1c + j), 0x00000000);
1583                 WREG32((0x2c20 + j), 0x00000000);
1584                 WREG32((0x2c24 + j), 0x00000000);
1585         }
1586
1587         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1588
1589         /* Setup tiling */
1590         tiling_config = 0;
1591         ramcfg = RREG32(RAMCFG);
1592         switch (rdev->config.r600.max_tile_pipes) {
1593         case 1:
1594                 tiling_config |= PIPE_TILING(0);
1595                 break;
1596         case 2:
1597                 tiling_config |= PIPE_TILING(1);
1598                 break;
1599         case 4:
1600                 tiling_config |= PIPE_TILING(2);
1601                 break;
1602         case 8:
1603                 tiling_config |= PIPE_TILING(3);
1604                 break;
1605         default:
1606                 break;
1607         }
1608         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1609         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1610         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1611         tiling_config |= GROUP_SIZE(0);
1612         rdev->config.r600.tiling_group_size = 256;
1613         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1614         if (tmp > 3) {
1615                 tiling_config |= ROW_TILING(3);
1616                 tiling_config |= SAMPLE_SPLIT(3);
1617         } else {
1618                 tiling_config |= ROW_TILING(tmp);
1619                 tiling_config |= SAMPLE_SPLIT(tmp);
1620         }
1621         tiling_config |= BANK_SWAPS(1);
1622
1623         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1624         cc_rb_backend_disable |=
1625                 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1626
1627         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1628         cc_gc_shader_pipe_config |=
1629                 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1630         cc_gc_shader_pipe_config |=
1631                 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1632
1633         backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1634                                                         (R6XX_MAX_BACKENDS -
1635                                                          r600_count_pipe_bits((cc_rb_backend_disable &
1636                                                                                R6XX_MAX_BACKENDS_MASK) >> 16)),
1637                                                         (cc_rb_backend_disable >> 16));
1638         rdev->config.r600.tile_config = tiling_config;
1639         tiling_config |= BACKEND_MAP(backend_map);
1640         WREG32(GB_TILING_CONFIG, tiling_config);
1641         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1642         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1643
1644         /* Setup pipes */
1645         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1646         WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1647         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1648
1649         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1650         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1651         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1652
1653         /* Setup some CP states */
1654         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1655         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1656
1657         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1658                              SYNC_WALKER | SYNC_ALIGNER));
1659         /* Setup various GPU states */
1660         if (rdev->family == CHIP_RV670)
1661                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1662
1663         tmp = RREG32(SX_DEBUG_1);
1664         tmp |= SMX_EVENT_RELEASE;
1665         if ((rdev->family > CHIP_R600))
1666                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1667         WREG32(SX_DEBUG_1, tmp);
1668
1669         if (((rdev->family) == CHIP_R600) ||
1670             ((rdev->family) == CHIP_RV630) ||
1671             ((rdev->family) == CHIP_RV610) ||
1672             ((rdev->family) == CHIP_RV620) ||
1673             ((rdev->family) == CHIP_RS780) ||
1674             ((rdev->family) == CHIP_RS880)) {
1675                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1676         } else {
1677                 WREG32(DB_DEBUG, 0);
1678         }
1679         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1680                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1681
1682         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1683         WREG32(VGT_NUM_INSTANCES, 0);
1684
1685         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1686         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1687
1688         tmp = RREG32(SQ_MS_FIFO_SIZES);
1689         if (((rdev->family) == CHIP_RV610) ||
1690             ((rdev->family) == CHIP_RV620) ||
1691             ((rdev->family) == CHIP_RS780) ||
1692             ((rdev->family) == CHIP_RS880)) {
1693                 tmp = (CACHE_FIFO_SIZE(0xa) |
1694                        FETCH_FIFO_HIWATER(0xa) |
1695                        DONE_FIFO_HIWATER(0xe0) |
1696                        ALU_UPDATE_FIFO_HIWATER(0x8));
1697         } else if (((rdev->family) == CHIP_R600) ||
1698                    ((rdev->family) == CHIP_RV630)) {
1699                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1700                 tmp |= DONE_FIFO_HIWATER(0x4);
1701         }
1702         WREG32(SQ_MS_FIFO_SIZES, tmp);
1703
1704         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1705          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1706          */
1707         sq_config = RREG32(SQ_CONFIG);
1708         sq_config &= ~(PS_PRIO(3) |
1709                        VS_PRIO(3) |
1710                        GS_PRIO(3) |
1711                        ES_PRIO(3));
1712         sq_config |= (DX9_CONSTS |
1713                       VC_ENABLE |
1714                       PS_PRIO(0) |
1715                       VS_PRIO(1) |
1716                       GS_PRIO(2) |
1717                       ES_PRIO(3));
1718
1719         if ((rdev->family) == CHIP_R600) {
1720                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1721                                           NUM_VS_GPRS(124) |
1722                                           NUM_CLAUSE_TEMP_GPRS(4));
1723                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1724                                           NUM_ES_GPRS(0));
1725                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1726                                            NUM_VS_THREADS(48) |
1727                                            NUM_GS_THREADS(4) |
1728                                            NUM_ES_THREADS(4));
1729                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1730                                             NUM_VS_STACK_ENTRIES(128));
1731                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1732                                             NUM_ES_STACK_ENTRIES(0));
1733         } else if (((rdev->family) == CHIP_RV610) ||
1734                    ((rdev->family) == CHIP_RV620) ||
1735                    ((rdev->family) == CHIP_RS780) ||
1736                    ((rdev->family) == CHIP_RS880)) {
1737                 /* no vertex cache */
1738                 sq_config &= ~VC_ENABLE;
1739
1740                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1741                                           NUM_VS_GPRS(44) |
1742                                           NUM_CLAUSE_TEMP_GPRS(2));
1743                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1744                                           NUM_ES_GPRS(17));
1745                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1746                                            NUM_VS_THREADS(78) |
1747                                            NUM_GS_THREADS(4) |
1748                                            NUM_ES_THREADS(31));
1749                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1750                                             NUM_VS_STACK_ENTRIES(40));
1751                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1752                                             NUM_ES_STACK_ENTRIES(16));
1753         } else if (((rdev->family) == CHIP_RV630) ||
1754                    ((rdev->family) == CHIP_RV635)) {
1755                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1756                                           NUM_VS_GPRS(44) |
1757                                           NUM_CLAUSE_TEMP_GPRS(2));
1758                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1759                                           NUM_ES_GPRS(18));
1760                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1761                                            NUM_VS_THREADS(78) |
1762                                            NUM_GS_THREADS(4) |
1763                                            NUM_ES_THREADS(31));
1764                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1765                                             NUM_VS_STACK_ENTRIES(40));
1766                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1767                                             NUM_ES_STACK_ENTRIES(16));
1768         } else if ((rdev->family) == CHIP_RV670) {
1769                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1770                                           NUM_VS_GPRS(44) |
1771                                           NUM_CLAUSE_TEMP_GPRS(2));
1772                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1773                                           NUM_ES_GPRS(17));
1774                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1775                                            NUM_VS_THREADS(78) |
1776                                            NUM_GS_THREADS(4) |
1777                                            NUM_ES_THREADS(31));
1778                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1779                                             NUM_VS_STACK_ENTRIES(64));
1780                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1781                                             NUM_ES_STACK_ENTRIES(64));
1782         }
1783
1784         WREG32(SQ_CONFIG, sq_config);
1785         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1786         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1787         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1788         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1789         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1790
1791         if (((rdev->family) == CHIP_RV610) ||
1792             ((rdev->family) == CHIP_RV620) ||
1793             ((rdev->family) == CHIP_RS780) ||
1794             ((rdev->family) == CHIP_RS880)) {
1795                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1796         } else {
1797                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1798         }
1799
1800         /* More default values. 2D/3D driver should adjust as needed */
1801         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1802                                          S1_X(0x4) | S1_Y(0xc)));
1803         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1804                                          S1_X(0x2) | S1_Y(0x2) |
1805                                          S2_X(0xa) | S2_Y(0x6) |
1806                                          S3_X(0x6) | S3_Y(0xa)));
1807         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1808                                              S1_X(0x4) | S1_Y(0xc) |
1809                                              S2_X(0x1) | S2_Y(0x6) |
1810                                              S3_X(0xa) | S3_Y(0xe)));
1811         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1812                                              S5_X(0x0) | S5_Y(0x0) |
1813                                              S6_X(0xb) | S6_Y(0x4) |
1814                                              S7_X(0x7) | S7_Y(0x8)));
1815
1816         WREG32(VGT_STRMOUT_EN, 0);
1817         tmp = rdev->config.r600.max_pipes * 16;
1818         switch (rdev->family) {
1819         case CHIP_RV610:
1820         case CHIP_RV620:
1821         case CHIP_RS780:
1822         case CHIP_RS880:
1823                 tmp += 32;
1824                 break;
1825         case CHIP_RV670:
1826                 tmp += 128;
1827                 break;
1828         default:
1829                 break;
1830         }
1831         if (tmp > 256) {
1832                 tmp = 256;
1833         }
1834         WREG32(VGT_ES_PER_GS, 128);
1835         WREG32(VGT_GS_PER_ES, tmp);
1836         WREG32(VGT_GS_PER_VS, 2);
1837         WREG32(VGT_GS_VERTEX_REUSE, 16);
1838
1839         /* more default values. 2D/3D driver should adjust as needed */
1840         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1841         WREG32(VGT_STRMOUT_EN, 0);
1842         WREG32(SX_MISC, 0);
1843         WREG32(PA_SC_MODE_CNTL, 0);
1844         WREG32(PA_SC_AA_CONFIG, 0);
1845         WREG32(PA_SC_LINE_STIPPLE, 0);
1846         WREG32(SPI_INPUT_Z, 0);
1847         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1848         WREG32(CB_COLOR7_FRAG, 0);
1849
1850         /* Clear render buffer base addresses */
1851         WREG32(CB_COLOR0_BASE, 0);
1852         WREG32(CB_COLOR1_BASE, 0);
1853         WREG32(CB_COLOR2_BASE, 0);
1854         WREG32(CB_COLOR3_BASE, 0);
1855         WREG32(CB_COLOR4_BASE, 0);
1856         WREG32(CB_COLOR5_BASE, 0);
1857         WREG32(CB_COLOR6_BASE, 0);
1858         WREG32(CB_COLOR7_BASE, 0);
1859         WREG32(CB_COLOR7_FRAG, 0);
1860
1861         switch (rdev->family) {
1862         case CHIP_RV610:
1863         case CHIP_RV620:
1864         case CHIP_RS780:
1865         case CHIP_RS880:
1866                 tmp = TC_L2_SIZE(8);
1867                 break;
1868         case CHIP_RV630:
1869         case CHIP_RV635:
1870                 tmp = TC_L2_SIZE(4);
1871                 break;
1872         case CHIP_R600:
1873                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1874                 break;
1875         default:
1876                 tmp = TC_L2_SIZE(0);
1877                 break;
1878         }
1879         WREG32(TC_CNTL, tmp);
1880
1881         tmp = RREG32(HDP_HOST_PATH_CNTL);
1882         WREG32(HDP_HOST_PATH_CNTL, tmp);
1883
1884         tmp = RREG32(ARB_POP);
1885         tmp |= ENABLE_TC128;
1886         WREG32(ARB_POP, tmp);
1887
1888         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1889         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1890                                NUM_CLIP_SEQ(3)));
1891         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1892 }
1893
1894
1895 /*
1896  * Indirect registers accessor
1897  */
1898 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1899 {
1900         u32 r;
1901
1902         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1903         (void)RREG32(PCIE_PORT_INDEX);
1904         r = RREG32(PCIE_PORT_DATA);
1905         return r;
1906 }
1907
1908 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1909 {
1910         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1911         (void)RREG32(PCIE_PORT_INDEX);
1912         WREG32(PCIE_PORT_DATA, (v));
1913         (void)RREG32(PCIE_PORT_DATA);
1914 }
1915
1916 /*
1917  * CP & Ring
1918  */
1919 void r600_cp_stop(struct radeon_device *rdev)
1920 {
1921         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1922         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1923         WREG32(SCRATCH_UMSK, 0);
1924 }
1925
1926 int r600_init_microcode(struct radeon_device *rdev)
1927 {
1928         struct platform_device *pdev;
1929         const char *chip_name;
1930         const char *rlc_chip_name;
1931         size_t pfp_req_size, me_req_size, rlc_req_size;
1932         char fw_name[30];
1933         int err;
1934
1935         DRM_DEBUG("\n");
1936
1937         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1938         err = IS_ERR(pdev);
1939         if (err) {
1940                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1941                 return -EINVAL;
1942         }
1943
1944         switch (rdev->family) {
1945         case CHIP_R600:
1946                 chip_name = "R600";
1947                 rlc_chip_name = "R600";
1948                 break;
1949         case CHIP_RV610:
1950                 chip_name = "RV610";
1951                 rlc_chip_name = "R600";
1952                 break;
1953         case CHIP_RV630:
1954                 chip_name = "RV630";
1955                 rlc_chip_name = "R600";
1956                 break;
1957         case CHIP_RV620:
1958                 chip_name = "RV620";
1959                 rlc_chip_name = "R600";
1960                 break;
1961         case CHIP_RV635:
1962                 chip_name = "RV635";
1963                 rlc_chip_name = "R600";
1964                 break;
1965         case CHIP_RV670:
1966                 chip_name = "RV670";
1967                 rlc_chip_name = "R600";
1968                 break;
1969         case CHIP_RS780:
1970         case CHIP_RS880:
1971                 chip_name = "RS780";
1972                 rlc_chip_name = "R600";
1973                 break;
1974         case CHIP_RV770:
1975                 chip_name = "RV770";
1976                 rlc_chip_name = "R700";
1977                 break;
1978         case CHIP_RV730:
1979         case CHIP_RV740:
1980                 chip_name = "RV730";
1981                 rlc_chip_name = "R700";
1982                 break;
1983         case CHIP_RV710:
1984                 chip_name = "RV710";
1985                 rlc_chip_name = "R700";
1986                 break;
1987         case CHIP_CEDAR:
1988                 chip_name = "CEDAR";
1989                 rlc_chip_name = "CEDAR";
1990                 break;
1991         case CHIP_REDWOOD:
1992                 chip_name = "REDWOOD";
1993                 rlc_chip_name = "REDWOOD";
1994                 break;
1995         case CHIP_JUNIPER:
1996                 chip_name = "JUNIPER";
1997                 rlc_chip_name = "JUNIPER";
1998                 break;
1999         case CHIP_CYPRESS:
2000         case CHIP_HEMLOCK:
2001                 chip_name = "CYPRESS";
2002                 rlc_chip_name = "CYPRESS";
2003                 break;
2004         default: BUG();
2005         }
2006
2007         if (rdev->family >= CHIP_CEDAR) {
2008                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2009                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2010                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2011         } else if (rdev->family >= CHIP_RV770) {
2012                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2013                 me_req_size = R700_PM4_UCODE_SIZE * 4;
2014                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2015         } else {
2016                 pfp_req_size = PFP_UCODE_SIZE * 4;
2017                 me_req_size = PM4_UCODE_SIZE * 12;
2018                 rlc_req_size = RLC_UCODE_SIZE * 4;
2019         }
2020
2021         DRM_INFO("Loading %s Microcode\n", chip_name);
2022
2023         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2024         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2025         if (err)
2026                 goto out;
2027         if (rdev->pfp_fw->size != pfp_req_size) {
2028                 printk(KERN_ERR
2029                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2030                        rdev->pfp_fw->size, fw_name);
2031                 err = -EINVAL;
2032                 goto out;
2033         }
2034
2035         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2036         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2037         if (err)
2038                 goto out;
2039         if (rdev->me_fw->size != me_req_size) {
2040                 printk(KERN_ERR
2041                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2042                        rdev->me_fw->size, fw_name);
2043                 err = -EINVAL;
2044         }
2045
2046         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2047         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2048         if (err)
2049                 goto out;
2050         if (rdev->rlc_fw->size != rlc_req_size) {
2051                 printk(KERN_ERR
2052                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2053                        rdev->rlc_fw->size, fw_name);
2054                 err = -EINVAL;
2055         }
2056
2057 out:
2058         platform_device_unregister(pdev);
2059
2060         if (err) {
2061                 if (err != -EINVAL)
2062                         printk(KERN_ERR
2063                                "r600_cp: Failed to load firmware \"%s\"\n",
2064                                fw_name);
2065                 release_firmware(rdev->pfp_fw);
2066                 rdev->pfp_fw = NULL;
2067                 release_firmware(rdev->me_fw);
2068                 rdev->me_fw = NULL;
2069                 release_firmware(rdev->rlc_fw);
2070                 rdev->rlc_fw = NULL;
2071         }
2072         return err;
2073 }
2074
2075 static int r600_cp_load_microcode(struct radeon_device *rdev)
2076 {
2077         const __be32 *fw_data;
2078         int i;
2079
2080         if (!rdev->me_fw || !rdev->pfp_fw)
2081                 return -EINVAL;
2082
2083         r600_cp_stop(rdev);
2084
2085         WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2086
2087         /* Reset cp */
2088         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2089         RREG32(GRBM_SOFT_RESET);
2090         mdelay(15);
2091         WREG32(GRBM_SOFT_RESET, 0);
2092
2093         WREG32(CP_ME_RAM_WADDR, 0);
2094
2095         fw_data = (const __be32 *)rdev->me_fw->data;
2096         WREG32(CP_ME_RAM_WADDR, 0);
2097         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2098                 WREG32(CP_ME_RAM_DATA,
2099                        be32_to_cpup(fw_data++));
2100
2101         fw_data = (const __be32 *)rdev->pfp_fw->data;
2102         WREG32(CP_PFP_UCODE_ADDR, 0);
2103         for (i = 0; i < PFP_UCODE_SIZE; i++)
2104                 WREG32(CP_PFP_UCODE_DATA,
2105                        be32_to_cpup(fw_data++));
2106
2107         WREG32(CP_PFP_UCODE_ADDR, 0);
2108         WREG32(CP_ME_RAM_WADDR, 0);
2109         WREG32(CP_ME_RAM_RADDR, 0);
2110         return 0;
2111 }
2112
2113 int r600_cp_start(struct radeon_device *rdev)
2114 {
2115         int r;
2116         uint32_t cp_me;
2117
2118         r = radeon_ring_lock(rdev, 7);
2119         if (r) {
2120                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2121                 return r;
2122         }
2123         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2124         radeon_ring_write(rdev, 0x1);
2125         if (rdev->family >= CHIP_RV770) {
2126                 radeon_ring_write(rdev, 0x0);
2127                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
2128         } else {
2129                 radeon_ring_write(rdev, 0x3);
2130                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
2131         }
2132         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2133         radeon_ring_write(rdev, 0);
2134         radeon_ring_write(rdev, 0);
2135         radeon_ring_unlock_commit(rdev);
2136
2137         cp_me = 0xff;
2138         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2139         return 0;
2140 }
2141
2142 int r600_cp_resume(struct radeon_device *rdev)
2143 {
2144         u32 tmp;
2145         u32 rb_bufsz;
2146         int r;
2147
2148         /* Reset cp */
2149         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2150         RREG32(GRBM_SOFT_RESET);
2151         mdelay(15);
2152         WREG32(GRBM_SOFT_RESET, 0);
2153
2154         /* Set ring buffer size */
2155         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
2156         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2157 #ifdef __BIG_ENDIAN
2158         tmp |= BUF_SWAP_32BIT;
2159 #endif
2160         WREG32(CP_RB_CNTL, tmp);
2161         WREG32(CP_SEM_WAIT_TIMER, 0x4);
2162
2163         /* Set the write pointer delay */
2164         WREG32(CP_RB_WPTR_DELAY, 0);
2165
2166         /* Initialize the ring buffer's read and write pointers */
2167         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2168         WREG32(CP_RB_RPTR_WR, 0);
2169         WREG32(CP_RB_WPTR, 0);
2170
2171         /* set the wb address whether it's enabled or not */
2172         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
2173         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2174         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2175
2176         if (rdev->wb.enabled)
2177                 WREG32(SCRATCH_UMSK, 0xff);
2178         else {
2179                 tmp |= RB_NO_UPDATE;
2180                 WREG32(SCRATCH_UMSK, 0);
2181         }
2182
2183         mdelay(1);
2184         WREG32(CP_RB_CNTL, tmp);
2185
2186         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2187         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2188
2189         rdev->cp.rptr = RREG32(CP_RB_RPTR);
2190         rdev->cp.wptr = RREG32(CP_RB_WPTR);
2191
2192         r600_cp_start(rdev);
2193         rdev->cp.ready = true;
2194         r = radeon_ring_test(rdev);
2195         if (r) {
2196                 rdev->cp.ready = false;
2197                 return r;
2198         }
2199         return 0;
2200 }
2201
2202 void r600_cp_commit(struct radeon_device *rdev)
2203 {
2204         WREG32(CP_RB_WPTR, rdev->cp.wptr);
2205         (void)RREG32(CP_RB_WPTR);
2206 }
2207
2208 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2209 {
2210         u32 rb_bufsz;
2211
2212         /* Align ring size */
2213         rb_bufsz = drm_order(ring_size / 8);
2214         ring_size = (1 << (rb_bufsz + 1)) * 4;
2215         rdev->cp.ring_size = ring_size;
2216         rdev->cp.align_mask = 16 - 1;
2217 }
2218
2219 void r600_cp_fini(struct radeon_device *rdev)
2220 {
2221         r600_cp_stop(rdev);
2222         radeon_ring_fini(rdev);
2223 }
2224
2225
2226 /*
2227  * GPU scratch registers helpers function.
2228  */
2229 void r600_scratch_init(struct radeon_device *rdev)
2230 {
2231         int i;
2232
2233         rdev->scratch.num_reg = 7;
2234         rdev->scratch.reg_base = SCRATCH_REG0;
2235         for (i = 0; i < rdev->scratch.num_reg; i++) {
2236                 rdev->scratch.free[i] = true;
2237                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2238         }
2239 }
2240
2241 int r600_ring_test(struct radeon_device *rdev)
2242 {
2243         uint32_t scratch;
2244         uint32_t tmp = 0;
2245         unsigned i;
2246         int r;
2247
2248         r = radeon_scratch_get(rdev, &scratch);
2249         if (r) {
2250                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2251                 return r;
2252         }
2253         WREG32(scratch, 0xCAFEDEAD);
2254         r = radeon_ring_lock(rdev, 3);
2255         if (r) {
2256                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2257                 radeon_scratch_free(rdev, scratch);
2258                 return r;
2259         }
2260         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2261         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2262         radeon_ring_write(rdev, 0xDEADBEEF);
2263         radeon_ring_unlock_commit(rdev);
2264         for (i = 0; i < rdev->usec_timeout; i++) {
2265                 tmp = RREG32(scratch);
2266                 if (tmp == 0xDEADBEEF)
2267                         break;
2268                 DRM_UDELAY(1);
2269         }
2270         if (i < rdev->usec_timeout) {
2271                 DRM_INFO("ring test succeeded in %d usecs\n", i);
2272         } else {
2273                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2274                           scratch, tmp);
2275                 r = -EINVAL;
2276         }
2277         radeon_scratch_free(rdev, scratch);
2278         return r;
2279 }
2280
2281 void r600_fence_ring_emit(struct radeon_device *rdev,
2282                           struct radeon_fence *fence)
2283 {
2284         if (rdev->wb.use_event) {
2285                 u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET +
2286                         (u64)(rdev->fence_drv.scratch_reg - rdev->scratch.reg_base);
2287                 /* EVENT_WRITE_EOP - flush caches, send int */
2288                 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2289                 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2290                 radeon_ring_write(rdev, addr & 0xffffffff);
2291                 radeon_ring_write(rdev, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2292                 radeon_ring_write(rdev, fence->seq);
2293                 radeon_ring_write(rdev, 0);
2294         } else {
2295                 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2296                 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2297                 /* wait for 3D idle clean */
2298                 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2299                 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2300                 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2301                 /* Emit fence sequence & fire IRQ */
2302                 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2303                 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2304                 radeon_ring_write(rdev, fence->seq);
2305                 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2306                 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2307                 radeon_ring_write(rdev, RB_INT_STAT);
2308         }
2309 }
2310
2311 int r600_copy_blit(struct radeon_device *rdev,
2312                    uint64_t src_offset, uint64_t dst_offset,
2313                    unsigned num_pages, struct radeon_fence *fence)
2314 {
2315         int r;
2316
2317         mutex_lock(&rdev->r600_blit.mutex);
2318         rdev->r600_blit.vb_ib = NULL;
2319         r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2320         if (r) {
2321                 if (rdev->r600_blit.vb_ib)
2322                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2323                 mutex_unlock(&rdev->r600_blit.mutex);
2324                 return r;
2325         }
2326         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2327         r600_blit_done_copy(rdev, fence);
2328         mutex_unlock(&rdev->r600_blit.mutex);
2329         return 0;
2330 }
2331
2332 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2333                          uint32_t tiling_flags, uint32_t pitch,
2334                          uint32_t offset, uint32_t obj_size)
2335 {
2336         /* FIXME: implement */
2337         return 0;
2338 }
2339
2340 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2341 {
2342         /* FIXME: implement */
2343 }
2344
2345
2346 bool r600_card_posted(struct radeon_device *rdev)
2347 {
2348         uint32_t reg;
2349
2350         /* first check CRTCs */
2351         reg = RREG32(D1CRTC_CONTROL) |
2352                 RREG32(D2CRTC_CONTROL);
2353         if (reg & CRTC_EN)
2354                 return true;
2355
2356         /* then check MEM_SIZE, in case the crtcs are off */
2357         if (RREG32(CONFIG_MEMSIZE))
2358                 return true;
2359
2360         return false;
2361 }
2362
2363 int r600_startup(struct radeon_device *rdev)
2364 {
2365         int r;
2366
2367         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2368                 r = r600_init_microcode(rdev);
2369                 if (r) {
2370                         DRM_ERROR("Failed to load firmware!\n");
2371                         return r;
2372                 }
2373         }
2374
2375         r600_mc_program(rdev);
2376         if (rdev->flags & RADEON_IS_AGP) {
2377                 r600_agp_enable(rdev);
2378         } else {
2379                 r = r600_pcie_gart_enable(rdev);
2380                 if (r)
2381                         return r;
2382         }
2383         r600_gpu_init(rdev);
2384         r = r600_blit_init(rdev);
2385         if (r) {
2386                 r600_blit_fini(rdev);
2387                 rdev->asic->copy = NULL;
2388                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2389         }
2390
2391         /* allocate wb buffer */
2392         r = radeon_wb_init(rdev);
2393         if (r)
2394                 return r;
2395
2396         /* Enable IRQ */
2397         r = r600_irq_init(rdev);
2398         if (r) {
2399                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2400                 radeon_irq_kms_fini(rdev);
2401                 return r;
2402         }
2403         r600_irq_set(rdev);
2404
2405         r = radeon_ring_init(rdev, rdev->cp.ring_size);
2406         if (r)
2407                 return r;
2408         r = r600_cp_load_microcode(rdev);
2409         if (r)
2410                 return r;
2411         r = r600_cp_resume(rdev);
2412         if (r)
2413                 return r;
2414
2415         return 0;
2416 }
2417
2418 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2419 {
2420         uint32_t temp;
2421
2422         temp = RREG32(CONFIG_CNTL);
2423         if (state == false) {
2424                 temp &= ~(1<<0);
2425                 temp |= (1<<1);
2426         } else {
2427                 temp &= ~(1<<1);
2428         }
2429         WREG32(CONFIG_CNTL, temp);
2430 }
2431
2432 int r600_resume(struct radeon_device *rdev)
2433 {
2434         int r;
2435
2436         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2437          * posting will perform necessary task to bring back GPU into good
2438          * shape.
2439          */
2440         /* post card */
2441         atom_asic_init(rdev->mode_info.atom_context);
2442
2443         r = r600_startup(rdev);
2444         if (r) {
2445                 DRM_ERROR("r600 startup failed on resume\n");
2446                 return r;
2447         }
2448
2449         r = r600_ib_test(rdev);
2450         if (r) {
2451                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2452                 return r;
2453         }
2454
2455         r = r600_audio_init(rdev);
2456         if (r) {
2457                 DRM_ERROR("radeon: audio resume failed\n");
2458                 return r;
2459         }
2460
2461         return r;
2462 }
2463
2464 int r600_suspend(struct radeon_device *rdev)
2465 {
2466         int r;
2467
2468         r600_audio_fini(rdev);
2469         /* FIXME: we should wait for ring to be empty */
2470         r600_cp_stop(rdev);
2471         rdev->cp.ready = false;
2472         r600_irq_suspend(rdev);
2473         radeon_wb_disable(rdev);
2474         r600_pcie_gart_disable(rdev);
2475         /* unpin shaders bo */
2476         if (rdev->r600_blit.shader_obj) {
2477                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2478                 if (!r) {
2479                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
2480                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2481                 }
2482         }
2483         return 0;
2484 }
2485
2486 /* Plan is to move initialization in that function and use
2487  * helper function so that radeon_device_init pretty much
2488  * do nothing more than calling asic specific function. This
2489  * should also allow to remove a bunch of callback function
2490  * like vram_info.
2491  */
2492 int r600_init(struct radeon_device *rdev)
2493 {
2494         int r;
2495
2496         r = radeon_dummy_page_init(rdev);
2497         if (r)
2498                 return r;
2499         if (r600_debugfs_mc_info_init(rdev)) {
2500                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2501         }
2502         /* This don't do much */
2503         r = radeon_gem_init(rdev);
2504         if (r)
2505                 return r;
2506         /* Read BIOS */
2507         if (!radeon_get_bios(rdev)) {
2508                 if (ASIC_IS_AVIVO(rdev))
2509                         return -EINVAL;
2510         }
2511         /* Must be an ATOMBIOS */
2512         if (!rdev->is_atom_bios) {
2513                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2514                 return -EINVAL;
2515         }
2516         r = radeon_atombios_init(rdev);
2517         if (r)
2518                 return r;
2519         /* Post card if necessary */
2520         if (!r600_card_posted(rdev)) {
2521                 if (!rdev->bios) {
2522                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2523                         return -EINVAL;
2524                 }
2525                 DRM_INFO("GPU not posted. posting now...\n");
2526                 atom_asic_init(rdev->mode_info.atom_context);
2527         }
2528         /* Initialize scratch registers */
2529         r600_scratch_init(rdev);
2530         /* Initialize surface registers */
2531         radeon_surface_init(rdev);
2532         /* Initialize clocks */
2533         radeon_get_clock_info(rdev->ddev);
2534         /* Fence driver */
2535         r = radeon_fence_driver_init(rdev);
2536         if (r)
2537                 return r;
2538         if (rdev->flags & RADEON_IS_AGP) {
2539                 r = radeon_agp_init(rdev);
2540                 if (r)
2541                         radeon_agp_disable(rdev);
2542         }
2543         r = r600_mc_init(rdev);
2544         if (r)
2545                 return r;
2546         /* Memory manager */
2547         r = radeon_bo_init(rdev);
2548         if (r)
2549                 return r;
2550
2551         r = radeon_irq_kms_init(rdev);
2552         if (r)
2553                 return r;
2554
2555         rdev->cp.ring_obj = NULL;
2556         r600_ring_init(rdev, 1024 * 1024);
2557
2558         rdev->ih.ring_obj = NULL;
2559         r600_ih_ring_init(rdev, 64 * 1024);
2560
2561         r = r600_pcie_gart_init(rdev);
2562         if (r)
2563                 return r;
2564
2565         rdev->accel_working = true;
2566         r = r600_startup(rdev);
2567         if (r) {
2568                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2569                 r600_cp_fini(rdev);
2570                 r600_irq_fini(rdev);
2571                 radeon_wb_fini(rdev);
2572                 radeon_irq_kms_fini(rdev);
2573                 r600_pcie_gart_fini(rdev);
2574                 rdev->accel_working = false;
2575         }
2576         if (rdev->accel_working) {
2577                 r = radeon_ib_pool_init(rdev);
2578                 if (r) {
2579                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2580                         rdev->accel_working = false;
2581                 } else {
2582                         r = r600_ib_test(rdev);
2583                         if (r) {
2584                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2585                                 rdev->accel_working = false;
2586                         }
2587                 }
2588         }
2589
2590         r = r600_audio_init(rdev);
2591         if (r)
2592                 return r; /* TODO error handling */
2593         return 0;
2594 }
2595
2596 void r600_fini(struct radeon_device *rdev)
2597 {
2598         r600_audio_fini(rdev);
2599         r600_blit_fini(rdev);
2600         r600_cp_fini(rdev);
2601         r600_irq_fini(rdev);
2602         radeon_wb_fini(rdev);
2603         radeon_irq_kms_fini(rdev);
2604         r600_pcie_gart_fini(rdev);
2605         radeon_agp_fini(rdev);
2606         radeon_gem_fini(rdev);
2607         radeon_fence_driver_fini(rdev);
2608         radeon_bo_fini(rdev);
2609         radeon_atombios_fini(rdev);
2610         kfree(rdev->bios);
2611         rdev->bios = NULL;
2612         radeon_dummy_page_fini(rdev);
2613 }
2614
2615
2616 /*
2617  * CS stuff
2618  */
2619 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2620 {
2621         /* FIXME: implement */
2622         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2623         radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2624         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2625         radeon_ring_write(rdev, ib->length_dw);
2626 }
2627
2628 int r600_ib_test(struct radeon_device *rdev)
2629 {
2630         struct radeon_ib *ib;
2631         uint32_t scratch;
2632         uint32_t tmp = 0;
2633         unsigned i;
2634         int r;
2635
2636         r = radeon_scratch_get(rdev, &scratch);
2637         if (r) {
2638                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2639                 return r;
2640         }
2641         WREG32(scratch, 0xCAFEDEAD);
2642         r = radeon_ib_get(rdev, &ib);
2643         if (r) {
2644                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2645                 return r;
2646         }
2647         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2648         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2649         ib->ptr[2] = 0xDEADBEEF;
2650         ib->ptr[3] = PACKET2(0);
2651         ib->ptr[4] = PACKET2(0);
2652         ib->ptr[5] = PACKET2(0);
2653         ib->ptr[6] = PACKET2(0);
2654         ib->ptr[7] = PACKET2(0);
2655         ib->ptr[8] = PACKET2(0);
2656         ib->ptr[9] = PACKET2(0);
2657         ib->ptr[10] = PACKET2(0);
2658         ib->ptr[11] = PACKET2(0);
2659         ib->ptr[12] = PACKET2(0);
2660         ib->ptr[13] = PACKET2(0);
2661         ib->ptr[14] = PACKET2(0);
2662         ib->ptr[15] = PACKET2(0);
2663         ib->length_dw = 16;
2664         r = radeon_ib_schedule(rdev, ib);
2665         if (r) {
2666                 radeon_scratch_free(rdev, scratch);
2667                 radeon_ib_free(rdev, &ib);
2668                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2669                 return r;
2670         }
2671         r = radeon_fence_wait(ib->fence, false);
2672         if (r) {
2673                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2674                 return r;
2675         }
2676         for (i = 0; i < rdev->usec_timeout; i++) {
2677                 tmp = RREG32(scratch);
2678                 if (tmp == 0xDEADBEEF)
2679                         break;
2680                 DRM_UDELAY(1);
2681         }
2682         if (i < rdev->usec_timeout) {
2683                 DRM_INFO("ib test succeeded in %u usecs\n", i);
2684         } else {
2685                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
2686                           scratch, tmp);
2687                 r = -EINVAL;
2688         }
2689         radeon_scratch_free(rdev, scratch);
2690         radeon_ib_free(rdev, &ib);
2691         return r;
2692 }
2693
2694 /*
2695  * Interrupts
2696  *
2697  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
2698  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
2699  * writing to the ring and the GPU consuming, the GPU writes to the ring
2700  * and host consumes.  As the host irq handler processes interrupts, it
2701  * increments the rptr.  When the rptr catches up with the wptr, all the
2702  * current interrupts have been processed.
2703  */
2704
2705 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2706 {
2707         u32 rb_bufsz;
2708
2709         /* Align ring size */
2710         rb_bufsz = drm_order(ring_size / 4);
2711         ring_size = (1 << rb_bufsz) * 4;
2712         rdev->ih.ring_size = ring_size;
2713         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2714         rdev->ih.rptr = 0;
2715 }
2716
2717 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2718 {
2719         int r;
2720
2721         /* Allocate ring buffer */
2722         if (rdev->ih.ring_obj == NULL) {
2723                 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2724                                      true,
2725                                      RADEON_GEM_DOMAIN_GTT,
2726                                      &rdev->ih.ring_obj);
2727                 if (r) {
2728                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2729                         return r;
2730                 }
2731                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2732                 if (unlikely(r != 0))
2733                         return r;
2734                 r = radeon_bo_pin(rdev->ih.ring_obj,
2735                                   RADEON_GEM_DOMAIN_GTT,
2736                                   &rdev->ih.gpu_addr);
2737                 if (r) {
2738                         radeon_bo_unreserve(rdev->ih.ring_obj);
2739                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2740                         return r;
2741                 }
2742                 r = radeon_bo_kmap(rdev->ih.ring_obj,
2743                                    (void **)&rdev->ih.ring);
2744                 radeon_bo_unreserve(rdev->ih.ring_obj);
2745                 if (r) {
2746                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2747                         return r;
2748                 }
2749         }
2750         return 0;
2751 }
2752
2753 static void r600_ih_ring_fini(struct radeon_device *rdev)
2754 {
2755         int r;
2756         if (rdev->ih.ring_obj) {
2757                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2758                 if (likely(r == 0)) {
2759                         radeon_bo_kunmap(rdev->ih.ring_obj);
2760                         radeon_bo_unpin(rdev->ih.ring_obj);
2761                         radeon_bo_unreserve(rdev->ih.ring_obj);
2762                 }
2763                 radeon_bo_unref(&rdev->ih.ring_obj);
2764                 rdev->ih.ring = NULL;
2765                 rdev->ih.ring_obj = NULL;
2766         }
2767 }
2768
2769 void r600_rlc_stop(struct radeon_device *rdev)
2770 {
2771
2772         if ((rdev->family >= CHIP_RV770) &&
2773             (rdev->family <= CHIP_RV740)) {
2774                 /* r7xx asics need to soft reset RLC before halting */
2775                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2776                 RREG32(SRBM_SOFT_RESET);
2777                 udelay(15000);
2778                 WREG32(SRBM_SOFT_RESET, 0);
2779                 RREG32(SRBM_SOFT_RESET);
2780         }
2781
2782         WREG32(RLC_CNTL, 0);
2783 }
2784
2785 static void r600_rlc_start(struct radeon_device *rdev)
2786 {
2787         WREG32(RLC_CNTL, RLC_ENABLE);
2788 }
2789
2790 static int r600_rlc_init(struct radeon_device *rdev)
2791 {
2792         u32 i;
2793         const __be32 *fw_data;
2794
2795         if (!rdev->rlc_fw)
2796                 return -EINVAL;
2797
2798         r600_rlc_stop(rdev);
2799
2800         WREG32(RLC_HB_BASE, 0);
2801         WREG32(RLC_HB_CNTL, 0);
2802         WREG32(RLC_HB_RPTR, 0);
2803         WREG32(RLC_HB_WPTR, 0);
2804         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2805         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2806         WREG32(RLC_MC_CNTL, 0);
2807         WREG32(RLC_UCODE_CNTL, 0);
2808
2809         fw_data = (const __be32 *)rdev->rlc_fw->data;
2810         if (rdev->family >= CHIP_CEDAR) {
2811                 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2812                         WREG32(RLC_UCODE_ADDR, i);
2813                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2814                 }
2815         } else if (rdev->family >= CHIP_RV770) {
2816                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2817                         WREG32(RLC_UCODE_ADDR, i);
2818                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2819                 }
2820         } else {
2821                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2822                         WREG32(RLC_UCODE_ADDR, i);
2823                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2824                 }
2825         }
2826         WREG32(RLC_UCODE_ADDR, 0);
2827
2828         r600_rlc_start(rdev);
2829
2830         return 0;
2831 }
2832
2833 static void r600_enable_interrupts(struct radeon_device *rdev)
2834 {
2835         u32 ih_cntl = RREG32(IH_CNTL);
2836         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2837
2838         ih_cntl |= ENABLE_INTR;
2839         ih_rb_cntl |= IH_RB_ENABLE;
2840         WREG32(IH_CNTL, ih_cntl);
2841         WREG32(IH_RB_CNTL, ih_rb_cntl);
2842         rdev->ih.enabled = true;
2843 }
2844
2845 void r600_disable_interrupts(struct radeon_device *rdev)
2846 {
2847         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2848         u32 ih_cntl = RREG32(IH_CNTL);
2849
2850         ih_rb_cntl &= ~IH_RB_ENABLE;
2851         ih_cntl &= ~ENABLE_INTR;
2852         WREG32(IH_RB_CNTL, ih_rb_cntl);
2853         WREG32(IH_CNTL, ih_cntl);
2854         /* set rptr, wptr to 0 */
2855         WREG32(IH_RB_RPTR, 0);
2856         WREG32(IH_RB_WPTR, 0);
2857         rdev->ih.enabled = false;
2858         rdev->ih.wptr = 0;
2859         rdev->ih.rptr = 0;
2860 }
2861
2862 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2863 {
2864         u32 tmp;
2865
2866         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2867         WREG32(GRBM_INT_CNTL, 0);
2868         WREG32(DxMODE_INT_MASK, 0);
2869         if (ASIC_IS_DCE3(rdev)) {
2870                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2871                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2872                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2873                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2874                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2875                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2876                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2877                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2878                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2879                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2880                 if (ASIC_IS_DCE32(rdev)) {
2881                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2882                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2883                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2884                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2885                 }
2886         } else {
2887                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2888                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2889                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2890                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2891                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2892                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2893                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2894                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2895         }
2896 }
2897
2898 int r600_irq_init(struct radeon_device *rdev)
2899 {
2900         int ret = 0;
2901         int rb_bufsz;
2902         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2903
2904         /* allocate ring */
2905         ret = r600_ih_ring_alloc(rdev);
2906         if (ret)
2907                 return ret;
2908
2909         /* disable irqs */
2910         r600_disable_interrupts(rdev);
2911
2912         /* init rlc */
2913         ret = r600_rlc_init(rdev);
2914         if (ret) {
2915                 r600_ih_ring_fini(rdev);
2916                 return ret;
2917         }
2918
2919         /* setup interrupt control */
2920         /* set dummy read address to ring address */
2921         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2922         interrupt_cntl = RREG32(INTERRUPT_CNTL);
2923         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2924          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2925          */
2926         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2927         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2928         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2929         WREG32(INTERRUPT_CNTL, interrupt_cntl);
2930
2931         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2932         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2933
2934         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2935                       IH_WPTR_OVERFLOW_CLEAR |
2936                       (rb_bufsz << 1));
2937
2938         if (rdev->wb.enabled)
2939                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
2940
2941         /* set the writeback address whether it's enabled or not */
2942         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
2943         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
2944
2945         WREG32(IH_RB_CNTL, ih_rb_cntl);
2946
2947         /* set rptr, wptr to 0 */
2948         WREG32(IH_RB_RPTR, 0);
2949         WREG32(IH_RB_WPTR, 0);
2950
2951         /* Default settings for IH_CNTL (disabled at first) */
2952         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2953         /* RPTR_REARM only works if msi's are enabled */
2954         if (rdev->msi_enabled)
2955                 ih_cntl |= RPTR_REARM;
2956
2957 #ifdef __BIG_ENDIAN
2958         ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2959 #endif
2960         WREG32(IH_CNTL, ih_cntl);
2961
2962         /* force the active interrupt state to all disabled */
2963         if (rdev->family >= CHIP_CEDAR)
2964                 evergreen_disable_interrupt_state(rdev);
2965         else
2966                 r600_disable_interrupt_state(rdev);
2967
2968         /* enable irqs */
2969         r600_enable_interrupts(rdev);
2970
2971         return ret;
2972 }
2973
2974 void r600_irq_suspend(struct radeon_device *rdev)
2975 {
2976         r600_irq_disable(rdev);
2977         r600_rlc_stop(rdev);
2978 }
2979
2980 void r600_irq_fini(struct radeon_device *rdev)
2981 {
2982         r600_irq_suspend(rdev);
2983         r600_ih_ring_fini(rdev);
2984 }
2985
2986 int r600_irq_set(struct radeon_device *rdev)
2987 {
2988         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2989         u32 mode_int = 0;
2990         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2991         u32 grbm_int_cntl = 0;
2992         u32 hdmi1, hdmi2;
2993
2994         if (!rdev->irq.installed) {
2995                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
2996                 return -EINVAL;
2997         }
2998         /* don't enable anything if the ih is disabled */
2999         if (!rdev->ih.enabled) {
3000                 r600_disable_interrupts(rdev);
3001                 /* force the active interrupt state to all disabled */
3002                 r600_disable_interrupt_state(rdev);
3003                 return 0;
3004         }
3005
3006         hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3007         if (ASIC_IS_DCE3(rdev)) {
3008                 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3009                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3010                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3011                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3012                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3013                 if (ASIC_IS_DCE32(rdev)) {
3014                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3015                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3016                 }
3017         } else {
3018                 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3019                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3020                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3021                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3022         }
3023
3024         if (rdev->irq.sw_int) {
3025                 DRM_DEBUG("r600_irq_set: sw int\n");
3026                 cp_int_cntl |= RB_INT_ENABLE;
3027                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3028         }
3029         if (rdev->irq.crtc_vblank_int[0]) {
3030                 DRM_DEBUG("r600_irq_set: vblank 0\n");
3031                 mode_int |= D1MODE_VBLANK_INT_MASK;
3032         }
3033         if (rdev->irq.crtc_vblank_int[1]) {
3034                 DRM_DEBUG("r600_irq_set: vblank 1\n");
3035                 mode_int |= D2MODE_VBLANK_INT_MASK;
3036         }
3037         if (rdev->irq.hpd[0]) {
3038                 DRM_DEBUG("r600_irq_set: hpd 1\n");
3039                 hpd1 |= DC_HPDx_INT_EN;
3040         }
3041         if (rdev->irq.hpd[1]) {
3042                 DRM_DEBUG("r600_irq_set: hpd 2\n");
3043                 hpd2 |= DC_HPDx_INT_EN;
3044         }
3045         if (rdev->irq.hpd[2]) {
3046                 DRM_DEBUG("r600_irq_set: hpd 3\n");
3047                 hpd3 |= DC_HPDx_INT_EN;
3048         }
3049         if (rdev->irq.hpd[3]) {
3050                 DRM_DEBUG("r600_irq_set: hpd 4\n");
3051                 hpd4 |= DC_HPDx_INT_EN;
3052         }
3053         if (rdev->irq.hpd[4]) {
3054                 DRM_DEBUG("r600_irq_set: hpd 5\n");
3055                 hpd5 |= DC_HPDx_INT_EN;
3056         }
3057         if (rdev->irq.hpd[5]) {
3058                 DRM_DEBUG("r600_irq_set: hpd 6\n");
3059                 hpd6 |= DC_HPDx_INT_EN;
3060         }
3061         if (rdev->irq.hdmi[0]) {
3062                 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3063                 hdmi1 |= R600_HDMI_INT_EN;
3064         }
3065         if (rdev->irq.hdmi[1]) {
3066                 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3067                 hdmi2 |= R600_HDMI_INT_EN;
3068         }
3069         if (rdev->irq.gui_idle) {
3070                 DRM_DEBUG("gui idle\n");
3071                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3072         }
3073
3074         WREG32(CP_INT_CNTL, cp_int_cntl);
3075         WREG32(DxMODE_INT_MASK, mode_int);
3076         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3077         WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
3078         if (ASIC_IS_DCE3(rdev)) {
3079                 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
3080                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3081                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3082                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3083                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3084                 if (ASIC_IS_DCE32(rdev)) {
3085                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3086                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3087                 }
3088         } else {
3089                 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
3090                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3091                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3092                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3093         }
3094
3095         return 0;
3096 }
3097
3098 static inline void r600_irq_ack(struct radeon_device *rdev,
3099                                 u32 *disp_int,
3100                                 u32 *disp_int_cont,
3101                                 u32 *disp_int_cont2)
3102 {
3103         u32 tmp;
3104
3105         if (ASIC_IS_DCE3(rdev)) {
3106                 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3107                 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3108                 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3109         } else {
3110                 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
3111                 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3112                 *disp_int_cont2 = 0;
3113         }
3114
3115         if (*disp_int & LB_D1_VBLANK_INTERRUPT)
3116                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3117         if (*disp_int & LB_D1_VLINE_INTERRUPT)
3118                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3119         if (*disp_int & LB_D2_VBLANK_INTERRUPT)
3120                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3121         if (*disp_int & LB_D2_VLINE_INTERRUPT)
3122                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3123         if (*disp_int & DC_HPD1_INTERRUPT) {
3124                 if (ASIC_IS_DCE3(rdev)) {
3125                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3126                         tmp |= DC_HPDx_INT_ACK;
3127                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3128                 } else {
3129                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3130                         tmp |= DC_HPDx_INT_ACK;
3131                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3132                 }
3133         }
3134         if (*disp_int & DC_HPD2_INTERRUPT) {
3135                 if (ASIC_IS_DCE3(rdev)) {
3136                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3137                         tmp |= DC_HPDx_INT_ACK;
3138                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3139                 } else {
3140                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3141                         tmp |= DC_HPDx_INT_ACK;
3142                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3143                 }
3144         }
3145         if (*disp_int_cont & DC_HPD3_INTERRUPT) {
3146                 if (ASIC_IS_DCE3(rdev)) {
3147                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3148                         tmp |= DC_HPDx_INT_ACK;
3149                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3150                 } else {
3151                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3152                         tmp |= DC_HPDx_INT_ACK;
3153                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3154                 }
3155         }
3156         if (*disp_int_cont & DC_HPD4_INTERRUPT) {
3157                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3158                 tmp |= DC_HPDx_INT_ACK;
3159                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3160         }
3161         if (ASIC_IS_DCE32(rdev)) {
3162                 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
3163                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3164                         tmp |= DC_HPDx_INT_ACK;
3165                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3166                 }
3167                 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
3168                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3169                         tmp |= DC_HPDx_INT_ACK;
3170                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3171                 }
3172         }
3173         if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3174                 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3175         }
3176         if (ASIC_IS_DCE3(rdev)) {
3177                 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3178                         WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3179                 }
3180         } else {
3181                 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3182                         WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3183                 }
3184         }
3185 }
3186
3187 void r600_irq_disable(struct radeon_device *rdev)
3188 {
3189         u32 disp_int, disp_int_cont, disp_int_cont2;
3190
3191         r600_disable_interrupts(rdev);
3192         /* Wait and acknowledge irq */
3193         mdelay(1);
3194         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3195         r600_disable_interrupt_state(rdev);
3196 }
3197
3198 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3199 {
3200         u32 wptr, tmp;
3201
3202         if (rdev->wb.enabled)
3203                 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
3204         else
3205                 wptr = RREG32(IH_RB_WPTR);
3206
3207         if (wptr & RB_OVERFLOW) {
3208                 /* When a ring buffer overflow happen start parsing interrupt
3209                  * from the last not overwritten vector (wptr + 16). Hopefully
3210                  * this should allow us to catchup.
3211                  */
3212                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3213                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3214                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3215                 tmp = RREG32(IH_RB_CNTL);
3216                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3217                 WREG32(IH_RB_CNTL, tmp);
3218         }
3219         return (wptr & rdev->ih.ptr_mask);
3220 }
3221
3222 /*        r600 IV Ring
3223  * Each IV ring entry is 128 bits:
3224  * [7:0]    - interrupt source id
3225  * [31:8]   - reserved
3226  * [59:32]  - interrupt source data
3227  * [127:60]  - reserved
3228  *
3229  * The basic interrupt vector entries
3230  * are decoded as follows:
3231  * src_id  src_data  description
3232  *      1         0  D1 Vblank
3233  *      1         1  D1 Vline
3234  *      5         0  D2 Vblank
3235  *      5         1  D2 Vline
3236  *     19         0  FP Hot plug detection A
3237  *     19         1  FP Hot plug detection B
3238  *     19         2  DAC A auto-detection
3239  *     19         3  DAC B auto-detection
3240  *     21         4  HDMI block A
3241  *     21         5  HDMI block B
3242  *    176         -  CP_INT RB
3243  *    177         -  CP_INT IB1
3244  *    178         -  CP_INT IB2
3245  *    181         -  EOP Interrupt
3246  *    233         -  GUI Idle
3247  *
3248  * Note, these are based on r600 and may need to be
3249  * adjusted or added to on newer asics
3250  */
3251
3252 int r600_irq_process(struct radeon_device *rdev)
3253 {
3254         u32 wptr = r600_get_ih_wptr(rdev);
3255         u32 rptr = rdev->ih.rptr;
3256         u32 src_id, src_data;
3257         u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
3258         unsigned long flags;
3259         bool queue_hotplug = false;
3260
3261         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3262         if (!rdev->ih.enabled)
3263                 return IRQ_NONE;
3264
3265         spin_lock_irqsave(&rdev->ih.lock, flags);
3266
3267         if (rptr == wptr) {
3268                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3269                 return IRQ_NONE;
3270         }
3271         if (rdev->shutdown) {
3272                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3273                 return IRQ_NONE;
3274         }
3275
3276 restart_ih:
3277         /* display interrupts */
3278         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3279
3280         rdev->ih.wptr = wptr;
3281         while (rptr != wptr) {
3282                 /* wptr/rptr are in bytes! */
3283                 ring_index = rptr / 4;
3284                 src_id =  rdev->ih.ring[ring_index] & 0xff;
3285                 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
3286
3287                 switch (src_id) {
3288                 case 1: /* D1 vblank/vline */
3289                         switch (src_data) {
3290                         case 0: /* D1 vblank */
3291                                 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
3292                                         drm_handle_vblank(rdev->ddev, 0);
3293                                         rdev->pm.vblank_sync = true;
3294                                         wake_up(&rdev->irq.vblank_queue);
3295                                         disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3296                                         DRM_DEBUG("IH: D1 vblank\n");
3297                                 }
3298                                 break;
3299                         case 1: /* D1 vline */
3300                                 if (disp_int & LB_D1_VLINE_INTERRUPT) {
3301                                         disp_int &= ~LB_D1_VLINE_INTERRUPT;
3302                                         DRM_DEBUG("IH: D1 vline\n");
3303                                 }
3304                                 break;
3305                         default:
3306                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3307                                 break;
3308                         }
3309                         break;
3310                 case 5: /* D2 vblank/vline */
3311                         switch (src_data) {
3312                         case 0: /* D2 vblank */
3313                                 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
3314                                         drm_handle_vblank(rdev->ddev, 1);
3315                                         rdev->pm.vblank_sync = true;
3316                                         wake_up(&rdev->irq.vblank_queue);
3317                                         disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3318                                         DRM_DEBUG("IH: D2 vblank\n");
3319                                 }
3320                                 break;
3321                         case 1: /* D1 vline */
3322                                 if (disp_int & LB_D2_VLINE_INTERRUPT) {
3323                                         disp_int &= ~LB_D2_VLINE_INTERRUPT;
3324                                         DRM_DEBUG("IH: D2 vline\n");
3325                                 }
3326                                 break;
3327                         default:
3328                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3329                                 break;
3330                         }
3331                         break;
3332                 case 19: /* HPD/DAC hotplug */
3333                         switch (src_data) {
3334                         case 0:
3335                                 if (disp_int & DC_HPD1_INTERRUPT) {
3336                                         disp_int &= ~DC_HPD1_INTERRUPT;
3337                                         queue_hotplug = true;
3338                                         DRM_DEBUG("IH: HPD1\n");
3339                                 }
3340                                 break;
3341                         case 1:
3342                                 if (disp_int & DC_HPD2_INTERRUPT) {
3343                                         disp_int &= ~DC_HPD2_INTERRUPT;
3344                                         queue_hotplug = true;
3345                                         DRM_DEBUG("IH: HPD2\n");
3346                                 }
3347                                 break;
3348                         case 4:
3349                                 if (disp_int_cont & DC_HPD3_INTERRUPT) {
3350                                         disp_int_cont &= ~DC_HPD3_INTERRUPT;
3351                                         queue_hotplug = true;
3352                                         DRM_DEBUG("IH: HPD3\n");
3353                                 }
3354                                 break;
3355                         case 5:
3356                                 if (disp_int_cont & DC_HPD4_INTERRUPT) {
3357                                         disp_int_cont &= ~DC_HPD4_INTERRUPT;
3358                                         queue_hotplug = true;
3359                                         DRM_DEBUG("IH: HPD4\n");
3360                                 }
3361                                 break;
3362                         case 10:
3363                                 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
3364                                         disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3365                                         queue_hotplug = true;
3366                                         DRM_DEBUG("IH: HPD5\n");
3367                                 }
3368                                 break;
3369                         case 12:
3370                                 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
3371                                         disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3372                                         queue_hotplug = true;
3373                                         DRM_DEBUG("IH: HPD6\n");
3374                                 }
3375                                 break;
3376                         default:
3377                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3378                                 break;
3379                         }
3380                         break;
3381                 case 21: /* HDMI */
3382                         DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3383                         r600_audio_schedule_polling(rdev);
3384                         break;
3385                 case 176: /* CP_INT in ring buffer */
3386                 case 177: /* CP_INT in IB1 */
3387                 case 178: /* CP_INT in IB2 */
3388                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3389                         radeon_fence_process(rdev);
3390                         break;
3391                 case 181: /* CP EOP event */
3392                         DRM_DEBUG("IH: CP EOP\n");
3393                         radeon_fence_process(rdev);
3394                         break;
3395                 case 233: /* GUI IDLE */
3396                         DRM_DEBUG("IH: CP EOP\n");
3397                         rdev->pm.gui_idle = true;
3398                         wake_up(&rdev->irq.idle_queue);
3399                         break;
3400                 default:
3401                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3402                         break;
3403                 }
3404
3405                 /* wptr/rptr are in bytes! */
3406                 rptr += 16;
3407                 rptr &= rdev->ih.ptr_mask;
3408         }
3409         /* make sure wptr hasn't changed while processing */
3410         wptr = r600_get_ih_wptr(rdev);
3411         if (wptr != rdev->ih.wptr)
3412                 goto restart_ih;
3413         if (queue_hotplug)
3414                 queue_work(rdev->wq, &rdev->hotplug_work);
3415         rdev->ih.rptr = rptr;
3416         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3417         spin_unlock_irqrestore(&rdev->ih.lock, flags);
3418         return IRQ_HANDLED;
3419 }
3420
3421 /*
3422  * Debugfs info
3423  */
3424 #if defined(CONFIG_DEBUG_FS)
3425
3426 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
3427 {
3428         struct drm_info_node *node = (struct drm_info_node *) m->private;
3429         struct drm_device *dev = node->minor->dev;
3430         struct radeon_device *rdev = dev->dev_private;
3431         unsigned count, i, j;
3432
3433         radeon_ring_free_size(rdev);
3434         count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3435         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
3436         seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3437         seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3438         seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3439         seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3440         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3441         seq_printf(m, "%u dwords in ring\n", count);
3442         i = rdev->cp.rptr;
3443         for (j = 0; j <= count; j++) {
3444                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
3445                 i = (i + 1) & rdev->cp.ptr_mask;
3446         }
3447         return 0;
3448 }
3449
3450 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3451 {
3452         struct drm_info_node *node = (struct drm_info_node *) m->private;
3453         struct drm_device *dev = node->minor->dev;
3454         struct radeon_device *rdev = dev->dev_private;
3455
3456         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3457         DREG32_SYS(m, rdev, VM_L2_STATUS);
3458         return 0;
3459 }
3460
3461 static struct drm_info_list r600_mc_info_list[] = {
3462         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3463         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3464 };
3465 #endif
3466
3467 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3468 {
3469 #if defined(CONFIG_DEBUG_FS)
3470         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3471 #else
3472         return 0;
3473 #endif
3474 }
3475
3476 /**
3477  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3478  * rdev: radeon device structure
3479  * bo: buffer object struct which userspace is waiting for idle
3480  *
3481  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3482  * through ring buffer, this leads to corruption in rendering, see
3483  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3484  * directly perform HDP flush by writing register through MMIO.
3485  */
3486 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3487 {
3488         /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
3489          * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
3490          */
3491         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
3492             rdev->vram_scratch.ptr) {
3493                 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3494                 u32 tmp;
3495
3496                 WREG32(HDP_DEBUG1, 0);
3497                 tmp = readl((void __iomem *)ptr);
3498         } else
3499                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3500 }