drivers/net/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2010 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/moduleparam.h>
  20 #include <linux/kernel.h>
  21 #include <linux/device.h>  /* for dev_info() */
  22 #include <linux/timer.h>
  23 #include <linux/errno.h>
  24 #include <linux/ioport.h>
  25 #include <linux/slab.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/pci.h>
  28 #include <linux/init.h>
  29 #include <linux/netdevice.h>
  30 #include <linux/etherdevice.h>
  31 #include <linux/skbuff.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/bitops.h>
  34 #include <linux/irq.h>
  35 #include <linux/delay.h>
  36 #include <asm/byteorder.h>
  37 #include <linux/time.h>
  38 #include <linux/ethtool.h>
  39 #include <linux/mii.h>
  40 #include <linux/if_vlan.h>
  41 #include <net/ip.h>
  42 #include <net/tcp.h>
  43 #include <net/checksum.h>
  44 #include <net/ip6_checksum.h>
  45 #include <linux/workqueue.h>
  46 #include <linux/crc32.h>
  47 #include <linux/crc32c.h>
  48 #include <linux/prefetch.h>
  49 #include <linux/zlib.h>
  50 #include <linux/io.h>
  51 #include <linux/stringify.h>
  52
  53 #define BNX2X_MAIN
  54 #include "bnx2x.h"
  55 #include "bnx2x_init.h"
  56 #include "bnx2x_init_ops.h"
  57 #include "bnx2x_cmn.h"
  58 #include "bnx2x_dcb.h"
  59
  60 #include <linux/firmware.h>
  61 #include "bnx2x_fw_file_hdr.h"
  62 /* FW files */
  63 #define FW_FILE_VERSION                                 \
  64         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
  65         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
  66         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
  67         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
  68 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
  69 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
  70 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
  71
  72 /* Time in jiffies before concluding the transmitter is hung */
  73 #define TX_TIMEOUT              (5*HZ)
  74
  75 static char version[] __devinitdata =
  76         "Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
  77         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  78
  79 MODULE_AUTHOR("Eliezer Tamir");
  80 MODULE_DESCRIPTION("Broadcom NetXtreme II "
  81                    "BCM57710/57711/57711E/57712/57712E Driver");
  82 MODULE_LICENSE("GPL");
  83 MODULE_VERSION(DRV_MODULE_VERSION);
  84 MODULE_FIRMWARE(FW_FILE_NAME_E1);
  85 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
  86 MODULE_FIRMWARE(FW_FILE_NAME_E2);
  87
  88 static int multi_mode = 1;
  89 module_param(multi_mode, int, 0);
  90 MODULE_PARM_DESC(multi_mode, " Multi queue mode "
  91                              "(0 Disable; 1 Enable (default))");
  92
  93 int num_queues;
  94 module_param(num_queues, int, 0);
  95 MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
  96                                 " (default is as a number of CPUs)");
  97
  98 static int disable_tpa;
  99 module_param(disable_tpa, int, 0);
 100 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 101
 102 static int int_mode;
 103 module_param(int_mode, int, 0);
 104 MODULE_PARM_DESC(int_mode, " Force interrupt mode other then MSI-X "
 105                                 "(1 INT#x; 2 MSI)");
 106
 107 static int dropless_fc;
 108 module_param(dropless_fc, int, 0);
 109 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 110
 111 static int poll;
 112 module_param(poll, int, 0);
 113 MODULE_PARM_DESC(poll, " Use polling (for debug)");
 114
 115 static int mrrs = -1;
 116 module_param(mrrs, int, 0);
 117 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 118
 119 static int debug;
 120 module_param(debug, int, 0);
 121 MODULE_PARM_DESC(debug, " Default debug msglevel");
 122
 123 static struct workqueue_struct *bnx2x_wq;
 124
 125 #ifdef BCM_CNIC
 126 static u8 ALL_ENODE_MACS[] = {0x01, 0x10, 0x18, 0x01, 0x00, 0x01};
 127 #endif
 128
 129 enum bnx2x_board_type {
 130         BCM57710 = 0,
 131         BCM57711 = 1,
 132         BCM57711E = 2,
 133         BCM57712 = 3,
 134         BCM57712E = 4
 135 };
 136
 137 /* indexed by board_type, above */
 138 static struct {
 139         char *name;
 140 } board_info[] __devinitdata = {
 141         { "Broadcom NetXtreme II BCM57710 XGb" },
 142         { "Broadcom NetXtreme II BCM57711 XGb" },
 143         { "Broadcom NetXtreme II BCM57711E XGb" },
 144         { "Broadcom NetXtreme II BCM57712 XGb" },
 145         { "Broadcom NetXtreme II BCM57712E XGb" }
 146 };
 147
 148 #ifndef PCI_DEVICE_ID_NX2_57712
 149 #define PCI_DEVICE_ID_NX2_57712         0x1662
 150 #endif
 151 #ifndef PCI_DEVICE_ID_NX2_57712E
 152 #define PCI_DEVICE_ID_NX2_57712E        0x1663
 153 #endif
 154
 155 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
 156         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 157         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 158         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 159         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 160         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712E), BCM57712E },
 161         { 0 }
 162 };
 163
 164 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 165
 166 /****************************************************************************
 167 * General service functions
 168 ****************************************************************************/
 169
 170 static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
 171                                        u32 addr, dma_addr_t mapping)
 172 {
 173         REG_WR(bp,  addr, U64_LO(mapping));
 174         REG_WR(bp,  addr + 4, U64_HI(mapping));
 175 }
 176
 177 static inline void __storm_memset_fill(struct bnx2x *bp,
 178                                        u32 addr, size_t size, u32 val)
 179 {
 180         int i;
 181         for (i = 0; i < size/4; i++)
 182                 REG_WR(bp,  addr + (i * 4), val);
 183 }
 184
 185 static inline void storm_memset_ustats_zero(struct bnx2x *bp,
 186                                             u8 port, u16 stat_id)
 187 {
 188         size_t size = sizeof(struct ustorm_per_client_stats);
 189
 190         u32 addr = BAR_USTRORM_INTMEM +
 191                         USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
 192
 193         __storm_memset_fill(bp, addr, size, 0);
 194 }
 195
 196 static inline void storm_memset_tstats_zero(struct bnx2x *bp,
 197                                             u8 port, u16 stat_id)
 198 {
 199         size_t size = sizeof(struct tstorm_per_client_stats);
 200
 201         u32 addr = BAR_TSTRORM_INTMEM +
 202                         TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
 203
 204         __storm_memset_fill(bp, addr, size, 0);
 205 }
 206
 207 static inline void storm_memset_xstats_zero(struct bnx2x *bp,
 208                                             u8 port, u16 stat_id)
 209 {
 210         size_t size = sizeof(struct xstorm_per_client_stats);
 211
 212         u32 addr = BAR_XSTRORM_INTMEM +
 213                         XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
 214
 215         __storm_memset_fill(bp, addr, size, 0);
 216 }
 217
 218
 219 static inline void storm_memset_spq_addr(struct bnx2x *bp,
 220                                          dma_addr_t mapping, u16 abs_fid)
 221 {
 222         u32 addr = XSEM_REG_FAST_MEMORY +
 223                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 224
 225         __storm_memset_dma_mapping(bp, addr, mapping);
 226 }
 227
 228 static inline void storm_memset_ov(struct bnx2x *bp, u16 ov, u16 abs_fid)
 229 {
 230         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(abs_fid), ov);
 231 }
 232
 233 static inline void storm_memset_func_cfg(struct bnx2x *bp,
 234                                 struct tstorm_eth_function_common_config *tcfg,
 235                                 u16 abs_fid)
 236 {
 237         size_t size = sizeof(struct tstorm_eth_function_common_config);
 238
 239         u32 addr = BAR_TSTRORM_INTMEM +
 240                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
 241
 242         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
 243 }
 244
 245 static inline void storm_memset_xstats_flags(struct bnx2x *bp,
 246                                 struct stats_indication_flags *flags,
 247                                 u16 abs_fid)
 248 {
 249         size_t size = sizeof(struct stats_indication_flags);
 250
 251         u32 addr = BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(abs_fid);
 252
 253         __storm_memset_struct(bp, addr, size, (u32 *)flags);
 254 }
 255
 256 static inline void storm_memset_tstats_flags(struct bnx2x *bp,
 257                                 struct stats_indication_flags *flags,
 258                                 u16 abs_fid)
 259 {
 260         size_t size = sizeof(struct stats_indication_flags);
 261
 262         u32 addr = BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(abs_fid);
 263
 264         __storm_memset_struct(bp, addr, size, (u32 *)flags);
 265 }
 266
 267 static inline void storm_memset_ustats_flags(struct bnx2x *bp,
 268                                 struct stats_indication_flags *flags,
 269                                 u16 abs_fid)
 270 {
 271         size_t size = sizeof(struct stats_indication_flags);
 272
 273         u32 addr = BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(abs_fid);
 274
 275         __storm_memset_struct(bp, addr, size, (u32 *)flags);
 276 }
 277
 278 static inline void storm_memset_cstats_flags(struct bnx2x *bp,
 279                                 struct stats_indication_flags *flags,
 280                                 u16 abs_fid)
 281 {
 282         size_t size = sizeof(struct stats_indication_flags);
 283
 284         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(abs_fid);
 285
 286         __storm_memset_struct(bp, addr, size, (u32 *)flags);
 287 }
 288
 289 static inline void storm_memset_xstats_addr(struct bnx2x *bp,
 290                                            dma_addr_t mapping, u16 abs_fid)
 291 {
 292         u32 addr = BAR_XSTRORM_INTMEM +
 293                 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
 294
 295         __storm_memset_dma_mapping(bp, addr, mapping);
 296 }
 297
 298 static inline void storm_memset_tstats_addr(struct bnx2x *bp,
 299                                            dma_addr_t mapping, u16 abs_fid)
 300 {
 301         u32 addr = BAR_TSTRORM_INTMEM +
 302                 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
 303
 304         __storm_memset_dma_mapping(bp, addr, mapping);
 305 }
 306
 307 static inline void storm_memset_ustats_addr(struct bnx2x *bp,
 308                                            dma_addr_t mapping, u16 abs_fid)
 309 {
 310         u32 addr = BAR_USTRORM_INTMEM +
 311                 USTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
 312
 313         __storm_memset_dma_mapping(bp, addr, mapping);
 314 }
 315
 316 static inline void storm_memset_cstats_addr(struct bnx2x *bp,
 317                                            dma_addr_t mapping, u16 abs_fid)
 318 {
 319         u32 addr = BAR_CSTRORM_INTMEM +
 320                 CSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
 321
 322         __storm_memset_dma_mapping(bp, addr, mapping);
 323 }
 324
 325 static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 326                                          u16 pf_id)
 327 {
 328         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 329                 pf_id);
 330         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 331                 pf_id);
 332         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 333                 pf_id);
 334         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 335                 pf_id);
 336 }
 337
 338 static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 339                                         u8 enable)
 340 {
 341         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 342                 enable);
 343         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 344                 enable);
 345         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 346                 enable);
 347         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 348                 enable);
 349 }
 350
 351 static inline void storm_memset_eq_data(struct bnx2x *bp,
 352                                 struct event_ring_data *eq_data,
 353                                 u16 pfid)
 354 {
 355         size_t size = sizeof(struct event_ring_data);
 356
 357         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 358
 359         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 360 }
 361
 362 static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 363                                         u16 pfid)
 364 {
 365         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 366         REG_WR16(bp, addr, eq_prod);
 367 }
 368
 369 static inline void storm_memset_hc_timeout(struct bnx2x *bp, u8 port,
 370                                              u16 fw_sb_id, u8 sb_index,
 371                                              u8 ticks)
 372 {
 373
 374         int index_offset = CHIP_IS_E2(bp) ?
 375                 offsetof(struct hc_status_block_data_e2, index_data) :
 376                 offsetof(struct hc_status_block_data_e1x, index_data);
 377         u32 addr = BAR_CSTRORM_INTMEM +
 378                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
 379                         index_offset +
 380                         sizeof(struct hc_index_data)*sb_index +
 381                         offsetof(struct hc_index_data, timeout);
 382         REG_WR8(bp, addr, ticks);
 383         DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d ticks %d\n",
 384                           port, fw_sb_id, sb_index, ticks);
 385 }
 386 static inline void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
 387                                              u16 fw_sb_id, u8 sb_index,
 388                                              u8 disable)
 389 {
 390         u32 enable_flag = disable ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
 391         int index_offset = CHIP_IS_E2(bp) ?
 392                 offsetof(struct hc_status_block_data_e2, index_data) :
 393                 offsetof(struct hc_status_block_data_e1x, index_data);
 394         u32 addr = BAR_CSTRORM_INTMEM +
 395                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
 396                         index_offset +
 397                         sizeof(struct hc_index_data)*sb_index +
 398                         offsetof(struct hc_index_data, flags);
 399         u16 flags = REG_RD16(bp, addr);
 400         /* clear and set */
 401         flags &= ~HC_INDEX_DATA_HC_ENABLED;
 402         flags |= enable_flag;
 403         REG_WR16(bp, addr, flags);
 404         DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d disable %d\n",
 405                           port, fw_sb_id, sb_index, disable);
 406 }
 407
 408 /* used only at init
 409  * locking is done by mcp
 410  */
 411 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 412 {
 413         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 414         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 415         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 416                                PCICFG_VENDOR_ID_OFFSET);
 417 }
 418
 419 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 420 {
 421         u32 val;
 422
 423         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 424         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 425         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 426                                PCICFG_VENDOR_ID_OFFSET);
 427
 428         return val;
 429 }
 430
 431 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 432 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 433 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 434 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 435 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 436
 437 static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
 438                           int msglvl)
 439 {
 440         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 441
 442         switch (dmae->opcode & DMAE_COMMAND_DST) {
 443         case DMAE_CMD_DST_PCI:
 444                 if (src_type == DMAE_CMD_SRC_PCI)
 445                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 446                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 447                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 448                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 449                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 450                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 451                            dmae->comp_val);
 452                 else
 453                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 454                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 455                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 456                            dmae->opcode, dmae->src_addr_lo >> 2,
 457                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 458                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 459                            dmae->comp_val);
 460                 break;
 461         case DMAE_CMD_DST_GRC:
 462                 if (src_type == DMAE_CMD_SRC_PCI)
 463                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 464                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 465                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 466                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 467                            dmae->len, dmae->dst_addr_lo >> 2,
 468                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 469                            dmae->comp_val);
 470                 else
 471                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 472                            "src [%08x], len [%d*4], dst [%08x]\n"
 473                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 474                            dmae->opcode, dmae->src_addr_lo >> 2,
 475                            dmae->len, dmae->dst_addr_lo >> 2,
 476                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 477                            dmae->comp_val);
 478                 break;
 479         default:
 480                 if (src_type == DMAE_CMD_SRC_PCI)
 481                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 482                            DP_LEVEL "src_addr [%x:%08x]  len [%d * 4]  "
 483                                     "dst_addr [none]\n"
 484                            DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 485                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 486                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 487                            dmae->comp_val);
 488                 else
 489                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 490                            DP_LEVEL "src_addr [%08x]  len [%d * 4]  "
 491                                     "dst_addr [none]\n"
 492                            DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 493                            dmae->opcode, dmae->src_addr_lo >> 2,
 494                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 495                            dmae->comp_val);
 496                 break;
 497         }
 498
 499 }
 500
 501 const u32 dmae_reg_go_c[] = {
 502         DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
 503         DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
 504         DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
 505         DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
 506 };
 507
 508 /* copy command into DMAE command memory and set DMAE command go */
 509 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 510 {
 511         u32 cmd_offset;
 512         int i;
 513
 514         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 515         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 516                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 517
 518                 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
 519                    idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
 520         }
 521         REG_WR(bp, dmae_reg_go_c[idx], 1);
 522 }
 523
 524 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 525 {
 526         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 527                            DMAE_CMD_C_ENABLE);
 528 }
 529
 530 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 531 {
 532         return opcode & ~DMAE_CMD_SRC_RESET;
 533 }
 534
 535 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 536                              bool with_comp, u8 comp_type)
 537 {
 538         u32 opcode = 0;
 539
 540         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 541                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 542
 543         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 544
 545         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 546         opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 547                    (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 548         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 549
 550 #ifdef __BIG_ENDIAN
 551         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 552 #else
 553         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 554 #endif
 555         if (with_comp)
 556                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 557         return opcode;
 558 }
 559
 560 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 561                                       struct dmae_command *dmae,
 562                                       u8 src_type, u8 dst_type)
 563 {
 564         memset(dmae, 0, sizeof(struct dmae_command));
 565
 566         /* set the opcode */
 567         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 568                                          true, DMAE_COMP_PCI);
 569
 570         /* fill in the completion parameters */
 571         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 572         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 573         dmae->comp_val = DMAE_COMP_VAL;
 574 }
 575
 576 /* issue a dmae command over the init-channel and wailt for completion */
 577 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
 578                                       struct dmae_command *dmae)
 579 {
 580         u32 *wb_comp = bnx2x_sp(bp, wb_comp);
 581         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 40;
 582         int rc = 0;
 583
 584         DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
 585            bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
 586            bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
 587
 588         /* lock the dmae channel */
 589         mutex_lock(&bp->dmae_mutex);
 590
 591         /* reset completion */
 592         *wb_comp = 0;
 593
 594         /* post the command on the channel used for initializations */
 595         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 596
 597         /* wait for completion */
 598         udelay(5);
 599         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 600                 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
 601
 602                 if (!cnt) {
 603                         BNX2X_ERR("DMAE timeout!\n");
 604                         rc = DMAE_TIMEOUT;
 605                         goto unlock;
 606                 }
 607                 cnt--;
 608                 udelay(50);
 609         }
 610         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 611                 BNX2X_ERR("DMAE PCI error!\n");
 612                 rc = DMAE_PCI_ERROR;
 613         }
 614
 615         DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
 616            bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
 617            bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
 618
 619 unlock:
 620         mutex_unlock(&bp->dmae_mutex);
 621         return rc;
 622 }
 623
 624 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 625                       u32 len32)
 626 {
 627         struct dmae_command dmae;
 628
 629         if (!bp->dmae_ready) {
 630                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 631
 632                 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x  len32 %d)"
 633                    "  using indirect\n", dst_addr, len32);
 634                 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 635                 return;
 636         }
 637
 638         /* set opcode and fixed command fields */
 639         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 640
 641         /* fill in addresses and len */
 642         dmae.src_addr_lo = U64_LO(dma_addr);
 643         dmae.src_addr_hi = U64_HI(dma_addr);
 644         dmae.dst_addr_lo = dst_addr >> 2;
 645         dmae.dst_addr_hi = 0;
 646         dmae.len = len32;
 647
 648         bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
 649
 650         /* issue the command and wait for completion */
 651         bnx2x_issue_dmae_with_comp(bp, &dmae);
 652 }
 653
 654 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 655 {
 656         struct dmae_command dmae;
 657
 658         if (!bp->dmae_ready) {
 659                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 660                 int i;
 661
 662                 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x  len32 %d)"
 663                    "  using indirect\n", src_addr, len32);
 664                 for (i = 0; i < len32; i++)
 665                         data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 666                 return;
 667         }
 668
 669         /* set opcode and fixed command fields */
 670         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 671
 672         /* fill in addresses and len */
 673         dmae.src_addr_lo = src_addr >> 2;
 674         dmae.src_addr_hi = 0;
 675         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 676         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 677         dmae.len = len32;
 678
 679         bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
 680
 681         /* issue the command and wait for completion */
 682         bnx2x_issue_dmae_with_comp(bp, &dmae);
 683 }
 684
 685 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 686                                       u32 addr, u32 len)
 687 {
 688         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 689         int offset = 0;
 690
 691         while (len > dmae_wr_max) {
 692                 bnx2x_write_dmae(bp, phys_addr + offset,
 693                                  addr + offset, dmae_wr_max);
 694                 offset += dmae_wr_max * 4;
 695                 len -= dmae_wr_max;
 696         }
 697
 698         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 699 }
 700
 701 /* used only for slowpath so not inlined */
 702 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
 703 {
 704         u32 wb_write[2];
 705
 706         wb_write[0] = val_hi;
 707         wb_write[1] = val_lo;
 708         REG_WR_DMAE(bp, reg, wb_write, 2);
 709 }
 710
 711 #ifdef USE_WB_RD
 712 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
 713 {
 714         u32 wb_data[2];
 715
 716         REG_RD_DMAE(bp, reg, wb_data, 2);
 717
 718         return HILO_U64(wb_data[0], wb_data[1]);
 719 }
 720 #endif
 721
 722 static int bnx2x_mc_assert(struct bnx2x *bp)
 723 {
 724         char last_idx;
 725         int i, rc = 0;
 726         u32 row0, row1, row2, row3;
 727
 728         /* XSTORM */
 729         last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
 730                            XSTORM_ASSERT_LIST_INDEX_OFFSET);
 731         if (last_idx)
 732                 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 733
 734         /* print the asserts */
 735         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 736
 737                 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 738                               XSTORM_ASSERT_LIST_OFFSET(i));
 739                 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 740                               XSTORM_ASSERT_LIST_OFFSET(i) + 4);
 741                 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 742                               XSTORM_ASSERT_LIST_OFFSET(i) + 8);
 743                 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 744                               XSTORM_ASSERT_LIST_OFFSET(i) + 12);
 745
 746                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 747                         BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
 748                                   " 0x%08x 0x%08x 0x%08x\n",
 749                                   i, row3, row2, row1, row0);
 750                         rc++;
 751                 } else {
 752                         break;
 753                 }
 754         }
 755
 756         /* TSTORM */
 757         last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
 758                            TSTORM_ASSERT_LIST_INDEX_OFFSET);
 759         if (last_idx)
 760                 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 761
 762         /* print the asserts */
 763         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 764
 765                 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 766                               TSTORM_ASSERT_LIST_OFFSET(i));
 767                 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 768                               TSTORM_ASSERT_LIST_OFFSET(i) + 4);
 769                 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 770                               TSTORM_ASSERT_LIST_OFFSET(i) + 8);
 771                 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 772                               TSTORM_ASSERT_LIST_OFFSET(i) + 12);
 773
 774                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 775                         BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
 776                                   " 0x%08x 0x%08x 0x%08x\n",
 777                                   i, row3, row2, row1, row0);
 778                         rc++;
 779                 } else {
 780                         break;
 781                 }
 782         }
 783
 784         /* CSTORM */
 785         last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
 786                            CSTORM_ASSERT_LIST_INDEX_OFFSET);
 787         if (last_idx)
 788                 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 789
 790         /* print the asserts */
 791         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 792
 793                 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 794                               CSTORM_ASSERT_LIST_OFFSET(i));
 795                 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 796                               CSTORM_ASSERT_LIST_OFFSET(i) + 4);
 797                 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 798                               CSTORM_ASSERT_LIST_OFFSET(i) + 8);
 799                 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 800                               CSTORM_ASSERT_LIST_OFFSET(i) + 12);
 801
 802                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 803                         BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
 804                                   " 0x%08x 0x%08x 0x%08x\n",
 805                                   i, row3, row2, row1, row0);
 806                         rc++;
 807                 } else {
 808                         break;
 809                 }
 810         }
 811
 812         /* USTORM */
 813         last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
 814                            USTORM_ASSERT_LIST_INDEX_OFFSET);
 815         if (last_idx)
 816                 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 817
 818         /* print the asserts */
 819         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 820
 821                 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
 822                               USTORM_ASSERT_LIST_OFFSET(i));
 823                 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
 824                               USTORM_ASSERT_LIST_OFFSET(i) + 4);
 825                 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
 826                               USTORM_ASSERT_LIST_OFFSET(i) + 8);
 827                 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
 828                               USTORM_ASSERT_LIST_OFFSET(i) + 12);
 829
 830                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 831                         BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
 832                                   " 0x%08x 0x%08x 0x%08x\n",
 833                                   i, row3, row2, row1, row0);
 834                         rc++;
 835                 } else {
 836                         break;
 837                 }
 838         }
 839
 840         return rc;
 841 }
 842
 843 static void bnx2x_fw_dump(struct bnx2x *bp)
 844 {
 845         u32 addr;
 846         u32 mark, offset;
 847         __be32 data[9];
 848         int word;
 849         u32 trace_shmem_base;
 850         if (BP_NOMCP(bp)) {
 851                 BNX2X_ERR("NO MCP - can not dump\n");
 852                 return;
 853         }
 854
 855         if (BP_PATH(bp) == 0)
 856                 trace_shmem_base = bp->common.shmem_base;
 857         else
 858                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 859         addr = trace_shmem_base - 0x0800 + 4;
 860         mark = REG_RD(bp, addr);
 861         mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
 862                         + ((mark + 0x3) & ~0x3) - 0x08000000;
 863         pr_err("begin fw dump (mark 0x%x)\n", mark);
 864
 865         pr_err("");
 866         for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
 867                 for (word = 0; word < 8; word++)
 868                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 869                 data[8] = 0x0;
 870                 pr_cont("%s", (char *)data);
 871         }
 872         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 873                 for (word = 0; word < 8; word++)
 874                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 875                 data[8] = 0x0;
 876                 pr_cont("%s", (char *)data);
 877         }
 878         pr_err("end of fw dump\n");
 879 }
 880
 881 void bnx2x_panic_dump(struct bnx2x *bp)
 882 {
 883         int i;
 884         u16 j;
 885         struct hc_sp_status_block_data sp_sb_data;
 886         int func = BP_FUNC(bp);
 887 #ifdef BNX2X_STOP_ON_ERROR
 888         u16 start = 0, end = 0;
 889 #endif
 890
 891         bp->stats_state = STATS_STATE_DISABLED;
 892         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 893
 894         BNX2X_ERR("begin crash dump -----------------\n");
 895
 896         /* Indices */
 897         /* Common */
 898         BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)"
 899                   "  spq_prod_idx(0x%x)\n",
 900                   bp->def_idx, bp->def_att_idx,
 901                   bp->attn_state, bp->spq_prod_idx);
 902         BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 903                   bp->def_status_blk->atten_status_block.attn_bits,
 904                   bp->def_status_blk->atten_status_block.attn_bits_ack,
 905                   bp->def_status_blk->atten_status_block.status_block_id,
 906                   bp->def_status_blk->atten_status_block.attn_bits_index);
 907         BNX2X_ERR("     def (");
 908         for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 909                 pr_cont("0x%x%s",
 910                        bp->def_status_blk->sp_sb.index_values[i],
 911                        (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 912
 913         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
 914                 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
 915                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
 916                         i*sizeof(u32));
 917
 918         pr_cont("igu_sb_id(0x%x)  igu_seg_id (0x%x) "
 919                          "pf_id(0x%x)  vnic_id(0x%x)  "
 920                          "vf_id(0x%x)  vf_valid (0x%x)\n",
 921                sp_sb_data.igu_sb_id,
 922                sp_sb_data.igu_seg_id,
 923                sp_sb_data.p_func.pf_id,
 924                sp_sb_data.p_func.vnic_id,
 925                sp_sb_data.p_func.vf_id,
 926                sp_sb_data.p_func.vf_valid);
 927
 928
 929         for_each_eth_queue(bp, i) {
 930                 struct bnx2x_fastpath *fp = &bp->fp[i];
 931                 int loop;
 932                 struct hc_status_block_data_e2 sb_data_e2;
 933                 struct hc_status_block_data_e1x sb_data_e1x;
 934                 struct hc_status_block_sm  *hc_sm_p =
 935                         CHIP_IS_E2(bp) ?
 936                         sb_data_e2.common.state_machine :
 937                         sb_data_e1x.common.state_machine;
 938                 struct hc_index_data *hc_index_p =
 939                         CHIP_IS_E2(bp) ?
 940                         sb_data_e2.index_data :
 941                         sb_data_e1x.index_data;
 942                 int data_size;
 943                 u32 *sb_data_p;
 944
 945                 /* Rx */
 946                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)"
 947                           "  rx_comp_prod(0x%x)"
 948                           "  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 949                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 950                           fp->rx_comp_prod,
 951                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 952                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)"
 953                           "  fp_hc_idx(0x%x)\n",
 954                           fp->rx_sge_prod, fp->last_max_sge,
 955                           le16_to_cpu(fp->fp_hc_idx));
 956
 957                 /* Tx */
 958                 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)"
 959                           "  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)"
 960                           "  *tx_cons_sb(0x%x)\n",
 961                           i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
 962                           fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
 963
 964                 loop = CHIP_IS_E2(bp) ?
 965                         HC_SB_MAX_INDICES_E2 : HC_SB_MAX_INDICES_E1X;
 966
 967                 /* host sb data */
 968
 969 #ifdef BCM_CNIC
 970                 if (IS_FCOE_FP(fp))
 971                         continue;
 972 #endif
 973                 BNX2X_ERR("     run indexes (");
 974                 for (j = 0; j < HC_SB_MAX_SM; j++)
 975                         pr_cont("0x%x%s",
 976                                fp->sb_running_index[j],
 977                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
 978
 979                 BNX2X_ERR("     indexes (");
 980                 for (j = 0; j < loop; j++)
 981                         pr_cont("0x%x%s",
 982                                fp->sb_index_values[j],
 983                                (j == loop - 1) ? ")" : " ");
 984                 /* fw sb data */
 985                 data_size = CHIP_IS_E2(bp) ?
 986                         sizeof(struct hc_status_block_data_e2) :
 987                         sizeof(struct hc_status_block_data_e1x);
 988                 data_size /= sizeof(u32);
 989                 sb_data_p = CHIP_IS_E2(bp) ?
 990                         (u32 *)&sb_data_e2 :
 991                         (u32 *)&sb_data_e1x;
 992                 /* copy sb data in here */
 993                 for (j = 0; j < data_size; j++)
 994                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
 995                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
 996                                 j * sizeof(u32));
 997
 998                 if (CHIP_IS_E2(bp)) {
 999                         pr_cont("pf_id(0x%x)  vf_id (0x%x)  vf_valid(0x%x) "
1000                                 "vnic_id(0x%x)  same_igu_sb_1b(0x%x)\n",
1001                                 sb_data_e2.common.p_func.pf_id,
1002                                 sb_data_e2.common.p_func.vf_id,
1003                                 sb_data_e2.common.p_func.vf_valid,
1004                                 sb_data_e2.common.p_func.vnic_id,
1005                                 sb_data_e2.common.same_igu_sb_1b);
1006                 } else {
1007                         pr_cont("pf_id(0x%x)  vf_id (0x%x)  vf_valid(0x%x) "
1008                                 "vnic_id(0x%x)  same_igu_sb_1b(0x%x)\n",
1009                                 sb_data_e1x.common.p_func.pf_id,
1010                                 sb_data_e1x.common.p_func.vf_id,
1011                                 sb_data_e1x.common.p_func.vf_valid,
1012                                 sb_data_e1x.common.p_func.vnic_id,
1013                                 sb_data_e1x.common.same_igu_sb_1b);
1014                 }
1015
1016                 /* SB_SMs data */
1017                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1018                         pr_cont("SM[%d] __flags (0x%x) "
1019                                "igu_sb_id (0x%x)  igu_seg_id(0x%x) "
1020                                "time_to_expire (0x%x) "
1021                                "timer_value(0x%x)\n", j,
1022                                hc_sm_p[j].__flags,
1023                                hc_sm_p[j].igu_sb_id,
1024                                hc_sm_p[j].igu_seg_id,
1025                                hc_sm_p[j].time_to_expire,
1026                                hc_sm_p[j].timer_value);
1027                 }
1028
1029                 /* Indecies data */
1030                 for (j = 0; j < loop; j++) {
1031                         pr_cont("INDEX[%d] flags (0x%x) "
1032                                          "timeout (0x%x)\n", j,
1033                                hc_index_p[j].flags,
1034                                hc_index_p[j].timeout);
1035                 }
1036         }
1037
1038 #ifdef BNX2X_STOP_ON_ERROR
1039         /* Rings */
1040         /* Rx */
1041         for_each_rx_queue(bp, i) {
1042                 struct bnx2x_fastpath *fp = &bp->fp[i];
1043
1044                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1045                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1046                 for (j = start; j != end; j = RX_BD(j + 1)) {
1047                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1048                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1049
1050                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1051                                   i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
1052                 }
1053
1054                 start = RX_SGE(fp->rx_sge_prod);
1055                 end = RX_SGE(fp->last_max_sge);
1056                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1057                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1058                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1059
1060                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1061                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1062                 }
1063
1064                 start = RCQ_BD(fp->rx_comp_cons - 10);
1065                 end = RCQ_BD(fp->rx_comp_cons + 503);
1066                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1067                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1068
1069                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1070                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1071                 }
1072         }
1073
1074         /* Tx */
1075         for_each_tx_queue(bp, i) {
1076                 struct bnx2x_fastpath *fp = &bp->fp[i];
1077
1078                 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
1079                 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
1080                 for (j = start; j != end; j = TX_BD(j + 1)) {
1081                         struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
1082
1083                         BNX2X_ERR("fp%d: packet[%x]=[%p,%x]\n",
1084                                   i, j, sw_bd->skb, sw_bd->first_bd);
1085                 }
1086
1087                 start = TX_BD(fp->tx_bd_cons - 10);
1088                 end = TX_BD(fp->tx_bd_cons + 254);
1089                 for (j = start; j != end; j = TX_BD(j + 1)) {
1090                         u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
1091
1092                         BNX2X_ERR("fp%d: tx_bd[%x]=[%x:%x:%x:%x]\n",
1093                                   i, j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
1094                 }
1095         }
1096 #endif
1097         bnx2x_fw_dump(bp);
1098         bnx2x_mc_assert(bp);
1099         BNX2X_ERR("end crash dump -----------------\n");
1100 }
1101
1102 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1103 {
1104         int port = BP_PORT(bp);
1105         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1106         u32 val = REG_RD(bp, addr);
1107         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1108         int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1109
1110         if (msix) {
1111                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1112                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1113                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1114                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1115         } else if (msi) {
1116                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1117                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1118                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1119                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1120         } else {
1121                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1122                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1123                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1124                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1125
1126                 if (!CHIP_IS_E1(bp)) {
1127                         DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1128                            val, port, addr);
1129
1130                         REG_WR(bp, addr, val);
1131
1132                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1133                 }
1134         }
1135
1136         if (CHIP_IS_E1(bp))
1137                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1138
1139         DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)  mode %s\n",
1140            val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1141
1142         REG_WR(bp, addr, val);
1143         /*
1144          * Ensure that HC_CONFIG is written before leading/trailing edge config
1145          */
1146         mmiowb();
1147         barrier();
1148
1149         if (!CHIP_IS_E1(bp)) {
1150                 /* init leading/trailing edge */
1151                 if (IS_MF(bp)) {
1152                         val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1153                         if (bp->port.pmf)
1154                                 /* enable nig and gpio3 attention */
1155                                 val |= 0x1100;
1156                 } else
1157                         val = 0xffff;
1158
1159                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1160                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1161         }
1162
1163         /* Make sure that interrupts are indeed enabled from here on */
1164         mmiowb();
1165 }
1166
1167 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1168 {
1169         u32 val;
1170         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1171         int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1172
1173         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1174
1175         if (msix) {
1176                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1177                          IGU_PF_CONF_SINGLE_ISR_EN);
1178                 val |= (IGU_PF_CONF_FUNC_EN |
1179                         IGU_PF_CONF_MSI_MSIX_EN |
1180                         IGU_PF_CONF_ATTN_BIT_EN);
1181         } else if (msi) {
1182                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1183                 val |= (IGU_PF_CONF_FUNC_EN |
1184                         IGU_PF_CONF_MSI_MSIX_EN |
1185                         IGU_PF_CONF_ATTN_BIT_EN |
1186                         IGU_PF_CONF_SINGLE_ISR_EN);
1187         } else {
1188                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1189                 val |= (IGU_PF_CONF_FUNC_EN |
1190                         IGU_PF_CONF_INT_LINE_EN |
1191                         IGU_PF_CONF_ATTN_BIT_EN |
1192                         IGU_PF_CONF_SINGLE_ISR_EN);
1193         }
1194
1195         DP(NETIF_MSG_INTR, "write 0x%x to IGU  mode %s\n",
1196            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1197
1198         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1199
1200         barrier();
1201
1202         /* init leading/trailing edge */
1203         if (IS_MF(bp)) {
1204                 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1205                 if (bp->port.pmf)
1206                         /* enable nig and gpio3 attention */
1207                         val |= 0x1100;
1208         } else
1209                 val = 0xffff;
1210
1211         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1212         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1213
1214         /* Make sure that interrupts are indeed enabled from here on */
1215         mmiowb();
1216 }
1217
1218 void bnx2x_int_enable(struct bnx2x *bp)
1219 {
1220         if (bp->common.int_block == INT_BLOCK_HC)
1221                 bnx2x_hc_int_enable(bp);
1222         else
1223                 bnx2x_igu_int_enable(bp);
1224 }
1225
1226 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1227 {
1228         int port = BP_PORT(bp);
1229         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1230         u32 val = REG_RD(bp, addr);
1231
1232         /*
1233          * in E1 we must use only PCI configuration space to disable
1234          * MSI/MSIX capablility
1235          * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1236          */
1237         if (CHIP_IS_E1(bp)) {
1238                 /*  Since IGU_PF_CONF_MSI_MSIX_EN still always on
1239                  *  Use mask register to prevent from HC sending interrupts
1240                  *  after we exit the function
1241                  */
1242                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1243
1244                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1245                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
1246                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1247         } else
1248                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1249                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1250                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
1251                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1252
1253         DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1254            val, port, addr);
1255
1256         /* flush all outstanding writes */
1257         mmiowb();
1258
1259         REG_WR(bp, addr, val);
1260         if (REG_RD(bp, addr) != val)
1261                 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1262 }
1263
1264 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1265 {
1266         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1267
1268         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1269                  IGU_PF_CONF_INT_LINE_EN |
1270                  IGU_PF_CONF_ATTN_BIT_EN);
1271
1272         DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1273
1274         /* flush all outstanding writes */
1275         mmiowb();
1276
1277         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1278         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1279                 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1280 }
1281
1282 static void bnx2x_int_disable(struct bnx2x *bp)
1283 {
1284         if (bp->common.int_block == INT_BLOCK_HC)
1285                 bnx2x_hc_int_disable(bp);
1286         else
1287                 bnx2x_igu_int_disable(bp);
1288 }
1289
1290 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1291 {
1292         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1293         int i, offset;
1294
1295         /* disable interrupt handling */
1296         atomic_inc(&bp->intr_sem);
1297         smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
1298
1299         if (disable_hw)
1300                 /* prevent the HW from sending interrupts */
1301                 bnx2x_int_disable(bp);
1302
1303         /* make sure all ISRs are done */
1304         if (msix) {
1305                 synchronize_irq(bp->msix_table[0].vector);
1306                 offset = 1;
1307 #ifdef BCM_CNIC
1308                 offset++;
1309 #endif
1310                 for_each_eth_queue(bp, i)
1311                         synchronize_irq(bp->msix_table[i + offset].vector);
1312         } else
1313                 synchronize_irq(bp->pdev->irq);
1314
1315         /* make sure sp_task is not running */
1316         cancel_delayed_work(&bp->sp_task);
1317         flush_workqueue(bnx2x_wq);
1318 }
1319
1320 /* fast path */
1321
1322 /*
1323  * General service functions
1324  */
1325
1326 /* Return true if succeeded to acquire the lock */
1327 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1328 {
1329         u32 lock_status;
1330         u32 resource_bit = (1 << resource);
1331         int func = BP_FUNC(bp);
1332         u32 hw_lock_control_reg;
1333
1334         DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1335
1336         /* Validating that the resource is within range */
1337         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1338                 DP(NETIF_MSG_HW,
1339                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1340                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1341                 return false;
1342         }
1343
1344         if (func <= 5)
1345                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1346         else
1347                 hw_lock_control_reg =
1348                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1349
1350         /* Try to acquire the lock */
1351         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1352         lock_status = REG_RD(bp, hw_lock_control_reg);
1353         if (lock_status & resource_bit)
1354                 return true;
1355
1356         DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1357         return false;
1358 }
1359
1360 #ifdef BCM_CNIC
1361 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid);
1362 #endif
1363
1364 void bnx2x_sp_event(struct bnx2x_fastpath *fp,
1365                            union eth_rx_cqe *rr_cqe)
1366 {
1367         struct bnx2x *bp = fp->bp;
1368         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1369         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1370
1371         DP(BNX2X_MSG_SP,
1372            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1373            fp->index, cid, command, bp->state,
1374            rr_cqe->ramrod_cqe.ramrod_type);
1375
1376         switch (command | fp->state) {
1377         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP | BNX2X_FP_STATE_OPENING):
1378                 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n", cid);
1379                 fp->state = BNX2X_FP_STATE_OPEN;
1380                 break;
1381
1382         case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
1383                 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n", cid);
1384                 fp->state = BNX2X_FP_STATE_HALTED;
1385                 break;
1386
1387         case (RAMROD_CMD_ID_ETH_TERMINATE | BNX2X_FP_STATE_TERMINATING):
1388                 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] teminate ramrod\n", cid);
1389                 fp->state = BNX2X_FP_STATE_TERMINATED;
1390                 break;
1391
1392         default:
1393                 BNX2X_ERR("unexpected MC reply (%d)  "
1394                           "fp[%d] state is %x\n",
1395                           command, fp->index, fp->state);
1396                 break;
1397         }
1398
1399         smp_mb__before_atomic_inc();
1400         atomic_inc(&bp->spq_left);
1401         /* push the change in fp->state and towards the memory */
1402         smp_wmb();
1403
1404         return;
1405 }
1406
1407 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1408 {
1409         struct bnx2x *bp = netdev_priv(dev_instance);
1410         u16 status = bnx2x_ack_int(bp);
1411         u16 mask;
1412         int i;
1413
1414         /* Return here if interrupt is shared and it's not for us */
1415         if (unlikely(status == 0)) {
1416                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1417                 return IRQ_NONE;
1418         }
1419         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1420
1421         /* Return here if interrupt is disabled */
1422         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1423                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1424                 return IRQ_HANDLED;
1425         }
1426
1427 #ifdef BNX2X_STOP_ON_ERROR
1428         if (unlikely(bp->panic))
1429                 return IRQ_HANDLED;
1430 #endif
1431
1432         for_each_eth_queue(bp, i) {
1433                 struct bnx2x_fastpath *fp = &bp->fp[i];
1434
1435                 mask = 0x2 << (fp->index + CNIC_CONTEXT_USE);
1436                 if (status & mask) {
1437                         /* Handle Rx and Tx according to SB id */
1438                         prefetch(fp->rx_cons_sb);
1439                         prefetch(fp->tx_cons_sb);
1440                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1441                         napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1442                         status &= ~mask;
1443                 }
1444         }
1445
1446 #ifdef BCM_CNIC
1447         mask = 0x2;
1448         if (status & (mask | 0x1)) {
1449                 struct cnic_ops *c_ops = NULL;
1450
1451                 rcu_read_lock();
1452                 c_ops = rcu_dereference(bp->cnic_ops);
1453                 if (c_ops)
1454                         c_ops->cnic_handler(bp->cnic_data, NULL);
1455                 rcu_read_unlock();
1456
1457                 status &= ~mask;
1458         }
1459 #endif
1460
1461         if (unlikely(status & 0x1)) {
1462                 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1463
1464                 status &= ~0x1;
1465                 if (!status)
1466                         return IRQ_HANDLED;
1467         }
1468
1469         if (unlikely(status))
1470                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1471                    status);
1472
1473         return IRQ_HANDLED;
1474 }
1475
1476 /* end of fast path */
1477
1478
1479 /* Link */
1480
1481 /*
1482  * General service functions
1483  */
1484
1485 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1486 {
1487         u32 lock_status;
1488         u32 resource_bit = (1 << resource);
1489         int func = BP_FUNC(bp);
1490         u32 hw_lock_control_reg;
1491         int cnt;
1492
1493         /* Validating that the resource is within range */
1494         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1495                 DP(NETIF_MSG_HW,
1496                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1497                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1498                 return -EINVAL;
1499         }
1500
1501         if (func <= 5) {
1502                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1503         } else {
1504                 hw_lock_control_reg =
1505                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1506         }
1507
1508         /* Validating that the resource is not already taken */
1509         lock_status = REG_RD(bp, hw_lock_control_reg);
1510         if (lock_status & resource_bit) {
1511                 DP(NETIF_MSG_HW, "lock_status 0x%x  resource_bit 0x%x\n",
1512                    lock_status, resource_bit);
1513                 return -EEXIST;
1514         }
1515
1516         /* Try for 5 second every 5ms */
1517         for (cnt = 0; cnt < 1000; cnt++) {
1518                 /* Try to acquire the lock */
1519                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1520                 lock_status = REG_RD(bp, hw_lock_control_reg);
1521                 if (lock_status & resource_bit)
1522                         return 0;
1523
1524                 msleep(5);
1525         }
1526         DP(NETIF_MSG_HW, "Timeout\n");
1527         return -EAGAIN;
1528 }
1529
1530 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1531 {
1532         u32 lock_status;
1533         u32 resource_bit = (1 << resource);
1534         int func = BP_FUNC(bp);
1535         u32 hw_lock_control_reg;
1536
1537         DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1538
1539         /* Validating that the resource is within range */
1540         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1541                 DP(NETIF_MSG_HW,
1542                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1543                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1544                 return -EINVAL;
1545         }
1546
1547         if (func <= 5) {
1548                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1549         } else {
1550                 hw_lock_control_reg =
1551                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1552         }
1553
1554         /* Validating that the resource is currently taken */
1555         lock_status = REG_RD(bp, hw_lock_control_reg);
1556         if (!(lock_status & resource_bit)) {
1557                 DP(NETIF_MSG_HW, "lock_status 0x%x  resource_bit 0x%x\n",
1558                    lock_status, resource_bit);
1559                 return -EFAULT;
1560         }
1561
1562         REG_WR(bp, hw_lock_control_reg, resource_bit);
1563         return 0;
1564 }
1565
1566
1567 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1568 {
1569         /* The GPIO should be swapped if swap register is set and active */
1570         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1571                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1572         int gpio_shift = gpio_num +
1573                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1574         u32 gpio_mask = (1 << gpio_shift);
1575         u32 gpio_reg;
1576         int value;
1577
1578         if (gpio_num > MISC_REGISTERS_GPIO_3) {
1579                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1580                 return -EINVAL;
1581         }
1582
1583         /* read GPIO value */
1584         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1585
1586         /* get the requested pin value */
1587         if ((gpio_reg & gpio_mask) == gpio_mask)
1588                 value = 1;
1589         else
1590                 value = 0;
1591
1592         DP(NETIF_MSG_LINK, "pin %d  value 0x%x\n", gpio_num, value);
1593
1594         return value;
1595 }
1596
1597 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1598 {
1599         /* The GPIO should be swapped if swap register is set and active */
1600         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1601                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1602         int gpio_shift = gpio_num +
1603                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1604         u32 gpio_mask = (1 << gpio_shift);
1605         u32 gpio_reg;
1606
1607         if (gpio_num > MISC_REGISTERS_GPIO_3) {
1608                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1609                 return -EINVAL;
1610         }
1611
1612         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1613         /* read GPIO and mask except the float bits */
1614         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1615
1616         switch (mode) {
1617         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1618                 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1619                    gpio_num, gpio_shift);
1620                 /* clear FLOAT and set CLR */
1621                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1622                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1623                 break;
1624
1625         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1626                 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1627                    gpio_num, gpio_shift);
1628                 /* clear FLOAT and set SET */
1629                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1630                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1631                 break;
1632
1633         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1634                 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1635                    gpio_num, gpio_shift);
1636                 /* set FLOAT */
1637                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1638                 break;
1639
1640         default:
1641                 break;
1642         }
1643
1644         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1645         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1646
1647         return 0;
1648 }
1649
1650 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1651 {
1652         /* The GPIO should be swapped if swap register is set and active */
1653         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1654                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1655         int gpio_shift = gpio_num +
1656                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1657         u32 gpio_mask = (1 << gpio_shift);
1658         u32 gpio_reg;
1659
1660         if (gpio_num > MISC_REGISTERS_GPIO_3) {
1661                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1662                 return -EINVAL;
1663         }
1664
1665         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1666         /* read GPIO int */
1667         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
1668
1669         switch (mode) {
1670         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
1671                 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
1672                                    "output low\n", gpio_num, gpio_shift);
1673                 /* clear SET and set CLR */
1674                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1675                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1676                 break;
1677
1678         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
1679                 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
1680                                    "output high\n", gpio_num, gpio_shift);
1681                 /* clear CLR and set SET */
1682                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1683                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1684                 break;
1685
1686         default:
1687                 break;
1688         }
1689
1690         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
1691         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1692
1693         return 0;
1694 }
1695
1696 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1697 {
1698         u32 spio_mask = (1 << spio_num);
1699         u32 spio_reg;
1700
1701         if ((spio_num < MISC_REGISTERS_SPIO_4) ||
1702             (spio_num > MISC_REGISTERS_SPIO_7)) {
1703                 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
1704                 return -EINVAL;
1705         }
1706
1707         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1708         /* read SPIO and mask except the float bits */
1709         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
1710
1711         switch (mode) {
1712         case MISC_REGISTERS_SPIO_OUTPUT_LOW:
1713                 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
1714                 /* clear FLOAT and set CLR */
1715                 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1716                 spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
1717                 break;
1718
1719         case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
1720                 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
1721                 /* clear FLOAT and set SET */
1722                 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1723                 spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
1724                 break;
1725
1726         case MISC_REGISTERS_SPIO_INPUT_HI_Z:
1727                 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
1728                 /* set FLOAT */
1729                 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1730                 break;
1731
1732         default:
1733                 break;
1734         }
1735
1736         REG_WR(bp, MISC_REG_SPIO, spio_reg);
1737         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1738
1739         return 0;
1740 }
1741
1742 int bnx2x_get_link_cfg_idx(struct bnx2x *bp)
1743 {
1744         u32 sel_phy_idx = 0;
1745         if (bp->link_vars.link_up) {
1746                 sel_phy_idx = EXT_PHY1;
1747                 /* In case link is SERDES, check if the EXT_PHY2 is the one */
1748                 if ((bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
1749                     (bp->link_params.phy[EXT_PHY2].supported & SUPPORTED_FIBRE))
1750                         sel_phy_idx = EXT_PHY2;
1751         } else {
1752
1753                 switch (bnx2x_phy_selection(&bp->link_params)) {
1754                 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
1755                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
1756                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
1757                        sel_phy_idx = EXT_PHY1;
1758                        break;
1759                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
1760                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
1761                        sel_phy_idx = EXT_PHY2;
1762                        break;
1763                 }
1764         }
1765         /*
1766         * The selected actived PHY is always after swapping (in case PHY
1767         * swapping is enabled). So when swapping is enabled, we need to reverse
1768         * the configuration
1769         */
1770
1771         if (bp->link_params.multi_phy_config &
1772             PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
1773                 if (sel_phy_idx == EXT_PHY1)
1774                         sel_phy_idx = EXT_PHY2;
1775                 else if (sel_phy_idx == EXT_PHY2)
1776                         sel_phy_idx = EXT_PHY1;
1777         }
1778         return LINK_CONFIG_IDX(sel_phy_idx);
1779 }
1780
1781 void bnx2x_calc_fc_adv(struct bnx2x *bp)
1782 {
1783         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1784         switch (bp->link_vars.ieee_fc &
1785                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
1786         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
1787                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
1788                                                    ADVERTISED_Pause);
1789                 break;
1790
1791         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
1792                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
1793                                                   ADVERTISED_Pause);
1794                 break;
1795
1796         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
1797                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
1798                 break;
1799
1800         default:
1801                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
1802                                                    ADVERTISED_Pause);
1803                 break;
1804         }
1805 }
1806
1807 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
1808 {
1809         if (!BP_NOMCP(bp)) {
1810                 u8 rc;
1811                 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
1812                 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
1813                 /* Initialize link parameters structure variables */
1814                 /* It is recommended to turn off RX FC for jumbo frames
1815                    for better performance */
1816                 if ((CHIP_IS_E1x(bp)) && (bp->dev->mtu > 5000))
1817                         bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
1818                 else
1819                         bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
1820
1821                 bnx2x_acquire_phy_lock(bp);
1822
1823                 if (load_mode == LOAD_DIAG) {
1824                         bp->link_params.loopback_mode = LOOPBACK_XGXS;
1825                         bp->link_params.req_line_speed[cfx_idx] = SPEED_10000;
1826                 }
1827
1828                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1829
1830                 bnx2x_release_phy_lock(bp);
1831
1832                 bnx2x_calc_fc_adv(bp);
1833
1834                 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
1835                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
1836                         bnx2x_link_report(bp);
1837                 }
1838                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
1839                 return rc;
1840         }
1841         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
1842         return -EINVAL;
1843 }
1844
1845 void bnx2x_link_set(struct bnx2x *bp)
1846 {
1847         if (!BP_NOMCP(bp)) {
1848                 bnx2x_acquire_phy_lock(bp);
1849                 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
1850                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1851                 bnx2x_release_phy_lock(bp);
1852
1853                 bnx2x_calc_fc_adv(bp);
1854         } else
1855                 BNX2X_ERR("Bootcode is missing - can not set link\n");
1856 }
1857
1858 static void bnx2x__link_reset(struct bnx2x *bp)
1859 {
1860         if (!BP_NOMCP(bp)) {
1861                 bnx2x_acquire_phy_lock(bp);
1862                 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
1863                 bnx2x_release_phy_lock(bp);
1864         } else
1865                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
1866 }
1867
1868 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
1869 {
1870         u8 rc = 0;
1871
1872         if (!BP_NOMCP(bp)) {
1873                 bnx2x_acquire_phy_lock(bp);
1874                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
1875                                      is_serdes);
1876                 bnx2x_release_phy_lock(bp);
1877         } else
1878                 BNX2X_ERR("Bootcode is missing - can not test link\n");
1879
1880         return rc;
1881 }
1882
1883 static void bnx2x_init_port_minmax(struct bnx2x *bp)
1884 {
1885         u32 r_param = bp->link_vars.line_speed / 8;
1886         u32 fair_periodic_timeout_usec;
1887         u32 t_fair;
1888
1889         memset(&(bp->cmng.rs_vars), 0,
1890                sizeof(struct rate_shaping_vars_per_port));
1891         memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
1892
1893         /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
1894         bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
1895
1896         /* this is the threshold below which no timer arming will occur
1897            1.25 coefficient is for the threshold to be a little bigger
1898            than the real time, to compensate for timer in-accuracy */
1899         bp->cmng.rs_vars.rs_threshold =
1900                                 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
1901
1902         /* resolution of fairness timer */
1903         fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
1904         /* for 10G it is 1000usec. for 1G it is 10000usec. */
1905         t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
1906
1907         /* this is the threshold below which we won't arm the timer anymore */
1908         bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
1909
1910         /* we multiply by 1e3/8 to get bytes/msec.
1911            We don't want the credits to pass a credit
1912            of the t_fair*FAIR_MEM (algorithm resolution) */
1913         bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
1914         /* since each tick is 4 usec */
1915         bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
1916 }
1917
1918 /* Calculates the sum of vn_min_rates.
1919    It's needed for further normalizing of the min_rates.
1920    Returns:
1921      sum of vn_min_rates.
1922        or
1923      0 - if all the min_rates are 0.
1924      In the later case fainess algorithm should be deactivated.
1925      If not all min_rates are zero then those that are zeroes will be set to 1.
1926  */
1927 static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
1928 {
1929         int all_zero = 1;
1930         int vn;
1931
1932         bp->vn_weight_sum = 0;
1933         for (vn = VN_0; vn < E1HVN_MAX; vn++) {
1934                 u32 vn_cfg = bp->mf_config[vn];
1935                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1936                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
1937
1938                 /* Skip hidden vns */
1939                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
1940                         continue;
1941
1942                 /* If min rate is zero - set it to 1 */
1943                 if (!vn_min_rate)
1944                         vn_min_rate = DEF_MIN_RATE;
1945                 else
1946                         all_zero = 0;
1947
1948                 bp->vn_weight_sum += vn_min_rate;
1949         }
1950
1951         /* ... only if all min rates are zeros - disable fairness */
1952         if (all_zero) {
1953                 bp->cmng.flags.cmng_enables &=
1954                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
1955                 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
1956                    "  fairness will be disabled\n");
1957         } else
1958                 bp->cmng.flags.cmng_enables |=
1959                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
1960 }
1961
1962 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
1963 {
1964         struct rate_shaping_vars_per_vn m_rs_vn;
1965         struct fairness_vars_per_vn m_fair_vn;
1966         u32 vn_cfg = bp->mf_config[vn];
1967         int func = 2*vn + BP_PORT(bp);
1968         u16 vn_min_rate, vn_max_rate;
1969         int i;
1970
1971         /* If function is hidden - set min and max to zeroes */
1972         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
1973                 vn_min_rate = 0;
1974                 vn_max_rate = 0;
1975
1976         } else {
1977                 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1978                                 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
1979                 /* If min rate is zero - set it to 1 */
1980                 if (bp->vn_weight_sum && (vn_min_rate == 0))
1981                         vn_min_rate = DEF_MIN_RATE;
1982                 vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
1983                                 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
1984         }
1985
1986         DP(NETIF_MSG_IFUP,
1987            "func %d: vn_min_rate %d  vn_max_rate %d  vn_weight_sum %d\n",
1988            func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
1989
1990         memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
1991         memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
1992
1993         /* global vn counter - maximal Mbps for this vn */
1994         m_rs_vn.vn_counter.rate = vn_max_rate;
1995
1996         /* quota - number of bytes transmitted in this period */
1997         m_rs_vn.vn_counter.quota =
1998                                 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
1999
2000         if (bp->vn_weight_sum) {
2001                 /* credit for each period of the fairness algorithm:
2002                    number of bytes in T_FAIR (the vn share the port rate).
2003                    vn_weight_sum should not be larger than 10000, thus
2004                    T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2005                    than zero */
2006                 m_fair_vn.vn_credit_delta =
2007                         max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2008                                                    (8 * bp->vn_weight_sum))),
2009                               (bp->cmng.fair_vars.fair_threshold * 2));
2010                 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
2011                    m_fair_vn.vn_credit_delta);
2012         }
2013
2014         /* Store it to internal memory */
2015         for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2016                 REG_WR(bp, BAR_XSTRORM_INTMEM +
2017                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2018                        ((u32 *)(&m_rs_vn))[i]);
2019
2020         for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2021                 REG_WR(bp, BAR_XSTRORM_INTMEM +
2022                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2023                        ((u32 *)(&m_fair_vn))[i]);
2024 }
2025
2026 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2027 {
2028         if (CHIP_REV_IS_SLOW(bp))
2029                 return CMNG_FNS_NONE;
2030         if (IS_MF(bp))
2031                 return CMNG_FNS_MINMAX;
2032
2033         return CMNG_FNS_NONE;
2034 }
2035
2036 static void bnx2x_read_mf_cfg(struct bnx2x *bp)
2037 {
2038         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2039
2040         if (BP_NOMCP(bp))
2041                 return; /* what should be the default bvalue in this case */
2042
2043         /* For 2 port configuration the absolute function number formula
2044          * is:
2045          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2046          *
2047          *      and there are 4 functions per port
2048          *
2049          * For 4 port configuration it is
2050          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2051          *
2052          *      and there are 2 functions per port
2053          */
2054         for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2055                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2056
2057                 if (func >= E1H_FUNC_MAX)
2058                         break;
2059
2060                 bp->mf_config[vn] =
2061                         MF_CFG_RD(bp, func_mf_config[func].config);
2062         }
2063 }
2064
2065 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2066 {
2067
2068         if (cmng_type == CMNG_FNS_MINMAX) {
2069                 int vn;
2070
2071                 /* clear cmng_enables */
2072                 bp->cmng.flags.cmng_enables = 0;
2073
2074                 /* read mf conf from shmem */
2075                 if (read_cfg)
2076                         bnx2x_read_mf_cfg(bp);
2077
2078                 /* Init rate shaping and fairness contexts */
2079                 bnx2x_init_port_minmax(bp);
2080
2081                 /* vn_weight_sum and enable fairness if not 0 */
2082                 bnx2x_calc_vn_weight_sum(bp);
2083
2084                 /* calculate and set min-max rate for each vn */
2085                 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2086                         bnx2x_init_vn_minmax(bp, vn);
2087
2088                 /* always enable rate shaping and fairness */
2089                 bp->cmng.flags.cmng_enables |=
2090                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2091                 if (!bp->vn_weight_sum)
2092                         DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2093                                    "  fairness will be disabled\n");
2094                 return;
2095         }
2096
2097         /* rate shaping and fairness are disabled */
2098         DP(NETIF_MSG_IFUP,
2099            "rate shaping and fairness are disabled\n");
2100 }
2101
2102 static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2103 {
2104         int port = BP_PORT(bp);
2105         int func;
2106         int vn;
2107
2108         /* Set the attention towards other drivers on the same port */
2109         for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2110                 if (vn == BP_E1HVN(bp))
2111                         continue;
2112
2113                 func = ((vn << 1) | port);
2114                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2115                        (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2116         }
2117 }
2118
2119 /* This function is called upon link interrupt */
2120 static void bnx2x_link_attn(struct bnx2x *bp)
2121 {
2122         u32 prev_link_status = bp->link_vars.link_status;
2123         /* Make sure that we are synced with the current statistics */
2124         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2125
2126         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2127
2128         if (bp->link_vars.link_up) {
2129
2130                 /* dropless flow control */
2131                 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2132                         int port = BP_PORT(bp);
2133                         u32 pause_enabled = 0;
2134
2135                         if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2136                                 pause_enabled = 1;
2137
2138                         REG_WR(bp, BAR_USTRORM_INTMEM +
2139                                USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2140                                pause_enabled);
2141                 }
2142
2143                 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
2144                         struct host_port_stats *pstats;
2145
2146                         pstats = bnx2x_sp(bp, port_stats);
2147                         /* reset old bmac stats */
2148                         memset(&(pstats->mac_stx[0]), 0,
2149                                sizeof(struct mac_stx));
2150                 }
2151                 if (bp->state == BNX2X_STATE_OPEN)
2152                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2153         }
2154
2155         /* indicate link status only if link status actually changed */
2156         if (prev_link_status != bp->link_vars.link_status)
2157                 bnx2x_link_report(bp);
2158
2159         if (IS_MF(bp))
2160                 bnx2x_link_sync_notify(bp);
2161
2162         if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2163                 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2164
2165                 if (cmng_fns != CMNG_FNS_NONE) {
2166                         bnx2x_cmng_fns_init(bp, false, cmng_fns);
2167                         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2168                 } else
2169                         /* rate shaping and fairness are disabled */
2170                         DP(NETIF_MSG_IFUP,
2171                            "single function mode without fairness\n");
2172         }
2173 }
2174
2175 void bnx2x__link_status_update(struct bnx2x *bp)
2176 {
2177         if ((bp->state != BNX2X_STATE_OPEN) || (bp->flags & MF_FUNC_DIS))
2178                 return;
2179
2180         bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2181
2182         if (bp->link_vars.link_up)
2183                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2184         else
2185                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2186
2187         /* the link status update could be the result of a DCC event
2188            hence re-read the shmem mf configuration */
2189         bnx2x_read_mf_cfg(bp);
2190
2191         /* indicate link status */
2192         bnx2x_link_report(bp);
2193 }
2194
2195 static void bnx2x_pmf_update(struct bnx2x *bp)
2196 {
2197         int port = BP_PORT(bp);
2198         u32 val;
2199
2200         bp->port.pmf = 1;
2201         DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2202
2203         /* enable nig attention */
2204         val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
2205         if (bp->common.int_block == INT_BLOCK_HC) {
2206                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2207                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2208         } else if (CHIP_IS_E2(bp)) {
2209                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2210                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2211         }
2212
2213         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2214 }
2215
2216 /* end of Link */
2217
2218 /* slow path */
2219
2220 /*
2221  * General service functions
2222  */
2223
2224 /* send the MCP a request, block until there is a reply */
2225 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2226 {
2227         int mb_idx = BP_FW_MB_IDX(bp);
2228         u32 seq = ++bp->fw_seq;
2229         u32 rc = 0;
2230         u32 cnt = 1;
2231         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2232
2233         mutex_lock(&bp->fw_mb_mutex);
2234         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2235         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2236
2237         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
2238
2239         do {
2240                 /* let the FW do it's magic ... */
2241                 msleep(delay);
2242
2243                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2244
2245                 /* Give the FW up to 5 second (500*10ms) */
2246         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2247
2248         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2249            cnt*delay, rc, seq);
2250
2251         /* is this a reply to our command? */
2252         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2253                 rc &= FW_MSG_CODE_MASK;
2254         else {
2255                 /* FW BUG! */
2256                 BNX2X_ERR("FW failed to respond!\n");
2257                 bnx2x_fw_dump(bp);
2258                 rc = 0;
2259         }
2260         mutex_unlock(&bp->fw_mb_mutex);
2261
2262         return rc;
2263 }
2264
2265 static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2266 {
2267 #ifdef BCM_CNIC
2268         if (IS_FCOE_FP(fp) && IS_MF(bp))
2269                 return false;
2270 #endif
2271         return true;
2272 }
2273
2274 /* must be called under rtnl_lock */
2275 static void bnx2x_rxq_set_mac_filters(struct bnx2x *bp, u16 cl_id, u32 filters)
2276 {
2277         u32 mask = (1 << cl_id);
2278
2279         /* initial seeting is BNX2X_ACCEPT_NONE */
2280         u8 drop_all_ucast = 1, drop_all_bcast = 1, drop_all_mcast = 1;
2281         u8 accp_all_ucast = 0, accp_all_bcast = 0, accp_all_mcast = 0;
2282         u8 unmatched_unicast = 0;
2283
2284         if (filters & BNX2X_ACCEPT_UNMATCHED_UCAST)
2285                 unmatched_unicast = 1;
2286
2287         if (filters & BNX2X_PROMISCUOUS_MODE) {
2288                 /* promiscious - accept all, drop none */
2289                 drop_all_ucast = drop_all_bcast = drop_all_mcast = 0;
2290                 accp_all_ucast = accp_all_bcast = accp_all_mcast = 1;
2291                 if (IS_MF_SI(bp)) {
2292                         /*
2293                          * SI mode defines to accept in promiscuos mode
2294                          * only unmatched packets
2295                          */
2296                         unmatched_unicast = 1;
2297                         accp_all_ucast = 0;
2298                 }
2299         }
2300         if (filters & BNX2X_ACCEPT_UNICAST) {
2301                 /* accept matched ucast */
2302                 drop_all_ucast = 0;
2303         }
2304         if (filters & BNX2X_ACCEPT_MULTICAST) {
2305                 /* accept matched mcast */
2306                 drop_all_mcast = 0;
2307                 if (IS_MF_SI(bp))
2308                         /* since mcast addresses won't arrive with ovlan,
2309                          * fw needs to accept all of them in
2310                          * switch-independent mode */
2311                         accp_all_mcast = 1;
2312         }
2313         if (filters & BNX2X_ACCEPT_ALL_UNICAST) {
2314                 /* accept all mcast */
2315                 drop_all_ucast = 0;
2316                 accp_all_ucast = 1;
2317         }
2318         if (filters & BNX2X_ACCEPT_ALL_MULTICAST) {
2319                 /* accept all mcast */
2320                 drop_all_mcast = 0;
2321                 accp_all_mcast = 1;
2322         }
2323         if (filters & BNX2X_ACCEPT_BROADCAST) {
2324                 /* accept (all) bcast */
2325                 drop_all_bcast = 0;
2326                 accp_all_bcast = 1;
2327         }
2328
2329         bp->mac_filters.ucast_drop_all = drop_all_ucast ?
2330                 bp->mac_filters.ucast_drop_all | mask :
2331                 bp->mac_filters.ucast_drop_all & ~mask;
2332
2333         bp->mac_filters.mcast_drop_all = drop_all_mcast ?
2334                 bp->mac_filters.mcast_drop_all | mask :
2335                 bp->mac_filters.mcast_drop_all & ~mask;
2336
2337         bp->mac_filters.bcast_drop_all = drop_all_bcast ?
2338                 bp->mac_filters.bcast_drop_all | mask :
2339                 bp->mac_filters.bcast_drop_all & ~mask;
2340
2341         bp->mac_filters.ucast_accept_all = accp_all_ucast ?
2342                 bp->mac_filters.ucast_accept_all | mask :
2343                 bp->mac_filters.ucast_accept_all & ~mask;
2344
2345         bp->mac_filters.mcast_accept_all = accp_all_mcast ?
2346                 bp->mac_filters.mcast_accept_all | mask :
2347                 bp->mac_filters.mcast_accept_all & ~mask;
2348
2349         bp->mac_filters.bcast_accept_all = accp_all_bcast ?
2350                 bp->mac_filters.bcast_accept_all | mask :
2351                 bp->mac_filters.bcast_accept_all & ~mask;
2352
2353         bp->mac_filters.unmatched_unicast = unmatched_unicast ?
2354                 bp->mac_filters.unmatched_unicast | mask :
2355                 bp->mac_filters.unmatched_unicast & ~mask;
2356 }
2357
2358 static void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2359 {
2360         struct tstorm_eth_function_common_config tcfg = {0};
2361         u16 rss_flgs;
2362
2363         /* tpa */
2364         if (p->func_flgs & FUNC_FLG_TPA)
2365                 tcfg.config_flags |=
2366                 TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA;
2367
2368         /* set rss flags */
2369         rss_flgs = (p->rss->mode <<
2370                 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT);
2371
2372         if (p->rss->cap & RSS_IPV4_CAP)
2373                 rss_flgs |= RSS_IPV4_CAP_MASK;
2374         if (p->rss->cap & RSS_IPV4_TCP_CAP)
2375                 rss_flgs |= RSS_IPV4_TCP_CAP_MASK;
2376         if (p->rss->cap & RSS_IPV6_CAP)
2377                 rss_flgs |= RSS_IPV6_CAP_MASK;
2378         if (p->rss->cap & RSS_IPV6_TCP_CAP)
2379                 rss_flgs |= RSS_IPV6_TCP_CAP_MASK;
2380
2381         tcfg.config_flags |= rss_flgs;
2382         tcfg.rss_result_mask = p->rss->result_mask;
2383
2384         storm_memset_func_cfg(bp, &tcfg, p->func_id);
2385
2386         /* Enable the function in the FW */
2387         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2388         storm_memset_func_en(bp, p->func_id, 1);
2389
2390         /* statistics */
2391         if (p->func_flgs & FUNC_FLG_STATS) {
2392                 struct stats_indication_flags stats_flags = {0};
2393                 stats_flags.collect_eth = 1;
2394
2395                 storm_memset_xstats_flags(bp, &stats_flags, p->func_id);
2396                 storm_memset_xstats_addr(bp, p->fw_stat_map, p->func_id);
2397
2398                 storm_memset_tstats_flags(bp, &stats_flags, p->func_id);
2399                 storm_memset_tstats_addr(bp, p->fw_stat_map, p->func_id);
2400
2401                 storm_memset_ustats_flags(bp, &stats_flags, p->func_id);
2402                 storm_memset_ustats_addr(bp, p->fw_stat_map, p->func_id);
2403
2404                 storm_memset_cstats_flags(bp, &stats_flags, p->func_id);
2405                 storm_memset_cstats_addr(bp, p->fw_stat_map, p->func_id);
2406         }
2407
2408         /* spq */
2409         if (p->func_flgs & FUNC_FLG_SPQ) {
2410                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2411                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2412                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2413         }
2414 }
2415
2416 static inline u16 bnx2x_get_cl_flags(struct bnx2x *bp,
2417                                      struct bnx2x_fastpath *fp)
2418 {
2419         u16 flags = 0;
2420
2421         /* calculate queue flags */
2422         flags |= QUEUE_FLG_CACHE_ALIGN;
2423         flags |= QUEUE_FLG_HC;
2424         flags |= IS_MF_SD(bp) ? QUEUE_FLG_OV : 0;
2425
2426         flags |= QUEUE_FLG_VLAN;
2427         DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
2428
2429         if (!fp->disable_tpa)
2430                 flags |= QUEUE_FLG_TPA;
2431
2432         flags = stat_counter_valid(bp, fp) ?
2433                         (flags | QUEUE_FLG_STATS) : (flags & ~QUEUE_FLG_STATS);
2434
2435         return flags;
2436 }
2437
2438 static void bnx2x_pf_rx_cl_prep(struct bnx2x *bp,
2439         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2440         struct bnx2x_rxq_init_params *rxq_init)
2441 {
2442         u16 max_sge = 0;
2443         u16 sge_sz = 0;
2444         u16 tpa_agg_size = 0;
2445
2446         /* calculate queue flags */
2447         u16 flags = bnx2x_get_cl_flags(bp, fp);
2448
2449         if (!fp->disable_tpa) {
2450                 pause->sge_th_hi = 250;
2451                 pause->sge_th_lo = 150;
2452                 tpa_agg_size = min_t(u32,
2453                         (min_t(u32, 8, MAX_SKB_FRAGS) *
2454                         SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2455                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2456                         SGE_PAGE_SHIFT;
2457                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2458                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2459                 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2460                                     0xffff);
2461         }
2462
2463         /* pause - not for e1 */
2464         if (!CHIP_IS_E1(bp)) {
2465                 pause->bd_th_hi = 350;
2466                 pause->bd_th_lo = 250;
2467                 pause->rcq_th_hi = 350;
2468                 pause->rcq_th_lo = 250;
2469                 pause->sge_th_hi = 0;
2470                 pause->sge_th_lo = 0;
2471                 pause->pri_map = 1;
2472         }
2473
2474         /* rxq setup */
2475         rxq_init->flags = flags;
2476         rxq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2477         rxq_init->dscr_map = fp->rx_desc_mapping;
2478         rxq_init->sge_map = fp->rx_sge_mapping;
2479         rxq_init->rcq_map = fp->rx_comp_mapping;
2480         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2481         rxq_init->mtu = bp->dev->mtu;
2482         rxq_init->buf_sz = bp->rx_buf_size;
2483         rxq_init->cl_qzone_id = fp->cl_qzone_id;
2484         rxq_init->cl_id = fp->cl_id;
2485         rxq_init->spcl_id = fp->cl_id;
2486         rxq_init->stat_id = fp->cl_id;
2487         rxq_init->tpa_agg_sz = tpa_agg_size;
2488         rxq_init->sge_buf_sz = sge_sz;
2489         rxq_init->max_sges_pkt = max_sge;
2490         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2491         rxq_init->fw_sb_id = fp->fw_sb_id;
2492
2493         if (IS_FCOE_FP(fp))
2494                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2495         else
2496                 rxq_init->sb_cq_index = U_SB_ETH_RX_CQ_INDEX;
2497
2498         rxq_init->cid = HW_CID(bp, fp->cid);
2499
2500         rxq_init->hc_rate = bp->rx_ticks ? (1000000 / bp->rx_ticks) : 0;
2501 }
2502
2503 static void bnx2x_pf_tx_cl_prep(struct bnx2x *bp,
2504         struct bnx2x_fastpath *fp, struct bnx2x_txq_init_params *txq_init)
2505 {
2506         u16 flags = bnx2x_get_cl_flags(bp, fp);
2507
2508         txq_init->flags = flags;
2509         txq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2510         txq_init->dscr_map = fp->tx_desc_mapping;
2511         txq_init->stat_id = fp->cl_id;
2512         txq_init->cid = HW_CID(bp, fp->cid);
2513         txq_init->sb_cq_index = C_SB_ETH_TX_CQ_INDEX;
2514         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2515         txq_init->fw_sb_id = fp->fw_sb_id;
2516
2517         if (IS_FCOE_FP(fp)) {
2518                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2519                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2520         }
2521
2522         txq_init->hc_rate = bp->tx_ticks ? (1000000 / bp->tx_ticks) : 0;
2523 }
2524
2525 static void bnx2x_pf_init(struct bnx2x *bp)
2526 {
2527         struct bnx2x_func_init_params func_init = {0};
2528         struct bnx2x_rss_params rss = {0};
2529         struct event_ring_data eq_data = { {0} };
2530         u16 flags;
2531
2532         /* pf specific setups */
2533         if (!CHIP_IS_E1(bp))
2534                 storm_memset_ov(bp, bp->mf_ov, BP_FUNC(bp));
2535
2536         if (CHIP_IS_E2(bp)) {
2537                 /* reset IGU PF statistics: MSIX + ATTN */
2538                 /* PF */
2539                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2540                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2541                            (CHIP_MODE_IS_4_PORT(bp) ?
2542                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2543                 /* ATTN */
2544                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2545                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2546                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2547                            (CHIP_MODE_IS_4_PORT(bp) ?
2548                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2549         }
2550
2551         /* function setup flags */
2552         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2553
2554         if (CHIP_IS_E1x(bp))
2555                 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2556         else
2557                 flags |= FUNC_FLG_TPA;
2558
2559         /* function setup */
2560
2561         /**
2562          * Although RSS is meaningless when there is a single HW queue we
2563          * still need it enabled in order to have HW Rx hash generated.
2564          */
2565         rss.cap = (RSS_IPV4_CAP | RSS_IPV4_TCP_CAP |
2566                    RSS_IPV6_CAP | RSS_IPV6_TCP_CAP);
2567         rss.mode = bp->multi_mode;
2568         rss.result_mask = MULTI_MASK;
2569         func_init.rss = &rss;
2570
2571         func_init.func_flgs = flags;
2572         func_init.pf_id = BP_FUNC(bp);
2573         func_init.func_id = BP_FUNC(bp);
2574         func_init.fw_stat_map = bnx2x_sp_mapping(bp, fw_stats);
2575         func_init.spq_map = bp->spq_mapping;
2576         func_init.spq_prod = bp->spq_prod_idx;
2577
2578         bnx2x_func_init(bp, &func_init);
2579
2580         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2581
2582         /*
2583         Congestion management values depend on the link rate
2584         There is no active link so initial link rate is set to 10 Gbps.
2585         When the link comes up The congestion management values are
2586         re-calculated according to the actual link rate.
2587         */
2588         bp->link_vars.line_speed = SPEED_10000;
2589         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2590
2591         /* Only the PMF sets the HW */
2592         if (bp->port.pmf)
2593                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2594
2595         /* no rx until link is up */
2596         bp->rx_mode = BNX2X_RX_MODE_NONE;
2597         bnx2x_set_storm_rx_mode(bp);
2598
2599         /* init Event Queue */
2600         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2601         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2602         eq_data.producer = bp->eq_prod;
2603         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2604         eq_data.sb_id = DEF_SB_ID;
2605         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2606 }
2607
2608
2609 static void bnx2x_e1h_disable(struct bnx2x *bp)
2610 {
2611         int port = BP_PORT(bp);
2612
2613         netif_tx_disable(bp->dev);
2614
2615         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2616
2617         netif_carrier_off(bp->dev);
2618 }
2619
2620 static void bnx2x_e1h_enable(struct bnx2x *bp)
2621 {
2622         int port = BP_PORT(bp);
2623
2624         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2625
2626         /* Tx queue should be only reenabled */
2627         netif_tx_wake_all_queues(bp->dev);
2628
2629         /*
2630          * Should not call netif_carrier_on since it will be called if the link
2631          * is up when checking for link state
2632          */
2633 }
2634
2635 /* called due to MCP event (on pmf):
2636  *      reread new bandwidth configuration
2637  *      configure FW
2638  *      notify others function about the change
2639  */
2640 static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2641 {
2642         if (bp->link_vars.link_up) {
2643                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2644                 bnx2x_link_sync_notify(bp);
2645         }
2646         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2647 }
2648
2649 static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2650 {
2651         bnx2x_config_mf_bw(bp);
2652         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2653 }
2654
2655 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2656 {
2657         DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2658
2659         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2660
2661                 /*
2662                  * This is the only place besides the function initialization
2663                  * where the bp->flags can change so it is done without any
2664                  * locks
2665                  */
2666                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2667                         DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2668                         bp->flags |= MF_FUNC_DIS;
2669
2670                         bnx2x_e1h_disable(bp);
2671                 } else {
2672                         DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2673                         bp->flags &= ~MF_FUNC_DIS;
2674
2675                         bnx2x_e1h_enable(bp);
2676                 }
2677                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2678         }
2679         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
2680                 bnx2x_config_mf_bw(bp);
2681                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2682         }
2683
2684         /* Report results to MCP */
2685         if (dcc_event)
2686                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2687         else
2688                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2689 }
2690
2691 /* must be called under the spq lock */
2692 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2693 {
2694         struct eth_spe *next_spe = bp->spq_prod_bd;
2695
2696         if (bp->spq_prod_bd == bp->spq_last_bd) {
2697                 bp->spq_prod_bd = bp->spq;
2698                 bp->spq_prod_idx = 0;
2699                 DP(NETIF_MSG_TIMER, "end of spq\n");
2700         } else {
2701                 bp->spq_prod_bd++;
2702                 bp->spq_prod_idx++;
2703         }
2704         return next_spe;
2705 }
2706
2707 /* must be called under the spq lock */
2708 static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
2709 {
2710         int func = BP_FUNC(bp);
2711
2712         /* Make sure that BD data is updated before writing the producer */
2713         wmb();
2714
2715         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
2716                  bp->spq_prod_idx);
2717         mmiowb();
2718 }
2719
2720 /* the slow path queue is odd since completions arrive on the fastpath ring */
2721 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2722                   u32 data_hi, u32 data_lo, int common)
2723 {
2724         struct eth_spe *spe;
2725         u16 type;
2726
2727 #ifdef BNX2X_STOP_ON_ERROR
2728         if (unlikely(bp->panic))
2729                 return -EIO;
2730 #endif
2731
2732         spin_lock_bh(&bp->spq_lock);
2733
2734         if (!atomic_read(&bp->spq_left)) {
2735                 BNX2X_ERR("BUG! SPQ ring full!\n");
2736                 spin_unlock_bh(&bp->spq_lock);
2737                 bnx2x_panic();
2738                 return -EBUSY;
2739         }
2740
2741         spe = bnx2x_sp_get_next(bp);
2742
2743         /* CID needs port number to be encoded int it */
2744         spe->hdr.conn_and_cmd_data =
2745                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
2746                                     HW_CID(bp, cid));
2747
2748         if (common)
2749                 /* Common ramrods:
2750                  *      FUNC_START, FUNC_STOP, CFC_DEL, STATS, SET_MAC
2751                  *      TRAFFIC_STOP, TRAFFIC_START
2752                  */
2753                 type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2754                         & SPE_HDR_CONN_TYPE;
2755         else
2756                 /* ETH ramrods: SETUP, HALT */
2757                 type = (ETH_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2758                         & SPE_HDR_CONN_TYPE;
2759
2760         type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
2761                  SPE_HDR_FUNCTION_ID);
2762
2763         spe->hdr.type = cpu_to_le16(type);
2764
2765         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
2766         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
2767
2768         /* stats ramrod has it's own slot on the spq */
2769         if (command != RAMROD_CMD_ID_COMMON_STAT_QUERY)
2770                 /* It's ok if the actual decrement is issued towards the memory
2771                  * somewhere between the spin_lock and spin_unlock. Thus no
2772                  * more explict memory barrier is needed.
2773                  */
2774                 atomic_dec(&bp->spq_left);
2775
2776         DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
2777            "SPQE[%x] (%x:%x)  command %d  hw_cid %x  data (%x:%x) "
2778            "type(0x%x) left %x\n",
2779            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
2780            (u32)(U64_LO(bp->spq_mapping) +
2781            (void *)bp->spq_prod_bd - (void *)bp->spq), command,
2782            HW_CID(bp, cid), data_hi, data_lo, type, atomic_read(&bp->spq_left));
2783
2784         bnx2x_sp_prod_update(bp);
2785         spin_unlock_bh(&bp->spq_lock);
2786         return 0;
2787 }
2788
2789 /* acquire split MCP access lock register */
2790 static int bnx2x_acquire_alr(struct bnx2x *bp)
2791 {
2792         u32 j, val;
2793         int rc = 0;
2794
2795         might_sleep();
2796         for (j = 0; j < 1000; j++) {
2797                 val = (1UL << 31);
2798                 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2799                 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
2800                 if (val & (1L << 31))
2801                         break;
2802
2803                 msleep(5);
2804         }
2805         if (!(val & (1L << 31))) {
2806                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
2807                 rc = -EBUSY;
2808         }
2809
2810         return rc;
2811 }
2812
2813 /* release split MCP access lock register */
2814 static void bnx2x_release_alr(struct bnx2x *bp)
2815 {
2816         REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
2817 }
2818
2819 #define BNX2X_DEF_SB_ATT_IDX    0x0001
2820 #define BNX2X_DEF_SB_IDX        0x0002
2821
2822 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2823 {
2824         struct host_sp_status_block *def_sb = bp->def_status_blk;
2825         u16 rc = 0;
2826
2827         barrier(); /* status block is written to by the chip */
2828         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2829                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
2830                 rc |= BNX2X_DEF_SB_ATT_IDX;
2831         }
2832
2833         if (bp->def_idx != def_sb->sp_sb.running_index) {
2834                 bp->def_idx = def_sb->sp_sb.running_index;
2835                 rc |= BNX2X_DEF_SB_IDX;
2836         }
2837
2838         /* Do not reorder: indecies reading should complete before handling */
2839         barrier();
2840         return rc;
2841 }
2842
2843 /*
2844  * slow path service functions
2845  */
2846
2847 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2848 {
2849         int port = BP_PORT(bp);
2850         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2851                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
2852         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2853                                        NIG_REG_MASK_INTERRUPT_PORT0;
2854         u32 aeu_mask;
2855         u32 nig_mask = 0;
2856         u32 reg_addr;
2857
2858         if (bp->attn_state & asserted)
2859                 BNX2X_ERR("IGU ERROR\n");
2860
2861         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2862         aeu_mask = REG_RD(bp, aeu_addr);
2863
2864         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
2865            aeu_mask, asserted);
2866         aeu_mask &= ~(asserted & 0x3ff);
2867         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2868
2869         REG_WR(bp, aeu_addr, aeu_mask);
2870         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2871
2872         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2873         bp->attn_state |= asserted;
2874         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2875
2876         if (asserted & ATTN_HARD_WIRED_MASK) {
2877                 if (asserted & ATTN_NIG_FOR_FUNC) {
2878
2879                         bnx2x_acquire_phy_lock(bp);
2880
2881                         /* save nig interrupt mask */
2882                         nig_mask = REG_RD(bp, nig_int_mask_addr);
2883                         REG_WR(bp, nig_int_mask_addr, 0);
2884
2885                         bnx2x_link_attn(bp);
2886
2887                         /* handle unicore attn? */
2888                 }
2889                 if (asserted & ATTN_SW_TIMER_4_FUNC)
2890                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
2891
2892                 if (asserted & GPIO_2_FUNC)
2893                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
2894
2895                 if (asserted & GPIO_3_FUNC)
2896                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
2897
2898                 if (asserted & GPIO_4_FUNC)
2899                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
2900
2901                 if (port == 0) {
2902                         if (asserted & ATTN_GENERAL_ATTN_1) {
2903                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
2904                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2905                         }
2906                         if (asserted & ATTN_GENERAL_ATTN_2) {
2907                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
2908                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2909                         }
2910                         if (asserted & ATTN_GENERAL_ATTN_3) {
2911                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
2912                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2913                         }
2914                 } else {
2915                         if (asserted & ATTN_GENERAL_ATTN_4) {
2916                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
2917                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2918                         }
2919                         if (asserted & ATTN_GENERAL_ATTN_5) {
2920                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
2921                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2922                         }
2923                         if (asserted & ATTN_GENERAL_ATTN_6) {
2924                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
2925                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2926                         }
2927                 }
2928
2929         } /* if hardwired */
2930
2931         if (bp->common.int_block == INT_BLOCK_HC)
2932                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
2933                             COMMAND_REG_ATTN_BITS_SET);
2934         else
2935                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
2936
2937         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
2938            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
2939         REG_WR(bp, reg_addr, asserted);
2940
2941         /* now set back the mask */
2942         if (asserted & ATTN_NIG_FOR_FUNC) {
2943                 REG_WR(bp, nig_int_mask_addr, nig_mask);
2944                 bnx2x_release_phy_lock(bp);
2945         }
2946 }
2947
2948 static inline void bnx2x_fan_failure(struct bnx2x *bp)
2949 {
2950         int port = BP_PORT(bp);
2951         u32 ext_phy_config;
2952         /* mark the failure */
2953         ext_phy_config =
2954                 SHMEM_RD(bp,
2955                          dev_info.port_hw_config[port].external_phy_config);
2956
2957         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2958         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2959         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
2960                  ext_phy_config);
2961
2962         /* log the failure */
2963         netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
2964                " the driver to shutdown the card to prevent permanent"
2965                " damage.  Please contact OEM Support for assistance\n");
2966 }
2967
2968 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
2969 {
2970         int port = BP_PORT(bp);
2971         int reg_offset;
2972         u32 val;
2973
2974         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
2975                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
2976
2977         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
2978
2979                 val = REG_RD(bp, reg_offset);
2980                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
2981                 REG_WR(bp, reg_offset, val);
2982
2983                 BNX2X_ERR("SPIO5 hw attention\n");
2984
2985                 /* Fan failure attention */
2986                 bnx2x_hw_reset_phy(&bp->link_params);
2987                 bnx2x_fan_failure(bp);
2988         }
2989
2990         if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
2991                     AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) {
2992                 bnx2x_acquire_phy_lock(bp);
2993                 bnx2x_handle_module_detect_int(&bp->link_params);
2994                 bnx2x_release_phy_lock(bp);
2995         }
2996
2997         if (attn & HW_INTERRUT_ASSERT_SET_0) {
2998
2999                 val = REG_RD(bp, reg_offset);
3000                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3001                 REG_WR(bp, reg_offset, val);
3002
3003                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3004                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3005                 bnx2x_panic();
3006         }
3007 }
3008
3009 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3010 {
3011         u32 val;
3012
3013         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3014
3015                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3016                 BNX2X_ERR("DB hw attention 0x%x\n", val);
3017                 /* DORQ discard attention */
3018                 if (val & 0x2)
3019                         BNX2X_ERR("FATAL error from DORQ\n");
3020         }
3021
3022         if (attn & HW_INTERRUT_ASSERT_SET_1) {
3023
3024                 int port = BP_PORT(bp);
3025                 int reg_offset;
3026
3027                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3028                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3029
3030                 val = REG_RD(bp, reg_offset);
3031                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3032                 REG_WR(bp, reg_offset, val);
3033
3034                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3035                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3036                 bnx2x_panic();
3037         }
3038 }
3039
3040 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3041 {
3042         u32 val;
3043
3044         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3045
3046                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3047                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3048                 /* CFC error attention */
3049                 if (val & 0x2)
3050                         BNX2X_ERR("FATAL error from CFC\n");
3051         }
3052
3053         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3054
3055                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3056                 BNX2X_ERR("PXP hw attention 0x%x\n", val);
3057                 /* RQ_USDMDP_FIFO_OVERFLOW */
3058                 if (val & 0x18000)
3059                         BNX2X_ERR("FATAL error from PXP\n");
3060                 if (CHIP_IS_E2(bp)) {
3061                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3062                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3063                 }
3064         }
3065
3066         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3067
3068                 int port = BP_PORT(bp);
3069                 int reg_offset;
3070
3071                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3072                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3073
3074                 val = REG_RD(bp, reg_offset);
3075                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3076                 REG_WR(bp, reg_offset, val);
3077
3078                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3079                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3080                 bnx2x_panic();
3081         }
3082 }
3083
3084 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3085 {
3086         u32 val;
3087
3088         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3089
3090                 if (attn & BNX2X_PMF_LINK_ASSERT) {
3091                         int func = BP_FUNC(bp);
3092
3093                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3094                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3095                                         func_mf_config[BP_ABS_FUNC(bp)].config);
3096                         val = SHMEM_RD(bp,
3097                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
3098                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3099                                 bnx2x_dcc_event(bp,
3100                                             (val & DRV_STATUS_DCC_EVENT_MASK));
3101
3102                         if (val & DRV_STATUS_SET_MF_BW)
3103                                 bnx2x_set_mf_bw(bp);
3104
3105                         bnx2x__link_status_update(bp);
3106                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3107                                 bnx2x_pmf_update(bp);
3108
3109                         if (bp->port.pmf &&
3110                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3111                                 bp->dcbx_enabled > 0)
3112                                 /* start dcbx state machine */
3113                                 bnx2x_dcbx_set_params(bp,
3114                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
3115                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3116
3117                         BNX2X_ERR("MC assert!\n");
3118                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3119                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3120                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3121                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3122                         bnx2x_panic();
3123
3124                 } else if (attn & BNX2X_MCP_ASSERT) {
3125
3126                         BNX2X_ERR("MCP assert!\n");
3127                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3128                         bnx2x_fw_dump(bp);
3129
3130                 } else
3131                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3132         }
3133
3134         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3135                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3136                 if (attn & BNX2X_GRC_TIMEOUT) {
3137                         val = CHIP_IS_E1(bp) ? 0 :
3138                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3139                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
3140                 }
3141                 if (attn & BNX2X_GRC_RSV) {
3142                         val = CHIP_IS_E1(bp) ? 0 :
3143                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3144                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
3145                 }
3146                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3147         }
3148 }
3149
3150 #define BNX2X_MISC_GEN_REG      MISC_REG_GENERIC_POR_1
3151 #define LOAD_COUNTER_BITS       16 /* Number of bits for load counter */
3152 #define LOAD_COUNTER_MASK       (((u32)0x1 << LOAD_COUNTER_BITS) - 1)
3153 #define RESET_DONE_FLAG_MASK    (~LOAD_COUNTER_MASK)
3154 #define RESET_DONE_FLAG_SHIFT   LOAD_COUNTER_BITS
3155
3156 /*
3157  * should be run under rtnl lock
3158  */
3159 static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3160 {
3161         u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3162         val &= ~(1 << RESET_DONE_FLAG_SHIFT);
3163         REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3164         barrier();
3165         mmiowb();
3166 }
3167
3168 /*
3169  * should be run under rtnl lock
3170  */
3171 static inline void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3172 {
3173         u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3174         val |= (1 << 16);
3175         REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3176         barrier();
3177         mmiowb();
3178 }
3179
3180 /*
3181  * should be run under rtnl lock
3182  */
3183 bool bnx2x_reset_is_done(struct bnx2x *bp)
3184 {
3185         u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3186         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3187         return (val & RESET_DONE_FLAG_MASK) ? false : true;
3188 }
3189
3190 /*
3191  * should be run under rtnl lock
3192  */
3193 inline void bnx2x_inc_load_cnt(struct bnx2x *bp)
3194 {
3195         u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3196
3197         DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3198
3199         val1 = ((val & LOAD_COUNTER_MASK) + 1) & LOAD_COUNTER_MASK;
3200         REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3201         barrier();
3202         mmiowb();
3203 }
3204
3205 /*
3206  * should be run under rtnl lock
3207  */
3208 u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
3209 {
3210         u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3211
3212         DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3213
3214         val1 = ((val & LOAD_COUNTER_MASK) - 1) & LOAD_COUNTER_MASK;
3215         REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3216         barrier();
3217         mmiowb();
3218
3219         return val1;
3220 }
3221
3222 /*
3223  * should be run under rtnl lock
3224  */
3225 static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp)
3226 {
3227         return REG_RD(bp, BNX2X_MISC_GEN_REG) & LOAD_COUNTER_MASK;
3228 }
3229
3230 static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3231 {
3232         u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3233         REG_WR(bp, BNX2X_MISC_GEN_REG, val & (~LOAD_COUNTER_MASK));
3234 }
3235
3236 static inline void _print_next_block(int idx, const char *blk)
3237 {
3238         if (idx)
3239                 pr_cont(", ");
3240         pr_cont("%s", blk);
3241 }
3242
3243 static inline int bnx2x_print_blocks_with_parity0(u32 sig, int par_num)
3244 {
3245         int i = 0;
3246         u32 cur_bit = 0;
3247         for (i = 0; sig; i++) {
3248                 cur_bit = ((u32)0x1 << i);
3249                 if (sig & cur_bit) {
3250                         switch (cur_bit) {
3251                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3252                                 _print_next_block(par_num++, "BRB");
3253                                 break;
3254                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3255                                 _print_next_block(par_num++, "PARSER");
3256                                 break;
3257                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3258                                 _print_next_block(par_num++, "TSDM");
3259                                 break;
3260                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3261                                 _print_next_block(par_num++, "SEARCHER");
3262                                 break;
3263                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3264                                 _print_next_block(par_num++, "TSEMI");
3265                                 break;
3266                         }
3267
3268                         /* Clear the bit */
3269                         sig &= ~cur_bit;
3270                 }
3271         }
3272
3273         return par_num;
3274 }
3275
3276 static inline int bnx2x_print_blocks_with_parity1(u32 sig, int par_num)
3277 {
3278         int i = 0;
3279         u32 cur_bit = 0;
3280         for (i = 0; sig; i++) {
3281                 cur_bit = ((u32)0x1 << i);
3282                 if (sig & cur_bit) {
3283                         switch (cur_bit) {
3284                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3285                                 _print_next_block(par_num++, "PBCLIENT");
3286                                 break;
3287                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3288                                 _print_next_block(par_num++, "QM");
3289                                 break;
3290                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3291                                 _print_next_block(par_num++, "XSDM");
3292                                 break;
3293                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3294                                 _print_next_block(par_num++, "XSEMI");
3295                                 break;
3296                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3297                                 _print_next_block(par_num++, "DOORBELLQ");
3298                                 break;
3299                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3300                                 _print_next_block(par_num++, "VAUX PCI CORE");
3301                                 break;
3302                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3303                                 _print_next_block(par_num++, "DEBUG");
3304                                 break;
3305                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3306                                 _print_next_block(par_num++, "USDM");
3307                                 break;
3308                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3309                                 _print_next_block(par_num++, "USEMI");
3310                                 break;
3311                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3312                                 _print_next_block(par_num++, "UPB");
3313                                 break;
3314                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3315                                 _print_next_block(par_num++, "CSDM");
3316                                 break;
3317                         }
3318
3319                         /* Clear the bit */
3320                         sig &= ~cur_bit;
3321                 }
3322         }
3323
3324         return par_num;
3325 }
3326
3327 static inline int bnx2x_print_blocks_with_parity2(u32 sig, int par_num)
3328 {
3329         int i = 0;
3330         u32 cur_bit = 0;
3331         for (i = 0; sig; i++) {
3332                 cur_bit = ((u32)0x1 << i);
3333                 if (sig & cur_bit) {
3334                         switch (cur_bit) {
3335                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3336                                 _print_next_block(par_num++, "CSEMI");
3337                                 break;
3338                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3339                                 _print_next_block(par_num++, "PXP");
3340                                 break;
3341                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3342                                 _print_next_block(par_num++,
3343                                         "PXPPCICLOCKCLIENT");
3344                                 break;
3345                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3346                                 _print_next_block(par_num++, "CFC");
3347                                 break;
3348                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3349                                 _print_next_block(par_num++, "CDU");
3350                                 break;
3351                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3352                                 _print_next_block(par_num++, "IGU");
3353                                 break;
3354                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3355                                 _print_next_block(par_num++, "MISC");
3356                                 break;
3357                         }
3358
3359                         /* Clear the bit */
3360                         sig &= ~cur_bit;
3361                 }
3362         }
3363
3364         return par_num;
3365 }
3366
3367 static inline int bnx2x_print_blocks_with_parity3(u32 sig, int par_num)
3368 {
3369         int i = 0;
3370         u32 cur_bit = 0;
3371         for (i = 0; sig; i++) {
3372                 cur_bit = ((u32)0x1 << i);
3373                 if (sig & cur_bit) {
3374                         switch (cur_bit) {
3375                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3376                                 _print_next_block(par_num++, "MCP ROM");
3377                                 break;
3378                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3379                                 _print_next_block(par_num++, "MCP UMP RX");
3380                                 break;
3381                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3382                                 _print_next_block(par_num++, "MCP UMP TX");
3383                                 break;
3384                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3385                                 _print_next_block(par_num++, "MCP SCPAD");
3386                                 break;
3387                         }
3388
3389                         /* Clear the bit */
3390                         sig &= ~cur_bit;
3391                 }
3392         }
3393
3394         return par_num;
3395 }
3396
3397 static inline bool bnx2x_parity_attn(struct bnx2x *bp, u32 sig0, u32 sig1,
3398                                      u32 sig2, u32 sig3)
3399 {
3400         if ((sig0 & HW_PRTY_ASSERT_SET_0) || (sig1 & HW_PRTY_ASSERT_SET_1) ||
3401             (sig2 & HW_PRTY_ASSERT_SET_2) || (sig3 & HW_PRTY_ASSERT_SET_3)) {
3402                 int par_num = 0;
3403                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
3404                         "[0]:0x%08x [1]:0x%08x "
3405                         "[2]:0x%08x [3]:0x%08x\n",
3406                           sig0 & HW_PRTY_ASSERT_SET_0,
3407                           sig1 & HW_PRTY_ASSERT_SET_1,
3408                           sig2 & HW_PRTY_ASSERT_SET_2,
3409                           sig3 & HW_PRTY_ASSERT_SET_3);
3410                 printk(KERN_ERR"%s: Parity errors detected in blocks: ",
3411                        bp->dev->name);
3412                 par_num = bnx2x_print_blocks_with_parity0(
3413                         sig0 & HW_PRTY_ASSERT_SET_0, par_num);
3414                 par_num = bnx2x_print_blocks_with_parity1(
3415                         sig1 & HW_PRTY_ASSERT_SET_1, par_num);
3416                 par_num = bnx2x_print_blocks_with_parity2(
3417                         sig2 & HW_PRTY_ASSERT_SET_2, par_num);
3418                 par_num = bnx2x_print_blocks_with_parity3(
3419                         sig3 & HW_PRTY_ASSERT_SET_3, par_num);
3420                 printk("\n");
3421                 return true;
3422         } else
3423                 return false;
3424 }
3425
3426 bool bnx2x_chk_parity_attn(struct bnx2x *bp)
3427 {
3428         struct attn_route attn;
3429         int port = BP_PORT(bp);
3430
3431         attn.sig[0] = REG_RD(bp,
3432                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
3433                              port*4);
3434         attn.sig[1] = REG_RD(bp,
3435                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
3436                              port*4);
3437         attn.sig[2] = REG_RD(bp,
3438                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
3439                              port*4);
3440         attn.sig[3] = REG_RD(bp,
3441                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
3442                              port*4);
3443
3444         return bnx2x_parity_attn(bp, attn.sig[0], attn.sig[1], attn.sig[2],
3445                                         attn.sig[3]);
3446 }
3447
3448
3449 static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
3450 {
3451         u32 val;
3452         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3453
3454                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3455                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
3456                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3457                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3458                                   "ADDRESS_ERROR\n");
3459                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3460                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3461                                   "INCORRECT_RCV_BEHAVIOR\n");
3462                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3463                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3464                                   "WAS_ERROR_ATTN\n");
3465                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3466                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3467                                   "VF_LENGTH_VIOLATION_ATTN\n");
3468                 if (val &
3469                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3470                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3471                                   "VF_GRC_SPACE_VIOLATION_ATTN\n");
3472                 if (val &
3473                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3474                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3475                                   "VF_MSIX_BAR_VIOLATION_ATTN\n");
3476                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3477                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3478                                   "TCPL_ERROR_ATTN\n");
3479                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3480                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3481                                   "TCPL_IN_TWO_RCBS_ATTN\n");
3482                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3483                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3484                                   "CSSNOOP_FIFO_OVERFLOW\n");
3485         }
3486         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3487                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
3488                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
3489                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3490                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
3491                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3492                         BNX2X_ERR("ATC_ATC_INT_STS_REG"
3493                                   "_ATC_TCPL_TO_NOT_PEND\n");
3494                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3495                         BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3496                                   "ATC_GPA_MULTIPLE_HITS\n");
3497                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3498                         BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3499                                   "ATC_RCPL_TO_EMPTY_CNT\n");
3500                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3501                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
3502                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3503                         BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3504                                   "ATC_IREQ_LESS_THAN_STU\n");
3505         }
3506
3507         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3508                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3509                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
3510                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3511                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3512         }
3513
3514 }
3515
3516 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
3517 {
3518         struct attn_route attn, *group_mask;
3519         int port = BP_PORT(bp);
3520         int index;
3521         u32 reg_addr;
3522         u32 val;
3523         u32 aeu_mask;
3524
3525         /* need to take HW lock because MCP or other port might also
3526            try to handle this event */
3527         bnx2x_acquire_alr(bp);
3528
3529         if (CHIP_PARITY_ENABLED(bp) && bnx2x_chk_parity_attn(bp)) {
3530                 bp->recovery_state = BNX2X_RECOVERY_INIT;
3531                 bnx2x_set_reset_in_progress(bp);
3532                 schedule_delayed_work(&bp->reset_task, 0);
3533                 /* Disable HW interrupts */
3534                 bnx2x_int_disable(bp);
3535                 bnx2x_release_alr(bp);
3536                 /* In case of parity errors don't handle attentions so that
3537                  * other function would "see" parity errors.
3538                  */
3539                 return;
3540         }
3541
3542         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
3543         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
3544         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
3545         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
3546         if (CHIP_IS_E2(bp))
3547                 attn.sig[4] =
3548                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
3549         else
3550                 attn.sig[4] = 0;
3551
3552         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
3553            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
3554
3555         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
3556                 if (deasserted & (1 << index)) {
3557                         group_mask = &bp->attn_group[index];
3558
3559                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
3560                                          "%08x %08x %08x\n",
3561                            index,
3562                            group_mask->sig[0], group_mask->sig[1],
3563                            group_mask->sig[2], group_mask->sig[3],
3564                            group_mask->sig[4]);
3565
3566                         bnx2x_attn_int_deasserted4(bp,
3567                                         attn.sig[4] & group_mask->sig[4]);
3568                         bnx2x_attn_int_deasserted3(bp,
3569                                         attn.sig[3] & group_mask->sig[3]);
3570                         bnx2x_attn_int_deasserted1(bp,
3571                                         attn.sig[1] & group_mask->sig[1]);
3572                         bnx2x_attn_int_deasserted2(bp,
3573                                         attn.sig[2] & group_mask->sig[2]);
3574                         bnx2x_attn_int_deasserted0(bp,
3575                                         attn.sig[0] & group_mask->sig[0]);
3576                 }
3577         }
3578
3579         bnx2x_release_alr(bp);
3580
3581         if (bp->common.int_block == INT_BLOCK_HC)
3582                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3583                             COMMAND_REG_ATTN_BITS_CLR);
3584         else
3585                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
3586
3587         val = ~deasserted;
3588         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
3589            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3590         REG_WR(bp, reg_addr, val);
3591
3592         if (~bp->attn_state & deasserted)
3593                 BNX2X_ERR("IGU ERROR\n");
3594
3595         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3596                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
3597
3598         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3599         aeu_mask = REG_RD(bp, reg_addr);
3600
3601         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
3602            aeu_mask, deasserted);
3603         aeu_mask |= (deasserted & 0x3ff);
3604         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3605
3606         REG_WR(bp, reg_addr, aeu_mask);
3607         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3608
3609         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3610         bp->attn_state &= ~deasserted;
3611         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3612 }
3613
3614 static void bnx2x_attn_int(struct bnx2x *bp)
3615 {
3616         /* read local copy of bits */
3617         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
3618                                                                 attn_bits);
3619         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
3620                                                                 attn_bits_ack);
3621         u32 attn_state = bp->attn_state;
3622
3623         /* look for changed bits */
3624         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
3625         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
3626
3627         DP(NETIF_MSG_HW,
3628            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
3629            attn_bits, attn_ack, asserted, deasserted);
3630
3631         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
3632                 BNX2X_ERR("BAD attention state\n");
3633
3634         /* handle bits that were raised */
3635         if (asserted)
3636                 bnx2x_attn_int_asserted(bp, asserted);
3637
3638         if (deasserted)
3639                 bnx2x_attn_int_deasserted(bp, deasserted);
3640 }
3641
3642 static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
3643 {
3644         /* No memory barriers */
3645         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
3646         mmiowb(); /* keep prod updates ordered */
3647 }
3648
3649 #ifdef BCM_CNIC
3650 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
3651                                       union event_ring_elem *elem)
3652 {
3653         if (!bp->cnic_eth_dev.starting_cid  ||
3654             cid < bp->cnic_eth_dev.starting_cid)
3655                 return 1;
3656
3657         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
3658
3659         if (unlikely(elem->message.data.cfc_del_event.error)) {
3660                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
3661                           cid);
3662                 bnx2x_panic_dump(bp);
3663         }
3664         bnx2x_cnic_cfc_comp(bp, cid);
3665         return 0;
3666 }
3667 #endif
3668
3669 static void bnx2x_eq_int(struct bnx2x *bp)
3670 {
3671         u16 hw_cons, sw_cons, sw_prod;
3672         union event_ring_elem *elem;
3673         u32 cid;
3674         u8 opcode;
3675         int spqe_cnt = 0;
3676
3677         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
3678
3679         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
3680          * when we get the the next-page we nned to adjust so the loop
3681          * condition below will be met. The next element is the size of a
3682          * regular element and hence incrementing by 1
3683          */
3684         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
3685                 hw_cons++;
3686
3687         /* This function may never run in parralel with itself for a
3688          * specific bp, thus there is no need in "paired" read memory
3689          * barrier here.
3690          */
3691         sw_cons = bp->eq_cons;
3692         sw_prod = bp->eq_prod;
3693
3694         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->spq_left %u\n",
3695                         hw_cons, sw_cons, atomic_read(&bp->spq_left));
3696
3697         for (; sw_cons != hw_cons;
3698               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
3699
3700
3701                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
3702
3703                 cid = SW_CID(elem->message.data.cfc_del_event.cid);
3704                 opcode = elem->message.opcode;
3705
3706
3707                 /* handle eq element */
3708                 switch (opcode) {
3709                 case EVENT_RING_OPCODE_STAT_QUERY:
3710                         DP(NETIF_MSG_TIMER, "got statistics comp event\n");
3711                         /* nothing to do with stats comp */
3712                         continue;
3713
3714                 case EVENT_RING_OPCODE_CFC_DEL:
3715                         /* handle according to cid range */
3716                         /*
3717                          * we may want to verify here that the bp state is
3718                          * HALTING
3719                          */
3720                         DP(NETIF_MSG_IFDOWN,
3721                            "got delete ramrod for MULTI[%d]\n", cid);
3722 #ifdef BCM_CNIC
3723                         if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
3724                                 goto next_spqe;
3725                         if (cid == BNX2X_FCOE_ETH_CID)
3726                                 bnx2x_fcoe(bp, state) = BNX2X_FP_STATE_CLOSED;
3727                         else
3728 #endif
3729                                 bnx2x_fp(bp, cid, state) =
3730                                                 BNX2X_FP_STATE_CLOSED;
3731
3732                         goto next_spqe;
3733
3734                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
3735                         DP(NETIF_MSG_IFUP, "got STOP TRAFFIC\n");
3736                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
3737                         goto next_spqe;
3738                 case EVENT_RING_OPCODE_START_TRAFFIC:
3739                         DP(NETIF_MSG_IFUP, "got START TRAFFIC\n");
3740                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
3741                         goto next_spqe;
3742                 }
3743
3744                 switch (opcode | bp->state) {
3745                 case (EVENT_RING_OPCODE_FUNCTION_START |
3746                       BNX2X_STATE_OPENING_WAIT4_PORT):
3747                         DP(NETIF_MSG_IFUP, "got setup ramrod\n");
3748                         bp->state = BNX2X_STATE_FUNC_STARTED;
3749                         break;
3750
3751                 case (EVENT_RING_OPCODE_FUNCTION_STOP |
3752                       BNX2X_STATE_CLOSING_WAIT4_HALT):
3753                         DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
3754                         bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
3755                         break;
3756
3757                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
3758                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
3759                         DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
3760                         bp->set_mac_pending = 0;
3761                         break;
3762
3763                 case (EVENT_RING_OPCODE_SET_MAC |
3764                       BNX2X_STATE_CLOSING_WAIT4_HALT):
3765                         DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
3766                         bp->set_mac_pending = 0;
3767                         break;
3768                 default:
3769                         /* unknown event log error and continue */
3770                         BNX2X_ERR("Unknown EQ event %d\n",
3771                                   elem->message.opcode);
3772                 }
3773 next_spqe:
3774                 spqe_cnt++;
3775         } /* for */
3776
3777         smp_mb__before_atomic_inc();
3778         atomic_add(spqe_cnt, &bp->spq_left);
3779
3780         bp->eq_cons = sw_cons;
3781         bp->eq_prod = sw_prod;
3782         /* Make sure that above mem writes were issued towards the memory */
3783         smp_wmb();
3784
3785         /* update producer */
3786         bnx2x_update_eq_prod(bp, bp->eq_prod);
3787 }
3788
3789 static void bnx2x_sp_task(struct work_struct *work)
3790 {
3791         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
3792         u16 status;
3793
3794         /* Return here if interrupt is disabled */
3795         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
3796                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
3797                 return;
3798         }
3799
3800         status = bnx2x_update_dsb_idx(bp);
3801 /*      if (status == 0)                                     */
3802 /*              BNX2X_ERR("spurious slowpath interrupt!\n"); */
3803
3804         DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
3805
3806         /* HW attentions */
3807         if (status & BNX2X_DEF_SB_ATT_IDX) {
3808                 bnx2x_attn_int(bp);
3809                 status &= ~BNX2X_DEF_SB_ATT_IDX;
3810         }
3811
3812         /* SP events: STAT_QUERY and others */
3813         if (status & BNX2X_DEF_SB_IDX) {
3814 #ifdef BCM_CNIC
3815                 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
3816
3817                 if ((!NO_FCOE(bp)) &&
3818                         (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp)))
3819                         napi_schedule(&bnx2x_fcoe(bp, napi));
3820 #endif
3821                 /* Handle EQ completions */
3822                 bnx2x_eq_int(bp);
3823
3824                 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
3825                         le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
3826
3827                 status &= ~BNX2X_DEF_SB_IDX;
3828         }
3829
3830         if (unlikely(status))
3831                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
3832                    status);
3833
3834         bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
3835              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
3836 }
3837
3838 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
3839 {
3840         struct net_device *dev = dev_instance;
3841         struct bnx2x *bp = netdev_priv(dev);
3842
3843         /* Return here if interrupt is disabled */
3844         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
3845                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
3846                 return IRQ_HANDLED;
3847         }
3848
3849         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
3850                      IGU_INT_DISABLE, 0);
3851
3852 #ifdef BNX2X_STOP_ON_ERROR
3853         if (unlikely(bp->panic))
3854                 return IRQ_HANDLED;
3855 #endif
3856
3857 #ifdef BCM_CNIC
3858         {
3859                 struct cnic_ops *c_ops;
3860
3861                 rcu_read_lock();
3862                 c_ops = rcu_dereference(bp->cnic_ops);
3863                 if (c_ops)
3864                         c_ops->cnic_handler(bp->cnic_data, NULL);
3865                 rcu_read_unlock();
3866         }
3867 #endif
3868         queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
3869
3870         return IRQ_HANDLED;
3871 }
3872
3873 /* end of slow path */
3874
3875 static void bnx2x_timer(unsigned long data)
3876 {
3877         struct bnx2x *bp = (struct bnx2x *) data;
3878
3879         if (!netif_running(bp->dev))
3880                 return;
3881
3882         if (atomic_read(&bp->intr_sem) != 0)
3883                 goto timer_restart;
3884
3885         if (poll) {
3886                 struct bnx2x_fastpath *fp = &bp->fp[0];
3887                 int rc;
3888
3889                 bnx2x_tx_int(fp);
3890                 rc = bnx2x_rx_int(fp, 1000);
3891         }
3892
3893         if (!BP_NOMCP(bp)) {
3894                 int mb_idx = BP_FW_MB_IDX(bp);
3895                 u32 drv_pulse;
3896                 u32 mcp_pulse;
3897
3898                 ++bp->fw_drv_pulse_wr_seq;
3899                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
3900                 /* TBD - add SYSTEM_TIME */
3901                 drv_pulse = bp->fw_drv_pulse_wr_seq;
3902                 SHMEM_WR(bp, func_mb[mb_idx].drv_pulse_mb, drv_pulse);
3903
3904                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
3905                              MCP_PULSE_SEQ_MASK);
3906                 /* The delta between driver pulse and mcp response
3907                  * should be 1 (before mcp response) or 0 (after mcp response)
3908                  */
3909                 if ((drv_pulse != mcp_pulse) &&
3910                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
3911                         /* someone lost a heartbeat... */
3912                         BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
3913                                   drv_pulse, mcp_pulse);
3914                 }
3915         }
3916
3917         if (bp->state == BNX2X_STATE_OPEN)
3918                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
3919
3920 timer_restart:
3921         mod_timer(&bp->timer, jiffies + bp->current_interval);
3922 }
3923
3924 /* end of Statistics */
3925
3926 /* nic init */
3927
3928 /*
3929  * nic init service functions
3930  */
3931
3932 static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
3933 {
3934         u32 i;
3935         if (!(len%4) && !(addr%4))
3936                 for (i = 0; i < len; i += 4)
3937                         REG_WR(bp, addr + i, fill);
3938         else
3939                 for (i = 0; i < len; i++)
3940                         REG_WR8(bp, addr + i, fill);
3941
3942 }
3943
3944 /* helper: writes FP SP data to FW - data_size in dwords */
3945 static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
3946                                        int fw_sb_id,
3947                                        u32 *sb_data_p,
3948                                        u32 data_size)
3949 {
3950         int index;
3951         for (index = 0; index < data_size; index++)
3952                 REG_WR(bp, BAR_CSTRORM_INTMEM +
3953                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
3954                         sizeof(u32)*index,
3955                         *(sb_data_p + index));
3956 }
3957
3958 static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
3959 {
3960         u32 *sb_data_p;
3961         u32 data_size = 0;
3962         struct hc_status_block_data_e2 sb_data_e2;
3963         struct hc_status_block_data_e1x sb_data_e1x;
3964
3965         /* disable the function first */
3966         if (CHIP_IS_E2(bp)) {
3967                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
3968                 sb_data_e2.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3969                 sb_data_e2.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3970                 sb_data_e2.common.p_func.vf_valid = false;
3971                 sb_data_p = (u32 *)&sb_data_e2;
3972                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
3973         } else {
3974                 memset(&sb_data_e1x, 0,
3975                        sizeof(struct hc_status_block_data_e1x));
3976                 sb_data_e1x.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3977                 sb_data_e1x.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3978                 sb_data_e1x.common.p_func.vf_valid = false;
3979                 sb_data_p = (u32 *)&sb_data_e1x;
3980                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
3981         }
3982         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
3983
3984         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
3985                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
3986                         CSTORM_STATUS_BLOCK_SIZE);
3987         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
3988                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
3989                         CSTORM_SYNC_BLOCK_SIZE);
3990 }
3991
3992 /* helper:  writes SP SB data to FW */
3993 static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
3994                 struct hc_sp_status_block_data *sp_sb_data)
3995 {
3996         int func = BP_FUNC(bp);
3997         int i;
3998         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
3999                 REG_WR(bp, BAR_CSTRORM_INTMEM +
4000                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4001                         i*sizeof(u32),
4002                         *((u32 *)sp_sb_data + i));
4003 }
4004
4005 static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
4006 {
4007         int func = BP_FUNC(bp);
4008         struct hc_sp_status_block_data sp_sb_data;
4009         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4010
4011         sp_sb_data.p_func.pf_id = HC_FUNCTION_DISABLED;
4012         sp_sb_data.p_func.vf_id = HC_FUNCTION_DISABLED;
4013         sp_sb_data.p_func.vf_valid = false;
4014
4015         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4016
4017         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4018                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4019                         CSTORM_SP_STATUS_BLOCK_SIZE);
4020         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4021                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4022                         CSTORM_SP_SYNC_BLOCK_SIZE);
4023
4024 }
4025
4026
4027 static inline
4028 void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4029                                            int igu_sb_id, int igu_seg_id)
4030 {
4031         hc_sm->igu_sb_id = igu_sb_id;
4032         hc_sm->igu_seg_id = igu_seg_id;
4033         hc_sm->timer_value = 0xFF;
4034         hc_sm->time_to_expire = 0xFFFFFFFF;
4035 }
4036
4037 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
4038                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
4039 {
4040         int igu_seg_id;
4041
4042         struct hc_status_block_data_e2 sb_data_e2;
4043         struct hc_status_block_data_e1x sb_data_e1x;
4044         struct hc_status_block_sm  *hc_sm_p;
4045         struct hc_index_data *hc_index_p;
4046         int data_size;
4047         u32 *sb_data_p;
4048
4049         if (CHIP_INT_MODE_IS_BC(bp))
4050                 igu_seg_id = HC_SEG_ACCESS_NORM;
4051         else
4052                 igu_seg_id = IGU_SEG_ACCESS_NORM;
4053
4054         bnx2x_zero_fp_sb(bp, fw_sb_id);
4055
4056         if (CHIP_IS_E2(bp)) {
4057                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4058                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4059                 sb_data_e2.common.p_func.vf_id = vfid;
4060                 sb_data_e2.common.p_func.vf_valid = vf_valid;
4061                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4062                 sb_data_e2.common.same_igu_sb_1b = true;
4063                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4064                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4065                 hc_sm_p = sb_data_e2.common.state_machine;
4066                 hc_index_p = sb_data_e2.index_data;
4067                 sb_data_p = (u32 *)&sb_data_e2;
4068                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4069         } else {
4070                 memset(&sb_data_e1x, 0,
4071                        sizeof(struct hc_status_block_data_e1x));
4072                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4073                 sb_data_e1x.common.p_func.vf_id = 0xff;
4074                 sb_data_e1x.common.p_func.vf_valid = false;
4075                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4076                 sb_data_e1x.common.same_igu_sb_1b = true;
4077                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4078                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4079                 hc_sm_p = sb_data_e1x.common.state_machine;
4080                 hc_index_p = sb_data_e1x.index_data;
4081                 sb_data_p = (u32 *)&sb_data_e1x;
4082                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4083         }
4084
4085         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4086                                        igu_sb_id, igu_seg_id);
4087         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4088                                        igu_sb_id, igu_seg_id);
4089
4090         DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4091
4092         /* write indecies to HW */
4093         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4094 }
4095
4096 static void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u16 fw_sb_id,
4097                                         u8 sb_index, u8 disable, u16 usec)
4098 {
4099         int port = BP_PORT(bp);
4100         u8 ticks = usec / BNX2X_BTR;
4101
4102         storm_memset_hc_timeout(bp, port, fw_sb_id, sb_index, ticks);
4103
4104         disable = disable ? 1 : (usec ? 0 : 1);
4105         storm_memset_hc_disable(bp, port, fw_sb_id, sb_index, disable);
4106 }
4107
4108 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u16 fw_sb_id,
4109                                      u16 tx_usec, u16 rx_usec)
4110 {
4111         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, U_SB_ETH_RX_CQ_INDEX,
4112                                     false, rx_usec);
4113         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, C_SB_ETH_TX_CQ_INDEX,
4114                                     false, tx_usec);
4115 }
4116
4117 static void bnx2x_init_def_sb(struct bnx2x *bp)
4118 {
4119         struct host_sp_status_block *def_sb = bp->def_status_blk;
4120         dma_addr_t mapping = bp->def_status_blk_mapping;
4121         int igu_sp_sb_index;
4122         int igu_seg_id;
4123         int port = BP_PORT(bp);
4124         int func = BP_FUNC(bp);
4125         int reg_offset;
4126         u64 section;
4127         int index;
4128         struct hc_sp_status_block_data sp_sb_data;
4129         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4130
4131         if (CHIP_INT_MODE_IS_BC(bp)) {
4132                 igu_sp_sb_index = DEF_SB_IGU_ID;
4133                 igu_seg_id = HC_SEG_ACCESS_DEF;
4134         } else {
4135                 igu_sp_sb_index = bp->igu_dsb_id;
4136                 igu_seg_id = IGU_SEG_ACCESS_DEF;
4137         }
4138
4139         /* ATTN */
4140         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4141                                             atten_status_block);
4142         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
4143
4144         bp->attn_state = 0;
4145
4146         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4147                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4148         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4149                 int sindex;
4150                 /* take care of sig[0]..sig[4] */
4151                 for (sindex = 0; sindex < 4; sindex++)
4152                         bp->attn_group[index].sig[sindex] =
4153                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
4154
4155                 if (CHIP_IS_E2(bp))
4156                         /*
4157                          * enable5 is separate from the rest of the registers,
4158                          * and therefore the address skip is 4
4159                          * and not 16 between the different groups
4160                          */
4161                         bp->attn_group[index].sig[4] = REG_RD(bp,
4162                                         reg_offset + 0x10 + 0x4*index);
4163                 else
4164                         bp->attn_group[index].sig[4] = 0;
4165         }
4166
4167         if (bp->common.int_block == INT_BLOCK_HC) {
4168                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4169                                      HC_REG_ATTN_MSG0_ADDR_L);
4170
4171                 REG_WR(bp, reg_offset, U64_LO(section));
4172                 REG_WR(bp, reg_offset + 4, U64_HI(section));
4173         } else if (CHIP_IS_E2(bp)) {
4174                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4175                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4176         }
4177
4178         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4179                                             sp_sb);
4180
4181         bnx2x_zero_sp_sb(bp);
4182
4183         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
4184         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
4185         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
4186         sp_sb_data.igu_seg_id           = igu_seg_id;
4187         sp_sb_data.p_func.pf_id         = func;
4188         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
4189         sp_sb_data.p_func.vf_id         = 0xff;
4190
4191         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4192
4193         bp->stats_pending = 0;
4194         bp->set_mac_pending = 0;
4195
4196         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
4197 }
4198
4199 void bnx2x_update_coalesce(struct bnx2x *bp)
4200 {
4201         int i;
4202
4203         for_each_eth_queue(bp, i)
4204                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
4205                                          bp->rx_ticks, bp->tx_ticks);
4206 }
4207
4208 static void bnx2x_init_sp_ring(struct bnx2x *bp)
4209 {
4210         spin_lock_init(&bp->spq_lock);
4211         atomic_set(&bp->spq_left, MAX_SPQ_PENDING);
4212
4213         bp->spq_prod_idx = 0;
4214         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4215         bp->spq_prod_bd = bp->spq;
4216         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
4217 }
4218
4219 static void bnx2x_init_eq_ring(struct bnx2x *bp)
4220 {
4221         int i;
4222         for (i = 1; i <= NUM_EQ_PAGES; i++) {
4223                 union event_ring_elem *elem =
4224                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
4225
4226                 elem->next_page.addr.hi =
4227                         cpu_to_le32(U64_HI(bp->eq_mapping +
4228                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
4229                 elem->next_page.addr.lo =
4230                         cpu_to_le32(U64_LO(bp->eq_mapping +
4231                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
4232         }
4233         bp->eq_cons = 0;
4234         bp->eq_prod = NUM_EQ_DESC;
4235         bp->eq_cons_sb = BNX2X_EQ_INDEX;
4236 }
4237
4238 static void bnx2x_init_ind_table(struct bnx2x *bp)
4239 {
4240         int func = BP_FUNC(bp);
4241         int i;
4242
4243         if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
4244                 return;
4245
4246         DP(NETIF_MSG_IFUP,
4247            "Initializing indirection table  multi_mode %d\n", bp->multi_mode);
4248         for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
4249                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4250                         TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
4251                         bp->fp->cl_id + (i % (bp->num_queues -
4252                                 NONE_ETH_CONTEXT_USE)));
4253 }
4254
4255 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4256 {
4257         int mode = bp->rx_mode;
4258         int port = BP_PORT(bp);
4259         u16 cl_id;
4260         u32 def_q_filters = 0;
4261
4262         /* All but management unicast packets should pass to the host as well */
4263         u32 llh_mask =
4264                 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST |
4265                 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST |
4266                 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN |
4267                 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN;
4268
4269         switch (mode) {
4270         case BNX2X_RX_MODE_NONE: /* no Rx */
4271                 def_q_filters = BNX2X_ACCEPT_NONE;
4272 #ifdef BCM_CNIC
4273                 if (!NO_FCOE(bp)) {
4274                         cl_id = bnx2x_fcoe(bp, cl_id);
4275                         bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_NONE);
4276                 }
4277 #endif
4278                 break;
4279
4280         case BNX2X_RX_MODE_NORMAL:
4281                 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
4282                                 BNX2X_ACCEPT_MULTICAST;
4283 #ifdef BCM_CNIC
4284                 cl_id = bnx2x_fcoe(bp, cl_id);
4285                 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_UNICAST |
4286                                           BNX2X_ACCEPT_MULTICAST);
4287 #endif
4288                 break;
4289
4290         case BNX2X_RX_MODE_ALLMULTI:
4291                 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
4292                                 BNX2X_ACCEPT_ALL_MULTICAST;
4293 #ifdef BCM_CNIC
4294                 cl_id = bnx2x_fcoe(bp, cl_id);
4295                 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_UNICAST |
4296                                           BNX2X_ACCEPT_MULTICAST);
4297 #endif
4298                 break;
4299
4300         case BNX2X_RX_MODE_PROMISC:
4301                 def_q_filters |= BNX2X_PROMISCUOUS_MODE;
4302 #ifdef BCM_CNIC
4303                 cl_id = bnx2x_fcoe(bp, cl_id);
4304                 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_UNICAST |
4305                                           BNX2X_ACCEPT_MULTICAST);
4306 #endif
4307                 /* pass management unicast packets as well */
4308                 llh_mask |= NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST;
4309                 break;
4310
4311         default:
4312                 BNX2X_ERR("BAD rx mode (%d)\n", mode);
4313                 break;
4314         }
4315
4316         cl_id = BP_L_ID(bp);
4317         bnx2x_rxq_set_mac_filters(bp, cl_id, def_q_filters);
4318
4319         REG_WR(bp,
4320                (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
4321                        NIG_REG_LLH0_BRB1_DRV_MASK), llh_mask);
4322
4323         DP(NETIF_MSG_IFUP, "rx mode %d\n"
4324                 "drop_ucast 0x%x\ndrop_mcast 0x%x\ndrop_bcast 0x%x\n"
4325                 "accp_ucast 0x%x\naccp_mcast 0x%x\naccp_bcast 0x%x\n"
4326                 "unmatched_ucast 0x%x\n", mode,
4327                 bp->mac_filters.ucast_drop_all,
4328                 bp->mac_filters.mcast_drop_all,
4329                 bp->mac_filters.bcast_drop_all,
4330                 bp->mac_filters.ucast_accept_all,
4331                 bp->mac_filters.mcast_accept_all,
4332                 bp->mac_filters.bcast_accept_all,
4333                 bp->mac_filters.unmatched_unicast
4334         );
4335
4336         storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
4337 }
4338
4339 static void bnx2x_init_internal_common(struct bnx2x *bp)
4340 {
4341         int i;
4342
4343         if (!CHIP_IS_E1(bp)) {
4344
4345                 /* xstorm needs to know whether to add  ovlan to packets or not,
4346                  * in switch-independent we'll write 0 to here... */
4347                 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
4348                         bp->mf_mode);
4349                 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
4350                         bp->mf_mode);
4351                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
4352                         bp->mf_mode);
4353                 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
4354                         bp->mf_mode);
4355         }
4356
4357         if (IS_MF_SI(bp))
4358                 /*
4359                  * In switch independent mode, the TSTORM needs to accept
4360                  * packets that failed classification, since approximate match
4361                  * mac addresses aren't written to NIG LLH
4362                  */
4363                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4364                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
4365
4366         /* Zero this manually as its initialization is
4367            currently missing in the initTool */
4368         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
4369                 REG_WR(bp, BAR_USTRORM_INTMEM +
4370                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
4371         if (CHIP_IS_E2(bp)) {
4372                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
4373                         CHIP_INT_MODE_IS_BC(bp) ?
4374                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
4375         }
4376 }
4377
4378 static void bnx2x_init_internal_port(struct bnx2x *bp)
4379 {
4380         /* port */
4381         bnx2x_dcb_init_intmem_pfc(bp);
4382 }
4383
4384 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
4385 {
4386         switch (load_code) {
4387         case FW_MSG_CODE_DRV_LOAD_COMMON:
4388         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
4389                 bnx2x_init_internal_common(bp);
4390                 /* no break */
4391
4392         case FW_MSG_CODE_DRV_LOAD_PORT:
4393                 bnx2x_init_internal_port(bp);
4394                 /* no break */
4395
4396         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
4397                 /* internal memory per function is
4398                    initialized inside bnx2x_pf_init */
4399                 break;
4400
4401         default:
4402                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
4403                 break;
4404         }
4405 }
4406
4407 static void bnx2x_init_fp_sb(struct bnx2x *bp, int fp_idx)
4408 {
4409         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
4410
4411         fp->state = BNX2X_FP_STATE_CLOSED;
4412
4413         fp->index = fp->cid = fp_idx;
4414         fp->cl_id = BP_L_ID(bp) + fp_idx;
4415         fp->fw_sb_id = bp->base_fw_ndsb + fp->cl_id + CNIC_CONTEXT_USE;
4416         fp->igu_sb_id = bp->igu_base_sb + fp_idx + CNIC_CONTEXT_USE;
4417         /* qZone id equals to FW (per path) client id */
4418         fp->cl_qzone_id  = fp->cl_id +
4419                            BP_PORT(bp)*(CHIP_IS_E2(bp) ? ETH_MAX_RX_CLIENTS_E2 :
4420                                 ETH_MAX_RX_CLIENTS_E1H);
4421         /* init shortcut */
4422         fp->ustorm_rx_prods_offset = CHIP_IS_E2(bp) ?
4423                             USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id) :
4424                             USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
4425         /* Setup SB indicies */
4426         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
4427         fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
4428
4429         DP(NETIF_MSG_IFUP, "queue[%d]:  bnx2x_init_sb(%p,%p)  "
4430                                    "cl_id %d  fw_sb %d  igu_sb %d\n",
4431                    fp_idx, bp, fp->status_blk.e1x_sb, fp->cl_id, fp->fw_sb_id,
4432                    fp->igu_sb_id);
4433         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
4434                       fp->fw_sb_id, fp->igu_sb_id);
4435
4436         bnx2x_update_fpsb_idx(fp);
4437 }
4438
4439 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
4440 {
4441         int i;
4442
4443         for_each_eth_queue(bp, i)
4444                 bnx2x_init_fp_sb(bp, i);
4445 #ifdef BCM_CNIC
4446         if (!NO_FCOE(bp))
4447                 bnx2x_init_fcoe_fp(bp);
4448
4449         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
4450                       BNX2X_VF_ID_INVALID, false,
4451                       CNIC_SB_ID(bp), CNIC_IGU_SB_ID(bp));
4452
4453 #endif
4454
4455         /* ensure status block indices were read */
4456         rmb();
4457
4458         bnx2x_init_def_sb(bp);
4459         bnx2x_update_dsb_idx(bp);
4460         bnx2x_init_rx_rings(bp);
4461         bnx2x_init_tx_rings(bp);
4462         bnx2x_init_sp_ring(bp);
4463         bnx2x_init_eq_ring(bp);
4464         bnx2x_init_internal(bp, load_code);
4465         bnx2x_pf_init(bp);
4466         bnx2x_init_ind_table(bp);
4467         bnx2x_stats_init(bp);
4468
4469         /* At this point, we are ready for interrupts */
4470         atomic_set(&bp->intr_sem, 0);
4471
4472         /* flush all before enabling interrupts */
4473         mb();
4474         mmiowb();
4475
4476         bnx2x_int_enable(bp);
4477
4478         /* Check for SPIO5 */
4479         bnx2x_attn_int_deasserted0(bp,
4480                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
4481                                    AEU_INPUTS_ATTN_BITS_SPIO5);
4482 }
4483
4484 /* end of nic init */
4485
4486 /*
4487  * gzip service functions
4488  */
4489
4490 static int bnx2x_gunzip_init(struct bnx2x *bp)
4491 {
4492         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
4493                                             &bp->gunzip_mapping, GFP_KERNEL);
4494         if (bp->gunzip_buf  == NULL)
4495                 goto gunzip_nomem1;
4496
4497         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
4498         if (bp->strm  == NULL)
4499                 goto gunzip_nomem2;
4500
4501         bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
4502                                       GFP_KERNEL);
4503         if (bp->strm->workspace == NULL)
4504                 goto gunzip_nomem3;
4505
4506         return 0;
4507
4508 gunzip_nomem3:
4509         kfree(bp->strm);
4510         bp->strm = NULL;
4511
4512 gunzip_nomem2:
4513         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4514                           bp->gunzip_mapping);
4515         bp->gunzip_buf = NULL;
4516
4517 gunzip_nomem1:
4518         netdev_err(bp->dev, "Cannot allocate firmware buffer for"
4519                " un-compression\n");
4520         return -ENOMEM;
4521 }
4522
4523 static void bnx2x_gunzip_end(struct bnx2x *bp)
4524 {
4525         kfree(bp->strm->workspace);
4526         kfree(bp->strm);
4527         bp->strm = NULL;
4528
4529         if (bp->gunzip_buf) {
4530                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4531                                   bp->gunzip_mapping);
4532                 bp->gunzip_buf = NULL;
4533         }
4534 }
4535
4536 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
4537 {
4538         int n, rc;
4539
4540         /* check gzip header */
4541         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
4542                 BNX2X_ERR("Bad gzip header\n");
4543                 return -EINVAL;
4544         }
4545
4546         n = 10;
4547
4548 #define FNAME                           0x8
4549
4550         if (zbuf[3] & FNAME)
4551                 while ((zbuf[n++] != 0) && (n < len));
4552
4553         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
4554         bp->strm->avail_in = len - n;
4555         bp->strm->next_out = bp->gunzip_buf;
4556         bp->strm->avail_out = FW_BUF_SIZE;
4557
4558         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
4559         if (rc != Z_OK)
4560                 return rc;
4561
4562         rc = zlib_inflate(bp->strm, Z_FINISH);
4563         if ((rc != Z_OK) && (rc != Z_STREAM_END))
4564                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
4565                            bp->strm->msg);
4566
4567         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
4568         if (bp->gunzip_outlen & 0x3)
4569                 netdev_err(bp->dev, "Firmware decompression error:"
4570                                     " gunzip_outlen (%d) not aligned\n",
4571                                 bp->gunzip_outlen);
4572         bp->gunzip_outlen >>= 2;
4573
4574         zlib_inflateEnd(bp->strm);
4575
4576         if (rc == Z_STREAM_END)
4577                 return 0;
4578
4579         return rc;
4580 }
4581
4582 /* nic load/unload */
4583
4584 /*
4585  * General service functions
4586  */
4587
4588 /* send a NIG loopback debug packet */
4589 static void bnx2x_lb_pckt(struct bnx2x *bp)
4590 {
4591         u32 wb_write[3];
4592
4593         /* Ethernet source and destination addresses */
4594         wb_write[0] = 0x55555555;
4595         wb_write[1] = 0x55555555;
4596         wb_write[2] = 0x20;             /* SOP */
4597         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4598
4599         /* NON-IP protocol */
4600         wb_write[0] = 0x09000000;
4601         wb_write[1] = 0x55555555;
4602         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
4603         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4604 }
4605
4606 /* some of the internal memories
4607  * are not directly readable from the driver
4608  * to test them we send debug packets
4609  */
4610 static int bnx2x_int_mem_test(struct bnx2x *bp)
4611 {
4612         int factor;
4613         int count, i;
4614         u32 val = 0;
4615
4616         if (CHIP_REV_IS_FPGA(bp))
4617                 factor = 120;
4618         else if (CHIP_REV_IS_EMUL(bp))
4619                 factor = 200;
4620         else
4621                 factor = 1;
4622
4623         /* Disable inputs of parser neighbor blocks */
4624         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4625         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4626         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4627         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
4628
4629         /*  Write 0 to parser credits for CFC search request */
4630         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4631
4632         /* send Ethernet packet */
4633         bnx2x_lb_pckt(bp);
4634
4635         /* TODO do i reset NIG statistic? */
4636         /* Wait until NIG register shows 1 packet of size 0x10 */
4637         count = 1000 * factor;
4638         while (count) {
4639
4640                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4641                 val = *bnx2x_sp(bp, wb_data[0]);
4642                 if (val == 0x10)
4643                         break;
4644
4645                 msleep(10);
4646                 count--;
4647         }
4648         if (val != 0x10) {
4649                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
4650                 return -1;
4651         }
4652
4653         /* Wait until PRS register shows 1 packet */
4654         count = 1000 * factor;
4655         while (count) {
4656                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4657                 if (val == 1)
4658                         break;
4659
4660                 msleep(10);
4661                 count--;
4662         }
4663         if (val != 0x1) {
4664                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4665                 return -2;
4666         }
4667
4668         /* Reset and init BRB, PRS */
4669         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
4670         msleep(50);
4671         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
4672         msleep(50);
4673         bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
4674         bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
4675
4676         DP(NETIF_MSG_HW, "part2\n");
4677
4678         /* Disable inputs of parser neighbor blocks */
4679         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4680         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4681         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4682         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
4683
4684         /* Write 0 to parser credits for CFC search request */
4685         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4686
4687         /* send 10 Ethernet packets */
4688         for (i = 0; i < 10; i++)
4689                 bnx2x_lb_pckt(bp);
4690
4691         /* Wait until NIG register shows 10 + 1
4692            packets of size 11*0x10 = 0xb0 */
4693         count = 1000 * factor;
4694         while (count) {
4695
4696                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4697                 val = *bnx2x_sp(bp, wb_data[0]);
4698                 if (val == 0xb0)
4699                         break;
4700
4701                 msleep(10);
4702                 count--;
4703         }
4704         if (val != 0xb0) {
4705                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
4706                 return -3;
4707         }
4708
4709         /* Wait until PRS register shows 2 packets */
4710         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4711         if (val != 2)
4712                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
4713
4714         /* Write 1 to parser credits for CFC search request */
4715         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
4716
4717         /* Wait until PRS register shows 3 packets */
4718         msleep(10 * factor);
4719         /* Wait until NIG register shows 1 packet of size 0x10 */
4720         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4721         if (val != 3)
4722                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
4723
4724         /* clear NIG EOP FIFO */
4725         for (i = 0; i < 11; i++)
4726                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
4727         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
4728         if (val != 1) {
4729                 BNX2X_ERR("clear of NIG failed\n");
4730                 return -4;
4731         }
4732
4733         /* Reset and init BRB, PRS, NIG */
4734         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
4735         msleep(50);
4736         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
4737         msleep(50);
4738         bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
4739         bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
4740 #ifndef BCM_CNIC
4741         /* set NIC mode */
4742         REG_WR(bp, PRS_REG_NIC_MODE, 1);
4743 #endif
4744
4745         /* Enable inputs of parser neighbor blocks */
4746         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
4747         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
4748         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
4749         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
4750
4751         DP(NETIF_MSG_HW, "done\n");
4752
4753         return 0; /* OK */
4754 }
4755
4756 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
4757 {
4758         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
4759         if (CHIP_IS_E2(bp))
4760                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
4761         else
4762                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
4763         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
4764         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
4765         /*
4766          * mask read length error interrupts in brb for parser
4767          * (parsing unit and 'checksum and crc' unit)
4768          * these errors are legal (PU reads fixed length and CAC can cause
4769          * read length error on truncated packets)
4770          */
4771         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
4772         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
4773         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
4774         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
4775         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
4776         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
4777 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
4778 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
4779         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
4780         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
4781         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
4782 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
4783 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
4784         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
4785         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
4786         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
4787         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
4788 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
4789 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
4790
4791         if (CHIP_REV_IS_FPGA(bp))
4792                 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
4793         else if (CHIP_IS_E2(bp))
4794                 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
4795                            (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
4796                                 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
4797                                 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
4798                                 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
4799                                 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
4800         else
4801                 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
4802         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
4803         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
4804         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
4805 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
4806 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
4807         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
4808         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
4809 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4810         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
4811 }
4812
4813 static void bnx2x_reset_common(struct bnx2x *bp)
4814 {
4815         /* reset_common */
4816         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
4817                0xd3ffff7f);
4818         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
4819 }
4820
4821 static void bnx2x_init_pxp(struct bnx2x *bp)
4822 {
4823         u16 devctl;
4824         int r_order, w_order;
4825
4826         pci_read_config_word(bp->pdev,
4827                              bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
4828         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
4829         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4830         if (bp->mrrs == -1)
4831                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4832         else {
4833                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
4834                 r_order = bp->mrrs;
4835         }
4836
4837         bnx2x_init_pxp_arb(bp, r_order, w_order);
4838 }
4839
4840 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
4841 {
4842         int is_required;
4843         u32 val;
4844         int port;
4845
4846         if (BP_NOMCP(bp))
4847                 return;
4848
4849         is_required = 0;
4850         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
4851               SHARED_HW_CFG_FAN_FAILURE_MASK;
4852
4853         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
4854                 is_required = 1;
4855
4856         /*
4857          * The fan failure mechanism is usually related to the PHY type since
4858          * the power consumption of the board is affected by the PHY. Currently,
4859          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
4860          */
4861         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
4862                 for (port = PORT_0; port < PORT_MAX; port++) {
4863                         is_required |=
4864                                 bnx2x_fan_failure_det_req(
4865                                         bp,
4866                                         bp->common.shmem_base,
4867                                         bp->common.shmem2_base,
4868                                         port);
4869                 }
4870
4871         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
4872
4873         if (is_required == 0)
4874                 return;
4875
4876         /* Fan failure is indicated by SPIO 5 */
4877         bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
4878                        MISC_REGISTERS_SPIO_INPUT_HI_Z);
4879
4880         /* set to active low mode */
4881         val = REG_RD(bp, MISC_REG_SPIO_INT);
4882         val |= ((1 << MISC_REGISTERS_SPIO_5) <<
4883                                         MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
4884         REG_WR(bp, MISC_REG_SPIO_INT, val);
4885
4886         /* enable interrupt to signal the IGU */
4887         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
4888         val |= (1 << MISC_REGISTERS_SPIO_5);
4889         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
4890 }
4891
4892 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
4893 {
4894         u32 offset = 0;
4895
4896         if (CHIP_IS_E1(bp))
4897                 return;
4898         if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
4899                 return;
4900
4901         switch (BP_ABS_FUNC(bp)) {
4902         case 0:
4903                 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
4904                 break;
4905         case 1:
4906                 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
4907                 break;
4908         case 2:
4909                 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
4910                 break;
4911         case 3:
4912                 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
4913                 break;
4914         case 4:
4915                 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
4916                 break;
4917         case 5:
4918                 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
4919                 break;
4920         case 6:
4921                 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
4922                 break;
4923         case 7:
4924                 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
4925                 break;
4926         default:
4927                 return;
4928         }
4929
4930         REG_WR(bp, offset, pretend_func_num);
4931         REG_RD(bp, offset);
4932         DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
4933 }
4934
4935 static void bnx2x_pf_disable(struct bnx2x *bp)
4936 {
4937         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
4938         val &= ~IGU_PF_CONF_FUNC_EN;
4939
4940         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
4941         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
4942         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
4943 }
4944
4945 static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code)
4946 {
4947         u32 val, i;
4948
4949         DP(BNX2X_MSG_MCP, "starting common init  func %d\n", BP_ABS_FUNC(bp));
4950
4951         bnx2x_reset_common(bp);
4952         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
4953         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
4954
4955         bnx2x_init_block(bp, MISC_BLOCK, COMMON_STAGE);
4956         if (!CHIP_IS_E1(bp))
4957                 REG_WR(bp, MISC_REG_E1HMF_MODE, IS_MF(bp));
4958
4959         if (CHIP_IS_E2(bp)) {
4960                 u8 fid;
4961
4962                 /**
4963                  * 4-port mode or 2-port mode we need to turn of master-enable
4964                  * for everyone, after that, turn it back on for self.
4965                  * so, we disregard multi-function or not, and always disable
4966                  * for all functions on the given path, this means 0,2,4,6 for
4967                  * path 0 and 1,3,5,7 for path 1
4968                  */
4969                 for (fid = BP_PATH(bp); fid  < E2_FUNC_MAX*2; fid += 2) {
4970                         if (fid == BP_ABS_FUNC(bp)) {
4971                                 REG_WR(bp,
4972                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
4973                                     1);
4974                                 continue;
4975                         }
4976
4977                         bnx2x_pretend_func(bp, fid);
4978                         /* clear pf enable */
4979                         bnx2x_pf_disable(bp);
4980                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
4981                 }
4982         }
4983
4984         bnx2x_init_block(bp, PXP_BLOCK, COMMON_STAGE);
4985         if (CHIP_IS_E1(bp)) {
4986                 /* enable HW interrupt from PXP on USDM overflow
4987                    bit 16 on INT_MASK_0 */
4988                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
4989         }
4990
4991         bnx2x_init_block(bp, PXP2_BLOCK, COMMON_STAGE);
4992         bnx2x_init_pxp(bp);
4993
4994 #ifdef __BIG_ENDIAN
4995         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
4996         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
4997         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
4998         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
4999         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5000         /* make sure this value is 0 */
5001         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
5002
5003 /*      REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5004         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5005         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5006         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5007         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5008 #endif
5009
5010         bnx2x_ilt_init_page_size(bp, INITOP_SET);
5011
5012         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5013                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5014
5015         /* let the HW do it's magic ... */
5016         msleep(100);
5017         /* finish PXP init */
5018         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5019         if (val != 1) {
5020                 BNX2X_ERR("PXP2 CFG failed\n");
5021                 return -EBUSY;
5022         }
5023         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5024         if (val != 1) {
5025                 BNX2X_ERR("PXP2 RD_INIT failed\n");
5026                 return -EBUSY;
5027         }
5028
5029         /* Timers bug workaround E2 only. We need to set the entire ILT to
5030          * have entries with value "0" and valid bit on.
5031          * This needs to be done by the first PF that is loaded in a path
5032          * (i.e. common phase)
5033          */
5034         if (CHIP_IS_E2(bp)) {
5035                 struct ilt_client_info ilt_cli;
5036                 struct bnx2x_ilt ilt;
5037                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5038                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5039
5040                 /* initialize dummy TM client */
5041                 ilt_cli.start = 0;
5042                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5043                 ilt_cli.client_num = ILT_CLIENT_TM;
5044
5045                 /* Step 1: set zeroes to all ilt page entries with valid bit on
5046                  * Step 2: set the timers first/last ilt entry to point
5047                  * to the entire range to prevent ILT range error for 3rd/4th
5048                  * vnic (this code assumes existance of the vnic)
5049                  *
5050                  * both steps performed by call to bnx2x_ilt_client_init_op()
5051                  * with dummy TM client
5052                  *
5053                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
5054                  * and his brother are split registers
5055                  */
5056                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
5057                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
5058                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5059
5060                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
5061                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
5062                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
5063         }
5064
5065
5066         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5067         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
5068
5069         if (CHIP_IS_E2(bp)) {
5070                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
5071                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
5072                 bnx2x_init_block(bp, PGLUE_B_BLOCK, COMMON_STAGE);
5073
5074                 bnx2x_init_block(bp, ATC_BLOCK, COMMON_STAGE);
5075
5076                 /* let the HW do it's magic ... */
5077                 do {
5078                         msleep(200);
5079                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
5080                 } while (factor-- && (val != 1));
5081
5082                 if (val != 1) {
5083                         BNX2X_ERR("ATC_INIT failed\n");
5084                         return -EBUSY;
5085                 }
5086         }
5087
5088         bnx2x_init_block(bp, DMAE_BLOCK, COMMON_STAGE);
5089
5090         /* clean the DMAE memory */
5091         bp->dmae_ready = 1;
5092         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
5093
5094         bnx2x_init_block(bp, TCM_BLOCK, COMMON_STAGE);
5095         bnx2x_init_block(bp, UCM_BLOCK, COMMON_STAGE);
5096         bnx2x_init_block(bp, CCM_BLOCK, COMMON_STAGE);
5097         bnx2x_init_block(bp, XCM_BLOCK, COMMON_STAGE);
5098
5099         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5100         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5101         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5102         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5103
5104         bnx2x_init_block(bp, QM_BLOCK, COMMON_STAGE);
5105
5106         if (CHIP_MODE_IS_4_PORT(bp))
5107                 bnx2x_init_block(bp, QM_4PORT_BLOCK, COMMON_STAGE);
5108
5109         /* QM queues pointers table */
5110         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
5111
5112         /* soft reset pulse */
5113         REG_WR(bp, QM_REG_SOFT_RESET, 1);
5114         REG_WR(bp, QM_REG_SOFT_RESET, 0);
5115
5116 #ifdef BCM_CNIC
5117         bnx2x_init_block(bp, TIMERS_BLOCK, COMMON_STAGE);
5118 #endif
5119
5120         bnx2x_init_block(bp, DQ_BLOCK, COMMON_STAGE);
5121         REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
5122
5123         if (!CHIP_REV_IS_SLOW(bp)) {
5124                 /* enable hw interrupt from doorbell Q */
5125                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5126         }
5127
5128         bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
5129         if (CHIP_MODE_IS_4_PORT(bp)) {
5130                 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD, 248);
5131                 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD, 328);
5132         }
5133
5134         bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
5135         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
5136 #ifndef BCM_CNIC
5137         /* set NIC mode */
5138         REG_WR(bp, PRS_REG_NIC_MODE, 1);
5139 #endif
5140         if (!CHIP_IS_E1(bp))
5141                 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_MF_SD(bp));
5142
5143         if (CHIP_IS_E2(bp)) {
5144                 /* Bit-map indicating which L2 hdrs may appear after the
5145                    basic Ethernet header */
5146                 int has_ovlan = IS_MF_SD(bp);
5147                 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5148                 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5149         }
5150
5151         bnx2x_init_block(bp, TSDM_BLOCK, COMMON_STAGE);
5152         bnx2x_init_block(bp, CSDM_BLOCK, COMMON_STAGE);
5153         bnx2x_init_block(bp, USDM_BLOCK, COMMON_STAGE);
5154         bnx2x_init_block(bp, XSDM_BLOCK, COMMON_STAGE);
5155
5156         bnx2x_init_fill(bp, TSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5157         bnx2x_init_fill(bp, USEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5158         bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5159         bnx2x_init_fill(bp, XSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5160
5161         bnx2x_init_block(bp, TSEM_BLOCK, COMMON_STAGE);
5162         bnx2x_init_block(bp, USEM_BLOCK, COMMON_STAGE);
5163         bnx2x_init_block(bp, CSEM_BLOCK, COMMON_STAGE);
5164         bnx2x_init_block(bp, XSEM_BLOCK, COMMON_STAGE);
5165
5166         if (CHIP_MODE_IS_4_PORT(bp))
5167                 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, COMMON_STAGE);
5168
5169         /* sync semi rtc */
5170         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5171                0x80000000);
5172         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
5173                0x80000000);
5174
5175         bnx2x_init_block(bp, UPB_BLOCK, COMMON_STAGE);
5176         bnx2x_init_block(bp, XPB_BLOCK, COMMON_STAGE);
5177         bnx2x_init_block(bp, PBF_BLOCK, COMMON_STAGE);
5178
5179         if (CHIP_IS_E2(bp)) {
5180                 int has_ovlan = IS_MF_SD(bp);
5181                 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5182                 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5183         }
5184
5185         REG_WR(bp, SRC_REG_SOFT_RST, 1);
5186         for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4)
5187                 REG_WR(bp, i, random32());
5188
5189         bnx2x_init_block(bp, SRCH_BLOCK, COMMON_STAGE);
5190 #ifdef BCM_CNIC
5191         REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
5192         REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
5193         REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
5194         REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
5195         REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
5196         REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
5197         REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
5198         REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
5199         REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
5200         REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
5201 #endif
5202         REG_WR(bp, SRC_REG_SOFT_RST, 0);
5203
5204         if (sizeof(union cdu_context) != 1024)
5205                 /* we currently assume that a context is 1024 bytes */
5206                 dev_alert(&bp->pdev->dev, "please adjust the size "
5207                                           "of cdu_context(%ld)\n",
5208                          (long)sizeof(union cdu_context));
5209
5210         bnx2x_init_block(bp, CDU_BLOCK, COMMON_STAGE);
5211         val = (4 << 24) + (0 << 12) + 1024;
5212         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
5213
5214         bnx2x_init_block(bp, CFC_BLOCK, COMMON_STAGE);
5215         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
5216         /* enable context validation interrupt from CFC */
5217         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5218
5219         /* set the thresholds to prevent CFC/CDU race */
5220         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
5221
5222         bnx2x_init_block(bp, HC_BLOCK, COMMON_STAGE);
5223
5224         if (CHIP_IS_E2(bp) && BP_NOMCP(bp))
5225                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
5226
5227         bnx2x_init_block(bp, IGU_BLOCK, COMMON_STAGE);
5228         bnx2x_init_block(bp, MISC_AEU_BLOCK, COMMON_STAGE);
5229
5230         bnx2x_init_block(bp, PXPCS_BLOCK, COMMON_STAGE);
5231         /* Reset PCIE errors for debug */
5232         REG_WR(bp, 0x2814, 0xffffffff);
5233         REG_WR(bp, 0x3820, 0xffffffff);
5234
5235         if (CHIP_IS_E2(bp)) {
5236                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
5237                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
5238                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
5239                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
5240                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
5241                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
5242                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
5243                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
5244                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
5245                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
5246                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
5247         }
5248
5249         bnx2x_init_block(bp, EMAC0_BLOCK, COMMON_STAGE);
5250         bnx2x_init_block(bp, EMAC1_BLOCK, COMMON_STAGE);
5251         bnx2x_init_block(bp, DBU_BLOCK, COMMON_STAGE);
5252         bnx2x_init_block(bp, DBG_BLOCK, COMMON_STAGE);
5253
5254         bnx2x_init_block(bp, NIG_BLOCK, COMMON_STAGE);
5255         if (!CHIP_IS_E1(bp)) {
5256                 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
5257                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
5258         }
5259         if (CHIP_IS_E2(bp)) {
5260                 /* Bit-map indicating which L2 hdrs may appear after the
5261                    basic Ethernet header */
5262                 REG_WR(bp, NIG_REG_P0_HDRS_AFTER_BASIC, (IS_MF_SD(bp) ? 7 : 6));
5263         }
5264
5265         if (CHIP_REV_IS_SLOW(bp))
5266                 msleep(200);
5267
5268         /* finish CFC init */
5269         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
5270         if (val != 1) {
5271                 BNX2X_ERR("CFC LL_INIT failed\n");
5272                 return -EBUSY;
5273         }
5274         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
5275         if (val != 1) {
5276                 BNX2X_ERR("CFC AC_INIT failed\n");
5277                 return -EBUSY;
5278         }
5279         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
5280         if (val != 1) {
5281                 BNX2X_ERR("CFC CAM_INIT failed\n");
5282                 return -EBUSY;
5283         }
5284         REG_WR(bp, CFC_REG_DEBUG0, 0);
5285
5286         if (CHIP_IS_E1(bp)) {
5287                 /* read NIG statistic
5288                    to see if this is our first up since powerup */
5289                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5290                 val = *bnx2x_sp(bp, wb_data[0]);
5291
5292                 /* do internal memory self test */
5293                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
5294                         BNX2X_ERR("internal mem self test failed\n");
5295                         return -EBUSY;
5296                 }
5297         }
5298
5299         bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
5300                                                        bp->common.shmem_base,
5301                                                        bp->common.shmem2_base);
5302
5303         bnx2x_setup_fan_failure_detection(bp);
5304
5305         /* clear PXP2 attentions */
5306         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
5307
5308         bnx2x_enable_blocks_attention(bp);
5309         if (CHIP_PARITY_ENABLED(bp))
5310                 bnx2x_enable_blocks_parity(bp);
5311
5312         if (!BP_NOMCP(bp)) {
5313                 /* In E2 2-PORT mode, same ext phy is used for the two paths */
5314                 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
5315                     CHIP_IS_E1x(bp)) {
5316                         u32 shmem_base[2], shmem2_base[2];
5317                         shmem_base[0] =  bp->common.shmem_base;
5318                         shmem2_base[0] = bp->common.shmem2_base;
5319                         if (CHIP_IS_E2(bp)) {
5320                                 shmem_base[1] =
5321                                         SHMEM2_RD(bp, other_shmem_base_addr);
5322                                 shmem2_base[1] =
5323                                         SHMEM2_RD(bp, other_shmem2_base_addr);
5324                         }
5325                         bnx2x_acquire_phy_lock(bp);
5326                         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5327                                               bp->common.chip_id);
5328                         bnx2x_release_phy_lock(bp);
5329                 }
5330         } else
5331                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
5332
5333         return 0;
5334 }
5335
5336 static int bnx2x_init_hw_port(struct bnx2x *bp)
5337 {
5338         int port = BP_PORT(bp);
5339         int init_stage = port ? PORT1_STAGE : PORT0_STAGE;
5340         u32 low, high;
5341         u32 val;
5342
5343         DP(BNX2X_MSG_MCP, "starting port init  port %d\n", port);
5344
5345         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
5346
5347         bnx2x_init_block(bp, PXP_BLOCK, init_stage);
5348         bnx2x_init_block(bp, PXP2_BLOCK, init_stage);
5349
5350         /* Timers bug workaround: disables the pf_master bit in pglue at
5351          * common phase, we need to enable it here before any dmae access are
5352          * attempted. Therefore we manually added the enable-master to the
5353          * port phase (it also happens in the function phase)
5354          */
5355         if (CHIP_IS_E2(bp))
5356                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5357
5358         bnx2x_init_block(bp, TCM_BLOCK, init_stage);
5359         bnx2x_init_block(bp, UCM_BLOCK, init_stage);
5360         bnx2x_init_block(bp, CCM_BLOCK, init_stage);
5361         bnx2x_init_block(bp, XCM_BLOCK, init_stage);
5362
5363         /* QM cid (connection) count */
5364         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
5365
5366 #ifdef BCM_CNIC
5367         bnx2x_init_block(bp, TIMERS_BLOCK, init_stage);
5368         REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
5369         REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
5370 #endif
5371
5372         bnx2x_init_block(bp, DQ_BLOCK, init_stage);
5373
5374         if (CHIP_MODE_IS_4_PORT(bp))
5375                 bnx2x_init_block(bp, QM_4PORT_BLOCK, init_stage);
5376
5377         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
5378                 bnx2x_init_block(bp, BRB1_BLOCK, init_stage);
5379                 if (CHIP_REV_IS_SLOW(bp) && CHIP_IS_E1(bp)) {
5380                         /* no pause for emulation and FPGA */
5381                         low = 0;
5382                         high = 513;
5383                 } else {
5384                         if (IS_MF(bp))
5385                                 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
5386                         else if (bp->dev->mtu > 4096) {
5387                                 if (bp->flags & ONE_PORT_FLAG)
5388                                         low = 160;
5389                                 else {
5390                                         val = bp->dev->mtu;
5391                                         /* (24*1024 + val*4)/256 */
5392                                         low = 96 + (val/64) +
5393                                                         ((val % 64) ? 1 : 0);
5394                                 }
5395                         } else
5396                                 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
5397                         high = low + 56;        /* 14*1024/256 */
5398                 }
5399                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
5400                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
5401         }
5402
5403         if (CHIP_MODE_IS_4_PORT(bp)) {
5404                 REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 + port*8, 248);
5405                 REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 + port*8, 328);
5406                 REG_WR(bp, (BP_PORT(bp) ? BRB1_REG_MAC_GUARANTIED_1 :
5407                                           BRB1_REG_MAC_GUARANTIED_0), 40);
5408         }
5409
5410         bnx2x_init_block(bp, PRS_BLOCK, init_stage);
5411
5412         bnx2x_init_block(bp, TSDM_BLOCK, init_stage);
5413         bnx2x_init_block(bp, CSDM_BLOCK, init_stage);
5414         bnx2x_init_block(bp, USDM_BLOCK, init_stage);
5415         bnx2x_init_block(bp, XSDM_BLOCK, init_stage);
5416
5417         bnx2x_init_block(bp, TSEM_BLOCK, init_stage);
5418         bnx2x_init_block(bp, USEM_BLOCK, init_stage);
5419         bnx2x_init_block(bp, CSEM_BLOCK, init_stage);
5420         bnx2x_init_block(bp, XSEM_BLOCK, init_stage);
5421         if (CHIP_MODE_IS_4_PORT(bp))
5422                 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, init_stage);
5423
5424         bnx2x_init_block(bp, UPB_BLOCK, init_stage);
5425         bnx2x_init_block(bp, XPB_BLOCK, init_stage);
5426
5427         bnx2x_init_block(bp, PBF_BLOCK, init_stage);
5428
5429         if (!CHIP_IS_E2(bp)) {
5430                 /* configure PBF to work without PAUSE mtu 9000 */
5431                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
5432
5433                 /* update threshold */
5434                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
5435                 /* update init credit */
5436                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
5437
5438                 /* probe changes */
5439                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
5440                 udelay(50);
5441                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
5442         }
5443
5444 #ifdef BCM_CNIC
5445         bnx2x_init_block(bp, SRCH_BLOCK, init_stage);
5446 #endif
5447         bnx2x_init_block(bp, CDU_BLOCK, init_stage);
5448         bnx2x_init_block(bp, CFC_BLOCK, init_stage);
5449
5450         if (CHIP_IS_E1(bp)) {
5451                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5452                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5453         }
5454         bnx2x_init_block(bp, HC_BLOCK, init_stage);
5455
5456         bnx2x_init_block(bp, IGU_BLOCK, init_stage);
5457
5458         bnx2x_init_block(bp, MISC_AEU_BLOCK, init_stage);
5459         /* init aeu_mask_attn_func_0/1:
5460          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
5461          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
5462          *             bits 4-7 are used for "per vn group attention" */
5463         val = IS_MF(bp) ? 0xF7 : 0x7;
5464         /* Enable DCBX attention for all but E1 */
5465         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
5466         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
5467
5468         bnx2x_init_block(bp, PXPCS_BLOCK, init_stage);
5469         bnx2x_init_block(bp, EMAC0_BLOCK, init_stage);
5470         bnx2x_init_block(bp, EMAC1_BLOCK, init_stage);
5471         bnx2x_init_block(bp, DBU_BLOCK, init_stage);
5472         bnx2x_init_block(bp, DBG_BLOCK, init_stage);
5473
5474         bnx2x_init_block(bp, NIG_BLOCK, init_stage);
5475
5476         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
5477
5478         if (!CHIP_IS_E1(bp)) {
5479                 /* 0x2 disable mf_ov, 0x1 enable */
5480                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
5481                        (IS_MF_SD(bp) ? 0x1 : 0x2));
5482
5483                 if (CHIP_IS_E2(bp)) {
5484                         val = 0;
5485                         switch (bp->mf_mode) {
5486                         case MULTI_FUNCTION_SD:
5487                                 val = 1;
5488                                 break;
5489                         case MULTI_FUNCTION_SI:
5490                                 val = 2;
5491                                 break;
5492                         }
5493
5494                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
5495                                                   NIG_REG_LLH0_CLS_TYPE), val);
5496                 }
5497                 {
5498                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
5499                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
5500                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
5501                 }
5502         }
5503
5504         bnx2x_init_block(bp, MCP_BLOCK, init_stage);
5505         bnx2x_init_block(bp, DMAE_BLOCK, init_stage);
5506         bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
5507                                                        bp->common.shmem_base,
5508                                                        bp->common.shmem2_base);
5509         if (bnx2x_fan_failure_det_req(bp, bp->common.shmem_base,
5510                                       bp->common.shmem2_base, port)) {
5511                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5512                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5513                 val = REG_RD(bp, reg_addr);
5514                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
5515                 REG_WR(bp, reg_addr, val);
5516         }
5517         bnx2x__link_reset(bp);
5518
5519         return 0;
5520 }
5521
5522 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
5523 {
5524         int reg;
5525
5526         if (CHIP_IS_E1(bp))
5527                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
5528         else
5529                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
5530
5531         bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
5532 }
5533
5534 static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
5535 {
5536         bnx2x_igu_clear_sb_gen(bp, idu_sb_id, true /*PF*/);
5537 }
5538
5539 static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
5540 {
5541         u32 i, base = FUNC_ILT_BASE(func);
5542         for (i = base; i < base + ILT_PER_FUNC; i++)
5543                 bnx2x_ilt_wr(bp, i, 0);
5544 }
5545
5546 static int bnx2x_init_hw_func(struct bnx2x *bp)
5547 {
5548         int port = BP_PORT(bp);
5549         int func = BP_FUNC(bp);
5550         struct bnx2x_ilt *ilt = BP_ILT(bp);
5551         u16 cdu_ilt_start;
5552         u32 addr, val;
5553         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
5554         int i, main_mem_width;
5555
5556         DP(BNX2X_MSG_MCP, "starting func init  func %d\n", func);
5557
5558         /* set MSI reconfigure capability */
5559         if (bp->common.int_block == INT_BLOCK_HC) {
5560                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
5561                 val = REG_RD(bp, addr);
5562                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
5563                 REG_WR(bp, addr, val);
5564         }
5565
5566         ilt = BP_ILT(bp);
5567         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
5568
5569         for (i = 0; i < L2_ILT_LINES(bp); i++) {
5570                 ilt->lines[cdu_ilt_start + i].page =
5571                         bp->context.vcxt + (ILT_PAGE_CIDS * i);
5572                 ilt->lines[cdu_ilt_start + i].page_mapping =
5573                         bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
5574                 /* cdu ilt pages are allocated manually so there's no need to
5575                 set the size */
5576         }
5577         bnx2x_ilt_init_op(bp, INITOP_SET);
5578
5579 #ifdef BCM_CNIC
5580         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
5581
5582         /* T1 hash bits value determines the T1 number of entries */
5583         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
5584 #endif
5585
5586 #ifndef BCM_CNIC
5587         /* set NIC mode */
5588         REG_WR(bp, PRS_REG_NIC_MODE, 1);
5589 #endif  /* BCM_CNIC */
5590
5591         if (CHIP_IS_E2(bp)) {
5592                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
5593
5594                 /* Turn on a single ISR mode in IGU if driver is going to use
5595                  * INT#x or MSI
5596                  */
5597                 if (!(bp->flags & USING_MSIX_FLAG))
5598                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
5599                 /*
5600                  * Timers workaround bug: function init part.
5601                  * Need to wait 20msec after initializing ILT,
5602                  * needed to make sure there are no requests in
5603                  * one of the PXP internal queues with "old" ILT addresses
5604                  */
5605                 msleep(20);
5606                 /*
5607                  * Master enable - Due to WB DMAE writes performed before this
5608                  * register is re-initialized as part of the regular function
5609                  * init
5610                  */
5611                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5612                 /* Enable the function in IGU */
5613                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
5614         }
5615
5616         bp->dmae_ready = 1;
5617
5618         bnx2x_init_block(bp, PGLUE_B_BLOCK, FUNC0_STAGE + func);
5619
5620         if (CHIP_IS_E2(bp))
5621                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
5622
5623         bnx2x_init_block(bp, MISC_BLOCK, FUNC0_STAGE + func);
5624         bnx2x_init_block(bp, TCM_BLOCK, FUNC0_STAGE + func);
5625         bnx2x_init_block(bp, UCM_BLOCK, FUNC0_STAGE + func);
5626         bnx2x_init_block(bp, CCM_BLOCK, FUNC0_STAGE + func);
5627         bnx2x_init_block(bp, XCM_BLOCK, FUNC0_STAGE + func);
5628         bnx2x_init_block(bp, TSEM_BLOCK, FUNC0_STAGE + func);
5629         bnx2x_init_block(bp, USEM_BLOCK, FUNC0_STAGE + func);
5630         bnx2x_init_block(bp, CSEM_BLOCK, FUNC0_STAGE + func);
5631         bnx2x_init_block(bp, XSEM_BLOCK, FUNC0_STAGE + func);
5632
5633         if (CHIP_IS_E2(bp)) {
5634                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_PATH_ID_OFFSET,
5635                                                                 BP_PATH(bp));
5636                 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_PATH_ID_OFFSET,
5637                                                                 BP_PATH(bp));
5638         }
5639
5640         if (CHIP_MODE_IS_4_PORT(bp))
5641                 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, FUNC0_STAGE + func);
5642
5643         if (CHIP_IS_E2(bp))
5644                 REG_WR(bp, QM_REG_PF_EN, 1);
5645
5646         bnx2x_init_block(bp, QM_BLOCK, FUNC0_STAGE + func);
5647
5648         if (CHIP_MODE_IS_4_PORT(bp))
5649                 bnx2x_init_block(bp, QM_4PORT_BLOCK, FUNC0_STAGE + func);
5650
5651         bnx2x_init_block(bp, TIMERS_BLOCK, FUNC0_STAGE + func);
5652         bnx2x_init_block(bp, DQ_BLOCK, FUNC0_STAGE + func);
5653         bnx2x_init_block(bp, BRB1_BLOCK, FUNC0_STAGE + func);
5654         bnx2x_init_block(bp, PRS_BLOCK, FUNC0_STAGE + func);
5655         bnx2x_init_block(bp, TSDM_BLOCK, FUNC0_STAGE + func);
5656         bnx2x_init_block(bp, CSDM_BLOCK, FUNC0_STAGE + func);
5657         bnx2x_init_block(bp, USDM_BLOCK, FUNC0_STAGE + func);
5658         bnx2x_init_block(bp, XSDM_BLOCK, FUNC0_STAGE + func);
5659         bnx2x_init_block(bp, UPB_BLOCK, FUNC0_STAGE + func);
5660         bnx2x_init_block(bp, XPB_BLOCK, FUNC0_STAGE + func);
5661         bnx2x_init_block(bp, PBF_BLOCK, FUNC0_STAGE + func);
5662         if (CHIP_IS_E2(bp))
5663                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
5664
5665         bnx2x_init_block(bp, CDU_BLOCK, FUNC0_STAGE + func);
5666
5667         bnx2x_init_block(bp, CFC_BLOCK, FUNC0_STAGE + func);
5668
5669         if (CHIP_IS_E2(bp))
5670                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
5671
5672         if (IS_MF(bp)) {
5673                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
5674                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
5675         }
5676
5677         bnx2x_init_block(bp, MISC_AEU_BLOCK, FUNC0_STAGE + func);
5678
5679         /* HC init per function */
5680         if (bp->common.int_block == INT_BLOCK_HC) {
5681                 if (CHIP_IS_E1H(bp)) {
5682                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5683
5684                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5685                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5686                 }
5687                 bnx2x_init_block(bp, HC_BLOCK, FUNC0_STAGE + func);
5688
5689         } else {
5690                 int num_segs, sb_idx, prod_offset;
5691
5692                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5693
5694                 if (CHIP_IS_E2(bp)) {
5695                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
5696                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
5697                 }
5698
5699                 bnx2x_init_block(bp, IGU_BLOCK, FUNC0_STAGE + func);
5700
5701                 if (CHIP_IS_E2(bp)) {
5702                         int dsb_idx = 0;
5703                         /**
5704                          * Producer memory:
5705                          * E2 mode: address 0-135 match to the mapping memory;
5706                          * 136 - PF0 default prod; 137 - PF1 default prod;
5707                          * 138 - PF2 default prod; 139 - PF3 default prod;
5708                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
5709                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
5710                          * 144-147 reserved.
5711                          *
5712                          * E1.5 mode - In backward compatible mode;
5713                          * for non default SB; each even line in the memory
5714                          * holds the U producer and each odd line hold
5715                          * the C producer. The first 128 producers are for
5716                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
5717                          * producers are for the DSB for each PF.
5718                          * Each PF has five segments: (the order inside each
5719                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
5720                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
5721                          * 144-147 attn prods;
5722                          */
5723                         /* non-default-status-blocks */
5724                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5725                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
5726                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
5727                                 prod_offset = (bp->igu_base_sb + sb_idx) *
5728                                         num_segs;
5729
5730                                 for (i = 0; i < num_segs; i++) {
5731                                         addr = IGU_REG_PROD_CONS_MEMORY +
5732                                                         (prod_offset + i) * 4;
5733                                         REG_WR(bp, addr, 0);
5734                                 }
5735                                 /* send consumer update with value 0 */
5736                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
5737                                              USTORM_ID, 0, IGU_INT_NOP, 1);
5738                                 bnx2x_igu_clear_sb(bp,
5739                                                    bp->igu_base_sb + sb_idx);
5740                         }
5741
5742                         /* default-status-blocks */
5743                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5744                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
5745
5746                         if (CHIP_MODE_IS_4_PORT(bp))
5747                                 dsb_idx = BP_FUNC(bp);
5748                         else
5749                                 dsb_idx = BP_E1HVN(bp);
5750
5751                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
5752                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
5753                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
5754
5755                         for (i = 0; i < (num_segs * E1HVN_MAX);
5756                              i += E1HVN_MAX) {
5757                                 addr = IGU_REG_PROD_CONS_MEMORY +
5758                                                         (prod_offset + i)*4;
5759                                 REG_WR(bp, addr, 0);
5760                         }
5761                         /* send consumer update with 0 */
5762                         if (CHIP_INT_MODE_IS_BC(bp)) {
5763                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5764                                              USTORM_ID, 0, IGU_INT_NOP, 1);
5765                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5766                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
5767                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5768                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
5769                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5770                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
5771                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5772                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
5773                         } else {
5774                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5775                                              USTORM_ID, 0, IGU_INT_NOP, 1);
5776                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5777                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
5778                         }
5779                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
5780
5781                         /* !!! these should become driver const once
5782                            rf-tool supports split-68 const */
5783                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
5784                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
5785                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
5786                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
5787                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
5788                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
5789                 }
5790         }
5791
5792         /* Reset PCIE errors for debug */
5793         REG_WR(bp, 0x2114, 0xffffffff);
5794         REG_WR(bp, 0x2120, 0xffffffff);
5795
5796         bnx2x_init_block(bp, EMAC0_BLOCK, FUNC0_STAGE + func);
5797         bnx2x_init_block(bp, EMAC1_BLOCK, FUNC0_STAGE + func);
5798         bnx2x_init_block(bp, DBU_BLOCK, FUNC0_STAGE + func);
5799         bnx2x_init_block(bp, DBG_BLOCK, FUNC0_STAGE + func);
5800         bnx2x_init_block(bp, MCP_BLOCK, FUNC0_STAGE + func);
5801         bnx2x_init_block(bp, DMAE_BLOCK, FUNC0_STAGE + func);
5802
5803         if (CHIP_IS_E1x(bp)) {
5804                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
5805                 main_mem_base = HC_REG_MAIN_MEMORY +
5806                                 BP_PORT(bp) * (main_mem_size * 4);
5807                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
5808                 main_mem_width = 8;
5809
5810                 val = REG_RD(bp, main_mem_prty_clr);
5811                 if (val)
5812                         DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
5813                                           "block during "
5814                                           "function init (0x%x)!\n", val);
5815
5816                 /* Clear "false" parity errors in MSI-X table */
5817                 for (i = main_mem_base;
5818                      i < main_mem_base + main_mem_size * 4;
5819                      i += main_mem_width) {
5820                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
5821                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
5822                                          i, main_mem_width / 4);
5823                 }
5824                 /* Clear HC parity attention */
5825                 REG_RD(bp, main_mem_prty_clr);
5826         }
5827
5828         bnx2x_phy_probe(&bp->link_params);
5829
5830         return 0;
5831 }
5832
5833 int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
5834 {
5835         int rc = 0;
5836
5837         DP(BNX2X_MSG_MCP, "function %d  load_code %x\n",
5838            BP_ABS_FUNC(bp), load_code);
5839
5840         bp->dmae_ready = 0;
5841         mutex_init(&bp->dmae_mutex);
5842         rc = bnx2x_gunzip_init(bp);
5843         if (rc)
5844                 return rc;
5845
5846         switch (load_code) {
5847         case FW_MSG_CODE_DRV_LOAD_COMMON:
5848         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5849                 rc = bnx2x_init_hw_common(bp, load_code);
5850                 if (rc)
5851                         goto init_hw_err;
5852                 /* no break */
5853
5854         case FW_MSG_CODE_DRV_LOAD_PORT:
5855                 rc = bnx2x_init_hw_port(bp);
5856                 if (rc)
5857                         goto init_hw_err;
5858                 /* no break */
5859
5860         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5861                 rc = bnx2x_init_hw_func(bp);
5862                 if (rc)
5863                         goto init_hw_err;
5864                 break;
5865
5866         default:
5867                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5868                 break;
5869         }
5870
5871         if (!BP_NOMCP(bp)) {
5872                 int mb_idx = BP_FW_MB_IDX(bp);
5873
5874                 bp->fw_drv_pulse_wr_seq =
5875                                 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
5876                                  DRV_PULSE_SEQ_MASK);
5877                 DP(BNX2X_MSG_MCP, "drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
5878         }
5879
5880 init_hw_err:
5881         bnx2x_gunzip_end(bp);
5882
5883         return rc;
5884 }
5885
5886 void bnx2x_free_mem(struct bnx2x *bp)
5887 {
5888
5889 #define BNX2X_PCI_FREE(x, y, size) \
5890         do { \
5891                 if (x) { \
5892                         dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \
5893                         x = NULL; \
5894                         y = 0; \
5895                 } \
5896         } while (0)
5897
5898 #define BNX2X_FREE(x) \
5899         do { \
5900                 if (x) { \
5901                         kfree((void *)x); \
5902                         x = NULL; \
5903                 } \
5904         } while (0)
5905
5906         int i;
5907
5908         /* fastpath */
5909         /* Common */
5910         for_each_queue(bp, i) {
5911 #ifdef BCM_CNIC
5912                 /* FCoE client uses default status block */
5913                 if (IS_FCOE_IDX(i)) {
5914                         union host_hc_status_block *sb =
5915                                 &bnx2x_fp(bp, i, status_blk);
5916                         memset(sb, 0, sizeof(union host_hc_status_block));
5917                         bnx2x_fp(bp, i, status_blk_mapping) = 0;
5918                 } else {
5919 #endif
5920                 /* status blocks */
5921                 if (CHIP_IS_E2(bp))
5922                         BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk.e2_sb),
5923                                        bnx2x_fp(bp, i, status_blk_mapping),
5924                                        sizeof(struct host_hc_status_block_e2));
5925                 else
5926                         BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk.e1x_sb),
5927                                        bnx2x_fp(bp, i, status_blk_mapping),
5928                                        sizeof(struct host_hc_status_block_e1x));
5929 #ifdef BCM_CNIC
5930                 }
5931 #endif
5932         }
5933         /* Rx */
5934         for_each_rx_queue(bp, i) {
5935
5936                 /* fastpath rx rings: rx_buf rx_desc rx_comp */
5937                 BNX2X_FREE(bnx2x_fp(bp, i, rx_buf_ring));
5938                 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_desc_ring),
5939                                bnx2x_fp(bp, i, rx_desc_mapping),
5940                                sizeof(struct eth_rx_bd) * NUM_RX_BD);
5941
5942                 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_comp_ring),
5943                                bnx2x_fp(bp, i, rx_comp_mapping),
5944                                sizeof(struct eth_fast_path_rx_cqe) *
5945                                NUM_RCQ_BD);
5946
5947                 /* SGE ring */
5948                 BNX2X_FREE(bnx2x_fp(bp, i, rx_page_ring));
5949                 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_sge_ring),
5950                                bnx2x_fp(bp, i, rx_sge_mapping),
5951                                BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
5952         }
5953         /* Tx */
5954         for_each_tx_queue(bp, i) {
5955
5956                 /* fastpath tx rings: tx_buf tx_desc */
5957                 BNX2X_FREE(bnx2x_fp(bp, i, tx_buf_ring));
5958                 BNX2X_PCI_FREE(bnx2x_fp(bp, i, tx_desc_ring),
5959                                bnx2x_fp(bp, i, tx_desc_mapping),
5960                                sizeof(union eth_tx_bd_types) * NUM_TX_BD);
5961         }
5962         /* end of fastpath */
5963
5964         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
5965                        sizeof(struct host_sp_status_block));
5966
5967         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
5968                        sizeof(struct bnx2x_slowpath));
5969
5970         BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
5971                        bp->context.size);
5972
5973         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
5974
5975         BNX2X_FREE(bp->ilt->lines);
5976
5977 #ifdef BCM_CNIC
5978         if (CHIP_IS_E2(bp))
5979                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
5980                                sizeof(struct host_hc_status_block_e2));
5981         else
5982                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
5983                                sizeof(struct host_hc_status_block_e1x));
5984
5985         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
5986 #endif
5987
5988         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
5989
5990         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
5991                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
5992
5993 #undef BNX2X_PCI_FREE
5994 #undef BNX2X_KFREE
5995 }
5996
5997 static inline void set_sb_shortcuts(struct bnx2x *bp, int index)
5998 {
5999         union host_hc_status_block status_blk = bnx2x_fp(bp, index, status_blk);
6000         if (CHIP_IS_E2(bp)) {
6001                 bnx2x_fp(bp, index, sb_index_values) =
6002                         (__le16 *)status_blk.e2_sb->sb.index_values;
6003                 bnx2x_fp(bp, index, sb_running_index) =
6004                         (__le16 *)status_blk.e2_sb->sb.running_index;
6005         } else {
6006                 bnx2x_fp(bp, index, sb_index_values) =
6007                         (__le16 *)status_blk.e1x_sb->sb.index_values;
6008                 bnx2x_fp(bp, index, sb_running_index) =
6009                         (__le16 *)status_blk.e1x_sb->sb.running_index;
6010         }
6011 }
6012
6013 int bnx2x_alloc_mem(struct bnx2x *bp)
6014 {
6015 #define BNX2X_PCI_ALLOC(x, y, size) \
6016         do { \
6017                 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
6018                 if (x == NULL) \
6019                         goto alloc_mem_err; \
6020                 memset(x, 0, size); \
6021         } while (0)
6022
6023 #define BNX2X_ALLOC(x, size) \
6024         do { \
6025                 x = kzalloc(size, GFP_KERNEL); \
6026                 if (x == NULL) \
6027                         goto alloc_mem_err; \
6028         } while (0)
6029
6030         int i;
6031
6032         /* fastpath */
6033         /* Common */
6034         for_each_queue(bp, i) {
6035                 union host_hc_status_block *sb = &bnx2x_fp(bp, i, status_blk);
6036                 bnx2x_fp(bp, i, bp) = bp;
6037                 /* status blocks */
6038 #ifdef BCM_CNIC
6039                 if (!IS_FCOE_IDX(i)) {
6040 #endif
6041                         if (CHIP_IS_E2(bp))
6042                                 BNX2X_PCI_ALLOC(sb->e2_sb,
6043                                     &bnx2x_fp(bp, i, status_blk_mapping),
6044                                     sizeof(struct host_hc_status_block_e2));
6045                         else
6046                                 BNX2X_PCI_ALLOC(sb->e1x_sb,
6047                                     &bnx2x_fp(bp, i, status_blk_mapping),
6048                                     sizeof(struct host_hc_status_block_e1x));
6049 #ifdef BCM_CNIC
6050                 }
6051 #endif
6052                 set_sb_shortcuts(bp, i);
6053         }
6054         /* Rx */
6055         for_each_queue(bp, i) {
6056
6057                 /* fastpath rx rings: rx_buf rx_desc rx_comp */
6058                 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_buf_ring),
6059                                 sizeof(struct sw_rx_bd) * NUM_RX_BD);
6060                 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_desc_ring),
6061                                 &bnx2x_fp(bp, i, rx_desc_mapping),
6062                                 sizeof(struct eth_rx_bd) * NUM_RX_BD);
6063
6064                 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_comp_ring),
6065                                 &bnx2x_fp(bp, i, rx_comp_mapping),
6066                                 sizeof(struct eth_fast_path_rx_cqe) *
6067                                 NUM_RCQ_BD);
6068
6069                 /* SGE ring */
6070                 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_page_ring),
6071                                 sizeof(struct sw_rx_page) * NUM_RX_SGE);
6072                 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_sge_ring),
6073                                 &bnx2x_fp(bp, i, rx_sge_mapping),
6074                                 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
6075         }
6076         /* Tx */
6077         for_each_queue(bp, i) {
6078
6079                 /* fastpath tx rings: tx_buf tx_desc */
6080                 BNX2X_ALLOC(bnx2x_fp(bp, i, tx_buf_ring),
6081                                 sizeof(struct sw_tx_bd) * NUM_TX_BD);
6082                 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, tx_desc_ring),
6083                                 &bnx2x_fp(bp, i, tx_desc_mapping),
6084                                 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
6085         }
6086         /* end of fastpath */
6087
6088 #ifdef BCM_CNIC
6089         if (CHIP_IS_E2(bp))
6090                 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
6091                                 sizeof(struct host_hc_status_block_e2));
6092         else
6093                 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
6094                                 sizeof(struct host_hc_status_block_e1x));
6095
6096         /* allocate searcher T2 table */
6097         BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
6098 #endif
6099
6100
6101         BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6102                         sizeof(struct host_sp_status_block));
6103
6104         BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6105                         sizeof(struct bnx2x_slowpath));
6106
6107         bp->context.size = sizeof(union cdu_context) * bp->l2_cid_count;
6108
6109         BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
6110                         bp->context.size);
6111
6112         BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
6113
6114         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
6115                 goto alloc_mem_err;
6116
6117         /* Slow path ring */
6118         BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
6119
6120         /* EQ */
6121         BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
6122                         BCM_PAGE_SIZE * NUM_EQ_PAGES);
6123         return 0;
6124
6125 alloc_mem_err:
6126         bnx2x_free_mem(bp);
6127         return -ENOMEM;
6128
6129 #undef BNX2X_PCI_ALLOC
6130 #undef BNX2X_ALLOC
6131 }
6132
6133 /*
6134  * Init service functions
6135  */
6136 static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6137                              int *state_p, int flags);
6138
6139 int bnx2x_func_start(struct bnx2x *bp)
6140 {
6141         bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0, 0, 0, 1);
6142
6143         /* Wait for completion */
6144         return bnx2x_wait_ramrod(bp, BNX2X_STATE_FUNC_STARTED, 0, &(bp->state),
6145                                  WAIT_RAMROD_COMMON);
6146 }
6147
6148 static int bnx2x_func_stop(struct bnx2x *bp)
6149 {
6150         bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 0, 0, 0, 1);
6151
6152         /* Wait for completion */
6153         return bnx2x_wait_ramrod(bp, BNX2X_STATE_CLOSING_WAIT4_UNLOAD,
6154                                       0, &(bp->state), WAIT_RAMROD_COMMON);
6155 }
6156
6157 /**
6158  * Sets a MAC in a CAM for a few L2 Clients for E1x chips
6159  *
6160  * @param bp driver descriptor
6161  * @param set set or clear an entry (1 or 0)
6162  * @param mac pointer to a buffer containing a MAC
6163  * @param cl_bit_vec bit vector of clients to register a MAC for
6164  * @param cam_offset offset in a CAM to use
6165  * @param is_bcast is the set MAC a broadcast address (for E1 only)
6166  */
6167 static void bnx2x_set_mac_addr_gen(struct bnx2x *bp, int set, const u8 *mac,
6168                                    u32 cl_bit_vec, u8 cam_offset,
6169                                    u8 is_bcast)
6170 {
6171         struct mac_configuration_cmd *config =
6172                 (struct mac_configuration_cmd *)bnx2x_sp(bp, mac_config);
6173         int ramrod_flags = WAIT_RAMROD_COMMON;
6174
6175         bp->set_mac_pending = 1;
6176         smp_wmb();
6177
6178         config->hdr.length = 1;
6179         config->hdr.offset = cam_offset;
6180         config->hdr.client_id = 0xff;
6181         config->hdr.reserved1 = 0;
6182
6183         /* primary MAC */
6184         config->config_table[0].msb_mac_addr =
6185                                         swab16(*(u16 *)&mac[0]);
6186         config->config_table[0].middle_mac_addr =
6187                                         swab16(*(u16 *)&mac[2]);
6188         config->config_table[0].lsb_mac_addr =
6189                                         swab16(*(u16 *)&mac[4]);
6190         config->config_table[0].clients_bit_vector =
6191                                         cpu_to_le32(cl_bit_vec);
6192         config->config_table[0].vlan_id = 0;
6193         config->config_table[0].pf_id = BP_FUNC(bp);
6194         if (set)
6195                 SET_FLAG(config->config_table[0].flags,
6196                         MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6197                         T_ETH_MAC_COMMAND_SET);
6198         else
6199                 SET_FLAG(config->config_table[0].flags,
6200                         MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6201                         T_ETH_MAC_COMMAND_INVALIDATE);
6202
6203         if (is_bcast)
6204                 SET_FLAG(config->config_table[0].flags,
6205                         MAC_CONFIGURATION_ENTRY_BROADCAST, 1);
6206
6207         DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x)  PF_ID %d  CLID mask %d\n",
6208            (set ? "setting" : "clearing"),
6209            config->config_table[0].msb_mac_addr,
6210            config->config_table[0].middle_mac_addr,
6211            config->config_table[0].lsb_mac_addr, BP_FUNC(bp), cl_bit_vec);
6212
6213         bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6214                       U64_HI(bnx2x_sp_mapping(bp, mac_config)),
6215                       U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
6216
6217         /* Wait for a completion */
6218         bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending, ramrod_flags);
6219 }
6220
6221 static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6222                              int *state_p, int flags)
6223 {
6224         /* can take a while if any port is running */
6225         int cnt = 5000;
6226         u8 poll = flags & WAIT_RAMROD_POLL;
6227         u8 common = flags & WAIT_RAMROD_COMMON;
6228
6229         DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n",
6230            poll ? "polling" : "waiting", state, idx);
6231
6232         might_sleep();
6233         while (cnt--) {
6234                 if (poll) {
6235                         if (common)
6236                                 bnx2x_eq_int(bp);
6237                         else {
6238                                 bnx2x_rx_int(bp->fp, 10);
6239                                 /* if index is different from 0
6240                                  * the reply for some commands will
6241                                  * be on the non default queue
6242                                  */
6243                                 if (idx)
6244                                         bnx2x_rx_int(&bp->fp[idx], 10);
6245                         }
6246                 }
6247
6248                 mb(); /* state is changed by bnx2x_sp_event() */
6249                 if (*state_p == state) {
6250 #ifdef BNX2X_STOP_ON_ERROR
6251                         DP(NETIF_MSG_IFUP, "exit  (cnt %d)\n", 5000 - cnt);
6252 #endif
6253                         return 0;
6254                 }
6255
6256                 msleep(1);
6257
6258                 if (bp->panic)
6259                         return -EIO;
6260         }
6261
6262         /* timeout! */
6263         BNX2X_ERR("timeout %s for state %x on IDX [%d]\n",
6264                   poll ? "polling" : "waiting", state, idx);
6265 #ifdef BNX2X_STOP_ON_ERROR
6266         bnx2x_panic();
6267 #endif
6268
6269         return -EBUSY;
6270 }
6271
6272 static u8 bnx2x_e1h_cam_offset(struct bnx2x *bp, u8 rel_offset)
6273 {
6274         if (CHIP_IS_E1H(bp))
6275                 return E1H_FUNC_MAX * rel_offset + BP_FUNC(bp);
6276         else if (CHIP_MODE_IS_4_PORT(bp))
6277                 return BP_FUNC(bp) * 32  + rel_offset;
6278         else
6279                 return BP_VN(bp) * 32  + rel_offset;
6280 }
6281
6282 /**
6283  *  LLH CAM line allocations: currently only iSCSI and ETH macs are
6284  *  relevant. In addition, current implementation is tuned for a
6285  *  single ETH MAC.
6286  *
6287  *  When multiple unicast ETH MACs PF configuration in switch
6288  *  independent mode is required (NetQ, multiple netdev MACs,
6289  *  etc.), consider better utilisation of 16 per function MAC
6290  *  entries in the LLH memory.
6291  */
6292 enum {
6293         LLH_CAM_ISCSI_ETH_LINE = 0,
6294         LLH_CAM_ETH_LINE,
6295         LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE
6296 };
6297
6298 static void bnx2x_set_mac_in_nig(struct bnx2x *bp,
6299                           int set,
6300                           unsigned char *dev_addr,
6301                           int index)
6302 {
6303         u32 wb_data[2];
6304         u32 mem_offset, ena_offset, mem_index;
6305         /**
6306          * indexes mapping:
6307          * 0..7 - goes to MEM
6308          * 8..15 - goes to MEM2
6309          */
6310
6311         if (!IS_MF_SI(bp) || index > LLH_CAM_MAX_PF_LINE)
6312                 return;
6313
6314         /* calculate memory start offset according to the mapping
6315          * and index in the memory */
6316         if (index < NIG_LLH_FUNC_MEM_MAX_OFFSET) {
6317                 mem_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM :
6318                                            NIG_REG_LLH0_FUNC_MEM;
6319                 ena_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE :
6320                                            NIG_REG_LLH0_FUNC_MEM_ENABLE;
6321                 mem_index = index;
6322         } else {
6323                 mem_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2 :
6324                                            NIG_REG_P0_LLH_FUNC_MEM2;
6325                 ena_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2_ENABLE :
6326                                            NIG_REG_P0_LLH_FUNC_MEM2_ENABLE;
6327                 mem_index = index - NIG_LLH_FUNC_MEM_MAX_OFFSET;
6328         }
6329
6330         if (set) {
6331                 /* LLH_FUNC_MEM is a u64 WB register */
6332                 mem_offset += 8*mem_index;
6333
6334                 wb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) |
6335                               (dev_addr[4] <<  8) |  dev_addr[5]);
6336                 wb_data[1] = ((dev_addr[0] <<  8) |  dev_addr[1]);
6337
6338                 REG_WR_DMAE(bp, mem_offset, wb_data, 2);
6339         }
6340
6341         /* enable/disable the entry */
6342         REG_WR(bp, ena_offset + 4*mem_index, set);
6343
6344 }
6345
6346 void bnx2x_set_eth_mac(struct bnx2x *bp, int set)
6347 {
6348         u8 cam_offset = (CHIP_IS_E1(bp) ? (BP_PORT(bp) ? 32 : 0) :
6349                          bnx2x_e1h_cam_offset(bp, CAM_ETH_LINE));
6350
6351         /* networking  MAC */
6352         bnx2x_set_mac_addr_gen(bp, set, bp->dev->dev_addr,
6353                                (1 << bp->fp->cl_id), cam_offset , 0);
6354
6355         bnx2x_set_mac_in_nig(bp, set, bp->dev->dev_addr, LLH_CAM_ETH_LINE);
6356
6357         if (CHIP_IS_E1(bp)) {
6358                 /* broadcast MAC */
6359                 static const u8 bcast[ETH_ALEN] = {
6360                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff
6361                 };
6362                 bnx2x_set_mac_addr_gen(bp, set, bcast, 0, cam_offset + 1, 1);
6363         }
6364 }
6365 static void bnx2x_set_e1_mc_list(struct bnx2x *bp, u8 offset)
6366 {
6367         int i = 0, old;
6368         struct net_device *dev = bp->dev;
6369         struct netdev_hw_addr *ha;
6370         struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6371         dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6372
6373         netdev_for_each_mc_addr(ha, dev) {
6374                 /* copy mac */
6375                 config_cmd->config_table[i].msb_mac_addr =
6376                         swab16(*(u16 *)&bnx2x_mc_addr(ha)[0]);
6377                 config_cmd->config_table[i].middle_mac_addr =
6378                         swab16(*(u16 *)&bnx2x_mc_addr(ha)[2]);
6379                 config_cmd->config_table[i].lsb_mac_addr =
6380                         swab16(*(u16 *)&bnx2x_mc_addr(ha)[4]);
6381
6382                 config_cmd->config_table[i].vlan_id = 0;
6383                 config_cmd->config_table[i].pf_id = BP_FUNC(bp);
6384                 config_cmd->config_table[i].clients_bit_vector =
6385                         cpu_to_le32(1 << BP_L_ID(bp));
6386
6387                 SET_FLAG(config_cmd->config_table[i].flags,
6388                         MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6389                         T_ETH_MAC_COMMAND_SET);
6390
6391                 DP(NETIF_MSG_IFUP,
6392                    "setting MCAST[%d] (%04x:%04x:%04x)\n", i,
6393                    config_cmd->config_table[i].msb_mac_addr,
6394                    config_cmd->config_table[i].middle_mac_addr,
6395                    config_cmd->config_table[i].lsb_mac_addr);
6396                 i++;
6397         }
6398         old = config_cmd->hdr.length;
6399         if (old > i) {
6400                 for (; i < old; i++) {
6401                         if (CAM_IS_INVALID(config_cmd->
6402                                            config_table[i])) {
6403                                 /* already invalidated */
6404                                 break;
6405                         }
6406                         /* invalidate */
6407                         SET_FLAG(config_cmd->config_table[i].flags,
6408                                 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6409                                 T_ETH_MAC_COMMAND_INVALIDATE);
6410                 }
6411         }
6412
6413         config_cmd->hdr.length = i;
6414         config_cmd->hdr.offset = offset;
6415         config_cmd->hdr.client_id = 0xff;
6416         config_cmd->hdr.reserved1 = 0;
6417
6418         bp->set_mac_pending = 1;
6419         smp_wmb();
6420
6421         bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6422                    U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
6423 }
6424 static void bnx2x_invlidate_e1_mc_list(struct bnx2x *bp)
6425 {
6426         int i;
6427         struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6428         dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6429         int ramrod_flags = WAIT_RAMROD_COMMON;
6430
6431         bp->set_mac_pending = 1;
6432         smp_wmb();
6433
6434         for (i = 0; i < config_cmd->hdr.length; i++)
6435                 SET_FLAG(config_cmd->config_table[i].flags,
6436                         MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6437                         T_ETH_MAC_COMMAND_INVALIDATE);
6438
6439         bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6440                       U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
6441
6442         /* Wait for a completion */
6443         bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending,
6444                                 ramrod_flags);
6445
6446 }
6447
6448 #ifdef BCM_CNIC
6449 /**
6450  * Set iSCSI MAC(s) at the next enties in the CAM after the ETH
6451  * MAC(s). This function will wait until the ramdord completion
6452  * returns.
6453  *
6454  * @param bp driver handle
6455  * @param set set or clear the CAM entry
6456  *
6457  * @return 0 if cussess, -ENODEV if ramrod doesn't return.
6458  */
6459 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp, int set)
6460 {
6461         u8 cam_offset = (CHIP_IS_E1(bp) ? ((BP_PORT(bp) ? 32 : 0) + 2) :
6462                          bnx2x_e1h_cam_offset(bp, CAM_ISCSI_ETH_LINE));
6463         u32 iscsi_l2_cl_id = BNX2X_ISCSI_ETH_CL_ID +
6464                 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
6465         u32 cl_bit_vec = (1 << iscsi_l2_cl_id);
6466
6467         /* Send a SET_MAC ramrod */
6468         bnx2x_set_mac_addr_gen(bp, set, bp->iscsi_mac, cl_bit_vec,
6469                                cam_offset, 0);
6470
6471         bnx2x_set_mac_in_nig(bp, set, bp->iscsi_mac, LLH_CAM_ISCSI_ETH_LINE);
6472
6473         return 0;
6474 }
6475
6476 /**
6477  * Set FCoE L2 MAC(s) at the next enties in the CAM after the
6478  * ETH MAC(s). This function will wait until the ramdord
6479  * completion returns.
6480  *
6481  * @param bp driver handle
6482  * @param set set or clear the CAM entry
6483  *
6484  * @return 0 if cussess, -ENODEV if ramrod doesn't return.
6485  */
6486 int bnx2x_set_fip_eth_mac_addr(struct bnx2x *bp, int set)
6487 {
6488         u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
6489         /**
6490          * CAM allocation for E1H
6491          * eth unicasts: by func number
6492          * iscsi: by func number
6493          * fip unicast: by func number
6494          * fip multicast: by func number
6495          */
6496         bnx2x_set_mac_addr_gen(bp, set, bp->fip_mac,
6497                 cl_bit_vec, bnx2x_e1h_cam_offset(bp, CAM_FIP_ETH_LINE), 0);
6498
6499         return 0;
6500 }
6501
6502 int bnx2x_set_all_enode_macs(struct bnx2x *bp, int set)
6503 {
6504         u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
6505
6506         /**
6507          * CAM allocation for E1H
6508          * eth unicasts: by func number
6509          * iscsi: by func number
6510          * fip unicast: by func number
6511          * fip multicast: by func number
6512          */
6513         bnx2x_set_mac_addr_gen(bp, set, ALL_ENODE_MACS, cl_bit_vec,
6514                 bnx2x_e1h_cam_offset(bp, CAM_FIP_MCAST_LINE), 0);
6515
6516         return 0;
6517 }
6518 #endif
6519
6520 static void bnx2x_fill_cl_init_data(struct bnx2x *bp,
6521                                     struct bnx2x_client_init_params *params,
6522                                     u8 activate,
6523                                     struct client_init_ramrod_data *data)
6524 {
6525         /* Clear the buffer */
6526         memset(data, 0, sizeof(*data));
6527
6528         /* general */
6529         data->general.client_id = params->rxq_params.cl_id;
6530         data->general.statistics_counter_id = params->rxq_params.stat_id;
6531         data->general.statistics_en_flg =
6532                 (params->rxq_params.flags & QUEUE_FLG_STATS) ? 1 : 0;
6533         data->general.is_fcoe_flg =
6534                 (params->ramrod_params.flags & CLIENT_IS_FCOE) ? 1 : 0;
6535         data->general.activate_flg = activate;
6536         data->general.sp_client_id = params->rxq_params.spcl_id;
6537
6538         /* Rx data */
6539         data->rx.tpa_en_flg =
6540                 (params->rxq_params.flags & QUEUE_FLG_TPA) ? 1 : 0;
6541         data->rx.vmqueue_mode_en_flg = 0;
6542         data->rx.cache_line_alignment_log_size =
6543                 params->rxq_params.cache_line_log;
6544         data->rx.enable_dynamic_hc =
6545                 (params->rxq_params.flags & QUEUE_FLG_DHC) ? 1 : 0;
6546         data->rx.max_sges_for_packet = params->rxq_params.max_sges_pkt;
6547         data->rx.client_qzone_id = params->rxq_params.cl_qzone_id;
6548         data->rx.max_agg_size = params->rxq_params.tpa_agg_sz;
6549
6550         /* We don't set drop flags */
6551         data->rx.drop_ip_cs_err_flg = 0;
6552         data->rx.drop_tcp_cs_err_flg = 0;
6553         data->rx.drop_ttl0_flg = 0;
6554         data->rx.drop_udp_cs_err_flg = 0;
6555
6556         data->rx.inner_vlan_removal_enable_flg =
6557                 (params->rxq_params.flags & QUEUE_FLG_VLAN) ? 1 : 0;
6558         data->rx.outer_vlan_removal_enable_flg =
6559                 (params->rxq_params.flags & QUEUE_FLG_OV) ? 1 : 0;
6560         data->rx.status_block_id = params->rxq_params.fw_sb_id;
6561         data->rx.rx_sb_index_number = params->rxq_params.sb_cq_index;
6562         data->rx.bd_buff_size = cpu_to_le16(params->rxq_params.buf_sz);
6563         data->rx.sge_buff_size = cpu_to_le16(params->rxq_params.sge_buf_sz);
6564         data->rx.mtu = cpu_to_le16(params->rxq_params.mtu);
6565         data->rx.bd_page_base.lo =
6566                 cpu_to_le32(U64_LO(params->rxq_params.dscr_map));
6567         data->rx.bd_page_base.hi =
6568                 cpu_to_le32(U64_HI(params->rxq_params.dscr_map));
6569         data->rx.sge_page_base.lo =
6570                 cpu_to_le32(U64_LO(params->rxq_params.sge_map));
6571         data->rx.sge_page_base.hi =
6572                 cpu_to_le32(U64_HI(params->rxq_params.sge_map));
6573         data->rx.cqe_page_base.lo =
6574                 cpu_to_le32(U64_LO(params->rxq_params.rcq_map));
6575         data->rx.cqe_page_base.hi =
6576                 cpu_to_le32(U64_HI(params->rxq_params.rcq_map));
6577         data->rx.is_leading_rss =
6578                 (params->ramrod_params.flags & CLIENT_IS_LEADING_RSS) ? 1 : 0;
6579         data->rx.is_approx_mcast = data->rx.is_leading_rss;
6580
6581         /* Tx data */
6582         data->tx.enforce_security_flg = 0; /* VF specific */
6583         data->tx.tx_status_block_id = params->txq_params.fw_sb_id;
6584         data->tx.tx_sb_index_number = params->txq_params.sb_cq_index;
6585         data->tx.mtu = 0; /* VF specific */
6586         data->tx.tx_bd_page_base.lo =
6587                 cpu_to_le32(U64_LO(params->txq_params.dscr_map));
6588         data->tx.tx_bd_page_base.hi =
6589                 cpu_to_le32(U64_HI(params->txq_params.dscr_map));
6590
6591         /* flow control data */
6592         data->fc.cqe_pause_thr_low = cpu_to_le16(params->pause.rcq_th_lo);
6593         data->fc.cqe_pause_thr_high = cpu_to_le16(params->pause.rcq_th_hi);
6594         data->fc.bd_pause_thr_low = cpu_to_le16(params->pause.bd_th_lo);
6595         data->fc.bd_pause_thr_high = cpu_to_le16(params->pause.bd_th_hi);
6596         data->fc.sge_pause_thr_low = cpu_to_le16(params->pause.sge_th_lo);
6597         data->fc.sge_pause_thr_high = cpu_to_le16(params->pause.sge_th_hi);
6598         data->fc.rx_cos_mask = cpu_to_le16(params->pause.pri_map);
6599
6600         data->fc.safc_group_num = params->txq_params.cos;
6601         data->fc.safc_group_en_flg =
6602                 (params->txq_params.flags & QUEUE_FLG_COS) ? 1 : 0;
6603         data->fc.traffic_type =
6604                 (params->ramrod_params.flags & CLIENT_IS_FCOE) ?
6605                 LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW;
6606 }
6607
6608 static inline void bnx2x_set_ctx_validation(struct eth_context *cxt, u32 cid)
6609 {
6610         /* ustorm cxt validation */
6611         cxt->ustorm_ag_context.cdu_usage =
6612                 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_UCM_AG,
6613                                        ETH_CONNECTION_TYPE);
6614         /* xcontext validation */
6615         cxt->xstorm_ag_context.cdu_reserved =
6616                 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_XCM_AG,
6617                                        ETH_CONNECTION_TYPE);
6618 }
6619
6620 static int bnx2x_setup_fw_client(struct bnx2x *bp,
6621                                  struct bnx2x_client_init_params *params,
6622                                  u8 activate,
6623                                  struct client_init_ramrod_data *data,
6624                                  dma_addr_t data_mapping)
6625 {
6626         u16 hc_usec;
6627         int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;
6628         int ramrod_flags = 0, rc;
6629
6630         /* HC and context validation values */
6631         hc_usec = params->txq_params.hc_rate ?
6632                 1000000 / params->txq_params.hc_rate : 0;
6633         bnx2x_update_coalesce_sb_index(bp,
6634                         params->txq_params.fw_sb_id,
6635                         params->txq_params.sb_cq_index,
6636                         !(params->txq_params.flags & QUEUE_FLG_HC),
6637                         hc_usec);
6638
6639         *(params->ramrod_params.pstate) = BNX2X_FP_STATE_OPENING;
6640
6641         hc_usec = params->rxq_params.hc_rate ?
6642                 1000000 / params->rxq_params.hc_rate : 0;
6643         bnx2x_update_coalesce_sb_index(bp,
6644                         params->rxq_params.fw_sb_id,
6645                         params->rxq_params.sb_cq_index,
6646                         !(params->rxq_params.flags & QUEUE_FLG_HC),
6647                         hc_usec);
6648
6649         bnx2x_set_ctx_validation(params->rxq_params.cxt,
6650                                  params->rxq_params.cid);
6651
6652         /* zero stats */
6653         if (params->txq_params.flags & QUEUE_FLG_STATS)
6654                 storm_memset_xstats_zero(bp, BP_PORT(bp),
6655                                          params->txq_params.stat_id);
6656
6657         if (params->rxq_params.flags & QUEUE_FLG_STATS) {
6658                 storm_memset_ustats_zero(bp, BP_PORT(bp),
6659                                          params->rxq_params.stat_id);
6660                 storm_memset_tstats_zero(bp, BP_PORT(bp),
6661                                          params->rxq_params.stat_id);
6662         }
6663
6664         /* Fill the ramrod data */
6665         bnx2x_fill_cl_init_data(bp, params, activate, data);
6666
6667         /* SETUP ramrod.
6668          *
6669          * bnx2x_sp_post() takes a spin_lock thus no other explict memory
6670          * barrier except from mmiowb() is needed to impose a
6671          * proper ordering of memory operations.
6672          */
6673         mmiowb();
6674
6675
6676         bnx2x_sp_post(bp, ramrod, params->ramrod_params.cid,
6677                       U64_HI(data_mapping), U64_LO(data_mapping), 0);
6678
6679         /* Wait for completion */
6680         rc = bnx2x_wait_ramrod(bp, params->ramrod_params.state,
6681                                  params->ramrod_params.index,
6682                                  params->ramrod_params.pstate,
6683                                  ramrod_flags);
6684         return rc;
6685 }
6686
6687 /**
6688  * Configure interrupt mode according to current configuration.
6689  * In case of MSI-X it will also try to enable MSI-X.
6690  *
6691  * @param bp
6692  *
6693  * @return int
6694  */
6695 static int __devinit bnx2x_set_int_mode(struct bnx2x *bp)
6696 {
6697         int rc = 0;
6698
6699         switch (bp->int_mode) {
6700         case INT_MODE_MSI:
6701                 bnx2x_enable_msi(bp);
6702                 /* falling through... */
6703         case INT_MODE_INTx:
6704                 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
6705                 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
6706                 break;
6707         default:
6708                 /* Set number of queues according to bp->multi_mode value */
6709                 bnx2x_set_num_queues(bp);
6710
6711                 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
6712                    bp->num_queues);
6713
6714                 /* if we can't use MSI-X we only need one fp,
6715                  * so try to enable MSI-X with the requested number of fp's
6716                  * and fallback to MSI or legacy INTx with one fp
6717                  */
6718                 rc = bnx2x_enable_msix(bp);
6719                 if (rc) {
6720                         /* failed to enable MSI-X */
6721                         if (bp->multi_mode)
6722                                 DP(NETIF_MSG_IFUP,
6723                                           "Multi requested but failed to "
6724                                           "enable MSI-X (%d), "
6725                                           "set number of queues to %d\n",
6726                                    bp->num_queues,
6727                                    1 + NONE_ETH_CONTEXT_USE);
6728                         bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
6729
6730                         if (!(bp->flags & DISABLE_MSI_FLAG))
6731                                 bnx2x_enable_msi(bp);
6732                 }
6733
6734                 break;
6735         }
6736
6737         return rc;
6738 }
6739
6740 /* must be called prioir to any HW initializations */
6741 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
6742 {
6743         return L2_ILT_LINES(bp);
6744 }
6745
6746 void bnx2x_ilt_set_info(struct bnx2x *bp)
6747 {
6748         struct ilt_client_info *ilt_client;
6749         struct bnx2x_ilt *ilt = BP_ILT(bp);
6750         u16 line = 0;
6751
6752         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
6753         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
6754
6755         /* CDU */
6756         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
6757         ilt_client->client_num = ILT_CLIENT_CDU;
6758         ilt_client->page_size = CDU_ILT_PAGE_SZ;
6759         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
6760         ilt_client->start = line;
6761         line += L2_ILT_LINES(bp);
6762 #ifdef BCM_CNIC
6763         line += CNIC_ILT_LINES;
6764 #endif
6765         ilt_client->end = line - 1;
6766
6767         DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
6768                                          "flags 0x%x, hw psz %d\n",
6769            ilt_client->start,
6770            ilt_client->end,
6771            ilt_client->page_size,
6772            ilt_client->flags,
6773            ilog2(ilt_client->page_size >> 12));
6774
6775         /* QM */
6776         if (QM_INIT(bp->qm_cid_count)) {
6777                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
6778                 ilt_client->client_num = ILT_CLIENT_QM;
6779                 ilt_client->page_size = QM_ILT_PAGE_SZ;
6780                 ilt_client->flags = 0;
6781                 ilt_client->start = line;
6782
6783                 /* 4 bytes for each cid */
6784                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
6785                                                          QM_ILT_PAGE_SZ);
6786
6787                 ilt_client->end = line - 1;
6788
6789                 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
6790                                                  "flags 0x%x, hw psz %d\n",
6791                    ilt_client->start,
6792                    ilt_client->end,
6793                    ilt_client->page_size,
6794                    ilt_client->flags,
6795                    ilog2(ilt_client->page_size >> 12));
6796
6797         }
6798         /* SRC */
6799         ilt_client = &ilt->clients[ILT_CLIENT_SRC];
6800 #ifdef BCM_CNIC
6801         ilt_client->client_num = ILT_CLIENT_SRC;
6802         ilt_client->page_size = SRC_ILT_PAGE_SZ;
6803         ilt_client->flags = 0;
6804         ilt_client->start = line;
6805         line += SRC_ILT_LINES;
6806         ilt_client->end = line - 1;
6807
6808         DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
6809                                          "flags 0x%x, hw psz %d\n",
6810            ilt_client->start,
6811            ilt_client->end,
6812            ilt_client->page_size,
6813            ilt_client->flags,
6814            ilog2(ilt_client->page_size >> 12));
6815
6816 #else
6817         ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6818 #endif
6819
6820         /* TM */
6821         ilt_client = &ilt->clients[ILT_CLIENT_TM];
6822 #ifdef BCM_CNIC
6823         ilt_client->client_num = ILT_CLIENT_TM;
6824         ilt_client->page_size = TM_ILT_PAGE_SZ;
6825         ilt_client->flags = 0;
6826         ilt_client->start = line;
6827         line += TM_ILT_LINES;
6828         ilt_client->end = line - 1;
6829
6830         DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
6831                                          "flags 0x%x, hw psz %d\n",
6832            ilt_client->start,
6833            ilt_client->end,
6834            ilt_client->page_size,
6835            ilt_client->flags,
6836            ilog2(ilt_client->page_size >> 12));
6837
6838 #else
6839         ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6840 #endif
6841 }
6842
6843 int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6844                        int is_leading)
6845 {
6846         struct bnx2x_client_init_params params = { {0} };
6847         int rc;
6848
6849         /* reset IGU state skip FCoE L2 queue */
6850         if (!IS_FCOE_FP(fp))
6851                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
6852                              IGU_INT_ENABLE, 0);
6853
6854         params.ramrod_params.pstate = &fp->state;
6855         params.ramrod_params.state = BNX2X_FP_STATE_OPEN;
6856         params.ramrod_params.index = fp->index;
6857         params.ramrod_params.cid = fp->cid;
6858
6859 #ifdef BCM_CNIC
6860         if (IS_FCOE_FP(fp))
6861                 params.ramrod_params.flags |= CLIENT_IS_FCOE;
6862
6863 #endif
6864
6865         if (is_leading)
6866                 params.ramrod_params.flags |= CLIENT_IS_LEADING_RSS;
6867
6868         bnx2x_pf_rx_cl_prep(bp, fp, &params.pause, &params.rxq_params);
6869
6870         bnx2x_pf_tx_cl_prep(bp, fp, &params.txq_params);
6871
6872         rc = bnx2x_setup_fw_client(bp, &params, 1,
6873                                      bnx2x_sp(bp, client_init_data),
6874                                      bnx2x_sp_mapping(bp, client_init_data));
6875         return rc;
6876 }
6877
6878 static int bnx2x_stop_fw_client(struct bnx2x *bp,
6879                                 struct bnx2x_client_ramrod_params *p)
6880 {
6881         int rc;
6882
6883         int poll_flag = p->poll ? WAIT_RAMROD_POLL : 0;
6884
6885         /* halt the connection */
6886         *p->pstate = BNX2X_FP_STATE_HALTING;
6887         bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, p->cid, 0,
6888                                                   p->cl_id, 0);
6889
6890         /* Wait for completion */
6891         rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, p->index,
6892                                p->pstate, poll_flag);
6893         if (rc) /* timeout */
6894                 return rc;
6895
6896         *p->pstate = BNX2X_FP_STATE_TERMINATING;
6897         bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TERMINATE, p->cid, 0,
6898                                                        p->cl_id, 0);
6899         /* Wait for completion */
6900         rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_TERMINATED, p->index,
6901                                p->pstate, poll_flag);
6902         if (rc) /* timeout */
6903                 return rc;
6904
6905
6906         /* delete cfc entry */
6907         bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_CFC_DEL, p->cid, 0, 0, 1);
6908
6909         /* Wait for completion */
6910         rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_CLOSED, p->index,
6911                                p->pstate, WAIT_RAMROD_COMMON);
6912         return rc;
6913 }
6914
6915 static int bnx2x_stop_client(struct bnx2x *bp, int index)
6916 {
6917         struct bnx2x_client_ramrod_params client_stop = {0};
6918         struct bnx2x_fastpath *fp = &bp->fp[index];
6919
6920         client_stop.index = index;
6921         client_stop.cid = fp->cid;
6922         client_stop.cl_id = fp->cl_id;
6923         client_stop.pstate = &(fp->state);
6924         client_stop.poll = 0;
6925
6926         return bnx2x_stop_fw_client(bp, &client_stop);
6927 }
6928
6929
6930 static void bnx2x_reset_func(struct bnx2x *bp)
6931 {
6932         int port = BP_PORT(bp);
6933         int func = BP_FUNC(bp);
6934         int i;
6935         int pfunc_offset_fp = offsetof(struct hc_sb_data, p_func) +
6936                         (CHIP_IS_E2(bp) ?
6937                          offsetof(struct hc_status_block_data_e2, common) :
6938                          offsetof(struct hc_status_block_data_e1x, common));
6939         int pfunc_offset_sp = offsetof(struct hc_sp_status_block_data, p_func);
6940         int pfid_offset = offsetof(struct pci_entity, pf_id);
6941
6942         /* Disable the function in the FW */
6943         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
6944         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
6945         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
6946         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
6947
6948         /* FP SBs */
6949         for_each_eth_queue(bp, i) {
6950                 struct bnx2x_fastpath *fp = &bp->fp[i];
6951                 REG_WR8(bp,
6952                         BAR_CSTRORM_INTMEM +
6953                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id)
6954                         + pfunc_offset_fp + pfid_offset,
6955                         HC_FUNCTION_DISABLED);
6956         }
6957
6958         /* SP SB */
6959         REG_WR8(bp,
6960                 BAR_CSTRORM_INTMEM +
6961                 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
6962                 pfunc_offset_sp + pfid_offset,
6963                 HC_FUNCTION_DISABLED);
6964
6965
6966         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
6967                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
6968                        0);
6969
6970         /* Configure IGU */
6971         if (bp->common.int_block == INT_BLOCK_HC) {
6972                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6973                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6974         } else {
6975                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6976                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6977         }
6978
6979 #ifdef BCM_CNIC
6980         /* Disable Timer scan */
6981         REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
6982         /*
6983          * Wait for at least 10ms and up to 2 second for the timers scan to
6984          * complete
6985          */
6986         for (i = 0; i < 200; i++) {
6987                 msleep(10);
6988                 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
6989                         break;
6990         }
6991 #endif
6992         /* Clear ILT */
6993         bnx2x_clear_func_ilt(bp, func);
6994
6995         /* Timers workaround bug for E2: if this is vnic-3,
6996          * we need to set the entire ilt range for this timers.
6997          */
6998         if (CHIP_IS_E2(bp) && BP_VN(bp) == 3) {
6999                 struct ilt_client_info ilt_cli;
7000                 /* use dummy TM client */
7001                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7002                 ilt_cli.start = 0;
7003                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7004                 ilt_cli.client_num = ILT_CLIENT_TM;
7005
7006                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7007         }
7008
7009         /* this assumes that reset_port() called before reset_func()*/
7010         if (CHIP_IS_E2(bp))
7011                 bnx2x_pf_disable(bp);
7012
7013         bp->dmae_ready = 0;
7014 }
7015
7016 static void bnx2x_reset_port(struct bnx2x *bp)
7017 {
7018         int port = BP_PORT(bp);
7019         u32 val;
7020
7021         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7022
7023         /* Do not rcv packets to BRB */
7024         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7025         /* Do not direct rcv packets that are not for MCP to the BRB */
7026         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7027                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7028
7029         /* Configure AEU */
7030         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7031
7032         msleep(100);
7033         /* Check for BRB port occupancy */
7034         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7035         if (val)
7036                 DP(NETIF_MSG_IFDOWN,
7037                    "BRB1 is not empty  %d blocks are occupied\n", val);
7038
7039         /* TODO: Close Doorbell port? */
7040 }
7041
7042 static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
7043 {
7044         DP(BNX2X_MSG_MCP, "function %d  reset_code %x\n",
7045            BP_ABS_FUNC(bp), reset_code);
7046
7047         switch (reset_code) {
7048         case FW_MSG_CODE_DRV_UNLOAD_COMMON:
7049                 bnx2x_reset_port(bp);
7050                 bnx2x_reset_func(bp);
7051                 bnx2x_reset_common(bp);
7052                 break;
7053
7054         case FW_MSG_CODE_DRV_UNLOAD_PORT:
7055                 bnx2x_reset_port(bp);
7056                 bnx2x_reset_func(bp);
7057                 break;
7058
7059         case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
7060                 bnx2x_reset_func(bp);
7061                 break;
7062
7063         default:
7064                 BNX2X_ERR("Unknown reset_code (0x%x) from MCP\n", reset_code);
7065                 break;
7066         }
7067 }
7068
7069 #ifdef BCM_CNIC
7070 static inline void bnx2x_del_fcoe_eth_macs(struct bnx2x *bp)
7071 {
7072         if (bp->flags & FCOE_MACS_SET) {
7073                 if (!IS_MF_SD(bp))
7074                         bnx2x_set_fip_eth_mac_addr(bp, 0);
7075
7076                 bnx2x_set_all_enode_macs(bp, 0);
7077
7078                 bp->flags &= ~FCOE_MACS_SET;
7079         }
7080 }
7081 #endif
7082
7083 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7084 {
7085         int port = BP_PORT(bp);
7086         u32 reset_code = 0;
7087         int i, cnt, rc;
7088
7089         /* Wait until tx fastpath tasks complete */
7090         for_each_tx_queue(bp, i) {
7091                 struct bnx2x_fastpath *fp = &bp->fp[i];
7092
7093                 cnt = 1000;
7094                 while (bnx2x_has_tx_work_unload(fp)) {
7095
7096                         if (!cnt) {
7097                                 BNX2X_ERR("timeout waiting for queue[%d]\n",
7098                                           i);
7099 #ifdef BNX2X_STOP_ON_ERROR
7100                                 bnx2x_panic();
7101                                 return -EBUSY;
7102 #else
7103                                 break;
7104 #endif
7105                         }
7106                         cnt--;
7107                         msleep(1);
7108                 }
7109         }
7110         /* Give HW time to discard old tx messages */
7111         msleep(1);
7112
7113         if (CHIP_IS_E1(bp)) {
7114                 /* invalidate mc list,
7115                  * wait and poll (interrupts are off)
7116                  */
7117                 bnx2x_invlidate_e1_mc_list(bp);
7118                 bnx2x_set_eth_mac(bp, 0);
7119
7120         } else {
7121                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7122
7123                 bnx2x_set_eth_mac(bp, 0);
7124
7125                 for (i = 0; i < MC_HASH_SIZE; i++)
7126                         REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
7127         }
7128
7129 #ifdef BCM_CNIC
7130         bnx2x_del_fcoe_eth_macs(bp);
7131 #endif
7132
7133         if (unload_mode == UNLOAD_NORMAL)
7134                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7135
7136         else if (bp->flags & NO_WOL_FLAG)
7137                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
7138
7139         else if (bp->wol) {
7140                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7141                 u8 *mac_addr = bp->dev->dev_addr;
7142                 u32 val;
7143                 /* The mac address is written to entries 1-4 to
7144                    preserve entry 0 which is used by the PMF */
7145                 u8 entry = (BP_E1HVN(bp) + 1)*8;
7146
7147                 val = (mac_addr[0] << 8) | mac_addr[1];
7148                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7149
7150                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7151                       (mac_addr[4] << 8) | mac_addr[5];
7152                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7153
7154                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7155
7156         } else
7157                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7158
7159         /* Close multi and leading connections
7160            Completions for ramrods are collected in a synchronous way */
7161         for_each_queue(bp, i)
7162
7163                 if (bnx2x_stop_client(bp, i))
7164 #ifdef BNX2X_STOP_ON_ERROR
7165                         return;
7166 #else
7167                         goto unload_error;
7168 #endif
7169
7170         rc = bnx2x_func_stop(bp);
7171         if (rc) {
7172                 BNX2X_ERR("Function stop failed!\n");
7173 #ifdef BNX2X_STOP_ON_ERROR
7174                 return;
7175 #else
7176                 goto unload_error;
7177 #endif
7178         }
7179 #ifndef BNX2X_STOP_ON_ERROR
7180 unload_error:
7181 #endif
7182         if (!BP_NOMCP(bp))
7183                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7184         else {
7185                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      "
7186                                      "%d, %d, %d\n", BP_PATH(bp),
7187                    load_count[BP_PATH(bp)][0],
7188                    load_count[BP_PATH(bp)][1],
7189                    load_count[BP_PATH(bp)][2]);
7190                 load_count[BP_PATH(bp)][0]--;
7191                 load_count[BP_PATH(bp)][1 + port]--;
7192                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  "
7193                                      "%d, %d, %d\n", BP_PATH(bp),
7194                    load_count[BP_PATH(bp)][0], load_count[BP_PATH(bp)][1],
7195                    load_count[BP_PATH(bp)][2]);
7196                 if (load_count[BP_PATH(bp)][0] == 0)
7197                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7198                 else if (load_count[BP_PATH(bp)][1 + port] == 0)
7199                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7200                 else
7201                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7202         }
7203
7204         if ((reset_code == FW_MSG_CODE_DRV_UNLOAD_COMMON) ||
7205             (reset_code == FW_MSG_CODE_DRV_UNLOAD_PORT))
7206                 bnx2x__link_reset(bp);
7207
7208         /* Disable HW interrupts, NAPI */
7209         bnx2x_netif_stop(bp, 1);
7210
7211         /* Release IRQs */
7212         bnx2x_free_irq(bp);
7213
7214         /* Reset the chip */
7215         bnx2x_reset_chip(bp, reset_code);
7216
7217         /* Report UNLOAD_DONE to MCP */
7218         if (!BP_NOMCP(bp))
7219                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7220
7221 }
7222
7223 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
7224 {
7225         u32 val;
7226
7227         DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7228
7229         if (CHIP_IS_E1(bp)) {
7230                 int port = BP_PORT(bp);
7231                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7232                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
7233
7234                 val = REG_RD(bp, addr);
7235                 val &= ~(0x300);
7236                 REG_WR(bp, addr, val);
7237         } else if (CHIP_IS_E1H(bp)) {
7238                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7239                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7240                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7241                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7242         }
7243 }
7244
7245 /* Close gates #2, #3 and #4: */
7246 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7247 {
7248         u32 val, addr;
7249
7250         /* Gates #2 and #4a are closed/opened for "not E1" only */
7251         if (!CHIP_IS_E1(bp)) {
7252                 /* #4 */
7253                 val = REG_RD(bp, PXP_REG_HST_DISCARD_DOORBELLS);
7254                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS,
7255                        close ? (val | 0x1) : (val & (~(u32)1)));
7256                 /* #2 */
7257                 val = REG_RD(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES);
7258                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES,
7259                        close ? (val | 0x1) : (val & (~(u32)1)));
7260         }
7261
7262         /* #3 */
7263         addr = BP_PORT(bp) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
7264         val = REG_RD(bp, addr);
7265         REG_WR(bp, addr, (!close) ? (val | 0x1) : (val & (~(u32)1)));
7266
7267         DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7268                 close ? "closing" : "opening");
7269         mmiowb();
7270 }
7271
7272 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
7273
7274 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7275 {
7276         /* Do some magic... */
7277         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7278         *magic_val = val & SHARED_MF_CLP_MAGIC;
7279         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7280 }
7281
7282 /* Restore the value of the `magic' bit.
7283  *
7284  * @param pdev Device handle.
7285  * @param magic_val Old value of the `magic' bit.
7286  */
7287 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7288 {
7289         /* Restore the `magic' bit value... */
7290         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7291         MF_CFG_WR(bp, shared_mf_config.clp_mb,
7292                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7293 }
7294
7295 /**
7296  * Prepares for MCP reset: takes care of CLP configurations.
7297  *
7298  * @param bp
7299  * @param magic_val Old value of 'magic' bit.
7300  */
7301 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7302 {
7303         u32 shmem;
7304         u32 validity_offset;
7305
7306         DP(NETIF_MSG_HW, "Starting\n");
7307
7308         /* Set `magic' bit in order to save MF config */
7309         if (!CHIP_IS_E1(bp))
7310                 bnx2x_clp_reset_prep(bp, magic_val);
7311
7312         /* Get shmem offset */
7313         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7314         validity_offset = offsetof(struct shmem_region, validity_map[0]);
7315
7316         /* Clear validity map flags */
7317         if (shmem > 0)
7318                 REG_WR(bp, shmem + validity_offset, 0);
7319 }
7320
7321 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
7322 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
7323
7324 /* Waits for MCP_ONE_TIMEOUT or MCP_ONE_TIMEOUT*10,
7325  * depending on the HW type.
7326  *
7327  * @param bp
7328  */
7329 static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7330 {
7331         /* special handling for emulation and FPGA,
7332            wait 10 times longer */
7333         if (CHIP_REV_IS_SLOW(bp))
7334                 msleep(MCP_ONE_TIMEOUT*10);
7335         else
7336                 msleep(MCP_ONE_TIMEOUT);
7337 }
7338
7339 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
7340 {
7341         u32 shmem, cnt, validity_offset, val;
7342         int rc = 0;
7343
7344         msleep(100);
7345
7346         /* Get shmem offset */
7347         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7348         if (shmem == 0) {
7349                 BNX2X_ERR("Shmem 0 return failure\n");
7350                 rc = -ENOTTY;
7351                 goto exit_lbl;
7352         }
7353
7354         validity_offset = offsetof(struct shmem_region, validity_map[0]);
7355
7356         /* Wait for MCP to come up */
7357         for (cnt = 0; cnt < (MCP_TIMEOUT / MCP_ONE_TIMEOUT); cnt++) {
7358                 /* TBD: its best to check validity map of last port.
7359                  * currently checks on port 0.
7360                  */
7361                 val = REG_RD(bp, shmem + validity_offset);
7362                 DP(NETIF_MSG_HW, "shmem 0x%x validity map(0x%x)=0x%x\n", shmem,
7363                    shmem + validity_offset, val);
7364
7365                 /* check that shared memory is valid. */
7366                 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7367                     == (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7368                         break;
7369
7370                 bnx2x_mcp_wait_one(bp);
7371         }
7372
7373         DP(NETIF_MSG_HW, "Cnt=%d Shmem validity map 0x%x\n", cnt, val);
7374
7375         /* Check that shared memory is valid. This indicates that MCP is up. */
7376         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
7377             (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
7378                 BNX2X_ERR("Shmem signature not present. MCP is not up !!\n");
7379                 rc = -ENOTTY;
7380                 goto exit_lbl;
7381         }
7382
7383 exit_lbl:
7384         /* Restore the `magic' bit value */
7385         if (!CHIP_IS_E1(bp))
7386                 bnx2x_clp_reset_done(bp, magic_val);
7387
7388         return rc;
7389 }
7390
7391 static void bnx2x_pxp_prep(struct bnx2x *bp)
7392 {
7393         if (!CHIP_IS_E1(bp)) {
7394                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
7395                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
7396                 REG_WR(bp, PXP2_REG_RQ_CFG_DONE, 0);
7397                 mmiowb();
7398         }
7399 }
7400
7401 /*
7402  * Reset the whole chip except for:
7403  *      - PCIE core
7404  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
7405  *              one reset bit)
7406  *      - IGU
7407  *      - MISC (including AEU)
7408  *      - GRC
7409  *      - RBCN, RBCP
7410  */
7411 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp)
7412 {
7413         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
7414
7415         not_reset_mask1 =
7416                 MISC_REGISTERS_RESET_REG_1_RST_HC |
7417                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
7418                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
7419
7420         not_reset_mask2 =
7421                 MISC_REGISTERS_RESET_REG_2_RST_MDIO |
7422                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
7423                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
7424                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
7425                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
7426                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
7427                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
7428                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B;
7429
7430         reset_mask1 = 0xffffffff;
7431
7432         if (CHIP_IS_E1(bp))
7433                 reset_mask2 = 0xffff;
7434         else
7435                 reset_mask2 = 0x1ffff;
7436
7437         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7438                reset_mask1 & (~not_reset_mask1));
7439         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7440                reset_mask2 & (~not_reset_mask2));
7441
7442         barrier();
7443         mmiowb();
7444
7445         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
7446         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2);
7447         mmiowb();
7448 }
7449
7450 static int bnx2x_process_kill(struct bnx2x *bp)
7451 {
7452         int cnt = 1000;
7453         u32 val = 0;
7454         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
7455
7456
7457         /* Empty the Tetris buffer, wait for 1s */
7458         do {
7459                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
7460                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
7461                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
7462                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
7463                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
7464                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
7465                     ((port_is_idle_0 & 0x1) == 0x1) &&
7466                     ((port_is_idle_1 & 0x1) == 0x1) &&
7467                     (pgl_exp_rom2 == 0xffffffff))
7468                         break;
7469                 msleep(1);
7470         } while (cnt-- > 0);
7471
7472         if (cnt <= 0) {
7473                 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
7474                           " are still"
7475                           " outstanding read requests after 1s!\n");
7476                 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
7477                           " port_is_idle_0=0x%08x,"
7478                           " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
7479                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
7480                           pgl_exp_rom2);
7481                 return -EAGAIN;
7482         }
7483
7484         barrier();
7485
7486         /* Close gates #2, #3 and #4 */
7487         bnx2x_set_234_gates(bp, true);
7488
7489         /* TBD: Indicate that "process kill" is in progress to MCP */
7490
7491         /* Clear "unprepared" bit */
7492         REG_WR(bp, MISC_REG_UNPREPARED, 0);
7493         barrier();
7494
7495         /* Make sure all is written to the chip before the reset */
7496         mmiowb();
7497
7498         /* Wait for 1ms to empty GLUE and PCI-E core queues,
7499          * PSWHST, GRC and PSWRD Tetris buffer.
7500          */
7501         msleep(1);
7502
7503         /* Prepare to chip reset: */
7504         /* MCP */
7505         bnx2x_reset_mcp_prep(bp, &val);
7506
7507         /* PXP */
7508         bnx2x_pxp_prep(bp);
7509         barrier();
7510
7511         /* reset the chip */
7512         bnx2x_process_kill_chip_reset(bp);
7513         barrier();
7514
7515         /* Recover after reset: */
7516         /* MCP */
7517         if (bnx2x_reset_mcp_comp(bp, val))
7518                 return -EAGAIN;
7519
7520         /* PXP */
7521         bnx2x_pxp_prep(bp);
7522
7523         /* Open the gates #2, #3 and #4 */
7524         bnx2x_set_234_gates(bp, false);
7525
7526         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
7527          * reset state, re-enable attentions. */
7528
7529         return 0;
7530 }
7531
7532 static int bnx2x_leader_reset(struct bnx2x *bp)
7533 {
7534         int rc = 0;
7535         /* Try to recover after the failure */
7536         if (bnx2x_process_kill(bp)) {
7537                 printk(KERN_ERR "%s: Something bad had happen! Aii!\n",
7538                        bp->dev->name);
7539                 rc = -EAGAIN;
7540                 goto exit_leader_reset;
7541         }
7542
7543         /* Clear "reset is in progress" bit and update the driver state */
7544         bnx2x_set_reset_done(bp);
7545         bp->recovery_state = BNX2X_RECOVERY_DONE;
7546
7547 exit_leader_reset:
7548         bp->is_leader = 0;
7549         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESERVED_08);
7550         smp_wmb();
7551         return rc;
7552 }
7553
7554 /* Assumption: runs under rtnl lock. This together with the fact
7555  * that it's called only from bnx2x_reset_task() ensure that it
7556  * will never be called when netif_running(bp->dev) is false.
7557  */
7558 static void bnx2x_parity_recover(struct bnx2x *bp)
7559 {
7560         DP(NETIF_MSG_HW, "Handling parity\n");
7561         while (1) {
7562                 switch (bp->recovery_state) {
7563                 case BNX2X_RECOVERY_INIT:
7564                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
7565                         /* Try to get a LEADER_LOCK HW lock */
7566                         if (bnx2x_trylock_hw_lock(bp,
7567                                 HW_LOCK_RESOURCE_RESERVED_08))
7568                                 bp->is_leader = 1;
7569
7570                         /* Stop the driver */
7571                         /* If interface has been removed - break */
7572                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
7573                                 return;
7574
7575                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
7576                         /* Ensure "is_leader" and "recovery_state"
7577                          *  update values are seen on other CPUs
7578                          */
7579                         smp_wmb();
7580                         break;
7581
7582                 case BNX2X_RECOVERY_WAIT:
7583                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
7584                         if (bp->is_leader) {
7585                                 u32 load_counter = bnx2x_get_load_cnt(bp);
7586                                 if (load_counter) {
7587                                         /* Wait until all other functions get
7588                                          * down.
7589                                          */
7590                                         schedule_delayed_work(&bp->reset_task,
7591                                                                 HZ/10);
7592                                         return;
7593                                 } else {
7594                                         /* If all other functions got down -
7595                                          * try to bring the chip back to
7596                                          * normal. In any case it's an exit
7597                                          * point for a leader.
7598                                          */
7599                                         if (bnx2x_leader_reset(bp) ||
7600                                         bnx2x_nic_load(bp, LOAD_NORMAL)) {
7601                                                 printk(KERN_ERR"%s: Recovery "
7602                                                 "has failed. Power cycle is "
7603                                                 "needed.\n", bp->dev->name);
7604                                                 /* Disconnect this device */
7605                                                 netif_device_detach(bp->dev);
7606                                                 /* Block ifup for all function
7607                                                  * of this ASIC until
7608                                                  * "process kill" or power
7609                                                  * cycle.
7610                                                  */
7611                                                 bnx2x_set_reset_in_progress(bp);
7612                                                 /* Shut down the power */
7613                                                 bnx2x_set_power_state(bp,
7614                                                                 PCI_D3hot);
7615                                                 return;
7616                                         }
7617
7618                                         return;
7619                                 }
7620                         } else { /* non-leader */
7621                                 if (!bnx2x_reset_is_done(bp)) {
7622                                         /* Try to get a LEADER_LOCK HW lock as
7623                                          * long as a former leader may have
7624                                          * been unloaded by the user or
7625                                          * released a leadership by another
7626                                          * reason.
7627                                          */
7628                                         if (bnx2x_trylock_hw_lock(bp,
7629                                             HW_LOCK_RESOURCE_RESERVED_08)) {
7630                                                 /* I'm a leader now! Restart a
7631                                                  * switch case.
7632                                                  */
7633                                                 bp->is_leader = 1;
7634                                                 break;
7635                                         }
7636
7637                                         schedule_delayed_work(&bp->reset_task,
7638                                                                 HZ/10);
7639                                         return;
7640
7641                                 } else { /* A leader has completed
7642                                           * the "process kill". It's an exit
7643                                           * point for a non-leader.
7644                                           */
7645                                         bnx2x_nic_load(bp, LOAD_NORMAL);
7646                                         bp->recovery_state =
7647                                                 BNX2X_RECOVERY_DONE;
7648                                         smp_wmb();
7649                                         return;
7650                                 }
7651                         }
7652                 default:
7653                         return;
7654                 }
7655         }
7656 }
7657
7658 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
7659  * scheduled on a general queue in order to prevent a dead lock.
7660  */
7661 static void bnx2x_reset_task(struct work_struct *work)
7662 {
7663         struct bnx2x *bp = container_of(work, struct bnx2x, reset_task.work);
7664
7665 #ifdef BNX2X_STOP_ON_ERROR
7666         BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
7667                   " so reset not done to allow debug dump,\n"
7668          KERN_ERR " you will need to reboot when done\n");
7669         return;
7670 #endif
7671
7672         rtnl_lock();
7673
7674         if (!netif_running(bp->dev))
7675                 goto reset_task_exit;
7676
7677         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE))
7678                 bnx2x_parity_recover(bp);
7679         else {
7680                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
7681                 bnx2x_nic_load(bp, LOAD_NORMAL);
7682         }
7683
7684 reset_task_exit:
7685         rtnl_unlock();
7686 }
7687
7688 /* end of nic load/unload */
7689
7690 /*
7691  * Init service functions
7692  */
7693
7694 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
7695 {
7696         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
7697         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
7698         return base + (BP_ABS_FUNC(bp)) * stride;
7699 }
7700
7701 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
7702 {
7703         u32 reg = bnx2x_get_pretend_reg(bp);
7704
7705         /* Flush all outstanding writes */
7706         mmiowb();
7707
7708         /* Pretend to be function 0 */
7709         REG_WR(bp, reg, 0);
7710         REG_RD(bp, reg);        /* Flush the GRC transaction (in the chip) */
7711
7712         /* From now we are in the "like-E1" mode */
7713         bnx2x_int_disable(bp);
7714
7715         /* Flush all outstanding writes */
7716         mmiowb();
7717
7718         /* Restore the original function */
7719         REG_WR(bp, reg, BP_ABS_FUNC(bp));
7720         REG_RD(bp, reg);
7721 }
7722
7723 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
7724 {
7725         if (CHIP_IS_E1(bp))
7726                 bnx2x_int_disable(bp);
7727         else
7728                 bnx2x_undi_int_disable_e1h(bp);
7729 }
7730
7731 static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
7732 {
7733         u32 val;
7734
7735         /* Check if there is any driver already loaded */
7736         val = REG_RD(bp, MISC_REG_UNPREPARED);
7737         if (val == 0x1) {
7738                 /* Check if it is the UNDI driver
7739                  * UNDI driver initializes CID offset for normal bell to 0x7
7740                  */
7741                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7742                 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
7743                 if (val == 0x7) {
7744                         u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7745                         /* save our pf_num */
7746                         int orig_pf_num = bp->pf_num;
7747                         u32 swap_en;
7748                         u32 swap_val;
7749
7750                         /* clear the UNDI indication */
7751                         REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
7752
7753                         BNX2X_DEV_INFO("UNDI is active! reset device\n");
7754
7755                         /* try unload UNDI on port 0 */
7756                         bp->pf_num = 0;
7757                         bp->fw_seq =
7758                               (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
7759                                 DRV_MSG_SEQ_NUMBER_MASK);
7760                         reset_code = bnx2x_fw_command(bp, reset_code, 0);
7761
7762                         /* if UNDI is loaded on the other port */
7763                         if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
7764
7765                                 /* send "DONE" for previous unload */
7766                                 bnx2x_fw_command(bp,
7767                                                  DRV_MSG_CODE_UNLOAD_DONE, 0);
7768
7769                                 /* unload UNDI on port 1 */
7770                                 bp->pf_num = 1;
7771                                 bp->fw_seq =
7772                               (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
7773                                         DRV_MSG_SEQ_NUMBER_MASK);
7774                                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7775
7776                                 bnx2x_fw_command(bp, reset_code, 0);
7777                         }
7778
7779                         /* now it's safe to release the lock */
7780                         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7781
7782                         bnx2x_undi_int_disable(bp);
7783
7784                         /* close input traffic and wait for it */
7785                         /* Do not rcv packets to BRB */
7786                         REG_WR(bp,
7787                               (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_DRV_MASK :
7788                                              NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
7789                         /* Do not direct rcv packets that are not for MCP to
7790                          * the BRB */
7791                         REG_WR(bp,
7792                                (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_NOT_MCP :
7793                                               NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7794                         /* clear AEU */
7795                         REG_WR(bp,
7796                              (BP_PORT(bp) ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7797                                             MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
7798                         msleep(10);
7799
7800                         /* save NIG port swap info */
7801                         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7802                         swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7803                         /* reset device */
7804                         REG_WR(bp,
7805                                GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7806                                0xd3ffffff);
7807                         REG_WR(bp,
7808                                GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7809                                0x1403);
7810                         /* take the NIG out of reset and restore swap values */
7811                         REG_WR(bp,
7812                                GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7813                                MISC_REGISTERS_RESET_REG_1_RST_NIG);
7814                         REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
7815                         REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
7816
7817                         /* send unload done to the MCP */
7818                         bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7819
7820                         /* restore our func and fw_seq */
7821                         bp->pf_num = orig_pf_num;
7822                         bp->fw_seq =
7823                               (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
7824                                 DRV_MSG_SEQ_NUMBER_MASK);
7825                 } else
7826                         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7827         }
7828 }
7829
7830 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
7831 {
7832         u32 val, val2, val3, val4, id;
7833         u16 pmc;
7834
7835         /* Get the chip revision id and number. */
7836         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
7837         val = REG_RD(bp, MISC_REG_CHIP_NUM);
7838         id = ((val & 0xffff) << 16);
7839         val = REG_RD(bp, MISC_REG_CHIP_REV);
7840         id |= ((val & 0xf) << 12);
7841         val = REG_RD(bp, MISC_REG_CHIP_METAL);
7842         id |= ((val & 0xff) << 4);
7843         val = REG_RD(bp, MISC_REG_BOND_ID);
7844         id |= (val & 0xf);
7845         bp->common.chip_id = id;
7846
7847         /* Set doorbell size */
7848         bp->db_size = (1 << BNX2X_DB_SHIFT);
7849
7850         if (CHIP_IS_E2(bp)) {
7851                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
7852                 if ((val & 1) == 0)
7853                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
7854                 else
7855                         val = (val >> 1) & 1;
7856                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
7857                                                        "2_PORT_MODE");
7858                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
7859                                                  CHIP_2_PORT_MODE;
7860
7861                 if (CHIP_MODE_IS_4_PORT(bp))
7862                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
7863                 else
7864                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
7865         } else {
7866                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
7867                 bp->pfid = bp->pf_num;                  /* 0..7 */
7868         }
7869
7870         /*
7871          * set base FW non-default (fast path) status block id, this value is
7872          * used to initialize the fw_sb_id saved on the fp/queue structure to
7873          * determine the id used by the FW.
7874          */
7875         if (CHIP_IS_E1x(bp))
7876                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x;
7877         else /* E2 */
7878                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E2;
7879
7880         bp->link_params.chip_id = bp->common.chip_id;
7881         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
7882
7883         val = (REG_RD(bp, 0x2874) & 0x55);
7884         if ((bp->common.chip_id & 0x1) ||
7885             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
7886                 bp->flags |= ONE_PORT_FLAG;
7887                 BNX2X_DEV_INFO("single port device\n");
7888         }
7889
7890         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
7891         bp->common.flash_size = (NVRAM_1MB_SIZE <<
7892                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
7893         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
7894                        bp->common.flash_size, bp->common.flash_size);
7895
7896         bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7897         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
7898                                         MISC_REG_GENERIC_CR_1 :
7899                                         MISC_REG_GENERIC_CR_0));
7900         bp->link_params.shmem_base = bp->common.shmem_base;
7901         bp->link_params.shmem2_base = bp->common.shmem2_base;
7902         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
7903                        bp->common.shmem_base, bp->common.shmem2_base);
7904
7905         if (!bp->common.shmem_base) {
7906                 BNX2X_DEV_INFO("MCP not active\n");
7907                 bp->flags |= NO_MCP_FLAG;
7908                 return;
7909         }
7910
7911         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7912         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7913                 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7914                 BNX2X_ERR("BAD MCP validity signature\n");
7915
7916         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
7917         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
7918
7919         bp->link_params.hw_led_mode = ((bp->common.hw_config &
7920                                         SHARED_HW_CFG_LED_MODE_MASK) >>
7921                                        SHARED_HW_CFG_LED_MODE_SHIFT);
7922
7923         bp->link_params.feature_config_flags = 0;
7924         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
7925         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
7926                 bp->link_params.feature_config_flags |=
7927                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7928         else
7929                 bp->link_params.feature_config_flags &=
7930                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7931
7932         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
7933         bp->common.bc_ver = val;
7934         BNX2X_DEV_INFO("bc_ver %X\n", val);
7935         if (val < BNX2X_BC_VER) {
7936                 /* for now only warn
7937                  * later we might need to enforce this */
7938                 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
7939                           "please upgrade BC\n", BNX2X_BC_VER, val);
7940         }
7941         bp->link_params.feature_config_flags |=
7942                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
7943                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
7944
7945         bp->link_params.feature_config_flags |=
7946                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
7947                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
7948
7949         if (BP_E1HVN(bp) == 0) {
7950                 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
7951                 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
7952         } else {
7953                 /* no WOL capability for E1HVN != 0 */
7954                 bp->flags |= NO_WOL_FLAG;
7955         }
7956         BNX2X_DEV_INFO("%sWoL capable\n",
7957                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
7958
7959         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
7960         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
7961         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
7962         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
7963
7964         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
7965                  val, val2, val3, val4);
7966 }
7967
7968 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
7969 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
7970
7971 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
7972 {
7973         int pfid = BP_FUNC(bp);
7974         int vn = BP_E1HVN(bp);
7975         int igu_sb_id;
7976         u32 val;
7977         u8 fid;
7978
7979         bp->igu_base_sb = 0xff;
7980         bp->igu_sb_cnt = 0;
7981         if (CHIP_INT_MODE_IS_BC(bp)) {
7982                 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
7983                                        NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
7984
7985                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
7986                         FP_SB_MAX_E1x;
7987
7988                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
7989                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
7990
7991                 return;
7992         }
7993
7994         /* IGU in normal mode - read CAM */
7995         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
7996              igu_sb_id++) {
7997                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
7998                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
7999                         continue;
8000                 fid = IGU_FID(val);
8001                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8002                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
8003                                 continue;
8004                         if (IGU_VEC(val) == 0)
8005                                 /* default status block */
8006                                 bp->igu_dsb_id = igu_sb_id;
8007                         else {
8008                                 if (bp->igu_base_sb == 0xff)
8009                                         bp->igu_base_sb = igu_sb_id;
8010                                 bp->igu_sb_cnt++;
8011                         }
8012                 }
8013         }
8014         bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
8015                                    NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
8016         if (bp->igu_sb_cnt == 0)
8017                 BNX2X_ERR("CAM configuration error\n");
8018 }
8019
8020 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
8021                                                     u32 switch_cfg)
8022 {
8023         int cfg_size = 0, idx, port = BP_PORT(bp);
8024
8025         /* Aggregation of supported attributes of all external phys */
8026         bp->port.supported[0] = 0;
8027         bp->port.supported[1] = 0;
8028         switch (bp->link_params.num_phys) {
8029         case 1:
8030                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
8031                 cfg_size = 1;
8032                 break;
8033         case 2:
8034                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
8035                 cfg_size = 1;
8036                 break;
8037         case 3:
8038                 if (bp->link_params.multi_phy_config &
8039                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8040                         bp->port.supported[1] =
8041                                 bp->link_params.phy[EXT_PHY1].supported;
8042                         bp->port.supported[0] =
8043                                 bp->link_params.phy[EXT_PHY2].supported;
8044                 } else {
8045                         bp->port.supported[0] =
8046                                 bp->link_params.phy[EXT_PHY1].supported;
8047                         bp->port.supported[1] =
8048                                 bp->link_params.phy[EXT_PHY2].supported;
8049                 }
8050                 cfg_size = 2;
8051                 break;
8052         }
8053
8054         if (!(bp->port.supported[0] || bp->port.supported[1])) {
8055                 BNX2X_ERR("NVRAM config error. BAD phy config."
8056                           "PHY1 config 0x%x, PHY2 config 0x%x\n",
8057                            SHMEM_RD(bp,
8058                            dev_info.port_hw_config[port].external_phy_config),
8059                            SHMEM_RD(bp,
8060                            dev_info.port_hw_config[port].external_phy_config2));
8061                         return;
8062         }
8063
8064         switch (switch_cfg) {
8065         case SWITCH_CFG_1G:
8066                 bp->port.phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR +
8067                                            port*0x10);
8068                 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
8069                 break;
8070
8071         case SWITCH_CFG_10G:
8072                 bp->port.phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR +
8073                                            port*0x18);
8074                 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
8075                 break;
8076
8077         default:
8078                 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
8079                           bp->port.link_config[0]);
8080                 return;
8081         }
8082         /* mask what we support according to speed_cap_mask per configuration */
8083         for (idx = 0; idx < cfg_size; idx++) {
8084                 if (!(bp->link_params.speed_cap_mask[idx] &
8085                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
8086                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
8087
8088                 if (!(bp->link_params.speed_cap_mask[idx] &
8089                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
8090                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
8091
8092                 if (!(bp->link_params.speed_cap_mask[idx] &
8093                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
8094                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
8095
8096                 if (!(bp->link_params.speed_cap_mask[idx] &
8097                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
8098                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
8099
8100                 if (!(bp->link_params.speed_cap_mask[idx] &
8101                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
8102                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
8103                                                      SUPPORTED_1000baseT_Full);
8104
8105                 if (!(bp->link_params.speed_cap_mask[idx] &
8106                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
8107                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
8108
8109                 if (!(bp->link_params.speed_cap_mask[idx] &
8110                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
8111                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8112
8113         }
8114
8115         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8116                        bp->port.supported[1]);
8117 }
8118
8119 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
8120 {
8121         u32 link_config, idx, cfg_size = 0;
8122         bp->port.advertising[0] = 0;
8123         bp->port.advertising[1] = 0;
8124         switch (bp->link_params.num_phys) {
8125         case 1:
8126         case 2:
8127                 cfg_size = 1;
8128                 break;
8129         case 3:
8130                 cfg_size = 2;
8131                 break;
8132         }
8133         for (idx = 0; idx < cfg_size; idx++) {
8134                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8135                 link_config = bp->port.link_config[idx];
8136                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8137                 case PORT_FEATURE_LINK_SPEED_AUTO:
8138                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8139                                 bp->link_params.req_line_speed[idx] =
8140                                         SPEED_AUTO_NEG;
8141                                 bp->port.advertising[idx] |=
8142                                         bp->port.supported[idx];
8143                         } else {
8144                                 /* force 10G, no AN */
8145                                 bp->link_params.req_line_speed[idx] =
8146                                         SPEED_10000;
8147                                 bp->port.advertising[idx] |=
8148                                         (ADVERTISED_10000baseT_Full |
8149                                          ADVERTISED_FIBRE);
8150                                 continue;
8151                         }
8152                         break;
8153
8154                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8155                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
8156                                 bp->link_params.req_line_speed[idx] =
8157                                         SPEED_10;
8158                                 bp->port.advertising[idx] |=
8159                                         (ADVERTISED_10baseT_Full |
8160                                          ADVERTISED_TP);
8161                         } else {
8162                                 BNX2X_ERROR("NVRAM config error. "
8163                                             "Invalid link_config 0x%x"
8164                                             "  speed_cap_mask 0x%x\n",
8165                                             link_config,
8166                                     bp->link_params.speed_cap_mask[idx]);
8167                                 return;
8168                         }
8169                         break;
8170
8171                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8172                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
8173                                 bp->link_params.req_line_speed[idx] =
8174                                         SPEED_10;
8175                                 bp->link_params.req_duplex[idx] =
8176                                         DUPLEX_HALF;
8177                                 bp->port.advertising[idx] |=
8178                                         (ADVERTISED_10baseT_Half |
8179                                          ADVERTISED_TP);
8180                         } else {
8181                                 BNX2X_ERROR("NVRAM config error. "
8182                                             "Invalid link_config 0x%x"
8183                                             "  speed_cap_mask 0x%x\n",
8184                                             link_config,
8185                                           bp->link_params.speed_cap_mask[idx]);
8186                                 return;
8187                         }
8188                         break;
8189
8190                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8191                         if (bp->port.supported[idx] &
8192                             SUPPORTED_100baseT_Full) {
8193                                 bp->link_params.req_line_speed[idx] =
8194                                         SPEED_100;
8195                                 bp->port.advertising[idx] |=
8196                                         (ADVERTISED_100baseT_Full |
8197                                          ADVERTISED_TP);
8198                         } else {
8199                                 BNX2X_ERROR("NVRAM config error. "
8200                                             "Invalid link_config 0x%x"
8201                                             "  speed_cap_mask 0x%x\n",
8202                                             link_config,
8203                                           bp->link_params.speed_cap_mask[idx]);
8204                                 return;
8205                         }
8206                         break;
8207
8208                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8209                         if (bp->port.supported[idx] &
8210                             SUPPORTED_100baseT_Half) {
8211                                 bp->link_params.req_line_speed[idx] =
8212                                                                 SPEED_100;
8213                                 bp->link_params.req_duplex[idx] =
8214                                                                 DUPLEX_HALF;
8215                                 bp->port.advertising[idx] |=
8216                                         (ADVERTISED_100baseT_Half |
8217                                          ADVERTISED_TP);
8218                         } else {
8219                                 BNX2X_ERROR("NVRAM config error. "
8220                                     "Invalid link_config 0x%x"
8221                                     "  speed_cap_mask 0x%x\n",
8222                                     link_config,
8223                                     bp->link_params.speed_cap_mask[idx]);
8224                                 return;
8225                         }
8226                         break;
8227
8228                 case PORT_FEATURE_LINK_SPEED_1G:
8229                         if (bp->port.supported[idx] &
8230                             SUPPORTED_1000baseT_Full) {
8231                                 bp->link_params.req_line_speed[idx] =
8232                                         SPEED_1000;
8233                                 bp->port.advertising[idx] |=
8234                                         (ADVERTISED_1000baseT_Full |
8235                                          ADVERTISED_TP);
8236                         } else {
8237                                 BNX2X_ERROR("NVRAM config error. "
8238                                     "Invalid link_config 0x%x"
8239                                     "  speed_cap_mask 0x%x\n",
8240                                     link_config,
8241                                     bp->link_params.speed_cap_mask[idx]);
8242                                 return;
8243                         }
8244                         break;
8245
8246                 case PORT_FEATURE_LINK_SPEED_2_5G:
8247                         if (bp->port.supported[idx] &
8248                             SUPPORTED_2500baseX_Full) {
8249                                 bp->link_params.req_line_speed[idx] =
8250                                         SPEED_2500;
8251                                 bp->port.advertising[idx] |=
8252                                         (ADVERTISED_2500baseX_Full |
8253                                                 ADVERTISED_TP);
8254                         } else {
8255                                 BNX2X_ERROR("NVRAM config error. "
8256                                     "Invalid link_config 0x%x"
8257                                     "  speed_cap_mask 0x%x\n",
8258                                     link_config,
8259                                     bp->link_params.speed_cap_mask[idx]);
8260                                 return;
8261                         }
8262                         break;
8263
8264                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8265                 case PORT_FEATURE_LINK_SPEED_10G_KX4:
8266                 case PORT_FEATURE_LINK_SPEED_10G_KR:
8267                         if (bp->port.supported[idx] &
8268                             SUPPORTED_10000baseT_Full) {
8269                                 bp->link_params.req_line_speed[idx] =
8270                                         SPEED_10000;
8271                                 bp->port.advertising[idx] |=
8272                                         (ADVERTISED_10000baseT_Full |
8273                                                 ADVERTISED_FIBRE);
8274                         } else {
8275                                 BNX2X_ERROR("NVRAM config error. "
8276                                     "Invalid link_config 0x%x"
8277                                     "  speed_cap_mask 0x%x\n",
8278                                     link_config,
8279                                     bp->link_params.speed_cap_mask[idx]);
8280                                 return;
8281                         }
8282                         break;
8283
8284                 default:
8285                         BNX2X_ERROR("NVRAM config error. "
8286                                     "BAD link speed link_config 0x%x\n",
8287                                           link_config);
8288                                 bp->link_params.req_line_speed[idx] =
8289                                                         SPEED_AUTO_NEG;
8290                                 bp->port.advertising[idx] =
8291                                                 bp->port.supported[idx];
8292                         break;
8293                 }
8294
8295                 bp->link_params.req_flow_ctrl[idx] = (link_config &
8296                                          PORT_FEATURE_FLOW_CONTROL_MASK);
8297                 if ((bp->link_params.req_flow_ctrl[idx] ==
8298                      BNX2X_FLOW_CTRL_AUTO) &&
8299                     !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
8300                         bp->link_params.req_flow_ctrl[idx] =
8301                                 BNX2X_FLOW_CTRL_NONE;
8302                 }
8303
8304                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl"
8305                                " 0x%x advertising 0x%x\n",
8306                                bp->link_params.req_line_speed[idx],
8307                                bp->link_params.req_duplex[idx],
8308                                bp->link_params.req_flow_ctrl[idx],
8309                                bp->port.advertising[idx]);
8310         }
8311 }
8312
8313 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
8314 {
8315         mac_hi = cpu_to_be16(mac_hi);
8316         mac_lo = cpu_to_be32(mac_lo);
8317         memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
8318         memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
8319 }
8320
8321 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
8322 {
8323         int port = BP_PORT(bp);
8324         u32 config;
8325         u32 ext_phy_type, ext_phy_config;
8326
8327         bp->link_params.bp = bp;
8328         bp->link_params.port = port;
8329
8330         bp->link_params.lane_config =
8331                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
8332
8333         bp->link_params.speed_cap_mask[0] =
8334                 SHMEM_RD(bp,
8335                          dev_info.port_hw_config[port].speed_capability_mask);
8336         bp->link_params.speed_cap_mask[1] =
8337                 SHMEM_RD(bp,
8338                          dev_info.port_hw_config[port].speed_capability_mask2);
8339         bp->port.link_config[0] =
8340                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
8341
8342         bp->port.link_config[1] =
8343                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
8344
8345         bp->link_params.multi_phy_config =
8346                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
8347         /* If the device is capable of WoL, set the default state according
8348          * to the HW
8349          */
8350         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
8351         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
8352                    (config & PORT_FEATURE_WOL_ENABLED));
8353
8354         BNX2X_DEV_INFO("lane_config 0x%08x  "
8355                        "speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
8356                        bp->link_params.lane_config,
8357                        bp->link_params.speed_cap_mask[0],
8358                        bp->port.link_config[0]);
8359
8360         bp->link_params.switch_cfg = (bp->port.link_config[0] &
8361                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
8362         bnx2x_phy_probe(&bp->link_params);
8363         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
8364
8365         bnx2x_link_settings_requested(bp);
8366
8367         /*
8368          * If connected directly, work with the internal PHY, otherwise, work
8369          * with the external PHY
8370          */
8371         ext_phy_config =
8372                 SHMEM_RD(bp,
8373                          dev_info.port_hw_config[port].external_phy_config);
8374         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
8375         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8376                 bp->mdio.prtad = bp->port.phy_addr;
8377
8378         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
8379                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
8380                 bp->mdio.prtad =
8381                         XGXS_EXT_PHY_ADDR(ext_phy_config);
8382 }
8383
8384 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
8385 {
8386         u32 val, val2;
8387         int func = BP_ABS_FUNC(bp);
8388         int port = BP_PORT(bp);
8389
8390         if (BP_NOMCP(bp)) {
8391                 BNX2X_ERROR("warning: random MAC workaround active\n");
8392                 random_ether_addr(bp->dev->dev_addr);
8393         } else if (IS_MF(bp)) {
8394                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
8395                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
8396                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
8397                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
8398                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8399
8400 #ifdef BCM_CNIC
8401                 /* iSCSI NPAR MAC */
8402                 if (IS_MF_SI(bp)) {
8403                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
8404                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
8405                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
8406                                                      iscsi_mac_addr_upper);
8407                                 val = MF_CFG_RD(bp, func_ext_config[func].
8408                                                     iscsi_mac_addr_lower);
8409                                 bnx2x_set_mac_buf(bp->iscsi_mac, val, val2);
8410                         }
8411                 }
8412 #endif
8413         } else {
8414                 /* in SF read MACs from port configuration */
8415                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
8416                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
8417                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8418
8419 #ifdef BCM_CNIC
8420                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
8421                                     iscsi_mac_upper);
8422                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
8423                                    iscsi_mac_lower);
8424                 bnx2x_set_mac_buf(bp->iscsi_mac, val, val2);
8425 #endif
8426         }
8427
8428         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
8429         memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
8430
8431 #ifdef BCM_CNIC
8432         /* Inform the upper layers about FCoE MAC */
8433         if (!CHIP_IS_E1x(bp)) {
8434                 if (IS_MF_SD(bp))
8435                         memcpy(bp->fip_mac, bp->dev->dev_addr,
8436                                sizeof(bp->fip_mac));
8437                 else
8438                         memcpy(bp->fip_mac, bp->iscsi_mac,
8439                                sizeof(bp->fip_mac));
8440         }
8441 #endif
8442 }
8443
8444 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
8445 {
8446         int /*abs*/func = BP_ABS_FUNC(bp);
8447         int vn, port;
8448         u32 val = 0;
8449         int rc = 0;
8450
8451         bnx2x_get_common_hwinfo(bp);
8452
8453         if (CHIP_IS_E1x(bp)) {
8454                 bp->common.int_block = INT_BLOCK_HC;
8455
8456                 bp->igu_dsb_id = DEF_SB_IGU_ID;
8457                 bp->igu_base_sb = 0;
8458                 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
8459                                        NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
8460         } else {
8461                 bp->common.int_block = INT_BLOCK_IGU;
8462                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8463                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8464                         DP(NETIF_MSG_PROBE, "IGU Backward Compatible Mode\n");
8465                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
8466                 } else
8467                         DP(NETIF_MSG_PROBE, "IGU Normal Mode\n");
8468
8469                 bnx2x_get_igu_cam_info(bp);
8470
8471         }
8472         DP(NETIF_MSG_PROBE, "igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n",
8473                              bp->igu_dsb_id, bp->igu_base_sb, bp->igu_sb_cnt);
8474
8475         /*
8476          * Initialize MF configuration
8477          */
8478
8479         bp->mf_ov = 0;
8480         bp->mf_mode = 0;
8481         vn = BP_E1HVN(bp);
8482         port = BP_PORT(bp);
8483
8484         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
8485                 DP(NETIF_MSG_PROBE,
8486                             "shmem2base 0x%x, size %d, mfcfg offset %d\n",
8487                             bp->common.shmem2_base, SHMEM2_RD(bp, size),
8488                             (u32)offsetof(struct shmem2_region, mf_cfg_addr));
8489                 if (SHMEM2_HAS(bp, mf_cfg_addr))
8490                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
8491                 else
8492                         bp->common.mf_cfg_base = bp->common.shmem_base +
8493                                 offsetof(struct shmem_region, func_mb) +
8494                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
8495                 /*
8496                  * get mf configuration:
8497                  * 1. existance of MF configuration
8498                  * 2. MAC address must be legal (check only upper bytes)
8499                  *    for  Switch-Independent mode;
8500                  *    OVLAN must be legal for Switch-Dependent mode
8501                  * 3. SF_MODE configures specific MF mode
8502                  */
8503                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
8504                         /* get mf configuration */
8505                         val = SHMEM_RD(bp,
8506                                        dev_info.shared_feature_config.config);
8507                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
8508
8509                         switch (val) {
8510                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
8511                                 val = MF_CFG_RD(bp, func_mf_config[func].
8512                                                 mac_upper);
8513                                 /* check for legal mac (upper bytes)*/
8514                                 if (val != 0xffff) {
8515                                         bp->mf_mode = MULTI_FUNCTION_SI;
8516                                         bp->mf_config[vn] = MF_CFG_RD(bp,
8517                                                    func_mf_config[func].config);
8518                                 } else
8519                                         DP(NETIF_MSG_PROBE, "illegal MAC "
8520                                                             "address for SI\n");
8521                                 break;
8522                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
8523                                 /* get OV configuration */
8524                                 val = MF_CFG_RD(bp,
8525                                         func_mf_config[FUNC_0].e1hov_tag);
8526                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
8527
8528                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
8529                                         bp->mf_mode = MULTI_FUNCTION_SD;
8530                                         bp->mf_config[vn] = MF_CFG_RD(bp,
8531                                                 func_mf_config[func].config);
8532                                 } else
8533                                         DP(NETIF_MSG_PROBE, "illegal OV for "
8534                                                             "SD\n");
8535                                 break;
8536                         default:
8537                                 /* Unknown configuration: reset mf_config */
8538                                 bp->mf_config[vn] = 0;
8539                                 DP(NETIF_MSG_PROBE, "Unkown MF mode 0x%x\n",
8540                                    val);
8541                         }
8542                 }
8543
8544                 BNX2X_DEV_INFO("%s function mode\n",
8545                                IS_MF(bp) ? "multi" : "single");
8546
8547                 switch (bp->mf_mode) {
8548                 case MULTI_FUNCTION_SD:
8549                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
8550                               FUNC_MF_CFG_E1HOV_TAG_MASK;
8551                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
8552                                 bp->mf_ov = val;
8553                                 BNX2X_DEV_INFO("MF OV for func %d is %d"
8554                                                " (0x%04x)\n", func,
8555                                                bp->mf_ov, bp->mf_ov);
8556                         } else {
8557                                 BNX2X_ERR("No valid MF OV for func %d,"
8558                                           "  aborting\n", func);
8559                                 rc = -EPERM;
8560                         }
8561                         break;
8562                 case MULTI_FUNCTION_SI:
8563                         BNX2X_DEV_INFO("func %d is in MF "
8564                                        "switch-independent mode\n", func);
8565                         break;
8566                 default:
8567                         if (vn) {
8568                                 BNX2X_ERR("VN %d in single function mode,"
8569                                           "  aborting\n", vn);
8570                                 rc = -EPERM;
8571                         }
8572                         break;
8573                 }
8574
8575         }
8576
8577         /* adjust igu_sb_cnt to MF for E1x */
8578         if (CHIP_IS_E1x(bp) && IS_MF(bp))
8579                 bp->igu_sb_cnt /= E1HVN_MAX;
8580
8581         /*
8582          * adjust E2 sb count: to be removed when FW will support
8583          * more then 16 L2 clients
8584          */
8585 #define MAX_L2_CLIENTS                          16
8586         if (CHIP_IS_E2(bp))
8587                 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
8588                                        MAX_L2_CLIENTS / (IS_MF(bp) ? 4 : 1));
8589
8590         if (!BP_NOMCP(bp)) {
8591                 bnx2x_get_port_hwinfo(bp);
8592
8593                 bp->fw_seq =
8594                         (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
8595                          DRV_MSG_SEQ_NUMBER_MASK);
8596                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
8597         }
8598
8599         /* Get MAC addresses */
8600         bnx2x_get_mac_hwinfo(bp);
8601
8602         return rc;
8603 }
8604
8605 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
8606 {
8607         int cnt, i, block_end, rodi;
8608         char vpd_data[BNX2X_VPD_LEN+1];
8609         char str_id_reg[VENDOR_ID_LEN+1];
8610         char str_id_cap[VENDOR_ID_LEN+1];
8611         u8 len;
8612
8613         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
8614         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
8615
8616         if (cnt < BNX2X_VPD_LEN)
8617                 goto out_not_found;
8618
8619         i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
8620                              PCI_VPD_LRDT_RO_DATA);
8621         if (i < 0)
8622                 goto out_not_found;
8623
8624
8625         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
8626                     pci_vpd_lrdt_size(&vpd_data[i]);
8627
8628         i += PCI_VPD_LRDT_TAG_SIZE;
8629
8630         if (block_end > BNX2X_VPD_LEN)
8631                 goto out_not_found;
8632
8633         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8634                                    PCI_VPD_RO_KEYWORD_MFR_ID);
8635         if (rodi < 0)
8636                 goto out_not_found;
8637
8638         len = pci_vpd_info_field_size(&vpd_data[rodi]);
8639
8640         if (len != VENDOR_ID_LEN)
8641                 goto out_not_found;
8642
8643         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8644
8645         /* vendor specific info */
8646         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
8647         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
8648         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
8649             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
8650
8651                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8652                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
8653                 if (rodi >= 0) {
8654                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
8655
8656                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8657
8658                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
8659                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
8660                                 bp->fw_ver[len] = ' ';
8661                         }
8662                 }
8663                 return;
8664         }
8665 out_not_found:
8666         return;
8667 }
8668
8669 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
8670 {
8671         int func;
8672         int timer_interval;
8673         int rc;
8674
8675         /* Disable interrupt handling until HW is initialized */
8676         atomic_set(&bp->intr_sem, 1);
8677         smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
8678
8679         mutex_init(&bp->port.phy_mutex);
8680         mutex_init(&bp->fw_mb_mutex);
8681         spin_lock_init(&bp->stats_lock);
8682 #ifdef BCM_CNIC
8683         mutex_init(&bp->cnic_mutex);
8684 #endif
8685
8686         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
8687         INIT_DELAYED_WORK(&bp->reset_task, bnx2x_reset_task);
8688
8689         rc = bnx2x_get_hwinfo(bp);
8690
8691         if (!rc)
8692                 rc = bnx2x_alloc_mem_bp(bp);
8693
8694         bnx2x_read_fwinfo(bp);
8695
8696         func = BP_FUNC(bp);
8697
8698         /* need to reset chip if undi was active */
8699         if (!BP_NOMCP(bp))
8700                 bnx2x_undi_unload(bp);
8701
8702         if (CHIP_REV_IS_FPGA(bp))
8703                 dev_err(&bp->pdev->dev, "FPGA detected\n");
8704
8705         if (BP_NOMCP(bp) && (func == 0))
8706                 dev_err(&bp->pdev->dev, "MCP disabled, "
8707                                         "must load devices in order!\n");
8708
8709         bp->multi_mode = multi_mode;
8710         bp->int_mode = int_mode;
8711
8712         bp->dev->features |= NETIF_F_GRO;
8713
8714         /* Set TPA flags */
8715         if (disable_tpa) {
8716                 bp->flags &= ~TPA_ENABLE_FLAG;
8717                 bp->dev->features &= ~NETIF_F_LRO;
8718         } else {
8719                 bp->flags |= TPA_ENABLE_FLAG;
8720                 bp->dev->features |= NETIF_F_LRO;
8721         }
8722         bp->disable_tpa = disable_tpa;
8723
8724         if (CHIP_IS_E1(bp))
8725                 bp->dropless_fc = 0;
8726         else
8727                 bp->dropless_fc = dropless_fc;
8728
8729         bp->mrrs = mrrs;
8730
8731         bp->tx_ring_size = MAX_TX_AVAIL;
8732
8733         bp->rx_csum = 1;
8734
8735         /* make sure that the numbers are in the right granularity */
8736         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
8737         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
8738
8739         timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
8740         bp->current_interval = (poll ? poll : timer_interval);
8741
8742         init_timer(&bp->timer);
8743         bp->timer.expires = jiffies + bp->current_interval;
8744         bp->timer.data = (unsigned long) bp;
8745         bp->timer.function = bnx2x_timer;
8746
8747         bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
8748         bnx2x_dcbx_init_params(bp);
8749
8750         return rc;
8751 }
8752
8753
8754 /****************************************************************************
8755 * General service functions
8756 ****************************************************************************/
8757
8758 /* called with rtnl_lock */
8759 static int bnx2x_open(struct net_device *dev)
8760 {
8761         struct bnx2x *bp = netdev_priv(dev);
8762
8763         netif_carrier_off(dev);
8764
8765         bnx2x_set_power_state(bp, PCI_D0);
8766
8767         if (!bnx2x_reset_is_done(bp)) {
8768                 do {
8769                         /* Reset MCP mail box sequence if there is on going
8770                          * recovery
8771                          */
8772                         bp->fw_seq = 0;
8773
8774                         /* If it's the first function to load and reset done
8775                          * is still not cleared it may mean that. We don't
8776                          * check the attention state here because it may have
8777                          * already been cleared by a "common" reset but we
8778                          * shell proceed with "process kill" anyway.
8779                          */
8780                         if ((bnx2x_get_load_cnt(bp) == 0) &&
8781                                 bnx2x_trylock_hw_lock(bp,
8782                                 HW_LOCK_RESOURCE_RESERVED_08) &&
8783                                 (!bnx2x_leader_reset(bp))) {
8784                                 DP(NETIF_MSG_HW, "Recovered in open\n");
8785                                 break;
8786                         }
8787
8788                         bnx2x_set_power_state(bp, PCI_D3hot);
8789
8790                         printk(KERN_ERR"%s: Recovery flow hasn't been properly"
8791                         " completed yet. Try again later. If u still see this"
8792                         " message after a few retries then power cycle is"
8793                         " required.\n", bp->dev->name);
8794
8795                         return -EAGAIN;
8796                 } while (0);
8797         }
8798
8799         bp->recovery_state = BNX2X_RECOVERY_DONE;
8800
8801         return bnx2x_nic_load(bp, LOAD_OPEN);
8802 }
8803
8804 /* called with rtnl_lock */
8805 static int bnx2x_close(struct net_device *dev)
8806 {
8807         struct bnx2x *bp = netdev_priv(dev);
8808
8809         /* Unload the driver, release IRQs */
8810         bnx2x_nic_unload(bp, UNLOAD_CLOSE);
8811         bnx2x_set_power_state(bp, PCI_D3hot);
8812
8813         return 0;
8814 }
8815
8816 /* called with netif_tx_lock from dev_mcast.c */
8817 void bnx2x_set_rx_mode(struct net_device *dev)
8818 {
8819         struct bnx2x *bp = netdev_priv(dev);
8820         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
8821         int port = BP_PORT(bp);
8822
8823         if (bp->state != BNX2X_STATE_OPEN) {
8824                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
8825                 return;
8826         }
8827
8828         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags);
8829
8830         if (dev->flags & IFF_PROMISC)
8831                 rx_mode = BNX2X_RX_MODE_PROMISC;
8832         else if ((dev->flags & IFF_ALLMULTI) ||
8833                  ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
8834                   CHIP_IS_E1(bp)))
8835                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
8836         else { /* some multicasts */
8837                 if (CHIP_IS_E1(bp)) {
8838                         /*
8839                          * set mc list, do not wait as wait implies sleep
8840                          * and set_rx_mode can be invoked from non-sleepable
8841                          * context
8842                          */
8843                         u8 offset = (CHIP_REV_IS_SLOW(bp) ?
8844                                      BNX2X_MAX_EMUL_MULTI*(1 + port) :
8845                                      BNX2X_MAX_MULTICAST*(1 + port));
8846
8847                         bnx2x_set_e1_mc_list(bp, offset);
8848                 } else { /* E1H */
8849                         /* Accept one or more multicasts */
8850                         struct netdev_hw_addr *ha;
8851                         u32 mc_filter[MC_HASH_SIZE];
8852                         u32 crc, bit, regidx;
8853                         int i;
8854
8855                         memset(mc_filter, 0, 4 * MC_HASH_SIZE);
8856
8857                         netdev_for_each_mc_addr(ha, dev) {
8858                                 DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",
8859                                    bnx2x_mc_addr(ha));
8860
8861                                 crc = crc32c_le(0, bnx2x_mc_addr(ha),
8862                                                 ETH_ALEN);
8863                                 bit = (crc >> 24) & 0xff;
8864                                 regidx = bit >> 5;
8865                                 bit &= 0x1f;
8866                                 mc_filter[regidx] |= (1 << bit);
8867                         }
8868
8869                         for (i = 0; i < MC_HASH_SIZE; i++)
8870                                 REG_WR(bp, MC_HASH_OFFSET(bp, i),
8871                                        mc_filter[i]);
8872                 }
8873         }
8874
8875         bp->rx_mode = rx_mode;
8876         bnx2x_set_storm_rx_mode(bp);
8877 }
8878
8879 /* called with rtnl_lock */
8880 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
8881                            int devad, u16 addr)
8882 {
8883         struct bnx2x *bp = netdev_priv(netdev);
8884         u16 value;
8885         int rc;
8886
8887         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
8888            prtad, devad, addr);
8889
8890         /* The HW expects different devad if CL22 is used */
8891         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
8892
8893         bnx2x_acquire_phy_lock(bp);
8894         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
8895         bnx2x_release_phy_lock(bp);
8896         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
8897
8898         if (!rc)
8899                 rc = value;
8900         return rc;
8901 }
8902
8903 /* called with rtnl_lock */
8904 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
8905                             u16 addr, u16 value)
8906 {
8907         struct bnx2x *bp = netdev_priv(netdev);
8908         int rc;
8909
8910         DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
8911                            " value 0x%x\n", prtad, devad, addr, value);
8912
8913         /* The HW expects different devad if CL22 is used */
8914         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
8915
8916         bnx2x_acquire_phy_lock(bp);
8917         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
8918         bnx2x_release_phy_lock(bp);
8919         return rc;
8920 }
8921
8922 /* called with rtnl_lock */
8923 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8924 {
8925         struct bnx2x *bp = netdev_priv(dev);
8926         struct mii_ioctl_data *mdio = if_mii(ifr);
8927
8928         DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
8929            mdio->phy_id, mdio->reg_num, mdio->val_in);
8930
8931         if (!netif_running(dev))
8932                 return -EAGAIN;
8933
8934         return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
8935 }
8936
8937 #ifdef CONFIG_NET_POLL_CONTROLLER
8938 static void poll_bnx2x(struct net_device *dev)
8939 {
8940         struct bnx2x *bp = netdev_priv(dev);
8941
8942         disable_irq(bp->pdev->irq);
8943         bnx2x_interrupt(bp->pdev->irq, dev);
8944         enable_irq(bp->pdev->irq);
8945 }
8946 #endif
8947
8948 static const struct net_device_ops bnx2x_netdev_ops = {
8949         .ndo_open               = bnx2x_open,
8950         .ndo_stop               = bnx2x_close,
8951         .ndo_start_xmit         = bnx2x_start_xmit,
8952         .ndo_select_queue       = bnx2x_select_queue,
8953         .ndo_set_multicast_list = bnx2x_set_rx_mode,
8954         .ndo_set_mac_address    = bnx2x_change_mac_addr,
8955         .ndo_validate_addr      = eth_validate_addr,
8956         .ndo_do_ioctl           = bnx2x_ioctl,
8957         .ndo_change_mtu         = bnx2x_change_mtu,
8958         .ndo_tx_timeout         = bnx2x_tx_timeout,
8959 #ifdef CONFIG_NET_POLL_CONTROLLER
8960         .ndo_poll_controller    = poll_bnx2x,
8961 #endif
8962 };
8963
8964 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
8965                                     struct net_device *dev)
8966 {
8967         struct bnx2x *bp;
8968         int rc;
8969
8970         SET_NETDEV_DEV(dev, &pdev->dev);
8971         bp = netdev_priv(dev);
8972
8973         bp->dev = dev;
8974         bp->pdev = pdev;
8975         bp->flags = 0;
8976         bp->pf_num = PCI_FUNC(pdev->devfn);
8977
8978         rc = pci_enable_device(pdev);
8979         if (rc) {
8980                 dev_err(&bp->pdev->dev,
8981                         "Cannot enable PCI device, aborting\n");
8982                 goto err_out;
8983         }
8984
8985         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
8986                 dev_err(&bp->pdev->dev,
8987                         "Cannot find PCI device base address, aborting\n");
8988                 rc = -ENODEV;
8989                 goto err_out_disable;
8990         }
8991
8992         if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
8993                 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
8994                        " base address, aborting\n");
8995                 rc = -ENODEV;
8996                 goto err_out_disable;
8997         }
8998
8999         if (atomic_read(&pdev->enable_cnt) == 1) {
9000                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9001                 if (rc) {
9002                         dev_err(&bp->pdev->dev,
9003                                 "Cannot obtain PCI resources, aborting\n");
9004                         goto err_out_disable;
9005                 }
9006
9007                 pci_set_master(pdev);
9008                 pci_save_state(pdev);
9009         }
9010
9011         bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9012         if (bp->pm_cap == 0) {
9013                 dev_err(&bp->pdev->dev,
9014                         "Cannot find power management capability, aborting\n");
9015                 rc = -EIO;
9016                 goto err_out_release;
9017         }
9018
9019         bp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9020         if (bp->pcie_cap == 0) {
9021                 dev_err(&bp->pdev->dev,
9022                         "Cannot find PCI Express capability, aborting\n");
9023                 rc = -EIO;
9024                 goto err_out_release;
9025         }
9026
9027         if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) == 0) {
9028                 bp->flags |= USING_DAC_FLAG;
9029                 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)) != 0) {
9030                         dev_err(&bp->pdev->dev, "dma_set_coherent_mask"
9031                                " failed, aborting\n");
9032                         rc = -EIO;
9033                         goto err_out_release;
9034                 }
9035
9036         } else if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
9037                 dev_err(&bp->pdev->dev,
9038                         "System does not support DMA, aborting\n");
9039                 rc = -EIO;
9040                 goto err_out_release;
9041         }
9042
9043         dev->mem_start = pci_resource_start(pdev, 0);
9044         dev->base_addr = dev->mem_start;
9045         dev->mem_end = pci_resource_end(pdev, 0);
9046
9047         dev->irq = pdev->irq;
9048
9049         bp->regview = pci_ioremap_bar(pdev, 0);
9050         if (!bp->regview) {
9051                 dev_err(&bp->pdev->dev,
9052                         "Cannot map register space, aborting\n");
9053                 rc = -ENOMEM;
9054                 goto err_out_release;
9055         }
9056
9057         bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
9058                                         min_t(u64, BNX2X_DB_SIZE(bp),
9059                                               pci_resource_len(pdev, 2)));
9060         if (!bp->doorbells) {
9061                 dev_err(&bp->pdev->dev,
9062                         "Cannot map doorbell space, aborting\n");
9063                 rc = -ENOMEM;
9064                 goto err_out_unmap;
9065         }
9066
9067         bnx2x_set_power_state(bp, PCI_D0);
9068
9069         /* clean indirect addresses */
9070         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
9071                                PCICFG_VENDOR_ID_OFFSET);
9072         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
9073         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
9074         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
9075         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
9076
9077         /* Reset the load counter */
9078         bnx2x_clear_load_cnt(bp);
9079
9080         dev->watchdog_timeo = TX_TIMEOUT;
9081
9082         dev->netdev_ops = &bnx2x_netdev_ops;
9083         bnx2x_set_ethtool_ops(dev);
9084         dev->features |= NETIF_F_SG;
9085         dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
9086         if (bp->flags & USING_DAC_FLAG)
9087                 dev->features |= NETIF_F_HIGHDMA;
9088         dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
9089         dev->features |= NETIF_F_TSO6;
9090         dev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
9091
9092         dev->vlan_features |= NETIF_F_SG;
9093         dev->vlan_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
9094         if (bp->flags & USING_DAC_FLAG)
9095                 dev->vlan_features |= NETIF_F_HIGHDMA;
9096         dev->vlan_features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
9097         dev->vlan_features |= NETIF_F_TSO6;
9098
9099 #ifdef BCM_DCB
9100         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
9101 #endif
9102
9103         /* get_port_hwinfo() will set prtad and mmds properly */
9104         bp->mdio.prtad = MDIO_PRTAD_NONE;
9105         bp->mdio.mmds = 0;
9106         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
9107         bp->mdio.dev = dev;
9108         bp->mdio.mdio_read = bnx2x_mdio_read;
9109         bp->mdio.mdio_write = bnx2x_mdio_write;
9110
9111         return 0;
9112
9113 err_out_unmap:
9114         if (bp->regview) {
9115                 iounmap(bp->regview);
9116                 bp->regview = NULL;
9117         }
9118         if (bp->doorbells) {
9119                 iounmap(bp->doorbells);
9120                 bp->doorbells = NULL;
9121         }
9122
9123 err_out_release:
9124         if (atomic_read(&pdev->enable_cnt) == 1)
9125                 pci_release_regions(pdev);
9126
9127 err_out_disable:
9128         pci_disable_device(pdev);
9129         pci_set_drvdata(pdev, NULL);
9130
9131 err_out:
9132         return rc;
9133 }
9134
9135 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
9136                                                  int *width, int *speed)
9137 {
9138         u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
9139
9140         *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
9141
9142         /* return value of 1=2.5GHz 2=5GHz */
9143         *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
9144 }
9145
9146 static int bnx2x_check_firmware(struct bnx2x *bp)
9147 {
9148         const struct firmware *firmware = bp->firmware;
9149         struct bnx2x_fw_file_hdr *fw_hdr;
9150         struct bnx2x_fw_file_section *sections;
9151         u32 offset, len, num_ops;
9152         u16 *ops_offsets;
9153         int i;
9154         const u8 *fw_ver;
9155
9156         if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
9157                 return -EINVAL;
9158
9159         fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
9160         sections = (struct bnx2x_fw_file_section *)fw_hdr;
9161
9162         /* Make sure none of the offsets and sizes make us read beyond
9163          * the end of the firmware data */
9164         for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
9165                 offset = be32_to_cpu(sections[i].offset);
9166                 len = be32_to_cpu(sections[i].len);
9167                 if (offset + len > firmware->size) {
9168                         dev_err(&bp->pdev->dev,
9169                                 "Section %d length is out of bounds\n", i);
9170                         return -EINVAL;
9171                 }
9172         }
9173
9174         /* Likewise for the init_ops offsets */
9175         offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
9176         ops_offsets = (u16 *)(firmware->data + offset);
9177         num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
9178
9179         for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
9180                 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
9181                         dev_err(&bp->pdev->dev,
9182                                 "Section offset %d is out of bounds\n", i);
9183                         return -EINVAL;
9184                 }
9185         }
9186
9187         /* Check FW version */
9188         offset = be32_to_cpu(fw_hdr->fw_version.offset);
9189         fw_ver = firmware->data + offset;
9190         if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
9191             (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
9192             (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
9193             (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
9194                 dev_err(&bp->pdev->dev,
9195                         "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
9196                        fw_ver[0], fw_ver[1], fw_ver[2],
9197                        fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
9198                        BCM_5710_FW_MINOR_VERSION,
9199                        BCM_5710_FW_REVISION_VERSION,
9200                        BCM_5710_FW_ENGINEERING_VERSION);
9201                 return -EINVAL;
9202         }
9203
9204         return 0;
9205 }
9206
9207 static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
9208 {
9209         const __be32 *source = (const __be32 *)_source;
9210         u32 *target = (u32 *)_target;
9211         u32 i;
9212
9213         for (i = 0; i < n/4; i++)
9214                 target[i] = be32_to_cpu(source[i]);
9215 }
9216
9217 /*
9218    Ops array is stored in the following format:
9219    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
9220  */
9221 static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
9222 {
9223         const __be32 *source = (const __be32 *)_source;
9224         struct raw_op *target = (struct raw_op *)_target;
9225         u32 i, j, tmp;
9226
9227         for (i = 0, j = 0; i < n/8; i++, j += 2) {
9228                 tmp = be32_to_cpu(source[j]);
9229                 target[i].op = (tmp >> 24) & 0xff;
9230                 target[i].offset = tmp & 0xffffff;
9231                 target[i].raw_data = be32_to_cpu(source[j + 1]);
9232         }
9233 }
9234
9235 /**
9236  * IRO array is stored in the following format:
9237  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
9238  */
9239 static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
9240 {
9241         const __be32 *source = (const __be32 *)_source;
9242         struct iro *target = (struct iro *)_target;
9243         u32 i, j, tmp;
9244
9245         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
9246                 target[i].base = be32_to_cpu(source[j]);
9247                 j++;
9248                 tmp = be32_to_cpu(source[j]);
9249                 target[i].m1 = (tmp >> 16) & 0xffff;
9250                 target[i].m2 = tmp & 0xffff;
9251                 j++;
9252                 tmp = be32_to_cpu(source[j]);
9253                 target[i].m3 = (tmp >> 16) & 0xffff;
9254                 target[i].size = tmp & 0xffff;
9255                 j++;
9256         }
9257 }
9258
9259 static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
9260 {
9261         const __be16 *source = (const __be16 *)_source;
9262         u16 *target = (u16 *)_target;
9263         u32 i;
9264
9265         for (i = 0; i < n/2; i++)
9266                 target[i] = be16_to_cpu(source[i]);
9267 }
9268
9269 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
9270 do {                                                                    \
9271         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
9272         bp->arr = kmalloc(len, GFP_KERNEL);                             \
9273         if (!bp->arr) {                                                 \
9274                 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
9275                 goto lbl;                                               \
9276         }                                                               \
9277         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
9278              (u8 *)bp->arr, len);                                       \
9279 } while (0)
9280
9281 int bnx2x_init_firmware(struct bnx2x *bp)
9282 {
9283         const char *fw_file_name;
9284         struct bnx2x_fw_file_hdr *fw_hdr;
9285         int rc;
9286
9287         if (CHIP_IS_E1(bp))
9288                 fw_file_name = FW_FILE_NAME_E1;
9289         else if (CHIP_IS_E1H(bp))
9290                 fw_file_name = FW_FILE_NAME_E1H;
9291         else if (CHIP_IS_E2(bp))
9292                 fw_file_name = FW_FILE_NAME_E2;
9293         else {
9294                 BNX2X_ERR("Unsupported chip revision\n");
9295                 return -EINVAL;
9296         }
9297
9298         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
9299
9300         rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
9301         if (rc) {
9302                 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
9303                 goto request_firmware_exit;
9304         }
9305
9306         rc = bnx2x_check_firmware(bp);
9307         if (rc) {
9308                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
9309                 goto request_firmware_exit;
9310         }
9311
9312         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
9313
9314         /* Initialize the pointers to the init arrays */
9315         /* Blob */
9316         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
9317
9318         /* Opcodes */
9319         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
9320
9321         /* Offsets */
9322         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
9323                             be16_to_cpu_n);
9324
9325         /* STORMs firmware */
9326         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9327                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
9328         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
9329                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
9330         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9331                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
9332         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
9333                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
9334         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9335                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
9336         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
9337                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
9338         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9339                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
9340         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
9341                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
9342         /* IRO */
9343         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
9344
9345         return 0;
9346
9347 iro_alloc_err:
9348         kfree(bp->init_ops_offsets);
9349 init_offsets_alloc_err:
9350         kfree(bp->init_ops);
9351 init_ops_alloc_err:
9352         kfree(bp->init_data);
9353 request_firmware_exit:
9354         release_firmware(bp->firmware);
9355
9356         return rc;
9357 }
9358
9359 static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp, int l2_cid_count)
9360 {
9361         int cid_count = L2_FP_COUNT(l2_cid_count);
9362
9363 #ifdef BCM_CNIC
9364         cid_count += CNIC_CID_MAX;
9365 #endif
9366         return roundup(cid_count, QM_CID_ROUND);
9367 }
9368
9369 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
9370                                     const struct pci_device_id *ent)
9371 {
9372         struct net_device *dev = NULL;
9373         struct bnx2x *bp;
9374         int pcie_width, pcie_speed;
9375         int rc, cid_count;
9376
9377         switch (ent->driver_data) {
9378         case BCM57710:
9379         case BCM57711:
9380         case BCM57711E:
9381                 cid_count = FP_SB_MAX_E1x;
9382                 break;
9383
9384         case BCM57712:
9385         case BCM57712E:
9386                 cid_count = FP_SB_MAX_E2;
9387                 break;
9388
9389         default:
9390                 pr_err("Unknown board_type (%ld), aborting\n",
9391                            ent->driver_data);
9392                 return -ENODEV;
9393         }
9394
9395         cid_count += NONE_ETH_CONTEXT_USE + CNIC_CONTEXT_USE;
9396
9397         /* dev zeroed in init_etherdev */
9398         dev = alloc_etherdev_mq(sizeof(*bp), cid_count);
9399         if (!dev) {
9400                 dev_err(&pdev->dev, "Cannot allocate net device\n");
9401                 return -ENOMEM;
9402         }
9403
9404         bp = netdev_priv(dev);
9405         bp->msg_enable = debug;
9406
9407         pci_set_drvdata(pdev, dev);
9408
9409         bp->l2_cid_count = cid_count;
9410
9411         rc = bnx2x_init_dev(pdev, dev);
9412         if (rc < 0) {
9413                 free_netdev(dev);
9414                 return rc;
9415         }
9416
9417         rc = bnx2x_init_bp(bp);
9418         if (rc)
9419                 goto init_one_exit;
9420
9421         /* calc qm_cid_count */
9422         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp, cid_count);
9423
9424 #ifdef BCM_CNIC
9425         /* disable FCOE L2 queue for E1x*/
9426         if (CHIP_IS_E1x(bp))
9427                 bp->flags |= NO_FCOE_FLAG;
9428
9429 #endif
9430
9431         /* Configure interupt mode: try to enable MSI-X/MSI if
9432          * needed, set bp->num_queues appropriately.
9433          */
9434         bnx2x_set_int_mode(bp);
9435
9436         /* Add all NAPI objects */
9437         bnx2x_add_all_napi(bp);
9438
9439         rc = register_netdev(dev);
9440         if (rc) {
9441                 dev_err(&pdev->dev, "Cannot register net device\n");
9442                 goto init_one_exit;
9443         }
9444
9445 #ifdef BCM_CNIC
9446         if (!NO_FCOE(bp)) {
9447                 /* Add storage MAC address */
9448                 rtnl_lock();
9449                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9450                 rtnl_unlock();
9451         }
9452 #endif
9453
9454         bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
9455
9456         netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
9457                " IRQ %d, ", board_info[ent->driver_data].name,
9458                (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
9459                pcie_width,
9460                ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
9461                  (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
9462                                                 "5GHz (Gen2)" : "2.5GHz",
9463                dev->base_addr, bp->pdev->irq);
9464         pr_cont("node addr %pM\n", dev->dev_addr);
9465
9466         return 0;
9467
9468 init_one_exit:
9469         if (bp->regview)
9470                 iounmap(bp->regview);
9471
9472         if (bp->doorbells)
9473                 iounmap(bp->doorbells);
9474
9475         free_netdev(dev);
9476
9477         if (atomic_read(&pdev->enable_cnt) == 1)
9478                 pci_release_regions(pdev);
9479
9480         pci_disable_device(pdev);
9481         pci_set_drvdata(pdev, NULL);
9482
9483         return rc;
9484 }
9485
9486 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
9487 {
9488         struct net_device *dev = pci_get_drvdata(pdev);
9489         struct bnx2x *bp;
9490
9491         if (!dev) {
9492                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
9493                 return;
9494         }
9495         bp = netdev_priv(dev);
9496
9497 #ifdef BCM_CNIC
9498         /* Delete storage MAC address */
9499         if (!NO_FCOE(bp)) {
9500                 rtnl_lock();
9501                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9502                 rtnl_unlock();
9503         }
9504 #endif
9505
9506         unregister_netdev(dev);
9507
9508         /* Delete all NAPI objects */
9509         bnx2x_del_all_napi(bp);
9510
9511         /* Power on: we can't let PCI layer write to us while we are in D3 */
9512         bnx2x_set_power_state(bp, PCI_D0);
9513
9514         /* Disable MSI/MSI-X */
9515         bnx2x_disable_msi(bp);
9516
9517         /* Power off */
9518         bnx2x_set_power_state(bp, PCI_D3hot);
9519
9520         /* Make sure RESET task is not scheduled before continuing */
9521         cancel_delayed_work_sync(&bp->reset_task);
9522
9523         if (bp->regview)
9524                 iounmap(bp->regview);
9525
9526         if (bp->doorbells)
9527                 iounmap(bp->doorbells);
9528
9529         bnx2x_free_mem_bp(bp);
9530
9531         free_netdev(dev);
9532
9533         if (atomic_read(&pdev->enable_cnt) == 1)
9534                 pci_release_regions(pdev);
9535
9536         pci_disable_device(pdev);
9537         pci_set_drvdata(pdev, NULL);
9538 }
9539
9540 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
9541 {
9542         int i;
9543
9544         bp->state = BNX2X_STATE_ERROR;
9545
9546         bp->rx_mode = BNX2X_RX_MODE_NONE;
9547
9548         bnx2x_netif_stop(bp, 0);
9549         netif_carrier_off(bp->dev);
9550
9551         del_timer_sync(&bp->timer);
9552         bp->stats_state = STATS_STATE_DISABLED;
9553         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
9554
9555         /* Release IRQs */
9556         bnx2x_free_irq(bp);
9557
9558         /* Free SKBs, SGEs, TPA pool and driver internals */
9559         bnx2x_free_skbs(bp);
9560
9561         for_each_rx_queue(bp, i)
9562                 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
9563
9564         bnx2x_free_mem(bp);
9565
9566         bp->state = BNX2X_STATE_CLOSED;
9567
9568         return 0;
9569 }
9570
9571 static void bnx2x_eeh_recover(struct bnx2x *bp)
9572 {
9573         u32 val;
9574
9575         mutex_init(&bp->port.phy_mutex);
9576
9577         bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9578         bp->link_params.shmem_base = bp->common.shmem_base;
9579         BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
9580
9581         if (!bp->common.shmem_base ||
9582             (bp->common.shmem_base < 0xA0000) ||
9583             (bp->common.shmem_base >= 0xC0000)) {
9584                 BNX2X_DEV_INFO("MCP not active\n");
9585                 bp->flags |= NO_MCP_FLAG;
9586                 return;
9587         }
9588
9589         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9590         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9591                 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9592                 BNX2X_ERR("BAD MCP validity signature\n");
9593
9594         if (!BP_NOMCP(bp)) {
9595                 bp->fw_seq =
9596                     (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9597                     DRV_MSG_SEQ_NUMBER_MASK);
9598                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9599         }
9600 }
9601
9602 /**
9603  * bnx2x_io_error_detected - called when PCI error is detected
9604  * @pdev: Pointer to PCI device
9605  * @state: The current pci connection state
9606  *
9607  * This function is called after a PCI bus error affecting
9608  * this device has been detected.
9609  */
9610 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
9611                                                 pci_channel_state_t state)
9612 {
9613         struct net_device *dev = pci_get_drvdata(pdev);
9614         struct bnx2x *bp = netdev_priv(dev);
9615
9616         rtnl_lock();
9617
9618         netif_device_detach(dev);
9619
9620         if (state == pci_channel_io_perm_failure) {
9621                 rtnl_unlock();
9622                 return PCI_ERS_RESULT_DISCONNECT;
9623         }
9624
9625         if (netif_running(dev))
9626                 bnx2x_eeh_nic_unload(bp);
9627
9628         pci_disable_device(pdev);
9629
9630         rtnl_unlock();
9631
9632         /* Request a slot reset */
9633         return PCI_ERS_RESULT_NEED_RESET;
9634 }
9635
9636 /**
9637  * bnx2x_io_slot_reset - called after the PCI bus has been reset
9638  * @pdev: Pointer to PCI device
9639  *
9640  * Restart the card from scratch, as if from a cold-boot.
9641  */
9642 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
9643 {
9644         struct net_device *dev = pci_get_drvdata(pdev);
9645         struct bnx2x *bp = netdev_priv(dev);
9646
9647         rtnl_lock();
9648
9649         if (pci_enable_device(pdev)) {
9650                 dev_err(&pdev->dev,
9651                         "Cannot re-enable PCI device after reset\n");
9652                 rtnl_unlock();
9653                 return PCI_ERS_RESULT_DISCONNECT;
9654         }
9655
9656         pci_set_master(pdev);
9657         pci_restore_state(pdev);
9658
9659         if (netif_running(dev))
9660                 bnx2x_set_power_state(bp, PCI_D0);
9661
9662         rtnl_unlock();
9663
9664         return PCI_ERS_RESULT_RECOVERED;
9665 }
9666
9667 /**
9668  * bnx2x_io_resume - called when traffic can start flowing again
9669  * @pdev: Pointer to PCI device
9670  *
9671  * This callback is called when the error recovery driver tells us that
9672  * its OK to resume normal operation.
9673  */
9674 static void bnx2x_io_resume(struct pci_dev *pdev)
9675 {
9676         struct net_device *dev = pci_get_drvdata(pdev);
9677         struct bnx2x *bp = netdev_priv(dev);
9678
9679         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
9680                 printk(KERN_ERR "Handling parity error recovery. "
9681                                 "Try again later\n");
9682                 return;
9683         }
9684
9685         rtnl_lock();
9686
9687         bnx2x_eeh_recover(bp);
9688
9689         if (netif_running(dev))
9690                 bnx2x_nic_load(bp, LOAD_NORMAL);
9691
9692         netif_device_attach(dev);
9693
9694         rtnl_unlock();
9695 }
9696
9697 static struct pci_error_handlers bnx2x_err_handler = {
9698         .error_detected = bnx2x_io_error_detected,
9699         .slot_reset     = bnx2x_io_slot_reset,
9700         .resume         = bnx2x_io_resume,
9701 };
9702
9703 static struct pci_driver bnx2x_pci_driver = {
9704         .name        = DRV_MODULE_NAME,
9705         .id_table    = bnx2x_pci_tbl,
9706         .probe       = bnx2x_init_one,
9707         .remove      = __devexit_p(bnx2x_remove_one),
9708         .suspend     = bnx2x_suspend,
9709         .resume      = bnx2x_resume,
9710         .err_handler = &bnx2x_err_handler,
9711 };
9712
9713 static int __init bnx2x_init(void)
9714 {
9715         int ret;
9716
9717         pr_info("%s", version);
9718
9719         bnx2x_wq = create_singlethread_workqueue("bnx2x");
9720         if (bnx2x_wq == NULL) {
9721                 pr_err("Cannot create workqueue\n");
9722                 return -ENOMEM;
9723         }
9724
9725         ret = pci_register_driver(&bnx2x_pci_driver);
9726         if (ret) {
9727                 pr_err("Cannot register driver\n");
9728                 destroy_workqueue(bnx2x_wq);
9729         }
9730         return ret;
9731 }
9732
9733 static void __exit bnx2x_cleanup(void)
9734 {
9735         pci_unregister_driver(&bnx2x_pci_driver);
9736
9737         destroy_workqueue(bnx2x_wq);
9738 }
9739
9740 module_init(bnx2x_init);
9741 module_exit(bnx2x_cleanup);
9742
9743 #ifdef BCM_CNIC
9744
9745 /* count denotes the number of new completions we have seen */
9746 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
9747 {
9748         struct eth_spe *spe;
9749
9750 #ifdef BNX2X_STOP_ON_ERROR
9751         if (unlikely(bp->panic))
9752                 return;
9753 #endif
9754
9755         spin_lock_bh(&bp->spq_lock);
9756         BUG_ON(bp->cnic_spq_pending < count);
9757         bp->cnic_spq_pending -= count;
9758
9759
9760         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
9761                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
9762                                 & SPE_HDR_CONN_TYPE) >>
9763                                 SPE_HDR_CONN_TYPE_SHIFT;
9764
9765                 /* Set validation for iSCSI L2 client before sending SETUP
9766                  *  ramrod
9767                  */
9768                 if (type == ETH_CONNECTION_TYPE) {
9769                         u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->
9770                                              hdr.conn_and_cmd_data) >>
9771                                 SPE_HDR_CMD_ID_SHIFT) & 0xff;
9772
9773                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
9774                                 bnx2x_set_ctx_validation(&bp->context.
9775                                                 vcxt[BNX2X_ISCSI_ETH_CID].eth,
9776                                         HW_CID(bp, BNX2X_ISCSI_ETH_CID));
9777                 }
9778
9779                 /* There may be not more than 8 L2 and COMMON SPEs and not more
9780                  * than 8 L5 SPEs in the air.
9781                  */
9782                 if ((type == NONE_CONNECTION_TYPE) ||
9783                     (type == ETH_CONNECTION_TYPE)) {
9784                         if (!atomic_read(&bp->spq_left))
9785                                 break;
9786                         else
9787                                 atomic_dec(&bp->spq_left);
9788                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
9789                            (type == FCOE_CONNECTION_TYPE)) {
9790                         if (bp->cnic_spq_pending >=
9791                             bp->cnic_eth_dev.max_kwqe_pending)
9792                                 break;
9793                         else
9794                                 bp->cnic_spq_pending++;
9795                 } else {
9796                         BNX2X_ERR("Unknown SPE type: %d\n", type);
9797                         bnx2x_panic();
9798                         break;
9799                 }
9800
9801                 spe = bnx2x_sp_get_next(bp);
9802                 *spe = *bp->cnic_kwq_cons;
9803
9804                 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
9805                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
9806
9807                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
9808                         bp->cnic_kwq_cons = bp->cnic_kwq;
9809                 else
9810                         bp->cnic_kwq_cons++;
9811         }
9812         bnx2x_sp_prod_update(bp);
9813         spin_unlock_bh(&bp->spq_lock);
9814 }
9815
9816 static int bnx2x_cnic_sp_queue(struct net_device *dev,
9817                                struct kwqe_16 *kwqes[], u32 count)
9818 {
9819         struct bnx2x *bp = netdev_priv(dev);
9820         int i;
9821
9822 #ifdef BNX2X_STOP_ON_ERROR
9823         if (unlikely(bp->panic))
9824                 return -EIO;
9825 #endif
9826
9827         spin_lock_bh(&bp->spq_lock);
9828
9829         for (i = 0; i < count; i++) {
9830                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
9831
9832                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
9833                         break;
9834
9835                 *bp->cnic_kwq_prod = *spe;
9836
9837                 bp->cnic_kwq_pending++;
9838
9839                 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
9840                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
9841                    spe->data.update_data_addr.hi,
9842                    spe->data.update_data_addr.lo,
9843                    bp->cnic_kwq_pending);
9844
9845                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
9846                         bp->cnic_kwq_prod = bp->cnic_kwq;
9847                 else
9848                         bp->cnic_kwq_prod++;
9849         }
9850
9851         spin_unlock_bh(&bp->spq_lock);
9852
9853         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
9854                 bnx2x_cnic_sp_post(bp, 0);
9855
9856         return i;
9857 }
9858
9859 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
9860 {
9861         struct cnic_ops *c_ops;
9862         int rc = 0;
9863
9864         mutex_lock(&bp->cnic_mutex);
9865         c_ops = bp->cnic_ops;
9866         if (c_ops)
9867                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
9868         mutex_unlock(&bp->cnic_mutex);
9869
9870         return rc;
9871 }
9872
9873 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
9874 {
9875         struct cnic_ops *c_ops;
9876         int rc = 0;
9877
9878         rcu_read_lock();
9879         c_ops = rcu_dereference(bp->cnic_ops);
9880         if (c_ops)
9881                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
9882         rcu_read_unlock();
9883
9884         return rc;
9885 }
9886
9887 /*
9888  * for commands that have no data
9889  */
9890 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
9891 {
9892         struct cnic_ctl_info ctl = {0};
9893
9894         ctl.cmd = cmd;
9895
9896         return bnx2x_cnic_ctl_send(bp, &ctl);
9897 }
9898
9899 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid)
9900 {
9901         struct cnic_ctl_info ctl;
9902
9903         /* first we tell CNIC and only then we count this as a completion */
9904         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
9905         ctl.data.comp.cid = cid;
9906
9907         bnx2x_cnic_ctl_send_bh(bp, &ctl);
9908         bnx2x_cnic_sp_post(bp, 0);
9909 }
9910
9911 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
9912 {
9913         struct bnx2x *bp = netdev_priv(dev);
9914         int rc = 0;
9915
9916         switch (ctl->cmd) {
9917         case DRV_CTL_CTXTBL_WR_CMD: {
9918                 u32 index = ctl->data.io.offset;
9919                 dma_addr_t addr = ctl->data.io.dma_addr;
9920
9921                 bnx2x_ilt_wr(bp, index, addr);
9922                 break;
9923         }
9924
9925         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
9926                 int count = ctl->data.credit.credit_count;
9927
9928                 bnx2x_cnic_sp_post(bp, count);
9929                 break;
9930         }
9931
9932         /* rtnl_lock is held.  */
9933         case DRV_CTL_START_L2_CMD: {
9934                 u32 cli = ctl->data.ring.client_id;
9935
9936                 /* Clear FCoE FIP and ALL ENODE MACs addresses first */
9937                 bnx2x_del_fcoe_eth_macs(bp);
9938
9939                 /* Set iSCSI MAC address */
9940                 bnx2x_set_iscsi_eth_mac_addr(bp, 1);
9941
9942                 mmiowb();
9943                 barrier();
9944
9945                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
9946                  * because it's the only way for UIO Client to accept
9947                  * multicasts (in non-promiscuous mode only one Client per
9948                  * function will receive multicast packets (leading in our
9949                  * case).
9950                  */
9951                 bnx2x_rxq_set_mac_filters(bp, cli,
9952                         BNX2X_ACCEPT_UNICAST |
9953                         BNX2X_ACCEPT_BROADCAST |
9954                         BNX2X_ACCEPT_ALL_MULTICAST);
9955                 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
9956
9957                 break;
9958         }
9959
9960         /* rtnl_lock is held.  */
9961         case DRV_CTL_STOP_L2_CMD: {
9962                 u32 cli = ctl->data.ring.client_id;
9963
9964                 /* Stop accepting on iSCSI L2 ring */
9965                 bnx2x_rxq_set_mac_filters(bp, cli, BNX2X_ACCEPT_NONE);
9966                 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
9967
9968                 mmiowb();
9969                 barrier();
9970
9971                 /* Unset iSCSI L2 MAC */
9972                 bnx2x_set_iscsi_eth_mac_addr(bp, 0);
9973                 break;
9974         }
9975         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
9976                 int count = ctl->data.credit.credit_count;
9977
9978                 smp_mb__before_atomic_inc();
9979                 atomic_add(count, &bp->spq_left);
9980                 smp_mb__after_atomic_inc();
9981                 break;
9982         }
9983
9984         default:
9985                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
9986                 rc = -EINVAL;
9987         }
9988
9989         return rc;
9990 }
9991
9992 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
9993 {
9994         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
9995
9996         if (bp->flags & USING_MSIX_FLAG) {
9997                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
9998                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
9999                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
10000         } else {
10001                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
10002                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
10003         }
10004         if (CHIP_IS_E2(bp))
10005                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
10006         else
10007                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
10008
10009         cp->irq_arr[0].status_blk_num = CNIC_SB_ID(bp);
10010         cp->irq_arr[0].status_blk_num2 = CNIC_IGU_SB_ID(bp);
10011         cp->irq_arr[1].status_blk = bp->def_status_blk;
10012         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
10013         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
10014
10015         cp->num_irq = 2;
10016 }
10017
10018 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
10019                                void *data)
10020 {
10021         struct bnx2x *bp = netdev_priv(dev);
10022         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10023
10024         if (ops == NULL)
10025                 return -EINVAL;
10026
10027         if (atomic_read(&bp->intr_sem) != 0)
10028                 return -EBUSY;
10029
10030         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
10031         if (!bp->cnic_kwq)
10032                 return -ENOMEM;
10033
10034         bp->cnic_kwq_cons = bp->cnic_kwq;
10035         bp->cnic_kwq_prod = bp->cnic_kwq;
10036         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
10037
10038         bp->cnic_spq_pending = 0;
10039         bp->cnic_kwq_pending = 0;
10040
10041         bp->cnic_data = data;
10042
10043         cp->num_irq = 0;
10044         cp->drv_state = CNIC_DRV_STATE_REGD;
10045         cp->iro_arr = bp->iro_arr;
10046
10047         bnx2x_setup_cnic_irq_info(bp);
10048
10049         rcu_assign_pointer(bp->cnic_ops, ops);
10050
10051         return 0;
10052 }
10053
10054 static int bnx2x_unregister_cnic(struct net_device *dev)
10055 {
10056         struct bnx2x *bp = netdev_priv(dev);
10057         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10058
10059         mutex_lock(&bp->cnic_mutex);
10060         cp->drv_state = 0;
10061         rcu_assign_pointer(bp->cnic_ops, NULL);
10062         mutex_unlock(&bp->cnic_mutex);
10063         synchronize_rcu();
10064         kfree(bp->cnic_kwq);
10065         bp->cnic_kwq = NULL;
10066
10067         return 0;
10068 }
10069
10070 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
10071 {
10072         struct bnx2x *bp = netdev_priv(dev);
10073         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10074
10075         cp->drv_owner = THIS_MODULE;
10076         cp->chip_id = CHIP_ID(bp);
10077         cp->pdev = bp->pdev;
10078         cp->io_base = bp->regview;
10079         cp->io_base2 = bp->doorbells;
10080         cp->max_kwqe_pending = 8;
10081         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
10082         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
10083                              bnx2x_cid_ilt_lines(bp);
10084         cp->ctx_tbl_len = CNIC_ILT_LINES;
10085         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
10086         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
10087         cp->drv_ctl = bnx2x_drv_ctl;
10088         cp->drv_register_cnic = bnx2x_register_cnic;
10089         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
10090         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
10091         cp->iscsi_l2_client_id = BNX2X_ISCSI_ETH_CL_ID +
10092                 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
10093         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
10094
10095         DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
10096                          "starting cid %d\n",
10097            cp->ctx_blk_size,
10098            cp->ctx_tbl_offset,
10099            cp->ctx_tbl_len,
10100            cp->starting_cid);
10101         return cp;
10102 }
10103 EXPORT_SYMBOL(bnx2x_cnic_probe);
10104
10105 #endif /* BCM_CNIC */
10106