2 * Copyright (C) 1999 - 2010 Intel Corporation.
3 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
5 * This code was derived from the Intel e1000e Linux driver.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26 #include <linux/mii.h>
27 #include <linux/delay.h>
28 #include <linux/pci.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/vmalloc.h>
36 * pch_gbe_regs_mac_adr - Structure holding values of mac address registers
37 * @high Denotes the 1st to 4th byte from the initial of MAC address
38 * @low Denotes the 5th to 6th byte from the initial of MAC address
40 struct pch_gbe_regs_mac_adr {
45 * pch_udc_regs - Structure holding values of MAC registers
71 struct pch_gbe_regs_mac_adr mac_adr[16];
100 /* Interrupt Status */
101 /* Interrupt Status Hold */
102 /* Interrupt Enable */
103 #define PCH_GBE_INT_RX_DMA_CMPLT 0x00000001 /* Receive DMA Transfer Complete */
104 #define PCH_GBE_INT_RX_VALID 0x00000002 /* MAC Normal Receive Complete */
105 #define PCH_GBE_INT_RX_FRAME_ERR 0x00000004 /* Receive frame error */
106 #define PCH_GBE_INT_RX_FIFO_ERR 0x00000008 /* Receive FIFO Overflow */
107 #define PCH_GBE_INT_RX_DMA_ERR 0x00000010 /* Receive DMA Transfer Error */
108 #define PCH_GBE_INT_RX_DSC_EMP 0x00000020 /* Receive Descriptor Empty */
109 #define PCH_GBE_INT_TX_CMPLT 0x00000100 /* MAC Transmission Complete */
110 #define PCH_GBE_INT_TX_DMA_CMPLT 0x00000200 /* DMA Transfer Complete */
111 #define PCH_GBE_INT_TX_FIFO_ERR 0x00000400 /* Transmission FIFO underflow. */
112 #define PCH_GBE_INT_TX_DMA_ERR 0x00000800 /* Transmission DMA Error */
113 #define PCH_GBE_INT_PAUSE_CMPLT 0x00001000 /* Pause Transmission complete */
114 #define PCH_GBE_INT_MIIM_CMPLT 0x00010000 /* MIIM I/F Read completion */
115 #define PCH_GBE_INT_PHY_INT 0x00100000 /* Interruption from PHY */
116 #define PCH_GBE_INT_WOL_DET 0x01000000 /* Wake On LAN Event detection. */
117 #define PCH_GBE_INT_TCPIP_ERR 0x10000000 /* TCP/IP Accelerator Error */
120 #define PCH_GBE_MODE_MII_ETHER 0x00000000 /* GIGA Ethernet Mode [MII] */
121 #define PCH_GBE_MODE_GMII_ETHER 0x80000000 /* GIGA Ethernet Mode [GMII] */
122 #define PCH_GBE_MODE_HALF_DUPLEX 0x00000000 /* Duplex Mode [half duplex] */
123 #define PCH_GBE_MODE_FULL_DUPLEX 0x40000000 /* Duplex Mode [full duplex] */
124 #define PCH_GBE_MODE_FR_BST 0x04000000 /* Frame bursting is done */
127 #define PCH_GBE_ALL_RST 0x80000000 /* All reset */
128 #define PCH_GBE_TX_RST 0x40000000 /* TX MAC, TX FIFO, TX DMA reset */
129 #define PCH_GBE_RX_RST 0x04000000 /* RX MAC, RX FIFO, RX DMA reset */
131 /* TCP/IP Accelerator Control */
132 #define PCH_GBE_EX_LIST_EN 0x00000008 /* External List Enable */
133 #define PCH_GBE_RX_TCPIPACC_OFF 0x00000004 /* RX TCP/IP ACC Disabled */
134 #define PCH_GBE_TX_TCPIPACC_EN 0x00000002 /* TX TCP/IP ACC Enable */
135 #define PCH_GBE_RX_TCPIPACC_EN 0x00000001 /* RX TCP/IP ACC Enable */
138 #define PCH_GBE_MRE_MAC_RX_EN 0x00000001 /* MAC Receive Enable */
140 /* RX Flow Control */
141 #define PCH_GBE_FL_CTRL_EN 0x80000000 /* Pause packet is enabled */
143 /* Pause Packet Request */
144 #define PCH_GBE_PS_PKT_RQ 0x80000000 /* Pause packet Request */
147 #define PCH_GBE_ADD_FIL_EN 0x80000000 /* Address Filtering Enable */
148 /* Multicast Filtering Enable */
149 #define PCH_GBE_MLT_FIL_EN 0x40000000
150 /* Receive Almost Empty Threshold */
151 #define PCH_GBE_RH_ALM_EMP_4 0x00000000 /* 4 words */
152 #define PCH_GBE_RH_ALM_EMP_8 0x00004000 /* 8 words */
153 #define PCH_GBE_RH_ALM_EMP_16 0x00008000 /* 16 words */
154 #define PCH_GBE_RH_ALM_EMP_32 0x0000C000 /* 32 words */
155 /* Receive Almost Full Threshold */
156 #define PCH_GBE_RH_ALM_FULL_4 0x00000000 /* 4 words */
157 #define PCH_GBE_RH_ALM_FULL_8 0x00001000 /* 8 words */
158 #define PCH_GBE_RH_ALM_FULL_16 0x00002000 /* 16 words */
159 #define PCH_GBE_RH_ALM_FULL_32 0x00003000 /* 32 words */
160 /* RX FIFO Read Triger Threshold */
161 #define PCH_GBE_RH_RD_TRG_4 0x00000000 /* 4 words */
162 #define PCH_GBE_RH_RD_TRG_8 0x00000200 /* 8 words */
163 #define PCH_GBE_RH_RD_TRG_16 0x00000400 /* 16 words */
164 #define PCH_GBE_RH_RD_TRG_32 0x00000600 /* 32 words */
165 #define PCH_GBE_RH_RD_TRG_64 0x00000800 /* 64 words */
166 #define PCH_GBE_RH_RD_TRG_128 0x00000A00 /* 128 words */
167 #define PCH_GBE_RH_RD_TRG_256 0x00000C00 /* 256 words */
168 #define PCH_GBE_RH_RD_TRG_512 0x00000E00 /* 512 words */
170 /* Receive Descriptor bit definitions */
171 #define PCH_GBE_RXD_ACC_STAT_BCAST 0x00000400
172 #define PCH_GBE_RXD_ACC_STAT_MCAST 0x00000200
173 #define PCH_GBE_RXD_ACC_STAT_UCAST 0x00000100
174 #define PCH_GBE_RXD_ACC_STAT_TCPIPOK 0x000000C0
175 #define PCH_GBE_RXD_ACC_STAT_IPOK 0x00000080
176 #define PCH_GBE_RXD_ACC_STAT_TCPOK 0x00000040
177 #define PCH_GBE_RXD_ACC_STAT_IP6ERR 0x00000020
178 #define PCH_GBE_RXD_ACC_STAT_OFLIST 0x00000010
179 #define PCH_GBE_RXD_ACC_STAT_TYPEIP 0x00000008
180 #define PCH_GBE_RXD_ACC_STAT_MACL 0x00000004
181 #define PCH_GBE_RXD_ACC_STAT_PPPOE 0x00000002
182 #define PCH_GBE_RXD_ACC_STAT_VTAGT 0x00000001
183 #define PCH_GBE_RXD_GMAC_STAT_PAUSE 0x0200
184 #define PCH_GBE_RXD_GMAC_STAT_MARBR 0x0100
185 #define PCH_GBE_RXD_GMAC_STAT_MARMLT 0x0080
186 #define PCH_GBE_RXD_GMAC_STAT_MARIND 0x0040
187 #define PCH_GBE_RXD_GMAC_STAT_MARNOTMT 0x0020
188 #define PCH_GBE_RXD_GMAC_STAT_TLONG 0x0010
189 #define PCH_GBE_RXD_GMAC_STAT_TSHRT 0x0008
190 #define PCH_GBE_RXD_GMAC_STAT_NOTOCTAL 0x0004
191 #define PCH_GBE_RXD_GMAC_STAT_NBLERR 0x0002
192 #define PCH_GBE_RXD_GMAC_STAT_CRCERR 0x0001
194 /* Transmit Descriptor bit definitions */
195 #define PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF 0x0008
196 #define PCH_GBE_TXD_CTRL_ITAG 0x0004
197 #define PCH_GBE_TXD_CTRL_ICRC 0x0002
198 #define PCH_GBE_TXD_CTRL_APAD 0x0001
199 #define PCH_GBE_TXD_WORDS_SHIFT 2
200 #define PCH_GBE_TXD_GMAC_STAT_CMPLT 0x2000
201 #define PCH_GBE_TXD_GMAC_STAT_ABT 0x1000
202 #define PCH_GBE_TXD_GMAC_STAT_EXCOL 0x0800
203 #define PCH_GBE_TXD_GMAC_STAT_SNGCOL 0x0400
204 #define PCH_GBE_TXD_GMAC_STAT_MLTCOL 0x0200
205 #define PCH_GBE_TXD_GMAC_STAT_CRSER 0x0100
206 #define PCH_GBE_TXD_GMAC_STAT_TLNG 0x0080
207 #define PCH_GBE_TXD_GMAC_STAT_TSHRT 0x0040
208 #define PCH_GBE_TXD_GMAC_STAT_LTCOL 0x0020
209 #define PCH_GBE_TXD_GMAC_STAT_TFUNDFLW 0x0010
210 #define PCH_GBE_TXD_GMAC_STAT_RTYCNT_MASK 0x000F
213 #define PCH_GBE_TM_NO_RTRY 0x80000000 /* No Retransmission */
214 #define PCH_GBE_TM_LONG_PKT 0x40000000 /* Long Packt TX Enable */
215 #define PCH_GBE_TM_ST_AND_FD 0x20000000 /* Stare and Forward */
216 #define PCH_GBE_TM_SHORT_PKT 0x10000000 /* Short Packet TX Enable */
217 #define PCH_GBE_TM_LTCOL_RETX 0x08000000 /* Retransmission at Late Collision */
218 /* Frame Start Threshold */
219 #define PCH_GBE_TM_TH_TX_STRT_4 0x00000000 /* 4 words */
220 #define PCH_GBE_TM_TH_TX_STRT_8 0x00004000 /* 8 words */
221 #define PCH_GBE_TM_TH_TX_STRT_16 0x00008000 /* 16 words */
222 #define PCH_GBE_TM_TH_TX_STRT_32 0x0000C000 /* 32 words */
223 /* Transmit Almost Empty Threshold */
224 #define PCH_GBE_TM_TH_ALM_EMP_4 0x00000000 /* 4 words */
225 #define PCH_GBE_TM_TH_ALM_EMP_8 0x00000800 /* 8 words */
226 #define PCH_GBE_TM_TH_ALM_EMP_16 0x00001000 /* 16 words */
227 #define PCH_GBE_TM_TH_ALM_EMP_32 0x00001800 /* 32 words */
228 #define PCH_GBE_TM_TH_ALM_EMP_64 0x00002000 /* 64 words */
229 #define PCH_GBE_TM_TH_ALM_EMP_128 0x00002800 /* 128 words */
230 #define PCH_GBE_TM_TH_ALM_EMP_256 0x00003000 /* 256 words */
231 #define PCH_GBE_TM_TH_ALM_EMP_512 0x00003800 /* 512 words */
232 /* Transmit Almost Full Threshold */
233 #define PCH_GBE_TM_TH_ALM_FULL_4 0x00000000 /* 4 words */
234 #define PCH_GBE_TM_TH_ALM_FULL_8 0x00000200 /* 8 words */
235 #define PCH_GBE_TM_TH_ALM_FULL_16 0x00000400 /* 16 words */
236 #define PCH_GBE_TM_TH_ALM_FULL_32 0x00000600 /* 32 words */
239 #define PCH_GBE_RF_ALM_FULL 0x80000000 /* RX FIFO is almost full. */
240 #define PCH_GBE_RF_ALM_EMP 0x40000000 /* RX FIFO is almost empty. */
241 #define PCH_GBE_RF_RD_TRG 0x20000000 /* Become more than RH_RD_TRG. */
242 #define PCH_GBE_RF_STRWD 0x1FFE0000 /* The word count of RX FIFO. */
243 #define PCH_GBE_RF_RCVING 0x00010000 /* Stored in RX FIFO. */
245 /* MAC Address Mask */
246 #define PCH_GBE_BUSY 0x80000000
249 #define PCH_GBE_MIIM_OPER_WRITE 0x04000000
250 #define PCH_GBE_MIIM_OPER_READ 0x00000000
251 #define PCH_GBE_MIIM_OPER_READY 0x04000000
252 #define PCH_GBE_MIIM_PHY_ADDR_SHIFT 21
253 #define PCH_GBE_MIIM_REG_ADDR_SHIFT 16
256 #define PCH_GBE_LINK_UP 0x80000008
257 #define PCH_GBE_RXC_SPEED_MSK 0x00000006
258 #define PCH_GBE_RXC_SPEED_2_5M 0x00000000 /* 2.5MHz */
259 #define PCH_GBE_RXC_SPEED_25M 0x00000002 /* 25MHz */
260 #define PCH_GBE_RXC_SPEED_125M 0x00000004 /* 100MHz */
261 #define PCH_GBE_DUPLEX_FULL 0x00000001
264 #define PCH_GBE_CRS_SEL 0x00000010
265 #define PCH_GBE_RGMII_RATE_125M 0x00000000
266 #define PCH_GBE_RGMII_RATE_25M 0x00000008
267 #define PCH_GBE_RGMII_RATE_2_5M 0x0000000C
268 #define PCH_GBE_RGMII_MODE_GMII 0x00000000
269 #define PCH_GBE_RGMII_MODE_RGMII 0x00000002
270 #define PCH_GBE_CHIP_TYPE_EXTERNAL 0x00000000
271 #define PCH_GBE_CHIP_TYPE_INTERNAL 0x00000001
274 #define PCH_GBE_RX_DMA_EN 0x00000002 /* Enables Receive DMA */
275 #define PCH_GBE_TX_DMA_EN 0x00000001 /* Enables Transmission DMA */
277 /* Wake On LAN Status */
278 #define PCH_GBE_WLS_BR 0x00000008 /* Broadcas Address */
279 #define PCH_GBE_WLS_MLT 0x00000004 /* Multicast Address */
281 /* The Frame registered in Address Recognizer */
282 #define PCH_GBE_WLS_IND 0x00000002
283 #define PCH_GBE_WLS_MP 0x00000001 /* Magic packet Address */
285 /* Wake On LAN Control */
286 #define PCH_GBE_WLC_WOL_MODE 0x00010000
287 #define PCH_GBE_WLC_IGN_TLONG 0x00000100
288 #define PCH_GBE_WLC_IGN_TSHRT 0x00000080
289 #define PCH_GBE_WLC_IGN_OCTER 0x00000040
290 #define PCH_GBE_WLC_IGN_NBLER 0x00000020
291 #define PCH_GBE_WLC_IGN_CRCER 0x00000010
292 #define PCH_GBE_WLC_BR 0x00000008
293 #define PCH_GBE_WLC_MLT 0x00000004
294 #define PCH_GBE_WLC_IND 0x00000002
295 #define PCH_GBE_WLC_MP 0x00000001
297 /* Wake On LAN Address Mask */
298 #define PCH_GBE_WLA_BUSY 0x80000000
302 /* TX/RX descriptor defines */
303 #define PCH_GBE_MAX_TXD 4096
304 #define PCH_GBE_DEFAULT_TXD 256
305 #define PCH_GBE_MIN_TXD 8
306 #define PCH_GBE_MAX_RXD 4096
307 #define PCH_GBE_DEFAULT_RXD 256
308 #define PCH_GBE_MIN_RXD 8
310 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
311 #define PCH_GBE_TX_DESC_MULTIPLE 8
312 #define PCH_GBE_RX_DESC_MULTIPLE 8
314 /* Read/Write operation is done through MII Management IF */
315 #define PCH_GBE_HAL_MIIM_READ ((u32)0x00000000)
316 #define PCH_GBE_HAL_MIIM_WRITE ((u32)0x04000000)
318 /* flow control values */
319 #define PCH_GBE_FC_NONE 0
320 #define PCH_GBE_FC_RX_PAUSE 1
321 #define PCH_GBE_FC_TX_PAUSE 2
322 #define PCH_GBE_FC_FULL 3
323 #define PCH_GBE_FC_DEFAULT PCH_GBE_FC_FULL
328 * struct pch_gbe_functions - HAL APi function pointer
329 * @get_bus_info: for pch_gbe_hal_get_bus_info
330 * @init_hw: for pch_gbe_hal_init_hw
331 * @read_phy_reg: for pch_gbe_hal_read_phy_reg
332 * @write_phy_reg: for pch_gbe_hal_write_phy_reg
333 * @reset_phy: for pch_gbe_hal_phy_hw_reset
334 * @sw_reset_phy: for pch_gbe_hal_phy_sw_reset
335 * @power_up_phy: for pch_gbe_hal_power_up_phy
336 * @power_down_phy: for pch_gbe_hal_power_down_phy
337 * @read_mac_addr: for pch_gbe_hal_read_mac_addr
339 struct pch_gbe_functions {
340 void (*get_bus_info) (struct pch_gbe_hw *);
341 s32 (*init_hw) (struct pch_gbe_hw *);
342 s32 (*read_phy_reg) (struct pch_gbe_hw *, u32, u16 *);
343 s32 (*write_phy_reg) (struct pch_gbe_hw *, u32, u16);
344 void (*reset_phy) (struct pch_gbe_hw *);
345 void (*sw_reset_phy) (struct pch_gbe_hw *);
346 void (*power_up_phy) (struct pch_gbe_hw *hw);
347 void (*power_down_phy) (struct pch_gbe_hw *hw);
348 s32 (*read_mac_addr) (struct pch_gbe_hw *);
352 * struct pch_gbe_mac_info - MAC infomation
353 * @addr[6]: Store the MAC address
354 * @fc: Mode of flow control
355 * @fc_autoneg: Auto negotiation enable for flow control setting
356 * @tx_fc_enable: Enable flag of Transmit flow control
357 * @max_frame_size: Max transmit frame size
358 * @min_frame_size: Min transmit frame size
359 * @autoneg: Auto negotiation enable
360 * @link_speed: Link speed
361 * @link_duplex: Link duplex
363 struct pch_gbe_mac_info {
376 * struct pch_gbe_phy_info - PHY infomation
378 * @id: PHY's identifier
379 * @revision: PHY's revision
380 * @reset_delay_us: HW reset delay time[us]
381 * @autoneg_advertised: Autoneg advertised
383 struct pch_gbe_phy_info {
388 u16 autoneg_advertised;
392 * @ingroup Gigabit Ether driver Layer
393 * @struct pch_gbe_bus_info
394 * @brief Bus infomation
396 struct pch_gbe_bus_info {
403 * @ingroup Gigabit Ether driver Layer
405 * @brief Hardware infomation
410 struct pch_gbe_regs __iomem *reg;
411 spinlock_t miim_lock;
413 const struct pch_gbe_functions *func;
414 struct pch_gbe_mac_info mac;
415 struct pch_gbe_phy_info phy;
416 struct pch_gbe_bus_info bus;
420 * struct pch_gbe_rx_desc - Receive Descriptor
421 * @buffer_addr: RX Frame Buffer Address
422 * @tcp_ip_status: TCP/IP Accelerator Status
423 * @rx_words_eob: RX word count and Byte position
424 * @gbec_status: GMAC Status
425 * @dma_status: DMA Status
426 * @reserved1: Reserved
427 * @reserved2: Reserved
429 struct pch_gbe_rx_desc {
440 * struct pch_gbe_tx_desc - Transmit Descriptor
441 * @buffer_addr: TX Frame Buffer Address
442 * @length: Data buffer length
443 * @reserved1: Reserved
444 * @tx_words_eob: TX word count and Byte position
445 * @tx_frame_ctrl: TX Frame Control
446 * @dma_status: DMA Status
447 * @reserved2: Reserved
448 * @gbec_status: GMAC Status
450 struct pch_gbe_tx_desc {
463 * struct pch_gbe_buffer - Buffer infomation
464 * @skb: pointer to a socket buffer
466 * @time_stamp: time stamp
469 struct pch_gbe_buffer {
472 unsigned long time_stamp;
478 * struct pch_gbe_tx_ring - tx ring infomation
479 * @tx_lock: spinlock structs
480 * @desc: pointer to the descriptor ring memory
481 * @dma: physical address of the descriptor ring
482 * @size: length of descriptor ring in bytes
483 * @count: number of descriptors in the ring
484 * @next_to_use: next descriptor to associate a buffer with
485 * @next_to_clean: next descriptor to check for DD status bit
486 * @buffer_info: array of buffer information structs
488 struct pch_gbe_tx_ring {
490 struct pch_gbe_tx_desc *desc;
494 unsigned int next_to_use;
495 unsigned int next_to_clean;
496 struct pch_gbe_buffer *buffer_info;
500 * struct pch_gbe_rx_ring - rx ring infomation
501 * @desc: pointer to the descriptor ring memory
502 * @dma: physical address of the descriptor ring
503 * @size: length of descriptor ring in bytes
504 * @count: number of descriptors in the ring
505 * @next_to_use: next descriptor to associate a buffer with
506 * @next_to_clean: next descriptor to check for DD status bit
507 * @buffer_info: array of buffer information structs
509 struct pch_gbe_rx_ring {
510 struct pch_gbe_rx_desc *desc;
514 unsigned int next_to_use;
515 unsigned int next_to_clean;
516 struct pch_gbe_buffer *buffer_info;
520 * struct pch_gbe_hw_stats - Statistics counters collected by the MAC
521 * @rx_packets: total packets received
522 * @tx_packets: total packets transmitted
523 * @rx_bytes: total bytes received
524 * @tx_bytes: total bytes transmitted
525 * @rx_errors: bad packets received
526 * @tx_errors: packet transmit problems
527 * @rx_dropped: no space in Linux buffers
528 * @tx_dropped: no space available in Linux
529 * @multicast: multicast packets received
530 * @collisions: collisions
531 * @rx_crc_errors: received packet with crc error
532 * @rx_frame_errors: received frame alignment error
533 * @rx_alloc_buff_failed: allocate failure of a receive buffer
534 * @tx_length_errors: transmit length error
535 * @tx_aborted_errors: transmit aborted error
536 * @tx_carrier_errors: transmit carrier error
537 * @tx_timeout_count: Number of transmit timeout
538 * @tx_restart_count: Number of transmit restert
539 * @intr_rx_dsc_empty_count: Interrupt count of receive descriptor empty
540 * @intr_rx_frame_err_count: Interrupt count of receive frame error
541 * @intr_rx_fifo_err_count: Interrupt count of receive FIFO error
542 * @intr_rx_dma_err_count: Interrupt count of receive DMA error
543 * @intr_tx_fifo_err_count: Interrupt count of transmit FIFO error
544 * @intr_tx_dma_err_count: Interrupt count of transmit DMA error
545 * @intr_tcpip_err_count: Interrupt count of TCP/IP Accelerator
547 struct pch_gbe_hw_stats {
560 u32 rx_alloc_buff_failed;
561 u32 tx_length_errors;
562 u32 tx_aborted_errors;
563 u32 tx_carrier_errors;
564 u32 tx_timeout_count;
565 u32 tx_restart_count;
566 u32 intr_rx_dsc_empty_count;
567 u32 intr_rx_frame_err_count;
568 u32 intr_rx_fifo_err_count;
569 u32 intr_rx_dma_err_count;
570 u32 intr_tx_fifo_err_count;
571 u32 intr_tx_dma_err_count;
572 u32 intr_tcpip_err_count;
576 * struct pch_gbe_adapter - board specific private data structure
577 * @stats_lock: Spinlock structure for status
578 * @tx_queue_lock: Spinlock structure for transmit
579 * @ethtool_lock: Spinlock structure for ethtool
580 * @irq_sem: Semaphore for interrupt
581 * @netdev: Pointer of network device structure
582 * @pdev: Pointer of pci device structure
583 * @polling_netdev: Pointer of polling network device structure
584 * @napi: NAPI structure
585 * @hw: Pointer of hardware structure
586 * @stats: Hardware status
587 * @reset_task: Reset task
588 * @mii: MII information structure
589 * @watchdog_timer: Watchdog timer list
590 * @wake_up_evt: Wake up event
591 * @config_space: Configuration space
592 * @msg_enable: Driver message level
593 * @led_status: LED status
594 * @tx_ring: Pointer of Tx descriptor ring structure
595 * @rx_ring: Pointer of Rx descriptor ring structure
596 * @rx_buffer_len: Receive buffer length
597 * @tx_queue_len: Transmit queue length
598 * @rx_csum: Receive TCP/IP checksum enable/disable
599 * @tx_csum: Transmit TCP/IP checksum enable/disable
600 * @have_msi: PCI MSI mode flag
603 struct pch_gbe_adapter {
604 spinlock_t stats_lock;
605 spinlock_t tx_queue_lock;
606 spinlock_t ethtool_lock;
608 struct net_device *netdev;
609 struct pci_dev *pdev;
610 struct net_device *polling_netdev;
611 struct napi_struct napi;
612 struct pch_gbe_hw hw;
613 struct pch_gbe_hw_stats stats;
614 struct work_struct reset_task;
615 struct mii_if_info mii;
616 struct timer_list watchdog_timer;
619 unsigned long led_status;
620 struct pch_gbe_tx_ring *tx_ring;
621 struct pch_gbe_rx_ring *rx_ring;
622 unsigned long rx_buffer_len;
623 unsigned long tx_queue_len;
629 extern const char pch_driver_version[];
632 extern int pch_gbe_up(struct pch_gbe_adapter *adapter);
633 extern void pch_gbe_down(struct pch_gbe_adapter *adapter);
634 extern void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter);
635 extern void pch_gbe_reset(struct pch_gbe_adapter *adapter);
636 extern int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
637 struct pch_gbe_tx_ring *txdr);
638 extern int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
639 struct pch_gbe_rx_ring *rxdr);
640 extern void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
641 struct pch_gbe_tx_ring *tx_ring);
642 extern void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
643 struct pch_gbe_rx_ring *rx_ring);
644 extern void pch_gbe_update_stats(struct pch_gbe_adapter *adapter);
645 extern int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
646 extern void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
648 /* pch_gbe_param.c */
649 extern void pch_gbe_check_options(struct pch_gbe_adapter *adapter);
651 /* pch_gbe_ethtool.c */
652 extern void pch_gbe_set_ethtool_ops(struct net_device *netdev);
655 extern s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw);
656 extern s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw);
657 extern u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw,
658 u32 addr, u32 dir, u32 reg, u16 data);
659 #endif /* _PCH_GBE_H_ */