drivers/net/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28 #include <linux/pci-aspm.h>
  29
  30 #include <asm/system.h>
  31 #include <asm/io.h>
  32 #include <asm/irq.h>
  33
  34 #define RTL8169_VERSION "2.3LK-NAPI"
  35 #define MODULENAME "r8169"
  36 #define PFX MODULENAME ": "
  37
  38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  40
  41 #ifdef RTL8169_DEBUG
  42 #define assert(expr) \
  43         if (!(expr)) {                                  \
  44                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  45                 #expr,__FILE__,__func__,__LINE__);              \
  46         }
  47 #define dprintk(fmt, args...) \
  48         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  49 #else
  50 #define assert(expr) do {} while (0)
  51 #define dprintk(fmt, args...)   do {} while (0)
  52 #endif /* RTL8169_DEBUG */
  53
  54 #define R8169_MSG_DEFAULT \
  55         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  56
  57 #define TX_BUFFS_AVAIL(tp) \
  58         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  59
  60 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  61    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  62 static const int multicast_filter_limit = 32;
  63
  64 /* MAC address length */
  65 #define MAC_ADDR_LEN    6
  66
  67 #define MAX_READ_REQUEST_SHIFT  12
  68 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  69 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  70 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  71 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  72 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  73
  74 #define R8169_REGS_SIZE         256
  75 #define R8169_NAPI_WEIGHT       64
  76 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  77 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  78 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  79 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  80 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  81
  82 #define RTL8169_TX_TIMEOUT      (6*HZ)
  83 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  84
  85 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  86 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  87 #define RTL_EEPROM_SIG_ADDR     0x0000
  88
  89 /* write/read MMIO register */
  90 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  91 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  92 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  93 #define RTL_R8(reg)             readb (ioaddr + (reg))
  94 #define RTL_R16(reg)            readw (ioaddr + (reg))
  95 #define RTL_R32(reg)            readl (ioaddr + (reg))
  96
  97 enum mac_version {
  98         RTL_GIGA_MAC_NONE   = 0x00,
  99         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
 100         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
 101         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
 102         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
 103         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
 104         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
 105         RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
 106         RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
 107         RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
 108         RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
 109         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
 110         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
 111         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
 112         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
 113         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
 114         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
 115         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
 116         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
 117         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
 118         RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
 119         RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
 120         RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
 121         RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
 122         RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
 123         RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
 124         RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
 125         RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
 126         RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
 127 };
 128
 129 #define _R(NAME,MAC,MASK) \
 130         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
 131
 132 static const struct {
 133         const char *name;
 134         u8 mac_version;
 135         u32 RxConfigMask;       /* Clears the bits supported by this chip */
 136 } rtl_chip_info[] = {
 137         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
 138         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
 139         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
 140         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
 141         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
 142         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
 143         _R("RTL8102e",          RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
 144         _R("RTL8102e",          RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
 145         _R("RTL8102e",          RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
 146         _R("RTL8101e",          RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
 147         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
 148         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
 149         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
 150         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
 151         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
 152         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
 153         _R("RTL8101e",          RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
 154         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
 155         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
 156         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
 157         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
 158         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
 159         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
 160         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
 161         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
 162         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
 163         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_27, 0xff7e1880), // PCI-E
 164         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_28, 0xff7e1880)  // PCI-E
 165 };
 166 #undef _R
 167
 168 enum cfg_version {
 169         RTL_CFG_0 = 0x00,
 170         RTL_CFG_1,
 171         RTL_CFG_2
 172 };
 173
 174 static void rtl_hw_start_8169(struct net_device *);
 175 static void rtl_hw_start_8168(struct net_device *);
 176 static void rtl_hw_start_8101(struct net_device *);
 177
 178 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 179         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 180         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 181         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 182         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 183         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 184         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 185         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 186         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 187         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 188                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 189         { 0x0001,                               0x8168,
 190                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 191         {0,},
 192 };
 193
 194 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 195
 196 static int rx_buf_sz = 16383;
 197 static int use_dac;
 198 static struct {
 199         u32 msg_enable;
 200 } debug = { -1 };
 201
 202 enum rtl_registers {
 203         MAC0            = 0,    /* Ethernet hardware address. */
 204         MAC4            = 4,
 205         MAR0            = 8,    /* Multicast filter. */
 206         CounterAddrLow          = 0x10,
 207         CounterAddrHigh         = 0x14,
 208         TxDescStartAddrLow      = 0x20,
 209         TxDescStartAddrHigh     = 0x24,
 210         TxHDescStartAddrLow     = 0x28,
 211         TxHDescStartAddrHigh    = 0x2c,
 212         FLASH           = 0x30,
 213         ERSR            = 0x36,
 214         ChipCmd         = 0x37,
 215         TxPoll          = 0x38,
 216         IntrMask        = 0x3c,
 217         IntrStatus      = 0x3e,
 218         TxConfig        = 0x40,
 219         RxConfig        = 0x44,
 220         RxMissed        = 0x4c,
 221         Cfg9346         = 0x50,
 222         Config0         = 0x51,
 223         Config1         = 0x52,
 224         Config2         = 0x53,
 225         Config3         = 0x54,
 226         Config4         = 0x55,
 227         Config5         = 0x56,
 228         MultiIntr       = 0x5c,
 229         PHYAR           = 0x60,
 230         PHYstatus       = 0x6c,
 231         RxMaxSize       = 0xda,
 232         CPlusCmd        = 0xe0,
 233         IntrMitigate    = 0xe2,
 234         RxDescAddrLow   = 0xe4,
 235         RxDescAddrHigh  = 0xe8,
 236         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 237
 238 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 239
 240         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 241
 242 #define TxPacketMax     (8064 >> 7)
 243
 244         FuncEvent       = 0xf0,
 245         FuncEventMask   = 0xf4,
 246         FuncPresetState = 0xf8,
 247         FuncForceEvent  = 0xfc,
 248 };
 249
 250 enum rtl8110_registers {
 251         TBICSR                  = 0x64,
 252         TBI_ANAR                = 0x68,
 253         TBI_LPAR                = 0x6a,
 254 };
 255
 256 enum rtl8168_8101_registers {
 257         CSIDR                   = 0x64,
 258         CSIAR                   = 0x68,
 259 #define CSIAR_FLAG                      0x80000000
 260 #define CSIAR_WRITE_CMD                 0x80000000
 261 #define CSIAR_BYTE_ENABLE               0x0f
 262 #define CSIAR_BYTE_ENABLE_SHIFT         12
 263 #define CSIAR_ADDR_MASK                 0x0fff
 264         PMCH                    = 0x6f,
 265         EPHYAR                  = 0x80,
 266 #define EPHYAR_FLAG                     0x80000000
 267 #define EPHYAR_WRITE_CMD                0x80000000
 268 #define EPHYAR_REG_MASK                 0x1f
 269 #define EPHYAR_REG_SHIFT                16
 270 #define EPHYAR_DATA_MASK                0xffff
 271         DBG_REG                 = 0xd1,
 272 #define FIX_NAK_1                       (1 << 4)
 273 #define FIX_NAK_2                       (1 << 3)
 274         EFUSEAR                 = 0xdc,
 275 #define EFUSEAR_FLAG                    0x80000000
 276 #define EFUSEAR_WRITE_CMD               0x80000000
 277 #define EFUSEAR_READ_CMD                0x00000000
 278 #define EFUSEAR_REG_MASK                0x03ff
 279 #define EFUSEAR_REG_SHIFT               8
 280 #define EFUSEAR_DATA_MASK               0xff
 281 };
 282
 283 enum rtl8168_registers {
 284         ERIDR                   = 0x70,
 285         ERIAR                   = 0x74,
 286 #define ERIAR_FLAG                      0x80000000
 287 #define ERIAR_WRITE_CMD                 0x80000000
 288 #define ERIAR_READ_CMD                  0x00000000
 289 #define ERIAR_ADDR_BYTE_ALIGN           4
 290 #define ERIAR_EXGMAC                    0
 291 #define ERIAR_MSIX                      1
 292 #define ERIAR_ASF                       2
 293 #define ERIAR_TYPE_SHIFT                16
 294 #define ERIAR_BYTEEN                    0x0f
 295 #define ERIAR_BYTEEN_SHIFT              12
 296         EPHY_RXER_NUM           = 0x7c,
 297         OCPDR                   = 0xb0, /* OCP GPHY access */
 298 #define OCPDR_WRITE_CMD                 0x80000000
 299 #define OCPDR_READ_CMD                  0x00000000
 300 #define OCPDR_REG_MASK                  0x7f
 301 #define OCPDR_GPHY_REG_SHIFT            16
 302 #define OCPDR_DATA_MASK                 0xffff
 303         OCPAR                   = 0xb4,
 304 #define OCPAR_FLAG                      0x80000000
 305 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 306 #define OCPAR_GPHY_READ_CMD             0x0000f060
 307         RDSAR1                  = 0xd0  /* 8168c only. Undocumented on 8168dp */
 308 };
 309
 310 enum rtl_register_content {
 311         /* InterruptStatusBits */
 312         SYSErr          = 0x8000,
 313         PCSTimeout      = 0x4000,
 314         SWInt           = 0x0100,
 315         TxDescUnavail   = 0x0080,
 316         RxFIFOOver      = 0x0040,
 317         LinkChg         = 0x0020,
 318         RxOverflow      = 0x0010,
 319         TxErr           = 0x0008,
 320         TxOK            = 0x0004,
 321         RxErr           = 0x0002,
 322         RxOK            = 0x0001,
 323
 324         /* RxStatusDesc */
 325         RxFOVF  = (1 << 23),
 326         RxRWT   = (1 << 22),
 327         RxRES   = (1 << 21),
 328         RxRUNT  = (1 << 20),
 329         RxCRC   = (1 << 19),
 330
 331         /* ChipCmdBits */
 332         CmdReset        = 0x10,
 333         CmdRxEnb        = 0x08,
 334         CmdTxEnb        = 0x04,
 335         RxBufEmpty      = 0x01,
 336
 337         /* TXPoll register p.5 */
 338         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 339         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 340         FSWInt          = 0x01,         /* Forced software interrupt */
 341
 342         /* Cfg9346Bits */
 343         Cfg9346_Lock    = 0x00,
 344         Cfg9346_Unlock  = 0xc0,
 345
 346         /* rx_mode_bits */
 347         AcceptErr       = 0x20,
 348         AcceptRunt      = 0x10,
 349         AcceptBroadcast = 0x08,
 350         AcceptMulticast = 0x04,
 351         AcceptMyPhys    = 0x02,
 352         AcceptAllPhys   = 0x01,
 353
 354         /* RxConfigBits */
 355         RxCfgFIFOShift  = 13,
 356         RxCfgDMAShift   =  8,
 357
 358         /* TxConfigBits */
 359         TxInterFrameGapShift = 24,
 360         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 361
 362         /* Config1 register p.24 */
 363         LEDS1           = (1 << 7),
 364         LEDS0           = (1 << 6),
 365         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 366         Speed_down      = (1 << 4),
 367         MEMMAP          = (1 << 3),
 368         IOMAP           = (1 << 2),
 369         VPD             = (1 << 1),
 370         PMEnable        = (1 << 0),     /* Power Management Enable */
 371
 372         /* Config2 register p. 25 */
 373         PCI_Clock_66MHz = 0x01,
 374         PCI_Clock_33MHz = 0x00,
 375
 376         /* Config3 register p.25 */
 377         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 378         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 379         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 380
 381         /* Config5 register p.27 */
 382         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 383         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 384         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 385         LanWake         = (1 << 1),     /* LanWake enable/disable */
 386         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 387
 388         /* TBICSR p.28 */
 389         TBIReset        = 0x80000000,
 390         TBILoopback     = 0x40000000,
 391         TBINwEnable     = 0x20000000,
 392         TBINwRestart    = 0x10000000,
 393         TBILinkOk       = 0x02000000,
 394         TBINwComplete   = 0x01000000,
 395
 396         /* CPlusCmd p.31 */
 397         EnableBist      = (1 << 15),    // 8168 8101
 398         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 399         Normal_mode     = (1 << 13),    // unused
 400         Force_half_dup  = (1 << 12),    // 8168 8101
 401         Force_rxflow_en = (1 << 11),    // 8168 8101
 402         Force_txflow_en = (1 << 10),    // 8168 8101
 403         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 404         ASF             = (1 << 8),     // 8168 8101
 405         PktCntrDisable  = (1 << 7),     // 8168 8101
 406         Mac_dbgo_sel    = 0x001c,       // 8168
 407         RxVlan          = (1 << 6),
 408         RxChkSum        = (1 << 5),
 409         PCIDAC          = (1 << 4),
 410         PCIMulRW        = (1 << 3),
 411         INTT_0          = 0x0000,       // 8168
 412         INTT_1          = 0x0001,       // 8168
 413         INTT_2          = 0x0002,       // 8168
 414         INTT_3          = 0x0003,       // 8168
 415
 416         /* rtl8169_PHYstatus */
 417         TBI_Enable      = 0x80,
 418         TxFlowCtrl      = 0x40,
 419         RxFlowCtrl      = 0x20,
 420         _1000bpsF       = 0x10,
 421         _100bps         = 0x08,
 422         _10bps          = 0x04,
 423         LinkStatus      = 0x02,
 424         FullDup         = 0x01,
 425
 426         /* _TBICSRBit */
 427         TBILinkOK       = 0x02000000,
 428
 429         /* DumpCounterCommand */
 430         CounterDump     = 0x8,
 431 };
 432
 433 enum desc_status_bit {
 434         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 435         RingEnd         = (1 << 30), /* End of descriptor ring */
 436         FirstFrag       = (1 << 29), /* First segment of a packet */
 437         LastFrag        = (1 << 28), /* Final segment of a packet */
 438
 439         /* Tx private */
 440         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
 441         MSSShift        = 16,        /* MSS value position */
 442         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
 443         IPCS            = (1 << 18), /* Calculate IP checksum */
 444         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
 445         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
 446         TxVlanTag       = (1 << 17), /* Add VLAN tag */
 447
 448         /* Rx private */
 449         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 450         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 451
 452 #define RxProtoUDP      (PID1)
 453 #define RxProtoTCP      (PID0)
 454 #define RxProtoIP       (PID1 | PID0)
 455 #define RxProtoMask     RxProtoIP
 456
 457         IPFail          = (1 << 16), /* IP checksum failed */
 458         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 459         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 460         RxVlanTag       = (1 << 16), /* VLAN tag available */
 461 };
 462
 463 #define RsvdMask        0x3fffc000
 464
 465 struct TxDesc {
 466         __le32 opts1;
 467         __le32 opts2;
 468         __le64 addr;
 469 };
 470
 471 struct RxDesc {
 472         __le32 opts1;
 473         __le32 opts2;
 474         __le64 addr;
 475 };
 476
 477 struct ring_info {
 478         struct sk_buff  *skb;
 479         u32             len;
 480         u8              __pad[sizeof(void *) - sizeof(u32)];
 481 };
 482
 483 enum features {
 484         RTL_FEATURE_WOL         = (1 << 0),
 485         RTL_FEATURE_MSI         = (1 << 1),
 486         RTL_FEATURE_GMII        = (1 << 2),
 487 };
 488
 489 struct rtl8169_counters {
 490         __le64  tx_packets;
 491         __le64  rx_packets;
 492         __le64  tx_errors;
 493         __le32  rx_errors;
 494         __le16  rx_missed;
 495         __le16  align_errors;
 496         __le32  tx_one_collision;
 497         __le32  tx_multi_collision;
 498         __le64  rx_unicast;
 499         __le64  rx_broadcast;
 500         __le32  rx_multicast;
 501         __le16  tx_aborted;
 502         __le16  tx_underun;
 503 };
 504
 505 struct rtl8169_private {
 506         void __iomem *mmio_addr;        /* memory map physical address */
 507         struct pci_dev *pci_dev;        /* Index of PCI device */
 508         struct net_device *dev;
 509         struct napi_struct napi;
 510         spinlock_t lock;                /* spin lock flag */
 511         u32 msg_enable;
 512         int chipset;
 513         int mac_version;
 514         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 515         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 516         u32 dirty_rx;
 517         u32 dirty_tx;
 518         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 519         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 520         dma_addr_t TxPhyAddr;
 521         dma_addr_t RxPhyAddr;
 522         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 523         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 524         struct timer_list timer;
 525         u16 cp_cmd;
 526         u16 intr_event;
 527         u16 napi_event;
 528         u16 intr_mask;
 529         int phy_1000_ctrl_reg;
 530 #ifdef CONFIG_R8169_VLAN
 531         struct vlan_group *vlgrp;
 532 #endif
 533
 534         struct mdio_ops {
 535                 void (*write)(void __iomem *, int, int);
 536                 int (*read)(void __iomem *, int);
 537         } mdio_ops;
 538
 539         struct pll_power_ops {
 540                 void (*down)(struct rtl8169_private *);
 541                 void (*up)(struct rtl8169_private *);
 542         } pll_power_ops;
 543
 544         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
 545         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 546         void (*phy_reset_enable)(struct rtl8169_private *tp);
 547         void (*hw_start)(struct net_device *);
 548         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 549         unsigned int (*link_ok)(void __iomem *);
 550         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 551         int pcie_cap;
 552         struct delayed_work task;
 553         unsigned features;
 554
 555         struct mii_if_info mii;
 556         struct rtl8169_counters counters;
 557         u32 saved_wolopts;
 558
 559         const struct firmware *fw;
 560 };
 561
 562 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 563 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 564 module_param(use_dac, int, 0);
 565 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 566 module_param_named(debug, debug.msg_enable, int, 0);
 567 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 568 MODULE_LICENSE("GPL");
 569 MODULE_VERSION(RTL8169_VERSION);
 570 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 571 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 572
 573 static int rtl8169_open(struct net_device *dev);
 574 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 575                                       struct net_device *dev);
 576 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 577 static int rtl8169_init_ring(struct net_device *dev);
 578 static void rtl_hw_start(struct net_device *dev);
 579 static int rtl8169_close(struct net_device *dev);
 580 static void rtl_set_rx_mode(struct net_device *dev);
 581 static void rtl8169_tx_timeout(struct net_device *dev);
 582 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 583 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 584                                 void __iomem *, u32 budget);
 585 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 586 static void rtl8169_down(struct net_device *dev);
 587 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 588 static int rtl8169_poll(struct napi_struct *napi, int budget);
 589
 590 static const unsigned int rtl8169_rx_config =
 591         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 592
 593 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 594 {
 595         void __iomem *ioaddr = tp->mmio_addr;
 596         int i;
 597
 598         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 599         for (i = 0; i < 20; i++) {
 600                 udelay(100);
 601                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 602                         break;
 603         }
 604         return RTL_R32(OCPDR);
 605 }
 606
 607 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 608 {
 609         void __iomem *ioaddr = tp->mmio_addr;
 610         int i;
 611
 612         RTL_W32(OCPDR, data);
 613         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 614         for (i = 0; i < 20; i++) {
 615                 udelay(100);
 616                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 617                         break;
 618         }
 619 }
 620
 621 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 622 {
 623         void __iomem *ioaddr = tp->mmio_addr;
 624         int i;
 625
 626         RTL_W8(ERIDR, cmd);
 627         RTL_W32(ERIAR, 0x800010e8);
 628         msleep(2);
 629         for (i = 0; i < 5; i++) {
 630                 udelay(100);
 631                 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
 632                         break;
 633         }
 634
 635         ocp_write(tp, 0x1, 0x30, 0x00000001);
 636 }
 637
 638 #define OOB_CMD_RESET           0x00
 639 #define OOB_CMD_DRIVER_START    0x05
 640 #define OOB_CMD_DRIVER_STOP     0x06
 641
 642 static void rtl8168_driver_start(struct rtl8169_private *tp)
 643 {
 644         int i;
 645
 646         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 647
 648         for (i = 0; i < 10; i++) {
 649                 msleep(10);
 650                 if (ocp_read(tp, 0x0f, 0x0010) & 0x00000800)
 651                         break;
 652         }
 653 }
 654
 655 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 656 {
 657         int i;
 658
 659         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 660
 661         for (i = 0; i < 10; i++) {
 662                 msleep(10);
 663                 if ((ocp_read(tp, 0x0f, 0x0010) & 0x00000800) == 0)
 664                         break;
 665         }
 666 }
 667
 668
 669 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 670 {
 671         int i;
 672
 673         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 674
 675         for (i = 20; i > 0; i--) {
 676                 /*
 677                  * Check if the RTL8169 has completed writing to the specified
 678                  * MII register.
 679                  */
 680                 if (!(RTL_R32(PHYAR) & 0x80000000))
 681                         break;
 682                 udelay(25);
 683         }
 684         /*
 685          * According to hardware specs a 20us delay is required after write
 686          * complete indication, but before sending next command.
 687          */
 688         udelay(20);
 689 }
 690
 691 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 692 {
 693         int i, value = -1;
 694
 695         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 696
 697         for (i = 20; i > 0; i--) {
 698                 /*
 699                  * Check if the RTL8169 has completed retrieving data from
 700                  * the specified MII register.
 701                  */
 702                 if (RTL_R32(PHYAR) & 0x80000000) {
 703                         value = RTL_R32(PHYAR) & 0xffff;
 704                         break;
 705                 }
 706                 udelay(25);
 707         }
 708         /*
 709          * According to hardware specs a 20us delay is required after read
 710          * complete indication, but before sending next command.
 711          */
 712         udelay(20);
 713
 714         return value;
 715 }
 716
 717 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 718 {
 719         int i;
 720
 721         RTL_W32(OCPDR, data |
 722                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 723         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 724         RTL_W32(EPHY_RXER_NUM, 0);
 725
 726         for (i = 0; i < 100; i++) {
 727                 mdelay(1);
 728                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 729                         break;
 730         }
 731 }
 732
 733 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 734 {
 735         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 736                 (value & OCPDR_DATA_MASK));
 737 }
 738
 739 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 740 {
 741         int i;
 742
 743         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 744
 745         mdelay(1);
 746         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 747         RTL_W32(EPHY_RXER_NUM, 0);
 748
 749         for (i = 0; i < 100; i++) {
 750                 mdelay(1);
 751                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 752                         break;
 753         }
 754
 755         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 756 }
 757
 758 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 759
 760 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 761 {
 762         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 763 }
 764
 765 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 766 {
 767         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 768 }
 769
 770 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 771 {
 772         r8168dp_2_mdio_start(ioaddr);
 773
 774         r8169_mdio_write(ioaddr, reg_addr, value);
 775
 776         r8168dp_2_mdio_stop(ioaddr);
 777 }
 778
 779 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
 780 {
 781         int value;
 782
 783         r8168dp_2_mdio_start(ioaddr);
 784
 785         value = r8169_mdio_read(ioaddr, reg_addr);
 786
 787         r8168dp_2_mdio_stop(ioaddr);
 788
 789         return value;
 790 }
 791
 792 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
 793 {
 794         tp->mdio_ops.write(tp->mmio_addr, location, val);
 795 }
 796
 797 static int rtl_readphy(struct rtl8169_private *tp, int location)
 798 {
 799         return tp->mdio_ops.read(tp->mmio_addr, location);
 800 }
 801
 802 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
 803 {
 804         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
 805 }
 806
 807 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
 808 {
 809         int val;
 810
 811         val = rtl_readphy(tp, reg_addr);
 812         rtl_writephy(tp, reg_addr, (val | p) & ~m);
 813 }
 814
 815 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 816                            int val)
 817 {
 818         struct rtl8169_private *tp = netdev_priv(dev);
 819
 820         rtl_writephy(tp, location, val);
 821 }
 822
 823 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
 824 {
 825         struct rtl8169_private *tp = netdev_priv(dev);
 826
 827         return rtl_readphy(tp, location);
 828 }
 829
 830 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
 831 {
 832         unsigned int i;
 833
 834         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
 835                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 836
 837         for (i = 0; i < 100; i++) {
 838                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
 839                         break;
 840                 udelay(10);
 841         }
 842 }
 843
 844 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
 845 {
 846         u16 value = 0xffff;
 847         unsigned int i;
 848
 849         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 850
 851         for (i = 0; i < 100; i++) {
 852                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
 853                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
 854                         break;
 855                 }
 856                 udelay(10);
 857         }
 858
 859         return value;
 860 }
 861
 862 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
 863 {
 864         unsigned int i;
 865
 866         RTL_W32(CSIDR, value);
 867         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
 868                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 869
 870         for (i = 0; i < 100; i++) {
 871                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
 872                         break;
 873                 udelay(10);
 874         }
 875 }
 876
 877 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
 878 {
 879         u32 value = ~0x00;
 880         unsigned int i;
 881
 882         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
 883                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 884
 885         for (i = 0; i < 100; i++) {
 886                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
 887                         value = RTL_R32(CSIDR);
 888                         break;
 889                 }
 890                 udelay(10);
 891         }
 892
 893         return value;
 894 }
 895
 896 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
 897 {
 898         u8 value = 0xff;
 899         unsigned int i;
 900
 901         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
 902
 903         for (i = 0; i < 300; i++) {
 904                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
 905                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
 906                         break;
 907                 }
 908                 udelay(100);
 909         }
 910
 911         return value;
 912 }
 913
 914 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
 915 {
 916         RTL_W16(IntrMask, 0x0000);
 917
 918         RTL_W16(IntrStatus, 0xffff);
 919 }
 920
 921 static void rtl8169_asic_down(void __iomem *ioaddr)
 922 {
 923         RTL_W8(ChipCmd, 0x00);
 924         rtl8169_irq_mask_and_ack(ioaddr);
 925         RTL_R16(CPlusCmd);
 926 }
 927
 928 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
 929 {
 930         void __iomem *ioaddr = tp->mmio_addr;
 931
 932         return RTL_R32(TBICSR) & TBIReset;
 933 }
 934
 935 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
 936 {
 937         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
 938 }
 939
 940 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
 941 {
 942         return RTL_R32(TBICSR) & TBILinkOk;
 943 }
 944
 945 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
 946 {
 947         return RTL_R8(PHYstatus) & LinkStatus;
 948 }
 949
 950 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
 951 {
 952         void __iomem *ioaddr = tp->mmio_addr;
 953
 954         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
 955 }
 956
 957 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
 958 {
 959         unsigned int val;
 960
 961         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
 962         rtl_writephy(tp, MII_BMCR, val & 0xffff);
 963 }
 964
 965 static void __rtl8169_check_link_status(struct net_device *dev,
 966                                       struct rtl8169_private *tp,
 967                                       void __iomem *ioaddr,
 968                                       bool pm)
 969 {
 970         unsigned long flags;
 971
 972         spin_lock_irqsave(&tp->lock, flags);
 973         if (tp->link_ok(ioaddr)) {
 974                 /* This is to cancel a scheduled suspend if there's one. */
 975                 if (pm)
 976                         pm_request_resume(&tp->pci_dev->dev);
 977                 netif_carrier_on(dev);
 978                 if (net_ratelimit())
 979                         netif_info(tp, ifup, dev, "link up\n");
 980         } else {
 981                 netif_carrier_off(dev);
 982                 netif_info(tp, ifdown, dev, "link down\n");
 983                 if (pm)
 984                         pm_schedule_suspend(&tp->pci_dev->dev, 100);
 985         }
 986         spin_unlock_irqrestore(&tp->lock, flags);
 987 }
 988
 989 static void rtl8169_check_link_status(struct net_device *dev,
 990                                       struct rtl8169_private *tp,
 991                                       void __iomem *ioaddr)
 992 {
 993         __rtl8169_check_link_status(dev, tp, ioaddr, false);
 994 }
 995
 996 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
 997
 998 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
 999 {
1000         void __iomem *ioaddr = tp->mmio_addr;
1001         u8 options;
1002         u32 wolopts = 0;
1003
1004         options = RTL_R8(Config1);
1005         if (!(options & PMEnable))
1006                 return 0;
1007
1008         options = RTL_R8(Config3);
1009         if (options & LinkUp)
1010                 wolopts |= WAKE_PHY;
1011         if (options & MagicPacket)
1012                 wolopts |= WAKE_MAGIC;
1013
1014         options = RTL_R8(Config5);
1015         if (options & UWF)
1016                 wolopts |= WAKE_UCAST;
1017         if (options & BWF)
1018                 wolopts |= WAKE_BCAST;
1019         if (options & MWF)
1020                 wolopts |= WAKE_MCAST;
1021
1022         return wolopts;
1023 }
1024
1025 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1026 {
1027         struct rtl8169_private *tp = netdev_priv(dev);
1028
1029         spin_lock_irq(&tp->lock);
1030
1031         wol->supported = WAKE_ANY;
1032         wol->wolopts = __rtl8169_get_wol(tp);
1033
1034         spin_unlock_irq(&tp->lock);
1035 }
1036
1037 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1038 {
1039         void __iomem *ioaddr = tp->mmio_addr;
1040         unsigned int i;
1041         static const struct {
1042                 u32 opt;
1043                 u16 reg;
1044                 u8  mask;
1045         } cfg[] = {
1046                 { WAKE_ANY,   Config1, PMEnable },
1047                 { WAKE_PHY,   Config3, LinkUp },
1048                 { WAKE_MAGIC, Config3, MagicPacket },
1049                 { WAKE_UCAST, Config5, UWF },
1050                 { WAKE_BCAST, Config5, BWF },
1051                 { WAKE_MCAST, Config5, MWF },
1052                 { WAKE_ANY,   Config5, LanWake }
1053         };
1054
1055         RTL_W8(Cfg9346, Cfg9346_Unlock);
1056
1057         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1058                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1059                 if (wolopts & cfg[i].opt)
1060                         options |= cfg[i].mask;
1061                 RTL_W8(cfg[i].reg, options);
1062         }
1063
1064         RTL_W8(Cfg9346, Cfg9346_Lock);
1065 }
1066
1067 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1068 {
1069         struct rtl8169_private *tp = netdev_priv(dev);
1070
1071         spin_lock_irq(&tp->lock);
1072
1073         if (wol->wolopts)
1074                 tp->features |= RTL_FEATURE_WOL;
1075         else
1076                 tp->features &= ~RTL_FEATURE_WOL;
1077         __rtl8169_set_wol(tp, wol->wolopts);
1078         spin_unlock_irq(&tp->lock);
1079
1080         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1081
1082         return 0;
1083 }
1084
1085 static void rtl8169_get_drvinfo(struct net_device *dev,
1086                                 struct ethtool_drvinfo *info)
1087 {
1088         struct rtl8169_private *tp = netdev_priv(dev);
1089
1090         strcpy(info->driver, MODULENAME);
1091         strcpy(info->version, RTL8169_VERSION);
1092         strcpy(info->bus_info, pci_name(tp->pci_dev));
1093 }
1094
1095 static int rtl8169_get_regs_len(struct net_device *dev)
1096 {
1097         return R8169_REGS_SIZE;
1098 }
1099
1100 static int rtl8169_set_speed_tbi(struct net_device *dev,
1101                                  u8 autoneg, u16 speed, u8 duplex)
1102 {
1103         struct rtl8169_private *tp = netdev_priv(dev);
1104         void __iomem *ioaddr = tp->mmio_addr;
1105         int ret = 0;
1106         u32 reg;
1107
1108         reg = RTL_R32(TBICSR);
1109         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1110             (duplex == DUPLEX_FULL)) {
1111                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1112         } else if (autoneg == AUTONEG_ENABLE)
1113                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1114         else {
1115                 netif_warn(tp, link, dev,
1116                            "incorrect speed setting refused in TBI mode\n");
1117                 ret = -EOPNOTSUPP;
1118         }
1119
1120         return ret;
1121 }
1122
1123 static int rtl8169_set_speed_xmii(struct net_device *dev,
1124                                   u8 autoneg, u16 speed, u8 duplex)
1125 {
1126         struct rtl8169_private *tp = netdev_priv(dev);
1127         int giga_ctrl, bmcr;
1128
1129         if (autoneg == AUTONEG_ENABLE) {
1130                 int auto_nego;
1131
1132                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1133                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1134                               ADVERTISE_100HALF | ADVERTISE_100FULL);
1135                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1136
1137                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1138                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1139
1140                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1141                 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1142                     (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1143                     (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1144                     (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1145                     (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1146                     (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1147                     (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
1148                     (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
1149                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1150                 } else {
1151                         netif_info(tp, link, dev,
1152                                    "PHY does not support 1000Mbps\n");
1153                 }
1154
1155                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1156
1157                 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
1158                     (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
1159                     (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
1160                         /*
1161                          * Wake up the PHY.
1162                          * Vendor specific (0x1f) and reserved (0x0e) MII
1163                          * registers.
1164                          */
1165                         rtl_writephy(tp, 0x1f, 0x0000);
1166                         rtl_writephy(tp, 0x0e, 0x0000);
1167                 }
1168
1169                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1170                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1171         } else {
1172                 giga_ctrl = 0;
1173
1174                 if (speed == SPEED_10)
1175                         bmcr = 0;
1176                 else if (speed == SPEED_100)
1177                         bmcr = BMCR_SPEED100;
1178                 else
1179                         return -EINVAL;
1180
1181                 if (duplex == DUPLEX_FULL)
1182                         bmcr |= BMCR_FULLDPLX;
1183
1184                 rtl_writephy(tp, 0x1f, 0x0000);
1185         }
1186
1187         tp->phy_1000_ctrl_reg = giga_ctrl;
1188
1189         rtl_writephy(tp, MII_BMCR, bmcr);
1190
1191         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1192             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1193                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1194                         rtl_writephy(tp, 0x17, 0x2138);
1195                         rtl_writephy(tp, 0x0e, 0x0260);
1196                 } else {
1197                         rtl_writephy(tp, 0x17, 0x2108);
1198                         rtl_writephy(tp, 0x0e, 0x0000);
1199                 }
1200         }
1201
1202         return 0;
1203 }
1204
1205 static int rtl8169_set_speed(struct net_device *dev,
1206                              u8 autoneg, u16 speed, u8 duplex)
1207 {
1208         struct rtl8169_private *tp = netdev_priv(dev);
1209         int ret;
1210
1211         ret = tp->set_speed(dev, autoneg, speed, duplex);
1212
1213         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1214                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1215
1216         return ret;
1217 }
1218
1219 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1220 {
1221         struct rtl8169_private *tp = netdev_priv(dev);
1222         unsigned long flags;
1223         int ret;
1224
1225         spin_lock_irqsave(&tp->lock, flags);
1226         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1227         spin_unlock_irqrestore(&tp->lock, flags);
1228
1229         return ret;
1230 }
1231
1232 static u32 rtl8169_get_rx_csum(struct net_device *dev)
1233 {
1234         struct rtl8169_private *tp = netdev_priv(dev);
1235
1236         return tp->cp_cmd & RxChkSum;
1237 }
1238
1239 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1240 {
1241         struct rtl8169_private *tp = netdev_priv(dev);
1242         void __iomem *ioaddr = tp->mmio_addr;
1243         unsigned long flags;
1244
1245         spin_lock_irqsave(&tp->lock, flags);
1246
1247         if (data)
1248                 tp->cp_cmd |= RxChkSum;
1249         else
1250                 tp->cp_cmd &= ~RxChkSum;
1251
1252         RTL_W16(CPlusCmd, tp->cp_cmd);
1253         RTL_R16(CPlusCmd);
1254
1255         spin_unlock_irqrestore(&tp->lock, flags);
1256
1257         return 0;
1258 }
1259
1260 #ifdef CONFIG_R8169_VLAN
1261
1262 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1263                                       struct sk_buff *skb)
1264 {
1265         return (vlan_tx_tag_present(skb)) ?
1266                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1267 }
1268
1269 static void rtl8169_vlan_rx_register(struct net_device *dev,
1270                                      struct vlan_group *grp)
1271 {
1272         struct rtl8169_private *tp = netdev_priv(dev);
1273         void __iomem *ioaddr = tp->mmio_addr;
1274         unsigned long flags;
1275
1276         spin_lock_irqsave(&tp->lock, flags);
1277         tp->vlgrp = grp;
1278         /*
1279          * Do not disable RxVlan on 8110SCd.
1280          */
1281         if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1282                 tp->cp_cmd |= RxVlan;
1283         else
1284                 tp->cp_cmd &= ~RxVlan;
1285         RTL_W16(CPlusCmd, tp->cp_cmd);
1286         RTL_R16(CPlusCmd);
1287         spin_unlock_irqrestore(&tp->lock, flags);
1288 }
1289
1290 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1291                                struct sk_buff *skb, int polling)
1292 {
1293         u32 opts2 = le32_to_cpu(desc->opts2);
1294         struct vlan_group *vlgrp = tp->vlgrp;
1295         int ret;
1296
1297         if (vlgrp && (opts2 & RxVlanTag)) {
1298                 u16 vtag = swab16(opts2 & 0xffff);
1299
1300                 if (likely(polling))
1301                         vlan_gro_receive(&tp->napi, vlgrp, vtag, skb);
1302                 else
1303                         __vlan_hwaccel_rx(skb, vlgrp, vtag, polling);
1304                 ret = 0;
1305         } else
1306                 ret = -1;
1307         desc->opts2 = 0;
1308         return ret;
1309 }
1310
1311 #else /* !CONFIG_R8169_VLAN */
1312
1313 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1314                                       struct sk_buff *skb)
1315 {
1316         return 0;
1317 }
1318
1319 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1320                                struct sk_buff *skb, int polling)
1321 {
1322         return -1;
1323 }
1324
1325 #endif
1326
1327 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1328 {
1329         struct rtl8169_private *tp = netdev_priv(dev);
1330         void __iomem *ioaddr = tp->mmio_addr;
1331         u32 status;
1332
1333         cmd->supported =
1334                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1335         cmd->port = PORT_FIBRE;
1336         cmd->transceiver = XCVR_INTERNAL;
1337
1338         status = RTL_R32(TBICSR);
1339         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1340         cmd->autoneg = !!(status & TBINwEnable);
1341
1342         cmd->speed = SPEED_1000;
1343         cmd->duplex = DUPLEX_FULL; /* Always set */
1344
1345         return 0;
1346 }
1347
1348 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1349 {
1350         struct rtl8169_private *tp = netdev_priv(dev);
1351
1352         return mii_ethtool_gset(&tp->mii, cmd);
1353 }
1354
1355 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1356 {
1357         struct rtl8169_private *tp = netdev_priv(dev);
1358         unsigned long flags;
1359         int rc;
1360
1361         spin_lock_irqsave(&tp->lock, flags);
1362
1363         rc = tp->get_settings(dev, cmd);
1364
1365         spin_unlock_irqrestore(&tp->lock, flags);
1366         return rc;
1367 }
1368
1369 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1370                              void *p)
1371 {
1372         struct rtl8169_private *tp = netdev_priv(dev);
1373         unsigned long flags;
1374
1375         if (regs->len > R8169_REGS_SIZE)
1376                 regs->len = R8169_REGS_SIZE;
1377
1378         spin_lock_irqsave(&tp->lock, flags);
1379         memcpy_fromio(p, tp->mmio_addr, regs->len);
1380         spin_unlock_irqrestore(&tp->lock, flags);
1381 }
1382
1383 static u32 rtl8169_get_msglevel(struct net_device *dev)
1384 {
1385         struct rtl8169_private *tp = netdev_priv(dev);
1386
1387         return tp->msg_enable;
1388 }
1389
1390 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1391 {
1392         struct rtl8169_private *tp = netdev_priv(dev);
1393
1394         tp->msg_enable = value;
1395 }
1396
1397 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1398         "tx_packets",
1399         "rx_packets",
1400         "tx_errors",
1401         "rx_errors",
1402         "rx_missed",
1403         "align_errors",
1404         "tx_single_collisions",
1405         "tx_multi_collisions",
1406         "unicast",
1407         "broadcast",
1408         "multicast",
1409         "tx_aborted",
1410         "tx_underrun",
1411 };
1412
1413 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1414 {
1415         switch (sset) {
1416         case ETH_SS_STATS:
1417                 return ARRAY_SIZE(rtl8169_gstrings);
1418         default:
1419                 return -EOPNOTSUPP;
1420         }
1421 }
1422
1423 static void rtl8169_update_counters(struct net_device *dev)
1424 {
1425         struct rtl8169_private *tp = netdev_priv(dev);
1426         void __iomem *ioaddr = tp->mmio_addr;
1427         struct rtl8169_counters *counters;
1428         dma_addr_t paddr;
1429         u32 cmd;
1430         int wait = 1000;
1431         struct device *d = &tp->pci_dev->dev;
1432
1433         /*
1434          * Some chips are unable to dump tally counters when the receiver
1435          * is disabled.
1436          */
1437         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1438                 return;
1439
1440         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1441         if (!counters)
1442                 return;
1443
1444         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1445         cmd = (u64)paddr & DMA_BIT_MASK(32);
1446         RTL_W32(CounterAddrLow, cmd);
1447         RTL_W32(CounterAddrLow, cmd | CounterDump);
1448
1449         while (wait--) {
1450                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1451                         /* copy updated counters */
1452                         memcpy(&tp->counters, counters, sizeof(*counters));
1453                         break;
1454                 }
1455                 udelay(10);
1456         }
1457
1458         RTL_W32(CounterAddrLow, 0);
1459         RTL_W32(CounterAddrHigh, 0);
1460
1461         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1462 }
1463
1464 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1465                                       struct ethtool_stats *stats, u64 *data)
1466 {
1467         struct rtl8169_private *tp = netdev_priv(dev);
1468
1469         ASSERT_RTNL();
1470
1471         rtl8169_update_counters(dev);
1472
1473         data[0] = le64_to_cpu(tp->counters.tx_packets);
1474         data[1] = le64_to_cpu(tp->counters.rx_packets);
1475         data[2] = le64_to_cpu(tp->counters.tx_errors);
1476         data[3] = le32_to_cpu(tp->counters.rx_errors);
1477         data[4] = le16_to_cpu(tp->counters.rx_missed);
1478         data[5] = le16_to_cpu(tp->counters.align_errors);
1479         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1480         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1481         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1482         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1483         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1484         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1485         data[12] = le16_to_cpu(tp->counters.tx_underun);
1486 }
1487
1488 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1489 {
1490         switch(stringset) {
1491         case ETH_SS_STATS:
1492                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1493                 break;
1494         }
1495 }
1496
1497 static const struct ethtool_ops rtl8169_ethtool_ops = {
1498         .get_drvinfo            = rtl8169_get_drvinfo,
1499         .get_regs_len           = rtl8169_get_regs_len,
1500         .get_link               = ethtool_op_get_link,
1501         .get_settings           = rtl8169_get_settings,
1502         .set_settings           = rtl8169_set_settings,
1503         .get_msglevel           = rtl8169_get_msglevel,
1504         .set_msglevel           = rtl8169_set_msglevel,
1505         .get_rx_csum            = rtl8169_get_rx_csum,
1506         .set_rx_csum            = rtl8169_set_rx_csum,
1507         .set_tx_csum            = ethtool_op_set_tx_csum,
1508         .set_sg                 = ethtool_op_set_sg,
1509         .set_tso                = ethtool_op_set_tso,
1510         .get_regs               = rtl8169_get_regs,
1511         .get_wol                = rtl8169_get_wol,
1512         .set_wol                = rtl8169_set_wol,
1513         .get_strings            = rtl8169_get_strings,
1514         .get_sset_count         = rtl8169_get_sset_count,
1515         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1516 };
1517
1518 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1519                                     void __iomem *ioaddr)
1520 {
1521         /*
1522          * The driver currently handles the 8168Bf and the 8168Be identically
1523          * but they can be identified more specifically through the test below
1524          * if needed:
1525          *
1526          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1527          *
1528          * Same thing for the 8101Eb and the 8101Ec:
1529          *
1530          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1531          */
1532         static const struct {
1533                 u32 mask;
1534                 u32 val;
1535                 int mac_version;
1536         } mac_info[] = {
1537                 /* 8168D family. */
1538                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1539                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1540                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1541
1542                 /* 8168DP family. */
1543                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1544                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1545
1546                 /* 8168C family. */
1547                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1548                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1549                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1550                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1551                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1552                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1553                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1554                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1555                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1556
1557                 /* 8168B family. */
1558                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1559                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1560                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1561                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1562
1563                 /* 8101 family. */
1564                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1565                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1566                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1567                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1568                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1569                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1570                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1571                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1572                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1573                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1574                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1575                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1576                 /* FIXME: where did these entries come from ? -- FR */
1577                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1578                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1579
1580                 /* 8110 family. */
1581                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1582                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1583                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1584                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1585                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1586                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1587
1588                 /* Catch-all */
1589                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1590         }, *p = mac_info;
1591         u32 reg;
1592
1593         reg = RTL_R32(TxConfig);
1594         while ((reg & p->mask) != p->val)
1595                 p++;
1596         tp->mac_version = p->mac_version;
1597 }
1598
1599 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1600 {
1601         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1602 }
1603
1604 struct phy_reg {
1605         u16 reg;
1606         u16 val;
1607 };
1608
1609 static void rtl_writephy_batch(struct rtl8169_private *tp,
1610                                const struct phy_reg *regs, int len)
1611 {
1612         while (len-- > 0) {
1613                 rtl_writephy(tp, regs->reg, regs->val);
1614                 regs++;
1615         }
1616 }
1617
1618 #define PHY_READ                0x00000000
1619 #define PHY_DATA_OR             0x10000000
1620 #define PHY_DATA_AND            0x20000000
1621 #define PHY_BJMPN               0x30000000
1622 #define PHY_READ_EFUSE          0x40000000
1623 #define PHY_READ_MAC_BYTE       0x50000000
1624 #define PHY_WRITE_MAC_BYTE      0x60000000
1625 #define PHY_CLEAR_READCOUNT     0x70000000
1626 #define PHY_WRITE               0x80000000
1627 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1628 #define PHY_COMP_EQ_SKIPN       0xa0000000
1629 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1630 #define PHY_WRITE_PREVIOUS      0xc0000000
1631 #define PHY_SKIPN               0xd0000000
1632 #define PHY_DELAY_MS            0xe0000000
1633 #define PHY_WRITE_ERI_WORD      0xf0000000
1634
1635 static void
1636 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1637 {
1638         __le32 *phytable = (__le32 *)fw->data;
1639         struct net_device *dev = tp->dev;
1640         size_t index, fw_size = fw->size / sizeof(*phytable);
1641         u32 predata, count;
1642
1643         if (fw->size % sizeof(*phytable)) {
1644                 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1645                 return;
1646         }
1647
1648         for (index = 0; index < fw_size; index++) {
1649                 u32 action = le32_to_cpu(phytable[index]);
1650                 u32 regno = (action & 0x0fff0000) >> 16;
1651
1652                 switch(action & 0xf0000000) {
1653                 case PHY_READ:
1654                 case PHY_DATA_OR:
1655                 case PHY_DATA_AND:
1656                 case PHY_READ_EFUSE:
1657                 case PHY_CLEAR_READCOUNT:
1658                 case PHY_WRITE:
1659                 case PHY_WRITE_PREVIOUS:
1660                 case PHY_DELAY_MS:
1661                         break;
1662
1663                 case PHY_BJMPN:
1664                         if (regno > index) {
1665                                 netif_err(tp, probe, tp->dev,
1666                                         "Out of range of firmware\n");
1667                                 return;
1668                         }
1669                         break;
1670                 case PHY_READCOUNT_EQ_SKIP:
1671                         if (index + 2 >= fw_size) {
1672                                 netif_err(tp, probe, tp->dev,
1673                                         "Out of range of firmware\n");
1674                                 return;
1675                         }
1676                         break;
1677                 case PHY_COMP_EQ_SKIPN:
1678                 case PHY_COMP_NEQ_SKIPN:
1679                 case PHY_SKIPN:
1680                         if (index + 1 + regno >= fw_size) {
1681                                 netif_err(tp, probe, tp->dev,
1682                                         "Out of range of firmware\n");
1683                                 return;
1684                         }
1685                         break;
1686
1687                 case PHY_READ_MAC_BYTE:
1688                 case PHY_WRITE_MAC_BYTE:
1689                 case PHY_WRITE_ERI_WORD:
1690                 default:
1691                         netif_err(tp, probe, tp->dev,
1692                                   "Invalid action 0x%08x\n", action);
1693                         return;
1694                 }
1695         }
1696
1697         predata = 0;
1698         count = 0;
1699
1700         for (index = 0; index < fw_size; ) {
1701                 u32 action = le32_to_cpu(phytable[index]);
1702                 u32 data = action & 0x0000ffff;
1703                 u32 regno = (action & 0x0fff0000) >> 16;
1704
1705                 if (!action)
1706                         break;
1707
1708                 switch(action & 0xf0000000) {
1709                 case PHY_READ:
1710                         predata = rtl_readphy(tp, regno);
1711                         count++;
1712                         index++;
1713                         break;
1714                 case PHY_DATA_OR:
1715                         predata |= data;
1716                         index++;
1717                         break;
1718                 case PHY_DATA_AND:
1719                         predata &= data;
1720                         index++;
1721                         break;
1722                 case PHY_BJMPN:
1723                         index -= regno;
1724                         break;
1725                 case PHY_READ_EFUSE:
1726                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1727                         index++;
1728                         break;
1729                 case PHY_CLEAR_READCOUNT:
1730                         count = 0;
1731                         index++;
1732                         break;
1733                 case PHY_WRITE:
1734                         rtl_writephy(tp, regno, data);
1735                         index++;
1736                         break;
1737                 case PHY_READCOUNT_EQ_SKIP:
1738                         if (count == data)
1739                                 index += 2;
1740                         else
1741                                 index += 1;
1742                         break;
1743                 case PHY_COMP_EQ_SKIPN:
1744                         if (predata == data)
1745                                 index += regno;
1746                         index++;
1747                         break;
1748                 case PHY_COMP_NEQ_SKIPN:
1749                         if (predata != data)
1750                                 index += regno;
1751                         index++;
1752                         break;
1753                 case PHY_WRITE_PREVIOUS:
1754                         rtl_writephy(tp, regno, predata);
1755                         index++;
1756                         break;
1757                 case PHY_SKIPN:
1758                         index += regno + 1;
1759                         break;
1760                 case PHY_DELAY_MS:
1761                         mdelay(data);
1762                         index++;
1763                         break;
1764
1765                 case PHY_READ_MAC_BYTE:
1766                 case PHY_WRITE_MAC_BYTE:
1767                 case PHY_WRITE_ERI_WORD:
1768                 default:
1769                         BUG();
1770                 }
1771         }
1772 }
1773
1774 static void rtl_release_firmware(struct rtl8169_private *tp)
1775 {
1776         release_firmware(tp->fw);
1777         tp->fw = NULL;
1778 }
1779
1780 static int rtl_apply_firmware(struct rtl8169_private *tp, const char *fw_name)
1781 {
1782         const struct firmware **fw = &tp->fw;
1783         int rc = !*fw;
1784
1785         if (rc) {
1786                 rc = request_firmware(fw, fw_name, &tp->pci_dev->dev);
1787                 if (rc < 0)
1788                         goto out;
1789         }
1790
1791         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1792         rtl_phy_write_fw(tp, *fw);
1793 out:
1794         return rc;
1795 }
1796
1797 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1798 {
1799         static const struct phy_reg phy_reg_init[] = {
1800                 { 0x1f, 0x0001 },
1801                 { 0x06, 0x006e },
1802                 { 0x08, 0x0708 },
1803                 { 0x15, 0x4000 },
1804                 { 0x18, 0x65c7 },
1805
1806                 { 0x1f, 0x0001 },
1807                 { 0x03, 0x00a1 },
1808                 { 0x02, 0x0008 },
1809                 { 0x01, 0x0120 },
1810                 { 0x00, 0x1000 },
1811                 { 0x04, 0x0800 },
1812                 { 0x04, 0x0000 },
1813
1814                 { 0x03, 0xff41 },
1815                 { 0x02, 0xdf60 },
1816                 { 0x01, 0x0140 },
1817                 { 0x00, 0x0077 },
1818                 { 0x04, 0x7800 },
1819                 { 0x04, 0x7000 },
1820
1821                 { 0x03, 0x802f },
1822                 { 0x02, 0x4f02 },
1823                 { 0x01, 0x0409 },
1824                 { 0x00, 0xf0f9 },
1825                 { 0x04, 0x9800 },
1826                 { 0x04, 0x9000 },
1827
1828                 { 0x03, 0xdf01 },
1829                 { 0x02, 0xdf20 },
1830                 { 0x01, 0xff95 },
1831                 { 0x00, 0xba00 },
1832                 { 0x04, 0xa800 },
1833                 { 0x04, 0xa000 },
1834
1835                 { 0x03, 0xff41 },
1836                 { 0x02, 0xdf20 },
1837                 { 0x01, 0x0140 },
1838                 { 0x00, 0x00bb },
1839                 { 0x04, 0xb800 },
1840                 { 0x04, 0xb000 },
1841
1842                 { 0x03, 0xdf41 },
1843                 { 0x02, 0xdc60 },
1844                 { 0x01, 0x6340 },
1845                 { 0x00, 0x007d },
1846                 { 0x04, 0xd800 },
1847                 { 0x04, 0xd000 },
1848
1849                 { 0x03, 0xdf01 },
1850                 { 0x02, 0xdf20 },
1851                 { 0x01, 0x100a },
1852                 { 0x00, 0xa0ff },
1853                 { 0x04, 0xf800 },
1854                 { 0x04, 0xf000 },
1855
1856                 { 0x1f, 0x0000 },
1857                 { 0x0b, 0x0000 },
1858                 { 0x00, 0x9200 }
1859         };
1860
1861         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1862 }
1863
1864 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
1865 {
1866         static const struct phy_reg phy_reg_init[] = {
1867                 { 0x1f, 0x0002 },
1868                 { 0x01, 0x90d0 },
1869                 { 0x1f, 0x0000 }
1870         };
1871
1872         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1873 }
1874
1875 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
1876 {
1877         struct pci_dev *pdev = tp->pci_dev;
1878         u16 vendor_id, device_id;
1879
1880         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1881         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1882
1883         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1884                 return;
1885
1886         rtl_writephy(tp, 0x1f, 0x0001);
1887         rtl_writephy(tp, 0x10, 0xf01b);
1888         rtl_writephy(tp, 0x1f, 0x0000);
1889 }
1890
1891 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
1892 {
1893         static const struct phy_reg phy_reg_init[] = {
1894                 { 0x1f, 0x0001 },
1895                 { 0x04, 0x0000 },
1896                 { 0x03, 0x00a1 },
1897                 { 0x02, 0x0008 },
1898                 { 0x01, 0x0120 },
1899                 { 0x00, 0x1000 },
1900                 { 0x04, 0x0800 },
1901                 { 0x04, 0x9000 },
1902                 { 0x03, 0x802f },
1903                 { 0x02, 0x4f02 },
1904                 { 0x01, 0x0409 },
1905                 { 0x00, 0xf099 },
1906                 { 0x04, 0x9800 },
1907                 { 0x04, 0xa000 },
1908                 { 0x03, 0xdf01 },
1909                 { 0x02, 0xdf20 },
1910                 { 0x01, 0xff95 },
1911                 { 0x00, 0xba00 },
1912                 { 0x04, 0xa800 },
1913                 { 0x04, 0xf000 },
1914                 { 0x03, 0xdf01 },
1915                 { 0x02, 0xdf20 },
1916                 { 0x01, 0x101a },
1917                 { 0x00, 0xa0ff },
1918                 { 0x04, 0xf800 },
1919                 { 0x04, 0x0000 },
1920                 { 0x1f, 0x0000 },
1921
1922                 { 0x1f, 0x0001 },
1923                 { 0x10, 0xf41b },
1924                 { 0x14, 0xfb54 },
1925                 { 0x18, 0xf5c7 },
1926                 { 0x1f, 0x0000 },
1927
1928                 { 0x1f, 0x0001 },
1929                 { 0x17, 0x0cc0 },
1930                 { 0x1f, 0x0000 }
1931         };
1932
1933         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1934
1935         rtl8169scd_hw_phy_config_quirk(tp);
1936 }
1937
1938 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
1939 {
1940         static const struct phy_reg phy_reg_init[] = {
1941                 { 0x1f, 0x0001 },
1942                 { 0x04, 0x0000 },
1943                 { 0x03, 0x00a1 },
1944                 { 0x02, 0x0008 },
1945                 { 0x01, 0x0120 },
1946                 { 0x00, 0x1000 },
1947                 { 0x04, 0x0800 },
1948                 { 0x04, 0x9000 },
1949                 { 0x03, 0x802f },
1950                 { 0x02, 0x4f02 },
1951                 { 0x01, 0x0409 },
1952                 { 0x00, 0xf099 },
1953                 { 0x04, 0x9800 },
1954                 { 0x04, 0xa000 },
1955                 { 0x03, 0xdf01 },
1956                 { 0x02, 0xdf20 },
1957                 { 0x01, 0xff95 },
1958                 { 0x00, 0xba00 },
1959                 { 0x04, 0xa800 },
1960                 { 0x04, 0xf000 },
1961                 { 0x03, 0xdf01 },
1962                 { 0x02, 0xdf20 },
1963                 { 0x01, 0x101a },
1964                 { 0x00, 0xa0ff },
1965                 { 0x04, 0xf800 },
1966                 { 0x04, 0x0000 },
1967                 { 0x1f, 0x0000 },
1968
1969                 { 0x1f, 0x0001 },
1970                 { 0x0b, 0x8480 },
1971                 { 0x1f, 0x0000 },
1972
1973                 { 0x1f, 0x0001 },
1974                 { 0x18, 0x67c7 },
1975                 { 0x04, 0x2000 },
1976                 { 0x03, 0x002f },
1977                 { 0x02, 0x4360 },
1978                 { 0x01, 0x0109 },
1979                 { 0x00, 0x3022 },
1980                 { 0x04, 0x2800 },
1981                 { 0x1f, 0x0000 },
1982
1983                 { 0x1f, 0x0001 },
1984                 { 0x17, 0x0cc0 },
1985                 { 0x1f, 0x0000 }
1986         };
1987
1988         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1989 }
1990
1991 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
1992 {
1993         static const struct phy_reg phy_reg_init[] = {
1994                 { 0x10, 0xf41b },
1995                 { 0x1f, 0x0000 }
1996         };
1997
1998         rtl_writephy(tp, 0x1f, 0x0001);
1999         rtl_patchphy(tp, 0x16, 1 << 0);
2000
2001         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2002 }
2003
2004 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2005 {
2006         static const struct phy_reg phy_reg_init[] = {
2007                 { 0x1f, 0x0001 },
2008                 { 0x10, 0xf41b },
2009                 { 0x1f, 0x0000 }
2010         };
2011
2012         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2013 }
2014
2015 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2016 {
2017         static const struct phy_reg phy_reg_init[] = {
2018                 { 0x1f, 0x0000 },
2019                 { 0x1d, 0x0f00 },
2020                 { 0x1f, 0x0002 },
2021                 { 0x0c, 0x1ec8 },
2022                 { 0x1f, 0x0000 }
2023         };
2024
2025         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2026 }
2027
2028 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2029 {
2030         static const struct phy_reg phy_reg_init[] = {
2031                 { 0x1f, 0x0001 },
2032                 { 0x1d, 0x3d98 },
2033                 { 0x1f, 0x0000 }
2034         };
2035
2036         rtl_writephy(tp, 0x1f, 0x0000);
2037         rtl_patchphy(tp, 0x14, 1 << 5);
2038         rtl_patchphy(tp, 0x0d, 1 << 5);
2039
2040         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2041 }
2042
2043 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2044 {
2045         static const struct phy_reg phy_reg_init[] = {
2046                 { 0x1f, 0x0001 },
2047                 { 0x12, 0x2300 },
2048                 { 0x1f, 0x0002 },
2049                 { 0x00, 0x88d4 },
2050                 { 0x01, 0x82b1 },
2051                 { 0x03, 0x7002 },
2052                 { 0x08, 0x9e30 },
2053                 { 0x09, 0x01f0 },
2054                 { 0x0a, 0x5500 },
2055                 { 0x0c, 0x00c8 },
2056                 { 0x1f, 0x0003 },
2057                 { 0x12, 0xc096 },
2058                 { 0x16, 0x000a },
2059                 { 0x1f, 0x0000 },
2060                 { 0x1f, 0x0000 },
2061                 { 0x09, 0x2000 },
2062                 { 0x09, 0x0000 }
2063         };
2064
2065         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2066
2067         rtl_patchphy(tp, 0x14, 1 << 5);
2068         rtl_patchphy(tp, 0x0d, 1 << 5);
2069         rtl_writephy(tp, 0x1f, 0x0000);
2070 }
2071
2072 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2073 {
2074         static const struct phy_reg phy_reg_init[] = {
2075                 { 0x1f, 0x0001 },
2076                 { 0x12, 0x2300 },
2077                 { 0x03, 0x802f },
2078                 { 0x02, 0x4f02 },
2079                 { 0x01, 0x0409 },
2080                 { 0x00, 0xf099 },
2081                 { 0x04, 0x9800 },
2082                 { 0x04, 0x9000 },
2083                 { 0x1d, 0x3d98 },
2084                 { 0x1f, 0x0002 },
2085                 { 0x0c, 0x7eb8 },
2086                 { 0x06, 0x0761 },
2087                 { 0x1f, 0x0003 },
2088                 { 0x16, 0x0f0a },
2089                 { 0x1f, 0x0000 }
2090         };
2091
2092         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2093
2094         rtl_patchphy(tp, 0x16, 1 << 0);
2095         rtl_patchphy(tp, 0x14, 1 << 5);
2096         rtl_patchphy(tp, 0x0d, 1 << 5);
2097         rtl_writephy(tp, 0x1f, 0x0000);
2098 }
2099
2100 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2101 {
2102         static const struct phy_reg phy_reg_init[] = {
2103                 { 0x1f, 0x0001 },
2104                 { 0x12, 0x2300 },
2105                 { 0x1d, 0x3d98 },
2106                 { 0x1f, 0x0002 },
2107                 { 0x0c, 0x7eb8 },
2108                 { 0x06, 0x5461 },
2109                 { 0x1f, 0x0003 },
2110                 { 0x16, 0x0f0a },
2111                 { 0x1f, 0x0000 }
2112         };
2113
2114         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2115
2116         rtl_patchphy(tp, 0x16, 1 << 0);
2117         rtl_patchphy(tp, 0x14, 1 << 5);
2118         rtl_patchphy(tp, 0x0d, 1 << 5);
2119         rtl_writephy(tp, 0x1f, 0x0000);
2120 }
2121
2122 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2123 {
2124         rtl8168c_3_hw_phy_config(tp);
2125 }
2126
2127 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2128 {
2129         static const struct phy_reg phy_reg_init_0[] = {
2130                 /* Channel Estimation */
2131                 { 0x1f, 0x0001 },
2132                 { 0x06, 0x4064 },
2133                 { 0x07, 0x2863 },
2134                 { 0x08, 0x059c },
2135                 { 0x09, 0x26b4 },
2136                 { 0x0a, 0x6a19 },
2137                 { 0x0b, 0xdcc8 },
2138                 { 0x10, 0xf06d },
2139                 { 0x14, 0x7f68 },
2140                 { 0x18, 0x7fd9 },
2141                 { 0x1c, 0xf0ff },
2142                 { 0x1d, 0x3d9c },
2143                 { 0x1f, 0x0003 },
2144                 { 0x12, 0xf49f },
2145                 { 0x13, 0x070b },
2146                 { 0x1a, 0x05ad },
2147                 { 0x14, 0x94c0 },
2148
2149                 /*
2150                  * Tx Error Issue
2151                  * enhance line driver power
2152                  */
2153                 { 0x1f, 0x0002 },
2154                 { 0x06, 0x5561 },
2155                 { 0x1f, 0x0005 },
2156                 { 0x05, 0x8332 },
2157                 { 0x06, 0x5561 },
2158
2159                 /*
2160                  * Can not link to 1Gbps with bad cable
2161                  * Decrease SNR threshold form 21.07dB to 19.04dB
2162                  */
2163                 { 0x1f, 0x0001 },
2164                 { 0x17, 0x0cc0 },
2165
2166                 { 0x1f, 0x0000 },
2167                 { 0x0d, 0xf880 }
2168         };
2169         void __iomem *ioaddr = tp->mmio_addr;
2170
2171         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2172
2173         /*
2174          * Rx Error Issue
2175          * Fine Tune Switching regulator parameter
2176          */
2177         rtl_writephy(tp, 0x1f, 0x0002);
2178         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2179         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2180
2181         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2182                 static const struct phy_reg phy_reg_init[] = {
2183                         { 0x1f, 0x0002 },
2184                         { 0x05, 0x669a },
2185                         { 0x1f, 0x0005 },
2186                         { 0x05, 0x8330 },
2187                         { 0x06, 0x669a },
2188                         { 0x1f, 0x0002 }
2189                 };
2190                 int val;
2191
2192                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2193
2194                 val = rtl_readphy(tp, 0x0d);
2195
2196                 if ((val & 0x00ff) != 0x006c) {
2197                         static const u32 set[] = {
2198                                 0x0065, 0x0066, 0x0067, 0x0068,
2199                                 0x0069, 0x006a, 0x006b, 0x006c
2200                         };
2201                         int i;
2202
2203                         rtl_writephy(tp, 0x1f, 0x0002);
2204
2205                         val &= 0xff00;
2206                         for (i = 0; i < ARRAY_SIZE(set); i++)
2207                                 rtl_writephy(tp, 0x0d, val | set[i]);
2208                 }
2209         } else {
2210                 static const struct phy_reg phy_reg_init[] = {
2211                         { 0x1f, 0x0002 },
2212                         { 0x05, 0x6662 },
2213                         { 0x1f, 0x0005 },
2214                         { 0x05, 0x8330 },
2215                         { 0x06, 0x6662 }
2216                 };
2217
2218                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2219         }
2220
2221         /* RSET couple improve */
2222         rtl_writephy(tp, 0x1f, 0x0002);
2223         rtl_patchphy(tp, 0x0d, 0x0300);
2224         rtl_patchphy(tp, 0x0f, 0x0010);
2225
2226         /* Fine tune PLL performance */
2227         rtl_writephy(tp, 0x1f, 0x0002);
2228         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2229         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2230
2231         rtl_writephy(tp, 0x1f, 0x0005);
2232         rtl_writephy(tp, 0x05, 0x001b);
2233         if ((rtl_readphy(tp, 0x06) != 0xbf00) ||
2234             (rtl_apply_firmware(tp, FIRMWARE_8168D_1) < 0)) {
2235                 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2236         }
2237
2238         rtl_writephy(tp, 0x1f, 0x0000);
2239 }
2240
2241 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2242 {
2243         static const struct phy_reg phy_reg_init_0[] = {
2244                 /* Channel Estimation */
2245                 { 0x1f, 0x0001 },
2246                 { 0x06, 0x4064 },
2247                 { 0x07, 0x2863 },
2248                 { 0x08, 0x059c },
2249                 { 0x09, 0x26b4 },
2250                 { 0x0a, 0x6a19 },
2251                 { 0x0b, 0xdcc8 },
2252                 { 0x10, 0xf06d },
2253                 { 0x14, 0x7f68 },
2254                 { 0x18, 0x7fd9 },
2255                 { 0x1c, 0xf0ff },
2256                 { 0x1d, 0x3d9c },
2257                 { 0x1f, 0x0003 },
2258                 { 0x12, 0xf49f },
2259                 { 0x13, 0x070b },
2260                 { 0x1a, 0x05ad },
2261                 { 0x14, 0x94c0 },
2262
2263                 /*
2264                  * Tx Error Issue
2265                  * enhance line driver power
2266                  */
2267                 { 0x1f, 0x0002 },
2268                 { 0x06, 0x5561 },
2269                 { 0x1f, 0x0005 },
2270                 { 0x05, 0x8332 },
2271                 { 0x06, 0x5561 },
2272
2273                 /*
2274                  * Can not link to 1Gbps with bad cable
2275                  * Decrease SNR threshold form 21.07dB to 19.04dB
2276                  */
2277                 { 0x1f, 0x0001 },
2278                 { 0x17, 0x0cc0 },
2279
2280                 { 0x1f, 0x0000 },
2281                 { 0x0d, 0xf880 }
2282         };
2283         void __iomem *ioaddr = tp->mmio_addr;
2284
2285         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2286
2287         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2288                 static const struct phy_reg phy_reg_init[] = {
2289                         { 0x1f, 0x0002 },
2290                         { 0x05, 0x669a },
2291                         { 0x1f, 0x0005 },
2292                         { 0x05, 0x8330 },
2293                         { 0x06, 0x669a },
2294
2295                         { 0x1f, 0x0002 }
2296                 };
2297                 int val;
2298
2299                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2300
2301                 val = rtl_readphy(tp, 0x0d);
2302                 if ((val & 0x00ff) != 0x006c) {
2303                         static const u32 set[] = {
2304                                 0x0065, 0x0066, 0x0067, 0x0068,
2305                                 0x0069, 0x006a, 0x006b, 0x006c
2306                         };
2307                         int i;
2308
2309                         rtl_writephy(tp, 0x1f, 0x0002);
2310
2311                         val &= 0xff00;
2312                         for (i = 0; i < ARRAY_SIZE(set); i++)
2313                                 rtl_writephy(tp, 0x0d, val | set[i]);
2314                 }
2315         } else {
2316                 static const struct phy_reg phy_reg_init[] = {
2317                         { 0x1f, 0x0002 },
2318                         { 0x05, 0x2642 },
2319                         { 0x1f, 0x0005 },
2320                         { 0x05, 0x8330 },
2321                         { 0x06, 0x2642 }
2322                 };
2323
2324                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2325         }
2326
2327         /* Fine tune PLL performance */
2328         rtl_writephy(tp, 0x1f, 0x0002);
2329         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2330         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2331
2332         /* Switching regulator Slew rate */
2333         rtl_writephy(tp, 0x1f, 0x0002);
2334         rtl_patchphy(tp, 0x0f, 0x0017);
2335
2336         rtl_writephy(tp, 0x1f, 0x0005);
2337         rtl_writephy(tp, 0x05, 0x001b);
2338         if ((rtl_readphy(tp, 0x06) != 0xb300) ||
2339             (rtl_apply_firmware(tp, FIRMWARE_8168D_2) < 0)) {
2340                 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2341         }
2342
2343         rtl_writephy(tp, 0x1f, 0x0000);
2344 }
2345
2346 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2347 {
2348         static const struct phy_reg phy_reg_init[] = {
2349                 { 0x1f, 0x0002 },
2350                 { 0x10, 0x0008 },
2351                 { 0x0d, 0x006c },
2352
2353                 { 0x1f, 0x0000 },
2354                 { 0x0d, 0xf880 },
2355
2356                 { 0x1f, 0x0001 },
2357                 { 0x17, 0x0cc0 },
2358
2359                 { 0x1f, 0x0001 },
2360                 { 0x0b, 0xa4d8 },
2361                 { 0x09, 0x281c },
2362                 { 0x07, 0x2883 },
2363                 { 0x0a, 0x6b35 },
2364                 { 0x1d, 0x3da4 },
2365                 { 0x1c, 0xeffd },
2366                 { 0x14, 0x7f52 },
2367                 { 0x18, 0x7fc6 },
2368                 { 0x08, 0x0601 },
2369                 { 0x06, 0x4063 },
2370                 { 0x10, 0xf074 },
2371                 { 0x1f, 0x0003 },
2372                 { 0x13, 0x0789 },
2373                 { 0x12, 0xf4bd },
2374                 { 0x1a, 0x04fd },
2375                 { 0x14, 0x84b0 },
2376                 { 0x1f, 0x0000 },
2377                 { 0x00, 0x9200 },
2378
2379                 { 0x1f, 0x0005 },
2380                 { 0x01, 0x0340 },
2381                 { 0x1f, 0x0001 },
2382                 { 0x04, 0x4000 },
2383                 { 0x03, 0x1d21 },
2384                 { 0x02, 0x0c32 },
2385                 { 0x01, 0x0200 },
2386                 { 0x00, 0x5554 },
2387                 { 0x04, 0x4800 },
2388                 { 0x04, 0x4000 },
2389                 { 0x04, 0xf000 },
2390                 { 0x03, 0xdf01 },
2391                 { 0x02, 0xdf20 },
2392                 { 0x01, 0x101a },
2393                 { 0x00, 0xa0ff },
2394                 { 0x04, 0xf800 },
2395                 { 0x04, 0xf000 },
2396                 { 0x1f, 0x0000 },
2397
2398                 { 0x1f, 0x0007 },
2399                 { 0x1e, 0x0023 },
2400                 { 0x16, 0x0000 },
2401                 { 0x1f, 0x0000 }
2402         };
2403
2404         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2405 }
2406
2407 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2408 {
2409         static const struct phy_reg phy_reg_init[] = {
2410                 { 0x1f, 0x0001 },
2411                 { 0x17, 0x0cc0 },
2412
2413                 { 0x1f, 0x0007 },
2414                 { 0x1e, 0x002d },
2415                 { 0x18, 0x0040 },
2416                 { 0x1f, 0x0000 }
2417         };
2418
2419         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2420         rtl_patchphy(tp, 0x0d, 1 << 5);
2421 }
2422
2423 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2424 {
2425         static const struct phy_reg phy_reg_init[] = {
2426                 { 0x1f, 0x0003 },
2427                 { 0x08, 0x441d },
2428                 { 0x01, 0x9100 },
2429                 { 0x1f, 0x0000 }
2430         };
2431
2432         rtl_writephy(tp, 0x1f, 0x0000);
2433         rtl_patchphy(tp, 0x11, 1 << 12);
2434         rtl_patchphy(tp, 0x19, 1 << 13);
2435         rtl_patchphy(tp, 0x10, 1 << 15);
2436
2437         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2438 }
2439
2440 static void rtl_hw_phy_config(struct net_device *dev)
2441 {
2442         struct rtl8169_private *tp = netdev_priv(dev);
2443
2444         rtl8169_print_mac_version(tp);
2445
2446         switch (tp->mac_version) {
2447         case RTL_GIGA_MAC_VER_01:
2448                 break;
2449         case RTL_GIGA_MAC_VER_02:
2450         case RTL_GIGA_MAC_VER_03:
2451                 rtl8169s_hw_phy_config(tp);
2452                 break;
2453         case RTL_GIGA_MAC_VER_04:
2454                 rtl8169sb_hw_phy_config(tp);
2455                 break;
2456         case RTL_GIGA_MAC_VER_05:
2457                 rtl8169scd_hw_phy_config(tp);
2458                 break;
2459         case RTL_GIGA_MAC_VER_06:
2460                 rtl8169sce_hw_phy_config(tp);
2461                 break;
2462         case RTL_GIGA_MAC_VER_07:
2463         case RTL_GIGA_MAC_VER_08:
2464         case RTL_GIGA_MAC_VER_09:
2465                 rtl8102e_hw_phy_config(tp);
2466                 break;
2467         case RTL_GIGA_MAC_VER_11:
2468                 rtl8168bb_hw_phy_config(tp);
2469                 break;
2470         case RTL_GIGA_MAC_VER_12:
2471                 rtl8168bef_hw_phy_config(tp);
2472                 break;
2473         case RTL_GIGA_MAC_VER_17:
2474                 rtl8168bef_hw_phy_config(tp);
2475                 break;
2476         case RTL_GIGA_MAC_VER_18:
2477                 rtl8168cp_1_hw_phy_config(tp);
2478                 break;
2479         case RTL_GIGA_MAC_VER_19:
2480                 rtl8168c_1_hw_phy_config(tp);
2481                 break;
2482         case RTL_GIGA_MAC_VER_20:
2483                 rtl8168c_2_hw_phy_config(tp);
2484                 break;
2485         case RTL_GIGA_MAC_VER_21:
2486                 rtl8168c_3_hw_phy_config(tp);
2487                 break;
2488         case RTL_GIGA_MAC_VER_22:
2489                 rtl8168c_4_hw_phy_config(tp);
2490                 break;
2491         case RTL_GIGA_MAC_VER_23:
2492         case RTL_GIGA_MAC_VER_24:
2493                 rtl8168cp_2_hw_phy_config(tp);
2494                 break;
2495         case RTL_GIGA_MAC_VER_25:
2496                 rtl8168d_1_hw_phy_config(tp);
2497                 break;
2498         case RTL_GIGA_MAC_VER_26:
2499                 rtl8168d_2_hw_phy_config(tp);
2500                 break;
2501         case RTL_GIGA_MAC_VER_27:
2502                 rtl8168d_3_hw_phy_config(tp);
2503                 break;
2504         case RTL_GIGA_MAC_VER_28:
2505                 rtl8168d_4_hw_phy_config(tp);
2506                 break;
2507
2508         default:
2509                 break;
2510         }
2511 }
2512
2513 static void rtl8169_phy_timer(unsigned long __opaque)
2514 {
2515         struct net_device *dev = (struct net_device *)__opaque;
2516         struct rtl8169_private *tp = netdev_priv(dev);
2517         struct timer_list *timer = &tp->timer;
2518         void __iomem *ioaddr = tp->mmio_addr;
2519         unsigned long timeout = RTL8169_PHY_TIMEOUT;
2520
2521         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2522
2523         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2524                 return;
2525
2526         spin_lock_irq(&tp->lock);
2527
2528         if (tp->phy_reset_pending(tp)) {
2529                 /*
2530                  * A busy loop could burn quite a few cycles on nowadays CPU.
2531                  * Let's delay the execution of the timer for a few ticks.
2532                  */
2533                 timeout = HZ/10;
2534                 goto out_mod_timer;
2535         }
2536
2537         if (tp->link_ok(ioaddr))
2538                 goto out_unlock;
2539
2540         netif_warn(tp, link, dev, "PHY reset until link up\n");
2541
2542         tp->phy_reset_enable(tp);
2543
2544 out_mod_timer:
2545         mod_timer(timer, jiffies + timeout);
2546 out_unlock:
2547         spin_unlock_irq(&tp->lock);
2548 }
2549
2550 static inline void rtl8169_delete_timer(struct net_device *dev)
2551 {
2552         struct rtl8169_private *tp = netdev_priv(dev);
2553         struct timer_list *timer = &tp->timer;
2554
2555         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2556                 return;
2557
2558         del_timer_sync(timer);
2559 }
2560
2561 static inline void rtl8169_request_timer(struct net_device *dev)
2562 {
2563         struct rtl8169_private *tp = netdev_priv(dev);
2564         struct timer_list *timer = &tp->timer;
2565
2566         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2567                 return;
2568
2569         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2570 }
2571
2572 #ifdef CONFIG_NET_POLL_CONTROLLER
2573 /*
2574  * Polling 'interrupt' - used by things like netconsole to send skbs
2575  * without having to re-enable interrupts. It's not called while
2576  * the interrupt routine is executing.
2577  */
2578 static void rtl8169_netpoll(struct net_device *dev)
2579 {
2580         struct rtl8169_private *tp = netdev_priv(dev);
2581         struct pci_dev *pdev = tp->pci_dev;
2582
2583         disable_irq(pdev->irq);
2584         rtl8169_interrupt(pdev->irq, dev);
2585         enable_irq(pdev->irq);
2586 }
2587 #endif
2588
2589 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2590                                   void __iomem *ioaddr)
2591 {
2592         iounmap(ioaddr);
2593         pci_release_regions(pdev);
2594         pci_clear_mwi(pdev);
2595         pci_disable_device(pdev);
2596         free_netdev(dev);
2597 }
2598
2599 static void rtl8169_phy_reset(struct net_device *dev,
2600                               struct rtl8169_private *tp)
2601 {
2602         unsigned int i;
2603
2604         tp->phy_reset_enable(tp);
2605         for (i = 0; i < 100; i++) {
2606                 if (!tp->phy_reset_pending(tp))
2607                         return;
2608                 msleep(1);
2609         }
2610         netif_err(tp, link, dev, "PHY reset failed\n");
2611 }
2612
2613 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2614 {
2615         void __iomem *ioaddr = tp->mmio_addr;
2616
2617         rtl_hw_phy_config(dev);
2618
2619         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2620                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2621                 RTL_W8(0x82, 0x01);
2622         }
2623
2624         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2625
2626         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2627                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2628
2629         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2630                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2631                 RTL_W8(0x82, 0x01);
2632                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2633                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2634         }
2635
2636         rtl8169_phy_reset(dev, tp);
2637
2638         /*
2639          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2640          * only 8101. Don't panic.
2641          */
2642         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
2643
2644         if (RTL_R8(PHYstatus) & TBI_Enable)
2645                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2646 }
2647
2648 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2649 {
2650         void __iomem *ioaddr = tp->mmio_addr;
2651         u32 high;
2652         u32 low;
2653
2654         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2655         high = addr[4] | (addr[5] << 8);
2656
2657         spin_lock_irq(&tp->lock);
2658
2659         RTL_W8(Cfg9346, Cfg9346_Unlock);
2660
2661         RTL_W32(MAC4, high);
2662         RTL_R32(MAC4);
2663
2664         RTL_W32(MAC0, low);
2665         RTL_R32(MAC0);
2666
2667         RTL_W8(Cfg9346, Cfg9346_Lock);
2668
2669         spin_unlock_irq(&tp->lock);
2670 }
2671
2672 static int rtl_set_mac_address(struct net_device *dev, void *p)
2673 {
2674         struct rtl8169_private *tp = netdev_priv(dev);
2675         struct sockaddr *addr = p;
2676
2677         if (!is_valid_ether_addr(addr->sa_data))
2678                 return -EADDRNOTAVAIL;
2679
2680         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2681
2682         rtl_rar_set(tp, dev->dev_addr);
2683
2684         return 0;
2685 }
2686
2687 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2688 {
2689         struct rtl8169_private *tp = netdev_priv(dev);
2690         struct mii_ioctl_data *data = if_mii(ifr);
2691
2692         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2693 }
2694
2695 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2696 {
2697         switch (cmd) {
2698         case SIOCGMIIPHY:
2699                 data->phy_id = 32; /* Internal PHY */
2700                 return 0;
2701
2702         case SIOCGMIIREG:
2703                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2704                 return 0;
2705
2706         case SIOCSMIIREG:
2707                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2708                 return 0;
2709         }
2710         return -EOPNOTSUPP;
2711 }
2712
2713 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2714 {
2715         return -EOPNOTSUPP;
2716 }
2717
2718 static const struct rtl_cfg_info {
2719         void (*hw_start)(struct net_device *);
2720         unsigned int region;
2721         unsigned int align;
2722         u16 intr_event;
2723         u16 napi_event;
2724         unsigned features;
2725         u8 default_ver;
2726 } rtl_cfg_infos [] = {
2727         [RTL_CFG_0] = {
2728                 .hw_start       = rtl_hw_start_8169,
2729                 .region         = 1,
2730                 .align          = 0,
2731                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2732                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2733                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2734                 .features       = RTL_FEATURE_GMII,
2735                 .default_ver    = RTL_GIGA_MAC_VER_01,
2736         },
2737         [RTL_CFG_1] = {
2738                 .hw_start       = rtl_hw_start_8168,
2739                 .region         = 2,
2740                 .align          = 8,
2741                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2742                                   TxErr | TxOK | RxOK | RxErr,
2743                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
2744                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2745                 .default_ver    = RTL_GIGA_MAC_VER_11,
2746         },
2747         [RTL_CFG_2] = {
2748                 .hw_start       = rtl_hw_start_8101,
2749                 .region         = 2,
2750                 .align          = 8,
2751                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2752                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2753                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2754                 .features       = RTL_FEATURE_MSI,
2755                 .default_ver    = RTL_GIGA_MAC_VER_13,
2756         }
2757 };
2758
2759 /* Cfg9346_Unlock assumed. */
2760 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2761                             const struct rtl_cfg_info *cfg)
2762 {
2763         unsigned msi = 0;
2764         u8 cfg2;
2765
2766         cfg2 = RTL_R8(Config2) & ~MSIEnable;
2767         if (cfg->features & RTL_FEATURE_MSI) {
2768                 if (pci_enable_msi(pdev)) {
2769                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2770                 } else {
2771                         cfg2 |= MSIEnable;
2772                         msi = RTL_FEATURE_MSI;
2773                 }
2774         }
2775         RTL_W8(Config2, cfg2);
2776         return msi;
2777 }
2778
2779 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2780 {
2781         if (tp->features & RTL_FEATURE_MSI) {
2782                 pci_disable_msi(pdev);
2783                 tp->features &= ~RTL_FEATURE_MSI;
2784         }
2785 }
2786
2787 static const struct net_device_ops rtl8169_netdev_ops = {
2788         .ndo_open               = rtl8169_open,
2789         .ndo_stop               = rtl8169_close,
2790         .ndo_get_stats          = rtl8169_get_stats,
2791         .ndo_start_xmit         = rtl8169_start_xmit,
2792         .ndo_tx_timeout         = rtl8169_tx_timeout,
2793         .ndo_validate_addr      = eth_validate_addr,
2794         .ndo_change_mtu         = rtl8169_change_mtu,
2795         .ndo_set_mac_address    = rtl_set_mac_address,
2796         .ndo_do_ioctl           = rtl8169_ioctl,
2797         .ndo_set_multicast_list = rtl_set_rx_mode,
2798 #ifdef CONFIG_R8169_VLAN
2799         .ndo_vlan_rx_register   = rtl8169_vlan_rx_register,
2800 #endif
2801 #ifdef CONFIG_NET_POLL_CONTROLLER
2802         .ndo_poll_controller    = rtl8169_netpoll,
2803 #endif
2804
2805 };
2806
2807 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2808 {
2809         struct mdio_ops *ops = &tp->mdio_ops;
2810
2811         switch (tp->mac_version) {
2812         case RTL_GIGA_MAC_VER_27:
2813                 ops->write      = r8168dp_1_mdio_write;
2814                 ops->read       = r8168dp_1_mdio_read;
2815                 break;
2816         case RTL_GIGA_MAC_VER_28:
2817                 ops->write      = r8168dp_2_mdio_write;
2818                 ops->read       = r8168dp_2_mdio_read;
2819                 break;
2820         default:
2821                 ops->write      = r8169_mdio_write;
2822                 ops->read       = r8169_mdio_read;
2823                 break;
2824         }
2825 }
2826
2827 static void r810x_phy_power_down(struct rtl8169_private *tp)
2828 {
2829         rtl_writephy(tp, 0x1f, 0x0000);
2830         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2831 }
2832
2833 static void r810x_phy_power_up(struct rtl8169_private *tp)
2834 {
2835         rtl_writephy(tp, 0x1f, 0x0000);
2836         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2837 }
2838
2839 static void r810x_pll_power_down(struct rtl8169_private *tp)
2840 {
2841         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2842                 rtl_writephy(tp, 0x1f, 0x0000);
2843                 rtl_writephy(tp, MII_BMCR, 0x0000);
2844                 return;
2845         }
2846
2847         r810x_phy_power_down(tp);
2848 }
2849
2850 static void r810x_pll_power_up(struct rtl8169_private *tp)
2851 {
2852         r810x_phy_power_up(tp);
2853 }
2854
2855 static void r8168_phy_power_up(struct rtl8169_private *tp)
2856 {
2857         rtl_writephy(tp, 0x1f, 0x0000);
2858         rtl_writephy(tp, 0x0e, 0x0000);
2859         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2860 }
2861
2862 static void r8168_phy_power_down(struct rtl8169_private *tp)
2863 {
2864         rtl_writephy(tp, 0x1f, 0x0000);
2865         rtl_writephy(tp, 0x0e, 0x0200);
2866         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2867 }
2868
2869 static void r8168_pll_power_down(struct rtl8169_private *tp)
2870 {
2871         void __iomem *ioaddr = tp->mmio_addr;
2872
2873         if (((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
2874              (tp->mac_version == RTL_GIGA_MAC_VER_28)) &&
2875             (ocp_read(tp, 0x0f, 0x0010) & 0x00008000)) {
2876                 return;
2877         }
2878
2879         if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
2880              (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
2881             (RTL_R16(CPlusCmd) & ASF)) {
2882                 return;
2883         }
2884
2885         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2886                 rtl_writephy(tp, 0x1f, 0x0000);
2887                 rtl_writephy(tp, MII_BMCR, 0x0000);
2888
2889                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
2890                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2891                 return;
2892         }
2893
2894         r8168_phy_power_down(tp);
2895
2896         switch (tp->mac_version) {
2897         case RTL_GIGA_MAC_VER_25:
2898         case RTL_GIGA_MAC_VER_26:
2899         case RTL_GIGA_MAC_VER_27:
2900         case RTL_GIGA_MAC_VER_28:
2901                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
2902                 break;
2903         }
2904 }
2905
2906 static void r8168_pll_power_up(struct rtl8169_private *tp)
2907 {
2908         void __iomem *ioaddr = tp->mmio_addr;
2909
2910         if (((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
2911              (tp->mac_version == RTL_GIGA_MAC_VER_28)) &&
2912             (ocp_read(tp, 0x0f, 0x0010) & 0x00008000)) {
2913                 return;
2914         }
2915
2916         switch (tp->mac_version) {
2917         case RTL_GIGA_MAC_VER_25:
2918         case RTL_GIGA_MAC_VER_26:
2919         case RTL_GIGA_MAC_VER_27:
2920         case RTL_GIGA_MAC_VER_28:
2921                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
2922                 break;
2923         }
2924
2925         r8168_phy_power_up(tp);
2926 }
2927
2928 static void rtl_pll_power_op(struct rtl8169_private *tp,
2929                              void (*op)(struct rtl8169_private *))
2930 {
2931         if (op)
2932                 op(tp);
2933 }
2934
2935 static void rtl_pll_power_down(struct rtl8169_private *tp)
2936 {
2937         rtl_pll_power_op(tp, tp->pll_power_ops.down);
2938 }
2939
2940 static void rtl_pll_power_up(struct rtl8169_private *tp)
2941 {
2942         rtl_pll_power_op(tp, tp->pll_power_ops.up);
2943 }
2944
2945 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
2946 {
2947         struct pll_power_ops *ops = &tp->pll_power_ops;
2948
2949         switch (tp->mac_version) {
2950         case RTL_GIGA_MAC_VER_07:
2951         case RTL_GIGA_MAC_VER_08:
2952         case RTL_GIGA_MAC_VER_09:
2953         case RTL_GIGA_MAC_VER_10:
2954         case RTL_GIGA_MAC_VER_16:
2955                 ops->down       = r810x_pll_power_down;
2956                 ops->up         = r810x_pll_power_up;
2957                 break;
2958
2959         case RTL_GIGA_MAC_VER_11:
2960         case RTL_GIGA_MAC_VER_12:
2961         case RTL_GIGA_MAC_VER_17:
2962         case RTL_GIGA_MAC_VER_18:
2963         case RTL_GIGA_MAC_VER_19:
2964         case RTL_GIGA_MAC_VER_20:
2965         case RTL_GIGA_MAC_VER_21:
2966         case RTL_GIGA_MAC_VER_22:
2967         case RTL_GIGA_MAC_VER_23:
2968         case RTL_GIGA_MAC_VER_24:
2969         case RTL_GIGA_MAC_VER_25:
2970         case RTL_GIGA_MAC_VER_26:
2971         case RTL_GIGA_MAC_VER_27:
2972         case RTL_GIGA_MAC_VER_28:
2973                 ops->down       = r8168_pll_power_down;
2974                 ops->up         = r8168_pll_power_up;
2975                 break;
2976
2977         default:
2978                 ops->down       = NULL;
2979                 ops->up         = NULL;
2980                 break;
2981         }
2982 }
2983
2984 static int __devinit
2985 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2986 {
2987         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2988         const unsigned int region = cfg->region;
2989         struct rtl8169_private *tp;
2990         struct mii_if_info *mii;
2991         struct net_device *dev;
2992         void __iomem *ioaddr;
2993         unsigned int i;
2994         int rc;
2995
2996         if (netif_msg_drv(&debug)) {
2997                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2998                        MODULENAME, RTL8169_VERSION);
2999         }
3000
3001         dev = alloc_etherdev(sizeof (*tp));
3002         if (!dev) {
3003                 if (netif_msg_drv(&debug))
3004                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3005                 rc = -ENOMEM;
3006                 goto out;
3007         }
3008
3009         SET_NETDEV_DEV(dev, &pdev->dev);
3010         dev->netdev_ops = &rtl8169_netdev_ops;
3011         tp = netdev_priv(dev);
3012         tp->dev = dev;
3013         tp->pci_dev = pdev;
3014         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3015
3016         mii = &tp->mii;
3017         mii->dev = dev;
3018         mii->mdio_read = rtl_mdio_read;
3019         mii->mdio_write = rtl_mdio_write;
3020         mii->phy_id_mask = 0x1f;
3021         mii->reg_num_mask = 0x1f;
3022         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3023
3024         /* disable ASPM completely as that cause random device stop working
3025          * problems as well as full system hangs for some PCIe devices users */
3026         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3027                                      PCIE_LINK_STATE_CLKPM);
3028
3029         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3030         rc = pci_enable_device(pdev);
3031         if (rc < 0) {
3032                 netif_err(tp, probe, dev, "enable failure\n");
3033                 goto err_out_free_dev_1;
3034         }
3035
3036         if (pci_set_mwi(pdev) < 0)
3037                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3038
3039         /* make sure PCI base addr 1 is MMIO */
3040         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3041                 netif_err(tp, probe, dev,
3042                           "region #%d not an MMIO resource, aborting\n",
3043                           region);
3044                 rc = -ENODEV;
3045                 goto err_out_mwi_2;
3046         }
3047
3048         /* check for weird/broken PCI region reporting */
3049         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3050                 netif_err(tp, probe, dev,
3051                           "Invalid PCI region size(s), aborting\n");
3052                 rc = -ENODEV;
3053                 goto err_out_mwi_2;
3054         }
3055
3056         rc = pci_request_regions(pdev, MODULENAME);
3057         if (rc < 0) {
3058                 netif_err(tp, probe, dev, "could not request regions\n");
3059                 goto err_out_mwi_2;
3060         }
3061
3062         tp->cp_cmd = RxChkSum;
3063
3064         if ((sizeof(dma_addr_t) > 4) &&
3065             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3066                 tp->cp_cmd |= PCIDAC;
3067                 dev->features |= NETIF_F_HIGHDMA;
3068         } else {
3069                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3070                 if (rc < 0) {
3071                         netif_err(tp, probe, dev, "DMA configuration failed\n");
3072                         goto err_out_free_res_3;
3073                 }
3074         }
3075
3076         /* ioremap MMIO region */
3077         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3078         if (!ioaddr) {
3079                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3080                 rc = -EIO;
3081                 goto err_out_free_res_3;
3082         }
3083
3084         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3085         if (!tp->pcie_cap)
3086                 netif_info(tp, probe, dev, "no PCI Express capability\n");
3087
3088         RTL_W16(IntrMask, 0x0000);
3089
3090         /* Soft reset the chip. */
3091         RTL_W8(ChipCmd, CmdReset);
3092
3093         /* Check that the chip has finished the reset. */
3094         for (i = 0; i < 100; i++) {
3095                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3096                         break;
3097                 msleep_interruptible(1);
3098         }
3099
3100         RTL_W16(IntrStatus, 0xffff);
3101
3102         pci_set_master(pdev);
3103
3104         /* Identify chip attached to board */
3105         rtl8169_get_mac_version(tp, ioaddr);
3106
3107         rtl_init_mdio_ops(tp);
3108         rtl_init_pll_power_ops(tp);
3109
3110         /* Use appropriate default if unknown */
3111         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3112                 netif_notice(tp, probe, dev,
3113                              "unknown MAC, using family default\n");
3114                 tp->mac_version = cfg->default_ver;
3115         }
3116
3117         rtl8169_print_mac_version(tp);
3118
3119         for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
3120                 if (tp->mac_version == rtl_chip_info[i].mac_version)
3121                         break;
3122         }
3123         if (i == ARRAY_SIZE(rtl_chip_info)) {
3124                 dev_err(&pdev->dev,
3125                         "driver bug, MAC version not found in rtl_chip_info\n");
3126                 goto err_out_msi_4;
3127         }
3128         tp->chipset = i;
3129
3130         RTL_W8(Cfg9346, Cfg9346_Unlock);
3131         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3132         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3133         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3134                 tp->features |= RTL_FEATURE_WOL;
3135         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3136                 tp->features |= RTL_FEATURE_WOL;
3137         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3138         RTL_W8(Cfg9346, Cfg9346_Lock);
3139
3140         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3141             (RTL_R8(PHYstatus) & TBI_Enable)) {
3142                 tp->set_speed = rtl8169_set_speed_tbi;
3143                 tp->get_settings = rtl8169_gset_tbi;
3144                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3145                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3146                 tp->link_ok = rtl8169_tbi_link_ok;
3147                 tp->do_ioctl = rtl_tbi_ioctl;
3148
3149                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3150         } else {
3151                 tp->set_speed = rtl8169_set_speed_xmii;
3152                 tp->get_settings = rtl8169_gset_xmii;
3153                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3154                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3155                 tp->link_ok = rtl8169_xmii_link_ok;
3156                 tp->do_ioctl = rtl_xmii_ioctl;
3157         }
3158
3159         spin_lock_init(&tp->lock);
3160
3161         tp->mmio_addr = ioaddr;
3162
3163         /* Get MAC address */
3164         for (i = 0; i < MAC_ADDR_LEN; i++)
3165                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3166         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3167
3168         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3169         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3170         dev->irq = pdev->irq;
3171         dev->base_addr = (unsigned long) ioaddr;
3172
3173         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3174
3175 #ifdef CONFIG_R8169_VLAN
3176         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3177 #endif
3178         dev->features |= NETIF_F_GRO;
3179
3180         tp->intr_mask = 0xffff;
3181         tp->hw_start = cfg->hw_start;
3182         tp->intr_event = cfg->intr_event;
3183         tp->napi_event = cfg->napi_event;
3184
3185         init_timer(&tp->timer);
3186         tp->timer.data = (unsigned long) dev;
3187         tp->timer.function = rtl8169_phy_timer;
3188
3189         rc = register_netdev(dev);
3190         if (rc < 0)
3191                 goto err_out_msi_4;
3192
3193         pci_set_drvdata(pdev, dev);
3194
3195         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3196                    rtl_chip_info[tp->chipset].name,
3197                    dev->base_addr, dev->dev_addr,
3198                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3199
3200         if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3201             (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
3202                 rtl8168_driver_start(tp);
3203         }
3204
3205         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3206
3207         if (pci_dev_run_wake(pdev))
3208                 pm_runtime_put_noidle(&pdev->dev);
3209
3210         netif_carrier_off(dev);
3211
3212 out:
3213         return rc;
3214
3215 err_out_msi_4:
3216         rtl_disable_msi(pdev, tp);
3217         iounmap(ioaddr);
3218 err_out_free_res_3:
3219         pci_release_regions(pdev);
3220 err_out_mwi_2:
3221         pci_clear_mwi(pdev);
3222         pci_disable_device(pdev);
3223 err_out_free_dev_1:
3224         free_netdev(dev);
3225         goto out;
3226 }
3227
3228 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3229 {
3230         struct net_device *dev = pci_get_drvdata(pdev);
3231         struct rtl8169_private *tp = netdev_priv(dev);
3232
3233         if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3234             (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
3235                 rtl8168_driver_stop(tp);
3236         }
3237
3238         cancel_delayed_work_sync(&tp->task);
3239
3240         rtl_release_firmware(tp);
3241
3242         unregister_netdev(dev);
3243
3244         if (pci_dev_run_wake(pdev))
3245                 pm_runtime_get_noresume(&pdev->dev);
3246
3247         /* restore original MAC address */
3248         rtl_rar_set(tp, dev->perm_addr);
3249
3250         rtl_disable_msi(pdev, tp);
3251         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3252         pci_set_drvdata(pdev, NULL);
3253 }
3254
3255 static int rtl8169_open(struct net_device *dev)
3256 {
3257         struct rtl8169_private *tp = netdev_priv(dev);
3258         void __iomem *ioaddr = tp->mmio_addr;
3259         struct pci_dev *pdev = tp->pci_dev;
3260         int retval = -ENOMEM;
3261
3262         pm_runtime_get_sync(&pdev->dev);
3263
3264         /*
3265          * Rx and Tx desscriptors needs 256 bytes alignment.
3266          * dma_alloc_coherent provides more.
3267          */
3268         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3269                                              &tp->TxPhyAddr, GFP_KERNEL);
3270         if (!tp->TxDescArray)
3271                 goto err_pm_runtime_put;
3272
3273         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3274                                              &tp->RxPhyAddr, GFP_KERNEL);
3275         if (!tp->RxDescArray)
3276                 goto err_free_tx_0;
3277
3278         retval = rtl8169_init_ring(dev);
3279         if (retval < 0)
3280                 goto err_free_rx_1;
3281
3282         INIT_DELAYED_WORK(&tp->task, NULL);
3283
3284         smp_mb();
3285
3286         retval = request_irq(dev->irq, rtl8169_interrupt,
3287                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3288                              dev->name, dev);
3289         if (retval < 0)
3290                 goto err_release_ring_2;
3291
3292         napi_enable(&tp->napi);
3293
3294         rtl8169_init_phy(dev, tp);
3295
3296         /*
3297          * Pretend we are using VLANs; This bypasses a nasty bug where
3298          * Interrupts stop flowing on high load on 8110SCd controllers.
3299          */
3300         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3301                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3302
3303         rtl_pll_power_up(tp);
3304
3305         rtl_hw_start(dev);
3306
3307         rtl8169_request_timer(dev);
3308
3309         tp->saved_wolopts = 0;
3310         pm_runtime_put_noidle(&pdev->dev);
3311
3312         rtl8169_check_link_status(dev, tp, ioaddr);
3313 out:
3314         return retval;
3315
3316 err_release_ring_2:
3317         rtl8169_rx_clear(tp);
3318 err_free_rx_1:
3319         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3320                           tp->RxPhyAddr);
3321         tp->RxDescArray = NULL;
3322 err_free_tx_0:
3323         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3324                           tp->TxPhyAddr);
3325         tp->TxDescArray = NULL;
3326 err_pm_runtime_put:
3327         pm_runtime_put_noidle(&pdev->dev);
3328         goto out;
3329 }
3330
3331 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3332 {
3333         void __iomem *ioaddr = tp->mmio_addr;
3334
3335         /* Disable interrupts */
3336         rtl8169_irq_mask_and_ack(ioaddr);
3337
3338         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3339             tp->mac_version == RTL_GIGA_MAC_VER_28) {
3340                 while (RTL_R8(TxPoll) & NPQ)
3341                         udelay(20);
3342
3343         }
3344
3345         /* Reset the chipset */
3346         RTL_W8(ChipCmd, CmdReset);
3347
3348         /* PCI commit */
3349         RTL_R8(ChipCmd);
3350 }
3351
3352 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3353 {
3354         void __iomem *ioaddr = tp->mmio_addr;
3355         u32 cfg = rtl8169_rx_config;
3356
3357         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3358         RTL_W32(RxConfig, cfg);
3359
3360         /* Set DMA burst size and Interframe Gap Time */
3361         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3362                 (InterFrameGap << TxInterFrameGapShift));
3363 }
3364
3365 static void rtl_hw_start(struct net_device *dev)
3366 {
3367         struct rtl8169_private *tp = netdev_priv(dev);
3368         void __iomem *ioaddr = tp->mmio_addr;
3369         unsigned int i;
3370
3371         /* Soft reset the chip. */
3372         RTL_W8(ChipCmd, CmdReset);
3373
3374         /* Check that the chip has finished the reset. */
3375         for (i = 0; i < 100; i++) {
3376                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3377                         break;
3378                 msleep_interruptible(1);
3379         }
3380
3381         tp->hw_start(dev);
3382
3383         netif_start_queue(dev);
3384 }
3385
3386
3387 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3388                                          void __iomem *ioaddr)
3389 {
3390         /*
3391          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3392          * register to be written before TxDescAddrLow to work.
3393          * Switching from MMIO to I/O access fixes the issue as well.
3394          */
3395         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3396         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3397         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3398         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3399 }
3400
3401 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3402 {
3403         u16 cmd;
3404
3405         cmd = RTL_R16(CPlusCmd);
3406         RTL_W16(CPlusCmd, cmd);
3407         return cmd;
3408 }
3409
3410 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3411 {
3412         /* Low hurts. Let's disable the filtering. */
3413         RTL_W16(RxMaxSize, rx_buf_sz + 1);
3414 }
3415
3416 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3417 {
3418         static const struct {
3419                 u32 mac_version;
3420                 u32 clk;
3421                 u32 val;
3422         } cfg2_info [] = {
3423                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3424                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3425                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3426                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3427         }, *p = cfg2_info;
3428         unsigned int i;
3429         u32 clk;
3430
3431         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3432         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3433                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3434                         RTL_W32(0x7c, p->val);
3435                         break;
3436                 }
3437         }
3438 }
3439
3440 static void rtl_hw_start_8169(struct net_device *dev)
3441 {
3442         struct rtl8169_private *tp = netdev_priv(dev);
3443         void __iomem *ioaddr = tp->mmio_addr;
3444         struct pci_dev *pdev = tp->pci_dev;
3445
3446         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3447                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3448                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3449         }
3450
3451         RTL_W8(Cfg9346, Cfg9346_Unlock);
3452         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3453             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3454             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3455             (tp->mac_version == RTL_GIGA_MAC_VER_04))
3456                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3457
3458         RTL_W8(EarlyTxThres, NoEarlyTx);
3459
3460         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3461
3462         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3463             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3464             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3465             (tp->mac_version == RTL_GIGA_MAC_VER_04))
3466                 rtl_set_rx_tx_config_registers(tp);
3467
3468         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3469
3470         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3471             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3472                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3473                         "Bit-3 and bit-14 MUST be 1\n");
3474                 tp->cp_cmd |= (1 << 14);
3475         }
3476
3477         RTL_W16(CPlusCmd, tp->cp_cmd);
3478
3479         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3480
3481         /*
3482          * Undocumented corner. Supposedly:
3483          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3484          */
3485         RTL_W16(IntrMitigate, 0x0000);
3486
3487         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3488
3489         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3490             (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3491             (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3492             (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3493                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3494                 rtl_set_rx_tx_config_registers(tp);
3495         }
3496
3497         RTL_W8(Cfg9346, Cfg9346_Lock);
3498
3499         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3500         RTL_R8(IntrMask);
3501
3502         RTL_W32(RxMissed, 0);
3503
3504         rtl_set_rx_mode(dev);
3505
3506         /* no early-rx interrupts */
3507         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3508
3509         /* Enable all known interrupts by setting the interrupt mask. */
3510         RTL_W16(IntrMask, tp->intr_event);
3511 }
3512
3513 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3514 {
3515         struct net_device *dev = pci_get_drvdata(pdev);
3516         struct rtl8169_private *tp = netdev_priv(dev);
3517         int cap = tp->pcie_cap;
3518
3519         if (cap) {
3520                 u16 ctl;
3521
3522                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3523                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3524                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3525         }
3526 }
3527
3528 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3529 {
3530         u32 csi;
3531
3532         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3533         rtl_csi_write(ioaddr, 0x070c, csi | bits);
3534 }
3535
3536 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3537 {
3538         rtl_csi_access_enable(ioaddr, 0x17000000);
3539 }
3540
3541 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3542 {
3543         rtl_csi_access_enable(ioaddr, 0x27000000);
3544 }
3545
3546 struct ephy_info {
3547         unsigned int offset;
3548         u16 mask;
3549         u16 bits;
3550 };
3551
3552 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3553 {
3554         u16 w;
3555
3556         while (len-- > 0) {
3557                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3558                 rtl_ephy_write(ioaddr, e->offset, w);
3559                 e++;
3560         }
3561 }
3562
3563 static void rtl_disable_clock_request(struct pci_dev *pdev)
3564 {
3565         struct net_device *dev = pci_get_drvdata(pdev);
3566         struct rtl8169_private *tp = netdev_priv(dev);
3567         int cap = tp->pcie_cap;
3568
3569         if (cap) {
3570                 u16 ctl;
3571
3572                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3573                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3574                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3575         }
3576 }
3577
3578 static void rtl_enable_clock_request(struct pci_dev *pdev)
3579 {
3580         struct net_device *dev = pci_get_drvdata(pdev);
3581         struct rtl8169_private *tp = netdev_priv(dev);
3582         int cap = tp->pcie_cap;
3583
3584         if (cap) {
3585                 u16 ctl;
3586
3587                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3588                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3589                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3590         }
3591 }
3592
3593 #define R8168_CPCMD_QUIRK_MASK (\
3594         EnableBist | \
3595         Mac_dbgo_oe | \
3596         Force_half_dup | \
3597         Force_rxflow_en | \
3598         Force_txflow_en | \
3599         Cxpl_dbg_sel | \
3600         ASF | \
3601         PktCntrDisable | \
3602         Mac_dbgo_sel)
3603
3604 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3605 {
3606         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3607
3608         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3609
3610         rtl_tx_performance_tweak(pdev,
3611                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3612 }
3613
3614 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3615 {
3616         rtl_hw_start_8168bb(ioaddr, pdev);
3617
3618         RTL_W8(MaxTxPacketSize, TxPacketMax);
3619
3620         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3621 }
3622
3623 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3624 {
3625         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3626
3627         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3628
3629         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3630
3631         rtl_disable_clock_request(pdev);
3632
3633         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3634 }
3635
3636 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3637 {
3638         static const struct ephy_info e_info_8168cp[] = {
3639                 { 0x01, 0,      0x0001 },
3640                 { 0x02, 0x0800, 0x1000 },
3641                 { 0x03, 0,      0x0042 },
3642                 { 0x06, 0x0080, 0x0000 },
3643                 { 0x07, 0,      0x2000 }
3644         };
3645
3646         rtl_csi_access_enable_2(ioaddr);
3647
3648         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3649
3650         __rtl_hw_start_8168cp(ioaddr, pdev);
3651 }
3652
3653 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3654 {
3655         rtl_csi_access_enable_2(ioaddr);
3656
3657         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3658
3659         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3660
3661         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3662 }
3663
3664 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3665 {
3666         rtl_csi_access_enable_2(ioaddr);
3667
3668         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3669
3670         /* Magic. */
3671         RTL_W8(DBG_REG, 0x20);
3672
3673         RTL_W8(MaxTxPacketSize, TxPacketMax);
3674
3675         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3676
3677         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3678 }
3679
3680 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3681 {
3682         static const struct ephy_info e_info_8168c_1[] = {
3683                 { 0x02, 0x0800, 0x1000 },
3684                 { 0x03, 0,      0x0002 },
3685                 { 0x06, 0x0080, 0x0000 }
3686         };
3687
3688         rtl_csi_access_enable_2(ioaddr);
3689
3690         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3691
3692         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3693
3694         __rtl_hw_start_8168cp(ioaddr, pdev);
3695 }
3696
3697 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3698 {
3699         static const struct ephy_info e_info_8168c_2[] = {
3700                 { 0x01, 0,      0x0001 },
3701                 { 0x03, 0x0400, 0x0220 }
3702         };
3703
3704         rtl_csi_access_enable_2(ioaddr);
3705
3706         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3707
3708         __rtl_hw_start_8168cp(ioaddr, pdev);
3709 }
3710
3711 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3712 {
3713         rtl_hw_start_8168c_2(ioaddr, pdev);
3714 }
3715
3716 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3717 {
3718         rtl_csi_access_enable_2(ioaddr);
3719
3720         __rtl_hw_start_8168cp(ioaddr, pdev);
3721 }
3722
3723 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3724 {
3725         rtl_csi_access_enable_2(ioaddr);
3726
3727         rtl_disable_clock_request(pdev);
3728
3729         RTL_W8(MaxTxPacketSize, TxPacketMax);
3730
3731         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3732
3733         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3734 }
3735
3736 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
3737 {
3738         static const struct ephy_info e_info_8168d_4[] = {
3739                 { 0x0b, ~0,     0x48 },
3740                 { 0x19, 0x20,   0x50 },
3741                 { 0x0c, ~0,     0x20 }
3742         };
3743         int i;
3744
3745         rtl_csi_access_enable_1(ioaddr);
3746
3747         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3748
3749         RTL_W8(MaxTxPacketSize, TxPacketMax);
3750
3751         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
3752                 const struct ephy_info *e = e_info_8168d_4 + i;
3753                 u16 w;
3754
3755                 w = rtl_ephy_read(ioaddr, e->offset);
3756                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
3757         }
3758
3759         rtl_enable_clock_request(pdev);
3760 }
3761
3762 static void rtl_hw_start_8168(struct net_device *dev)
3763 {
3764         struct rtl8169_private *tp = netdev_priv(dev);
3765         void __iomem *ioaddr = tp->mmio_addr;
3766         struct pci_dev *pdev = tp->pci_dev;
3767
3768         RTL_W8(Cfg9346, Cfg9346_Unlock);
3769
3770         RTL_W8(MaxTxPacketSize, TxPacketMax);
3771
3772         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3773
3774         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3775
3776         RTL_W16(CPlusCmd, tp->cp_cmd);
3777
3778         RTL_W16(IntrMitigate, 0x5151);
3779
3780         /* Work around for RxFIFO overflow. */
3781         if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
3782             tp->mac_version == RTL_GIGA_MAC_VER_22) {
3783                 tp->intr_event |= RxFIFOOver | PCSTimeout;
3784                 tp->intr_event &= ~RxOverflow;
3785         }
3786
3787         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3788
3789         rtl_set_rx_mode(dev);
3790
3791         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3792                 (InterFrameGap << TxInterFrameGapShift));
3793
3794         RTL_R8(IntrMask);
3795
3796         switch (tp->mac_version) {
3797         case RTL_GIGA_MAC_VER_11:
3798                 rtl_hw_start_8168bb(ioaddr, pdev);
3799         break;
3800
3801         case RTL_GIGA_MAC_VER_12:
3802         case RTL_GIGA_MAC_VER_17:
3803                 rtl_hw_start_8168bef(ioaddr, pdev);
3804         break;
3805
3806         case RTL_GIGA_MAC_VER_18:
3807                 rtl_hw_start_8168cp_1(ioaddr, pdev);
3808         break;
3809
3810         case RTL_GIGA_MAC_VER_19:
3811                 rtl_hw_start_8168c_1(ioaddr, pdev);
3812         break;
3813
3814         case RTL_GIGA_MAC_VER_20:
3815                 rtl_hw_start_8168c_2(ioaddr, pdev);
3816         break;
3817
3818         case RTL_GIGA_MAC_VER_21:
3819                 rtl_hw_start_8168c_3(ioaddr, pdev);
3820         break;
3821
3822         case RTL_GIGA_MAC_VER_22:
3823                 rtl_hw_start_8168c_4(ioaddr, pdev);
3824         break;
3825
3826         case RTL_GIGA_MAC_VER_23:
3827                 rtl_hw_start_8168cp_2(ioaddr, pdev);
3828         break;
3829
3830         case RTL_GIGA_MAC_VER_24:
3831                 rtl_hw_start_8168cp_3(ioaddr, pdev);
3832         break;
3833
3834         case RTL_GIGA_MAC_VER_25:
3835         case RTL_GIGA_MAC_VER_26:
3836         case RTL_GIGA_MAC_VER_27:
3837                 rtl_hw_start_8168d(ioaddr, pdev);
3838         break;
3839
3840         case RTL_GIGA_MAC_VER_28:
3841                 rtl_hw_start_8168d_4(ioaddr, pdev);
3842         break;
3843
3844         default:
3845                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3846                         dev->name, tp->mac_version);
3847         break;
3848         }
3849
3850         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3851
3852         RTL_W8(Cfg9346, Cfg9346_Lock);
3853
3854         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3855
3856         RTL_W16(IntrMask, tp->intr_event);
3857 }
3858
3859 #define R810X_CPCMD_QUIRK_MASK (\
3860         EnableBist | \
3861         Mac_dbgo_oe | \
3862         Force_half_dup | \
3863         Force_rxflow_en | \
3864         Force_txflow_en | \
3865         Cxpl_dbg_sel | \
3866         ASF | \
3867         PktCntrDisable | \
3868         Mac_dbgo_sel)
3869
3870 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3871 {
3872         static const struct ephy_info e_info_8102e_1[] = {
3873                 { 0x01, 0, 0x6e65 },
3874                 { 0x02, 0, 0x091f },
3875                 { 0x03, 0, 0xc2f9 },
3876                 { 0x06, 0, 0xafb5 },
3877                 { 0x07, 0, 0x0e00 },
3878                 { 0x19, 0, 0xec80 },
3879                 { 0x01, 0, 0x2e65 },
3880                 { 0x01, 0, 0x6e65 }
3881         };
3882         u8 cfg1;
3883
3884         rtl_csi_access_enable_2(ioaddr);
3885
3886         RTL_W8(DBG_REG, FIX_NAK_1);
3887
3888         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3889
3890         RTL_W8(Config1,
3891                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3892         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3893
3894         cfg1 = RTL_R8(Config1);
3895         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3896                 RTL_W8(Config1, cfg1 & ~LEDS0);
3897
3898         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3899 }
3900
3901 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3902 {
3903         rtl_csi_access_enable_2(ioaddr);
3904
3905         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3906
3907         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3908         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3909 }
3910
3911 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3912 {
3913         rtl_hw_start_8102e_2(ioaddr, pdev);
3914
3915         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3916 }
3917
3918 static void rtl_hw_start_8101(struct net_device *dev)
3919 {
3920         struct rtl8169_private *tp = netdev_priv(dev);
3921         void __iomem *ioaddr = tp->mmio_addr;
3922         struct pci_dev *pdev = tp->pci_dev;
3923
3924         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3925             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
3926                 int cap = tp->pcie_cap;
3927
3928                 if (cap) {
3929                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3930                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
3931                 }
3932         }
3933
3934         RTL_W8(Cfg9346, Cfg9346_Unlock);
3935
3936         switch (tp->mac_version) {
3937         case RTL_GIGA_MAC_VER_07:
3938                 rtl_hw_start_8102e_1(ioaddr, pdev);
3939                 break;
3940
3941         case RTL_GIGA_MAC_VER_08:
3942                 rtl_hw_start_8102e_3(ioaddr, pdev);
3943                 break;
3944
3945         case RTL_GIGA_MAC_VER_09:
3946                 rtl_hw_start_8102e_2(ioaddr, pdev);
3947                 break;
3948         }
3949
3950         RTL_W8(Cfg9346, Cfg9346_Lock);
3951
3952         RTL_W8(MaxTxPacketSize, TxPacketMax);
3953
3954         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3955
3956         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
3957         RTL_W16(CPlusCmd, tp->cp_cmd);
3958
3959         RTL_W16(IntrMitigate, 0x0000);
3960
3961         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3962
3963         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3964         rtl_set_rx_tx_config_registers(tp);
3965
3966         RTL_R8(IntrMask);
3967
3968         rtl_set_rx_mode(dev);
3969
3970         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
3971
3972         RTL_W16(IntrMask, tp->intr_event);
3973 }
3974
3975 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3976 {
3977         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3978                 return -EINVAL;
3979
3980         dev->mtu = new_mtu;
3981         return 0;
3982 }
3983
3984 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3985 {
3986         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
3987         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3988 }
3989
3990 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
3991                                      void **data_buff, struct RxDesc *desc)
3992 {
3993         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
3994                          DMA_FROM_DEVICE);
3995
3996         kfree(*data_buff);
3997         *data_buff = NULL;
3998         rtl8169_make_unusable_by_asic(desc);
3999 }
4000
4001 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4002 {
4003         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4004
4005         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4006 }
4007
4008 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4009                                        u32 rx_buf_sz)
4010 {
4011         desc->addr = cpu_to_le64(mapping);
4012         wmb();
4013         rtl8169_mark_to_asic(desc, rx_buf_sz);
4014 }
4015
4016 static inline void *rtl8169_align(void *data)
4017 {
4018         return (void *)ALIGN((long)data, 16);
4019 }
4020
4021 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4022                                              struct RxDesc *desc)
4023 {
4024         void *data;
4025         dma_addr_t mapping;
4026         struct device *d = &tp->pci_dev->dev;
4027         struct net_device *dev = tp->dev;
4028         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4029
4030         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4031         if (!data)
4032                 return NULL;
4033
4034         if (rtl8169_align(data) != data) {
4035                 kfree(data);
4036                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4037                 if (!data)
4038                         return NULL;
4039         }
4040
4041         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4042                                  DMA_FROM_DEVICE);
4043         if (unlikely(dma_mapping_error(d, mapping))) {
4044                 if (net_ratelimit())
4045                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4046                 goto err_out;
4047         }
4048
4049         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4050         return data;
4051
4052 err_out:
4053         kfree(data);
4054         return NULL;
4055 }
4056
4057 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4058 {
4059         unsigned int i;
4060
4061         for (i = 0; i < NUM_RX_DESC; i++) {
4062                 if (tp->Rx_databuff[i]) {
4063                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4064                                             tp->RxDescArray + i);
4065                 }
4066         }
4067 }
4068
4069 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4070 {
4071         desc->opts1 |= cpu_to_le32(RingEnd);
4072 }
4073
4074 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4075 {
4076         unsigned int i;
4077
4078         for (i = 0; i < NUM_RX_DESC; i++) {
4079                 void *data;
4080
4081                 if (tp->Rx_databuff[i])
4082                         continue;
4083
4084                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4085                 if (!data) {
4086                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4087                         goto err_out;
4088                 }
4089                 tp->Rx_databuff[i] = data;
4090         }
4091
4092         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4093         return 0;
4094
4095 err_out:
4096         rtl8169_rx_clear(tp);
4097         return -ENOMEM;
4098 }
4099
4100 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4101 {
4102         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4103 }
4104
4105 static int rtl8169_init_ring(struct net_device *dev)
4106 {
4107         struct rtl8169_private *tp = netdev_priv(dev);
4108
4109         rtl8169_init_ring_indexes(tp);
4110
4111         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4112         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4113
4114         return rtl8169_rx_fill(tp);
4115 }
4116
4117 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4118                                  struct TxDesc *desc)
4119 {
4120         unsigned int len = tx_skb->len;
4121
4122         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4123
4124         desc->opts1 = 0x00;
4125         desc->opts2 = 0x00;
4126         desc->addr = 0x00;
4127         tx_skb->len = 0;
4128 }
4129
4130 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4131                                    unsigned int n)
4132 {
4133         unsigned int i;
4134
4135         for (i = 0; i < n; i++) {
4136                 unsigned int entry = (start + i) % NUM_TX_DESC;
4137                 struct ring_info *tx_skb = tp->tx_skb + entry;
4138                 unsigned int len = tx_skb->len;
4139
4140                 if (len) {
4141                         struct sk_buff *skb = tx_skb->skb;
4142
4143                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4144                                              tp->TxDescArray + entry);
4145                         if (skb) {
4146                                 tp->dev->stats.tx_dropped++;
4147                                 dev_kfree_skb(skb);
4148                                 tx_skb->skb = NULL;
4149                         }
4150                 }
4151         }
4152 }
4153
4154 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4155 {
4156         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4157         tp->cur_tx = tp->dirty_tx = 0;
4158 }
4159
4160 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4161 {
4162         struct rtl8169_private *tp = netdev_priv(dev);
4163
4164         PREPARE_DELAYED_WORK(&tp->task, task);
4165         schedule_delayed_work(&tp->task, 4);
4166 }
4167
4168 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4169 {
4170         struct rtl8169_private *tp = netdev_priv(dev);
4171         void __iomem *ioaddr = tp->mmio_addr;
4172
4173         synchronize_irq(dev->irq);
4174
4175         /* Wait for any pending NAPI task to complete */
4176         napi_disable(&tp->napi);
4177
4178         rtl8169_irq_mask_and_ack(ioaddr);
4179
4180         tp->intr_mask = 0xffff;
4181         RTL_W16(IntrMask, tp->intr_event);
4182         napi_enable(&tp->napi);
4183 }
4184
4185 static void rtl8169_reinit_task(struct work_struct *work)
4186 {
4187         struct rtl8169_private *tp =
4188                 container_of(work, struct rtl8169_private, task.work);
4189         struct net_device *dev = tp->dev;
4190         int ret;
4191
4192         rtnl_lock();
4193
4194         if (!netif_running(dev))
4195                 goto out_unlock;
4196
4197         rtl8169_wait_for_quiescence(dev);
4198         rtl8169_close(dev);
4199
4200         ret = rtl8169_open(dev);
4201         if (unlikely(ret < 0)) {
4202                 if (net_ratelimit())
4203                         netif_err(tp, drv, dev,
4204                                   "reinit failure (status = %d). Rescheduling\n",
4205                                   ret);
4206                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4207         }
4208
4209 out_unlock:
4210         rtnl_unlock();
4211 }
4212
4213 static void rtl8169_reset_task(struct work_struct *work)
4214 {
4215         struct rtl8169_private *tp =
4216                 container_of(work, struct rtl8169_private, task.work);
4217         struct net_device *dev = tp->dev;
4218
4219         rtnl_lock();
4220
4221         if (!netif_running(dev))
4222                 goto out_unlock;
4223
4224         rtl8169_wait_for_quiescence(dev);
4225
4226         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4227         rtl8169_tx_clear(tp);
4228
4229         if (tp->dirty_rx == tp->cur_rx) {
4230                 rtl8169_init_ring_indexes(tp);
4231                 rtl_hw_start(dev);
4232                 netif_wake_queue(dev);
4233                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4234         } else {
4235                 if (net_ratelimit())
4236                         netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
4237                 rtl8169_schedule_work(dev, rtl8169_reset_task);
4238         }
4239
4240 out_unlock:
4241         rtnl_unlock();
4242 }
4243
4244 static void rtl8169_tx_timeout(struct net_device *dev)
4245 {
4246         struct rtl8169_private *tp = netdev_priv(dev);
4247
4248         rtl8169_hw_reset(tp);
4249
4250         /* Let's wait a bit while any (async) irq lands on */
4251         rtl8169_schedule_work(dev, rtl8169_reset_task);
4252 }
4253
4254 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4255                               u32 opts1)
4256 {
4257         struct skb_shared_info *info = skb_shinfo(skb);
4258         unsigned int cur_frag, entry;
4259         struct TxDesc * uninitialized_var(txd);
4260         struct device *d = &tp->pci_dev->dev;
4261
4262         entry = tp->cur_tx;
4263         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4264                 skb_frag_t *frag = info->frags + cur_frag;
4265                 dma_addr_t mapping;
4266                 u32 status, len;
4267                 void *addr;
4268
4269                 entry = (entry + 1) % NUM_TX_DESC;
4270
4271                 txd = tp->TxDescArray + entry;
4272                 len = frag->size;
4273                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4274                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4275                 if (unlikely(dma_mapping_error(d, mapping))) {
4276                         if (net_ratelimit())
4277                                 netif_err(tp, drv, tp->dev,
4278                                           "Failed to map TX fragments DMA!\n");
4279                         goto err_out;
4280                 }
4281
4282                 /* anti gcc 2.95.3 bugware (sic) */
4283                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4284
4285                 txd->opts1 = cpu_to_le32(status);
4286                 txd->addr = cpu_to_le64(mapping);
4287
4288                 tp->tx_skb[entry].len = len;
4289         }
4290
4291         if (cur_frag) {
4292                 tp->tx_skb[entry].skb = skb;
4293                 txd->opts1 |= cpu_to_le32(LastFrag);
4294         }
4295
4296         return cur_frag;
4297
4298 err_out:
4299         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4300         return -EIO;
4301 }
4302
4303 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4304 {
4305         if (dev->features & NETIF_F_TSO) {
4306                 u32 mss = skb_shinfo(skb)->gso_size;
4307
4308                 if (mss)
4309                         return LargeSend | ((mss & MSSMask) << MSSShift);
4310         }
4311         if (skb->ip_summed == CHECKSUM_PARTIAL) {
4312                 const struct iphdr *ip = ip_hdr(skb);
4313
4314                 if (ip->protocol == IPPROTO_TCP)
4315                         return IPCS | TCPCS;
4316                 else if (ip->protocol == IPPROTO_UDP)
4317                         return IPCS | UDPCS;
4318                 WARN_ON(1);     /* we need a WARN() */
4319         }
4320         return 0;
4321 }
4322
4323 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4324                                       struct net_device *dev)
4325 {
4326         struct rtl8169_private *tp = netdev_priv(dev);
4327         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4328         struct TxDesc *txd = tp->TxDescArray + entry;
4329         void __iomem *ioaddr = tp->mmio_addr;
4330         struct device *d = &tp->pci_dev->dev;
4331         dma_addr_t mapping;
4332         u32 status, len;
4333         u32 opts1;
4334         int frags;
4335
4336         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4337                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4338                 goto err_stop_0;
4339         }
4340
4341         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4342                 goto err_stop_0;
4343
4344         len = skb_headlen(skb);
4345         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4346         if (unlikely(dma_mapping_error(d, mapping))) {
4347                 if (net_ratelimit())
4348                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4349                 goto err_dma_0;
4350         }
4351
4352         tp->tx_skb[entry].len = len;
4353         txd->addr = cpu_to_le64(mapping);
4354         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4355
4356         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4357
4358         frags = rtl8169_xmit_frags(tp, skb, opts1);
4359         if (frags < 0)
4360                 goto err_dma_1;
4361         else if (frags)
4362                 opts1 |= FirstFrag;
4363         else {
4364                 opts1 |= FirstFrag | LastFrag;
4365                 tp->tx_skb[entry].skb = skb;
4366         }
4367
4368         wmb();
4369
4370         /* anti gcc 2.95.3 bugware (sic) */
4371         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4372         txd->opts1 = cpu_to_le32(status);
4373
4374         tp->cur_tx += frags + 1;
4375
4376         wmb();
4377
4378         RTL_W8(TxPoll, NPQ);    /* set polling bit */
4379
4380         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4381                 netif_stop_queue(dev);
4382                 smp_rmb();
4383                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4384                         netif_wake_queue(dev);
4385         }
4386
4387         return NETDEV_TX_OK;
4388
4389 err_dma_1:
4390         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4391 err_dma_0:
4392         dev_kfree_skb(skb);
4393         dev->stats.tx_dropped++;
4394         return NETDEV_TX_OK;
4395
4396 err_stop_0:
4397         netif_stop_queue(dev);
4398         dev->stats.tx_dropped++;
4399         return NETDEV_TX_BUSY;
4400 }
4401
4402 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4403 {
4404         struct rtl8169_private *tp = netdev_priv(dev);
4405         struct pci_dev *pdev = tp->pci_dev;
4406         u16 pci_status, pci_cmd;
4407
4408         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4409         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4410
4411         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4412                   pci_cmd, pci_status);
4413
4414         /*
4415          * The recovery sequence below admits a very elaborated explanation:
4416          * - it seems to work;
4417          * - I did not see what else could be done;
4418          * - it makes iop3xx happy.
4419          *
4420          * Feel free to adjust to your needs.
4421          */
4422         if (pdev->broken_parity_status)
4423                 pci_cmd &= ~PCI_COMMAND_PARITY;
4424         else
4425                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4426
4427         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4428
4429         pci_write_config_word(pdev, PCI_STATUS,
4430                 pci_status & (PCI_STATUS_DETECTED_PARITY |
4431                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4432                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4433
4434         /* The infamous DAC f*ckup only happens at boot time */
4435         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4436                 void __iomem *ioaddr = tp->mmio_addr;
4437
4438                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4439                 tp->cp_cmd &= ~PCIDAC;
4440                 RTL_W16(CPlusCmd, tp->cp_cmd);
4441                 dev->features &= ~NETIF_F_HIGHDMA;
4442         }
4443
4444         rtl8169_hw_reset(tp);
4445
4446         rtl8169_schedule_work(dev, rtl8169_reinit_task);
4447 }
4448
4449 static void rtl8169_tx_interrupt(struct net_device *dev,
4450                                  struct rtl8169_private *tp,
4451                                  void __iomem *ioaddr)
4452 {
4453         unsigned int dirty_tx, tx_left;
4454
4455         dirty_tx = tp->dirty_tx;
4456         smp_rmb();
4457         tx_left = tp->cur_tx - dirty_tx;
4458
4459         while (tx_left > 0) {
4460                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4461                 struct ring_info *tx_skb = tp->tx_skb + entry;
4462                 u32 status;
4463
4464                 rmb();
4465                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4466                 if (status & DescOwn)
4467                         break;
4468
4469                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4470                                      tp->TxDescArray + entry);
4471                 if (status & LastFrag) {
4472                         dev->stats.tx_packets++;
4473                         dev->stats.tx_bytes += tx_skb->skb->len;
4474                         dev_kfree_skb(tx_skb->skb);
4475                         tx_skb->skb = NULL;
4476                 }
4477                 dirty_tx++;
4478                 tx_left--;
4479         }
4480
4481         if (tp->dirty_tx != dirty_tx) {
4482                 tp->dirty_tx = dirty_tx;
4483                 smp_wmb();
4484                 if (netif_queue_stopped(dev) &&
4485                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4486                         netif_wake_queue(dev);
4487                 }
4488                 /*
4489                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4490                  * too close. Let's kick an extra TxPoll request when a burst
4491                  * of start_xmit activity is detected (if it is not detected,
4492                  * it is slow enough). -- FR
4493                  */
4494                 smp_rmb();
4495                 if (tp->cur_tx != dirty_tx)
4496                         RTL_W8(TxPoll, NPQ);
4497         }
4498 }
4499
4500 static inline int rtl8169_fragmented_frame(u32 status)
4501 {
4502         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4503 }
4504
4505 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4506 {
4507         u32 status = opts1 & RxProtoMask;
4508
4509         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4510             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4511                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4512         else
4513                 skb_checksum_none_assert(skb);
4514 }
4515
4516 static struct sk_buff *rtl8169_try_rx_copy(void *data,
4517                                            struct rtl8169_private *tp,
4518                                            int pkt_size,
4519                                            dma_addr_t addr)
4520 {
4521         struct sk_buff *skb;
4522         struct device *d = &tp->pci_dev->dev;
4523
4524         data = rtl8169_align(data);
4525         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4526         prefetch(data);
4527         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4528         if (skb)
4529                 memcpy(skb->data, data, pkt_size);
4530         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4531
4532         return skb;
4533 }
4534
4535 /*
4536  * Warning : rtl8169_rx_interrupt() might be called :
4537  * 1) from NAPI (softirq) context
4538  *      (polling = 1 : we should call netif_receive_skb())
4539  * 2) from process context (rtl8169_reset_task())
4540  *      (polling = 0 : we must call netif_rx() instead)
4541  */
4542 static int rtl8169_rx_interrupt(struct net_device *dev,
4543                                 struct rtl8169_private *tp,
4544                                 void __iomem *ioaddr, u32 budget)
4545 {
4546         unsigned int cur_rx, rx_left;
4547         unsigned int count;
4548         int polling = (budget != ~(u32)0) ? 1 : 0;
4549
4550         cur_rx = tp->cur_rx;
4551         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4552         rx_left = min(rx_left, budget);
4553
4554         for (; rx_left > 0; rx_left--, cur_rx++) {
4555                 unsigned int entry = cur_rx % NUM_RX_DESC;
4556                 struct RxDesc *desc = tp->RxDescArray + entry;
4557                 u32 status;
4558
4559                 rmb();
4560                 status = le32_to_cpu(desc->opts1);
4561
4562                 if (status & DescOwn)
4563                         break;
4564                 if (unlikely(status & RxRES)) {
4565                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4566                                    status);
4567                         dev->stats.rx_errors++;
4568                         if (status & (RxRWT | RxRUNT))
4569                                 dev->stats.rx_length_errors++;
4570                         if (status & RxCRC)
4571                                 dev->stats.rx_crc_errors++;
4572                         if (status & RxFOVF) {
4573                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
4574                                 dev->stats.rx_fifo_errors++;
4575                         }
4576                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4577                 } else {
4578                         struct sk_buff *skb;
4579                         dma_addr_t addr = le64_to_cpu(desc->addr);
4580                         int pkt_size = (status & 0x00001FFF) - 4;
4581
4582                         /*
4583                          * The driver does not support incoming fragmented
4584                          * frames. They are seen as a symptom of over-mtu
4585                          * sized frames.
4586                          */
4587                         if (unlikely(rtl8169_fragmented_frame(status))) {
4588                                 dev->stats.rx_dropped++;
4589                                 dev->stats.rx_length_errors++;
4590                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
4591                                 continue;
4592                         }
4593
4594                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4595                                                   tp, pkt_size, addr);
4596                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4597                         if (!skb) {
4598                                 dev->stats.rx_dropped++;
4599                                 continue;
4600                         }
4601
4602                         rtl8169_rx_csum(skb, status);
4603                         skb_put(skb, pkt_size);
4604                         skb->protocol = eth_type_trans(skb, dev);
4605
4606                         if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4607                                 if (likely(polling))
4608                                         napi_gro_receive(&tp->napi, skb);
4609                                 else
4610                                         netif_rx(skb);
4611                         }
4612
4613                         dev->stats.rx_bytes += pkt_size;
4614                         dev->stats.rx_packets++;
4615                 }
4616
4617                 /* Work around for AMD plateform. */
4618                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4619                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4620                         desc->opts2 = 0;
4621                         cur_rx++;
4622                 }
4623         }
4624
4625         count = cur_rx - tp->cur_rx;
4626         tp->cur_rx = cur_rx;
4627
4628         tp->dirty_rx += count;
4629
4630         return count;
4631 }
4632
4633 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4634 {
4635         struct net_device *dev = dev_instance;
4636         struct rtl8169_private *tp = netdev_priv(dev);
4637         void __iomem *ioaddr = tp->mmio_addr;
4638         int handled = 0;
4639         int status;
4640
4641         /* loop handling interrupts until we have no new ones or
4642          * we hit a invalid/hotplug case.
4643          */
4644         status = RTL_R16(IntrStatus);
4645         while (status && status != 0xffff) {
4646                 handled = 1;
4647
4648                 /* Handle all of the error cases first. These will reset
4649                  * the chip, so just exit the loop.
4650                  */
4651                 if (unlikely(!netif_running(dev))) {
4652                         rtl8169_asic_down(ioaddr);
4653                         break;
4654                 }
4655
4656                 if (unlikely(status & RxFIFOOver)) {
4657                         switch (tp->mac_version) {
4658                         /* Work around for rx fifo overflow */
4659                         case RTL_GIGA_MAC_VER_11:
4660                         case RTL_GIGA_MAC_VER_22:
4661                         case RTL_GIGA_MAC_VER_26:
4662                                 netif_stop_queue(dev);
4663                                 rtl8169_tx_timeout(dev);
4664                                 goto done;
4665                         /* Testers needed. */
4666                         case RTL_GIGA_MAC_VER_17:
4667                         case RTL_GIGA_MAC_VER_19:
4668                         case RTL_GIGA_MAC_VER_20:
4669                         case RTL_GIGA_MAC_VER_21:
4670                         case RTL_GIGA_MAC_VER_23:
4671                         case RTL_GIGA_MAC_VER_24:
4672                         case RTL_GIGA_MAC_VER_27:
4673                         case RTL_GIGA_MAC_VER_28:
4674                         /* Experimental science. Pktgen proof. */
4675                         case RTL_GIGA_MAC_VER_12:
4676                         case RTL_GIGA_MAC_VER_25:
4677                                 if (status == RxFIFOOver)
4678                                         goto done;
4679                                 break;
4680                         default:
4681                                 break;
4682                         }
4683                 }
4684
4685                 if (unlikely(status & SYSErr)) {
4686                         rtl8169_pcierr_interrupt(dev);
4687                         break;
4688                 }
4689
4690                 if (status & LinkChg)
4691                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
4692
4693                 /* We need to see the lastest version of tp->intr_mask to
4694                  * avoid ignoring an MSI interrupt and having to wait for
4695                  * another event which may never come.
4696                  */
4697                 smp_rmb();
4698                 if (status & tp->intr_mask & tp->napi_event) {
4699                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4700                         tp->intr_mask = ~tp->napi_event;
4701
4702                         if (likely(napi_schedule_prep(&tp->napi)))
4703                                 __napi_schedule(&tp->napi);
4704                         else
4705                                 netif_info(tp, intr, dev,
4706                                            "interrupt %04x in poll\n", status);
4707                 }
4708
4709                 /* We only get a new MSI interrupt when all active irq
4710                  * sources on the chip have been acknowledged. So, ack
4711                  * everything we've seen and check if new sources have become
4712                  * active to avoid blocking all interrupts from the chip.
4713                  */
4714                 RTL_W16(IntrStatus,
4715                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
4716                 status = RTL_R16(IntrStatus);
4717         }
4718 done:
4719         return IRQ_RETVAL(handled);
4720 }
4721
4722 static int rtl8169_poll(struct napi_struct *napi, int budget)
4723 {
4724         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4725         struct net_device *dev = tp->dev;
4726         void __iomem *ioaddr = tp->mmio_addr;
4727         int work_done;
4728
4729         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4730         rtl8169_tx_interrupt(dev, tp, ioaddr);
4731
4732         if (work_done < budget) {
4733                 napi_complete(napi);
4734
4735                 /* We need for force the visibility of tp->intr_mask
4736                  * for other CPUs, as we can loose an MSI interrupt
4737                  * and potentially wait for a retransmit timeout if we don't.
4738                  * The posted write to IntrMask is safe, as it will
4739                  * eventually make it to the chip and we won't loose anything
4740                  * until it does.
4741                  */
4742                 tp->intr_mask = 0xffff;
4743                 wmb();
4744                 RTL_W16(IntrMask, tp->intr_event);
4745         }
4746
4747         return work_done;
4748 }
4749
4750 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4751 {
4752         struct rtl8169_private *tp = netdev_priv(dev);
4753
4754         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4755                 return;
4756
4757         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4758         RTL_W32(RxMissed, 0);
4759 }
4760
4761 static void rtl8169_down(struct net_device *dev)
4762 {
4763         struct rtl8169_private *tp = netdev_priv(dev);
4764         void __iomem *ioaddr = tp->mmio_addr;
4765
4766         rtl8169_delete_timer(dev);
4767
4768         netif_stop_queue(dev);
4769
4770         napi_disable(&tp->napi);
4771
4772         spin_lock_irq(&tp->lock);
4773
4774         rtl8169_asic_down(ioaddr);
4775         /*
4776          * At this point device interrupts can not be enabled in any function,
4777          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4778          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4779          */
4780         rtl8169_rx_missed(dev, ioaddr);
4781
4782         spin_unlock_irq(&tp->lock);
4783
4784         synchronize_irq(dev->irq);
4785
4786         /* Give a racing hard_start_xmit a few cycles to complete. */
4787         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
4788
4789         rtl8169_tx_clear(tp);
4790
4791         rtl8169_rx_clear(tp);
4792
4793         rtl_pll_power_down(tp);
4794 }
4795
4796 static int rtl8169_close(struct net_device *dev)
4797 {
4798         struct rtl8169_private *tp = netdev_priv(dev);
4799         struct pci_dev *pdev = tp->pci_dev;
4800
4801         pm_runtime_get_sync(&pdev->dev);
4802
4803         /* update counters before going down */
4804         rtl8169_update_counters(dev);
4805
4806         rtl8169_down(dev);
4807
4808         free_irq(dev->irq, dev);
4809
4810         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4811                           tp->RxPhyAddr);
4812         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4813                           tp->TxPhyAddr);
4814         tp->TxDescArray = NULL;
4815         tp->RxDescArray = NULL;
4816
4817         pm_runtime_put_sync(&pdev->dev);
4818
4819         return 0;
4820 }
4821
4822 static void rtl_set_rx_mode(struct net_device *dev)
4823 {
4824         struct rtl8169_private *tp = netdev_priv(dev);
4825         void __iomem *ioaddr = tp->mmio_addr;
4826         unsigned long flags;
4827         u32 mc_filter[2];       /* Multicast hash filter */
4828         int rx_mode;
4829         u32 tmp = 0;
4830
4831         if (dev->flags & IFF_PROMISC) {
4832                 /* Unconditionally log net taps. */
4833                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4834                 rx_mode =
4835                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4836                     AcceptAllPhys;
4837                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4838         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4839                    (dev->flags & IFF_ALLMULTI)) {
4840                 /* Too many to filter perfectly -- accept all multicasts. */
4841                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4842                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4843         } else {
4844                 struct netdev_hw_addr *ha;
4845
4846                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4847                 mc_filter[1] = mc_filter[0] = 0;
4848                 netdev_for_each_mc_addr(ha, dev) {
4849                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4850                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4851                         rx_mode |= AcceptMulticast;
4852                 }
4853         }
4854
4855         spin_lock_irqsave(&tp->lock, flags);
4856
4857         tmp = rtl8169_rx_config | rx_mode |
4858               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4859
4860         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4861                 u32 data = mc_filter[0];
4862
4863                 mc_filter[0] = swab32(mc_filter[1]);
4864                 mc_filter[1] = swab32(data);
4865         }
4866
4867         RTL_W32(MAR0 + 4, mc_filter[1]);
4868         RTL_W32(MAR0 + 0, mc_filter[0]);
4869
4870         RTL_W32(RxConfig, tmp);
4871
4872         spin_unlock_irqrestore(&tp->lock, flags);
4873 }
4874
4875 /**
4876  *  rtl8169_get_stats - Get rtl8169 read/write statistics
4877  *  @dev: The Ethernet Device to get statistics for
4878  *
4879  *  Get TX/RX statistics for rtl8169
4880  */
4881 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4882 {
4883         struct rtl8169_private *tp = netdev_priv(dev);
4884         void __iomem *ioaddr = tp->mmio_addr;
4885         unsigned long flags;
4886
4887         if (netif_running(dev)) {
4888                 spin_lock_irqsave(&tp->lock, flags);
4889                 rtl8169_rx_missed(dev, ioaddr);
4890                 spin_unlock_irqrestore(&tp->lock, flags);
4891         }
4892
4893         return &dev->stats;
4894 }
4895
4896 static void rtl8169_net_suspend(struct net_device *dev)
4897 {
4898         struct rtl8169_private *tp = netdev_priv(dev);
4899
4900         if (!netif_running(dev))
4901                 return;
4902
4903         rtl_pll_power_down(tp);
4904
4905         netif_device_detach(dev);
4906         netif_stop_queue(dev);
4907 }
4908
4909 #ifdef CONFIG_PM
4910
4911 static int rtl8169_suspend(struct device *device)
4912 {
4913         struct pci_dev *pdev = to_pci_dev(device);
4914         struct net_device *dev = pci_get_drvdata(pdev);
4915
4916         rtl8169_net_suspend(dev);
4917
4918         return 0;
4919 }
4920
4921 static void __rtl8169_resume(struct net_device *dev)
4922 {
4923         struct rtl8169_private *tp = netdev_priv(dev);
4924
4925         netif_device_attach(dev);
4926
4927         rtl_pll_power_up(tp);
4928
4929         rtl8169_schedule_work(dev, rtl8169_reset_task);
4930 }
4931
4932 static int rtl8169_resume(struct device *device)
4933 {
4934         struct pci_dev *pdev = to_pci_dev(device);
4935         struct net_device *dev = pci_get_drvdata(pdev);
4936         struct rtl8169_private *tp = netdev_priv(dev);
4937
4938         rtl8169_init_phy(dev, tp);
4939
4940         if (netif_running(dev))
4941                 __rtl8169_resume(dev);
4942
4943         return 0;
4944 }
4945
4946 static int rtl8169_runtime_suspend(struct device *device)
4947 {
4948         struct pci_dev *pdev = to_pci_dev(device);
4949         struct net_device *dev = pci_get_drvdata(pdev);
4950         struct rtl8169_private *tp = netdev_priv(dev);
4951
4952         if (!tp->TxDescArray)
4953                 return 0;
4954
4955         spin_lock_irq(&tp->lock);
4956         tp->saved_wolopts = __rtl8169_get_wol(tp);
4957         __rtl8169_set_wol(tp, WAKE_ANY);
4958         spin_unlock_irq(&tp->lock);
4959
4960         rtl8169_net_suspend(dev);
4961
4962         return 0;
4963 }
4964
4965 static int rtl8169_runtime_resume(struct device *device)
4966 {
4967         struct pci_dev *pdev = to_pci_dev(device);
4968         struct net_device *dev = pci_get_drvdata(pdev);
4969         struct rtl8169_private *tp = netdev_priv(dev);
4970
4971         if (!tp->TxDescArray)
4972                 return 0;
4973
4974         spin_lock_irq(&tp->lock);
4975         __rtl8169_set_wol(tp, tp->saved_wolopts);
4976         tp->saved_wolopts = 0;
4977         spin_unlock_irq(&tp->lock);
4978
4979         rtl8169_init_phy(dev, tp);
4980
4981         __rtl8169_resume(dev);
4982
4983         return 0;
4984 }
4985
4986 static int rtl8169_runtime_idle(struct device *device)
4987 {
4988         struct pci_dev *pdev = to_pci_dev(device);
4989         struct net_device *dev = pci_get_drvdata(pdev);
4990         struct rtl8169_private *tp = netdev_priv(dev);
4991
4992         return tp->TxDescArray ? -EBUSY : 0;
4993 }
4994
4995 static const struct dev_pm_ops rtl8169_pm_ops = {
4996         .suspend = rtl8169_suspend,
4997         .resume = rtl8169_resume,
4998         .freeze = rtl8169_suspend,
4999         .thaw = rtl8169_resume,
5000         .poweroff = rtl8169_suspend,
5001         .restore = rtl8169_resume,
5002         .runtime_suspend = rtl8169_runtime_suspend,
5003         .runtime_resume = rtl8169_runtime_resume,
5004         .runtime_idle = rtl8169_runtime_idle,
5005 };
5006
5007 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5008
5009 #else /* !CONFIG_PM */
5010
5011 #define RTL8169_PM_OPS  NULL
5012
5013 #endif /* !CONFIG_PM */
5014
5015 static void rtl_shutdown(struct pci_dev *pdev)
5016 {
5017         struct net_device *dev = pci_get_drvdata(pdev);
5018         struct rtl8169_private *tp = netdev_priv(dev);
5019         void __iomem *ioaddr = tp->mmio_addr;
5020
5021         rtl8169_net_suspend(dev);
5022
5023         /* restore original MAC address */
5024         rtl_rar_set(tp, dev->perm_addr);
5025
5026         spin_lock_irq(&tp->lock);
5027
5028         rtl8169_asic_down(ioaddr);
5029
5030         spin_unlock_irq(&tp->lock);
5031
5032         if (system_state == SYSTEM_POWER_OFF) {
5033                 /* WoL fails with some 8168 when the receiver is disabled. */
5034                 if (tp->features & RTL_FEATURE_WOL) {
5035                         pci_clear_master(pdev);
5036
5037                         RTL_W8(ChipCmd, CmdRxEnb);
5038                         /* PCI commit */
5039                         RTL_R8(ChipCmd);
5040                 }
5041
5042                 pci_wake_from_d3(pdev, true);
5043                 pci_set_power_state(pdev, PCI_D3hot);
5044         }
5045 }
5046
5047 static struct pci_driver rtl8169_pci_driver = {
5048         .name           = MODULENAME,
5049         .id_table       = rtl8169_pci_tbl,
5050         .probe          = rtl8169_init_one,
5051         .remove         = __devexit_p(rtl8169_remove_one),
5052         .shutdown       = rtl_shutdown,
5053         .driver.pm      = RTL8169_PM_OPS,
5054 };
5055
5056 static int __init rtl8169_init_module(void)
5057 {
5058         return pci_register_driver(&rtl8169_pci_driver);
5059 }
5060
5061 static void __exit rtl8169_cleanup_module(void)
5062 {
5063         pci_unregister_driver(&rtl8169_pci_driver);
5064 }
5065
5066 module_init(rtl8169_init_module);
5067 module_exit(rtl8169_cleanup_module);