drivers/net/sfc/falcon.c

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2009 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #include <linux/bitops.h>
  12 #include <linux/delay.h>
  13 #include <linux/pci.h>
  14 #include <linux/module.h>
  15 #include <linux/seq_file.h>
  16 #include <linux/i2c.h>
  17 #include <linux/mii.h>
  18 #include <linux/slab.h>
  19 #include "net_driver.h"
  20 #include "bitfield.h"
  21 #include "efx.h"
  22 #include "mac.h"
  23 #include "spi.h"
  24 #include "nic.h"
  25 #include "regs.h"
  26 #include "io.h"
  27 #include "phy.h"
  28 #include "workarounds.h"
  29
  30 /* Hardware control for SFC4000 (aka Falcon). */
  31
  32 static const unsigned int
  33 /* "Large" EEPROM device: Atmel AT25640 or similar
  34  * 8 KB, 16-bit address, 32 B write block */
  35 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
  36                      | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
  37                      | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
  38 /* Default flash device: Atmel AT25F1024
  39  * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
  40 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
  41                       | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
  42                       | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
  43                       | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
  44                       | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
  45
  46 /**************************************************************************
  47  *
  48  * I2C bus - this is a bit-bashing interface using GPIO pins
  49  * Note that it uses the output enables to tristate the outputs
  50  * SDA is the data pin and SCL is the clock
  51  *
  52  **************************************************************************
  53  */
  54 static void falcon_setsda(void *data, int state)
  55 {
  56         struct efx_nic *efx = (struct efx_nic *)data;
  57         efx_oword_t reg;
  58
  59         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
  60         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
  61         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
  62 }
  63
  64 static void falcon_setscl(void *data, int state)
  65 {
  66         struct efx_nic *efx = (struct efx_nic *)data;
  67         efx_oword_t reg;
  68
  69         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
  70         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
  71         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
  72 }
  73
  74 static int falcon_getsda(void *data)
  75 {
  76         struct efx_nic *efx = (struct efx_nic *)data;
  77         efx_oword_t reg;
  78
  79         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
  80         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
  81 }
  82
  83 static int falcon_getscl(void *data)
  84 {
  85         struct efx_nic *efx = (struct efx_nic *)data;
  86         efx_oword_t reg;
  87
  88         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
  89         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
  90 }
  91
  92 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
  93         .setsda         = falcon_setsda,
  94         .setscl         = falcon_setscl,
  95         .getsda         = falcon_getsda,
  96         .getscl         = falcon_getscl,
  97         .udelay         = 5,
  98         /* Wait up to 50 ms for slave to let us pull SCL high */
  99         .timeout        = DIV_ROUND_UP(HZ, 20),
 100 };
 101
 102 static void falcon_push_irq_moderation(struct efx_channel *channel)
 103 {
 104         efx_dword_t timer_cmd;
 105         struct efx_nic *efx = channel->efx;
 106
 107         /* Set timer register */
 108         if (channel->irq_moderation) {
 109                 EFX_POPULATE_DWORD_2(timer_cmd,
 110                                      FRF_AB_TC_TIMER_MODE,
 111                                      FFE_BB_TIMER_MODE_INT_HLDOFF,
 112                                      FRF_AB_TC_TIMER_VAL,
 113                                      channel->irq_moderation - 1);
 114         } else {
 115                 EFX_POPULATE_DWORD_2(timer_cmd,
 116                                      FRF_AB_TC_TIMER_MODE,
 117                                      FFE_BB_TIMER_MODE_DIS,
 118                                      FRF_AB_TC_TIMER_VAL, 0);
 119         }
 120         BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
 121         efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
 122                                channel->channel);
 123 }
 124
 125 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx);
 126
 127 static void falcon_prepare_flush(struct efx_nic *efx)
 128 {
 129         falcon_deconfigure_mac_wrapper(efx);
 130
 131         /* Wait for the tx and rx fifo's to get to the next packet boundary
 132          * (~1ms without back-pressure), then to drain the remainder of the
 133          * fifo's at data path speeds (negligible), with a healthy margin. */
 134         msleep(10);
 135 }
 136
 137 /* Acknowledge a legacy interrupt from Falcon
 138  *
 139  * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
 140  *
 141  * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
 142  * BIU. Interrupt acknowledge is read sensitive so must write instead
 143  * (then read to ensure the BIU collector is flushed)
 144  *
 145  * NB most hardware supports MSI interrupts
 146  */
 147 inline void falcon_irq_ack_a1(struct efx_nic *efx)
 148 {
 149         efx_dword_t reg;
 150
 151         EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
 152         efx_writed(efx, &reg, FR_AA_INT_ACK_KER);
 153         efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
 154 }
 155
 156
 157 irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
 158 {
 159         struct efx_nic *efx = dev_id;
 160         efx_oword_t *int_ker = efx->irq_status.addr;
 161         int syserr;
 162         int queues;
 163
 164         /* Check to see if this is our interrupt.  If it isn't, we
 165          * exit without having touched the hardware.
 166          */
 167         if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
 168                 netif_vdbg(efx, intr, efx->net_dev,
 169                            "IRQ %d on CPU %d not for me\n", irq,
 170                            raw_smp_processor_id());
 171                 return IRQ_NONE;
 172         }
 173         efx->last_irq_cpu = raw_smp_processor_id();
 174         netif_vdbg(efx, intr, efx->net_dev,
 175                    "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
 176                    irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
 177
 178         /* Determine interrupting queues, clear interrupt status
 179          * register and acknowledge the device interrupt.
 180          */
 181         BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS);
 182         queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q);
 183
 184         /* Check to see if we have a serious error condition */
 185         if (queues & (1U << efx->fatal_irq_level)) {
 186                 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
 187                 if (unlikely(syserr))
 188                         return efx_nic_fatal_interrupt(efx);
 189         }
 190
 191         EFX_ZERO_OWORD(*int_ker);
 192         wmb(); /* Ensure the vector is cleared before interrupt ack */
 193         falcon_irq_ack_a1(efx);
 194
 195         if (queues & 1)
 196                 efx_schedule_channel(efx_get_channel(efx, 0));
 197         if (queues & 2)
 198                 efx_schedule_channel(efx_get_channel(efx, 1));
 199         return IRQ_HANDLED;
 200 }
 201 /**************************************************************************
 202  *
 203  * EEPROM/flash
 204  *
 205  **************************************************************************
 206  */
 207
 208 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
 209
 210 static int falcon_spi_poll(struct efx_nic *efx)
 211 {
 212         efx_oword_t reg;
 213         efx_reado(efx, &reg, FR_AB_EE_SPI_HCMD);
 214         return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
 215 }
 216
 217 /* Wait for SPI command completion */
 218 static int falcon_spi_wait(struct efx_nic *efx)
 219 {
 220         /* Most commands will finish quickly, so we start polling at
 221          * very short intervals.  Sometimes the command may have to
 222          * wait for VPD or expansion ROM access outside of our
 223          * control, so we allow up to 100 ms. */
 224         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
 225         int i;
 226
 227         for (i = 0; i < 10; i++) {
 228                 if (!falcon_spi_poll(efx))
 229                         return 0;
 230                 udelay(10);
 231         }
 232
 233         for (;;) {
 234                 if (!falcon_spi_poll(efx))
 235                         return 0;
 236                 if (time_after_eq(jiffies, timeout)) {
 237                         netif_err(efx, hw, efx->net_dev,
 238                                   "timed out waiting for SPI\n");
 239                         return -ETIMEDOUT;
 240                 }
 241                 schedule_timeout_uninterruptible(1);
 242         }
 243 }
 244
 245 int falcon_spi_cmd(struct efx_nic *efx, const struct efx_spi_device *spi,
 246                    unsigned int command, int address,
 247                    const void *in, void *out, size_t len)
 248 {
 249         bool addressed = (address >= 0);
 250         bool reading = (out != NULL);
 251         efx_oword_t reg;
 252         int rc;
 253
 254         /* Input validation */
 255         if (len > FALCON_SPI_MAX_LEN)
 256                 return -EINVAL;
 257         BUG_ON(!mutex_is_locked(&efx->spi_lock));
 258
 259         /* Check that previous command is not still running */
 260         rc = falcon_spi_poll(efx);
 261         if (rc)
 262                 return rc;
 263
 264         /* Program address register, if we have an address */
 265         if (addressed) {
 266                 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
 267                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HADR);
 268         }
 269
 270         /* Program data register, if we have data */
 271         if (in != NULL) {
 272                 memcpy(&reg, in, len);
 273                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HDATA);
 274         }
 275
 276         /* Issue read/write command */
 277         EFX_POPULATE_OWORD_7(reg,
 278                              FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
 279                              FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
 280                              FRF_AB_EE_SPI_HCMD_DABCNT, len,
 281                              FRF_AB_EE_SPI_HCMD_READ, reading,
 282                              FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
 283                              FRF_AB_EE_SPI_HCMD_ADBCNT,
 284                              (addressed ? spi->addr_len : 0),
 285                              FRF_AB_EE_SPI_HCMD_ENC, command);
 286         efx_writeo(efx, &reg, FR_AB_EE_SPI_HCMD);
 287
 288         /* Wait for read/write to complete */
 289         rc = falcon_spi_wait(efx);
 290         if (rc)
 291                 return rc;
 292
 293         /* Read data */
 294         if (out != NULL) {
 295                 efx_reado(efx, &reg, FR_AB_EE_SPI_HDATA);
 296                 memcpy(out, &reg, len);
 297         }
 298
 299         return 0;
 300 }
 301
 302 static size_t
 303 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
 304 {
 305         return min(FALCON_SPI_MAX_LEN,
 306                    (spi->block_size - (start & (spi->block_size - 1))));
 307 }
 308
 309 static inline u8
 310 efx_spi_munge_command(const struct efx_spi_device *spi,
 311                       const u8 command, const unsigned int address)
 312 {
 313         return command | (((address >> 8) & spi->munge_address) << 3);
 314 }
 315
 316 /* Wait up to 10 ms for buffered write completion */
 317 int
 318 falcon_spi_wait_write(struct efx_nic *efx, const struct efx_spi_device *spi)
 319 {
 320         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
 321         u8 status;
 322         int rc;
 323
 324         for (;;) {
 325                 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
 326                                     &status, sizeof(status));
 327                 if (rc)
 328                         return rc;
 329                 if (!(status & SPI_STATUS_NRDY))
 330                         return 0;
 331                 if (time_after_eq(jiffies, timeout)) {
 332                         netif_err(efx, hw, efx->net_dev,
 333                                   "SPI write timeout on device %d"
 334                                   " last status=0x%02x\n",
 335                                   spi->device_id, status);
 336                         return -ETIMEDOUT;
 337                 }
 338                 schedule_timeout_uninterruptible(1);
 339         }
 340 }
 341
 342 int falcon_spi_read(struct efx_nic *efx, const struct efx_spi_device *spi,
 343                     loff_t start, size_t len, size_t *retlen, u8 *buffer)
 344 {
 345         size_t block_len, pos = 0;
 346         unsigned int command;
 347         int rc = 0;
 348
 349         while (pos < len) {
 350                 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
 351
 352                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
 353                 rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL,
 354                                     buffer + pos, block_len);
 355                 if (rc)
 356                         break;
 357                 pos += block_len;
 358
 359                 /* Avoid locking up the system */
 360                 cond_resched();
 361                 if (signal_pending(current)) {
 362                         rc = -EINTR;
 363                         break;
 364                 }
 365         }
 366
 367         if (retlen)
 368                 *retlen = pos;
 369         return rc;
 370 }
 371
 372 int
 373 falcon_spi_write(struct efx_nic *efx, const struct efx_spi_device *spi,
 374                  loff_t start, size_t len, size_t *retlen, const u8 *buffer)
 375 {
 376         u8 verify_buffer[FALCON_SPI_MAX_LEN];
 377         size_t block_len, pos = 0;
 378         unsigned int command;
 379         int rc = 0;
 380
 381         while (pos < len) {
 382                 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
 383                 if (rc)
 384                         break;
 385
 386                 block_len = min(len - pos,
 387                                 falcon_spi_write_limit(spi, start + pos));
 388                 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
 389                 rc = falcon_spi_cmd(efx, spi, command, start + pos,
 390                                     buffer + pos, NULL, block_len);
 391                 if (rc)
 392                         break;
 393
 394                 rc = falcon_spi_wait_write(efx, spi);
 395                 if (rc)
 396                         break;
 397
 398                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
 399                 rc = falcon_spi_cmd(efx, spi, command, start + pos,
 400                                     NULL, verify_buffer, block_len);
 401                 if (memcmp(verify_buffer, buffer + pos, block_len)) {
 402                         rc = -EIO;
 403                         break;
 404                 }
 405
 406                 pos += block_len;
 407
 408                 /* Avoid locking up the system */
 409                 cond_resched();
 410                 if (signal_pending(current)) {
 411                         rc = -EINTR;
 412                         break;
 413                 }
 414         }
 415
 416         if (retlen)
 417                 *retlen = pos;
 418         return rc;
 419 }
 420
 421 /**************************************************************************
 422  *
 423  * MAC wrapper
 424  *
 425  **************************************************************************
 426  */
 427
 428 static void falcon_push_multicast_hash(struct efx_nic *efx)
 429 {
 430         union efx_multicast_hash *mc_hash = &efx->multicast_hash;
 431
 432         WARN_ON(!mutex_is_locked(&efx->mac_lock));
 433
 434         efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
 435         efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
 436 }
 437
 438 static void falcon_reset_macs(struct efx_nic *efx)
 439 {
 440         struct falcon_nic_data *nic_data = efx->nic_data;
 441         efx_oword_t reg, mac_ctrl;
 442         int count;
 443
 444         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
 445                 /* It's not safe to use GLB_CTL_REG to reset the
 446                  * macs, so instead use the internal MAC resets
 447                  */
 448                 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
 449                 efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
 450
 451                 for (count = 0; count < 10000; count++) {
 452                         efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);
 453                         if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
 454                             0)
 455                                 return;
 456                         udelay(10);
 457                 }
 458
 459                 netif_err(efx, hw, efx->net_dev,
 460                           "timed out waiting for XMAC core reset\n");
 461         }
 462
 463         /* Mac stats will fail whist the TX fifo is draining */
 464         WARN_ON(nic_data->stats_disable_count == 0);
 465
 466         efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL);
 467         EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1);
 468         efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
 469
 470         efx_reado(efx, &reg, FR_AB_GLB_CTL);
 471         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
 472         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
 473         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
 474         efx_writeo(efx, &reg, FR_AB_GLB_CTL);
 475
 476         count = 0;
 477         while (1) {
 478                 efx_reado(efx, &reg, FR_AB_GLB_CTL);
 479                 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
 480                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
 481                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
 482                         netif_dbg(efx, hw, efx->net_dev,
 483                                   "Completed MAC reset after %d loops\n",
 484                                   count);
 485                         break;
 486                 }
 487                 if (count > 20) {
 488                         netif_err(efx, hw, efx->net_dev, "MAC reset failed\n");
 489                         break;
 490                 }
 491                 count++;
 492                 udelay(10);
 493         }
 494
 495         /* Ensure the correct MAC is selected before statistics
 496          * are re-enabled by the caller */
 497         efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
 498
 499         falcon_setup_xaui(efx);
 500 }
 501
 502 void falcon_drain_tx_fifo(struct efx_nic *efx)
 503 {
 504         efx_oword_t reg;
 505
 506         if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) ||
 507             (efx->loopback_mode != LOOPBACK_NONE))
 508                 return;
 509
 510         efx_reado(efx, &reg, FR_AB_MAC_CTRL);
 511         /* There is no point in draining more than once */
 512         if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
 513                 return;
 514
 515         falcon_reset_macs(efx);
 516 }
 517
 518 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
 519 {
 520         efx_oword_t reg;
 521
 522         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
 523                 return;
 524
 525         /* Isolate the MAC -> RX */
 526         efx_reado(efx, &reg, FR_AZ_RX_CFG);
 527         EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
 528         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
 529
 530         /* Isolate TX -> MAC */
 531         falcon_drain_tx_fifo(efx);
 532 }
 533
 534 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
 535 {
 536         struct efx_link_state *link_state = &efx->link_state;
 537         efx_oword_t reg;
 538         int link_speed, isolate;
 539
 540         isolate = (efx->reset_pending != RESET_TYPE_NONE);
 541
 542         switch (link_state->speed) {
 543         case 10000: link_speed = 3; break;
 544         case 1000:  link_speed = 2; break;
 545         case 100:   link_speed = 1; break;
 546         default:    link_speed = 0; break;
 547         }
 548         /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
 549          * as advertised.  Disable to ensure packets are not
 550          * indefinitely held and TX queue can be flushed at any point
 551          * while the link is down. */
 552         EFX_POPULATE_OWORD_5(reg,
 553                              FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
 554                              FRF_AB_MAC_BCAD_ACPT, 1,
 555                              FRF_AB_MAC_UC_PROM, efx->promiscuous,
 556                              FRF_AB_MAC_LINK_STATUS, 1, /* always set */
 557                              FRF_AB_MAC_SPEED, link_speed);
 558         /* On B0, MAC backpressure can be disabled and packets get
 559          * discarded. */
 560         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
 561                 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
 562                                     !link_state->up || isolate);
 563         }
 564
 565         efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
 566
 567         /* Restore the multicast hash registers. */
 568         falcon_push_multicast_hash(efx);
 569
 570         efx_reado(efx, &reg, FR_AZ_RX_CFG);
 571         /* Enable XOFF signal from RX FIFO (we enabled it during NIC
 572          * initialisation but it may read back as 0) */
 573         EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
 574         /* Unisolate the MAC -> RX */
 575         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
 576                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, !isolate);
 577         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
 578 }
 579
 580 static void falcon_stats_request(struct efx_nic *efx)
 581 {
 582         struct falcon_nic_data *nic_data = efx->nic_data;
 583         efx_oword_t reg;
 584
 585         WARN_ON(nic_data->stats_pending);
 586         WARN_ON(nic_data->stats_disable_count);
 587
 588         if (nic_data->stats_dma_done == NULL)
 589                 return; /* no mac selected */
 590
 591         *nic_data->stats_dma_done = FALCON_STATS_NOT_DONE;
 592         nic_data->stats_pending = true;
 593         wmb(); /* ensure done flag is clear */
 594
 595         /* Initiate DMA transfer of stats */
 596         EFX_POPULATE_OWORD_2(reg,
 597                              FRF_AB_MAC_STAT_DMA_CMD, 1,
 598                              FRF_AB_MAC_STAT_DMA_ADR,
 599                              efx->stats_buffer.dma_addr);
 600         efx_writeo(efx, &reg, FR_AB_MAC_STAT_DMA);
 601
 602         mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2));
 603 }
 604
 605 static void falcon_stats_complete(struct efx_nic *efx)
 606 {
 607         struct falcon_nic_data *nic_data = efx->nic_data;
 608
 609         if (!nic_data->stats_pending)
 610                 return;
 611
 612         nic_data->stats_pending = 0;
 613         if (*nic_data->stats_dma_done == FALCON_STATS_DONE) {
 614                 rmb(); /* read the done flag before the stats */
 615                 efx->mac_op->update_stats(efx);
 616         } else {
 617                 netif_err(efx, hw, efx->net_dev,
 618                           "timed out waiting for statistics\n");
 619         }
 620 }
 621
 622 static void falcon_stats_timer_func(unsigned long context)
 623 {
 624         struct efx_nic *efx = (struct efx_nic *)context;
 625         struct falcon_nic_data *nic_data = efx->nic_data;
 626
 627         spin_lock(&efx->stats_lock);
 628
 629         falcon_stats_complete(efx);
 630         if (nic_data->stats_disable_count == 0)
 631                 falcon_stats_request(efx);
 632
 633         spin_unlock(&efx->stats_lock);
 634 }
 635
 636 static bool falcon_loopback_link_poll(struct efx_nic *efx)
 637 {
 638         struct efx_link_state old_state = efx->link_state;
 639
 640         WARN_ON(!mutex_is_locked(&efx->mac_lock));
 641         WARN_ON(!LOOPBACK_INTERNAL(efx));
 642
 643         efx->link_state.fd = true;
 644         efx->link_state.fc = efx->wanted_fc;
 645         efx->link_state.up = true;
 646         efx->link_state.speed = 10000;
 647
 648         return !efx_link_state_equal(&efx->link_state, &old_state);
 649 }
 650
 651 static int falcon_reconfigure_port(struct efx_nic *efx)
 652 {
 653         int rc;
 654
 655         WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0);
 656
 657         /* Poll the PHY link state *before* reconfiguring it. This means we
 658          * will pick up the correct speed (in loopback) to select the correct
 659          * MAC.
 660          */
 661         if (LOOPBACK_INTERNAL(efx))
 662                 falcon_loopback_link_poll(efx);
 663         else
 664                 efx->phy_op->poll(efx);
 665
 666         falcon_stop_nic_stats(efx);
 667         falcon_deconfigure_mac_wrapper(efx);
 668
 669         falcon_reset_macs(efx);
 670
 671         efx->phy_op->reconfigure(efx);
 672         rc = efx->mac_op->reconfigure(efx);
 673         BUG_ON(rc);
 674
 675         falcon_start_nic_stats(efx);
 676
 677         /* Synchronise efx->link_state with the kernel */
 678         efx_link_status_changed(efx);
 679
 680         return 0;
 681 }
 682
 683 /**************************************************************************
 684  *
 685  * PHY access via GMII
 686  *
 687  **************************************************************************
 688  */
 689
 690 /* Wait for GMII access to complete */
 691 static int falcon_gmii_wait(struct efx_nic *efx)
 692 {
 693         efx_oword_t md_stat;
 694         int count;
 695
 696         /* wait upto 50ms - taken max from datasheet */
 697         for (count = 0; count < 5000; count++) {
 698                 efx_reado(efx, &md_stat, FR_AB_MD_STAT);
 699                 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
 700                         if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
 701                             EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
 702                                 netif_err(efx, hw, efx->net_dev,
 703                                           "error from GMII access "
 704                                           EFX_OWORD_FMT"\n",
 705                                           EFX_OWORD_VAL(md_stat));
 706                                 return -EIO;
 707                         }
 708                         return 0;
 709                 }
 710                 udelay(10);
 711         }
 712         netif_err(efx, hw, efx->net_dev, "timed out waiting for GMII\n");
 713         return -ETIMEDOUT;
 714 }
 715
 716 /* Write an MDIO register of a PHY connected to Falcon. */
 717 static int falcon_mdio_write(struct net_device *net_dev,
 718                              int prtad, int devad, u16 addr, u16 value)
 719 {
 720         struct efx_nic *efx = netdev_priv(net_dev);
 721         efx_oword_t reg;
 722         int rc;
 723
 724         netif_vdbg(efx, hw, efx->net_dev,
 725                    "writing MDIO %d register %d.%d with 0x%04x\n",
 726                     prtad, devad, addr, value);
 727
 728         mutex_lock(&efx->mdio_lock);
 729
 730         /* Check MDIO not currently being accessed */
 731         rc = falcon_gmii_wait(efx);
 732         if (rc)
 733                 goto out;
 734
 735         /* Write the address/ID register */
 736         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
 737         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
 738
 739         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
 740                              FRF_AB_MD_DEV_ADR, devad);
 741         efx_writeo(efx, &reg, FR_AB_MD_ID);
 742
 743         /* Write data */
 744         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
 745         efx_writeo(efx, &reg, FR_AB_MD_TXD);
 746
 747         EFX_POPULATE_OWORD_2(reg,
 748                              FRF_AB_MD_WRC, 1,
 749                              FRF_AB_MD_GC, 0);
 750         efx_writeo(efx, &reg, FR_AB_MD_CS);
 751
 752         /* Wait for data to be written */
 753         rc = falcon_gmii_wait(efx);
 754         if (rc) {
 755                 /* Abort the write operation */
 756                 EFX_POPULATE_OWORD_2(reg,
 757                                      FRF_AB_MD_WRC, 0,
 758                                      FRF_AB_MD_GC, 1);
 759                 efx_writeo(efx, &reg, FR_AB_MD_CS);
 760                 udelay(10);
 761         }
 762
 763 out:
 764         mutex_unlock(&efx->mdio_lock);
 765         return rc;
 766 }
 767
 768 /* Read an MDIO register of a PHY connected to Falcon. */
 769 static int falcon_mdio_read(struct net_device *net_dev,
 770                             int prtad, int devad, u16 addr)
 771 {
 772         struct efx_nic *efx = netdev_priv(net_dev);
 773         efx_oword_t reg;
 774         int rc;
 775
 776         mutex_lock(&efx->mdio_lock);
 777
 778         /* Check MDIO not currently being accessed */
 779         rc = falcon_gmii_wait(efx);
 780         if (rc)
 781                 goto out;
 782
 783         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
 784         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
 785
 786         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
 787                              FRF_AB_MD_DEV_ADR, devad);
 788         efx_writeo(efx, &reg, FR_AB_MD_ID);
 789
 790         /* Request data to be read */
 791         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
 792         efx_writeo(efx, &reg, FR_AB_MD_CS);
 793
 794         /* Wait for data to become available */
 795         rc = falcon_gmii_wait(efx);
 796         if (rc == 0) {
 797                 efx_reado(efx, &reg, FR_AB_MD_RXD);
 798                 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
 799                 netif_vdbg(efx, hw, efx->net_dev,
 800                            "read from MDIO %d register %d.%d, got %04x\n",
 801                            prtad, devad, addr, rc);
 802         } else {
 803                 /* Abort the read operation */
 804                 EFX_POPULATE_OWORD_2(reg,
 805                                      FRF_AB_MD_RIC, 0,
 806                                      FRF_AB_MD_GC, 1);
 807                 efx_writeo(efx, &reg, FR_AB_MD_CS);
 808
 809                 netif_dbg(efx, hw, efx->net_dev,
 810                           "read from MDIO %d register %d.%d, got error %d\n",
 811                           prtad, devad, addr, rc);
 812         }
 813
 814 out:
 815         mutex_unlock(&efx->mdio_lock);
 816         return rc;
 817 }
 818
 819 /* This call is responsible for hooking in the MAC and PHY operations */
 820 static int falcon_probe_port(struct efx_nic *efx)
 821 {
 822         struct falcon_nic_data *nic_data = efx->nic_data;
 823         int rc;
 824
 825         switch (efx->phy_type) {
 826         case PHY_TYPE_SFX7101:
 827                 efx->phy_op = &falcon_sfx7101_phy_ops;
 828                 break;
 829         case PHY_TYPE_QT2022C2:
 830         case PHY_TYPE_QT2025C:
 831                 efx->phy_op = &falcon_qt202x_phy_ops;
 832                 break;
 833         case PHY_TYPE_TXC43128:
 834                 efx->phy_op = &falcon_txc_phy_ops;
 835                 break;
 836         default:
 837                 netif_err(efx, probe, efx->net_dev, "Unknown PHY type %d\n",
 838                           efx->phy_type);
 839                 return -ENODEV;
 840         }
 841
 842         /* Fill out MDIO structure and loopback modes */
 843         efx->mdio.mdio_read = falcon_mdio_read;
 844         efx->mdio.mdio_write = falcon_mdio_write;
 845         rc = efx->phy_op->probe(efx);
 846         if (rc != 0)
 847                 return rc;
 848
 849         /* Initial assumption */
 850         efx->link_state.speed = 10000;
 851         efx->link_state.fd = true;
 852
 853         /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
 854         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
 855                 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
 856         else
 857                 efx->wanted_fc = EFX_FC_RX;
 858         if (efx->mdio.mmds & MDIO_DEVS_AN)
 859                 efx->wanted_fc |= EFX_FC_AUTO;
 860
 861         /* Allocate buffer for stats */
 862         rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
 863                                   FALCON_MAC_STATS_SIZE);
 864         if (rc)
 865                 return rc;
 866         netif_dbg(efx, probe, efx->net_dev,
 867                   "stats buffer at %llx (virt %p phys %llx)\n",
 868                   (u64)efx->stats_buffer.dma_addr,
 869                   efx->stats_buffer.addr,
 870                   (u64)virt_to_phys(efx->stats_buffer.addr));
 871         nic_data->stats_dma_done = efx->stats_buffer.addr + XgDmaDone_offset;
 872
 873         return 0;
 874 }
 875
 876 static void falcon_remove_port(struct efx_nic *efx)
 877 {
 878         efx->phy_op->remove(efx);
 879         efx_nic_free_buffer(efx, &efx->stats_buffer);
 880 }
 881
 882 /**************************************************************************
 883  *
 884  * Falcon test code
 885  *
 886  **************************************************************************/
 887
 888 static int
 889 falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
 890 {
 891         struct falcon_nvconfig *nvconfig;
 892         struct efx_spi_device *spi;
 893         void *region;
 894         int rc, magic_num, struct_ver;
 895         __le16 *word, *limit;
 896         u32 csum;
 897
 898         spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
 899         if (!spi)
 900                 return -EINVAL;
 901
 902         region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
 903         if (!region)
 904                 return -ENOMEM;
 905         nvconfig = region + FALCON_NVCONFIG_OFFSET;
 906
 907         mutex_lock(&efx->spi_lock);
 908         rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region);
 909         mutex_unlock(&efx->spi_lock);
 910         if (rc) {
 911                 netif_err(efx, hw, efx->net_dev, "Failed to read %s\n",
 912                           efx->spi_flash ? "flash" : "EEPROM");
 913                 rc = -EIO;
 914                 goto out;
 915         }
 916
 917         magic_num = le16_to_cpu(nvconfig->board_magic_num);
 918         struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
 919
 920         rc = -EINVAL;
 921         if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
 922                 netif_err(efx, hw, efx->net_dev,
 923                           "NVRAM bad magic 0x%x\n", magic_num);
 924                 goto out;
 925         }
 926         if (struct_ver < 2) {
 927                 netif_err(efx, hw, efx->net_dev,
 928                           "NVRAM has ancient version 0x%x\n", struct_ver);
 929                 goto out;
 930         } else if (struct_ver < 4) {
 931                 word = &nvconfig->board_magic_num;
 932                 limit = (__le16 *) (nvconfig + 1);
 933         } else {
 934                 word = region;
 935                 limit = region + FALCON_NVCONFIG_END;
 936         }
 937         for (csum = 0; word < limit; ++word)
 938                 csum += le16_to_cpu(*word);
 939
 940         if (~csum & 0xffff) {
 941                 netif_err(efx, hw, efx->net_dev,
 942                           "NVRAM has incorrect checksum\n");
 943                 goto out;
 944         }
 945
 946         rc = 0;
 947         if (nvconfig_out)
 948                 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
 949
 950  out:
 951         kfree(region);
 952         return rc;
 953 }
 954
 955 static int falcon_test_nvram(struct efx_nic *efx)
 956 {
 957         return falcon_read_nvram(efx, NULL);
 958 }
 959
 960 static const struct efx_nic_register_test falcon_b0_register_tests[] = {
 961         { FR_AZ_ADR_REGION,
 962           EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
 963         { FR_AZ_RX_CFG,
 964           EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
 965         { FR_AZ_TX_CFG,
 966           EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
 967         { FR_AZ_TX_RESERVED,
 968           EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
 969         { FR_AB_MAC_CTRL,
 970           EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
 971         { FR_AZ_SRM_TX_DC_CFG,
 972           EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
 973         { FR_AZ_RX_DC_CFG,
 974           EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
 975         { FR_AZ_RX_DC_PF_WM,
 976           EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
 977         { FR_BZ_DP_CTRL,
 978           EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
 979         { FR_AB_GM_CFG2,
 980           EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
 981         { FR_AB_GMF_CFG0,
 982           EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
 983         { FR_AB_XM_GLB_CFG,
 984           EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
 985         { FR_AB_XM_TX_CFG,
 986           EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
 987         { FR_AB_XM_RX_CFG,
 988           EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
 989         { FR_AB_XM_RX_PARAM,
 990           EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
 991         { FR_AB_XM_FC,
 992           EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
 993         { FR_AB_XM_ADR_LO,
 994           EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
 995         { FR_AB_XX_SD_CTL,
 996           EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
 997 };
 998
 999 static int falcon_b0_test_registers(struct efx_nic *efx)
1000 {
1001         return efx_nic_test_registers(efx, falcon_b0_register_tests,
1002                                       ARRAY_SIZE(falcon_b0_register_tests));
1003 }
1004
1005 /**************************************************************************
1006  *
1007  * Device reset
1008  *
1009  **************************************************************************
1010  */
1011
1012 /* Resets NIC to known state.  This routine must be called in process
1013  * context and is allowed to sleep. */
1014 static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
1015 {
1016         struct falcon_nic_data *nic_data = efx->nic_data;
1017         efx_oword_t glb_ctl_reg_ker;
1018         int rc;
1019
1020         netif_dbg(efx, hw, efx->net_dev, "performing %s hardware reset\n",
1021                   RESET_TYPE(method));
1022
1023         /* Initiate device reset */
1024         if (method == RESET_TYPE_WORLD) {
1025                 rc = pci_save_state(efx->pci_dev);
1026                 if (rc) {
1027                         netif_err(efx, drv, efx->net_dev,
1028                                   "failed to backup PCI state of primary "
1029                                   "function prior to hardware reset\n");
1030                         goto fail1;
1031                 }
1032                 if (efx_nic_is_dual_func(efx)) {
1033                         rc = pci_save_state(nic_data->pci_dev2);
1034                         if (rc) {
1035                                 netif_err(efx, drv, efx->net_dev,
1036                                           "failed to backup PCI state of "
1037                                           "secondary function prior to "
1038                                           "hardware reset\n");
1039                                 goto fail2;
1040                         }
1041                 }
1042
1043                 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
1044                                      FRF_AB_EXT_PHY_RST_DUR,
1045                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
1046                                      FRF_AB_SWRST, 1);
1047         } else {
1048                 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
1049                                      /* exclude PHY from "invisible" reset */
1050                                      FRF_AB_EXT_PHY_RST_CTL,
1051                                      method == RESET_TYPE_INVISIBLE,
1052                                      /* exclude EEPROM/flash and PCIe */
1053                                      FRF_AB_PCIE_CORE_RST_CTL, 1,
1054                                      FRF_AB_PCIE_NSTKY_RST_CTL, 1,
1055                                      FRF_AB_PCIE_SD_RST_CTL, 1,
1056                                      FRF_AB_EE_RST_CTL, 1,
1057                                      FRF_AB_EXT_PHY_RST_DUR,
1058                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
1059                                      FRF_AB_SWRST, 1);
1060         }
1061         efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1062
1063         netif_dbg(efx, hw, efx->net_dev, "waiting for hardware reset\n");
1064         schedule_timeout_uninterruptible(HZ / 20);
1065
1066         /* Restore PCI configuration if needed */
1067         if (method == RESET_TYPE_WORLD) {
1068                 if (efx_nic_is_dual_func(efx)) {
1069                         rc = pci_restore_state(nic_data->pci_dev2);
1070                         if (rc) {
1071                                 netif_err(efx, drv, efx->net_dev,
1072                                           "failed to restore PCI config for "
1073                                           "the secondary function\n");
1074                                 goto fail3;
1075                         }
1076                 }
1077                 rc = pci_restore_state(efx->pci_dev);
1078                 if (rc) {
1079                         netif_err(efx, drv, efx->net_dev,
1080                                   "failed to restore PCI config for the "
1081                                   "primary function\n");
1082                         goto fail4;
1083                 }
1084                 netif_dbg(efx, drv, efx->net_dev,
1085                           "successfully restored PCI config\n");
1086         }
1087
1088         /* Assert that reset complete */
1089         efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1090         if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
1091                 rc = -ETIMEDOUT;
1092                 netif_err(efx, hw, efx->net_dev,
1093                           "timed out waiting for hardware reset\n");
1094                 goto fail5;
1095         }
1096         netif_dbg(efx, hw, efx->net_dev, "hardware reset complete\n");
1097
1098         return 0;
1099
1100         /* pci_save_state() and pci_restore_state() MUST be called in pairs */
1101 fail2:
1102 fail3:
1103         pci_restore_state(efx->pci_dev);
1104 fail1:
1105 fail4:
1106 fail5:
1107         return rc;
1108 }
1109
1110 static void falcon_monitor(struct efx_nic *efx)
1111 {
1112         bool link_changed;
1113         int rc;
1114
1115         BUG_ON(!mutex_is_locked(&efx->mac_lock));
1116
1117         rc = falcon_board(efx)->type->monitor(efx);
1118         if (rc) {
1119                 netif_err(efx, hw, efx->net_dev,
1120                           "Board sensor %s; shutting down PHY\n",
1121                           (rc == -ERANGE) ? "reported fault" : "failed");
1122                 efx->phy_mode |= PHY_MODE_LOW_POWER;
1123                 rc = __efx_reconfigure_port(efx);
1124                 WARN_ON(rc);
1125         }
1126
1127         if (LOOPBACK_INTERNAL(efx))
1128                 link_changed = falcon_loopback_link_poll(efx);
1129         else
1130                 link_changed = efx->phy_op->poll(efx);
1131
1132         if (link_changed) {
1133                 falcon_stop_nic_stats(efx);
1134                 falcon_deconfigure_mac_wrapper(efx);
1135
1136                 falcon_reset_macs(efx);
1137                 rc = efx->mac_op->reconfigure(efx);
1138                 BUG_ON(rc);
1139
1140                 falcon_start_nic_stats(efx);
1141
1142                 efx_link_status_changed(efx);
1143         }
1144
1145         falcon_poll_xmac(efx);
1146 }
1147
1148 /* Zeroes out the SRAM contents.  This routine must be called in
1149  * process context and is allowed to sleep.
1150  */
1151 static int falcon_reset_sram(struct efx_nic *efx)
1152 {
1153         efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
1154         int count;
1155
1156         /* Set the SRAM wake/sleep GPIO appropriately. */
1157         efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
1158         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
1159         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
1160         efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
1161
1162         /* Initiate SRAM reset */
1163         EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
1164                              FRF_AZ_SRM_INIT_EN, 1,
1165                              FRF_AZ_SRM_NB_SZ, 0);
1166         efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
1167
1168         /* Wait for SRAM reset to complete */
1169         count = 0;
1170         do {
1171                 netif_dbg(efx, hw, efx->net_dev,
1172                           "waiting for SRAM reset (attempt %d)...\n", count);
1173
1174                 /* SRAM reset is slow; expect around 16ms */
1175                 schedule_timeout_uninterruptible(HZ / 50);
1176
1177                 /* Check for reset complete */
1178                 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
1179                 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
1180                         netif_dbg(efx, hw, efx->net_dev,
1181                                   "SRAM reset complete\n");
1182
1183                         return 0;
1184                 }
1185         } while (++count < 20); /* wait upto 0.4 sec */
1186
1187         netif_err(efx, hw, efx->net_dev, "timed out waiting for SRAM reset\n");
1188         return -ETIMEDOUT;
1189 }
1190
1191 static int falcon_spi_device_init(struct efx_nic *efx,
1192                                   struct efx_spi_device **spi_device_ret,
1193                                   unsigned int device_id, u32 device_type)
1194 {
1195         struct efx_spi_device *spi_device;
1196
1197         if (device_type != 0) {
1198                 spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL);
1199                 if (!spi_device)
1200                         return -ENOMEM;
1201                 spi_device->device_id = device_id;
1202                 spi_device->size =
1203                         1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
1204                 spi_device->addr_len =
1205                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
1206                 spi_device->munge_address = (spi_device->size == 1 << 9 &&
1207                                              spi_device->addr_len == 1);
1208                 spi_device->erase_command =
1209                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
1210                 spi_device->erase_size =
1211                         1 << SPI_DEV_TYPE_FIELD(device_type,
1212                                                 SPI_DEV_TYPE_ERASE_SIZE);
1213                 spi_device->block_size =
1214                         1 << SPI_DEV_TYPE_FIELD(device_type,
1215                                                 SPI_DEV_TYPE_BLOCK_SIZE);
1216         } else {
1217                 spi_device = NULL;
1218         }
1219
1220         kfree(*spi_device_ret);
1221         *spi_device_ret = spi_device;
1222         return 0;
1223 }
1224
1225 static void falcon_remove_spi_devices(struct efx_nic *efx)
1226 {
1227         kfree(efx->spi_eeprom);
1228         efx->spi_eeprom = NULL;
1229         kfree(efx->spi_flash);
1230         efx->spi_flash = NULL;
1231 }
1232
1233 /* Extract non-volatile configuration */
1234 static int falcon_probe_nvconfig(struct efx_nic *efx)
1235 {
1236         struct falcon_nvconfig *nvconfig;
1237         int rc;
1238
1239         nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
1240         if (!nvconfig)
1241                 return -ENOMEM;
1242
1243         rc = falcon_read_nvram(efx, nvconfig);
1244         if (rc)
1245                 goto fail1;
1246
1247         efx->phy_type = nvconfig->board_v2.port0_phy_type;
1248         efx->mdio.prtad = nvconfig->board_v2.port0_phy_addr;
1249
1250         if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
1251                 rc = falcon_spi_device_init(
1252                         efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
1253                         le32_to_cpu(nvconfig->board_v3
1254                                     .spi_device_type[FFE_AB_SPI_DEVICE_FLASH]));
1255                 if (rc)
1256                         goto fail2;
1257                 rc = falcon_spi_device_init(
1258                         efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
1259                         le32_to_cpu(nvconfig->board_v3
1260                                     .spi_device_type[FFE_AB_SPI_DEVICE_EEPROM]));
1261                 if (rc)
1262                         goto fail2;
1263         }
1264
1265         /* Read the MAC addresses */
1266         memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
1267
1268         netif_dbg(efx, probe, efx->net_dev, "PHY is %d phy_id %d\n",
1269                   efx->phy_type, efx->mdio.prtad);
1270
1271         rc = falcon_probe_board(efx,
1272                                 le16_to_cpu(nvconfig->board_v2.board_revision));
1273         if (rc)
1274                 goto fail2;
1275
1276         kfree(nvconfig);
1277         return 0;
1278
1279  fail2:
1280         falcon_remove_spi_devices(efx);
1281  fail1:
1282         kfree(nvconfig);
1283         return rc;
1284 }
1285
1286 /* Probe all SPI devices on the NIC */
1287 static void falcon_probe_spi_devices(struct efx_nic *efx)
1288 {
1289         efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
1290         int boot_dev;
1291
1292         efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
1293         efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
1294         efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
1295
1296         if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
1297                 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
1298                             FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
1299                 netif_dbg(efx, probe, efx->net_dev, "Booted from %s\n",
1300                           boot_dev == FFE_AB_SPI_DEVICE_FLASH ?
1301                           "flash" : "EEPROM");
1302         } else {
1303                 /* Disable VPD and set clock dividers to safe
1304                  * values for initial programming. */
1305                 boot_dev = -1;
1306                 netif_dbg(efx, probe, efx->net_dev,
1307                           "Booted from internal ASIC settings;"
1308                           " setting SPI config\n");
1309                 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
1310                                      /* 125 MHz / 7 ~= 20 MHz */
1311                                      FRF_AB_EE_SF_CLOCK_DIV, 7,
1312                                      /* 125 MHz / 63 ~= 2 MHz */
1313                                      FRF_AB_EE_EE_CLOCK_DIV, 63);
1314                 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
1315         }
1316
1317         if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
1318                 falcon_spi_device_init(efx, &efx->spi_flash,
1319                                        FFE_AB_SPI_DEVICE_FLASH,
1320                                        default_flash_type);
1321         if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
1322                 falcon_spi_device_init(efx, &efx->spi_eeprom,
1323                                        FFE_AB_SPI_DEVICE_EEPROM,
1324                                        large_eeprom_type);
1325 }
1326
1327 static int falcon_probe_nic(struct efx_nic *efx)
1328 {
1329         struct falcon_nic_data *nic_data;
1330         struct falcon_board *board;
1331         int rc;
1332
1333         /* Allocate storage for hardware specific data */
1334         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
1335         if (!nic_data)
1336                 return -ENOMEM;
1337         efx->nic_data = nic_data;
1338
1339         rc = -ENODEV;
1340
1341         if (efx_nic_fpga_ver(efx) != 0) {
1342                 netif_err(efx, probe, efx->net_dev,
1343                           "Falcon FPGA not supported\n");
1344                 goto fail1;
1345         }
1346
1347         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1348                 efx_oword_t nic_stat;
1349                 struct pci_dev *dev;
1350                 u8 pci_rev = efx->pci_dev->revision;
1351
1352                 if ((pci_rev == 0xff) || (pci_rev == 0)) {
1353                         netif_err(efx, probe, efx->net_dev,
1354                                   "Falcon rev A0 not supported\n");
1355                         goto fail1;
1356                 }
1357                 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
1358                 if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) {
1359                         netif_err(efx, probe, efx->net_dev,
1360                                   "Falcon rev A1 1G not supported\n");
1361                         goto fail1;
1362                 }
1363                 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
1364                         netif_err(efx, probe, efx->net_dev,
1365                                   "Falcon rev A1 PCI-X not supported\n");
1366                         goto fail1;
1367                 }
1368
1369                 dev = pci_dev_get(efx->pci_dev);
1370                 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
1371                                              dev))) {
1372                         if (dev->bus == efx->pci_dev->bus &&
1373                             dev->devfn == efx->pci_dev->devfn + 1) {
1374                                 nic_data->pci_dev2 = dev;
1375                                 break;
1376                         }
1377                 }
1378                 if (!nic_data->pci_dev2) {
1379                         netif_err(efx, probe, efx->net_dev,
1380                                   "failed to find secondary function\n");
1381                         rc = -ENODEV;
1382                         goto fail2;
1383                 }
1384         }
1385
1386         /* Now we can reset the NIC */
1387         rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
1388         if (rc) {
1389                 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
1390                 goto fail3;
1391         }
1392
1393         /* Allocate memory for INT_KER */
1394         rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
1395         if (rc)
1396                 goto fail4;
1397         BUG_ON(efx->irq_status.dma_addr & 0x0f);
1398
1399         netif_dbg(efx, probe, efx->net_dev,
1400                   "INT_KER at %llx (virt %p phys %llx)\n",
1401                   (u64)efx->irq_status.dma_addr,
1402                   efx->irq_status.addr,
1403                   (u64)virt_to_phys(efx->irq_status.addr));
1404
1405         falcon_probe_spi_devices(efx);
1406
1407         /* Read in the non-volatile configuration */
1408         rc = falcon_probe_nvconfig(efx);
1409         if (rc) {
1410                 if (rc == -EINVAL)
1411                         netif_err(efx, probe, efx->net_dev, "NVRAM is invalid\n");
1412                 goto fail5;
1413         }
1414
1415         /* Initialise I2C adapter */
1416         board = falcon_board(efx);
1417         board->i2c_adap.owner = THIS_MODULE;
1418         board->i2c_data = falcon_i2c_bit_operations;
1419         board->i2c_data.data = efx;
1420         board->i2c_adap.algo_data = &board->i2c_data;
1421         board->i2c_adap.dev.parent = &efx->pci_dev->dev;
1422         strlcpy(board->i2c_adap.name, "SFC4000 GPIO",
1423                 sizeof(board->i2c_adap.name));
1424         rc = i2c_bit_add_bus(&board->i2c_adap);
1425         if (rc)
1426                 goto fail5;
1427
1428         rc = falcon_board(efx)->type->init(efx);
1429         if (rc) {
1430                 netif_err(efx, probe, efx->net_dev,
1431                           "failed to initialise board\n");
1432                 goto fail6;
1433         }
1434
1435         nic_data->stats_disable_count = 1;
1436         setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func,
1437                     (unsigned long)efx);
1438
1439         return 0;
1440
1441  fail6:
1442         BUG_ON(i2c_del_adapter(&board->i2c_adap));
1443         memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
1444  fail5:
1445         falcon_remove_spi_devices(efx);
1446         efx_nic_free_buffer(efx, &efx->irq_status);
1447  fail4:
1448  fail3:
1449         if (nic_data->pci_dev2) {
1450                 pci_dev_put(nic_data->pci_dev2);
1451                 nic_data->pci_dev2 = NULL;
1452         }
1453  fail2:
1454  fail1:
1455         kfree(efx->nic_data);
1456         return rc;
1457 }
1458
1459 static void falcon_init_rx_cfg(struct efx_nic *efx)
1460 {
1461         /* Prior to Siena the RX DMA engine will split each frame at
1462          * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
1463          * be so large that that never happens. */
1464         const unsigned huge_buf_size = (3 * 4096) >> 5;
1465         /* RX control FIFO thresholds (32 entries) */
1466         const unsigned ctrl_xon_thr = 20;
1467         const unsigned ctrl_xoff_thr = 25;
1468         /* RX data FIFO thresholds (256-byte units; size varies) */
1469         int data_xon_thr = efx_nic_rx_xon_thresh >> 8;
1470         int data_xoff_thr = efx_nic_rx_xoff_thresh >> 8;
1471         efx_oword_t reg;
1472
1473         efx_reado(efx, &reg, FR_AZ_RX_CFG);
1474         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1475                 /* Data FIFO size is 5.5K */
1476                 if (data_xon_thr < 0)
1477                         data_xon_thr = 512 >> 8;
1478                 if (data_xoff_thr < 0)
1479                         data_xoff_thr = 2048 >> 8;
1480                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
1481                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
1482                                     huge_buf_size);
1483                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr);
1484                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr);
1485                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
1486                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
1487         } else {
1488                 /* Data FIFO size is 80K; register fields moved */
1489                 if (data_xon_thr < 0)
1490                         data_xon_thr = 27648 >> 8; /* ~3*max MTU */
1491                 if (data_xoff_thr < 0)
1492                         data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
1493                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
1494                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
1495                                     huge_buf_size);
1496                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr);
1497                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr);
1498                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
1499                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
1500                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
1501
1502                 /* Enable hash insertion. This is broken for the
1503                  * 'Falcon' hash so also select Toeplitz TCP/IPv4 and
1504                  * IPv4 hashes. */
1505                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_INSRT_HDR, 1);
1506                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_ALG, 1);
1507                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_IP_HASH, 1);
1508         }
1509         /* Always enable XOFF signal from RX FIFO.  We enable
1510          * or disable transmission of pause frames at the MAC. */
1511         EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
1512         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1513 }
1514
1515 /* This call performs hardware-specific global initialisation, such as
1516  * defining the descriptor cache sizes and number of RSS channels.
1517  * It does not set up any buffers, descriptor rings or event queues.
1518  */
1519 static int falcon_init_nic(struct efx_nic *efx)
1520 {
1521         efx_oword_t temp;
1522         int rc;
1523
1524         /* Use on-chip SRAM */
1525         efx_reado(efx, &temp, FR_AB_NIC_STAT);
1526         EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
1527         efx_writeo(efx, &temp, FR_AB_NIC_STAT);
1528
1529         rc = falcon_reset_sram(efx);
1530         if (rc)
1531                 return rc;
1532
1533         /* Clear the parity enables on the TX data fifos as
1534          * they produce false parity errors because of timing issues
1535          */
1536         if (EFX_WORKAROUND_5129(efx)) {
1537                 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
1538                 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
1539                 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
1540         }
1541
1542         if (EFX_WORKAROUND_7244(efx)) {
1543                 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
1544                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
1545                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
1546                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
1547                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
1548                 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
1549         }
1550
1551         /* XXX This is documented only for Falcon A0/A1 */
1552         /* Setup RX.  Wait for descriptor is broken and must
1553          * be disabled.  RXDP recovery shouldn't be needed, but is.
1554          */
1555         efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
1556         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
1557         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
1558         if (EFX_WORKAROUND_5583(efx))
1559                 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
1560         efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
1561
1562         /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
1563          * descriptors (which is bad).
1564          */
1565         efx_reado(efx, &temp, FR_AZ_TX_CFG);
1566         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
1567         efx_writeo(efx, &temp, FR_AZ_TX_CFG);
1568
1569         falcon_init_rx_cfg(efx);
1570
1571         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1572                 /* Set hash key for IPv4 */
1573                 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
1574                 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
1575
1576                 /* Set destination of both TX and RX Flush events */
1577                 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
1578                 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
1579         }
1580
1581         efx_nic_init_common(efx);
1582
1583         return 0;
1584 }
1585
1586 static void falcon_remove_nic(struct efx_nic *efx)
1587 {
1588         struct falcon_nic_data *nic_data = efx->nic_data;
1589         struct falcon_board *board = falcon_board(efx);
1590         int rc;
1591
1592         board->type->fini(efx);
1593
1594         /* Remove I2C adapter and clear it in preparation for a retry */
1595         rc = i2c_del_adapter(&board->i2c_adap);
1596         BUG_ON(rc);
1597         memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
1598
1599         falcon_remove_spi_devices(efx);
1600         efx_nic_free_buffer(efx, &efx->irq_status);
1601
1602         falcon_reset_hw(efx, RESET_TYPE_ALL);
1603
1604         /* Release the second function after the reset */
1605         if (nic_data->pci_dev2) {
1606                 pci_dev_put(nic_data->pci_dev2);
1607                 nic_data->pci_dev2 = NULL;
1608         }
1609
1610         /* Tear down the private nic state */
1611         kfree(efx->nic_data);
1612         efx->nic_data = NULL;
1613 }
1614
1615 static void falcon_update_nic_stats(struct efx_nic *efx)
1616 {
1617         struct falcon_nic_data *nic_data = efx->nic_data;
1618         efx_oword_t cnt;
1619
1620         if (nic_data->stats_disable_count)
1621                 return;
1622
1623         efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
1624         efx->n_rx_nodesc_drop_cnt +=
1625                 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
1626
1627         if (nic_data->stats_pending &&
1628             *nic_data->stats_dma_done == FALCON_STATS_DONE) {
1629                 nic_data->stats_pending = false;
1630                 rmb(); /* read the done flag before the stats */
1631                 efx->mac_op->update_stats(efx);
1632         }
1633 }
1634
1635 void falcon_start_nic_stats(struct efx_nic *efx)
1636 {
1637         struct falcon_nic_data *nic_data = efx->nic_data;
1638
1639         spin_lock_bh(&efx->stats_lock);
1640         if (--nic_data->stats_disable_count == 0)
1641                 falcon_stats_request(efx);
1642         spin_unlock_bh(&efx->stats_lock);
1643 }
1644
1645 void falcon_stop_nic_stats(struct efx_nic *efx)
1646 {
1647         struct falcon_nic_data *nic_data = efx->nic_data;
1648         int i;
1649
1650         might_sleep();
1651
1652         spin_lock_bh(&efx->stats_lock);
1653         ++nic_data->stats_disable_count;
1654         spin_unlock_bh(&efx->stats_lock);
1655
1656         del_timer_sync(&nic_data->stats_timer);
1657
1658         /* Wait enough time for the most recent transfer to
1659          * complete. */
1660         for (i = 0; i < 4 && nic_data->stats_pending; i++) {
1661                 if (*nic_data->stats_dma_done == FALCON_STATS_DONE)
1662                         break;
1663                 msleep(1);
1664         }
1665
1666         spin_lock_bh(&efx->stats_lock);
1667         falcon_stats_complete(efx);
1668         spin_unlock_bh(&efx->stats_lock);
1669 }
1670
1671 static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
1672 {
1673         falcon_board(efx)->type->set_id_led(efx, mode);
1674 }
1675
1676 /**************************************************************************
1677  *
1678  * Wake on LAN
1679  *
1680  **************************************************************************
1681  */
1682
1683 static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1684 {
1685         wol->supported = 0;
1686         wol->wolopts = 0;
1687         memset(&wol->sopass, 0, sizeof(wol->sopass));
1688 }
1689
1690 static int falcon_set_wol(struct efx_nic *efx, u32 type)
1691 {
1692         if (type != 0)
1693                 return -EINVAL;
1694         return 0;
1695 }
1696
1697 /**************************************************************************
1698  *
1699  * Revision-dependent attributes used by efx.c and nic.c
1700  *
1701  **************************************************************************
1702  */
1703
1704 struct efx_nic_type falcon_a1_nic_type = {
1705         .probe = falcon_probe_nic,
1706         .remove = falcon_remove_nic,
1707         .init = falcon_init_nic,
1708         .fini = efx_port_dummy_op_void,
1709         .monitor = falcon_monitor,
1710         .reset = falcon_reset_hw,
1711         .probe_port = falcon_probe_port,
1712         .remove_port = falcon_remove_port,
1713         .prepare_flush = falcon_prepare_flush,
1714         .update_stats = falcon_update_nic_stats,
1715         .start_stats = falcon_start_nic_stats,
1716         .stop_stats = falcon_stop_nic_stats,
1717         .set_id_led = falcon_set_id_led,
1718         .push_irq_moderation = falcon_push_irq_moderation,
1719         .push_multicast_hash = falcon_push_multicast_hash,
1720         .reconfigure_port = falcon_reconfigure_port,
1721         .get_wol = falcon_get_wol,
1722         .set_wol = falcon_set_wol,
1723         .resume_wol = efx_port_dummy_op_void,
1724         .test_nvram = falcon_test_nvram,
1725         .default_mac_ops = &falcon_xmac_operations,
1726
1727         .revision = EFX_REV_FALCON_A1,
1728         .mem_map_size = 0x20000,
1729         .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
1730         .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
1731         .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
1732         .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
1733         .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
1734         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1735         .rx_buffer_padding = 0x24,
1736         .max_interrupt_mode = EFX_INT_MODE_MSI,
1737         .phys_addr_channels = 4,
1738         .tx_dc_base = 0x130000,
1739         .rx_dc_base = 0x100000,
1740         .offload_features = NETIF_F_IP_CSUM,
1741         .reset_world_flags = ETH_RESET_IRQ,
1742 };
1743
1744 struct efx_nic_type falcon_b0_nic_type = {
1745         .probe = falcon_probe_nic,
1746         .remove = falcon_remove_nic,
1747         .init = falcon_init_nic,
1748         .fini = efx_port_dummy_op_void,
1749         .monitor = falcon_monitor,
1750         .reset = falcon_reset_hw,
1751         .probe_port = falcon_probe_port,
1752         .remove_port = falcon_remove_port,
1753         .prepare_flush = falcon_prepare_flush,
1754         .update_stats = falcon_update_nic_stats,
1755         .start_stats = falcon_start_nic_stats,
1756         .stop_stats = falcon_stop_nic_stats,
1757         .set_id_led = falcon_set_id_led,
1758         .push_irq_moderation = falcon_push_irq_moderation,
1759         .push_multicast_hash = falcon_push_multicast_hash,
1760         .reconfigure_port = falcon_reconfigure_port,
1761         .get_wol = falcon_get_wol,
1762         .set_wol = falcon_set_wol,
1763         .resume_wol = efx_port_dummy_op_void,
1764         .test_registers = falcon_b0_test_registers,
1765         .test_nvram = falcon_test_nvram,
1766         .default_mac_ops = &falcon_xmac_operations,
1767
1768         .revision = EFX_REV_FALCON_B0,
1769         /* Map everything up to and including the RSS indirection
1770          * table.  Don't map MSI-X table, MSI-X PBA since Linux
1771          * requires that they not be mapped.  */
1772         .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
1773                          FR_BZ_RX_INDIRECTION_TBL_STEP *
1774                          FR_BZ_RX_INDIRECTION_TBL_ROWS),
1775         .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
1776         .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
1777         .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
1778         .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
1779         .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
1780         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1781         .rx_buffer_hash_size = 0x10,
1782         .rx_buffer_padding = 0,
1783         .max_interrupt_mode = EFX_INT_MODE_MSIX,
1784         .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
1785                                    * interrupt handler only supports 32
1786                                    * channels */
1787         .tx_dc_base = 0x130000,
1788         .rx_dc_base = 0x100000,
1789         .offload_features = NETIF_F_IP_CSUM | NETIF_F_RXHASH | NETIF_F_NTUPLE,
1790         .reset_world_flags = ETH_RESET_IRQ,
1791 };
1792