2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
18 #include <linux/pci.h>
19 #include <linux/pci-aspm.h>
27 static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
28 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
29 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
30 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
31 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
32 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
33 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
34 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
35 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
36 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
37 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
38 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
39 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
40 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
41 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
42 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
43 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
44 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
45 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
48 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
50 /* return bus cachesize in 4B word units */
51 static void ath5k_pci_read_cachesize(struct ath_common *common, int *csz)
53 struct ath5k_softc *sc = (struct ath5k_softc *) common->priv;
56 pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, &u8tmp);
60 * This check was put in to avoid "unplesant" consequences if
61 * the bootrom has not fully initialized all PCI devices.
62 * Sometimes the cache line size register is not set
66 *csz = L1_CACHE_BYTES >> 2; /* Use the default size */
72 bool ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data)
74 struct ath5k_hw *ah = (struct ath5k_hw *) common->ah;
78 * Initialize EEPROM access
80 if (ah->ah_version == AR5K_AR5210) {
81 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
82 (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
84 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
85 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
86 AR5K_EEPROM_CMD_READ);
89 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
90 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
91 if (status & AR5K_EEPROM_STAT_RDDONE) {
92 if (status & AR5K_EEPROM_STAT_RDERR)
94 *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
104 int ath5k_hw_read_srev(struct ath5k_hw *ah)
106 ah->ah_mac_srev = ath5k_hw_reg_read(ah, AR5K_SREV);
110 /* Common ath_bus_opts structure */
111 static const struct ath_bus_ops ath_pci_bus_ops = {
112 .ath_bus_type = ATH_PCI,
113 .read_cachesize = ath5k_pci_read_cachesize,
114 .eeprom_read = ath5k_pci_eeprom_read,
117 /********************\
118 * PCI Initialization *
119 \********************/
122 ath5k_pci_probe(struct pci_dev *pdev,
123 const struct pci_device_id *id)
126 struct ath5k_softc *sc;
127 struct ieee80211_hw *hw;
132 * L0s needs to be disabled on all ath5k cards.
134 * For distributions shipping with CONFIG_PCIEASPM (this will be enabled
135 * by default in the future in 2.6.36) this will also mean both L1 and
136 * L0s will be disabled when a pre 1.1 PCIe device is detected. We do
137 * know L1 works correctly even for all ath5k pre 1.1 PCIe devices
138 * though but cannot currently undue the effect of a blacklist, for
139 * details you can read pcie_aspm_sanity_check() and see how it adjusts
140 * the device link capability.
142 * It may be possible in the future to implement some PCI API to allow
143 * drivers to override blacklists for pre 1.1 PCIe but for now it is
144 * best to accept that both L0s and L1 will be disabled completely for
145 * distributions shipping with CONFIG_PCIEASPM rather than having this
146 * issue present. Motivation for adding this new API will be to help
147 * with power consumption for some of these devices.
149 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);
151 ret = pci_enable_device(pdev);
153 dev_err(&pdev->dev, "can't enable device\n");
157 /* XXX 32-bit addressing only */
158 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
160 dev_err(&pdev->dev, "32-bit DMA not available\n");
165 * Cache line size is used to size and align various
166 * structures used to communicate with the hardware.
168 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
171 * Linux 2.4.18 (at least) writes the cache line size
172 * register as a 16-bit wide register which is wrong.
173 * We must have this setup properly for rx buffer
174 * DMA to work so force a reasonable value here if it
177 csz = L1_CACHE_BYTES >> 2;
178 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
181 * The default setting of latency timer yields poor results,
182 * set it to the value used by other systems. It may be worth
183 * tweaking this setting more.
185 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
187 /* Enable bus mastering */
188 pci_set_master(pdev);
191 * Disable the RETRY_TIMEOUT register (0x41) to keep
192 * PCI Tx retries from interfering with C3 CPU state.
194 pci_write_config_byte(pdev, 0x41, 0);
196 ret = pci_request_region(pdev, 0, "ath5k");
198 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
202 mem = pci_iomap(pdev, 0, 0);
204 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
210 * Allocate hw (mac80211 main struct)
211 * and hw->priv (driver private data)
213 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
215 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
220 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
225 sc->dev = &pdev->dev;
227 sc->devid = id->device;
228 sc->iobase = mem; /* So we can unmap it on detach */
231 ret = ath5k_init_softc(sc, &ath_pci_bus_ops);
235 /* Set private data */
236 pci_set_drvdata(pdev, hw);
240 ieee80211_free_hw(hw);
242 pci_iounmap(pdev, mem);
244 pci_release_region(pdev, 0);
246 pci_disable_device(pdev);
251 static void __devexit
252 ath5k_pci_remove(struct pci_dev *pdev)
254 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
255 struct ath5k_softc *sc = hw->priv;
257 ath5k_deinit_softc(sc);
258 pci_iounmap(pdev, sc->iobase);
259 pci_release_region(pdev, 0);
260 pci_disable_device(pdev);
261 ieee80211_free_hw(hw);
264 #ifdef CONFIG_PM_SLEEP
265 static int ath5k_pci_suspend(struct device *dev)
267 struct ath5k_softc *sc = pci_get_drvdata(to_pci_dev(dev));
273 static int ath5k_pci_resume(struct device *dev)
275 struct pci_dev *pdev = to_pci_dev(dev);
276 struct ath5k_softc *sc = pci_get_drvdata(pdev);
279 * Suspend/Resume resets the PCI configuration space, so we have to
280 * re-disable the RETRY_TIMEOUT register (0x41) to keep
281 * PCI Tx retries from interfering with C3 CPU state
283 pci_write_config_byte(pdev, 0x41, 0);
285 ath5k_led_enable(sc);
289 static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
290 #define ATH5K_PM_OPS (&ath5k_pm_ops)
292 #define ATH5K_PM_OPS NULL
293 #endif /* CONFIG_PM_SLEEP */
295 static struct pci_driver ath5k_pci_driver = {
296 .name = KBUILD_MODNAME,
297 .id_table = ath5k_pci_id_table,
298 .probe = ath5k_pci_probe,
299 .remove = __devexit_p(ath5k_pci_remove),
300 .driver.pm = ATH5K_PM_OPS,
304 * Module init/exit functions
311 ret = pci_register_driver(&ath5k_pci_driver);
313 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
323 pci_unregister_driver(&ath5k_pci_driver);
326 module_init(init_ath5k_pci);
327 module_exit(exit_ath5k_pci);