drivers/net/wireless/rtlwifi/rtl8192se/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../efuse.h"
  32 #include "../base.h"
  33 #include "../regd.h"
  34 #include "../cam.h"
  35 #include "../ps.h"
  36 #include "../pci.h"
  37 #include "reg.h"
  38 #include "def.h"
  39 #include "phy.h"
  40 #include "dm.h"
  41 #include "fw.h"
  42 #include "led.h"
  43 #include "hw.h"
  44
  45 void rtl92se_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  46 {
  47         struct rtl_priv *rtlpriv = rtl_priv(hw);
  48         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  49         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  50
  51         switch (variable) {
  52         case HW_VAR_RCR: {
  53                         *((u32 *) (val)) = rtlpci->receive_config;
  54                         break;
  55                 }
  56         case HW_VAR_RF_STATE: {
  57                         *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
  58                         break;
  59                 }
  60         case HW_VAR_FW_PSMODE_STATUS: {
  61                         *((bool *) (val)) = ppsc->fw_current_inpsmode;
  62                         break;
  63                 }
  64         case HW_VAR_CORRECT_TSF: {
  65                         u64 tsf;
  66                         u32 *ptsf_low = (u32 *)&tsf;
  67                         u32 *ptsf_high = ((u32 *)&tsf) + 1;
  68
  69                         *ptsf_high = rtl_read_dword(rtlpriv, (TSFR + 4));
  70                         *ptsf_low = rtl_read_dword(rtlpriv, TSFR);
  71
  72                         *((u64 *) (val)) = tsf;
  73
  74                         break;
  75                 }
  76         case HW_VAR_MRC: {
  77                         *((bool *)(val)) = rtlpriv->dm.current_mrc_switch;
  78                         break;
  79                 }
  80         default: {
  81                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  82                          "switch case not processed\n");
  83                         break;
  84                 }
  85         }
  86 }
  87
  88 void rtl92se_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  89 {
  90         struct rtl_priv *rtlpriv = rtl_priv(hw);
  91         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  92         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  93         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  94         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  95         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  96
  97         switch (variable) {
  98         case HW_VAR_ETHER_ADDR:{
  99                         rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]);
 100                         rtl_write_word(rtlpriv, IDR4, ((u16 *)(val + 4))[0]);
 101                         break;
 102                 }
 103         case HW_VAR_BASIC_RATE:{
 104                         u16 rate_cfg = ((u16 *) val)[0];
 105                         u8 rate_index = 0;
 106
 107                         if (rtlhal->version == VERSION_8192S_ACUT)
 108                                 rate_cfg = rate_cfg & 0x150;
 109                         else
 110                                 rate_cfg = rate_cfg & 0x15f;
 111
 112                         rate_cfg |= 0x01;
 113
 114                         rtl_write_byte(rtlpriv, RRSR, rate_cfg & 0xff);
 115                         rtl_write_byte(rtlpriv, RRSR + 1,
 116                                        (rate_cfg >> 8) & 0xff);
 117
 118                         while (rate_cfg > 0x1) {
 119                                 rate_cfg = (rate_cfg >> 1);
 120                                 rate_index++;
 121                         }
 122                         rtl_write_byte(rtlpriv, INIRTSMCS_SEL, rate_index);
 123
 124                         break;
 125                 }
 126         case HW_VAR_BSSID:{
 127                         rtl_write_dword(rtlpriv, BSSIDR, ((u32 *)(val))[0]);
 128                         rtl_write_word(rtlpriv, BSSIDR + 4,
 129                                        ((u16 *)(val + 4))[0]);
 130                         break;
 131                 }
 132         case HW_VAR_SIFS:{
 133                         rtl_write_byte(rtlpriv, SIFS_OFDM, val[0]);
 134                         rtl_write_byte(rtlpriv, SIFS_OFDM + 1, val[1]);
 135                         break;
 136                 }
 137         case HW_VAR_SLOT_TIME:{
 138                         u8 e_aci;
 139
 140                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 141                                  "HW_VAR_SLOT_TIME %x\n", val[0]);
 142
 143                         rtl_write_byte(rtlpriv, SLOT_TIME, val[0]);
 144
 145                         for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 146                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 147                                                 HW_VAR_AC_PARAM,
 148                                                 (u8 *)(&e_aci));
 149                         }
 150                         break;
 151                 }
 152         case HW_VAR_ACK_PREAMBLE:{
 153                         u8 reg_tmp;
 154                         u8 short_preamble = (bool) (*(u8 *) val);
 155                         reg_tmp = (mac->cur_40_prime_sc) << 5;
 156                         if (short_preamble)
 157                                 reg_tmp |= 0x80;
 158
 159                         rtl_write_byte(rtlpriv, RRSR + 2, reg_tmp);
 160                         break;
 161                 }
 162         case HW_VAR_AMPDU_MIN_SPACE:{
 163                         u8 min_spacing_to_set;
 164                         u8 sec_min_space;
 165
 166                         min_spacing_to_set = *((u8 *)val);
 167                         if (min_spacing_to_set <= 7) {
 168                                 if (rtlpriv->sec.pairwise_enc_algorithm ==
 169                                     NO_ENCRYPTION)
 170                                         sec_min_space = 0;
 171                                 else
 172                                         sec_min_space = 1;
 173
 174                                 if (min_spacing_to_set < sec_min_space)
 175                                         min_spacing_to_set = sec_min_space;
 176                                 if (min_spacing_to_set > 5)
 177                                         min_spacing_to_set = 5;
 178
 179                                 mac->min_space_cfg =
 180                                                 ((mac->min_space_cfg & 0xf8) |
 181                                                 min_spacing_to_set);
 182
 183                                 *val = min_spacing_to_set;
 184
 185                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 186                                          "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 187                                          mac->min_space_cfg);
 188
 189                                 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
 190                                                mac->min_space_cfg);
 191                         }
 192                         break;
 193                 }
 194         case HW_VAR_SHORTGI_DENSITY:{
 195                         u8 density_to_set;
 196
 197                         density_to_set = *((u8 *) val);
 198                         mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
 199                         mac->min_space_cfg |= (density_to_set << 3);
 200
 201                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 202                                  "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 203                                  mac->min_space_cfg);
 204
 205                         rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
 206                                        mac->min_space_cfg);
 207
 208                         break;
 209                 }
 210         case HW_VAR_AMPDU_FACTOR:{
 211                         u8 factor_toset;
 212                         u8 regtoset;
 213                         u8 factorlevel[18] = {
 214                                 2, 4, 4, 7, 7, 13, 13,
 215                                 13, 2, 7, 7, 13, 13,
 216                                 15, 15, 15, 15, 0};
 217                         u8 index = 0;
 218
 219                         factor_toset = *((u8 *) val);
 220                         if (factor_toset <= 3) {
 221                                 factor_toset = (1 << (factor_toset + 2));
 222                                 if (factor_toset > 0xf)
 223                                         factor_toset = 0xf;
 224
 225                                 for (index = 0; index < 17; index++) {
 226                                         if (factorlevel[index] > factor_toset)
 227                                                 factorlevel[index] =
 228                                                                  factor_toset;
 229                                 }
 230
 231                                 for (index = 0; index < 8; index++) {
 232                                         regtoset = ((factorlevel[index * 2]) |
 233                                                     (factorlevel[index *
 234                                                     2 + 1] << 4));
 235                                         rtl_write_byte(rtlpriv,
 236                                                        AGGLEN_LMT_L + index,
 237                                                        regtoset);
 238                                 }
 239
 240                                 regtoset = ((factorlevel[16]) |
 241                                             (factorlevel[17] << 4));
 242                                 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, regtoset);
 243
 244                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 245                                          "Set HW_VAR_AMPDU_FACTOR: %#x\n",
 246                                          factor_toset);
 247                         }
 248                         break;
 249                 }
 250         case HW_VAR_AC_PARAM:{
 251                         u8 e_aci = *((u8 *) val);
 252                         rtl92s_dm_init_edca_turbo(hw);
 253
 254                         if (rtlpci->acm_method != eAcmWay2_SW)
 255                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 256                                                  HW_VAR_ACM_CTRL,
 257                                                  (u8 *)(&e_aci));
 258                         break;
 259                 }
 260         case HW_VAR_ACM_CTRL:{
 261                         u8 e_aci = *((u8 *) val);
 262                         union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)(&(
 263                                                         mac->ac[0].aifs));
 264                         u8 acm = p_aci_aifsn->f.acm;
 265                         u8 acm_ctrl = rtl_read_byte(rtlpriv, AcmHwCtrl);
 266
 267                         acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ?
 268                                    0x0 : 0x1);
 269
 270                         if (acm) {
 271                                 switch (e_aci) {
 272                                 case AC0_BE:
 273                                         acm_ctrl |= AcmHw_BeqEn;
 274                                         break;
 275                                 case AC2_VI:
 276                                         acm_ctrl |= AcmHw_ViqEn;
 277                                         break;
 278                                 case AC3_VO:
 279                                         acm_ctrl |= AcmHw_VoqEn;
 280                                         break;
 281                                 default:
 282                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 283                                                  "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 284                                                  acm);
 285                                         break;
 286                                 }
 287                         } else {
 288                                 switch (e_aci) {
 289                                 case AC0_BE:
 290                                         acm_ctrl &= (~AcmHw_BeqEn);
 291                                         break;
 292                                 case AC2_VI:
 293                                         acm_ctrl &= (~AcmHw_ViqEn);
 294                                         break;
 295                                 case AC3_VO:
 296                                         acm_ctrl &= (~AcmHw_BeqEn);
 297                                         break;
 298                                 default:
 299                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 300                                                  "switch case not processed\n");
 301                                         break;
 302                                 }
 303                         }
 304
 305                         RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 306                                  "HW_VAR_ACM_CTRL Write 0x%X\n", acm_ctrl);
 307                         rtl_write_byte(rtlpriv, AcmHwCtrl, acm_ctrl);
 308                         break;
 309                 }
 310         case HW_VAR_RCR:{
 311                         rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]);
 312                         rtlpci->receive_config = ((u32 *) (val))[0];
 313                         break;
 314                 }
 315         case HW_VAR_RETRY_LIMIT:{
 316                         u8 retry_limit = ((u8 *) (val))[0];
 317
 318                         rtl_write_word(rtlpriv, RETRY_LIMIT,
 319                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 320                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
 321                         break;
 322                 }
 323         case HW_VAR_DUAL_TSF_RST: {
 324                         break;
 325                 }
 326         case HW_VAR_EFUSE_BYTES: {
 327                         rtlefuse->efuse_usedbytes = *((u16 *) val);
 328                         break;
 329                 }
 330         case HW_VAR_EFUSE_USAGE: {
 331                         rtlefuse->efuse_usedpercentage = *((u8 *) val);
 332                         break;
 333                 }
 334         case HW_VAR_IO_CMD: {
 335                         break;
 336                 }
 337         case HW_VAR_WPA_CONFIG: {
 338                         rtl_write_byte(rtlpriv, REG_SECR, *((u8 *) val));
 339                         break;
 340                 }
 341         case HW_VAR_SET_RPWM:{
 342                         break;
 343                 }
 344         case HW_VAR_H2C_FW_PWRMODE:{
 345                         break;
 346                 }
 347         case HW_VAR_FW_PSMODE_STATUS: {
 348                         ppsc->fw_current_inpsmode = *((bool *) val);
 349                         break;
 350                 }
 351         case HW_VAR_H2C_FW_JOINBSSRPT:{
 352                         break;
 353                 }
 354         case HW_VAR_AID:{
 355                         break;
 356                 }
 357         case HW_VAR_CORRECT_TSF:{
 358                         break;
 359                 }
 360         case HW_VAR_MRC: {
 361                         bool bmrc_toset = *((bool *)val);
 362                         u8 u1bdata = 0;
 363
 364                         if (bmrc_toset) {
 365                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 366                                               MASKBYTE0, 0x33);
 367                                 u1bdata = (u8)rtl_get_bbreg(hw,
 368                                                 ROFDM1_TRXPATHENABLE,
 369                                                 MASKBYTE0);
 370                                 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
 371                                               MASKBYTE0,
 372                                               ((u1bdata & 0xf0) | 0x03));
 373                                 u1bdata = (u8)rtl_get_bbreg(hw,
 374                                                 ROFDM0_TRXPATHENABLE,
 375                                                 MASKBYTE1);
 376                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 377                                               MASKBYTE1,
 378                                               (u1bdata | 0x04));
 379
 380                                 /* Update current settings. */
 381                                 rtlpriv->dm.current_mrc_switch = bmrc_toset;
 382                         } else {
 383                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 384                                               MASKBYTE0, 0x13);
 385                                 u1bdata = (u8)rtl_get_bbreg(hw,
 386                                                  ROFDM1_TRXPATHENABLE,
 387                                                  MASKBYTE0);
 388                                 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
 389                                               MASKBYTE0,
 390                                               ((u1bdata & 0xf0) | 0x01));
 391                                 u1bdata = (u8)rtl_get_bbreg(hw,
 392                                                 ROFDM0_TRXPATHENABLE,
 393                                                 MASKBYTE1);
 394                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 395                                               MASKBYTE1, (u1bdata & 0xfb));
 396
 397                                 /* Update current settings. */
 398                                 rtlpriv->dm.current_mrc_switch = bmrc_toset;
 399                         }
 400
 401                         break;
 402                 }
 403         default:
 404                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 405                          "switch case not processed\n");
 406                 break;
 407         }
 408
 409 }
 410
 411 void rtl92se_enable_hw_security_config(struct ieee80211_hw *hw)
 412 {
 413         struct rtl_priv *rtlpriv = rtl_priv(hw);
 414         u8 sec_reg_value = 0x0;
 415
 416         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 417                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
 418                  rtlpriv->sec.pairwise_enc_algorithm,
 419                  rtlpriv->sec.group_enc_algorithm);
 420
 421         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 422                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
 423                          "not open hw encryption\n");
 424                 return;
 425         }
 426
 427         sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
 428
 429         if (rtlpriv->sec.use_defaultkey) {
 430                 sec_reg_value |= SCR_TXUSEDK;
 431                 sec_reg_value |= SCR_RXUSEDK;
 432         }
 433
 434         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",
 435                  sec_reg_value);
 436
 437         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
 438
 439 }
 440
 441 static u8 _rtl92ce_halset_sysclk(struct ieee80211_hw *hw, u8 data)
 442 {
 443         struct rtl_priv *rtlpriv = rtl_priv(hw);
 444         u8 waitcount = 100;
 445         bool bresult = false;
 446         u8 tmpvalue;
 447
 448         rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
 449
 450         /* Wait the MAC synchronized. */
 451         udelay(400);
 452
 453         /* Check if it is set ready. */
 454         tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
 455         bresult = ((tmpvalue & BIT(7)) == (data & BIT(7)));
 456
 457         if ((data & (BIT(6) | BIT(7))) == false) {
 458                 waitcount = 100;
 459                 tmpvalue = 0;
 460
 461                 while (1) {
 462                         waitcount--;
 463
 464                         tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
 465                         if ((tmpvalue & BIT(6)))
 466                                 break;
 467
 468                         pr_err("wait for BIT(6) return value %x\n", tmpvalue);
 469                         if (waitcount == 0)
 470                                 break;
 471
 472                         udelay(10);
 473                 }
 474
 475                 if (waitcount == 0)
 476                         bresult = false;
 477                 else
 478                         bresult = true;
 479         }
 480
 481         return bresult;
 482 }
 483
 484 void rtl8192se_gpiobit3_cfg_inputmode(struct ieee80211_hw *hw)
 485 {
 486         struct rtl_priv *rtlpriv = rtl_priv(hw);
 487         u8 u1tmp;
 488
 489         /* The following config GPIO function */
 490         rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
 491         u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
 492
 493         /* config GPIO3 to input */
 494         u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
 495         rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
 496
 497 }
 498
 499 static u8 _rtl92se_rf_onoff_detect(struct ieee80211_hw *hw)
 500 {
 501         struct rtl_priv *rtlpriv = rtl_priv(hw);
 502         u8 u1tmp;
 503         u8 retval = ERFON;
 504
 505         /* The following config GPIO function */
 506         rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
 507         u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
 508
 509         /* config GPIO3 to input */
 510         u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
 511         rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
 512
 513         /* On some of the platform, driver cannot read correct
 514          * value without delay between Write_GPIO_SEL and Read_GPIO_IN */
 515         mdelay(10);
 516
 517         /* check GPIO3 */
 518         u1tmp = rtl_read_byte(rtlpriv, GPIO_IN_SE);
 519         retval = (u1tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? ERFON : ERFOFF;
 520
 521         return retval;
 522 }
 523
 524 static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw *hw)
 525 {
 526         struct rtl_priv *rtlpriv = rtl_priv(hw);
 527         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 528         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 529
 530         u8 i;
 531         u8 tmpu1b;
 532         u16 tmpu2b;
 533         u8 pollingcnt = 20;
 534
 535         if (rtlpci->first_init) {
 536                 /* Reset PCIE Digital */
 537                 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
 538                 tmpu1b &= 0xFE;
 539                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
 540                 udelay(1);
 541                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b | BIT(0));
 542         }
 543
 544         /* Switch to SW IO control */
 545         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
 546         if (tmpu1b & BIT(7)) {
 547                 tmpu1b &= ~(BIT(6) | BIT(7));
 548
 549                 /* Set failed, return to prevent hang. */
 550                 if (!_rtl92ce_halset_sysclk(hw, tmpu1b))
 551                         return;
 552         }
 553
 554         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
 555         udelay(50);
 556         rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
 557         udelay(50);
 558
 559         /* Clear FW RPWM for FW control LPS.*/
 560         rtl_write_byte(rtlpriv, RPWM, 0x0);
 561
 562         /* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */
 563         tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
 564         tmpu1b &= 0x73;
 565         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
 566         /* wait for BIT 10/11/15 to pull high automatically!! */
 567         mdelay(1);
 568
 569         rtl_write_byte(rtlpriv, CMDR, 0);
 570         rtl_write_byte(rtlpriv, TCR, 0);
 571
 572         /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
 573         tmpu1b = rtl_read_byte(rtlpriv, 0x562);
 574         tmpu1b |= 0x08;
 575         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
 576         tmpu1b &= ~(BIT(3));
 577         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
 578
 579         /* Enable AFE clock source */
 580         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
 581         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
 582         /* Delay 1.5ms */
 583         mdelay(2);
 584         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
 585         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
 586
 587         /* Enable AFE Macro Block's Bandgap */
 588         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
 589         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
 590         mdelay(1);
 591
 592         /* Enable AFE Mbias */
 593         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
 594         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
 595         mdelay(1);
 596
 597         /* Enable LDOA15 block  */
 598         tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
 599         rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
 600
 601         /* Set Digital Vdd to Retention isolation Path. */
 602         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
 603         rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
 604
 605         /* For warm reboot NIC disappera bug. */
 606         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 607         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
 608
 609         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
 610
 611         /* Enable AFE PLL Macro Block */
 612         /* We need to delay 100u before enabling PLL. */
 613         udelay(200);
 614         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
 615         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
 616
 617         /* for divider reset  */
 618         udelay(100);
 619         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) |
 620                        BIT(4) | BIT(6)));
 621         udelay(10);
 622         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
 623         udelay(10);
 624
 625         /* Enable MAC 80MHZ clock  */
 626         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
 627         rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
 628         mdelay(1);
 629
 630         /* Release isolation AFE PLL & MD */
 631         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
 632
 633         /* Enable MAC clock */
 634         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
 635         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
 636
 637         /* Enable Core digital and enable IOREG R/W */
 638         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 639         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
 640
 641         tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
 642         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b & ~(BIT(7)));
 643
 644         /* enable REG_EN */
 645         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
 646
 647         /* Switch the control path. */
 648         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
 649         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
 650
 651         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
 652         tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
 653         if (!_rtl92ce_halset_sysclk(hw, tmpu1b))
 654                 return; /* Set failed, return to prevent hang. */
 655
 656         rtl_write_word(rtlpriv, CMDR, 0x07FC);
 657
 658         /* MH We must enable the section of code to prevent load IMEM fail. */
 659         /* Load MAC register from WMAc temporarily We simulate macreg. */
 660         /* txt HW will provide MAC txt later  */
 661         rtl_write_byte(rtlpriv, 0x6, 0x30);
 662         rtl_write_byte(rtlpriv, 0x49, 0xf0);
 663
 664         rtl_write_byte(rtlpriv, 0x4b, 0x81);
 665
 666         rtl_write_byte(rtlpriv, 0xb5, 0x21);
 667
 668         rtl_write_byte(rtlpriv, 0xdc, 0xff);
 669         rtl_write_byte(rtlpriv, 0xdd, 0xff);
 670         rtl_write_byte(rtlpriv, 0xde, 0xff);
 671         rtl_write_byte(rtlpriv, 0xdf, 0xff);
 672
 673         rtl_write_byte(rtlpriv, 0x11a, 0x00);
 674         rtl_write_byte(rtlpriv, 0x11b, 0x00);
 675
 676         for (i = 0; i < 32; i++)
 677                 rtl_write_byte(rtlpriv, INIMCS_SEL + i, 0x1b);
 678
 679         rtl_write_byte(rtlpriv, 0x236, 0xff);
 680
 681         rtl_write_byte(rtlpriv, 0x503, 0x22);
 682
 683         if (ppsc->support_aspm && !ppsc->support_backdoor)
 684                 rtl_write_byte(rtlpriv, 0x560, 0x40);
 685         else
 686                 rtl_write_byte(rtlpriv, 0x560, 0x00);
 687
 688         rtl_write_byte(rtlpriv, DBG_PORT, 0x91);
 689
 690         /* Set RX Desc Address */
 691         rtl_write_dword(rtlpriv, RDQDA, rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
 692         rtl_write_dword(rtlpriv, RCDA, rtlpci->rx_ring[RX_CMD_QUEUE].dma);
 693
 694         /* Set TX Desc Address */
 695         rtl_write_dword(rtlpriv, TBKDA, rtlpci->tx_ring[BK_QUEUE].dma);
 696         rtl_write_dword(rtlpriv, TBEDA, rtlpci->tx_ring[BE_QUEUE].dma);
 697         rtl_write_dword(rtlpriv, TVIDA, rtlpci->tx_ring[VI_QUEUE].dma);
 698         rtl_write_dword(rtlpriv, TVODA, rtlpci->tx_ring[VO_QUEUE].dma);
 699         rtl_write_dword(rtlpriv, TBDA, rtlpci->tx_ring[BEACON_QUEUE].dma);
 700         rtl_write_dword(rtlpriv, TCDA, rtlpci->tx_ring[TXCMD_QUEUE].dma);
 701         rtl_write_dword(rtlpriv, TMDA, rtlpci->tx_ring[MGNT_QUEUE].dma);
 702         rtl_write_dword(rtlpriv, THPDA, rtlpci->tx_ring[HIGH_QUEUE].dma);
 703         rtl_write_dword(rtlpriv, HDA, rtlpci->tx_ring[HCCA_QUEUE].dma);
 704
 705         rtl_write_word(rtlpriv, CMDR, 0x37FC);
 706
 707         /* To make sure that TxDMA can ready to download FW. */
 708         /* We should reset TxDMA if IMEM RPT was not ready. */
 709         do {
 710                 tmpu1b = rtl_read_byte(rtlpriv, TCR);
 711                 if ((tmpu1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE)
 712                         break;
 713
 714                 udelay(5);
 715         } while (pollingcnt--);
 716
 717         if (pollingcnt <= 0) {
 718                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 719                          "Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n",
 720                          tmpu1b);
 721                 tmpu1b = rtl_read_byte(rtlpriv, CMDR);
 722                 rtl_write_byte(rtlpriv, CMDR, tmpu1b & (~TXDMA_EN));
 723                 udelay(2);
 724                 /* Reset TxDMA */
 725                 rtl_write_byte(rtlpriv, CMDR, tmpu1b | TXDMA_EN);
 726         }
 727
 728         /* After MACIO reset,we must refresh LED state. */
 729         if ((ppsc->rfoff_reason == RF_CHANGE_BY_IPS) ||
 730            (ppsc->rfoff_reason == 0)) {
 731                 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 732                 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 733                 enum rf_pwrstate rfpwr_state_toset;
 734                 rfpwr_state_toset = _rtl92se_rf_onoff_detect(hw);
 735
 736                 if (rfpwr_state_toset == ERFON)
 737                         rtl92se_sw_led_on(hw, pLed0);
 738         }
 739 }
 740
 741 static void _rtl92se_macconfig_after_fwdownload(struct ieee80211_hw *hw)
 742 {
 743         struct rtl_priv *rtlpriv = rtl_priv(hw);
 744         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 745         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 746         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 747         u8 i;
 748         u16 tmpu2b;
 749
 750         /* 1. System Configure Register (Offset: 0x0000 - 0x003F) */
 751
 752         /* 2. Command Control Register (Offset: 0x0040 - 0x004F) */
 753         /* Turn on 0x40 Command register */
 754         rtl_write_word(rtlpriv, CMDR, (BBRSTN | BB_GLB_RSTN |
 755                         SCHEDULE_EN | MACRXEN | MACTXEN | DDMA_EN | FW2HW_EN |
 756                         RXDMA_EN | TXDMA_EN | HCI_RXDMA_EN | HCI_TXDMA_EN));
 757
 758         /* Set TCR TX DMA pre 2 FULL enable bit */
 759         rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) |
 760                         TXDMAPRE2FULL);
 761
 762         /* Set RCR      */
 763         rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
 764
 765         /* 3. MACID Setting Register (Offset: 0x0050 - 0x007F) */
 766
 767         /* 4. Timing Control Register  (Offset: 0x0080 - 0x009F) */
 768         /* Set CCK/OFDM SIFS */
 769         /* CCK SIFS shall always be 10us. */
 770         rtl_write_word(rtlpriv, SIFS_CCK, 0x0a0a);
 771         rtl_write_word(rtlpriv, SIFS_OFDM, 0x1010);
 772
 773         /* Set AckTimeout */
 774         rtl_write_byte(rtlpriv, ACK_TIMEOUT, 0x40);
 775
 776         /* Beacon related */
 777         rtl_write_word(rtlpriv, BCN_INTERVAL, 100);
 778         rtl_write_word(rtlpriv, ATIMWND, 2);
 779
 780         /* 5. FIFO Control Register (Offset: 0x00A0 - 0x015F) */
 781         /* 5.1 Initialize Number of Reserved Pages in Firmware Queue */
 782         /* Firmware allocate now, associate with FW internal setting.!!! */
 783
 784         /* 5.2 Setting TX/RX page size 0/1/2/3/4=64/128/256/512/1024 */
 785         /* 5.3 Set driver info, we only accept PHY status now. */
 786         /* 5.4 Set RXDMA arbitration to control RXDMA/MAC/FW R/W for RXFIFO  */
 787         rtl_write_byte(rtlpriv, RXDMA, rtl_read_byte(rtlpriv, RXDMA) | BIT(6));
 788
 789         /* 6. Adaptive Control Register  (Offset: 0x0160 - 0x01CF) */
 790         /* Set RRSR to all legacy rate and HT rate
 791          * CCK rate is supported by default.
 792          * CCK rate will be filtered out only when associated
 793          * AP does not support it.
 794          * Only enable ACK rate to OFDM 24M
 795          * Disable RRSR for CCK rate in A-Cut   */
 796
 797         if (rtlhal->version == VERSION_8192S_ACUT)
 798                 rtl_write_byte(rtlpriv, RRSR, 0xf0);
 799         else if (rtlhal->version == VERSION_8192S_BCUT)
 800                 rtl_write_byte(rtlpriv, RRSR, 0xff);
 801         rtl_write_byte(rtlpriv, RRSR + 1, 0x01);
 802         rtl_write_byte(rtlpriv, RRSR + 2, 0x00);
 803
 804         /* A-Cut IC do not support CCK rate. We forbid ARFR to */
 805         /* fallback to CCK rate */
 806         for (i = 0; i < 8; i++) {
 807                 /*Disable RRSR for CCK rate in A-Cut */
 808                 if (rtlhal->version == VERSION_8192S_ACUT)
 809                         rtl_write_dword(rtlpriv, ARFR0 + i * 4, 0x1f0ff0f0);
 810         }
 811
 812         /* Different rate use different AMPDU size */
 813         /* MCS32/ MCS15_SG use max AMPDU size 15*2=30K */
 814         rtl_write_byte(rtlpriv, AGGLEN_LMT_H, 0x0f);
 815         /* MCS0/1/2/3 use max AMPDU size 4*2=8K */
 816         rtl_write_word(rtlpriv, AGGLEN_LMT_L, 0x7442);
 817         /* MCS4/5 use max AMPDU size 8*2=16K 6/7 use 10*2=20K */
 818         rtl_write_word(rtlpriv, AGGLEN_LMT_L + 2, 0xddd7);
 819         /* MCS8/9 use max AMPDU size 8*2=16K 10/11 use 10*2=20K */
 820         rtl_write_word(rtlpriv, AGGLEN_LMT_L + 4, 0xd772);
 821         /* MCS12/13/14/15 use max AMPDU size 15*2=30K */
 822         rtl_write_word(rtlpriv, AGGLEN_LMT_L + 6, 0xfffd);
 823
 824         /* Set Data / Response auto rate fallack retry count */
 825         rtl_write_dword(rtlpriv, DARFRC, 0x04010000);
 826         rtl_write_dword(rtlpriv, DARFRC + 4, 0x09070605);
 827         rtl_write_dword(rtlpriv, RARFRC, 0x04010000);
 828         rtl_write_dword(rtlpriv, RARFRC + 4, 0x09070605);
 829
 830         /* 7. EDCA Setting Register (Offset: 0x01D0 - 0x01FF) */
 831         /* Set all rate to support SG */
 832         rtl_write_word(rtlpriv, SG_RATE, 0xFFFF);
 833
 834         /* 8. WMAC, BA, and CCX related Register (Offset: 0x0200 - 0x023F) */
 835         /* Set NAV protection length */
 836         rtl_write_word(rtlpriv, NAV_PROT_LEN, 0x0080);
 837         /* CF-END Threshold */
 838         rtl_write_byte(rtlpriv, CFEND_TH, 0xFF);
 839         /* Set AMPDU minimum space */
 840         rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 0x07);
 841         /* Set TXOP stall control for several queue/HI/BCN/MGT/ */
 842         rtl_write_byte(rtlpriv, TXOP_STALL_CTRL, 0x00);
 843
 844         /* 9. Security Control Register (Offset: 0x0240 - 0x025F) */
 845         /* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */
 846         /* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */
 847         /* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */
 848         /* 13. Test Mode and Debug Control Register (Offset: 0x0310 - 0x034F) */
 849
 850         /* 14. Set driver info, we only accept PHY status now. */
 851         rtl_write_byte(rtlpriv, RXDRVINFO_SZ, 4);
 852
 853         /* 15. For EEPROM R/W Workaround */
 854         /* 16. For EFUSE to share REG_SYS_FUNC_EN with EEPROM!!! */
 855         tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
 856         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmpu2b | BIT(13));
 857         tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
 858         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, tmpu2b & (~BIT(8)));
 859
 860         /* 17. For EFUSE */
 861         /* We may R/W EFUSE in EEPROM mode */
 862         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
 863                 u8      tempval;
 864
 865                 tempval = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL + 1);
 866                 tempval &= 0xFE;
 867                 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, tempval);
 868
 869                 /* Change Program timing */
 870                 rtl_write_byte(rtlpriv, REG_EFUSE_CTRL + 3, 0x72);
 871                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "EFUSE CONFIG OK\n");
 872         }
 873
 874         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n");
 875
 876 }
 877
 878 static void _rtl92se_hw_configure(struct ieee80211_hw *hw)
 879 {
 880         struct rtl_priv *rtlpriv = rtl_priv(hw);
 881         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 882         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 883         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 884
 885         u8 reg_bw_opmode = 0;
 886         u32 reg_rrsr = 0;
 887         u8 regtmp = 0;
 888
 889         reg_bw_opmode = BW_OPMODE_20MHZ;
 890         reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 891
 892         regtmp = rtl_read_byte(rtlpriv, INIRTSMCS_SEL);
 893         reg_rrsr = ((reg_rrsr & 0x000fffff) << 8) | regtmp;
 894         rtl_write_dword(rtlpriv, INIRTSMCS_SEL, reg_rrsr);
 895         rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
 896
 897         /* Set Retry Limit here */
 898         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
 899                         (u8 *)(&rtlpci->shortretry_limit));
 900
 901         rtl_write_byte(rtlpriv, MLT, 0x8f);
 902
 903         /* For Min Spacing configuration. */
 904         switch (rtlphy->rf_type) {
 905         case RF_1T2R:
 906         case RF_1T1R:
 907                 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
 908                 break;
 909         case RF_2T2R:
 910         case RF_2T2R_GREEN:
 911                 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
 912                 break;
 913         }
 914         rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, rtlhal->minspace_cfg);
 915 }
 916
 917 int rtl92se_hw_init(struct ieee80211_hw *hw)
 918 {
 919         struct rtl_priv *rtlpriv = rtl_priv(hw);
 920         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 921         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 922         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 923         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 924         u8 tmp_byte = 0;
 925
 926         bool rtstatus = true;
 927         u8 tmp_u1b;
 928         int err = false;
 929         u8 i;
 930         int wdcapra_add[] = {
 931                 EDCAPARA_BE, EDCAPARA_BK,
 932                 EDCAPARA_VI, EDCAPARA_VO};
 933         u8 secr_value = 0x0;
 934
 935         rtlpci->being_init_adapter = true;
 936
 937         rtlpriv->intf_ops->disable_aspm(hw);
 938
 939         /* 1. MAC Initialize */
 940         /* Before FW download, we have to set some MAC register */
 941         _rtl92se_macconfig_before_fwdownload(hw);
 942
 943         rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv,
 944                         PMC_FSM) >> 16) & 0xF);
 945
 946         rtl8192se_gpiobit3_cfg_inputmode(hw);
 947
 948         /* 2. download firmware */
 949         rtstatus = rtl92s_download_fw(hw);
 950         if (!rtstatus) {
 951                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 952                          "Failed to download FW. Init HW without FW now... "
 953                          "Please copy FW into /lib/firmware/rtlwifi\n");
 954                 return 1;
 955         }
 956
 957         /* After FW download, we have to reset MAC register */
 958         _rtl92se_macconfig_after_fwdownload(hw);
 959
 960         /*Retrieve default FW Cmd IO map. */
 961         rtlhal->fwcmd_iomap =   rtl_read_word(rtlpriv, LBUS_MON_ADDR);
 962         rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, LBUS_ADDR_MASK);
 963
 964         /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */
 965         if (rtl92s_phy_mac_config(hw) != true) {
 966                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "MAC Config failed\n");
 967                 return rtstatus;
 968         }
 969
 970         /* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */
 971         /* We must set flag avoid BB/RF config period later!! */
 972         rtl_write_dword(rtlpriv, CMDR, 0x37FC);
 973
 974         /* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */
 975         if (rtl92s_phy_bb_config(hw) != true) {
 976                 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "BB Config failed\n");
 977                 return rtstatus;
 978         }
 979
 980         /* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */
 981         /* Before initalizing RF. We can not use FW to do RF-R/W. */
 982
 983         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
 984
 985         /* RF Power Save */
 986 #if 0
 987         /* H/W or S/W RF OFF before sleep. */
 988         if (rtlpriv->psc.rfoff_reason > RF_CHANGE_BY_PS) {
 989                 u32 rfoffreason = rtlpriv->psc.rfoff_reason;
 990
 991                 rtlpriv->psc.rfoff_reason = RF_CHANGE_BY_INIT;
 992                 rtlpriv->psc.rfpwr_state = ERFON;
 993                 /* FIXME: check spinlocks if this block is uncommented */
 994                 rtl_ps_set_rf_state(hw, ERFOFF, rfoffreason);
 995         } else {
 996                 /* gpio radio on/off is out of adapter start */
 997                 if (rtlpriv->psc.hwradiooff == false) {
 998                         rtlpriv->psc.rfpwr_state = ERFON;
 999                         rtlpriv->psc.rfoff_reason = 0;
1000                 }
1001         }
1002 #endif
1003
1004         /* Before RF-R/W we must execute the IO from Scott's suggestion. */
1005         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, 0xDB);
1006         if (rtlhal->version == VERSION_8192S_ACUT)
1007                 rtl_write_byte(rtlpriv, SPS1_CTRL + 3, 0x07);
1008         else
1009                 rtl_write_byte(rtlpriv, RF_CTRL, 0x07);
1010
1011         if (rtl92s_phy_rf_config(hw) != true) {
1012                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RF Config failed\n");
1013                 return rtstatus;
1014         }
1015
1016         /* After read predefined TXT, we must set BB/MAC/RF
1017          * register as our requirement */
1018
1019         rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw,
1020                                                            (enum radio_path)0,
1021                                                            RF_CHNLBW,
1022                                                            RFREG_OFFSET_MASK);
1023         rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw,
1024                                                            (enum radio_path)1,
1025                                                            RF_CHNLBW,
1026                                                            RFREG_OFFSET_MASK);
1027
1028         /*---- Set CCK and OFDM Block "ON"----*/
1029         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1030         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1031
1032         /*3 Set Hardware(Do nothing now) */
1033         _rtl92se_hw_configure(hw);
1034
1035         /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1036         /* TX power index for different rate set. */
1037         /* Get original hw reg values */
1038         rtl92s_phy_get_hw_reg_originalvalue(hw);
1039         /* Write correct tx power index */
1040         rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1041
1042         /* We must set MAC address after firmware download. */
1043         for (i = 0; i < 6; i++)
1044                 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1045
1046         /* EEPROM R/W workaround */
1047         tmp_u1b = rtl_read_byte(rtlpriv, MAC_PINMUX_CFG);
1048         rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, tmp_u1b & (~BIT(3)));
1049
1050         rtl_write_byte(rtlpriv, 0x4d, 0x0);
1051
1052         if (hal_get_firmwareversion(rtlpriv) >= 0x49) {
1053                 tmp_byte = rtl_read_byte(rtlpriv, FW_RSVD_PG_CRTL) & (~BIT(4));
1054                 tmp_byte = tmp_byte | BIT(5);
1055                 rtl_write_byte(rtlpriv, FW_RSVD_PG_CRTL, tmp_byte);
1056                 rtl_write_dword(rtlpriv, TXDESC_MSK, 0xFFFFCFFF);
1057         }
1058
1059         /* We enable high power and RA related mechanism after NIC
1060          * initialized. */
1061         rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT);
1062
1063         /* Add to prevent ASPM bug. */
1064         /* Always enable hst and NIC clock request. */
1065         rtl92s_phy_switch_ephy_parameter(hw);
1066
1067         /* Security related
1068          * 1. Clear all H/W keys.
1069          * 2. Enable H/W encryption/decryption. */
1070         rtl_cam_reset_all_entry(hw);
1071         secr_value |= SCR_TXENCENABLE;
1072         secr_value |= SCR_RXENCENABLE;
1073         secr_value |= SCR_NOSKMC;
1074         rtl_write_byte(rtlpriv, REG_SECR, secr_value);
1075
1076         for (i = 0; i < 4; i++)
1077                 rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322);
1078
1079         if (rtlphy->rf_type == RF_1T2R) {
1080                 bool mrc2set = true;
1081                 /* Turn on B-Path */
1082                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set);
1083         }
1084
1085         rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON);
1086         rtl92s_dm_init(hw);
1087         rtlpci->being_init_adapter = false;
1088
1089         return err;
1090 }
1091
1092 void rtl92se_set_mac_addr(struct rtl_io *io, const u8 * addr)
1093 {
1094 }
1095
1096 void rtl92se_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1097 {
1098         struct rtl_priv *rtlpriv = rtl_priv(hw);
1099         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1100         u32 reg_rcr = rtlpci->receive_config;
1101
1102         if (rtlpriv->psc.rfpwr_state != ERFON)
1103                 return;
1104
1105         if (check_bssid) {
1106                 reg_rcr |= (RCR_CBSSID);
1107                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1108         } else if (check_bssid == false) {
1109                 reg_rcr &= (~RCR_CBSSID);
1110                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1111         }
1112
1113 }
1114
1115 static int _rtl92se_set_media_status(struct ieee80211_hw *hw,
1116                                      enum nl80211_iftype type)
1117 {
1118         struct rtl_priv *rtlpriv = rtl_priv(hw);
1119         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1120         u32 temp;
1121         bt_msr &= ~MSR_LINK_MASK;
1122
1123         switch (type) {
1124         case NL80211_IFTYPE_UNSPECIFIED:
1125                 bt_msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
1126                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1127                          "Set Network type to NO LINK!\n");
1128                 break;
1129         case NL80211_IFTYPE_ADHOC:
1130                 bt_msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
1131                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1132                          "Set Network type to Ad Hoc!\n");
1133                 break;
1134         case NL80211_IFTYPE_STATION:
1135                 bt_msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
1136                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1137                          "Set Network type to STA!\n");
1138                 break;
1139         case NL80211_IFTYPE_AP:
1140                 bt_msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
1141                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1142                          "Set Network type to AP!\n");
1143                 break;
1144         default:
1145                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1146                          "Network type %d not supported!\n", type);
1147                 return 1;
1148                 break;
1149
1150         }
1151
1152         rtl_write_byte(rtlpriv, (MSR), bt_msr);
1153
1154         temp = rtl_read_dword(rtlpriv, TCR);
1155         rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8)));
1156         rtl_write_dword(rtlpriv, TCR, temp | BIT(8));
1157
1158
1159         return 0;
1160 }
1161
1162 /* HW_VAR_MEDIA_STATUS & HW_VAR_CECHK_BSSID */
1163 int rtl92se_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1164 {
1165         struct rtl_priv *rtlpriv = rtl_priv(hw);
1166
1167         if (_rtl92se_set_media_status(hw, type))
1168                 return -EOPNOTSUPP;
1169
1170         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1171                 if (type != NL80211_IFTYPE_AP)
1172                         rtl92se_set_check_bssid(hw, true);
1173         } else {
1174                 rtl92se_set_check_bssid(hw, false);
1175         }
1176
1177         return 0;
1178 }
1179
1180 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1181 void rtl92se_set_qos(struct ieee80211_hw *hw, int aci)
1182 {
1183         struct rtl_priv *rtlpriv = rtl_priv(hw);
1184         rtl92s_dm_init_edca_turbo(hw);
1185
1186         switch (aci) {
1187         case AC1_BK:
1188                 rtl_write_dword(rtlpriv, EDCAPARA_BK, 0xa44f);
1189                 break;
1190         case AC0_BE:
1191                 /* rtl_write_dword(rtlpriv, EDCAPARA_BE, u4b_ac_param); */
1192                 break;
1193         case AC2_VI:
1194                 rtl_write_dword(rtlpriv, EDCAPARA_VI, 0x5e4322);
1195                 break;
1196         case AC3_VO:
1197                 rtl_write_dword(rtlpriv, EDCAPARA_VO, 0x2f3222);
1198                 break;
1199         default:
1200                 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1201                 break;
1202         }
1203 }
1204
1205 void rtl92se_enable_interrupt(struct ieee80211_hw *hw)
1206 {
1207         struct rtl_priv *rtlpriv = rtl_priv(hw);
1208         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1209
1210         rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]);
1211         /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */
1212         rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F);
1213 }
1214
1215 void rtl92se_disable_interrupt(struct ieee80211_hw *hw)
1216 {
1217         struct rtl_priv *rtlpriv;
1218         struct rtl_pci *rtlpci;
1219
1220         rtlpriv = rtl_priv(hw);
1221         /* if firmware not available, no interrupts */
1222         if (!rtlpriv || !rtlpriv->max_fw_size)
1223                 return;
1224         rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1225         rtl_write_dword(rtlpriv, INTA_MASK, 0);
1226         rtl_write_dword(rtlpriv, INTA_MASK + 4, 0);
1227
1228         synchronize_irq(rtlpci->pdev->irq);
1229 }
1230
1231
1232 static u8 _rtl92s_set_sysclk(struct ieee80211_hw *hw, u8 data)
1233 {
1234         struct rtl_priv *rtlpriv = rtl_priv(hw);
1235         u8 waitcnt = 100;
1236         bool result = false;
1237         u8 tmp;
1238
1239         rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
1240
1241         /* Wait the MAC synchronized. */
1242         udelay(400);
1243
1244         /* Check if it is set ready. */
1245         tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1246         result = ((tmp & BIT(7)) == (data & BIT(7)));
1247
1248         if ((data & (BIT(6) | BIT(7))) == false) {
1249                 waitcnt = 100;
1250                 tmp = 0;
1251
1252                 while (1) {
1253                         waitcnt--;
1254                         tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1255
1256                         if ((tmp & BIT(6)))
1257                                 break;
1258
1259                         pr_err("wait for BIT(6) return value %x\n", tmp);
1260
1261                         if (waitcnt == 0)
1262                                 break;
1263                         udelay(10);
1264                 }
1265
1266                 if (waitcnt == 0)
1267                         result = false;
1268                 else
1269                         result = true;
1270         }
1271
1272         return result;
1273 }
1274
1275 static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw)
1276 {
1277         struct rtl_priv *rtlpriv = rtl_priv(hw);
1278         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1279         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1280         u8 u1btmp;
1281
1282         if (rtlhal->driver_going2unload)
1283                 rtl_write_byte(rtlpriv, 0x560, 0x0);
1284
1285         /* Power save for BB/RF */
1286         u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
1287         u1btmp |= BIT(0);
1288         rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
1289         rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
1290         rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
1291         rtl_write_word(rtlpriv, CMDR, 0x57FC);
1292         udelay(100);
1293         rtl_write_word(rtlpriv, CMDR, 0x77FC);
1294         rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
1295         udelay(10);
1296         rtl_write_word(rtlpriv, CMDR, 0x37FC);
1297         udelay(10);
1298         rtl_write_word(rtlpriv, CMDR, 0x77FC);
1299         udelay(10);
1300         rtl_write_word(rtlpriv, CMDR, 0x57FC);
1301         rtl_write_word(rtlpriv, CMDR, 0x0000);
1302
1303         if (rtlhal->driver_going2unload) {
1304                 u1btmp = rtl_read_byte(rtlpriv, (REG_SYS_FUNC_EN + 1));
1305                 u1btmp &= ~(BIT(0));
1306                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1btmp);
1307         }
1308
1309         u1btmp = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1310
1311         /* Add description. After switch control path. register
1312          * after page1 will be invisible. We can not do any IO
1313          * for register>0x40. After resume&MACIO reset, we need
1314          * to remember previous reg content. */
1315         if (u1btmp & BIT(7)) {
1316                 u1btmp &= ~(BIT(6) | BIT(7));
1317                 if (!_rtl92s_set_sysclk(hw, u1btmp)) {
1318                         pr_err("Switch ctrl path fail\n");
1319                         return;
1320                 }
1321         }
1322
1323         /* Power save for MAC */
1324         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS  &&
1325                 !rtlhal->driver_going2unload) {
1326                 /* enable LED function */
1327                 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1328         /* SW/HW radio off or halt adapter!! For example S3/S4 */
1329         } else {
1330                 /* LED function disable. Power range is about 8mA now. */
1331                 /* if write 0xF1 disconnet_pci power
1332                  *       ifconfig wlan0 down power are both high 35:70 */
1333                 /* if write oxF9 disconnet_pci power
1334                  * ifconfig wlan0 down power are both low  12:45*/
1335                 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1336         }
1337
1338         rtl_write_byte(rtlpriv, SYS_CLKR + 1, 0x70);
1339         rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, 0x68);
1340         rtl_write_byte(rtlpriv,  AFE_PLL_CTRL, 0x00);
1341         rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1342         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, 0x0E);
1343         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1344
1345 }
1346
1347 static void _rtl92se_gen_refreshledstate(struct ieee80211_hw *hw)
1348 {
1349         struct rtl_priv *rtlpriv = rtl_priv(hw);
1350         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1351         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1352         struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
1353
1354         if (rtlpci->up_first_time == 1)
1355                 return;
1356
1357         if (rtlpriv->psc.rfoff_reason == RF_CHANGE_BY_IPS)
1358                 rtl92se_sw_led_on(hw, pLed0);
1359         else
1360                 rtl92se_sw_led_off(hw, pLed0);
1361 }
1362
1363
1364 static void _rtl92se_power_domain_init(struct ieee80211_hw *hw)
1365 {
1366         struct rtl_priv *rtlpriv = rtl_priv(hw);
1367         u16 tmpu2b;
1368         u8 tmpu1b;
1369
1370         rtlpriv->psc.pwrdomain_protect = true;
1371
1372         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1373         if (tmpu1b & BIT(7)) {
1374                 tmpu1b &= ~(BIT(6) | BIT(7));
1375                 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1376                         rtlpriv->psc.pwrdomain_protect = false;
1377                         return;
1378                 }
1379         }
1380
1381         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
1382         rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1383
1384         /* Reset MAC-IO and CPU and Core Digital BIT10/11/15 */
1385         tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1386
1387         /* If IPS we need to turn LED on. So we not
1388          * not disable BIT 3/7 of reg3. */
1389         if (rtlpriv->psc.rfoff_reason & (RF_CHANGE_BY_IPS | RF_CHANGE_BY_HW))
1390                 tmpu1b &= 0xFB;
1391         else
1392                 tmpu1b &= 0x73;
1393
1394         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
1395         /* wait for BIT 10/11/15 to pull high automatically!! */
1396         mdelay(1);
1397
1398         rtl_write_byte(rtlpriv, CMDR, 0);
1399         rtl_write_byte(rtlpriv, TCR, 0);
1400
1401         /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
1402         tmpu1b = rtl_read_byte(rtlpriv, 0x562);
1403         tmpu1b |= 0x08;
1404         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1405         tmpu1b &= ~(BIT(3));
1406         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1407
1408         /* Enable AFE clock source */
1409         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
1410         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
1411         /* Delay 1.5ms */
1412         udelay(1500);
1413         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
1414         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
1415
1416         /* Enable AFE Macro Block's Bandgap */
1417         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1418         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
1419         mdelay(1);
1420
1421         /* Enable AFE Mbias */
1422         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1423         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
1424         mdelay(1);
1425
1426         /* Enable LDOA15 block */
1427         tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
1428         rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
1429
1430         /* Set Digital Vdd to Retention isolation Path. */
1431         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
1432         rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
1433
1434
1435         /* For warm reboot NIC disappera bug. */
1436         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1437         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
1438
1439         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
1440
1441         /* Enable AFE PLL Macro Block */
1442         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
1443         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
1444         /* Enable MAC 80MHZ clock */
1445         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
1446         rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
1447         mdelay(1);
1448
1449         /* Release isolation AFE PLL & MD */
1450         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
1451
1452         /* Enable MAC clock */
1453         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1454         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
1455
1456         /* Enable Core digital and enable IOREG R/W */
1457         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1458         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
1459         /* enable REG_EN */
1460         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
1461
1462         /* Switch the control path. */
1463         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1464         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
1465
1466         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1467         tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
1468         if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1469                 rtlpriv->psc.pwrdomain_protect = false;
1470                 return;
1471         }
1472
1473         rtl_write_word(rtlpriv, CMDR, 0x37FC);
1474
1475         /* After MACIO reset,we must refresh LED state. */
1476         _rtl92se_gen_refreshledstate(hw);
1477
1478         rtlpriv->psc.pwrdomain_protect = false;
1479 }
1480
1481 void rtl92se_card_disable(struct ieee80211_hw *hw)
1482 {
1483         struct rtl_priv *rtlpriv = rtl_priv(hw);
1484         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1485         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1486         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1487         enum nl80211_iftype opmode;
1488         u8 wait = 30;
1489
1490         rtlpriv->intf_ops->enable_aspm(hw);
1491
1492         if (rtlpci->driver_is_goingto_unload ||
1493                 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1494                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1495
1496         /* we should chnge GPIO to input mode
1497          * this will drop away current about 25mA*/
1498         rtl8192se_gpiobit3_cfg_inputmode(hw);
1499
1500         /* this is very important for ips power save */
1501         while (wait-- >= 10 && rtlpriv->psc.pwrdomain_protect) {
1502                 if (rtlpriv->psc.pwrdomain_protect)
1503                         mdelay(20);
1504                 else
1505                         break;
1506         }
1507
1508         mac->link_state = MAC80211_NOLINK;
1509         opmode = NL80211_IFTYPE_UNSPECIFIED;
1510         _rtl92se_set_media_status(hw, opmode);
1511
1512         _rtl92s_phy_set_rfhalt(hw);
1513         udelay(100);
1514 }
1515
1516 void rtl92se_interrupt_recognized(struct ieee80211_hw *hw, u32 *p_inta,
1517                              u32 *p_intb)
1518 {
1519         struct rtl_priv *rtlpriv = rtl_priv(hw);
1520         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1521
1522         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1523         rtl_write_dword(rtlpriv, ISR, *p_inta);
1524
1525         *p_intb = rtl_read_dword(rtlpriv, ISR + 4) & rtlpci->irq_mask[1];
1526         rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1527 }
1528
1529 void rtl92se_set_beacon_related_registers(struct ieee80211_hw *hw)
1530 {
1531         struct rtl_priv *rtlpriv = rtl_priv(hw);
1532         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1533         u16 bcntime_cfg = 0;
1534         u16 bcn_cw = 6, bcn_ifs = 0xf;
1535         u16 atim_window = 2;
1536
1537         /* ATIM Window (in unit of TU). */
1538         rtl_write_word(rtlpriv, ATIMWND, atim_window);
1539
1540         /* Beacon interval (in unit of TU). */
1541         rtl_write_word(rtlpriv, BCN_INTERVAL, mac->beacon_interval);
1542
1543         /* DrvErlyInt (in unit of TU). (Time to send
1544          * interrupt to notify driver to change
1545          * beacon content) */
1546         rtl_write_word(rtlpriv, BCN_DRV_EARLY_INT, 10 << 4);
1547
1548         /* BcnDMATIM(in unit of us). Indicates the
1549          * time before TBTT to perform beacon queue DMA  */
1550         rtl_write_word(rtlpriv, BCN_DMATIME, 256);
1551
1552         /* Force beacon frame transmission even
1553          * after receiving beacon frame from
1554          * other ad hoc STA */
1555         rtl_write_byte(rtlpriv, BCN_ERR_THRESH, 100);
1556
1557         /* Beacon Time Configuration */
1558         if (mac->opmode == NL80211_IFTYPE_ADHOC)
1559                 bcntime_cfg |= (bcn_cw << BCN_TCFG_CW_SHIFT);
1560
1561         /* TODO: bcn_ifs may required to be changed on ASIC */
1562         bcntime_cfg |= bcn_ifs << BCN_TCFG_IFS;
1563
1564         /*for beacon changed */
1565         rtl92s_phy_set_beacon_hwreg(hw, mac->beacon_interval);
1566 }
1567
1568 void rtl92se_set_beacon_interval(struct ieee80211_hw *hw)
1569 {
1570         struct rtl_priv *rtlpriv = rtl_priv(hw);
1571         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1572         u16 bcn_interval = mac->beacon_interval;
1573
1574         /* Beacon interval (in unit of TU). */
1575         rtl_write_word(rtlpriv, BCN_INTERVAL, bcn_interval);
1576         /* 2008.10.24 added by tynli for beacon changed. */
1577         rtl92s_phy_set_beacon_hwreg(hw, bcn_interval);
1578 }
1579
1580 void rtl92se_update_interrupt_mask(struct ieee80211_hw *hw,
1581                 u32 add_msr, u32 rm_msr)
1582 {
1583         struct rtl_priv *rtlpriv = rtl_priv(hw);
1584         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1585
1586         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1587                  add_msr, rm_msr);
1588
1589         if (add_msr)
1590                 rtlpci->irq_mask[0] |= add_msr;
1591
1592         if (rm_msr)
1593                 rtlpci->irq_mask[0] &= (~rm_msr);
1594
1595         rtl92se_disable_interrupt(hw);
1596         rtl92se_enable_interrupt(hw);
1597 }
1598
1599 static void _rtl8192se_get_IC_Inferiority(struct ieee80211_hw *hw)
1600 {
1601         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1602         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1603         u8 efuse_id;
1604
1605         rtlhal->ic_class = IC_INFERIORITY_A;
1606
1607         /* Only retrieving while using EFUSE. */
1608         if ((rtlefuse->epromtype == EEPROM_BOOT_EFUSE) &&
1609                 !rtlefuse->autoload_failflag) {
1610                 efuse_id = efuse_read_1byte(hw, EFUSE_IC_ID_OFFSET);
1611
1612                 if (efuse_id == 0xfe)
1613                         rtlhal->ic_class = IC_INFERIORITY_B;
1614         }
1615 }
1616
1617 static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1618 {
1619         struct rtl_priv *rtlpriv = rtl_priv(hw);
1620         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1621         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1622         u16 i, usvalue;
1623         u16     eeprom_id;
1624         u8 tempval;
1625         u8 hwinfo[HWSET_MAX_SIZE_92S];
1626         u8 rf_path, index;
1627
1628         if (rtlefuse->epromtype == EEPROM_93C46) {
1629                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1630                          "RTL819X Not boot from eeprom, check it !!\n");
1631         } else if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1632                 rtl_efuse_shadow_map_update(hw);
1633
1634                 memcpy((void *)hwinfo, (void *)
1635                         &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1636                         HWSET_MAX_SIZE_92S);
1637         }
1638
1639         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP",
1640                       hwinfo, HWSET_MAX_SIZE_92S);
1641
1642         eeprom_id = *((u16 *)&hwinfo[0]);
1643         if (eeprom_id != RTL8190_EEPROM_ID) {
1644                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1645                          "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1646                 rtlefuse->autoload_failflag = true;
1647         } else {
1648                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1649                 rtlefuse->autoload_failflag = false;
1650         }
1651
1652         if (rtlefuse->autoload_failflag)
1653                 return;
1654
1655         _rtl8192se_get_IC_Inferiority(hw);
1656
1657         /* Read IC Version && Channel Plan */
1658         /* VID, DID      SE     0xA-D */
1659         rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1660         rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1661         rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1662         rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1663         rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1664
1665         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1666                  "EEPROMId = 0x%4x\n", eeprom_id);
1667         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1668                  "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1669         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1670                  "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1671         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1672                  "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1673         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1674                  "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1675
1676         for (i = 0; i < 6; i += 2) {
1677                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1678                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1679         }
1680
1681         for (i = 0; i < 6; i++)
1682                 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1683
1684         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1685
1686         /* Get Tx Power Level by Channel */
1687         /* Read Tx power of Channel 1 ~ 14 from EEPROM. */
1688         /* 92S suupport RF A & B */
1689         for (rf_path = 0; rf_path < 2; rf_path++) {
1690                 for (i = 0; i < 3; i++) {
1691                         /* Read CCK RF A & B Tx power  */
1692                         rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1693                         hwinfo[EEPROM_TXPOWERBASE + rf_path * 3 + i];
1694
1695                         /* Read OFDM RF A & B Tx power for 1T */
1696                         rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1697                         hwinfo[EEPROM_TXPOWERBASE + 6 + rf_path * 3 + i];
1698
1699                         /* Read OFDM RF A & B Tx power for 2T */
1700                         rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][i]
1701                                  = hwinfo[EEPROM_TXPOWERBASE + 12 +
1702                                    rf_path * 3 + i];
1703                 }
1704         }
1705
1706         for (rf_path = 0; rf_path < 2; rf_path++)
1707                 for (i = 0; i < 3; i++)
1708                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1709                                 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1710                                 rf_path, i,
1711                                 rtlefuse->eeprom_chnlarea_txpwr_cck
1712                                 [rf_path][i]);
1713         for (rf_path = 0; rf_path < 2; rf_path++)
1714                 for (i = 0; i < 3; i++)
1715                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1716                                 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1717                                 rf_path, i,
1718                                 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1719                                 [rf_path][i]);
1720         for (rf_path = 0; rf_path < 2; rf_path++)
1721                 for (i = 0; i < 3; i++)
1722                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1723                                 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1724                                 rf_path, i,
1725                                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif
1726                                 [rf_path][i]);
1727
1728         for (rf_path = 0; rf_path < 2; rf_path++) {
1729
1730                 /* Assign dedicated channel tx power */
1731                 for (i = 0; i < 14; i++)        {
1732                         /* channel 1~3 use the same Tx Power Level. */
1733                         if (i < 3)
1734                                 index = 0;
1735                         /* Channel 4-8 */
1736                         else if (i < 8)
1737                                 index = 1;
1738                         /* Channel 9-14 */
1739                         else
1740                                 index = 2;
1741
1742                         /* Record A & B CCK /OFDM - 1T/2T Channel area
1743                          * tx power */
1744                         rtlefuse->txpwrlevel_cck[rf_path][i]  =
1745                                 rtlefuse->eeprom_chnlarea_txpwr_cck
1746                                                         [rf_path][index];
1747                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i]  =
1748                                 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1749                                                         [rf_path][index];
1750                         rtlefuse->txpwrlevel_ht40_2s[rf_path][i]  =
1751                                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif
1752                                                         [rf_path][index];
1753                 }
1754
1755                 for (i = 0; i < 14; i++) {
1756                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1757                                 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1758                                 rf_path, i,
1759                                 rtlefuse->txpwrlevel_cck[rf_path][i],
1760                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1761                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1762                 }
1763         }
1764
1765         for (rf_path = 0; rf_path < 2; rf_path++) {
1766                 for (i = 0; i < 3; i++) {
1767                         /* Read Power diff limit. */
1768                         rtlefuse->eeprom_pwrgroup[rf_path][i] =
1769                                 hwinfo[EEPROM_TXPWRGROUP + rf_path * 3 + i];
1770                 }
1771         }
1772
1773         for (rf_path = 0; rf_path < 2; rf_path++) {
1774                 /* Fill Pwr group */
1775                 for (i = 0; i < 14; i++) {
1776                         /* Chanel 1-3 */
1777                         if (i < 3)
1778                                 index = 0;
1779                         /* Channel 4-8 */
1780                         else if (i < 8)
1781                                 index = 1;
1782                         /* Channel 9-13 */
1783                         else
1784                                 index = 2;
1785
1786                         rtlefuse->pwrgroup_ht20[rf_path][i] =
1787                                 (rtlefuse->eeprom_pwrgroup[rf_path][index] &
1788                                 0xf);
1789                         rtlefuse->pwrgroup_ht40[rf_path][i] =
1790                                 ((rtlefuse->eeprom_pwrgroup[rf_path][index] &
1791                                 0xf0) >> 4);
1792
1793                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1794                                 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1795                                 rf_path, i,
1796                                 rtlefuse->pwrgroup_ht20[rf_path][i]);
1797                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1798                                 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1799                                 rf_path, i,
1800                                 rtlefuse->pwrgroup_ht40[rf_path][i]);
1801                         }
1802         }
1803
1804         for (i = 0; i < 14; i++) {
1805                 /* Read tx power difference between HT OFDM 20/40 MHZ */
1806                 /* channel 1-3 */
1807                 if (i < 3)
1808                         index = 0;
1809                 /* Channel 4-8 */
1810                 else if (i < 8)
1811                         index = 1;
1812                 /* Channel 9-14 */
1813                 else
1814                         index = 2;
1815
1816                 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_HT20_DIFF +
1817                            index]) & 0xff;
1818                 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1819                 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1820                                                  ((tempval >> 4) & 0xF);
1821
1822                 /* Read OFDM<->HT tx power diff */
1823                 /* Channel 1-3 */
1824                 if (i < 3)
1825                         index = 0;
1826                 /* Channel 4-8 */
1827                 else if (i < 8)
1828                         index = 0x11;
1829                 /* Channel 9-14 */
1830                 else
1831                         index = 1;
1832
1833                 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_OFDM_DIFF + index])
1834                                   & 0xff;
1835                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] =
1836                                  (tempval & 0xF);
1837                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1838                                  ((tempval >> 4) & 0xF);
1839
1840                 tempval = (*(u8 *)&hwinfo[TX_PWR_SAFETY_CHK]);
1841                 rtlefuse->txpwr_safetyflag = (tempval & 0x01);
1842         }
1843
1844         rtlefuse->eeprom_regulatory = 0;
1845         if (rtlefuse->eeprom_version >= 2) {
1846                 /* BIT(0)~2 */
1847                 if (rtlefuse->eeprom_version >= 4)
1848                         rtlefuse->eeprom_regulatory =
1849                                  (hwinfo[EEPROM_REGULATORY] & 0x7);
1850                 else /* BIT(0) */
1851                         rtlefuse->eeprom_regulatory =
1852                                  (hwinfo[EEPROM_REGULATORY] & 0x1);
1853         }
1854         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1855                 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1856
1857         for (i = 0; i < 14; i++)
1858                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1859                         "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1860                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1861         for (i = 0; i < 14; i++)
1862                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1863                         "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1864                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1865         for (i = 0; i < 14; i++)
1866                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1867                         "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1868                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1869         for (i = 0; i < 14; i++)
1870                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1871                         "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1872                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1873
1874         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1875                 "TxPwrSafetyFlag = %d\n", rtlefuse->txpwr_safetyflag);
1876
1877         /* Read RF-indication and Tx Power gain
1878          * index diff of legacy to HT OFDM rate. */
1879         tempval = (*(u8 *)&hwinfo[EEPROM_RFIND_POWERDIFF]) & 0xff;
1880         rtlefuse->eeprom_txpowerdiff = tempval;
1881         rtlefuse->legacy_httxpowerdiff =
1882                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0];
1883
1884         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1885                 "TxPowerDiff = %#x\n", rtlefuse->eeprom_txpowerdiff);
1886
1887         /* Get TSSI value for each path. */
1888         usvalue = *(u16 *)&hwinfo[EEPROM_TSSI_A];
1889         rtlefuse->eeprom_tssi[RF90_PATH_A] = (u8)((usvalue & 0xff00) >> 8);
1890         usvalue = *(u8 *)&hwinfo[EEPROM_TSSI_B];
1891         rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff);
1892
1893         RTPRINT(rtlpriv, FINIT, INIT_TxPower, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1894                 rtlefuse->eeprom_tssi[RF90_PATH_A],
1895                 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1896
1897         /* Read antenna tx power offset of B/C/D to A  from EEPROM */
1898         /* and read ThermalMeter from EEPROM */
1899         tempval = *(u8 *)&hwinfo[EEPROM_THERMALMETER];
1900         rtlefuse->eeprom_thermalmeter = tempval;
1901         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1902                 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1903
1904         /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */
1905         rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f);
1906         rtlefuse->tssi_13dbm = rtlefuse->eeprom_thermalmeter * 100;
1907
1908         /* Read CrystalCap from EEPROM */
1909         tempval = (*(u8 *)&hwinfo[EEPROM_CRYSTALCAP]) >> 4;
1910         rtlefuse->eeprom_crystalcap = tempval;
1911         /* CrystalCap, BIT(12)~15 */
1912         rtlefuse->crystalcap = rtlefuse->eeprom_crystalcap;
1913
1914         /* Read IC Version && Channel Plan */
1915         /* Version ID, Channel plan */
1916         rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1917         rtlefuse->txpwr_fromeprom = true;
1918         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1919                 "EEPROM ChannelPlan = 0x%4x\n", rtlefuse->eeprom_channelplan);
1920
1921         /* Read Customer ID or Board Type!!! */
1922         tempval = *(u8 *)&hwinfo[EEPROM_BOARDTYPE];
1923         /* Change RF type definition */
1924         if (tempval == 0)
1925                 rtlphy->rf_type = RF_2T2R;
1926         else if (tempval == 1)
1927                 rtlphy->rf_type = RF_1T2R;
1928         else if (tempval == 2)
1929                 rtlphy->rf_type = RF_1T2R;
1930         else if (tempval == 3)
1931                 rtlphy->rf_type = RF_1T1R;
1932
1933         /* 1T2R but 1SS (1x1 receive combining) */
1934         rtlefuse->b1x1_recvcombine = false;
1935         if (rtlphy->rf_type == RF_1T2R) {
1936                 tempval = rtl_read_byte(rtlpriv, 0x07);
1937                 if (!(tempval & BIT(0))) {
1938                         rtlefuse->b1x1_recvcombine = true;
1939                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1940                                  "RF_TYPE=1T2R but only 1SS\n");
1941                 }
1942         }
1943         rtlefuse->b1ss_support = rtlefuse->b1x1_recvcombine;
1944         rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMID];
1945
1946         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x",
1947                  rtlefuse->eeprom_oemid);
1948
1949         /* set channel paln to world wide 13 */
1950         rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1951 }
1952
1953 void rtl92se_read_eeprom_info(struct ieee80211_hw *hw)
1954 {
1955         struct rtl_priv *rtlpriv = rtl_priv(hw);
1956         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1957         u8 tmp_u1b = 0;
1958
1959         tmp_u1b = rtl_read_byte(rtlpriv, EPROM_CMD);
1960
1961         if (tmp_u1b & BIT(4)) {
1962                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1963                 rtlefuse->epromtype = EEPROM_93C46;
1964         } else {
1965                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1966                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1967         }
1968
1969         if (tmp_u1b & BIT(5)) {
1970                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1971                 rtlefuse->autoload_failflag = false;
1972                 _rtl92se_read_adapter_info(hw);
1973         } else {
1974                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1975                 rtlefuse->autoload_failflag = true;
1976         }
1977 }
1978
1979 static void rtl92se_update_hal_rate_table(struct ieee80211_hw *hw,
1980                                           struct ieee80211_sta *sta)
1981 {
1982         struct rtl_priv *rtlpriv = rtl_priv(hw);
1983         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1984         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1985         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1986         u32 ratr_value;
1987         u8 ratr_index = 0;
1988         u8 nmode = mac->ht_enable;
1989         u8 mimo_ps = IEEE80211_SMPS_OFF;
1990         u16 shortgi_rate = 0;
1991         u32 tmp_ratr_value = 0;
1992         u8 curtxbw_40mhz = mac->bw_40;
1993         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1994                                 1 : 0;
1995         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1996                                 1 : 0;
1997         enum wireless_mode wirelessmode = mac->mode;
1998
1999         if (rtlhal->current_bandtype == BAND_ON_5G)
2000                 ratr_value = sta->supp_rates[1] << 4;
2001         else
2002                 ratr_value = sta->supp_rates[0];
2003         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2004                         sta->ht_cap.mcs.rx_mask[0] << 12);
2005         switch (wirelessmode) {
2006         case WIRELESS_MODE_B:
2007                 ratr_value &= 0x0000000D;
2008                 break;
2009         case WIRELESS_MODE_G:
2010                 ratr_value &= 0x00000FF5;
2011                 break;
2012         case WIRELESS_MODE_N_24G:
2013         case WIRELESS_MODE_N_5G:
2014                 nmode = 1;
2015                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2016                         ratr_value &= 0x0007F005;
2017                 } else {
2018                         u32 ratr_mask;
2019
2020                         if (get_rf_type(rtlphy) == RF_1T2R ||
2021                             get_rf_type(rtlphy) == RF_1T1R) {
2022                                 if (curtxbw_40mhz)
2023                                         ratr_mask = 0x000ff015;
2024                                 else
2025                                         ratr_mask = 0x000ff005;
2026                         } else {
2027                                 if (curtxbw_40mhz)
2028                                         ratr_mask = 0x0f0ff015;
2029                                 else
2030                                         ratr_mask = 0x0f0ff005;
2031                         }
2032
2033                         ratr_value &= ratr_mask;
2034                 }
2035                 break;
2036         default:
2037                 if (rtlphy->rf_type == RF_1T2R)
2038                         ratr_value &= 0x000ff0ff;
2039                 else
2040                         ratr_value &= 0x0f0ff0ff;
2041
2042                 break;
2043         }
2044
2045         if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2046                 ratr_value &= 0x0FFFFFFF;
2047         else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2048                 ratr_value &= 0x0FFFFFF0;
2049
2050         if (nmode && ((curtxbw_40mhz &&
2051                          curshortgi_40mhz) || (!curtxbw_40mhz &&
2052                                                  curshortgi_20mhz))) {
2053
2054                 ratr_value |= 0x10000000;
2055                 tmp_ratr_value = (ratr_value >> 12);
2056
2057                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2058                         if ((1 << shortgi_rate) & tmp_ratr_value)
2059                                 break;
2060                 }
2061
2062                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2063                     (shortgi_rate << 4) | (shortgi_rate);
2064
2065                 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2066         }
2067
2068         rtl_write_dword(rtlpriv, ARFR0 + ratr_index * 4, ratr_value);
2069         if (ratr_value & 0xfffff000)
2070                 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_N);
2071         else
2072                 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_BG);
2073
2074         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
2075                  rtl_read_dword(rtlpriv, ARFR0));
2076 }
2077
2078 static void rtl92se_update_hal_rate_mask(struct ieee80211_hw *hw,
2079                                          struct ieee80211_sta *sta,
2080                                          u8 rssi_level)
2081 {
2082         struct rtl_priv *rtlpriv = rtl_priv(hw);
2083         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2084         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2085         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2086         struct rtl_sta_info *sta_entry = NULL;
2087         u32 ratr_bitmap;
2088         u8 ratr_index = 0;
2089         u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2090                                 ? 1 : 0;
2091         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2092                                 1 : 0;
2093         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2094                                 1 : 0;
2095         enum wireless_mode wirelessmode = 0;
2096         bool shortgi = false;
2097         u32 ratr_value = 0;
2098         u8 shortgi_rate = 0;
2099         u32 mask = 0;
2100         u32 band = 0;
2101         bool bmulticast = false;
2102         u8 macid = 0;
2103         u8 mimo_ps = IEEE80211_SMPS_OFF;
2104
2105         sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2106         wirelessmode = sta_entry->wireless_mode;
2107         if (mac->opmode == NL80211_IFTYPE_STATION)
2108                 curtxbw_40mhz = mac->bw_40;
2109         else if (mac->opmode == NL80211_IFTYPE_AP ||
2110                 mac->opmode == NL80211_IFTYPE_ADHOC)
2111                 macid = sta->aid + 1;
2112
2113         if (rtlhal->current_bandtype == BAND_ON_5G)
2114                 ratr_bitmap = sta->supp_rates[1] << 4;
2115         else
2116                 ratr_bitmap = sta->supp_rates[0];
2117         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2118                         sta->ht_cap.mcs.rx_mask[0] << 12);
2119         switch (wirelessmode) {
2120         case WIRELESS_MODE_B:
2121                 band |= WIRELESS_11B;
2122                 ratr_index = RATR_INX_WIRELESS_B;
2123                 if (ratr_bitmap & 0x0000000c)
2124                         ratr_bitmap &= 0x0000000d;
2125                 else
2126                         ratr_bitmap &= 0x0000000f;
2127                 break;
2128         case WIRELESS_MODE_G:
2129                 band |= (WIRELESS_11G | WIRELESS_11B);
2130                 ratr_index = RATR_INX_WIRELESS_GB;
2131
2132                 if (rssi_level == 1)
2133                         ratr_bitmap &= 0x00000f00;
2134                 else if (rssi_level == 2)
2135                         ratr_bitmap &= 0x00000ff0;
2136                 else
2137                         ratr_bitmap &= 0x00000ff5;
2138                 break;
2139         case WIRELESS_MODE_A:
2140                 band |= WIRELESS_11A;
2141                 ratr_index = RATR_INX_WIRELESS_A;
2142                 ratr_bitmap &= 0x00000ff0;
2143                 break;
2144         case WIRELESS_MODE_N_24G:
2145         case WIRELESS_MODE_N_5G:
2146                 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2147                 ratr_index = RATR_INX_WIRELESS_NGB;
2148
2149                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2150                         if (rssi_level == 1)
2151                                 ratr_bitmap &= 0x00070000;
2152                         else if (rssi_level == 2)
2153                                 ratr_bitmap &= 0x0007f000;
2154                         else
2155                                 ratr_bitmap &= 0x0007f005;
2156                 } else {
2157                         if (rtlphy->rf_type == RF_1T2R ||
2158                                 rtlphy->rf_type == RF_1T1R) {
2159                                 if (rssi_level == 1) {
2160                                                 ratr_bitmap &= 0x000f0000;
2161                                 } else if (rssi_level == 3) {
2162                                         ratr_bitmap &= 0x000fc000;
2163                                 } else if (rssi_level == 5) {
2164                                                 ratr_bitmap &= 0x000ff000;
2165                                 } else {
2166                                         if (curtxbw_40mhz)
2167                                                 ratr_bitmap &= 0x000ff015;
2168                                         else
2169                                                 ratr_bitmap &= 0x000ff005;
2170                                 }
2171                         } else {
2172                                 if (rssi_level == 1) {
2173                                         ratr_bitmap &= 0x0f8f0000;
2174                                 } else if (rssi_level == 3) {
2175                                         ratr_bitmap &= 0x0f8fc000;
2176                                 } else if (rssi_level == 5) {
2177                                         ratr_bitmap &= 0x0f8ff000;
2178                                 } else {
2179                                         if (curtxbw_40mhz)
2180                                                 ratr_bitmap &= 0x0f8ff015;
2181                                         else
2182                                                 ratr_bitmap &= 0x0f8ff005;
2183                                 }
2184                         }
2185                 }
2186
2187                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2188                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2189                         if (macid == 0)
2190                                 shortgi = true;
2191                         else if (macid == 1)
2192                                 shortgi = false;
2193                 }
2194                 break;
2195         default:
2196                 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2197                 ratr_index = RATR_INX_WIRELESS_NGB;
2198
2199                 if (rtlphy->rf_type == RF_1T2R)
2200                         ratr_bitmap &= 0x000ff0ff;
2201                 else
2202                         ratr_bitmap &= 0x0f8ff0ff;
2203                 break;
2204         }
2205
2206         if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2207                 ratr_bitmap &= 0x0FFFFFFF;
2208         else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2209                 ratr_bitmap &= 0x0FFFFFF0;
2210
2211         if (shortgi) {
2212                 ratr_bitmap |= 0x10000000;
2213                 /* Get MAX MCS available. */
2214                 ratr_value = (ratr_bitmap >> 12);
2215                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2216                         if ((1 << shortgi_rate) & ratr_value)
2217                                 break;
2218                 }
2219
2220                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2221                         (shortgi_rate << 4) | (shortgi_rate);
2222                 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2223         }
2224
2225         mask |= (bmulticast ? 1 : 0) << 9 | (macid & 0x1f) << 4 | (band & 0xf);
2226
2227         RT_TRACE(rtlpriv, COMP_RATR, DBG_TRACE, "mask = %x, bitmap = %x\n",
2228                  mask, ratr_bitmap);
2229         rtl_write_dword(rtlpriv, 0x2c4, ratr_bitmap);
2230         rtl_write_dword(rtlpriv, WFM5, (FW_RA_UPDATE_MASK | (mask << 8)));
2231
2232         if (macid != 0)
2233                 sta_entry->ratr_index = ratr_index;
2234 }
2235
2236 void rtl92se_update_hal_rate_tbl(struct ieee80211_hw *hw,
2237                 struct ieee80211_sta *sta, u8 rssi_level)
2238 {
2239         struct rtl_priv *rtlpriv = rtl_priv(hw);
2240
2241         if (rtlpriv->dm.useramask)
2242                 rtl92se_update_hal_rate_mask(hw, sta, rssi_level);
2243         else
2244                 rtl92se_update_hal_rate_table(hw, sta);
2245 }
2246
2247 void rtl92se_update_channel_access_setting(struct ieee80211_hw *hw)
2248 {
2249         struct rtl_priv *rtlpriv = rtl_priv(hw);
2250         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2251         u16 sifs_timer;
2252
2253         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2254                                       (u8 *)&mac->slot_time);
2255         sifs_timer = 0x0e0e;
2256         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2257
2258 }
2259
2260 /* this ifunction is for RFKILL, it's different with windows,
2261  * because UI will disable wireless when GPIO Radio Off.
2262  * And here we not check or Disable/Enable ASPM like windows*/
2263 bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2264 {
2265         struct rtl_priv *rtlpriv = rtl_priv(hw);
2266         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2267         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2268         enum rf_pwrstate rfpwr_toset /*, cur_rfstate */;
2269         unsigned long flag = 0;
2270         bool actuallyset = false;
2271         bool turnonbypowerdomain = false;
2272
2273         /* just 8191se can check gpio before firstup, 92c/92d have fixed it */
2274         if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter))
2275                 return false;
2276
2277         if (ppsc->swrf_processing)
2278                 return false;
2279
2280         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2281         if (ppsc->rfchange_inprogress) {
2282                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2283                 return false;
2284         } else {
2285                 ppsc->rfchange_inprogress = true;
2286                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2287         }
2288
2289         /* cur_rfstate = ppsc->rfpwr_state;*/
2290
2291         /* because after _rtl92s_phy_set_rfhalt, all power
2292          * closed, so we must open some power for GPIO check,
2293          * or we will always check GPIO RFOFF here,
2294          * And we should close power after GPIO check */
2295         if (RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
2296                 _rtl92se_power_domain_init(hw);
2297                 turnonbypowerdomain = true;
2298         }
2299
2300         rfpwr_toset = _rtl92se_rf_onoff_detect(hw);
2301
2302         if ((ppsc->hwradiooff) && (rfpwr_toset == ERFON)) {
2303                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2304                          "RFKILL-HW Radio ON, RF ON\n");
2305
2306                 rfpwr_toset = ERFON;
2307                 ppsc->hwradiooff = false;
2308                 actuallyset = true;
2309         } else if ((ppsc->hwradiooff == false) && (rfpwr_toset == ERFOFF)) {
2310                 RT_TRACE(rtlpriv, COMP_RF,
2311                          DBG_DMESG, "RFKILL-HW Radio OFF, RF OFF\n");
2312
2313                 rfpwr_toset = ERFOFF;
2314                 ppsc->hwradiooff = true;
2315                 actuallyset = true;
2316         }
2317
2318         if (actuallyset) {
2319                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2320                 ppsc->rfchange_inprogress = false;
2321                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2322
2323         /* this not include ifconfig wlan0 down case */
2324         /* } else if (rfpwr_toset == ERFOFF || cur_rfstate == ERFOFF) { */
2325         } else {
2326                 /* because power_domain_init may be happen when
2327                  * _rtl92s_phy_set_rfhalt, this will open some powers
2328                  * and cause current increasing about 40 mA for ips,
2329                  * rfoff and ifconfig down, so we set
2330                  * _rtl92s_phy_set_rfhalt again here */
2331                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC &&
2332                         turnonbypowerdomain) {
2333                         _rtl92s_phy_set_rfhalt(hw);
2334                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2335                 }
2336
2337                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2338                 ppsc->rfchange_inprogress = false;
2339                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2340         }
2341
2342         *valid = 1;
2343         return !ppsc->hwradiooff;
2344
2345 }
2346
2347 /* Is_wepkey just used for WEP used as group & pairwise key
2348  * if pairwise is AES ang group is WEP Is_wepkey == false.*/
2349 void rtl92se_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr,
2350         bool is_group, u8 enc_algo, bool is_wepkey, bool clear_all)
2351 {
2352         struct rtl_priv *rtlpriv = rtl_priv(hw);
2353         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2354         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2355         u8 *macaddr = p_macaddr;
2356
2357         u32 entry_id = 0;
2358         bool is_pairwise = false;
2359
2360         static u8 cam_const_addr[4][6] = {
2361                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2362                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2363                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2364                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2365         };
2366         static u8 cam_const_broad[] = {
2367                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2368         };
2369
2370         if (clear_all) {
2371                 u8 idx = 0;
2372                 u8 cam_offset = 0;
2373                 u8 clear_number = 5;
2374
2375                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2376
2377                 for (idx = 0; idx < clear_number; idx++) {
2378                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2379                         rtl_cam_empty_entry(hw, cam_offset + idx);
2380
2381                         if (idx < 5) {
2382                                 memset(rtlpriv->sec.key_buf[idx], 0,
2383                                        MAX_KEY_LEN);
2384                                 rtlpriv->sec.key_len[idx] = 0;
2385                         }
2386                 }
2387
2388         } else {
2389                 switch (enc_algo) {
2390                 case WEP40_ENCRYPTION:
2391                         enc_algo = CAM_WEP40;
2392                         break;
2393                 case WEP104_ENCRYPTION:
2394                         enc_algo = CAM_WEP104;
2395                         break;
2396                 case TKIP_ENCRYPTION:
2397                         enc_algo = CAM_TKIP;
2398                         break;
2399                 case AESCCMP_ENCRYPTION:
2400                         enc_algo = CAM_AES;
2401                         break;
2402                 default:
2403                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2404                                  "switch case not processed\n");
2405                         enc_algo = CAM_TKIP;
2406                         break;
2407                 }
2408
2409                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2410                         macaddr = cam_const_addr[key_index];
2411                         entry_id = key_index;
2412                 } else {
2413                         if (is_group) {
2414                                 macaddr = cam_const_broad;
2415                                 entry_id = key_index;
2416                         } else {
2417                                 if (mac->opmode == NL80211_IFTYPE_AP) {
2418                                         entry_id = rtl_cam_get_free_entry(hw,
2419                                                                  p_macaddr);
2420                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2421                                                 RT_TRACE(rtlpriv,
2422                                                          COMP_SEC, DBG_EMERG,
2423                                                          "Can not find free hw security cam entry\n");
2424                                                 return;
2425                                         }
2426                                 } else {
2427                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2428                                 }
2429
2430                                 key_index = PAIRWISE_KEYIDX;
2431                                 is_pairwise = true;
2432                         }
2433                 }
2434
2435                 if (rtlpriv->sec.key_len[key_index] == 0) {
2436                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2437                                  "delete one entry, entry_id is %d\n",
2438                                  entry_id);
2439                         if (mac->opmode == NL80211_IFTYPE_AP)
2440                                 rtl_cam_del_entry(hw, p_macaddr);
2441                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2442                 } else {
2443                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2444                                  "The insert KEY length is %d\n",
2445                                  rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2446                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2447                                  "The insert KEY is %x %x\n",
2448                                  rtlpriv->sec.key_buf[0][0],
2449                                  rtlpriv->sec.key_buf[0][1]);
2450
2451                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2452                                  "add one entry\n");
2453                         if (is_pairwise) {
2454                                 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2455                                               "Pairwise Key content",
2456                                               rtlpriv->sec.pairwise_key,
2457                                               rtlpriv->sec.
2458                                               key_len[PAIRWISE_KEYIDX]);
2459
2460                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2461                                          "set Pairwise key\n");
2462
2463                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2464                                         entry_id, enc_algo,
2465                                         CAM_CONFIG_NO_USEDK,
2466                                         rtlpriv->sec.key_buf[key_index]);
2467                         } else {
2468                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2469                                          "set group key\n");
2470
2471                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2472                                         rtl_cam_add_one_entry(hw,
2473                                                 rtlefuse->dev_addr,
2474                                                 PAIRWISE_KEYIDX,
2475                                                 CAM_PAIRWISE_KEY_POSITION,
2476                                                 enc_algo, CAM_CONFIG_NO_USEDK,
2477                                                 rtlpriv->sec.key_buf[entry_id]);
2478                                 }
2479
2480                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2481                                               entry_id, enc_algo,
2482                                               CAM_CONFIG_NO_USEDK,
2483                                               rtlpriv->sec.key_buf[entry_id]);
2484                         }
2485
2486                 }
2487         }
2488 }
2489
2490 void rtl92se_suspend(struct ieee80211_hw *hw)
2491 {
2492         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2493
2494         rtlpci->up_first_time = true;
2495 }
2496
2497 void rtl92se_resume(struct ieee80211_hw *hw)
2498 {
2499         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2500         u32 val;
2501
2502         pci_read_config_dword(rtlpci->pdev, 0x40, &val);
2503         if ((val & 0x0000ff00) != 0)
2504                 pci_write_config_dword(rtlpci->pdev, 0x40,
2505                         val & 0xffff00ff);
2506 }