1 /* Moorestown PMIC GPIO (access through IPC) driver
2 * Copyright (c) 2008 - 2009, Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 * Moorestown platform PMIC chip
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include <linux/stddef.h>
27 #include <linux/slab.h>
28 #include <linux/ioport.h>
29 #include <linux/init.h>
31 #include <linux/gpio.h>
32 #include <asm/intel_scu_ipc.h>
33 #include <linux/device.h>
34 #include <linux/intel_pmic_gpio.h>
35 #include <linux/platform_device.h>
37 #define DRIVER_NAME "pmic_gpio"
39 /* register offset that IPC driver should use
40 * 8 GPIO + 8 GPOSW (6 controllable) + 8GPO
42 enum pmic_gpio_register {
51 /* bits definition for GPIO & GPOSW */
56 #define GPIO_INTCTL 0x30
59 #define GPOSW_DRV 0x01
60 #define GPOSW_DOU 0x08
61 #define GPOSW_RDRV 0x30
63 #define GPIO_UPDATE_TYPE 0x80000000
69 struct gpio_chip chip;
73 unsigned int update_type;
77 static void pmic_program_irqtype(int gpio, int type)
79 if (type & IRQ_TYPE_EDGE_RISING)
80 intel_scu_ipc_update_register(GPIO0 + gpio, 0x20, 0x20);
82 intel_scu_ipc_update_register(GPIO0 + gpio, 0x00, 0x20);
84 if (type & IRQ_TYPE_EDGE_FALLING)
85 intel_scu_ipc_update_register(GPIO0 + gpio, 0x10, 0x10);
87 intel_scu_ipc_update_register(GPIO0 + gpio, 0x00, 0x10);
90 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
94 "%s: only pin 0-7 support input\n", __func__);
95 return -1;/* we only have 8 GPIO can use as input */
97 return intel_scu_ipc_update_register(GPIO0 + offset,
101 static int pmic_gpio_direction_output(struct gpio_chip *chip,
102 unsigned offset, int value)
106 if (offset < 8)/* it is GPIO */
107 rc = intel_scu_ipc_update_register(GPIO0 + offset,
108 GPIO_DRV | (value ? GPIO_DOU : 0),
109 GPIO_DRV | GPIO_DOU | GPIO_DIR);
110 else if (offset < 16)/* it is GPOSW */
111 rc = intel_scu_ipc_update_register(GPOSWCTL0 + offset - 8,
112 GPOSW_DRV | (value ? GPOSW_DOU : 0),
113 GPOSW_DRV | GPOSW_DOU | GPOSW_RDRV);
114 else if (offset > 15 && offset < 24)/* it is GPO */
115 rc = intel_scu_ipc_update_register(GPO,
116 value ? 1 << (offset - 16) : 0,
120 "%s: invalid PMIC GPIO pin %d!\n", __func__, offset);
127 static int pmic_gpio_get(struct gpio_chip *chip, unsigned offset)
132 /* we only have 8 GPIO pins we can use as input */
135 ret = intel_scu_ipc_ioread8(GPIO0 + offset, &r);
141 static void pmic_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
143 if (offset < 8)/* it is GPIO */
144 intel_scu_ipc_update_register(GPIO0 + offset,
145 GPIO_DRV | (value ? GPIO_DOU : 0),
146 GPIO_DRV | GPIO_DOU);
147 else if (offset < 16)/* it is GPOSW */
148 intel_scu_ipc_update_register(GPOSWCTL0 + offset - 8,
149 GPOSW_DRV | (value ? GPOSW_DOU : 0),
150 GPOSW_DRV | GPOSW_DOU | GPOSW_RDRV);
151 else if (offset > 15 && offset < 24) /* it is GPO */
152 intel_scu_ipc_update_register(GPO,
153 value ? 1 << (offset - 16) : 0,
158 * This is called from genirq with pg->buslock locked and
159 * irq_desc->lock held. We can not access the scu bus here, so we
160 * store the change and update in the bus_sync_unlock() function below
162 static int pmic_irq_type(struct irq_data *data, unsigned type)
164 struct pmic_gpio *pg = irq_data_get_irq_chip_data(data);
165 u32 gpio = data->irq - pg->irq_base;
167 if (gpio >= pg->chip.ngpio)
170 pg->trigger_type = type;
171 pg->update_type = gpio | GPIO_UPDATE_TYPE;
175 static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
177 struct pmic_gpio *pg = container_of(chip, struct pmic_gpio, chip);
179 return pg->irq_base + offset;
182 static void pmic_bus_lock(struct irq_data *data)
184 struct pmic_gpio *pg = irq_data_get_irq_chip_data(data);
186 mutex_lock(&pg->buslock);
189 static void pmic_bus_sync_unlock(struct irq_data *data)
191 struct pmic_gpio *pg = irq_data_get_irq_chip_data(data);
193 if (pg->update_type) {
194 unsigned int gpio = pg->update_type & ~GPIO_UPDATE_TYPE;
196 pmic_program_irqtype(gpio, pg->trigger_type);
199 mutex_unlock(&pg->buslock);
202 /* the gpiointr register is read-clear, so just do nothing. */
203 static void pmic_irq_unmask(struct irq_data *data) { }
205 static void pmic_irq_mask(struct irq_data *data) { }
207 static struct irq_chip pmic_irqchip = {
209 .irq_mask = pmic_irq_mask,
210 .irq_unmask = pmic_irq_unmask,
211 .irq_set_type = pmic_irq_type,
214 static void pmic_irq_handler(unsigned irq, struct irq_desc *desc)
216 struct pmic_gpio *pg = (struct pmic_gpio *)get_irq_data(irq);
217 u8 intsts = *((u8 *)pg->gpiointr + 4);
220 for (gpio = 0; gpio < 8; gpio++) {
221 if (intsts & (1 << gpio)) {
222 pr_debug("pmic pin %d triggered\n", gpio);
223 generic_handle_irq(pg->irq_base + gpio);
226 desc->chip->irq_eoi(get_irq_desc_chip_data(desc));
229 static int __devinit platform_pmic_gpio_probe(struct platform_device *pdev)
231 struct device *dev = &pdev->dev;
232 int irq = platform_get_irq(pdev, 0);
233 struct intel_pmic_gpio_platform_data *pdata = dev->platform_data;
235 struct pmic_gpio *pg;
240 dev_dbg(dev, "no IRQ line\n");
244 if (!pdata || !pdata->gpio_base || !pdata->irq_base) {
245 dev_dbg(dev, "incorrect or missing platform data\n");
249 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
253 dev_set_drvdata(dev, pg);
256 /* setting up SRAM mapping for GPIOINT register */
257 pg->gpiointr = ioremap_nocache(pdata->gpiointr, 8);
259 printk(KERN_ERR "%s: Can not map GPIOINT.\n", __func__);
263 pg->irq_base = pdata->irq_base;
264 pg->chip.label = "intel_pmic";
265 pg->chip.direction_input = pmic_gpio_direction_input;
266 pg->chip.direction_output = pmic_gpio_direction_output;
267 pg->chip.get = pmic_gpio_get;
268 pg->chip.set = pmic_gpio_set;
269 pg->chip.to_irq = pmic_gpio_to_irq;
270 pg->chip.base = pdata->gpio_base;
271 pg->chip.ngpio = NUM_GPIO;
272 pg->chip.can_sleep = 1;
275 mutex_init(&pg->buslock);
278 retval = gpiochip_add(&pg->chip);
280 printk(KERN_ERR "%s: Can not add pmic gpio chip.\n", __func__);
283 set_irq_data(pg->irq, pg);
284 set_irq_chained_handler(pg->irq, pmic_irq_handler);
285 for (i = 0; i < 8; i++) {
286 set_irq_chip_and_handler_name(i + pg->irq_base, &pmic_irqchip,
287 handle_simple_irq, "demux");
288 set_irq_chip_data(i + pg->irq_base, pg);
292 iounmap(pg->gpiointr);
298 /* at the same time, register a platform driver
299 * this supports the sfi 0.81 fw */
300 static struct platform_driver platform_pmic_gpio_driver = {
303 .owner = THIS_MODULE,
305 .probe = platform_pmic_gpio_probe,
308 static int __init platform_pmic_gpio_init(void)
310 return platform_driver_register(&platform_pmic_gpio_driver);
313 subsys_initcall(platform_pmic_gpio_init);
315 MODULE_AUTHOR("Alek Du <alek.du@intel.com>");
316 MODULE_DESCRIPTION("Intel Moorestown PMIC GPIO driver");
317 MODULE_LICENSE("GPL v2");