sound/soc/codecs/wm8350.c

   1 /*
   2  * wm8350.c -- WM8350 ALSA SoC audio driver
   3  *
   4  * Copyright (C) 2007, 2008 Wolfson Microelectronics PLC.
   5  *
   6  * Author: Liam Girdwood <lrg@slimlogic.co.uk>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15 #include <linux/init.h>
  16 #include <linux/slab.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/mfd/wm8350/audio.h>
  21 #include <linux/mfd/wm8350/core.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <sound/core.h>
  24 #include <sound/pcm.h>
  25 #include <sound/pcm_params.h>
  26 #include <sound/soc.h>
  27 #include <sound/initval.h>
  28 #include <sound/tlv.h>
  29
  30 #include "wm8350.h"
  31
  32 #define WM8350_OUTn_0dB 0x39
  33
  34 #define WM8350_RAMP_NONE        0
  35 #define WM8350_RAMP_UP          1
  36 #define WM8350_RAMP_DOWN        2
  37
  38 /* We only include the analogue supplies here; the digital supplies
  39  * need to be available well before this driver can be probed.
  40  */
  41 static const char *supply_names[] = {
  42         "AVDD",
  43         "HPVDD",
  44 };
  45
  46 struct wm8350_output {
  47         u16 active;
  48         u16 left_vol;
  49         u16 right_vol;
  50         u16 ramp;
  51         u16 mute;
  52 };
  53
  54 struct wm8350_jack_data {
  55         struct snd_soc_jack *jack;
  56         int report;
  57         int short_report;
  58 };
  59
  60 struct wm8350_data {
  61         struct snd_soc_codec codec;
  62         struct wm8350_output out1;
  63         struct wm8350_output out2;
  64         struct wm8350_jack_data hpl;
  65         struct wm8350_jack_data hpr;
  66         struct wm8350_jack_data mic;
  67         struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
  68         int fll_freq_out;
  69         int fll_freq_in;
  70 };
  71
  72 static unsigned int wm8350_codec_cache_read(struct snd_soc_codec *codec,
  73                                             unsigned int reg)
  74 {
  75         struct wm8350 *wm8350 = codec->control_data;
  76         return wm8350->reg_cache[reg];
  77 }
  78
  79 static unsigned int wm8350_codec_read(struct snd_soc_codec *codec,
  80                                       unsigned int reg)
  81 {
  82         struct wm8350 *wm8350 = codec->control_data;
  83         return wm8350_reg_read(wm8350, reg);
  84 }
  85
  86 static int wm8350_codec_write(struct snd_soc_codec *codec, unsigned int reg,
  87                               unsigned int value)
  88 {
  89         struct wm8350 *wm8350 = codec->control_data;
  90         return wm8350_reg_write(wm8350, reg, value);
  91 }
  92
  93 /*
  94  * Ramp OUT1 PGA volume to minimise pops at stream startup and shutdown.
  95  */
  96 static inline int wm8350_out1_ramp_step(struct snd_soc_codec *codec)
  97 {
  98         struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
  99         struct wm8350_output *out1 = &wm8350_data->out1;
 100         struct wm8350 *wm8350 = codec->control_data;
 101         int left_complete = 0, right_complete = 0;
 102         u16 reg, val;
 103
 104         /* left channel */
 105         reg = wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME);
 106         val = (reg & WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
 107
 108         if (out1->ramp == WM8350_RAMP_UP) {
 109                 /* ramp step up */
 110                 if (val < out1->left_vol) {
 111                         val++;
 112                         reg &= ~WM8350_OUT1L_VOL_MASK;
 113                         wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
 114                                          reg | (val << WM8350_OUT1L_VOL_SHIFT));
 115                 } else
 116                         left_complete = 1;
 117         } else if (out1->ramp == WM8350_RAMP_DOWN) {
 118                 /* ramp step down */
 119                 if (val > 0) {
 120                         val--;
 121                         reg &= ~WM8350_OUT1L_VOL_MASK;
 122                         wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
 123                                          reg | (val << WM8350_OUT1L_VOL_SHIFT));
 124                 } else
 125                         left_complete = 1;
 126         } else
 127                 return 1;
 128
 129         /* right channel */
 130         reg = wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME);
 131         val = (reg & WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
 132         if (out1->ramp == WM8350_RAMP_UP) {
 133                 /* ramp step up */
 134                 if (val < out1->right_vol) {
 135                         val++;
 136                         reg &= ~WM8350_OUT1R_VOL_MASK;
 137                         wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
 138                                          reg | (val << WM8350_OUT1R_VOL_SHIFT));
 139                 } else
 140                         right_complete = 1;
 141         } else if (out1->ramp == WM8350_RAMP_DOWN) {
 142                 /* ramp step down */
 143                 if (val > 0) {
 144                         val--;
 145                         reg &= ~WM8350_OUT1R_VOL_MASK;
 146                         wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
 147                                          reg | (val << WM8350_OUT1R_VOL_SHIFT));
 148                 } else
 149                         right_complete = 1;
 150         }
 151
 152         /* only hit the update bit if either volume has changed this step */
 153         if (!left_complete || !right_complete)
 154                 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, WM8350_OUT1_VU);
 155
 156         return left_complete & right_complete;
 157 }
 158
 159 /*
 160  * Ramp OUT2 PGA volume to minimise pops at stream startup and shutdown.
 161  */
 162 static inline int wm8350_out2_ramp_step(struct snd_soc_codec *codec)
 163 {
 164         struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
 165         struct wm8350_output *out2 = &wm8350_data->out2;
 166         struct wm8350 *wm8350 = codec->control_data;
 167         int left_complete = 0, right_complete = 0;
 168         u16 reg, val;
 169
 170         /* left channel */
 171         reg = wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME);
 172         val = (reg & WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
 173         if (out2->ramp == WM8350_RAMP_UP) {
 174                 /* ramp step up */
 175                 if (val < out2->left_vol) {
 176                         val++;
 177                         reg &= ~WM8350_OUT2L_VOL_MASK;
 178                         wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
 179                                          reg | (val << WM8350_OUT1L_VOL_SHIFT));
 180                 } else
 181                         left_complete = 1;
 182         } else if (out2->ramp == WM8350_RAMP_DOWN) {
 183                 /* ramp step down */
 184                 if (val > 0) {
 185                         val--;
 186                         reg &= ~WM8350_OUT2L_VOL_MASK;
 187                         wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
 188                                          reg | (val << WM8350_OUT1L_VOL_SHIFT));
 189                 } else
 190                         left_complete = 1;
 191         } else
 192                 return 1;
 193
 194         /* right channel */
 195         reg = wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME);
 196         val = (reg & WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
 197         if (out2->ramp == WM8350_RAMP_UP) {
 198                 /* ramp step up */
 199                 if (val < out2->right_vol) {
 200                         val++;
 201                         reg &= ~WM8350_OUT2R_VOL_MASK;
 202                         wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
 203                                          reg | (val << WM8350_OUT1R_VOL_SHIFT));
 204                 } else
 205                         right_complete = 1;
 206         } else if (out2->ramp == WM8350_RAMP_DOWN) {
 207                 /* ramp step down */
 208                 if (val > 0) {
 209                         val--;
 210                         reg &= ~WM8350_OUT2R_VOL_MASK;
 211                         wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
 212                                          reg | (val << WM8350_OUT1R_VOL_SHIFT));
 213                 } else
 214                         right_complete = 1;
 215         }
 216
 217         /* only hit the update bit if either volume has changed this step */
 218         if (!left_complete || !right_complete)
 219                 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, WM8350_OUT2_VU);
 220
 221         return left_complete & right_complete;
 222 }
 223
 224 /*
 225  * This work ramps both output PGAs at stream start/stop time to
 226  * minimise pop associated with DAPM power switching.
 227  * It's best to enable Zero Cross when ramping occurs to minimise any
 228  * zipper noises.
 229  */
 230 static void wm8350_pga_work(struct work_struct *work)
 231 {
 232         struct snd_soc_dapm_context *dapm =
 233             container_of(work, struct snd_soc_dapm_context, delayed_work.work);
 234         struct snd_soc_codec *codec = dapm->codec;
 235         struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
 236         struct wm8350_output *out1 = &wm8350_data->out1,
 237             *out2 = &wm8350_data->out2;
 238         int i, out1_complete, out2_complete;
 239
 240         /* do we need to ramp at all ? */
 241         if (out1->ramp == WM8350_RAMP_NONE && out2->ramp == WM8350_RAMP_NONE)
 242                 return;
 243
 244         /* PGA volumes have 6 bits of resolution to ramp */
 245         for (i = 0; i <= 63; i++) {
 246                 out1_complete = 1, out2_complete = 1;
 247                 if (out1->ramp != WM8350_RAMP_NONE)
 248                         out1_complete = wm8350_out1_ramp_step(codec);
 249                 if (out2->ramp != WM8350_RAMP_NONE)
 250                         out2_complete = wm8350_out2_ramp_step(codec);
 251
 252                 /* ramp finished ? */
 253                 if (out1_complete && out2_complete)
 254                         break;
 255
 256                 /* we need to delay longer on the up ramp */
 257                 if (out1->ramp == WM8350_RAMP_UP ||
 258                     out2->ramp == WM8350_RAMP_UP) {
 259                         /* delay is longer over 0dB as increases are larger */
 260                         if (i >= WM8350_OUTn_0dB)
 261                                 schedule_timeout_interruptible(msecs_to_jiffies
 262                                                                (2));
 263                         else
 264                                 schedule_timeout_interruptible(msecs_to_jiffies
 265                                                                (1));
 266                 } else
 267                         udelay(50);     /* doesn't matter if we delay longer */
 268         }
 269
 270         out1->ramp = WM8350_RAMP_NONE;
 271         out2->ramp = WM8350_RAMP_NONE;
 272 }
 273
 274 /*
 275  * WM8350 Controls
 276  */
 277
 278 static int pga_event(struct snd_soc_dapm_widget *w,
 279                      struct snd_kcontrol *kcontrol, int event)
 280 {
 281         struct snd_soc_codec *codec = w->codec;
 282         struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
 283         struct wm8350_output *out;
 284
 285         switch (w->shift) {
 286         case 0:
 287         case 1:
 288                 out = &wm8350_data->out1;
 289                 break;
 290         case 2:
 291         case 3:
 292                 out = &wm8350_data->out2;
 293                 break;
 294
 295         default:
 296                 BUG();
 297                 return -1;
 298         }
 299
 300         switch (event) {
 301         case SND_SOC_DAPM_POST_PMU:
 302                 out->ramp = WM8350_RAMP_UP;
 303                 out->active = 1;
 304
 305                 if (!delayed_work_pending(&codec->dapm.delayed_work))
 306                         schedule_delayed_work(&codec->dapm.delayed_work,
 307                                               msecs_to_jiffies(1));
 308                 break;
 309
 310         case SND_SOC_DAPM_PRE_PMD:
 311                 out->ramp = WM8350_RAMP_DOWN;
 312                 out->active = 0;
 313
 314                 if (!delayed_work_pending(&codec->dapm.delayed_work))
 315                         schedule_delayed_work(&codec->dapm.delayed_work,
 316                                               msecs_to_jiffies(1));
 317                 break;
 318         }
 319
 320         return 0;
 321 }
 322
 323 static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol,
 324                                   struct snd_ctl_elem_value *ucontrol)
 325 {
 326         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 327         struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec);
 328         struct wm8350_output *out = NULL;
 329         struct soc_mixer_control *mc =
 330                 (struct soc_mixer_control *)kcontrol->private_value;
 331         int ret;
 332         unsigned int reg = mc->reg;
 333         u16 val;
 334
 335         /* For OUT1 and OUT2 we shadow the values and only actually write
 336          * them out when active in order to ensure the amplifier comes on
 337          * as quietly as possible. */
 338         switch (reg) {
 339         case WM8350_LOUT1_VOLUME:
 340                 out = &wm8350_priv->out1;
 341                 break;
 342         case WM8350_LOUT2_VOLUME:
 343                 out = &wm8350_priv->out2;
 344                 break;
 345         default:
 346                 break;
 347         }
 348
 349         if (out) {
 350                 out->left_vol = ucontrol->value.integer.value[0];
 351                 out->right_vol = ucontrol->value.integer.value[1];
 352                 if (!out->active)
 353                         return 1;
 354         }
 355
 356         ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
 357         if (ret < 0)
 358                 return ret;
 359
 360         /* now hit the volume update bits (always bit 8) */
 361         val = wm8350_codec_read(codec, reg);
 362         wm8350_codec_write(codec, reg, val | WM8350_OUT1_VU);
 363         return 1;
 364 }
 365
 366 static int wm8350_get_volsw_2r(struct snd_kcontrol *kcontrol,
 367                                struct snd_ctl_elem_value *ucontrol)
 368 {
 369         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 370         struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec);
 371         struct wm8350_output *out1 = &wm8350_priv->out1;
 372         struct wm8350_output *out2 = &wm8350_priv->out2;
 373         struct soc_mixer_control *mc =
 374                 (struct soc_mixer_control *)kcontrol->private_value;
 375         unsigned int reg = mc->reg;
 376
 377         /* If these are cached registers use the cache */
 378         switch (reg) {
 379         case WM8350_LOUT1_VOLUME:
 380                 ucontrol->value.integer.value[0] = out1->left_vol;
 381                 ucontrol->value.integer.value[1] = out1->right_vol;
 382                 return 0;
 383
 384         case WM8350_LOUT2_VOLUME:
 385                 ucontrol->value.integer.value[0] = out2->left_vol;
 386                 ucontrol->value.integer.value[1] = out2->right_vol;
 387                 return 0;
 388
 389         default:
 390                 break;
 391         }
 392
 393         return snd_soc_get_volsw_2r(kcontrol, ucontrol);
 394 }
 395
 396 /* double control with volume update */
 397 #define SOC_WM8350_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, \
 398                                 xinvert, tlv_array) \
 399 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
 400         .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
 401                 SNDRV_CTL_ELEM_ACCESS_READWRITE | \
 402                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
 403         .tlv.p = (tlv_array), \
 404         .info = snd_soc_info_volsw_2r, \
 405         .get = wm8350_get_volsw_2r, .put = wm8350_put_volsw_2r_vu, \
 406         .private_value = (unsigned long)&(struct soc_mixer_control) \
 407                 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
 408                  .rshift = xshift, .max = xmax, .invert = xinvert}, }
 409
 410 static const char *wm8350_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" };
 411 static const char *wm8350_pol[] = { "Normal", "Inv R", "Inv L", "Inv L & R" };
 412 static const char *wm8350_dacmutem[] = { "Normal", "Soft" };
 413 static const char *wm8350_dacmutes[] = { "Fast", "Slow" };
 414 static const char *wm8350_adcfilter[] = { "None", "High Pass" };
 415 static const char *wm8350_adchp[] = { "44.1kHz", "8kHz", "16kHz", "32kHz" };
 416 static const char *wm8350_lr[] = { "Left", "Right" };
 417
 418 static const struct soc_enum wm8350_enum[] = {
 419         SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 4, 4, wm8350_deemp),
 420         SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 0, 4, wm8350_pol),
 421         SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 14, 2, wm8350_dacmutem),
 422         SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 13, 2, wm8350_dacmutes),
 423         SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 15, 2, wm8350_adcfilter),
 424         SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 8, 4, wm8350_adchp),
 425         SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 0, 4, wm8350_pol),
 426         SOC_ENUM_SINGLE(WM8350_INPUT_MIXER_VOLUME, 15, 2, wm8350_lr),
 427 };
 428
 429 static DECLARE_TLV_DB_SCALE(pre_amp_tlv, -1200, 3525, 0);
 430 static DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 600, 0);
 431 static DECLARE_TLV_DB_SCALE(dac_pcm_tlv, -7163, 36, 1);
 432 static DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -12700, 50, 1);
 433 static DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 1);
 434
 435 static const unsigned int capture_sd_tlv[] = {
 436         TLV_DB_RANGE_HEAD(2),
 437         0, 12, TLV_DB_SCALE_ITEM(-3600, 300, 1),
 438         13, 15, TLV_DB_SCALE_ITEM(0, 0, 0),
 439 };
 440
 441 static const struct snd_kcontrol_new wm8350_snd_controls[] = {
 442         SOC_ENUM("Playback Deemphasis", wm8350_enum[0]),
 443         SOC_ENUM("Playback DAC Inversion", wm8350_enum[1]),
 444         SOC_WM8350_DOUBLE_R_TLV("Playback PCM Volume",
 445                                 WM8350_DAC_DIGITAL_VOLUME_L,
 446                                 WM8350_DAC_DIGITAL_VOLUME_R,
 447                                 0, 255, 0, dac_pcm_tlv),
 448         SOC_ENUM("Playback PCM Mute Function", wm8350_enum[2]),
 449         SOC_ENUM("Playback PCM Mute Speed", wm8350_enum[3]),
 450         SOC_ENUM("Capture PCM Filter", wm8350_enum[4]),
 451         SOC_ENUM("Capture PCM HP Filter", wm8350_enum[5]),
 452         SOC_ENUM("Capture ADC Inversion", wm8350_enum[6]),
 453         SOC_WM8350_DOUBLE_R_TLV("Capture PCM Volume",
 454                                 WM8350_ADC_DIGITAL_VOLUME_L,
 455                                 WM8350_ADC_DIGITAL_VOLUME_R,
 456                                 0, 255, 0, adc_pcm_tlv),
 457         SOC_DOUBLE_TLV("Capture Sidetone Volume",
 458                        WM8350_ADC_DIVIDER,
 459                        8, 4, 15, 1, capture_sd_tlv),
 460         SOC_WM8350_DOUBLE_R_TLV("Capture Volume",
 461                                 WM8350_LEFT_INPUT_VOLUME,
 462                                 WM8350_RIGHT_INPUT_VOLUME,
 463                                 2, 63, 0, pre_amp_tlv),
 464         SOC_DOUBLE_R("Capture ZC Switch",
 465                      WM8350_LEFT_INPUT_VOLUME,
 466                      WM8350_RIGHT_INPUT_VOLUME, 13, 1, 0),
 467         SOC_SINGLE_TLV("Left Input Left Sidetone Volume",
 468                        WM8350_OUTPUT_LEFT_MIXER_VOLUME, 1, 7, 0, out_mix_tlv),
 469         SOC_SINGLE_TLV("Left Input Right Sidetone Volume",
 470                        WM8350_OUTPUT_LEFT_MIXER_VOLUME,
 471                        5, 7, 0, out_mix_tlv),
 472         SOC_SINGLE_TLV("Left Input Bypass Volume",
 473                        WM8350_OUTPUT_LEFT_MIXER_VOLUME,
 474                        9, 7, 0, out_mix_tlv),
 475         SOC_SINGLE_TLV("Right Input Left Sidetone Volume",
 476                        WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
 477                        1, 7, 0, out_mix_tlv),
 478         SOC_SINGLE_TLV("Right Input Right Sidetone Volume",
 479                        WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
 480                        5, 7, 0, out_mix_tlv),
 481         SOC_SINGLE_TLV("Right Input Bypass Volume",
 482                        WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
 483                        13, 7, 0, out_mix_tlv),
 484         SOC_SINGLE("Left Input Mixer +20dB Switch",
 485                    WM8350_INPUT_MIXER_VOLUME_L, 0, 1, 0),
 486         SOC_SINGLE("Right Input Mixer +20dB Switch",
 487                    WM8350_INPUT_MIXER_VOLUME_R, 0, 1, 0),
 488         SOC_SINGLE_TLV("Out4 Capture Volume",
 489                        WM8350_INPUT_MIXER_VOLUME,
 490                        1, 7, 0, out_mix_tlv),
 491         SOC_WM8350_DOUBLE_R_TLV("Out1 Playback Volume",
 492                                 WM8350_LOUT1_VOLUME,
 493                                 WM8350_ROUT1_VOLUME,
 494                                 2, 63, 0, out_pga_tlv),
 495         SOC_DOUBLE_R("Out1 Playback ZC Switch",
 496                      WM8350_LOUT1_VOLUME,
 497                      WM8350_ROUT1_VOLUME, 13, 1, 0),
 498         SOC_WM8350_DOUBLE_R_TLV("Out2 Playback Volume",
 499                                 WM8350_LOUT2_VOLUME,
 500                                 WM8350_ROUT2_VOLUME,
 501                                 2, 63, 0, out_pga_tlv),
 502         SOC_DOUBLE_R("Out2 Playback ZC Switch", WM8350_LOUT2_VOLUME,
 503                      WM8350_ROUT2_VOLUME, 13, 1, 0),
 504         SOC_SINGLE("Out2 Right Invert Switch", WM8350_ROUT2_VOLUME, 10, 1, 0),
 505         SOC_SINGLE_TLV("Out2 Beep Volume", WM8350_BEEP_VOLUME,
 506                        5, 7, 0, out_mix_tlv),
 507
 508         SOC_DOUBLE_R("Out1 Playback Switch",
 509                      WM8350_LOUT1_VOLUME,
 510                      WM8350_ROUT1_VOLUME,
 511                      14, 1, 1),
 512         SOC_DOUBLE_R("Out2 Playback Switch",
 513                      WM8350_LOUT2_VOLUME,
 514                      WM8350_ROUT2_VOLUME,
 515                      14, 1, 1),
 516 };
 517
 518 /*
 519  * DAPM Controls
 520  */
 521
 522 /* Left Playback Mixer */
 523 static const struct snd_kcontrol_new wm8350_left_play_mixer_controls[] = {
 524         SOC_DAPM_SINGLE("Playback Switch",
 525                         WM8350_LEFT_MIXER_CONTROL, 11, 1, 0),
 526         SOC_DAPM_SINGLE("Left Bypass Switch",
 527                         WM8350_LEFT_MIXER_CONTROL, 2, 1, 0),
 528         SOC_DAPM_SINGLE("Right Playback Switch",
 529                         WM8350_LEFT_MIXER_CONTROL, 12, 1, 0),
 530         SOC_DAPM_SINGLE("Left Sidetone Switch",
 531                         WM8350_LEFT_MIXER_CONTROL, 0, 1, 0),
 532         SOC_DAPM_SINGLE("Right Sidetone Switch",
 533                         WM8350_LEFT_MIXER_CONTROL, 1, 1, 0),
 534 };
 535
 536 /* Right Playback Mixer */
 537 static const struct snd_kcontrol_new wm8350_right_play_mixer_controls[] = {
 538         SOC_DAPM_SINGLE("Playback Switch",
 539                         WM8350_RIGHT_MIXER_CONTROL, 12, 1, 0),
 540         SOC_DAPM_SINGLE("Right Bypass Switch",
 541                         WM8350_RIGHT_MIXER_CONTROL, 3, 1, 0),
 542         SOC_DAPM_SINGLE("Left Playback Switch",
 543                         WM8350_RIGHT_MIXER_CONTROL, 11, 1, 0),
 544         SOC_DAPM_SINGLE("Left Sidetone Switch",
 545                         WM8350_RIGHT_MIXER_CONTROL, 0, 1, 0),
 546         SOC_DAPM_SINGLE("Right Sidetone Switch",
 547                         WM8350_RIGHT_MIXER_CONTROL, 1, 1, 0),
 548 };
 549
 550 /* Out4 Mixer */
 551 static const struct snd_kcontrol_new wm8350_out4_mixer_controls[] = {
 552         SOC_DAPM_SINGLE("Right Playback Switch",
 553                         WM8350_OUT4_MIXER_CONTROL, 12, 1, 0),
 554         SOC_DAPM_SINGLE("Left Playback Switch",
 555                         WM8350_OUT4_MIXER_CONTROL, 11, 1, 0),
 556         SOC_DAPM_SINGLE("Right Capture Switch",
 557                         WM8350_OUT4_MIXER_CONTROL, 9, 1, 0),
 558         SOC_DAPM_SINGLE("Out3 Playback Switch",
 559                         WM8350_OUT4_MIXER_CONTROL, 2, 1, 0),
 560         SOC_DAPM_SINGLE("Right Mixer Switch",
 561                         WM8350_OUT4_MIXER_CONTROL, 1, 1, 0),
 562         SOC_DAPM_SINGLE("Left Mixer Switch",
 563                         WM8350_OUT4_MIXER_CONTROL, 0, 1, 0),
 564 };
 565
 566 /* Out3 Mixer */
 567 static const struct snd_kcontrol_new wm8350_out3_mixer_controls[] = {
 568         SOC_DAPM_SINGLE("Left Playback Switch",
 569                         WM8350_OUT3_MIXER_CONTROL, 11, 1, 0),
 570         SOC_DAPM_SINGLE("Left Capture Switch",
 571                         WM8350_OUT3_MIXER_CONTROL, 8, 1, 0),
 572         SOC_DAPM_SINGLE("Out4 Playback Switch",
 573                         WM8350_OUT3_MIXER_CONTROL, 3, 1, 0),
 574         SOC_DAPM_SINGLE("Left Mixer Switch",
 575                         WM8350_OUT3_MIXER_CONTROL, 0, 1, 0),
 576 };
 577
 578 /* Left Input Mixer */
 579 static const struct snd_kcontrol_new wm8350_left_capt_mixer_controls[] = {
 580         SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
 581                             WM8350_INPUT_MIXER_VOLUME_L, 1, 7, 0, out_mix_tlv),
 582         SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
 583                             WM8350_INPUT_MIXER_VOLUME_L, 9, 7, 0, out_mix_tlv),
 584         SOC_DAPM_SINGLE("PGA Capture Switch",
 585                         WM8350_LEFT_INPUT_VOLUME, 14, 1, 1),
 586 };
 587
 588 /* Right Input Mixer */
 589 static const struct snd_kcontrol_new wm8350_right_capt_mixer_controls[] = {
 590         SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
 591                             WM8350_INPUT_MIXER_VOLUME_R, 5, 7, 0, out_mix_tlv),
 592         SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
 593                             WM8350_INPUT_MIXER_VOLUME_R, 13, 7, 0, out_mix_tlv),
 594         SOC_DAPM_SINGLE("PGA Capture Switch",
 595                         WM8350_RIGHT_INPUT_VOLUME, 14, 1, 1),
 596 };
 597
 598 /* Left Mic Mixer */
 599 static const struct snd_kcontrol_new wm8350_left_mic_mixer_controls[] = {
 600         SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 1, 1, 0),
 601         SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 0, 1, 0),
 602         SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 2, 1, 0),
 603 };
 604
 605 /* Right Mic Mixer */
 606 static const struct snd_kcontrol_new wm8350_right_mic_mixer_controls[] = {
 607         SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 9, 1, 0),
 608         SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 8, 1, 0),
 609         SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 10, 1, 0),
 610 };
 611
 612 /* Beep Switch */
 613 static const struct snd_kcontrol_new wm8350_beep_switch_controls =
 614 SOC_DAPM_SINGLE("Switch", WM8350_BEEP_VOLUME, 15, 1, 1);
 615
 616 /* Out4 Capture Mux */
 617 static const struct snd_kcontrol_new wm8350_out4_capture_controls =
 618 SOC_DAPM_ENUM("Route", wm8350_enum[7]);
 619
 620 static const struct snd_soc_dapm_widget wm8350_dapm_widgets[] = {
 621
 622         SND_SOC_DAPM_PGA("IN3R PGA", WM8350_POWER_MGMT_2, 11, 0, NULL, 0),
 623         SND_SOC_DAPM_PGA("IN3L PGA", WM8350_POWER_MGMT_2, 10, 0, NULL, 0),
 624         SND_SOC_DAPM_PGA_E("Right Out2 PGA", WM8350_POWER_MGMT_3, 3, 0, NULL,
 625                            0, pga_event,
 626                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 627         SND_SOC_DAPM_PGA_E("Left Out2 PGA", WM8350_POWER_MGMT_3, 2, 0, NULL, 0,
 628                            pga_event,
 629                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 630         SND_SOC_DAPM_PGA_E("Right Out1 PGA", WM8350_POWER_MGMT_3, 1, 0, NULL,
 631                            0, pga_event,
 632                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 633         SND_SOC_DAPM_PGA_E("Left Out1 PGA", WM8350_POWER_MGMT_3, 0, 0, NULL, 0,
 634                            pga_event,
 635                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 636
 637         SND_SOC_DAPM_MIXER("Right Capture Mixer", WM8350_POWER_MGMT_2,
 638                            7, 0, &wm8350_right_capt_mixer_controls[0],
 639                            ARRAY_SIZE(wm8350_right_capt_mixer_controls)),
 640
 641         SND_SOC_DAPM_MIXER("Left Capture Mixer", WM8350_POWER_MGMT_2,
 642                            6, 0, &wm8350_left_capt_mixer_controls[0],
 643                            ARRAY_SIZE(wm8350_left_capt_mixer_controls)),
 644
 645         SND_SOC_DAPM_MIXER("Out4 Mixer", WM8350_POWER_MGMT_2, 5, 0,
 646                            &wm8350_out4_mixer_controls[0],
 647                            ARRAY_SIZE(wm8350_out4_mixer_controls)),
 648
 649         SND_SOC_DAPM_MIXER("Out3 Mixer", WM8350_POWER_MGMT_2, 4, 0,
 650                            &wm8350_out3_mixer_controls[0],
 651                            ARRAY_SIZE(wm8350_out3_mixer_controls)),
 652
 653         SND_SOC_DAPM_MIXER("Right Playback Mixer", WM8350_POWER_MGMT_2, 1, 0,
 654                            &wm8350_right_play_mixer_controls[0],
 655                            ARRAY_SIZE(wm8350_right_play_mixer_controls)),
 656
 657         SND_SOC_DAPM_MIXER("Left Playback Mixer", WM8350_POWER_MGMT_2, 0, 0,
 658                            &wm8350_left_play_mixer_controls[0],
 659                            ARRAY_SIZE(wm8350_left_play_mixer_controls)),
 660
 661         SND_SOC_DAPM_MIXER("Left Mic Mixer", WM8350_POWER_MGMT_2, 8, 0,
 662                            &wm8350_left_mic_mixer_controls[0],
 663                            ARRAY_SIZE(wm8350_left_mic_mixer_controls)),
 664
 665         SND_SOC_DAPM_MIXER("Right Mic Mixer", WM8350_POWER_MGMT_2, 9, 0,
 666                            &wm8350_right_mic_mixer_controls[0],
 667                            ARRAY_SIZE(wm8350_right_mic_mixer_controls)),
 668
 669         /* virtual mixer for Beep and Out2R */
 670         SND_SOC_DAPM_MIXER("Out2 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
 671
 672         SND_SOC_DAPM_SWITCH("Beep", WM8350_POWER_MGMT_3, 7, 0,
 673                             &wm8350_beep_switch_controls),
 674
 675         SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
 676                          WM8350_POWER_MGMT_4, 3, 0),
 677         SND_SOC_DAPM_ADC("Left ADC", "Left Capture",
 678                          WM8350_POWER_MGMT_4, 2, 0),
 679         SND_SOC_DAPM_DAC("Right DAC", "Right Playback",
 680                          WM8350_POWER_MGMT_4, 5, 0),
 681         SND_SOC_DAPM_DAC("Left DAC", "Left Playback",
 682                          WM8350_POWER_MGMT_4, 4, 0),
 683
 684         SND_SOC_DAPM_MICBIAS("Mic Bias", WM8350_POWER_MGMT_1, 4, 0),
 685
 686         SND_SOC_DAPM_MUX("Out4 Capture Channel", SND_SOC_NOPM, 0, 0,
 687                          &wm8350_out4_capture_controls),
 688
 689         SND_SOC_DAPM_OUTPUT("OUT1R"),
 690         SND_SOC_DAPM_OUTPUT("OUT1L"),
 691         SND_SOC_DAPM_OUTPUT("OUT2R"),
 692         SND_SOC_DAPM_OUTPUT("OUT2L"),
 693         SND_SOC_DAPM_OUTPUT("OUT3"),
 694         SND_SOC_DAPM_OUTPUT("OUT4"),
 695
 696         SND_SOC_DAPM_INPUT("IN1RN"),
 697         SND_SOC_DAPM_INPUT("IN1RP"),
 698         SND_SOC_DAPM_INPUT("IN2R"),
 699         SND_SOC_DAPM_INPUT("IN1LP"),
 700         SND_SOC_DAPM_INPUT("IN1LN"),
 701         SND_SOC_DAPM_INPUT("IN2L"),
 702         SND_SOC_DAPM_INPUT("IN3R"),
 703         SND_SOC_DAPM_INPUT("IN3L"),
 704 };
 705
 706 static const struct snd_soc_dapm_route audio_map[] = {
 707
 708         /* left playback mixer */
 709         {"Left Playback Mixer", "Playback Switch", "Left DAC"},
 710         {"Left Playback Mixer", "Left Bypass Switch", "IN3L PGA"},
 711         {"Left Playback Mixer", "Right Playback Switch", "Right DAC"},
 712         {"Left Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
 713         {"Left Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
 714
 715         /* right playback mixer */
 716         {"Right Playback Mixer", "Playback Switch", "Right DAC"},
 717         {"Right Playback Mixer", "Right Bypass Switch", "IN3R PGA"},
 718         {"Right Playback Mixer", "Left Playback Switch", "Left DAC"},
 719         {"Right Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
 720         {"Right Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
 721
 722         /* out4 playback mixer */
 723         {"Out4 Mixer", "Right Playback Switch", "Right DAC"},
 724         {"Out4 Mixer", "Left Playback Switch", "Left DAC"},
 725         {"Out4 Mixer", "Right Capture Switch", "Right Capture Mixer"},
 726         {"Out4 Mixer", "Out3 Playback Switch", "Out3 Mixer"},
 727         {"Out4 Mixer", "Right Mixer Switch", "Right Playback Mixer"},
 728         {"Out4 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
 729         {"OUT4", NULL, "Out4 Mixer"},
 730
 731         /* out3 playback mixer */
 732         {"Out3 Mixer", "Left Playback Switch", "Left DAC"},
 733         {"Out3 Mixer", "Left Capture Switch", "Left Capture Mixer"},
 734         {"Out3 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
 735         {"Out3 Mixer", "Out4 Playback Switch", "Out4 Mixer"},
 736         {"OUT3", NULL, "Out3 Mixer"},
 737
 738         /* out2 */
 739         {"Right Out2 PGA", NULL, "Right Playback Mixer"},
 740         {"Left Out2 PGA", NULL, "Left Playback Mixer"},
 741         {"OUT2L", NULL, "Left Out2 PGA"},
 742         {"OUT2R", NULL, "Right Out2 PGA"},
 743
 744         /* out1 */
 745         {"Right Out1 PGA", NULL, "Right Playback Mixer"},
 746         {"Left Out1 PGA", NULL, "Left Playback Mixer"},
 747         {"OUT1L", NULL, "Left Out1 PGA"},
 748         {"OUT1R", NULL, "Right Out1 PGA"},
 749
 750         /* ADCs */
 751         {"Left ADC", NULL, "Left Capture Mixer"},
 752         {"Right ADC", NULL, "Right Capture Mixer"},
 753
 754         /* Left capture mixer */
 755         {"Left Capture Mixer", "L2 Capture Volume", "IN2L"},
 756         {"Left Capture Mixer", "L3 Capture Volume", "IN3L PGA"},
 757         {"Left Capture Mixer", "PGA Capture Switch", "Left Mic Mixer"},
 758         {"Left Capture Mixer", NULL, "Out4 Capture Channel"},
 759
 760         /* Right capture mixer */
 761         {"Right Capture Mixer", "L2 Capture Volume", "IN2R"},
 762         {"Right Capture Mixer", "L3 Capture Volume", "IN3R PGA"},
 763         {"Right Capture Mixer", "PGA Capture Switch", "Right Mic Mixer"},
 764         {"Right Capture Mixer", NULL, "Out4 Capture Channel"},
 765
 766         /* L3 Inputs */
 767         {"IN3L PGA", NULL, "IN3L"},
 768         {"IN3R PGA", NULL, "IN3R"},
 769
 770         /* Left Mic mixer */
 771         {"Left Mic Mixer", "INN Capture Switch", "IN1LN"},
 772         {"Left Mic Mixer", "INP Capture Switch", "IN1LP"},
 773         {"Left Mic Mixer", "IN2 Capture Switch", "IN2L"},
 774
 775         /* Right Mic mixer */
 776         {"Right Mic Mixer", "INN Capture Switch", "IN1RN"},
 777         {"Right Mic Mixer", "INP Capture Switch", "IN1RP"},
 778         {"Right Mic Mixer", "IN2 Capture Switch", "IN2R"},
 779
 780         /* out 4 capture */
 781         {"Out4 Capture Channel", NULL, "Out4 Mixer"},
 782
 783         /* Beep */
 784         {"Beep", NULL, "IN3R PGA"},
 785 };
 786
 787 static int wm8350_add_widgets(struct snd_soc_codec *codec)
 788 {
 789         struct snd_soc_dapm_context *dapm = &codec->dapm;
 790         int ret;
 791
 792         ret = snd_soc_dapm_new_controls(dapm,
 793                                         wm8350_dapm_widgets,
 794                                         ARRAY_SIZE(wm8350_dapm_widgets));
 795         if (ret != 0) {
 796                 dev_err(codec->dev, "dapm control register failed\n");
 797                 return ret;
 798         }
 799
 800         /* set up audio paths */
 801         ret = snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
 802         if (ret != 0) {
 803                 dev_err(codec->dev, "DAPM route register failed\n");
 804                 return ret;
 805         }
 806
 807         return 0;
 808 }
 809
 810 static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 811                                  int clk_id, unsigned int freq, int dir)
 812 {
 813         struct snd_soc_codec *codec = codec_dai->codec;
 814         struct wm8350 *wm8350 = codec->control_data;
 815         u16 fll_4;
 816
 817         switch (clk_id) {
 818         case WM8350_MCLK_SEL_MCLK:
 819                 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_1,
 820                                   WM8350_MCLK_SEL);
 821                 break;
 822         case WM8350_MCLK_SEL_PLL_MCLK:
 823         case WM8350_MCLK_SEL_PLL_DAC:
 824         case WM8350_MCLK_SEL_PLL_ADC:
 825         case WM8350_MCLK_SEL_PLL_32K:
 826                 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_1,
 827                                 WM8350_MCLK_SEL);
 828                 fll_4 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_4) &
 829                     ~WM8350_FLL_CLK_SRC_MASK;
 830                 wm8350_codec_write(codec, WM8350_FLL_CONTROL_4, fll_4 | clk_id);
 831                 break;
 832         }
 833
 834         /* MCLK direction */
 835         if (dir == SND_SOC_CLOCK_OUT)
 836                 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2,
 837                                 WM8350_MCLK_DIR);
 838         else
 839                 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_2,
 840                                   WM8350_MCLK_DIR);
 841
 842         return 0;
 843 }
 844
 845 static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div)
 846 {
 847         struct snd_soc_codec *codec = codec_dai->codec;
 848         u16 val;
 849
 850         switch (div_id) {
 851         case WM8350_ADC_CLKDIV:
 852                 val = wm8350_codec_read(codec, WM8350_ADC_DIVIDER) &
 853                     ~WM8350_ADC_CLKDIV_MASK;
 854                 wm8350_codec_write(codec, WM8350_ADC_DIVIDER, val | div);
 855                 break;
 856         case WM8350_DAC_CLKDIV:
 857                 val = wm8350_codec_read(codec, WM8350_DAC_CLOCK_CONTROL) &
 858                     ~WM8350_DAC_CLKDIV_MASK;
 859                 wm8350_codec_write(codec, WM8350_DAC_CLOCK_CONTROL, val | div);
 860                 break;
 861         case WM8350_BCLK_CLKDIV:
 862                 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) &
 863                     ~WM8350_BCLK_DIV_MASK;
 864                 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
 865                 break;
 866         case WM8350_OPCLK_CLKDIV:
 867                 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) &
 868                     ~WM8350_OPCLK_DIV_MASK;
 869                 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
 870                 break;
 871         case WM8350_SYS_CLKDIV:
 872                 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) &
 873                     ~WM8350_MCLK_DIV_MASK;
 874                 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
 875                 break;
 876         case WM8350_DACLR_CLKDIV:
 877                 val = wm8350_codec_read(codec, WM8350_DAC_LR_RATE) &
 878                     ~WM8350_DACLRC_RATE_MASK;
 879                 wm8350_codec_write(codec, WM8350_DAC_LR_RATE, val | div);
 880                 break;
 881         case WM8350_ADCLR_CLKDIV:
 882                 val = wm8350_codec_read(codec, WM8350_ADC_LR_RATE) &
 883                     ~WM8350_ADCLRC_RATE_MASK;
 884                 wm8350_codec_write(codec, WM8350_ADC_LR_RATE, val | div);
 885                 break;
 886         default:
 887                 return -EINVAL;
 888         }
 889
 890         return 0;
 891 }
 892
 893 static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 894 {
 895         struct snd_soc_codec *codec = codec_dai->codec;
 896         u16 iface = wm8350_codec_read(codec, WM8350_AI_FORMATING) &
 897             ~(WM8350_AIF_BCLK_INV | WM8350_AIF_LRCLK_INV | WM8350_AIF_FMT_MASK);
 898         u16 master = wm8350_codec_read(codec, WM8350_AI_DAC_CONTROL) &
 899             ~WM8350_BCLK_MSTR;
 900         u16 dac_lrc = wm8350_codec_read(codec, WM8350_DAC_LR_RATE) &
 901             ~WM8350_DACLRC_ENA;
 902         u16 adc_lrc = wm8350_codec_read(codec, WM8350_ADC_LR_RATE) &
 903             ~WM8350_ADCLRC_ENA;
 904
 905         /* set master/slave audio interface */
 906         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 907         case SND_SOC_DAIFMT_CBM_CFM:
 908                 master |= WM8350_BCLK_MSTR;
 909                 dac_lrc |= WM8350_DACLRC_ENA;
 910                 adc_lrc |= WM8350_ADCLRC_ENA;
 911                 break;
 912         case SND_SOC_DAIFMT_CBS_CFS:
 913                 break;
 914         default:
 915                 return -EINVAL;
 916         }
 917
 918         /* interface format */
 919         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 920         case SND_SOC_DAIFMT_I2S:
 921                 iface |= 0x2 << 8;
 922                 break;
 923         case SND_SOC_DAIFMT_RIGHT_J:
 924                 break;
 925         case SND_SOC_DAIFMT_LEFT_J:
 926                 iface |= 0x1 << 8;
 927                 break;
 928         case SND_SOC_DAIFMT_DSP_A:
 929                 iface |= 0x3 << 8;
 930                 break;
 931         case SND_SOC_DAIFMT_DSP_B:
 932                 iface |= 0x3 << 8 | WM8350_AIF_LRCLK_INV;
 933                 break;
 934         default:
 935                 return -EINVAL;
 936         }
 937
 938         /* clock inversion */
 939         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 940         case SND_SOC_DAIFMT_NB_NF:
 941                 break;
 942         case SND_SOC_DAIFMT_IB_IF:
 943                 iface |= WM8350_AIF_LRCLK_INV | WM8350_AIF_BCLK_INV;
 944                 break;
 945         case SND_SOC_DAIFMT_IB_NF:
 946                 iface |= WM8350_AIF_BCLK_INV;
 947                 break;
 948         case SND_SOC_DAIFMT_NB_IF:
 949                 iface |= WM8350_AIF_LRCLK_INV;
 950                 break;
 951         default:
 952                 return -EINVAL;
 953         }
 954
 955         wm8350_codec_write(codec, WM8350_AI_FORMATING, iface);
 956         wm8350_codec_write(codec, WM8350_AI_DAC_CONTROL, master);
 957         wm8350_codec_write(codec, WM8350_DAC_LR_RATE, dac_lrc);
 958         wm8350_codec_write(codec, WM8350_ADC_LR_RATE, adc_lrc);
 959         return 0;
 960 }
 961
 962 static int wm8350_pcm_trigger(struct snd_pcm_substream *substream,
 963                               int cmd, struct snd_soc_dai *codec_dai)
 964 {
 965         struct snd_soc_codec *codec = codec_dai->codec;
 966         int master = wm8350_codec_cache_read(codec, WM8350_AI_DAC_CONTROL) &
 967             WM8350_BCLK_MSTR;
 968         int enabled = 0;
 969
 970         /* Check that the DACs or ADCs are enabled since they are
 971          * required for LRC in master mode. The DACs or ADCs need a
 972          * valid audio path i.e. pin -> ADC or DAC -> pin before
 973          * the LRC will be enabled in master mode. */
 974         if (!master || cmd != SNDRV_PCM_TRIGGER_START)
 975                 return 0;
 976
 977         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 978                 enabled = wm8350_codec_cache_read(codec, WM8350_POWER_MGMT_4) &
 979                     (WM8350_ADCR_ENA | WM8350_ADCL_ENA);
 980         } else {
 981                 enabled = wm8350_codec_cache_read(codec, WM8350_POWER_MGMT_4) &
 982                     (WM8350_DACR_ENA | WM8350_DACL_ENA);
 983         }
 984
 985         if (!enabled) {
 986                 dev_err(codec->dev,
 987                        "%s: invalid audio path - no clocks available\n",
 988                        __func__);
 989                 return -EINVAL;
 990         }
 991         return 0;
 992 }
 993
 994 static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream,
 995                                 struct snd_pcm_hw_params *params,
 996                                 struct snd_soc_dai *codec_dai)
 997 {
 998         struct snd_soc_codec *codec = codec_dai->codec;
 999         struct wm8350 *wm8350 = codec->control_data;
1000         u16 iface = wm8350_codec_read(codec, WM8350_AI_FORMATING) &
1001             ~WM8350_AIF_WL_MASK;
1002
1003         /* bit size */
1004         switch (params_format(params)) {
1005         case SNDRV_PCM_FORMAT_S16_LE:
1006                 break;
1007         case SNDRV_PCM_FORMAT_S20_3LE:
1008                 iface |= 0x1 << 10;
1009                 break;
1010         case SNDRV_PCM_FORMAT_S24_LE:
1011                 iface |= 0x2 << 10;
1012                 break;
1013         case SNDRV_PCM_FORMAT_S32_LE:
1014                 iface |= 0x3 << 10;
1015                 break;
1016         }
1017
1018         wm8350_codec_write(codec, WM8350_AI_FORMATING, iface);
1019
1020         /* The sloping stopband filter is recommended for use with
1021          * lower sample rates to improve performance.
1022          */
1023         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1024                 if (params_rate(params) < 24000)
1025                         wm8350_set_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
1026                                         WM8350_DAC_SB_FILT);
1027                 else
1028                         wm8350_clear_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
1029                                           WM8350_DAC_SB_FILT);
1030         }
1031
1032         return 0;
1033 }
1034
1035 static int wm8350_mute(struct snd_soc_dai *dai, int mute)
1036 {
1037         struct snd_soc_codec *codec = dai->codec;
1038         struct wm8350 *wm8350 = codec->control_data;
1039
1040         if (mute)
1041                 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
1042         else
1043                 wm8350_clear_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
1044         return 0;
1045 }
1046
1047 /* FLL divisors */
1048 struct _fll_div {
1049         int div;                /* FLL_OUTDIV */
1050         int n;
1051         int k;
1052         int ratio;              /* FLL_FRATIO */
1053 };
1054
1055 /* The size in bits of the fll divide multiplied by 10
1056  * to allow rounding later */
1057 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1058
1059 static inline int fll_factors(struct _fll_div *fll_div, unsigned int input,
1060                               unsigned int output)
1061 {
1062         u64 Kpart;
1063         unsigned int t1, t2, K, Nmod;
1064
1065         if (output >= 2815250 && output <= 3125000)
1066                 fll_div->div = 0x4;
1067         else if (output >= 5625000 && output <= 6250000)
1068                 fll_div->div = 0x3;
1069         else if (output >= 11250000 && output <= 12500000)
1070                 fll_div->div = 0x2;
1071         else if (output >= 22500000 && output <= 25000000)
1072                 fll_div->div = 0x1;
1073         else {
1074                 printk(KERN_ERR "wm8350: fll freq %d out of range\n", output);
1075                 return -EINVAL;
1076         }
1077
1078         if (input > 48000)
1079                 fll_div->ratio = 1;
1080         else
1081                 fll_div->ratio = 8;
1082
1083         t1 = output * (1 << (fll_div->div + 1));
1084         t2 = input * fll_div->ratio;
1085
1086         fll_div->n = t1 / t2;
1087         Nmod = t1 % t2;
1088
1089         if (Nmod) {
1090                 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1091                 do_div(Kpart, t2);
1092                 K = Kpart & 0xFFFFFFFF;
1093
1094                 /* Check if we need to round */
1095                 if ((K % 10) >= 5)
1096                         K += 5;
1097
1098                 /* Move down to proper range now rounding is done */
1099                 K /= 10;
1100                 fll_div->k = K;
1101         } else
1102                 fll_div->k = 0;
1103
1104         return 0;
1105 }
1106
1107 static int wm8350_set_fll(struct snd_soc_dai *codec_dai,
1108                           int pll_id, int source, unsigned int freq_in,
1109                           unsigned int freq_out)
1110 {
1111         struct snd_soc_codec *codec = codec_dai->codec;
1112         struct wm8350 *wm8350 = codec->control_data;
1113         struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1114         struct _fll_div fll_div;
1115         int ret = 0;
1116         u16 fll_1, fll_4;
1117
1118         if (freq_in == priv->fll_freq_in && freq_out == priv->fll_freq_out)
1119                 return 0;
1120
1121         /* power down FLL - we need to do this for reconfiguration */
1122         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1123                           WM8350_FLL_ENA | WM8350_FLL_OSC_ENA);
1124
1125         if (freq_out == 0 || freq_in == 0)
1126                 return ret;
1127
1128         ret = fll_factors(&fll_div, freq_in, freq_out);
1129         if (ret < 0)
1130                 return ret;
1131         dev_dbg(wm8350->dev,
1132                 "FLL in %u FLL out %u N 0x%x K 0x%x div %d ratio %d",
1133                 freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div,
1134                 fll_div.ratio);
1135
1136         /* set up N.K & dividers */
1137         fll_1 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_1) &
1138             ~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000);
1139         wm8350_codec_write(codec, WM8350_FLL_CONTROL_1,
1140                            fll_1 | (fll_div.div << 8) | 0x50);
1141         wm8350_codec_write(codec, WM8350_FLL_CONTROL_2,
1142                            (fll_div.ratio << 11) | (fll_div.
1143                                                     n & WM8350_FLL_N_MASK));
1144         wm8350_codec_write(codec, WM8350_FLL_CONTROL_3, fll_div.k);
1145         fll_4 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_4) &
1146             ~(WM8350_FLL_FRAC | WM8350_FLL_SLOW_LOCK_REF);
1147         wm8350_codec_write(codec, WM8350_FLL_CONTROL_4,
1148                            fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) |
1149                            (fll_div.ratio == 8 ? WM8350_FLL_SLOW_LOCK_REF : 0));
1150
1151         /* power FLL on */
1152         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_OSC_ENA);
1153         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_ENA);
1154
1155         priv->fll_freq_out = freq_out;
1156         priv->fll_freq_in = freq_in;
1157
1158         return 0;
1159 }
1160
1161 static int wm8350_set_bias_level(struct snd_soc_codec *codec,
1162                                  enum snd_soc_bias_level level)
1163 {
1164         struct wm8350 *wm8350 = codec->control_data;
1165         struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1166         struct wm8350_audio_platform_data *platform =
1167                 wm8350->codec.platform_data;
1168         u16 pm1;
1169         int ret;
1170
1171         switch (level) {
1172         case SND_SOC_BIAS_ON:
1173                 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1174                     ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1175                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1176                                  pm1 | WM8350_VMID_50K |
1177                                  platform->codec_current_on << 14);
1178                 break;
1179
1180         case SND_SOC_BIAS_PREPARE:
1181                 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1);
1182                 pm1 &= ~WM8350_VMID_MASK;
1183                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1184                                  pm1 | WM8350_VMID_50K);
1185                 break;
1186
1187         case SND_SOC_BIAS_STANDBY:
1188                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1189                         ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies),
1190                                                     priv->supplies);
1191                         if (ret != 0)
1192                                 return ret;
1193
1194                         /* Enable the system clock */
1195                         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4,
1196                                         WM8350_SYSCLK_ENA);
1197
1198                         /* mute DAC & outputs */
1199                         wm8350_set_bits(wm8350, WM8350_DAC_MUTE,
1200                                         WM8350_DAC_MUTE_ENA);
1201
1202                         /* discharge cap memory */
1203                         wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1204                                          platform->dis_out1 |
1205                                          (platform->dis_out2 << 2) |
1206                                          (platform->dis_out3 << 4) |
1207                                          (platform->dis_out4 << 6));
1208
1209                         /* wait for discharge */
1210                         schedule_timeout_interruptible(msecs_to_jiffies
1211                                                        (platform->
1212                                                         cap_discharge_msecs));
1213
1214                         /* enable antipop */
1215                         wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1216                                          (platform->vmid_s_curve << 8));
1217
1218                         /* ramp up vmid */
1219                         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1220                                          (platform->
1221                                           codec_current_charge << 14) |
1222                                          WM8350_VMID_5K | WM8350_VMIDEN |
1223                                          WM8350_VBUFEN);
1224
1225                         /* wait for vmid */
1226                         schedule_timeout_interruptible(msecs_to_jiffies
1227                                                        (platform->
1228                                                         vmid_charge_msecs));
1229
1230                         /* turn on vmid 300k  */
1231                         pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1232                             ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1233                         pm1 |= WM8350_VMID_300K |
1234                                 (platform->codec_current_standby << 14);
1235                         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1236                                          pm1);
1237
1238
1239                         /* enable analogue bias */
1240                         pm1 |= WM8350_BIASEN;
1241                         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1242
1243                         /* disable antipop */
1244                         wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1245
1246                 } else {
1247                         /* turn on vmid 300k and reduce current */
1248                         pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1249                             ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1250                         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1251                                          pm1 | WM8350_VMID_300K |
1252                                          (platform->
1253                                           codec_current_standby << 14));
1254
1255                 }
1256                 break;
1257
1258         case SND_SOC_BIAS_OFF:
1259
1260                 /* mute DAC & enable outputs */
1261                 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
1262
1263                 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_3,
1264                                 WM8350_OUT1L_ENA | WM8350_OUT1R_ENA |
1265                                 WM8350_OUT2L_ENA | WM8350_OUT2R_ENA);
1266
1267                 /* enable anti pop S curve */
1268                 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1269                                  (platform->vmid_s_curve << 8));
1270
1271                 /* turn off vmid  */
1272                 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1273                     ~WM8350_VMIDEN;
1274                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1275
1276                 /* wait */
1277                 schedule_timeout_interruptible(msecs_to_jiffies
1278                                                (platform->
1279                                                 vmid_discharge_msecs));
1280
1281                 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1282                                  (platform->vmid_s_curve << 8) |
1283                                  platform->dis_out1 |
1284                                  (platform->dis_out2 << 2) |
1285                                  (platform->dis_out3 << 4) |
1286                                  (platform->dis_out4 << 6));
1287
1288                 /* turn off VBuf and drain */
1289                 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1290                     ~(WM8350_VBUFEN | WM8350_VMID_MASK);
1291                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1292                                  pm1 | WM8350_OUTPUT_DRAIN_EN);
1293
1294                 /* wait */
1295                 schedule_timeout_interruptible(msecs_to_jiffies
1296                                                (platform->drain_msecs));
1297
1298                 pm1 &= ~WM8350_BIASEN;
1299                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1300
1301                 /* disable anti-pop */
1302                 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1303
1304                 wm8350_clear_bits(wm8350, WM8350_LOUT1_VOLUME,
1305                                   WM8350_OUT1L_ENA);
1306                 wm8350_clear_bits(wm8350, WM8350_ROUT1_VOLUME,
1307                                   WM8350_OUT1R_ENA);
1308                 wm8350_clear_bits(wm8350, WM8350_LOUT2_VOLUME,
1309                                   WM8350_OUT2L_ENA);
1310                 wm8350_clear_bits(wm8350, WM8350_ROUT2_VOLUME,
1311                                   WM8350_OUT2R_ENA);
1312
1313                 /* disable clock gen */
1314                 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1315                                   WM8350_SYSCLK_ENA);
1316
1317                 regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
1318                                        priv->supplies);
1319                 break;
1320         }
1321         codec->dapm.bias_level = level;
1322         return 0;
1323 }
1324
1325 static int wm8350_suspend(struct snd_soc_codec *codec, pm_message_t state)
1326 {
1327         wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF);
1328         return 0;
1329 }
1330
1331 static int wm8350_resume(struct snd_soc_codec *codec)
1332 {
1333         wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1334
1335         return 0;
1336 }
1337
1338 static irqreturn_t wm8350_hp_jack_handler(int irq, void *data)
1339 {
1340         struct wm8350_data *priv = data;
1341         struct wm8350 *wm8350 = priv->codec.control_data;
1342         u16 reg;
1343         int report;
1344         int mask;
1345         struct wm8350_jack_data *jack = NULL;
1346
1347         switch (irq - wm8350->irq_base) {
1348         case WM8350_IRQ_CODEC_JCK_DET_L:
1349                 jack = &priv->hpl;
1350                 mask = WM8350_JACK_L_LVL;
1351                 break;
1352
1353         case WM8350_IRQ_CODEC_JCK_DET_R:
1354                 jack = &priv->hpr;
1355                 mask = WM8350_JACK_R_LVL;
1356                 break;
1357
1358         default:
1359                 BUG();
1360         }
1361
1362         if (!jack->jack) {
1363                 dev_warn(wm8350->dev, "Jack interrupt called with no jack\n");
1364                 return IRQ_NONE;
1365         }
1366
1367         /* Debounce */
1368         msleep(200);
1369
1370         reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1371         if (reg & mask)
1372                 report = jack->report;
1373         else
1374                 report = 0;
1375
1376         snd_soc_jack_report(jack->jack, report, jack->report);
1377
1378         return IRQ_HANDLED;
1379 }
1380
1381 /**
1382  * wm8350_hp_jack_detect - Enable headphone jack detection.
1383  *
1384  * @codec:  WM8350 codec
1385  * @which:  left or right jack detect signal
1386  * @jack:   jack to report detection events on
1387  * @report: value to report
1388  *
1389  * Enables the headphone jack detection of the WM8350.  If no report
1390  * is specified then detection is disabled.
1391  */
1392 int wm8350_hp_jack_detect(struct snd_soc_codec *codec, enum wm8350_jack which,
1393                           struct snd_soc_jack *jack, int report)
1394 {
1395         struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1396         struct wm8350 *wm8350 = codec->control_data;
1397         int irq;
1398         int ena;
1399
1400         switch (which) {
1401         case WM8350_JDL:
1402                 priv->hpl.jack = jack;
1403                 priv->hpl.report = report;
1404                 irq = WM8350_IRQ_CODEC_JCK_DET_L;
1405                 ena = WM8350_JDL_ENA;
1406                 break;
1407
1408         case WM8350_JDR:
1409                 priv->hpr.jack = jack;
1410                 priv->hpr.report = report;
1411                 irq = WM8350_IRQ_CODEC_JCK_DET_R;
1412                 ena = WM8350_JDR_ENA;
1413                 break;
1414
1415         default:
1416                 return -EINVAL;
1417         }
1418
1419         if (report) {
1420                 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1421                 wm8350_set_bits(wm8350, WM8350_JACK_DETECT, ena);
1422         } else {
1423                 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, ena);
1424         }
1425
1426         /* Sync status */
1427         wm8350_hp_jack_handler(irq + wm8350->irq_base, priv);
1428
1429         return 0;
1430 }
1431 EXPORT_SYMBOL_GPL(wm8350_hp_jack_detect);
1432
1433 static irqreturn_t wm8350_mic_handler(int irq, void *data)
1434 {
1435         struct wm8350_data *priv = data;
1436         struct wm8350 *wm8350 = priv->codec.control_data;
1437         u16 reg;
1438         int report = 0;
1439
1440         reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1441         if (reg & WM8350_JACK_MICSCD_LVL)
1442                 report |= priv->mic.short_report;
1443         if (reg & WM8350_JACK_MICSD_LVL)
1444                 report |= priv->mic.report;
1445
1446         snd_soc_jack_report(priv->mic.jack, report,
1447                             priv->mic.report | priv->mic.short_report);
1448
1449         return IRQ_HANDLED;
1450 }
1451
1452 /**
1453  * wm8350_mic_jack_detect - Enable microphone jack detection.
1454  *
1455  * @codec:         WM8350 codec
1456  * @jack:          jack to report detection events on
1457  * @detect_report: value to report when presence detected
1458  * @short_report:  value to report when microphone short detected
1459  *
1460  * Enables the microphone jack detection of the WM8350.  If both reports
1461  * are specified as zero then detection is disabled.
1462  */
1463 int wm8350_mic_jack_detect(struct snd_soc_codec *codec,
1464                            struct snd_soc_jack *jack,
1465                            int detect_report, int short_report)
1466 {
1467         struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1468         struct wm8350 *wm8350 = codec->control_data;
1469
1470         priv->mic.jack = jack;
1471         priv->mic.report = detect_report;
1472         priv->mic.short_report = short_report;
1473
1474         if (detect_report || short_report) {
1475                 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1476                 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_1,
1477                                 WM8350_MIC_DET_ENA);
1478         } else {
1479                 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_1,
1480                                   WM8350_MIC_DET_ENA);
1481         }
1482
1483         return 0;
1484 }
1485 EXPORT_SYMBOL_GPL(wm8350_mic_jack_detect);
1486
1487 #define WM8350_RATES (SNDRV_PCM_RATE_8000_96000)
1488
1489 #define WM8350_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1490                         SNDRV_PCM_FMTBIT_S20_3LE |\
1491                         SNDRV_PCM_FMTBIT_S24_LE)
1492
1493 static struct snd_soc_dai_ops wm8350_dai_ops = {
1494          .hw_params     = wm8350_pcm_hw_params,
1495          .digital_mute  = wm8350_mute,
1496          .trigger       = wm8350_pcm_trigger,
1497          .set_fmt       = wm8350_set_dai_fmt,
1498          .set_sysclk    = wm8350_set_dai_sysclk,
1499          .set_pll       = wm8350_set_fll,
1500          .set_clkdiv    = wm8350_set_clkdiv,
1501 };
1502
1503 static struct snd_soc_dai_driver wm8350_dai = {
1504         .name = "wm8350-hifi",
1505         .playback = {
1506                 .stream_name = "Playback",
1507                 .channels_min = 1,
1508                 .channels_max = 2,
1509                 .rates = WM8350_RATES,
1510                 .formats = WM8350_FORMATS,
1511         },
1512         .capture = {
1513                  .stream_name = "Capture",
1514                  .channels_min = 1,
1515                  .channels_max = 2,
1516                  .rates = WM8350_RATES,
1517                  .formats = WM8350_FORMATS,
1518          },
1519         .ops = &wm8350_dai_ops,
1520 };
1521
1522 static  int wm8350_codec_probe(struct snd_soc_codec *codec)
1523 {
1524         struct wm8350 *wm8350 = dev_get_platdata(codec->dev);
1525         struct wm8350_data *priv;
1526         struct wm8350_output *out1;
1527         struct wm8350_output *out2;
1528         int ret, i;
1529
1530         if (wm8350->codec.platform_data == NULL) {
1531                 dev_err(codec->dev, "No audio platform data supplied\n");
1532                 return -EINVAL;
1533         }
1534
1535         priv = kzalloc(sizeof(struct wm8350_data), GFP_KERNEL);
1536         if (priv == NULL)
1537                 return -ENOMEM;
1538         snd_soc_codec_set_drvdata(codec, priv);
1539
1540         for (i = 0; i < ARRAY_SIZE(supply_names); i++)
1541                 priv->supplies[i].supply = supply_names[i];
1542
1543         ret = regulator_bulk_get(wm8350->dev, ARRAY_SIZE(priv->supplies),
1544                                  priv->supplies);
1545         if (ret != 0)
1546                 goto err_priv;
1547
1548         wm8350->codec.codec = codec;
1549         codec->control_data = wm8350;
1550
1551         /* Put the codec into reset if it wasn't already */
1552         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1553
1554         INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8350_pga_work);
1555
1556         /* Enable the codec */
1557         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1558
1559         /* Enable robust clocking mode in ADC */
1560         wm8350_codec_write(codec, WM8350_SECURITY, 0xa7);
1561         wm8350_codec_write(codec, 0xde, 0x13);
1562         wm8350_codec_write(codec, WM8350_SECURITY, 0);
1563
1564         /* read OUT1 & OUT2 volumes */
1565         out1 = &priv->out1;
1566         out2 = &priv->out2;
1567         out1->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME) &
1568                           WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1569         out1->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME) &
1570                            WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1571         out2->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME) &
1572                           WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1573         out2->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME) &
1574                            WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1575         wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 0);
1576         wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 0);
1577         wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 0);
1578         wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 0);
1579
1580         /* Latch VU bits & mute */
1581         wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME,
1582                         WM8350_OUT1_VU | WM8350_OUT1L_MUTE);
1583         wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME,
1584                         WM8350_OUT2_VU | WM8350_OUT2L_MUTE);
1585         wm8350_set_bits(wm8350, WM8350_ROUT1_VOLUME,
1586                         WM8350_OUT1_VU | WM8350_OUT1R_MUTE);
1587         wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME,
1588                         WM8350_OUT2_VU | WM8350_OUT2R_MUTE);
1589
1590         /* Make sure AIF tristating is disabled by default */
1591         wm8350_clear_bits(wm8350, WM8350_AI_FORMATING, WM8350_AIF_TRI);
1592
1593         /* Make sure we've got a sane companding setup too */
1594         wm8350_clear_bits(wm8350, WM8350_ADC_DAC_COMP,
1595                           WM8350_DAC_COMP | WM8350_LOOPBACK);
1596
1597         /* Make sure jack detect is disabled to start off with */
1598         wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1599                           WM8350_JDL_ENA | WM8350_JDR_ENA);
1600
1601         wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L,
1602                             wm8350_hp_jack_handler, 0, "Left jack detect",
1603                             priv);
1604         wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R,
1605                             wm8350_hp_jack_handler, 0, "Right jack detect",
1606                             priv);
1607         wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICSCD,
1608                             wm8350_mic_handler, 0, "Microphone short", priv);
1609         wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICD,
1610                             wm8350_mic_handler, 0, "Microphone detect", priv);
1611
1612
1613         snd_soc_add_controls(codec, wm8350_snd_controls,
1614                                 ARRAY_SIZE(wm8350_snd_controls));
1615         wm8350_add_widgets(codec);
1616
1617         wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1618
1619         return 0;
1620
1621 err_priv:
1622         kfree(priv);
1623         return ret;
1624 }
1625
1626 static int  wm8350_codec_remove(struct snd_soc_codec *codec)
1627 {
1628         struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1629         struct wm8350 *wm8350 = dev_get_platdata(codec->dev);
1630
1631         wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1632                           WM8350_JDL_ENA | WM8350_JDR_ENA);
1633         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1634
1635         wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICD, priv);
1636         wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, priv);
1637         wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv);
1638         wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv);
1639
1640         priv->hpl.jack = NULL;
1641         priv->hpr.jack = NULL;
1642         priv->mic.jack = NULL;
1643
1644         /* if there was any work waiting then we run it now and
1645          * wait for its completion */
1646         flush_delayed_work_sync(&codec->delayed_work);
1647
1648         wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF);
1649
1650         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1651
1652         regulator_bulk_free(ARRAY_SIZE(priv->supplies), priv->supplies);
1653         kfree(priv);
1654         return 0;
1655 }
1656
1657 static struct snd_soc_codec_driver soc_codec_dev_wm8350 = {
1658         .probe =        wm8350_codec_probe,
1659         .remove =       wm8350_codec_remove,
1660         .suspend =      wm8350_suspend,
1661         .resume =       wm8350_resume,
1662         .read = wm8350_codec_read,
1663         .write = wm8350_codec_write,
1664         .set_bias_level = wm8350_set_bias_level,
1665 };
1666
1667 static int __devinit wm8350_probe(struct platform_device *pdev)
1668 {
1669         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8350,
1670                         &wm8350_dai, 1);
1671 }
1672
1673 static int __devexit wm8350_remove(struct platform_device *pdev)
1674 {
1675         snd_soc_unregister_codec(&pdev->dev);
1676         return 0;
1677 }
1678
1679 static struct platform_driver wm8350_codec_driver = {
1680         .driver = {
1681                    .name = "wm8350-codec",
1682                    .owner = THIS_MODULE,
1683                    },
1684         .probe = wm8350_probe,
1685         .remove = __devexit_p(wm8350_remove),
1686 };
1687
1688 static __init int wm8350_init(void)
1689 {
1690         return platform_driver_register(&wm8350_codec_driver);
1691 }
1692 module_init(wm8350_init);
1693
1694 static __exit void wm8350_exit(void)
1695 {
1696         platform_driver_unregister(&wm8350_codec_driver);
1697 }
1698 module_exit(wm8350_exit);
1699
1700 MODULE_DESCRIPTION("ASoC WM8350 driver");
1701 MODULE_AUTHOR("Liam Girdwood");
1702 MODULE_LICENSE("GPL");
1703 MODULE_ALIAS("platform:wm8350-codec");