sound/soc/codecs/wm8993.c

   1 /*
   2  * wm8993.c -- WM8993 ALSA SoC audio driver
   3  *
   4  * Copyright 2009, 2010 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15 #include <linux/init.h>
  16 #include <linux/delay.h>
  17 #include <linux/pm.h>
  18 #include <linux/i2c.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/slab.h>
  22 #include <sound/core.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/tlv.h>
  26 #include <sound/soc.h>
  27 #include <sound/soc-dapm.h>
  28 #include <sound/initval.h>
  29 #include <sound/wm8993.h>
  30
  31 #include "wm8993.h"
  32 #include "wm_hubs.h"
  33
  34 #define WM8993_NUM_SUPPLIES 6
  35 static const char *wm8993_supply_names[WM8993_NUM_SUPPLIES] = {
  36         "DCVDD",
  37         "DBVDD",
  38         "AVDD1",
  39         "AVDD2",
  40         "CPVDD",
  41         "SPKVDD",
  42 };
  43
  44 static u16 wm8993_reg_defaults[WM8993_REGISTER_COUNT] = {
  45         0x8993,     /* R0   - Software Reset */
  46         0x0000,     /* R1   - Power Management (1) */
  47         0x6000,     /* R2   - Power Management (2) */
  48         0x0000,     /* R3   - Power Management (3) */
  49         0x4050,     /* R4   - Audio Interface (1) */
  50         0x4000,     /* R5   - Audio Interface (2) */
  51         0x01C8,     /* R6   - Clocking 1 */
  52         0x0000,     /* R7   - Clocking 2 */
  53         0x0000,     /* R8   - Audio Interface (3) */
  54         0x0040,     /* R9   - Audio Interface (4) */
  55         0x0004,     /* R10  - DAC CTRL */
  56         0x00C0,     /* R11  - Left DAC Digital Volume */
  57         0x00C0,     /* R12  - Right DAC Digital Volume */
  58         0x0000,     /* R13  - Digital Side Tone */
  59         0x0300,     /* R14  - ADC CTRL */
  60         0x00C0,     /* R15  - Left ADC Digital Volume */
  61         0x00C0,     /* R16  - Right ADC Digital Volume */
  62         0x0000,     /* R17 */
  63         0x0000,     /* R18  - GPIO CTRL 1 */
  64         0x0010,     /* R19  - GPIO1 */
  65         0x0000,     /* R20  - IRQ_DEBOUNCE */
  66         0x0000,     /* R21 */
  67         0x8000,     /* R22  - GPIOCTRL 2 */
  68         0x0800,     /* R23  - GPIO_POL */
  69         0x008B,     /* R24  - Left Line Input 1&2 Volume */
  70         0x008B,     /* R25  - Left Line Input 3&4 Volume */
  71         0x008B,     /* R26  - Right Line Input 1&2 Volume */
  72         0x008B,     /* R27  - Right Line Input 3&4 Volume */
  73         0x006D,     /* R28  - Left Output Volume */
  74         0x006D,     /* R29  - Right Output Volume */
  75         0x0066,     /* R30  - Line Outputs Volume */
  76         0x0020,     /* R31  - HPOUT2 Volume */
  77         0x0079,     /* R32  - Left OPGA Volume */
  78         0x0079,     /* R33  - Right OPGA Volume */
  79         0x0003,     /* R34  - SPKMIXL Attenuation */
  80         0x0003,     /* R35  - SPKMIXR Attenuation */
  81         0x0011,     /* R36  - SPKOUT Mixers */
  82         0x0100,     /* R37  - SPKOUT Boost */
  83         0x0079,     /* R38  - Speaker Volume Left */
  84         0x0079,     /* R39  - Speaker Volume Right */
  85         0x0000,     /* R40  - Input Mixer2 */
  86         0x0000,     /* R41  - Input Mixer3 */
  87         0x0000,     /* R42  - Input Mixer4 */
  88         0x0000,     /* R43  - Input Mixer5 */
  89         0x0000,     /* R44  - Input Mixer6 */
  90         0x0000,     /* R45  - Output Mixer1 */
  91         0x0000,     /* R46  - Output Mixer2 */
  92         0x0000,     /* R47  - Output Mixer3 */
  93         0x0000,     /* R48  - Output Mixer4 */
  94         0x0000,     /* R49  - Output Mixer5 */
  95         0x0000,     /* R50  - Output Mixer6 */
  96         0x0000,     /* R51  - HPOUT2 Mixer */
  97         0x0000,     /* R52  - Line Mixer1 */
  98         0x0000,     /* R53  - Line Mixer2 */
  99         0x0000,     /* R54  - Speaker Mixer */
 100         0x0000,     /* R55  - Additional Control */
 101         0x0000,     /* R56  - AntiPOP1 */
 102         0x0000,     /* R57  - AntiPOP2 */
 103         0x0000,     /* R58  - MICBIAS */
 104         0x0000,     /* R59 */
 105         0x0000,     /* R60  - FLL Control 1 */
 106         0x0000,     /* R61  - FLL Control 2 */
 107         0x0000,     /* R62  - FLL Control 3 */
 108         0x2EE0,     /* R63  - FLL Control 4 */
 109         0x0002,     /* R64  - FLL Control 5 */
 110         0x2287,     /* R65  - Clocking 3 */
 111         0x025F,     /* R66  - Clocking 4 */
 112         0x0000,     /* R67  - MW Slave Control */
 113         0x0000,     /* R68 */
 114         0x0002,     /* R69  - Bus Control 1 */
 115         0x0000,     /* R70  - Write Sequencer 0 */
 116         0x0000,     /* R71  - Write Sequencer 1 */
 117         0x0000,     /* R72  - Write Sequencer 2 */
 118         0x0000,     /* R73  - Write Sequencer 3 */
 119         0x0000,     /* R74  - Write Sequencer 4 */
 120         0x0000,     /* R75  - Write Sequencer 5 */
 121         0x1F25,     /* R76  - Charge Pump 1 */
 122         0x0000,     /* R77 */
 123         0x0000,     /* R78 */
 124         0x0000,     /* R79 */
 125         0x0000,     /* R80 */
 126         0x0000,     /* R81  - Class W 0 */
 127         0x0000,     /* R82 */
 128         0x0000,     /* R83 */
 129         0x0000,     /* R84  - DC Servo 0 */
 130         0x054A,     /* R85  - DC Servo 1 */
 131         0x0000,     /* R86 */
 132         0x0000,     /* R87  - DC Servo 3 */
 133         0x0000,     /* R88  - DC Servo Readback 0 */
 134         0x0000,     /* R89  - DC Servo Readback 1 */
 135         0x0000,     /* R90  - DC Servo Readback 2 */
 136         0x0000,     /* R91 */
 137         0x0000,     /* R92 */
 138         0x0000,     /* R93 */
 139         0x0000,     /* R94 */
 140         0x0000,     /* R95 */
 141         0x0100,     /* R96  - Analogue HP 0 */
 142         0x0000,     /* R97 */
 143         0x0000,     /* R98  - EQ1 */
 144         0x000C,     /* R99  - EQ2 */
 145         0x000C,     /* R100 - EQ3 */
 146         0x000C,     /* R101 - EQ4 */
 147         0x000C,     /* R102 - EQ5 */
 148         0x000C,     /* R103 - EQ6 */
 149         0x0FCA,     /* R104 - EQ7 */
 150         0x0400,     /* R105 - EQ8 */
 151         0x00D8,     /* R106 - EQ9 */
 152         0x1EB5,     /* R107 - EQ10 */
 153         0xF145,     /* R108 - EQ11 */
 154         0x0B75,     /* R109 - EQ12 */
 155         0x01C5,     /* R110 - EQ13 */
 156         0x1C58,     /* R111 - EQ14 */
 157         0xF373,     /* R112 - EQ15 */
 158         0x0A54,     /* R113 - EQ16 */
 159         0x0558,     /* R114 - EQ17 */
 160         0x168E,     /* R115 - EQ18 */
 161         0xF829,     /* R116 - EQ19 */
 162         0x07AD,     /* R117 - EQ20 */
 163         0x1103,     /* R118 - EQ21 */
 164         0x0564,     /* R119 - EQ22 */
 165         0x0559,     /* R120 - EQ23 */
 166         0x4000,     /* R121 - EQ24 */
 167         0x0000,     /* R122 - Digital Pulls */
 168         0x0F08,     /* R123 - DRC Control 1 */
 169         0x0000,     /* R124 - DRC Control 2 */
 170         0x0080,     /* R125 - DRC Control 3 */
 171         0x0000,     /* R126 - DRC Control 4 */
 172 };
 173
 174 static struct {
 175         int ratio;
 176         int clk_sys_rate;
 177 } clk_sys_rates[] = {
 178         { 64,   0 },
 179         { 128,  1 },
 180         { 192,  2 },
 181         { 256,  3 },
 182         { 384,  4 },
 183         { 512,  5 },
 184         { 768,  6 },
 185         { 1024, 7 },
 186         { 1408, 8 },
 187         { 1536, 9 },
 188 };
 189
 190 static struct {
 191         int rate;
 192         int sample_rate;
 193 } sample_rates[] = {
 194         { 8000,  0  },
 195         { 11025, 1  },
 196         { 12000, 1  },
 197         { 16000, 2  },
 198         { 22050, 3  },
 199         { 24000, 3  },
 200         { 32000, 4  },
 201         { 44100, 5  },
 202         { 48000, 5  },
 203 };
 204
 205 static struct {
 206         int div; /* *10 due to .5s */
 207         int bclk_div;
 208 } bclk_divs[] = {
 209         { 10,  0  },
 210         { 15,  1  },
 211         { 20,  2  },
 212         { 30,  3  },
 213         { 40,  4  },
 214         { 55,  5  },
 215         { 60,  6  },
 216         { 80,  7  },
 217         { 110, 8  },
 218         { 120, 9  },
 219         { 160, 10 },
 220         { 220, 11 },
 221         { 240, 12 },
 222         { 320, 13 },
 223         { 440, 14 },
 224         { 480, 15 },
 225 };
 226
 227 struct wm8993_priv {
 228         struct wm_hubs_data hubs_data;
 229         u16 reg_cache[WM8993_REGISTER_COUNT];
 230         struct regulator_bulk_data supplies[WM8993_NUM_SUPPLIES];
 231         struct wm8993_platform_data pdata;
 232         enum snd_soc_control_type control_type;
 233         void *control_data;
 234         int master;
 235         int sysclk_source;
 236         int tdm_slots;
 237         int tdm_width;
 238         unsigned int mclk_rate;
 239         unsigned int sysclk_rate;
 240         unsigned int fs;
 241         unsigned int bclk;
 242         int class_w_users;
 243         unsigned int fll_fref;
 244         unsigned int fll_fout;
 245         int fll_src;
 246 };
 247
 248 static int wm8993_volatile(unsigned int reg)
 249 {
 250         switch (reg) {
 251         case WM8993_SOFTWARE_RESET:
 252         case WM8993_DC_SERVO_0:
 253         case WM8993_DC_SERVO_READBACK_0:
 254         case WM8993_DC_SERVO_READBACK_1:
 255         case WM8993_DC_SERVO_READBACK_2:
 256                 return 1;
 257         default:
 258                 return 0;
 259         }
 260 }
 261
 262 struct _fll_div {
 263         u16 fll_fratio;
 264         u16 fll_outdiv;
 265         u16 fll_clk_ref_div;
 266         u16 n;
 267         u16 k;
 268 };
 269
 270 /* The size in bits of the FLL divide multiplied by 10
 271  * to allow rounding later */
 272 #define FIXED_FLL_SIZE ((1 << 16) * 10)
 273
 274 static struct {
 275         unsigned int min;
 276         unsigned int max;
 277         u16 fll_fratio;
 278         int ratio;
 279 } fll_fratios[] = {
 280         {       0,    64000, 4, 16 },
 281         {   64000,   128000, 3,  8 },
 282         {  128000,   256000, 2,  4 },
 283         {  256000,  1000000, 1,  2 },
 284         { 1000000, 13500000, 0,  1 },
 285 };
 286
 287 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
 288                        unsigned int Fout)
 289 {
 290         u64 Kpart;
 291         unsigned int K, Ndiv, Nmod, target;
 292         unsigned int div;
 293         int i;
 294
 295         /* Fref must be <=13.5MHz */
 296         div = 1;
 297         fll_div->fll_clk_ref_div = 0;
 298         while ((Fref / div) > 13500000) {
 299                 div *= 2;
 300                 fll_div->fll_clk_ref_div++;
 301
 302                 if (div > 8) {
 303                         pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
 304                                Fref);
 305                         return -EINVAL;
 306                 }
 307         }
 308
 309         pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
 310
 311         /* Apply the division for our remaining calculations */
 312         Fref /= div;
 313
 314         /* Fvco should be 90-100MHz; don't check the upper bound */
 315         div = 0;
 316         target = Fout * 2;
 317         while (target < 90000000) {
 318                 div++;
 319                 target *= 2;
 320                 if (div > 7) {
 321                         pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
 322                                Fout);
 323                         return -EINVAL;
 324                 }
 325         }
 326         fll_div->fll_outdiv = div;
 327
 328         pr_debug("Fvco=%dHz\n", target);
 329
 330         /* Find an appropraite FLL_FRATIO and factor it out of the target */
 331         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
 332                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
 333                         fll_div->fll_fratio = fll_fratios[i].fll_fratio;
 334                         target /= fll_fratios[i].ratio;
 335                         break;
 336                 }
 337         }
 338         if (i == ARRAY_SIZE(fll_fratios)) {
 339                 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
 340                 return -EINVAL;
 341         }
 342
 343         /* Now, calculate N.K */
 344         Ndiv = target / Fref;
 345
 346         fll_div->n = Ndiv;
 347         Nmod = target % Fref;
 348         pr_debug("Nmod=%d\n", Nmod);
 349
 350         /* Calculate fractional part - scale up so we can round. */
 351         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
 352
 353         do_div(Kpart, Fref);
 354
 355         K = Kpart & 0xFFFFFFFF;
 356
 357         if ((K % 10) >= 5)
 358                 K += 5;
 359
 360         /* Move down to proper range now rounding is done */
 361         fll_div->k = K / 10;
 362
 363         pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
 364                  fll_div->n, fll_div->k,
 365                  fll_div->fll_fratio, fll_div->fll_outdiv,
 366                  fll_div->fll_clk_ref_div);
 367
 368         return 0;
 369 }
 370
 371 static int _wm8993_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
 372                           unsigned int Fref, unsigned int Fout)
 373 {
 374         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
 375         u16 reg1, reg4, reg5;
 376         struct _fll_div fll_div;
 377         int ret;
 378
 379         /* Any change? */
 380         if (Fref == wm8993->fll_fref && Fout == wm8993->fll_fout)
 381                 return 0;
 382
 383         /* Disable the FLL */
 384         if (Fout == 0) {
 385                 dev_dbg(codec->dev, "FLL disabled\n");
 386                 wm8993->fll_fref = 0;
 387                 wm8993->fll_fout = 0;
 388
 389                 reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1);
 390                 reg1 &= ~WM8993_FLL_ENA;
 391                 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
 392
 393                 return 0;
 394         }
 395
 396         ret = fll_factors(&fll_div, Fref, Fout);
 397         if (ret != 0)
 398                 return ret;
 399
 400         reg5 = snd_soc_read(codec, WM8993_FLL_CONTROL_5);
 401         reg5 &= ~WM8993_FLL_CLK_SRC_MASK;
 402
 403         switch (fll_id) {
 404         case WM8993_FLL_MCLK:
 405                 break;
 406
 407         case WM8993_FLL_LRCLK:
 408                 reg5 |= 1;
 409                 break;
 410
 411         case WM8993_FLL_BCLK:
 412                 reg5 |= 2;
 413                 break;
 414
 415         default:
 416                 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
 417                 return -EINVAL;
 418         }
 419
 420         /* Any FLL configuration change requires that the FLL be
 421          * disabled first. */
 422         reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1);
 423         reg1 &= ~WM8993_FLL_ENA;
 424         snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
 425
 426         /* Apply the configuration */
 427         if (fll_div.k)
 428                 reg1 |= WM8993_FLL_FRAC_MASK;
 429         else
 430                 reg1 &= ~WM8993_FLL_FRAC_MASK;
 431         snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
 432
 433         snd_soc_write(codec, WM8993_FLL_CONTROL_2,
 434                       (fll_div.fll_outdiv << WM8993_FLL_OUTDIV_SHIFT) |
 435                       (fll_div.fll_fratio << WM8993_FLL_FRATIO_SHIFT));
 436         snd_soc_write(codec, WM8993_FLL_CONTROL_3, fll_div.k);
 437
 438         reg4 = snd_soc_read(codec, WM8993_FLL_CONTROL_4);
 439         reg4 &= ~WM8993_FLL_N_MASK;
 440         reg4 |= fll_div.n << WM8993_FLL_N_SHIFT;
 441         snd_soc_write(codec, WM8993_FLL_CONTROL_4, reg4);
 442
 443         reg5 &= ~WM8993_FLL_CLK_REF_DIV_MASK;
 444         reg5 |= fll_div.fll_clk_ref_div << WM8993_FLL_CLK_REF_DIV_SHIFT;
 445         snd_soc_write(codec, WM8993_FLL_CONTROL_5, reg5);
 446
 447         /* Enable the FLL */
 448         snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1 | WM8993_FLL_ENA);
 449
 450         dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
 451
 452         wm8993->fll_fref = Fref;
 453         wm8993->fll_fout = Fout;
 454         wm8993->fll_src = source;
 455
 456         return 0;
 457 }
 458
 459 static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
 460                           unsigned int Fref, unsigned int Fout)
 461 {
 462         return _wm8993_set_fll(dai->codec, fll_id, source, Fref, Fout);
 463 }
 464
 465 static int configure_clock(struct snd_soc_codec *codec)
 466 {
 467         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
 468         unsigned int reg;
 469
 470         /* This should be done on init() for bypass paths */
 471         switch (wm8993->sysclk_source) {
 472         case WM8993_SYSCLK_MCLK:
 473                 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8993->mclk_rate);
 474
 475                 reg = snd_soc_read(codec, WM8993_CLOCKING_2);
 476                 reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC);
 477                 if (wm8993->mclk_rate > 13500000) {
 478                         reg |= WM8993_MCLK_DIV;
 479                         wm8993->sysclk_rate = wm8993->mclk_rate / 2;
 480                 } else {
 481                         reg &= ~WM8993_MCLK_DIV;
 482                         wm8993->sysclk_rate = wm8993->mclk_rate;
 483                 }
 484                 snd_soc_write(codec, WM8993_CLOCKING_2, reg);
 485                 break;
 486
 487         case WM8993_SYSCLK_FLL:
 488                 dev_dbg(codec->dev, "Using %dHz FLL clock\n",
 489                         wm8993->fll_fout);
 490
 491                 reg = snd_soc_read(codec, WM8993_CLOCKING_2);
 492                 reg |= WM8993_SYSCLK_SRC;
 493                 if (wm8993->fll_fout > 13500000) {
 494                         reg |= WM8993_MCLK_DIV;
 495                         wm8993->sysclk_rate = wm8993->fll_fout / 2;
 496                 } else {
 497                         reg &= ~WM8993_MCLK_DIV;
 498                         wm8993->sysclk_rate = wm8993->fll_fout;
 499                 }
 500                 snd_soc_write(codec, WM8993_CLOCKING_2, reg);
 501                 break;
 502
 503         default:
 504                 dev_err(codec->dev, "System clock not configured\n");
 505                 return -EINVAL;
 506         }
 507
 508         dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8993->sysclk_rate);
 509
 510         return 0;
 511 }
 512
 513 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
 514 static const DECLARE_TLV_DB_SCALE(drc_comp_threash, -4500, 75, 0);
 515 static const DECLARE_TLV_DB_SCALE(drc_comp_amp, -2250, 75, 0);
 516 static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
 517 static const unsigned int drc_max_tlv[] = {
 518         TLV_DB_RANGE_HEAD(4),
 519         0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0),
 520         3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
 521 };
 522 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
 523 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -1800, 300, 0);
 524 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 525 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 526 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
 527
 528 static const char *dac_deemph_text[] = {
 529         "None",
 530         "32kHz",
 531         "44.1kHz",
 532         "48kHz",
 533 };
 534
 535 static const struct soc_enum dac_deemph =
 536         SOC_ENUM_SINGLE(WM8993_DAC_CTRL, 4, 4, dac_deemph_text);
 537
 538 static const char *adc_hpf_text[] = {
 539         "Hi-Fi",
 540         "Voice 1",
 541         "Voice 2",
 542         "Voice 3",
 543 };
 544
 545 static const struct soc_enum adc_hpf =
 546         SOC_ENUM_SINGLE(WM8993_ADC_CTRL, 5, 4, adc_hpf_text);
 547
 548 static const char *drc_path_text[] = {
 549         "ADC",
 550         "DAC"
 551 };
 552
 553 static const struct soc_enum drc_path =
 554         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 14, 2, drc_path_text);
 555
 556 static const char *drc_r0_text[] = {
 557         "1",
 558         "1/2",
 559         "1/4",
 560         "1/8",
 561         "1/16",
 562         "0",
 563 };
 564
 565 static const struct soc_enum drc_r0 =
 566         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 8, 6, drc_r0_text);
 567
 568 static const char *drc_r1_text[] = {
 569         "1",
 570         "1/2",
 571         "1/4",
 572         "1/8",
 573         "0",
 574 };
 575
 576 static const struct soc_enum drc_r1 =
 577         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_4, 13, 5, drc_r1_text);
 578
 579 static const char *drc_attack_text[] = {
 580         "Reserved",
 581         "181us",
 582         "363us",
 583         "726us",
 584         "1.45ms",
 585         "2.9ms",
 586         "5.8ms",
 587         "11.6ms",
 588         "23.2ms",
 589         "46.4ms",
 590         "92.8ms",
 591         "185.6ms",
 592 };
 593
 594 static const struct soc_enum drc_attack =
 595         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 12, 12, drc_attack_text);
 596
 597 static const char *drc_decay_text[] = {
 598         "186ms",
 599         "372ms",
 600         "743ms",
 601         "1.49s",
 602         "2.97ms",
 603         "5.94ms",
 604         "11.89ms",
 605         "23.78ms",
 606         "47.56ms",
 607 };
 608
 609 static const struct soc_enum drc_decay =
 610         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 8, 9, drc_decay_text);
 611
 612 static const char *drc_ff_text[] = {
 613         "5 samples",
 614         "9 samples",
 615 };
 616
 617 static const struct soc_enum drc_ff =
 618         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 7, 2, drc_ff_text);
 619
 620 static const char *drc_qr_rate_text[] = {
 621         "0.725ms",
 622         "1.45ms",
 623         "5.8ms",
 624 };
 625
 626 static const struct soc_enum drc_qr_rate =
 627         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 0, 3, drc_qr_rate_text);
 628
 629 static const char *drc_smooth_text[] = {
 630         "Low",
 631         "Medium",
 632         "High",
 633 };
 634
 635 static const struct soc_enum drc_smooth =
 636         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 4, 3, drc_smooth_text);
 637
 638 static const struct snd_kcontrol_new wm8993_snd_controls[] = {
 639 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8993_DIGITAL_SIDE_TONE,
 640                5, 9, 12, 0, sidetone_tlv),
 641
 642 SOC_SINGLE("DRC Switch", WM8993_DRC_CONTROL_1, 15, 1, 0),
 643 SOC_ENUM("DRC Path", drc_path),
 644 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8993_DRC_CONTROL_2,
 645                2, 60, 1, drc_comp_threash),
 646 SOC_SINGLE_TLV("DRC Compressor Amplitude Volume", WM8993_DRC_CONTROL_3,
 647                11, 30, 1, drc_comp_amp),
 648 SOC_ENUM("DRC R0", drc_r0),
 649 SOC_ENUM("DRC R1", drc_r1),
 650 SOC_SINGLE_TLV("DRC Minimum Volume", WM8993_DRC_CONTROL_1, 2, 3, 1,
 651                drc_min_tlv),
 652 SOC_SINGLE_TLV("DRC Maximum Volume", WM8993_DRC_CONTROL_1, 0, 3, 0,
 653                drc_max_tlv),
 654 SOC_ENUM("DRC Attack Rate", drc_attack),
 655 SOC_ENUM("DRC Decay Rate", drc_decay),
 656 SOC_ENUM("DRC FF Delay", drc_ff),
 657 SOC_SINGLE("DRC Anti-clip Switch", WM8993_DRC_CONTROL_1, 9, 1, 0),
 658 SOC_SINGLE("DRC Quick Release Switch", WM8993_DRC_CONTROL_1, 10, 1, 0),
 659 SOC_SINGLE_TLV("DRC Quick Release Volume", WM8993_DRC_CONTROL_3, 2, 3, 0,
 660                drc_qr_tlv),
 661 SOC_ENUM("DRC Quick Release Rate", drc_qr_rate),
 662 SOC_SINGLE("DRC Smoothing Switch", WM8993_DRC_CONTROL_1, 11, 1, 0),
 663 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8993_DRC_CONTROL_1, 8, 1, 0),
 664 SOC_ENUM("DRC Smoothing Hysteresis Threshold", drc_smooth),
 665 SOC_SINGLE_TLV("DRC Startup Volume", WM8993_DRC_CONTROL_4, 8, 18, 0,
 666                drc_startup_tlv),
 667
 668 SOC_SINGLE("EQ Switch", WM8993_EQ1, 0, 1, 0),
 669
 670 SOC_DOUBLE_R_TLV("Capture Volume", WM8993_LEFT_ADC_DIGITAL_VOLUME,
 671                  WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
 672 SOC_SINGLE("ADC High Pass Filter Switch", WM8993_ADC_CTRL, 8, 1, 0),
 673 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
 674
 675 SOC_DOUBLE_R_TLV("Playback Volume", WM8993_LEFT_DAC_DIGITAL_VOLUME,
 676                  WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
 677 SOC_SINGLE_TLV("Playback Boost Volume", WM8993_AUDIO_INTERFACE_2, 10, 3, 0,
 678                dac_boost_tlv),
 679 SOC_ENUM("DAC Deemphasis", dac_deemph),
 680
 681 SOC_SINGLE_TLV("SPKL DAC Volume", WM8993_SPKMIXL_ATTENUATION,
 682                2, 1, 1, wm_hubs_spkmix_tlv),
 683
 684 SOC_SINGLE_TLV("SPKR DAC Volume", WM8993_SPKMIXR_ATTENUATION,
 685                2, 1, 1, wm_hubs_spkmix_tlv),
 686 };
 687
 688 static const struct snd_kcontrol_new wm8993_eq_controls[] = {
 689 SOC_SINGLE_TLV("EQ1 Volume", WM8993_EQ2, 0, 24, 0, eq_tlv),
 690 SOC_SINGLE_TLV("EQ2 Volume", WM8993_EQ3, 0, 24, 0, eq_tlv),
 691 SOC_SINGLE_TLV("EQ3 Volume", WM8993_EQ4, 0, 24, 0, eq_tlv),
 692 SOC_SINGLE_TLV("EQ4 Volume", WM8993_EQ5, 0, 24, 0, eq_tlv),
 693 SOC_SINGLE_TLV("EQ5 Volume", WM8993_EQ6, 0, 24, 0, eq_tlv),
 694 };
 695
 696 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 697                          struct snd_kcontrol *kcontrol, int event)
 698 {
 699         struct snd_soc_codec *codec = w->codec;
 700
 701         switch (event) {
 702         case SND_SOC_DAPM_PRE_PMU:
 703                 return configure_clock(codec);
 704
 705         case SND_SOC_DAPM_POST_PMD:
 706                 break;
 707         }
 708
 709         return 0;
 710 }
 711
 712 /*
 713  * When used with DAC outputs only the WM8993 charge pump supports
 714  * operation in class W mode, providing very low power consumption
 715  * when used with digital sources.  Enable and disable this mode
 716  * automatically depending on the mixer configuration.
 717  *
 718  * Currently the only supported paths are the direct DAC->headphone
 719  * paths (which provide minimum power consumption anyway).
 720  */
 721 static int class_w_put(struct snd_kcontrol *kcontrol,
 722                        struct snd_ctl_elem_value *ucontrol)
 723 {
 724         struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
 725         struct snd_soc_codec *codec = widget->codec;
 726         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
 727         int ret;
 728
 729         /* Turn it off if we're using the main output mixer */
 730         if (ucontrol->value.integer.value[0] == 0) {
 731                 if (wm8993->class_w_users == 0) {
 732                         dev_dbg(codec->dev, "Disabling Class W\n");
 733                         snd_soc_update_bits(codec, WM8993_CLASS_W_0,
 734                                             WM8993_CP_DYN_FREQ |
 735                                             WM8993_CP_DYN_V,
 736                                             0);
 737                 }
 738                 wm8993->class_w_users++;
 739         }
 740
 741         /* Implement the change */
 742         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
 743
 744         /* Enable it if we're using the direct DAC path */
 745         if (ucontrol->value.integer.value[0] == 1) {
 746                 if (wm8993->class_w_users == 1) {
 747                         dev_dbg(codec->dev, "Enabling Class W\n");
 748                         snd_soc_update_bits(codec, WM8993_CLASS_W_0,
 749                                             WM8993_CP_DYN_FREQ |
 750                                             WM8993_CP_DYN_V,
 751                                             WM8993_CP_DYN_FREQ |
 752                                             WM8993_CP_DYN_V);
 753                 }
 754                 wm8993->class_w_users--;
 755         }
 756
 757         dev_dbg(codec->dev, "Indirect DAC use count now %d\n",
 758                 wm8993->class_w_users);
 759
 760         return ret;
 761 }
 762
 763 #define SOC_DAPM_ENUM_W(xname, xenum) \
 764 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 765         .info = snd_soc_info_enum_double, \
 766         .get = snd_soc_dapm_get_enum_double, \
 767         .put = class_w_put, \
 768         .private_value = (unsigned long)&xenum }
 769
 770 static const char *hp_mux_text[] = {
 771         "Mixer",
 772         "DAC",
 773 };
 774
 775 static const struct soc_enum hpl_enum =
 776         SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER1, 8, 2, hp_mux_text);
 777
 778 static const struct snd_kcontrol_new hpl_mux =
 779         SOC_DAPM_ENUM_W("Left Headphone Mux", hpl_enum);
 780
 781 static const struct soc_enum hpr_enum =
 782         SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER2, 8, 2, hp_mux_text);
 783
 784 static const struct snd_kcontrol_new hpr_mux =
 785         SOC_DAPM_ENUM_W("Right Headphone Mux", hpr_enum);
 786
 787 static const struct snd_kcontrol_new left_speaker_mixer[] = {
 788 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 7, 1, 0),
 789 SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER, 5, 1, 0),
 790 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 3, 1, 0),
 791 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
 792 };
 793
 794 static const struct snd_kcontrol_new right_speaker_mixer[] = {
 795 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
 796 SOC_DAPM_SINGLE("IN1RP Switch", WM8993_SPEAKER_MIXER, 4, 1, 0),
 797 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 2, 1, 0),
 798 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 0, 1, 0),
 799 };
 800
 801 static const char *aif_text[] = {
 802         "Left", "Right"
 803 };
 804
 805 static const struct soc_enum aifoutl_enum =
 806         SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1, 15, 2, aif_text);
 807
 808 static const struct snd_kcontrol_new aifoutl_mux =
 809         SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
 810
 811 static const struct soc_enum aifoutr_enum =
 812         SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1, 14, 2, aif_text);
 813
 814 static const struct snd_kcontrol_new aifoutr_mux =
 815         SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
 816
 817 static const struct soc_enum aifinl_enum =
 818         SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2, 15, 2, aif_text);
 819
 820 static const struct snd_kcontrol_new aifinl_mux =
 821         SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
 822
 823 static const struct soc_enum aifinr_enum =
 824         SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2, 14, 2, aif_text);
 825
 826 static const struct snd_kcontrol_new aifinr_mux =
 827         SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
 828
 829 static const char *sidetone_text[] = {
 830         "None", "Left", "Right"
 831 };
 832
 833 static const struct soc_enum sidetonel_enum =
 834         SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE, 2, 3, sidetone_text);
 835
 836 static const struct snd_kcontrol_new sidetonel_mux =
 837         SOC_DAPM_ENUM("Left Sidetone", sidetonel_enum);
 838
 839 static const struct soc_enum sidetoner_enum =
 840         SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE, 0, 3, sidetone_text);
 841
 842 static const struct snd_kcontrol_new sidetoner_mux =
 843         SOC_DAPM_ENUM("Right Sidetone", sidetoner_enum);
 844
 845 static const struct snd_soc_dapm_widget wm8993_dapm_widgets[] = {
 846 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8993_BUS_CONTROL_1, 1, 0, clk_sys_event,
 847                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 848 SND_SOC_DAPM_SUPPLY("TOCLK", WM8993_CLOCKING_1, 14, 0, NULL, 0),
 849 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8993_CLOCKING_3, 0, 0, NULL, 0),
 850
 851 SND_SOC_DAPM_ADC("ADCL", NULL, WM8993_POWER_MANAGEMENT_2, 1, 0),
 852 SND_SOC_DAPM_ADC("ADCR", NULL, WM8993_POWER_MANAGEMENT_2, 0, 0),
 853
 854 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
 855 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
 856
 857 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
 858 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
 859
 860 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
 861 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
 862
 863 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
 864 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
 865
 866 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &sidetonel_mux),
 867 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &sidetoner_mux),
 868
 869 SND_SOC_DAPM_DAC("DACL", NULL, WM8993_POWER_MANAGEMENT_3, 1, 0),
 870 SND_SOC_DAPM_DAC("DACR", NULL, WM8993_POWER_MANAGEMENT_3, 0, 0),
 871
 872 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
 873 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
 874
 875 SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3, 8, 0,
 876                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
 877 SND_SOC_DAPM_MIXER("SPKR", WM8993_POWER_MANAGEMENT_3, 9, 0,
 878                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
 879
 880 };
 881
 882 static const struct snd_soc_dapm_route routes[] = {
 883         { "ADCL", NULL, "CLK_SYS" },
 884         { "ADCL", NULL, "CLK_DSP" },
 885         { "ADCR", NULL, "CLK_SYS" },
 886         { "ADCR", NULL, "CLK_DSP" },
 887
 888         { "AIFOUTL Mux", "Left", "ADCL" },
 889         { "AIFOUTL Mux", "Right", "ADCR" },
 890         { "AIFOUTR Mux", "Left", "ADCL" },
 891         { "AIFOUTR Mux", "Right", "ADCR" },
 892
 893         { "AIFOUTL", NULL, "AIFOUTL Mux" },
 894         { "AIFOUTR", NULL, "AIFOUTR Mux" },
 895
 896         { "DACL Mux", "Left", "AIFINL" },
 897         { "DACL Mux", "Right", "AIFINR" },
 898         { "DACR Mux", "Left", "AIFINL" },
 899         { "DACR Mux", "Right", "AIFINR" },
 900
 901         { "DACL Sidetone", "Left", "ADCL" },
 902         { "DACL Sidetone", "Right", "ADCR" },
 903         { "DACR Sidetone", "Left", "ADCL" },
 904         { "DACR Sidetone", "Right", "ADCR" },
 905
 906         { "DACL", NULL, "CLK_SYS" },
 907         { "DACL", NULL, "CLK_DSP" },
 908         { "DACL", NULL, "DACL Mux" },
 909         { "DACL", NULL, "DACL Sidetone" },
 910         { "DACR", NULL, "CLK_SYS" },
 911         { "DACR", NULL, "CLK_DSP" },
 912         { "DACR", NULL, "DACR Mux" },
 913         { "DACR", NULL, "DACR Sidetone" },
 914
 915         { "Left Output Mixer", "DAC Switch", "DACL" },
 916
 917         { "Right Output Mixer", "DAC Switch", "DACR" },
 918
 919         { "Left Output PGA", NULL, "CLK_SYS" },
 920
 921         { "Right Output PGA", NULL, "CLK_SYS" },
 922
 923         { "SPKL", "DAC Switch", "DACL" },
 924         { "SPKL", NULL, "CLK_SYS" },
 925
 926         { "SPKR", "DAC Switch", "DACR" },
 927         { "SPKR", NULL, "CLK_SYS" },
 928
 929         { "Left Headphone Mux", "DAC", "DACL" },
 930         { "Right Headphone Mux", "DAC", "DACR" },
 931 };
 932
 933 static void wm8993_cache_restore(struct snd_soc_codec *codec)
 934 {
 935         u16 *cache = codec->reg_cache;
 936         int i;
 937
 938         if (!codec->cache_sync)
 939                 return;
 940
 941         /* Reenable hardware writes */
 942         codec->cache_only = 0;
 943
 944         /* Restore the register settings */
 945         for (i = 1; i < WM8993_MAX_REGISTER; i++) {
 946                 if (cache[i] == wm8993_reg_defaults[i])
 947                         continue;
 948                 snd_soc_write(codec, i, cache[i]);
 949         }
 950
 951         /* We're in sync again */
 952         codec->cache_sync = 0;
 953 }
 954
 955 static int wm8993_set_bias_level(struct snd_soc_codec *codec,
 956                                  enum snd_soc_bias_level level)
 957 {
 958         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
 959         int ret;
 960
 961         switch (level) {
 962         case SND_SOC_BIAS_ON:
 963         case SND_SOC_BIAS_PREPARE:
 964                 /* VMID=2*40k */
 965                 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
 966                                     WM8993_VMID_SEL_MASK, 0x2);
 967                 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
 968                                     WM8993_TSHUT_ENA, WM8993_TSHUT_ENA);
 969                 break;
 970
 971         case SND_SOC_BIAS_STANDBY:
 972                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
 973                         ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
 974                                                     wm8993->supplies);
 975                         if (ret != 0)
 976                                 return ret;
 977
 978                         wm8993_cache_restore(codec);
 979
 980                         /* Tune DC servo configuration */
 981                         snd_soc_write(codec, 0x44, 3);
 982                         snd_soc_write(codec, 0x56, 3);
 983                         snd_soc_write(codec, 0x44, 0);
 984
 985                         /* Bring up VMID with fast soft start */
 986                         snd_soc_update_bits(codec, WM8993_ANTIPOP2,
 987                                             WM8993_STARTUP_BIAS_ENA |
 988                                             WM8993_VMID_BUF_ENA |
 989                                             WM8993_VMID_RAMP_MASK |
 990                                             WM8993_BIAS_SRC,
 991                                             WM8993_STARTUP_BIAS_ENA |
 992                                             WM8993_VMID_BUF_ENA |
 993                                             WM8993_VMID_RAMP_MASK |
 994                                             WM8993_BIAS_SRC);
 995
 996                         /* If either line output is single ended we
 997                          * need the VMID buffer */
 998                         if (!wm8993->pdata.lineout1_diff ||
 999                             !wm8993->pdata.lineout2_diff)
1000                                 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
1001                                                  WM8993_LINEOUT_VMID_BUF_ENA,
1002                                                  WM8993_LINEOUT_VMID_BUF_ENA);
1003
1004                         /* VMID=2*40k */
1005                         snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1006                                             WM8993_VMID_SEL_MASK |
1007                                             WM8993_BIAS_ENA,
1008                                             WM8993_BIAS_ENA | 0x2);
1009                         msleep(32);
1010
1011                         /* Switch to normal bias */
1012                         snd_soc_update_bits(codec, WM8993_ANTIPOP2,
1013                                             WM8993_BIAS_SRC |
1014                                             WM8993_STARTUP_BIAS_ENA, 0);
1015                 }
1016
1017                 /* VMID=2*240k */
1018                 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1019                                     WM8993_VMID_SEL_MASK, 0x4);
1020
1021                 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
1022                                     WM8993_TSHUT_ENA, 0);
1023                 break;
1024
1025         case SND_SOC_BIAS_OFF:
1026                 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
1027                                     WM8993_LINEOUT_VMID_BUF_ENA, 0);
1028
1029                 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1030                                     WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA,
1031                                     0);
1032
1033 #ifdef CONFIG_REGULATOR
1034                /* Post 2.6.34 we will be able to get a callback when
1035                 * the regulators are disabled which we can use but
1036                 * for now just assume that the power will be cut if
1037                 * the regulator API is in use.
1038                 */
1039                 codec->cache_sync = 1;
1040 #endif
1041
1042                 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies),
1043                                        wm8993->supplies);
1044                 break;
1045         }
1046
1047         codec->bias_level = level;
1048
1049         return 0;
1050 }
1051
1052 static int wm8993_set_sysclk(struct snd_soc_dai *codec_dai,
1053                              int clk_id, unsigned int freq, int dir)
1054 {
1055         struct snd_soc_codec *codec = codec_dai->codec;
1056         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1057
1058         switch (clk_id) {
1059         case WM8993_SYSCLK_MCLK:
1060                 wm8993->mclk_rate = freq;
1061         case WM8993_SYSCLK_FLL:
1062                 wm8993->sysclk_source = clk_id;
1063                 break;
1064
1065         default:
1066                 return -EINVAL;
1067         }
1068
1069         return 0;
1070 }
1071
1072 static int wm8993_set_dai_fmt(struct snd_soc_dai *dai,
1073                               unsigned int fmt)
1074 {
1075         struct snd_soc_codec *codec = dai->codec;
1076         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1077         unsigned int aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1);
1078         unsigned int aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4);
1079
1080         aif1 &= ~(WM8993_BCLK_DIR | WM8993_AIF_BCLK_INV |
1081                   WM8993_AIF_LRCLK_INV | WM8993_AIF_FMT_MASK);
1082         aif4 &= ~WM8993_LRCLK_DIR;
1083
1084         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1085         case SND_SOC_DAIFMT_CBS_CFS:
1086                 wm8993->master = 0;
1087                 break;
1088         case SND_SOC_DAIFMT_CBS_CFM:
1089                 aif4 |= WM8993_LRCLK_DIR;
1090                 wm8993->master = 1;
1091                 break;
1092         case SND_SOC_DAIFMT_CBM_CFS:
1093                 aif1 |= WM8993_BCLK_DIR;
1094                 wm8993->master = 1;
1095                 break;
1096         case SND_SOC_DAIFMT_CBM_CFM:
1097                 aif1 |= WM8993_BCLK_DIR;
1098                 aif4 |= WM8993_LRCLK_DIR;
1099                 wm8993->master = 1;
1100                 break;
1101         default:
1102                 return -EINVAL;
1103         }
1104
1105         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1106         case SND_SOC_DAIFMT_DSP_B:
1107                 aif1 |= WM8993_AIF_LRCLK_INV;
1108         case SND_SOC_DAIFMT_DSP_A:
1109                 aif1 |= 0x18;
1110                 break;
1111         case SND_SOC_DAIFMT_I2S:
1112                 aif1 |= 0x10;
1113                 break;
1114         case SND_SOC_DAIFMT_RIGHT_J:
1115                 break;
1116         case SND_SOC_DAIFMT_LEFT_J:
1117                 aif1 |= 0x8;
1118                 break;
1119         default:
1120                 return -EINVAL;
1121         }
1122
1123         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1124         case SND_SOC_DAIFMT_DSP_A:
1125         case SND_SOC_DAIFMT_DSP_B:
1126                 /* frame inversion not valid for DSP modes */
1127                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1128                 case SND_SOC_DAIFMT_NB_NF:
1129                         break;
1130                 case SND_SOC_DAIFMT_IB_NF:
1131                         aif1 |= WM8993_AIF_BCLK_INV;
1132                         break;
1133                 default:
1134                         return -EINVAL;
1135                 }
1136                 break;
1137
1138         case SND_SOC_DAIFMT_I2S:
1139         case SND_SOC_DAIFMT_RIGHT_J:
1140         case SND_SOC_DAIFMT_LEFT_J:
1141                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1142                 case SND_SOC_DAIFMT_NB_NF:
1143                         break;
1144                 case SND_SOC_DAIFMT_IB_IF:
1145                         aif1 |= WM8993_AIF_BCLK_INV | WM8993_AIF_LRCLK_INV;
1146                         break;
1147                 case SND_SOC_DAIFMT_IB_NF:
1148                         aif1 |= WM8993_AIF_BCLK_INV;
1149                         break;
1150                 case SND_SOC_DAIFMT_NB_IF:
1151                         aif1 |= WM8993_AIF_LRCLK_INV;
1152                         break;
1153                 default:
1154                         return -EINVAL;
1155                 }
1156                 break;
1157         default:
1158                 return -EINVAL;
1159         }
1160
1161         snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
1162         snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
1163
1164         return 0;
1165 }
1166
1167 static int wm8993_hw_params(struct snd_pcm_substream *substream,
1168                             struct snd_pcm_hw_params *params,
1169                             struct snd_soc_dai *dai)
1170 {
1171         struct snd_soc_codec *codec = dai->codec;
1172         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1173         int ret, i, best, best_val, cur_val;
1174         unsigned int clocking1, clocking3, aif1, aif4;
1175
1176         clocking1 = snd_soc_read(codec, WM8993_CLOCKING_1);
1177         clocking1 &= ~WM8993_BCLK_DIV_MASK;
1178
1179         clocking3 = snd_soc_read(codec, WM8993_CLOCKING_3);
1180         clocking3 &= ~(WM8993_CLK_SYS_RATE_MASK | WM8993_SAMPLE_RATE_MASK);
1181
1182         aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1);
1183         aif1 &= ~WM8993_AIF_WL_MASK;
1184
1185         aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4);
1186         aif4 &= ~WM8993_LRCLK_RATE_MASK;
1187
1188         /* What BCLK do we need? */
1189         wm8993->fs = params_rate(params);
1190         wm8993->bclk = 2 * wm8993->fs;
1191         if (wm8993->tdm_slots) {
1192                 dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n",
1193                         wm8993->tdm_slots, wm8993->tdm_width);
1194                 wm8993->bclk *= wm8993->tdm_width * wm8993->tdm_slots;
1195         } else {
1196                 switch (params_format(params)) {
1197                 case SNDRV_PCM_FORMAT_S16_LE:
1198                         wm8993->bclk *= 16;
1199                         break;
1200                 case SNDRV_PCM_FORMAT_S20_3LE:
1201                         wm8993->bclk *= 20;
1202                         aif1 |= 0x8;
1203                         break;
1204                 case SNDRV_PCM_FORMAT_S24_LE:
1205                         wm8993->bclk *= 24;
1206                         aif1 |= 0x10;
1207                         break;
1208                 case SNDRV_PCM_FORMAT_S32_LE:
1209                         wm8993->bclk *= 32;
1210                         aif1 |= 0x18;
1211                         break;
1212                 default:
1213                         return -EINVAL;
1214                 }
1215         }
1216
1217         dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8993->bclk);
1218
1219         ret = configure_clock(codec);
1220         if (ret != 0)
1221                 return ret;
1222
1223         /* Select nearest CLK_SYS_RATE */
1224         best = 0;
1225         best_val = abs((wm8993->sysclk_rate / clk_sys_rates[0].ratio)
1226                        - wm8993->fs);
1227         for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1228                 cur_val = abs((wm8993->sysclk_rate /
1229                                clk_sys_rates[i].ratio) - wm8993->fs);;
1230                 if (cur_val < best_val) {
1231                         best = i;
1232                         best_val = cur_val;
1233                 }
1234         }
1235         dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1236                 clk_sys_rates[best].ratio);
1237         clocking3 |= (clk_sys_rates[best].clk_sys_rate
1238                       << WM8993_CLK_SYS_RATE_SHIFT);
1239
1240         /* SAMPLE_RATE */
1241         best = 0;
1242         best_val = abs(wm8993->fs - sample_rates[0].rate);
1243         for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1244                 /* Closest match */
1245                 cur_val = abs(wm8993->fs - sample_rates[i].rate);
1246                 if (cur_val < best_val) {
1247                         best = i;
1248                         best_val = cur_val;
1249                 }
1250         }
1251         dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1252                 sample_rates[best].rate);
1253         clocking3 |= (sample_rates[best].sample_rate
1254                       << WM8993_SAMPLE_RATE_SHIFT);
1255
1256         /* BCLK_DIV */
1257         best = 0;
1258         best_val = INT_MAX;
1259         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1260                 cur_val = ((wm8993->sysclk_rate * 10) / bclk_divs[i].div)
1261                         - wm8993->bclk;
1262                 if (cur_val < 0) /* Table is sorted */
1263                         break;
1264                 if (cur_val < best_val) {
1265                         best = i;
1266                         best_val = cur_val;
1267                 }
1268         }
1269         wm8993->bclk = (wm8993->sysclk_rate * 10) / bclk_divs[best].div;
1270         dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1271                 bclk_divs[best].div, wm8993->bclk);
1272         clocking1 |= bclk_divs[best].bclk_div << WM8993_BCLK_DIV_SHIFT;
1273
1274         /* LRCLK is a simple fraction of BCLK */
1275         dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8993->bclk / wm8993->fs);
1276         aif4 |= wm8993->bclk / wm8993->fs;
1277
1278         snd_soc_write(codec, WM8993_CLOCKING_1, clocking1);
1279         snd_soc_write(codec, WM8993_CLOCKING_3, clocking3);
1280         snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
1281         snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
1282
1283         /* ReTune Mobile? */
1284         if (wm8993->pdata.num_retune_configs) {
1285                 u16 eq1 = snd_soc_read(codec, WM8993_EQ1);
1286                 struct wm8993_retune_mobile_setting *s;
1287
1288                 best = 0;
1289                 best_val = abs(wm8993->pdata.retune_configs[0].rate
1290                                - wm8993->fs);
1291                 for (i = 0; i < wm8993->pdata.num_retune_configs; i++) {
1292                         cur_val = abs(wm8993->pdata.retune_configs[i].rate
1293                                       - wm8993->fs);
1294                         if (cur_val < best_val) {
1295                                 best_val = cur_val;
1296                                 best = i;
1297                         }
1298                 }
1299                 s = &wm8993->pdata.retune_configs[best];
1300
1301                 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1302                         s->name, s->rate);
1303
1304                 /* Disable EQ while we reconfigure */
1305                 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, 0);
1306
1307                 for (i = 1; i < ARRAY_SIZE(s->config); i++)
1308                         snd_soc_write(codec, WM8993_EQ1 + i, s->config[i]);
1309
1310                 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, eq1);
1311         }
1312
1313         return 0;
1314 }
1315
1316 static int wm8993_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1317 {
1318         struct snd_soc_codec *codec = codec_dai->codec;
1319         unsigned int reg;
1320
1321         reg = snd_soc_read(codec, WM8993_DAC_CTRL);
1322
1323         if (mute)
1324                 reg |= WM8993_DAC_MUTE;
1325         else
1326                 reg &= ~WM8993_DAC_MUTE;
1327
1328         snd_soc_write(codec, WM8993_DAC_CTRL, reg);
1329
1330         return 0;
1331 }
1332
1333 static int wm8993_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1334                                unsigned int rx_mask, int slots, int slot_width)
1335 {
1336         struct snd_soc_codec *codec = dai->codec;
1337         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1338         int aif1 = 0;
1339         int aif2 = 0;
1340
1341         /* Don't need to validate anything if we're turning off TDM */
1342         if (slots == 0) {
1343                 wm8993->tdm_slots = 0;
1344                 goto out;
1345         }
1346
1347         /* Note that we allow configurations we can't handle ourselves -
1348          * for example, we can generate clocks for slots 2 and up even if
1349          * we can't use those slots ourselves.
1350          */
1351         aif1 |= WM8993_AIFADC_TDM;
1352         aif2 |= WM8993_AIFDAC_TDM;
1353
1354         switch (rx_mask) {
1355         case 3:
1356                 break;
1357         case 0xc:
1358                 aif1 |= WM8993_AIFADC_TDM_CHAN;
1359                 break;
1360         default:
1361                 return -EINVAL;
1362         }
1363
1364
1365         switch (tx_mask) {
1366         case 3:
1367                 break;
1368         case 0xc:
1369                 aif2 |= WM8993_AIFDAC_TDM_CHAN;
1370                 break;
1371         default:
1372                 return -EINVAL;
1373         }
1374
1375 out:
1376         wm8993->tdm_width = slot_width;
1377         wm8993->tdm_slots = slots / 2;
1378
1379         snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_1,
1380                             WM8993_AIFADC_TDM | WM8993_AIFADC_TDM_CHAN, aif1);
1381         snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_2,
1382                             WM8993_AIFDAC_TDM | WM8993_AIFDAC_TDM_CHAN, aif2);
1383
1384         return 0;
1385 }
1386
1387 static struct snd_soc_dai_ops wm8993_ops = {
1388         .set_sysclk = wm8993_set_sysclk,
1389         .set_fmt = wm8993_set_dai_fmt,
1390         .hw_params = wm8993_hw_params,
1391         .digital_mute = wm8993_digital_mute,
1392         .set_pll = wm8993_set_fll,
1393         .set_tdm_slot = wm8993_set_tdm_slot,
1394 };
1395
1396 #define WM8993_RATES SNDRV_PCM_RATE_8000_48000
1397
1398 #define WM8993_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1399                         SNDRV_PCM_FMTBIT_S20_3LE |\
1400                         SNDRV_PCM_FMTBIT_S24_LE |\
1401                         SNDRV_PCM_FMTBIT_S32_LE)
1402
1403 static struct snd_soc_dai_driver wm8993_dai = {
1404         .name = "wm8993-hifi",
1405         .playback = {
1406                 .stream_name = "Playback",
1407                 .channels_min = 1,
1408                 .channels_max = 2,
1409                 .rates = WM8993_RATES,
1410                 .formats = WM8993_FORMATS,
1411         },
1412         .capture = {
1413                  .stream_name = "Capture",
1414                  .channels_min = 1,
1415                  .channels_max = 2,
1416                  .rates = WM8993_RATES,
1417                  .formats = WM8993_FORMATS,
1418          },
1419         .ops = &wm8993_ops,
1420         .symmetric_rates = 1,
1421 };
1422
1423 static int wm8993_probe(struct snd_soc_codec *codec)
1424 {
1425         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1426         int ret, i, val;
1427
1428         codec->control_data = wm8993->control_data;
1429         wm8993->hubs_data.hp_startup_mode = 1;
1430         wm8993->hubs_data.dcs_codes = -2;
1431
1432         ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1433         if (ret != 0) {
1434                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1435                 return ret;
1436         }
1437
1438         for (i = 0; i < ARRAY_SIZE(wm8993->supplies); i++)
1439                 wm8993->supplies[i].supply = wm8993_supply_names[i];
1440
1441         ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8993->supplies),
1442                                  wm8993->supplies);
1443         if (ret != 0) {
1444                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1445                 return ret;
1446         }
1447
1448         ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
1449                                     wm8993->supplies);
1450         if (ret != 0) {
1451                 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1452                 goto err_get;
1453         }
1454
1455         val = snd_soc_read(codec, WM8993_SOFTWARE_RESET);
1456         if (val != wm8993_reg_defaults[WM8993_SOFTWARE_RESET]) {
1457                 dev_err(codec->dev, "Invalid ID register value %x\n", val);
1458                 ret = -EINVAL;
1459                 goto err_enable;
1460         }
1461
1462         ret = snd_soc_write(codec, WM8993_SOFTWARE_RESET, 0xffff);
1463         if (ret != 0)
1464                 goto err_enable;
1465
1466         codec->cache_only = 1;
1467
1468         /* By default we're using the output mixers */
1469         wm8993->class_w_users = 2;
1470
1471         /* Latch volume update bits and default ZC on */
1472         snd_soc_update_bits(codec, WM8993_RIGHT_DAC_DIGITAL_VOLUME,
1473                             WM8993_DAC_VU, WM8993_DAC_VU);
1474         snd_soc_update_bits(codec, WM8993_RIGHT_ADC_DIGITAL_VOLUME,
1475                             WM8993_ADC_VU, WM8993_ADC_VU);
1476
1477         /* Manualy manage the HPOUT sequencing for independent stereo
1478          * control. */
1479         snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
1480                             WM8993_HPOUT1_AUTO_PU, 0);
1481
1482         /* Use automatic clock configuration */
1483         snd_soc_update_bits(codec, WM8993_CLOCKING_4, WM8993_SR_MODE, 0);
1484
1485         wm_hubs_handle_analogue_pdata(codec, wm8993->pdata.lineout1_diff,
1486                                       wm8993->pdata.lineout2_diff,
1487                                       wm8993->pdata.lineout1fb,
1488                                       wm8993->pdata.lineout2fb,
1489                                       wm8993->pdata.jd_scthr,
1490                                       wm8993->pdata.jd_thr,
1491                                       wm8993->pdata.micbias1_lvl,
1492                                       wm8993->pdata.micbias2_lvl);
1493
1494         ret = wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1495         if (ret != 0)
1496                 goto err_enable;
1497
1498         snd_soc_add_controls(codec, wm8993_snd_controls,
1499                              ARRAY_SIZE(wm8993_snd_controls));
1500         if (wm8993->pdata.num_retune_configs != 0) {
1501                 dev_dbg(codec->dev, "Using ReTune Mobile\n");
1502         } else {
1503                 dev_dbg(codec->dev, "No ReTune Mobile, using normal EQ\n");
1504                 snd_soc_add_controls(codec, wm8993_eq_controls,
1505                                      ARRAY_SIZE(wm8993_eq_controls));
1506         }
1507
1508         snd_soc_dapm_new_controls(codec, wm8993_dapm_widgets,
1509                                   ARRAY_SIZE(wm8993_dapm_widgets));
1510         wm_hubs_add_analogue_controls(codec);
1511
1512         snd_soc_dapm_add_routes(codec, routes, ARRAY_SIZE(routes));
1513         wm_hubs_add_analogue_routes(codec, wm8993->pdata.lineout1_diff,
1514                                     wm8993->pdata.lineout2_diff);
1515
1516         return 0;
1517
1518 err_enable:
1519         regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1520 err_get:
1521         regulator_bulk_free(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1522         return ret;
1523 }
1524
1525 static int wm8993_remove(struct snd_soc_codec *codec)
1526 {
1527         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1528
1529         wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF);
1530         regulator_bulk_free(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1531         return 0;
1532 }
1533
1534 #ifdef CONFIG_PM
1535 static int wm8993_suspend(struct snd_soc_codec *codec, pm_message_t state)
1536 {
1537         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1538         int fll_fout = wm8993->fll_fout;
1539         int fll_fref  = wm8993->fll_fref;
1540         int ret;
1541
1542         /* Stop the FLL in an orderly fashion */
1543         ret = _wm8993_set_fll(codec, 0, 0, 0, 0);
1544         if (ret != 0) {
1545                 dev_err(codec->dev, "Failed to stop FLL\n");
1546                 return ret;
1547         }
1548
1549         wm8993->fll_fout = fll_fout;
1550         wm8993->fll_fref = fll_fref;
1551
1552         wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF);
1553
1554         return 0;
1555 }
1556
1557 static int wm8993_resume(struct snd_soc_codec *codec)
1558 {
1559         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1560         int ret;
1561
1562         wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1563
1564         /* Restart the FLL? */
1565         if (wm8993->fll_fout) {
1566                 int fll_fout = wm8993->fll_fout;
1567                 int fll_fref  = wm8993->fll_fref;
1568
1569                 wm8993->fll_fref = 0;
1570                 wm8993->fll_fout = 0;
1571
1572                 ret = _wm8993_set_fll(codec, 0, wm8993->fll_src,
1573                                      fll_fref, fll_fout);
1574                 if (ret != 0)
1575                         dev_err(codec->dev, "Failed to restart FLL\n");
1576         }
1577
1578         return 0;
1579 }
1580 #else
1581 #define wm8993_suspend NULL
1582 #define wm8993_resume NULL
1583 #endif
1584
1585 static struct snd_soc_codec_driver soc_codec_dev_wm8993 = {
1586         .probe =        wm8993_probe,
1587         .remove =       wm8993_remove,
1588         .suspend =      wm8993_suspend,
1589         .resume =       wm8993_resume,
1590         .set_bias_level = wm8993_set_bias_level,
1591         .reg_cache_size = sizeof(wm8993_reg_defaults),
1592         .reg_word_size = sizeof(u16),
1593         .reg_cache_default = wm8993_reg_defaults,
1594         .volatile_register = wm8993_volatile,
1595 };
1596
1597 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1598 static __devinit int wm8993_i2c_probe(struct i2c_client *i2c,
1599                                       const struct i2c_device_id *id)
1600 {
1601         struct wm8993_priv *wm8993;
1602         int ret;
1603
1604         wm8993 = kzalloc(sizeof(struct wm8993_priv), GFP_KERNEL);
1605         if (wm8993 == NULL)
1606                 return -ENOMEM;
1607
1608         i2c_set_clientdata(i2c, wm8993);
1609         wm8993->control_data = i2c;
1610
1611         ret = snd_soc_register_codec(&i2c->dev,
1612                         &soc_codec_dev_wm8993, &wm8993_dai, 1);
1613         if (ret < 0)
1614                 kfree(wm8993);
1615         return ret;
1616 }
1617
1618 static __devexit int wm8993_i2c_remove(struct i2c_client *client)
1619 {
1620         snd_soc_unregister_codec(&client->dev);
1621         kfree(i2c_get_clientdata(client));
1622         return 0;
1623 }
1624
1625 static const struct i2c_device_id wm8993_i2c_id[] = {
1626         { "wm8993", 0 },
1627         { }
1628 };
1629 MODULE_DEVICE_TABLE(i2c, wm8993_i2c_id);
1630
1631 static struct i2c_driver wm8993_i2c_driver = {
1632         .driver = {
1633                 .name = "wm8993-codec",
1634                 .owner = THIS_MODULE,
1635         },
1636         .probe =    wm8993_i2c_probe,
1637         .remove =   __devexit_p(wm8993_i2c_remove),
1638         .id_table = wm8993_i2c_id,
1639 };
1640 #endif
1641
1642 static int __init wm8993_modinit(void)
1643 {
1644         int ret = 0;
1645 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1646         ret = i2c_add_driver(&wm8993_i2c_driver);
1647         if (ret != 0) {
1648                 pr_err("WM8993: Unable to register I2C driver: %d\n",
1649                        ret);
1650         }
1651 #endif
1652         return ret;
1653 }
1654 module_init(wm8993_modinit);
1655
1656 static void __exit wm8993_exit(void)
1657 {
1658 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1659         i2c_del_driver(&wm8993_i2c_driver);
1660 #endif
1661 }
1662 module_exit(wm8993_exit);
1663
1664
1665 MODULE_DESCRIPTION("ASoC WM8993 driver");
1666 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1667 MODULE_LICENSE("GPL");