2 * Fifo-attached Serial Interface (FSI) support for SH7724
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/delay.h>
16 #include <linux/pm_runtime.h>
18 #include <linux/slab.h>
19 #include <sound/soc.h>
20 #include <sound/sh_fsi.h>
23 #define DOFF_CTL 0x0004
24 #define DOFF_ST 0x0008
26 #define DIFF_CTL 0x0010
27 #define DIFF_ST 0x0014
32 #define MUTE_ST 0x0028
33 #define OUT_SEL 0x0030
34 #define REG_END OUT_SEL
36 #define A_MST_CTLR 0x0180
37 #define B_MST_CTLR 0x01A0
38 #define CPU_INT_ST 0x01F4
39 #define CPU_IEMSK 0x01F8
40 #define CPU_IMSK 0x01FC
45 #define CLK_RST 0x0210
46 #define SOFT_RST 0x0214
47 #define FIFO_SZ 0x0218
48 #define MREG_START A_MST_CTLR
49 #define MREG_END FIFO_SZ
53 #define CR_MONO (0x0 << 4)
54 #define CR_MONO_D (0x1 << 4)
55 #define CR_PCM (0x2 << 4)
56 #define CR_I2S (0x3 << 4)
57 #define CR_TDM (0x4 << 4)
58 #define CR_TDM_D (0x5 << 4)
59 #define CR_SPDIF 0x00100120
63 #define IRQ_HALF 0x00100000
64 #define FIFO_CLR 0x00000001
67 #define ERR_OVER 0x00000010
68 #define ERR_UNDER 0x00000001
69 #define ST_ERR (ERR_OVER | ERR_UNDER)
72 #define ACKMD_MASK 0x00007000
73 #define BPFMD_MASK 0x00000700
76 #define BP (1 << 4) /* Fix the signal of Biphase output */
77 #define SE (1 << 0) /* Fix the master clock */
80 #define B_CLK 0x00000010
81 #define A_CLK 0x00000001
84 #define INT_B_IN (1 << 12)
85 #define INT_B_OUT (1 << 8)
86 #define INT_A_IN (1 << 4)
87 #define INT_A_OUT (1 << 0)
90 #define PBSR (1 << 12) /* Port B Software Reset */
91 #define PASR (1 << 8) /* Port A Software Reset */
92 #define IR (1 << 4) /* Interrupt Reset */
93 #define FSISR (1 << 0) /* Software Reset */
96 #define OUT_SZ_MASK 0x7
100 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
102 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
104 /************************************************************************
110 ************************************************************************/
113 struct snd_pcm_substream *substream;
114 struct fsi_master *master;
138 struct fsi_priv fsia;
139 struct fsi_priv fsib;
140 struct fsi_core *core;
141 struct sh_fsi_platform_info *info;
145 /************************************************************************
148 basic read write function
151 ************************************************************************/
152 static void __fsi_reg_write(u32 reg, u32 data)
154 /* valid data area is 24bit */
157 __raw_writel(data, reg);
160 static u32 __fsi_reg_read(u32 reg)
162 return __raw_readl(reg);
165 static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data)
167 u32 val = __fsi_reg_read(reg);
172 __fsi_reg_write(reg, val);
175 static void fsi_reg_write(struct fsi_priv *fsi, u32 reg, u32 data)
178 pr_err("fsi: register access err (%s)\n", __func__);
182 __fsi_reg_write((u32)(fsi->base + reg), data);
185 static u32 fsi_reg_read(struct fsi_priv *fsi, u32 reg)
188 pr_err("fsi: register access err (%s)\n", __func__);
192 return __fsi_reg_read((u32)(fsi->base + reg));
195 static void fsi_reg_mask_set(struct fsi_priv *fsi, u32 reg, u32 mask, u32 data)
198 pr_err("fsi: register access err (%s)\n", __func__);
202 __fsi_reg_mask_set((u32)(fsi->base + reg), mask, data);
205 static void fsi_master_write(struct fsi_master *master, u32 reg, u32 data)
209 if ((reg < MREG_START) ||
211 pr_err("fsi: register access err (%s)\n", __func__);
215 spin_lock_irqsave(&master->lock, flags);
216 __fsi_reg_write((u32)(master->base + reg), data);
217 spin_unlock_irqrestore(&master->lock, flags);
220 static u32 fsi_master_read(struct fsi_master *master, u32 reg)
225 if ((reg < MREG_START) ||
227 pr_err("fsi: register access err (%s)\n", __func__);
231 spin_lock_irqsave(&master->lock, flags);
232 ret = __fsi_reg_read((u32)(master->base + reg));
233 spin_unlock_irqrestore(&master->lock, flags);
238 static void fsi_master_mask_set(struct fsi_master *master,
239 u32 reg, u32 mask, u32 data)
243 if ((reg < MREG_START) ||
245 pr_err("fsi: register access err (%s)\n", __func__);
249 spin_lock_irqsave(&master->lock, flags);
250 __fsi_reg_mask_set((u32)(master->base + reg), mask, data);
251 spin_unlock_irqrestore(&master->lock, flags);
254 /************************************************************************
260 ************************************************************************/
261 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
266 static int fsi_is_port_a(struct fsi_priv *fsi)
268 return fsi->master->base == fsi->base;
271 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
273 struct snd_soc_pcm_runtime *rtd = substream->private_data;
278 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
280 struct snd_soc_dai *dai = fsi_get_dai(substream);
281 struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
284 return &master->fsia;
286 return &master->fsib;
289 static u32 fsi_get_info_flags(struct fsi_priv *fsi)
291 int is_porta = fsi_is_port_a(fsi);
292 struct fsi_master *master = fsi_get_master(fsi);
294 return is_porta ? master->info->porta_flags :
295 master->info->portb_flags;
298 static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play)
301 u32 flags = fsi_get_info_flags(fsi);
303 mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE;
310 return (mode & flags) != mode;
313 static u32 fsi_port_ab_io_bit(struct fsi_priv *fsi, int is_play)
315 int is_porta = fsi_is_port_a(fsi);
319 data = is_play ? (1 << 0) : (1 << 4);
321 data = is_play ? (1 << 8) : (1 << 12);
326 static void fsi_stream_push(struct fsi_priv *fsi,
327 struct snd_pcm_substream *substream,
331 fsi->substream = substream;
332 fsi->buffer_len = buffer_len;
333 fsi->period_len = period_len;
334 fsi->byte_offset = 0;
338 static void fsi_stream_pop(struct fsi_priv *fsi)
340 fsi->substream = NULL;
343 fsi->byte_offset = 0;
347 static int fsi_get_fifo_residue(struct fsi_priv *fsi, int is_play)
350 u32 reg = is_play ? DOFF_ST : DIFF_ST;
353 status = fsi_reg_read(fsi, reg);
354 residue = 0x1ff & (status >> 8);
355 residue *= fsi->chan;
360 /************************************************************************
366 ************************************************************************/
367 static void fsi_irq_enable(struct fsi_priv *fsi, int is_play)
369 u32 data = fsi_port_ab_io_bit(fsi, is_play);
370 struct fsi_master *master = fsi_get_master(fsi);
372 fsi_master_mask_set(master, master->core->imsk, data, data);
373 fsi_master_mask_set(master, master->core->iemsk, data, data);
376 static void fsi_irq_disable(struct fsi_priv *fsi, int is_play)
378 u32 data = fsi_port_ab_io_bit(fsi, is_play);
379 struct fsi_master *master = fsi_get_master(fsi);
381 fsi_master_mask_set(master, master->core->imsk, data, 0);
382 fsi_master_mask_set(master, master->core->iemsk, data, 0);
385 static u32 fsi_irq_get_status(struct fsi_master *master)
387 return fsi_master_read(master, master->core->int_st);
390 static void fsi_irq_clear_all_status(struct fsi_master *master)
392 fsi_master_write(master, master->core->int_st, 0);
395 static void fsi_irq_clear_status(struct fsi_priv *fsi)
398 struct fsi_master *master = fsi_get_master(fsi);
400 data |= fsi_port_ab_io_bit(fsi, 0);
401 data |= fsi_port_ab_io_bit(fsi, 1);
403 /* clear interrupt factor */
404 fsi_master_mask_set(master, master->core->int_st, data, 0);
407 /************************************************************************
410 SPDIF master clock function
412 These functions are used later FSI2
413 ************************************************************************/
414 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
416 struct fsi_master *master = fsi_get_master(fsi);
419 if (master->core->ver < 2) {
420 pr_err("fsi: register access err (%s)\n", __func__);
425 fsi_master_mask_set(master, fsi->mst_ctrl, val, val);
427 fsi_master_mask_set(master, fsi->mst_ctrl, val, 0);
430 /************************************************************************
436 ************************************************************************/
437 static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable)
439 u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4);
440 struct fsi_master *master = fsi_get_master(fsi);
443 fsi_master_mask_set(master, CLK_RST, val, val);
445 fsi_master_mask_set(master, CLK_RST, val, 0);
448 static void fsi_fifo_init(struct fsi_priv *fsi,
450 struct snd_soc_dai *dai)
452 struct fsi_master *master = fsi_get_master(fsi);
455 /* get on-chip RAM capacity */
456 shift = fsi_master_read(master, FIFO_SZ);
457 shift >>= fsi_is_port_a(fsi) ? AO_SZ_SHIFT : BO_SZ_SHIFT;
458 shift &= OUT_SZ_MASK;
459 fsi->fifo_max = 256 << shift;
460 dev_dbg(dai->dev, "fifo = %d words\n", fsi->fifo_max);
463 * The maximum number of sample data varies depending
464 * on the number of channels selected for the format.
466 * FIFOs are used in 4-channel units in 3-channel mode
467 * and in 8-channel units in 5- to 7-channel mode
468 * meaning that more FIFOs than the required size of DPRAM
471 * ex) if 256 words of DP-RAM is connected
472 * 1 channel: 256 (256 x 1 = 256)
473 * 2 channels: 128 (128 x 2 = 256)
474 * 3 channels: 64 ( 64 x 3 = 192)
475 * 4 channels: 64 ( 64 x 4 = 256)
476 * 5 channels: 32 ( 32 x 5 = 160)
477 * 6 channels: 32 ( 32 x 6 = 192)
478 * 7 channels: 32 ( 32 x 7 = 224)
479 * 8 channels: 32 ( 32 x 8 = 256)
481 for (i = 1; i < fsi->chan; i <<= 1)
483 dev_dbg(dai->dev, "%d channel %d store\n", fsi->chan, fsi->fifo_max);
485 ctrl = is_play ? DOFF_CTL : DIFF_CTL;
487 /* set interrupt generation factor */
488 fsi_reg_write(fsi, ctrl, IRQ_HALF);
491 fsi_reg_mask_set(fsi, ctrl, FIFO_CLR, FIFO_CLR);
494 static void fsi_soft_all_reset(struct fsi_master *master)
497 fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0);
501 fsi_master_mask_set(master, SOFT_RST, FSISR, 0);
502 fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR);
506 /* playback interrupt */
507 static int fsi_data_push(struct fsi_priv *fsi, int startup)
509 struct snd_pcm_runtime *runtime;
510 struct snd_pcm_substream *substream = NULL;
520 !fsi->substream->runtime)
524 substream = fsi->substream;
525 runtime = substream->runtime;
527 /* FSI FIFO has limit.
528 * So, this driver can not send periods data at a time
530 if (fsi->byte_offset >=
531 fsi->period_len * (fsi->periods + 1)) {
534 fsi->periods = (fsi->periods + 1) % runtime->periods;
536 if (0 == fsi->periods)
537 fsi->byte_offset = 0;
540 /* get 1 channel data width */
541 width = frames_to_bytes(runtime, 1) / fsi->chan;
543 /* get send size for alsa */
544 send = (fsi->buffer_len - fsi->byte_offset) / width;
546 /* get FIFO free size */
547 fifo_free = (fsi->fifo_max * fsi->chan) - fsi_get_fifo_residue(fsi, 1);
550 if (fifo_free < send)
553 start = runtime->dma_area;
554 start += fsi->byte_offset;
558 for (i = 0; i < send; i++)
559 fsi_reg_write(fsi, DODT,
560 ((u32)*((u16 *)start + i) << 8));
563 for (i = 0; i < send; i++)
564 fsi_reg_write(fsi, DODT, *((u32 *)start + i));
570 fsi->byte_offset += send * width;
572 status = fsi_reg_read(fsi, DOFF_ST);
574 struct snd_soc_dai *dai = fsi_get_dai(substream);
576 if (status & ERR_OVER)
577 dev_err(dai->dev, "over run\n");
578 if (status & ERR_UNDER)
579 dev_err(dai->dev, "under run\n");
581 fsi_reg_write(fsi, DOFF_ST, 0);
583 fsi_irq_enable(fsi, 1);
586 snd_pcm_period_elapsed(substream);
591 static int fsi_data_pop(struct fsi_priv *fsi, int startup)
593 struct snd_pcm_runtime *runtime;
594 struct snd_pcm_substream *substream = NULL;
604 !fsi->substream->runtime)
608 substream = fsi->substream;
609 runtime = substream->runtime;
611 /* FSI FIFO has limit.
612 * So, this driver can not send periods data at a time
614 if (fsi->byte_offset >=
615 fsi->period_len * (fsi->periods + 1)) {
618 fsi->periods = (fsi->periods + 1) % runtime->periods;
620 if (0 == fsi->periods)
621 fsi->byte_offset = 0;
624 /* get 1 channel data width */
625 width = frames_to_bytes(runtime, 1) / fsi->chan;
627 /* get free space for alsa */
628 free = (fsi->buffer_len - fsi->byte_offset) / width;
631 fifo_fill = fsi_get_fifo_residue(fsi, 0);
633 if (free < fifo_fill)
636 start = runtime->dma_area;
637 start += fsi->byte_offset;
641 for (i = 0; i < fifo_fill; i++)
642 *((u16 *)start + i) =
643 (u16)(fsi_reg_read(fsi, DIDT) >> 8);
646 for (i = 0; i < fifo_fill; i++)
647 *((u32 *)start + i) = fsi_reg_read(fsi, DIDT);
653 fsi->byte_offset += fifo_fill * width;
655 status = fsi_reg_read(fsi, DIFF_ST);
657 struct snd_soc_dai *dai = fsi_get_dai(substream);
659 if (status & ERR_OVER)
660 dev_err(dai->dev, "over run\n");
661 if (status & ERR_UNDER)
662 dev_err(dai->dev, "under run\n");
664 fsi_reg_write(fsi, DIFF_ST, 0);
666 fsi_irq_enable(fsi, 0);
669 snd_pcm_period_elapsed(substream);
674 static irqreturn_t fsi_interrupt(int irq, void *data)
676 struct fsi_master *master = data;
677 u32 int_st = fsi_irq_get_status(master);
679 /* clear irq status */
680 fsi_master_mask_set(master, SOFT_RST, IR, 0);
681 fsi_master_mask_set(master, SOFT_RST, IR, IR);
683 if (int_st & INT_A_OUT)
684 fsi_data_push(&master->fsia, 0);
685 if (int_st & INT_B_OUT)
686 fsi_data_push(&master->fsib, 0);
687 if (int_st & INT_A_IN)
688 fsi_data_pop(&master->fsia, 0);
689 if (int_st & INT_B_IN)
690 fsi_data_pop(&master->fsib, 0);
692 fsi_irq_clear_all_status(master);
697 /************************************************************************
703 ************************************************************************/
704 static int fsi_dai_startup(struct snd_pcm_substream *substream,
705 struct snd_soc_dai *dai)
707 struct fsi_priv *fsi = fsi_get_priv(substream);
708 u32 flags = fsi_get_info_flags(fsi);
709 struct fsi_master *master = fsi_get_master(fsi);
713 int is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
717 pm_runtime_get_sync(dai->dev);
720 data = is_play ? (1 << 0) : (1 << 4);
721 is_master = fsi_is_master_mode(fsi, is_play);
723 fsi_reg_mask_set(fsi, CKG1, data, data);
725 fsi_reg_mask_set(fsi, CKG1, data, 0);
727 /* clock inversion (CKG2) */
729 if (SH_FSI_LRM_INV & flags)
731 if (SH_FSI_BRM_INV & flags)
733 if (SH_FSI_LRS_INV & flags)
735 if (SH_FSI_BRS_INV & flags)
738 fsi_reg_write(fsi, CKG2, data);
742 reg = is_play ? DO_FMT : DI_FMT;
743 fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags);
745 case SH_FSI_FMT_MONO:
749 case SH_FSI_FMT_MONO_DELAY:
762 fsi->chan = is_play ?
763 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
764 data = CR_TDM | (fsi->chan - 1);
766 case SH_FSI_FMT_TDM_DELAY:
767 fsi->chan = is_play ?
768 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
769 data = CR_TDM_D | (fsi->chan - 1);
771 case SH_FSI_FMT_SPDIF:
772 if (master->core->ver < 2) {
773 dev_err(dai->dev, "This FSI can not use SPDIF\n");
778 fsi_spdif_clk_ctrl(fsi, 1);
779 fsi_reg_mask_set(fsi, OUT_SEL, 0x0010, 0x0010);
782 dev_err(dai->dev, "unknown format.\n");
785 fsi_reg_write(fsi, reg, data);
788 fsi_irq_disable(fsi, is_play);
789 fsi_irq_clear_status(fsi);
792 fsi_fifo_init(fsi, is_play, dai);
797 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
798 struct snd_soc_dai *dai)
800 struct fsi_priv *fsi = fsi_get_priv(substream);
801 int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
803 fsi_irq_disable(fsi, is_play);
804 fsi_clk_ctrl(fsi, 0);
806 pm_runtime_put_sync(dai->dev);
809 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
810 struct snd_soc_dai *dai)
812 struct fsi_priv *fsi = fsi_get_priv(substream);
813 struct snd_pcm_runtime *runtime = substream->runtime;
814 int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
818 case SNDRV_PCM_TRIGGER_START:
819 fsi_stream_push(fsi, substream,
820 frames_to_bytes(runtime, runtime->buffer_size),
821 frames_to_bytes(runtime, runtime->period_size));
822 ret = is_play ? fsi_data_push(fsi, 1) : fsi_data_pop(fsi, 1);
824 case SNDRV_PCM_TRIGGER_STOP:
825 fsi_irq_disable(fsi, is_play);
833 static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
834 struct snd_pcm_hw_params *params,
835 struct snd_soc_dai *dai)
837 struct fsi_priv *fsi = fsi_get_priv(substream);
838 struct fsi_master *master = fsi_get_master(fsi);
839 int (*set_rate)(int is_porta, int rate) = master->info->set_rate;
840 int fsi_ver = master->core->ver;
841 int is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
844 /* if slave mode, set_rate is not needed */
845 if (!fsi_is_master_mode(fsi, is_play))
848 /* it is error if no set_rate */
852 ret = set_rate(fsi_is_port_a(fsi), params_rate(params));
856 switch (ret & SH_FSI_ACKMD_MASK) {
859 case SH_FSI_ACKMD_512:
862 case SH_FSI_ACKMD_256:
865 case SH_FSI_ACKMD_128:
868 case SH_FSI_ACKMD_64:
871 case SH_FSI_ACKMD_32:
873 dev_err(dai->dev, "unsupported ACKMD\n");
879 switch (ret & SH_FSI_BPFMD_MASK) {
882 case SH_FSI_BPFMD_32:
885 case SH_FSI_BPFMD_64:
888 case SH_FSI_BPFMD_128:
891 case SH_FSI_BPFMD_256:
894 case SH_FSI_BPFMD_512:
897 case SH_FSI_BPFMD_16:
899 dev_err(dai->dev, "unsupported ACKMD\n");
905 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
907 fsi_clk_ctrl(fsi, 1);
915 static struct snd_soc_dai_ops fsi_dai_ops = {
916 .startup = fsi_dai_startup,
917 .shutdown = fsi_dai_shutdown,
918 .trigger = fsi_dai_trigger,
919 .hw_params = fsi_dai_hw_params,
922 /************************************************************************
928 ************************************************************************/
929 static struct snd_pcm_hardware fsi_pcm_hardware = {
930 .info = SNDRV_PCM_INFO_INTERLEAVED |
931 SNDRV_PCM_INFO_MMAP |
932 SNDRV_PCM_INFO_MMAP_VALID |
933 SNDRV_PCM_INFO_PAUSE,
940 .buffer_bytes_max = 64 * 1024,
941 .period_bytes_min = 32,
942 .period_bytes_max = 8192,
948 static int fsi_pcm_open(struct snd_pcm_substream *substream)
950 struct snd_pcm_runtime *runtime = substream->runtime;
953 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
955 ret = snd_pcm_hw_constraint_integer(runtime,
956 SNDRV_PCM_HW_PARAM_PERIODS);
961 static int fsi_hw_params(struct snd_pcm_substream *substream,
962 struct snd_pcm_hw_params *hw_params)
964 return snd_pcm_lib_malloc_pages(substream,
965 params_buffer_bytes(hw_params));
968 static int fsi_hw_free(struct snd_pcm_substream *substream)
970 return snd_pcm_lib_free_pages(substream);
973 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
975 struct snd_pcm_runtime *runtime = substream->runtime;
976 struct fsi_priv *fsi = fsi_get_priv(substream);
979 location = (fsi->byte_offset - 1);
983 return bytes_to_frames(runtime, location);
986 static struct snd_pcm_ops fsi_pcm_ops = {
987 .open = fsi_pcm_open,
988 .ioctl = snd_pcm_lib_ioctl,
989 .hw_params = fsi_hw_params,
990 .hw_free = fsi_hw_free,
991 .pointer = fsi_pointer,
994 /************************************************************************
1000 ************************************************************************/
1001 #define PREALLOC_BUFFER (32 * 1024)
1002 #define PREALLOC_BUFFER_MAX (32 * 1024)
1004 static void fsi_pcm_free(struct snd_pcm *pcm)
1006 snd_pcm_lib_preallocate_free_for_all(pcm);
1009 static int fsi_pcm_new(struct snd_card *card,
1010 struct snd_soc_dai *dai,
1011 struct snd_pcm *pcm)
1014 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
1015 * in MMAP mode (i.e. aplay -M)
1017 return snd_pcm_lib_preallocate_pages_for_all(
1019 SNDRV_DMA_TYPE_CONTINUOUS,
1020 snd_dma_continuous_data(GFP_KERNEL),
1021 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1024 /************************************************************************
1030 ************************************************************************/
1031 static struct snd_soc_dai_driver fsi_soc_dai[] = {
1036 .formats = FSI_FMTS,
1042 .formats = FSI_FMTS,
1046 .ops = &fsi_dai_ops,
1052 .formats = FSI_FMTS,
1058 .formats = FSI_FMTS,
1062 .ops = &fsi_dai_ops,
1066 static struct snd_soc_platform_driver fsi_soc_platform = {
1067 .ops = &fsi_pcm_ops,
1068 .pcm_new = fsi_pcm_new,
1069 .pcm_free = fsi_pcm_free,
1072 /************************************************************************
1078 ************************************************************************/
1079 static int fsi_probe(struct platform_device *pdev)
1081 struct fsi_master *master;
1082 const struct platform_device_id *id_entry;
1083 struct resource *res;
1087 id_entry = pdev->id_entry;
1089 dev_err(&pdev->dev, "unknown fsi device\n");
1093 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1094 irq = platform_get_irq(pdev, 0);
1095 if (!res || (int)irq <= 0) {
1096 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1101 master = kzalloc(sizeof(*master), GFP_KERNEL);
1103 dev_err(&pdev->dev, "Could not allocate master\n");
1108 master->base = ioremap_nocache(res->start, resource_size(res));
1109 if (!master->base) {
1111 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1115 /* master setting */
1117 master->info = pdev->dev.platform_data;
1118 master->core = (struct fsi_core *)id_entry->driver_data;
1119 spin_lock_init(&master->lock);
1122 master->fsia.base = master->base;
1123 master->fsia.master = master;
1124 master->fsia.mst_ctrl = A_MST_CTLR;
1127 master->fsib.base = master->base + 0x40;
1128 master->fsib.master = master;
1129 master->fsib.mst_ctrl = B_MST_CTLR;
1131 pm_runtime_enable(&pdev->dev);
1132 pm_runtime_resume(&pdev->dev);
1133 dev_set_drvdata(&pdev->dev, master);
1135 fsi_soft_all_reset(master);
1137 ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED,
1138 id_entry->name, master);
1140 dev_err(&pdev->dev, "irq request err\n");
1144 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
1146 dev_err(&pdev->dev, "cannot snd soc register\n");
1150 return snd_soc_register_dais(&pdev->dev, fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
1153 free_irq(irq, master);
1155 iounmap(master->base);
1156 pm_runtime_disable(&pdev->dev);
1164 static int fsi_remove(struct platform_device *pdev)
1166 struct fsi_master *master;
1168 master = dev_get_drvdata(&pdev->dev);
1170 snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai));
1171 snd_soc_unregister_platform(&pdev->dev);
1173 pm_runtime_disable(&pdev->dev);
1175 free_irq(master->irq, master);
1177 iounmap(master->base);
1183 static int fsi_runtime_nop(struct device *dev)
1185 /* Runtime PM callback shared between ->runtime_suspend()
1186 * and ->runtime_resume(). Simply returns success.
1188 * This driver re-initializes all registers after
1189 * pm_runtime_get_sync() anyway so there is no need
1190 * to save and restore registers here.
1195 static struct dev_pm_ops fsi_pm_ops = {
1196 .runtime_suspend = fsi_runtime_nop,
1197 .runtime_resume = fsi_runtime_nop,
1200 static struct fsi_core fsi1_core = {
1209 static struct fsi_core fsi2_core = {
1213 .int_st = CPU_INT_ST,
1218 static struct platform_device_id fsi_id_table[] = {
1219 { "sh_fsi", (kernel_ulong_t)&fsi1_core },
1220 { "sh_fsi2", (kernel_ulong_t)&fsi2_core },
1223 static struct platform_driver fsi_driver = {
1225 .name = "fsi-pcm-audio",
1229 .remove = fsi_remove,
1230 .id_table = fsi_id_table,
1233 static int __init fsi_mobile_init(void)
1235 return platform_driver_register(&fsi_driver);
1238 static void __exit fsi_mobile_exit(void)
1240 platform_driver_unregister(&fsi_driver);
1242 module_init(fsi_mobile_init);
1243 module_exit(fsi_mobile_exit);
1245 MODULE_LICENSE("GPL");
1246 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
1247 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");